| stats.txt (10535:4ccec5baf82c) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.843655 # Number of seconds simulated 4sim_ticks 2843654861000 # Number of ticks simulated 5final_tick 2843654861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.844427 # Number of seconds simulated 4sim_ticks 2844427140500 # Number of ticks simulated 5final_tick 2844427140500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 157498 # Simulator instruction rate (inst/s) 8host_op_rate 190690 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3581426538 # Simulator tick rate (ticks/s) 10host_mem_usage 613612 # Number of bytes of host memory used 11host_seconds 794.00 # Real time elapsed on the host 12sim_insts 125053138 # Number of instructions simulated 13sim_ops 151407658 # Number of ops (including micro ops) simulated | 7host_inst_rate 150296 # Simulator instruction rate (inst/s) 8host_op_rate 181972 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3416553864 # Simulator tick rate (ticks/s) 10host_mem_usage 612172 # Number of bytes of host memory used 11host_seconds 832.54 # Real time elapsed on the host 12sim_insts 125127935 # Number of instructions simulated 13sim_ops 151499394 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 10304 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.inst 1363068 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.l2cache.prefetcher 10771008 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 534304 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.l2cache.prefetcher 1165248 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.inst 1349820 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.l2cache.prefetcher 10836800 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 503456 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.l2cache.prefetcher 1120064 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 24system.physmem.bytes_read::total 13845276 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 418688 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 26560 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 445248 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 7176128 # Number of bytes written to this memory | 24system.physmem.bytes_read::total 13821980 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 416640 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 27264 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 443904 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 9404288 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory | 29system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 32system.physmem.bytes_written::total 9512208 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory | 31system.physmem.bytes_written::total 9422032 # Number of bytes written to this memory 32system.physmem.num_reads::cpu0.dtb.walker 161 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu0.inst 21823 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.l2cache.prefetcher 168297 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 8372 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.l2cache.prefetcher 18207 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu0.inst 21616 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.l2cache.prefetcher 169325 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.inst 7890 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.l2cache.prefetcher 17501 # Number of read requests responded to by this memory |
| 40system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 39system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 41system.physmem.num_reads::total 216881 # Number of read requests responded to by this memory 42system.physmem.num_writes::writebacks 112127 # Number of write requests responded to by this memory | 40system.physmem.num_reads::total 216517 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 146942 # Number of write requests responded to by this memory |
| 43system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory | 42system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory |
| 45system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 152787 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 3398 # Total read bandwidth from this memory (bytes/s) | 44system.physmem.num_writes::total 151378 # Number of write requests responded to by this memory 45system.physmem.bw_read::cpu0.dtb.walker 3623 # Total read bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) |
| 49system.physmem.bw_read::cpu0.inst 479337 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.l2cache.prefetcher 3787734 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.dtb.walker 338 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 187893 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.l2cache.prefetcher 409771 # Total read bandwidth from this memory (bytes/s) | 47system.physmem.bw_read::cpu0.inst 474549 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.l2cache.prefetcher 3809836 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.inst 176997 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.l2cache.prefetcher 393775 # Total read bandwidth from this memory (bytes/s) |
| 54system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) | 52system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) |
| 55system.physmem.bw_read::total 4868831 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu0.inst 147236 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu1.inst 9340 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::total 156576 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_write::writebacks 2523558 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::total 4859319 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 146476 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 9585 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 156061 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 3306215 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::cpu0.inst 6224 # Write bandwidth from this memory (bytes/s) |
| 61system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) | 59system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) |
| 62system.physmem.bw_write::realview.ide 815266 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 3345064 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2523558 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 3398 # Total bandwidth to/from this memory (bytes/s) | 60system.physmem.bw_write::total 3312453 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 3306215 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.dtb.walker 3623 # Total bandwidth to/from this memory (bytes/s) |
| 66system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) |
| 67system.physmem.bw_total::cpu0.inst 485562 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.l2cache.prefetcher 3787734 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 338 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 187907 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.l2cache.prefetcher 409771 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::realview.ide 815604 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::total 8213896 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.readReqs 216881 # Number of read requests accepted 75system.physmem.writeReqs 152787 # Number of write requests accepted 76system.physmem.readBursts 216881 # Number of DRAM read bursts, including those serviced by the write queue 77system.physmem.writeBursts 152787 # Number of DRAM write bursts, including those merged in the write queue 78system.physmem.bytesReadDRAM 13864960 # Total number of bytes read from DRAM 79system.physmem.bytesReadWrQ 15424 # Total number of bytes read from write queue 80system.physmem.bytesWritten 9526912 # Total number of bytes written to DRAM 81system.physmem.bytesReadSys 13845276 # Total read bytes from the system interface side 82system.physmem.bytesWrittenSys 9512208 # Total written bytes from the system interface side 83system.physmem.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue 84system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one 85system.physmem.neitherReadNorWriteReqs 13516 # Number of requests that are neither read nor write 86system.physmem.perBankRdBursts::0 13445 # Per bank write bursts 87system.physmem.perBankRdBursts::1 13090 # Per bank write bursts 88system.physmem.perBankRdBursts::2 14400 # Per bank write bursts 89system.physmem.perBankRdBursts::3 13760 # Per bank write bursts 90system.physmem.perBankRdBursts::4 15799 # Per bank write bursts 91system.physmem.perBankRdBursts::5 12812 # Per bank write bursts 92system.physmem.perBankRdBursts::6 13576 # Per bank write bursts 93system.physmem.perBankRdBursts::7 13750 # Per bank write bursts 94system.physmem.perBankRdBursts::8 13572 # Per bank write bursts 95system.physmem.perBankRdBursts::9 13600 # Per bank write bursts 96system.physmem.perBankRdBursts::10 13300 # Per bank write bursts 97system.physmem.perBankRdBursts::11 11904 # Per bank write bursts 98system.physmem.perBankRdBursts::12 13370 # Per bank write bursts 99system.physmem.perBankRdBursts::13 13720 # Per bank write bursts 100system.physmem.perBankRdBursts::14 13497 # Per bank write bursts 101system.physmem.perBankRdBursts::15 13045 # Per bank write bursts 102system.physmem.perBankWrBursts::0 9322 # Per bank write bursts 103system.physmem.perBankWrBursts::1 9428 # Per bank write bursts 104system.physmem.perBankWrBursts::2 10143 # Per bank write bursts 105system.physmem.perBankWrBursts::3 9576 # Per bank write bursts 106system.physmem.perBankWrBursts::4 8974 # Per bank write bursts 107system.physmem.perBankWrBursts::5 8900 # Per bank write bursts 108system.physmem.perBankWrBursts::6 9376 # Per bank write bursts 109system.physmem.perBankWrBursts::7 9386 # Per bank write bursts 110system.physmem.perBankWrBursts::8 9384 # Per bank write bursts 111system.physmem.perBankWrBursts::9 9431 # Per bank write bursts 112system.physmem.perBankWrBursts::10 9355 # Per bank write bursts 113system.physmem.perBankWrBursts::11 8834 # Per bank write bursts 114system.physmem.perBankWrBursts::12 9379 # Per bank write bursts 115system.physmem.perBankWrBursts::13 9206 # Per bank write bursts 116system.physmem.perBankWrBursts::14 9289 # Per bank write bursts 117system.physmem.perBankWrBursts::15 8875 # Per bank write bursts | 64system.physmem.bw_total::cpu0.inst 480773 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.l2cache.prefetcher 3809836 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.inst 177011 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.l2cache.prefetcher 393775 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 8171773 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.readReqs 216517 # Number of read requests accepted 72system.physmem.writeReqs 187602 # Number of write requests accepted 73system.physmem.readBursts 216517 # Number of DRAM read bursts, including those serviced by the write queue 74system.physmem.writeBursts 187602 # Number of DRAM write bursts, including those merged in the write queue 75system.physmem.bytesReadDRAM 13846784 # Total number of bytes read from DRAM 76system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue 77system.physmem.bytesWritten 11642944 # Total number of bytes written to DRAM 78system.physmem.bytesReadSys 13821980 # Total read bytes from the system interface side 79system.physmem.bytesWrittenSys 11740368 # Total written bytes from the system interface side 80system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue 81system.physmem.mergedWrBursts 5664 # Number of DRAM write bursts merged with an existing one 82system.physmem.neitherReadNorWriteReqs 13644 # Number of requests that are neither read nor write 83system.physmem.perBankRdBursts::0 13513 # Per bank write bursts 84system.physmem.perBankRdBursts::1 13311 # Per bank write bursts 85system.physmem.perBankRdBursts::2 14548 # Per bank write bursts 86system.physmem.perBankRdBursts::3 14027 # Per bank write bursts 87system.physmem.perBankRdBursts::4 15548 # Per bank write bursts 88system.physmem.perBankRdBursts::5 13123 # Per bank write bursts 89system.physmem.perBankRdBursts::6 13508 # Per bank write bursts 90system.physmem.perBankRdBursts::7 14039 # Per bank write bursts 91system.physmem.perBankRdBursts::8 13183 # Per bank write bursts 92system.physmem.perBankRdBursts::9 13181 # Per bank write bursts 93system.physmem.perBankRdBursts::10 13142 # Per bank write bursts 94system.physmem.perBankRdBursts::11 11743 # Per bank write bursts 95system.physmem.perBankRdBursts::12 13238 # Per bank write bursts 96system.physmem.perBankRdBursts::13 14181 # Per bank write bursts 97system.physmem.perBankRdBursts::14 13272 # Per bank write bursts 98system.physmem.perBankRdBursts::15 12799 # Per bank write bursts 99system.physmem.perBankWrBursts::0 11429 # Per bank write bursts 100system.physmem.perBankWrBursts::1 11725 # Per bank write bursts 101system.physmem.perBankWrBursts::2 12190 # Per bank write bursts 102system.physmem.perBankWrBursts::3 11854 # Per bank write bursts 103system.physmem.perBankWrBursts::4 10909 # Per bank write bursts 104system.physmem.perBankWrBursts::5 11199 # Per bank write bursts 105system.physmem.perBankWrBursts::6 11528 # Per bank write bursts 106system.physmem.perBankWrBursts::7 11643 # Per bank write bursts 107system.physmem.perBankWrBursts::8 11026 # Per bank write bursts 108system.physmem.perBankWrBursts::9 11436 # Per bank write bursts 109system.physmem.perBankWrBursts::10 11468 # Per bank write bursts 110system.physmem.perBankWrBursts::11 11022 # Per bank write bursts 111system.physmem.perBankWrBursts::12 11525 # Per bank write bursts 112system.physmem.perBankWrBursts::13 11398 # Per bank write bursts 113system.physmem.perBankWrBursts::14 10974 # Per bank write bursts 114system.physmem.perBankWrBursts::15 10595 # Per bank write bursts |
| 118system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 119system.physmem.numWrRetry 3 # Number of times write queue was full causing retry 120system.physmem.totGap 2843652584000 # Total gap between requests | 116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 117system.physmem.totGap 2844424796500 # Total gap between requests |
| 121system.physmem.readPktSize::0 0 # Read request sizes (log2) 122system.physmem.readPktSize::1 0 # Read request sizes (log2) 123system.physmem.readPktSize::2 559 # Read request sizes (log2) 124system.physmem.readPktSize::3 28 # Read request sizes (log2) 125system.physmem.readPktSize::4 0 # Read request sizes (log2) 126system.physmem.readPktSize::5 0 # Read request sizes (log2) | 118system.physmem.readPktSize::0 0 # Read request sizes (log2) 119system.physmem.readPktSize::1 0 # Read request sizes (log2) 120system.physmem.readPktSize::2 559 # Read request sizes (log2) 121system.physmem.readPktSize::3 28 # Read request sizes (log2) 122system.physmem.readPktSize::4 0 # Read request sizes (log2) 123system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 127system.physmem.readPktSize::6 216294 # Read request sizes (log2) | 124system.physmem.readPktSize::6 215930 # Read request sizes (log2) |
| 128system.physmem.writePktSize::0 0 # Write request sizes (log2) 129system.physmem.writePktSize::1 0 # Write request sizes (log2) 130system.physmem.writePktSize::2 4436 # Write request sizes (log2) 131system.physmem.writePktSize::3 0 # Write request sizes (log2) 132system.physmem.writePktSize::4 0 # Write request sizes (log2) 133system.physmem.writePktSize::5 0 # Write request sizes (log2) | 125system.physmem.writePktSize::0 0 # Write request sizes (log2) 126system.physmem.writePktSize::1 0 # Write request sizes (log2) 127system.physmem.writePktSize::2 4436 # Write request sizes (log2) 128system.physmem.writePktSize::3 0 # Write request sizes (log2) 129system.physmem.writePktSize::4 0 # Write request sizes (log2) 130system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 134system.physmem.writePktSize::6 148351 # Write request sizes (log2) 135system.physmem.rdQLenPdf::0 79253 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::1 62833 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::2 17902 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::3 12267 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::4 10637 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::5 9321 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::6 8351 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::7 7490 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::10 425 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::11 318 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::12 210 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::13 171 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see | 131system.physmem.writePktSize::6 183166 # Write request sizes (log2) 132system.physmem.rdQLenPdf::0 79055 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::1 63481 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::2 16932 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::3 12216 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::4 10702 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::5 9369 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::6 8301 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::7 7427 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::8 6415 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::9 1133 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::10 442 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::11 303 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::12 206 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::15 92 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see |
| 152system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see | 149system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see |
| 153system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see | 150system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| 155system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 174system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 152system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 171system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 182system.physmem.wrQLenPdf::15 2952 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::17 4345 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::18 5357 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::19 6270 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::20 7461 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::21 8095 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::22 8963 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::23 9736 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::24 10858 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::25 10694 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::26 10594 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::27 10430 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::28 10909 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::29 9025 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::30 8830 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::31 8791 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::32 8216 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::33 582 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::34 381 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::35 300 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::36 204 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::46 132 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see | 179system.physmem.wrQLenPdf::15 3120 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 5952 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 7602 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 8745 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 10117 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 11015 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 12070 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 12267 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 13080 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 12741 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 12428 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 11920 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 12228 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 10042 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 9631 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 9531 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 8901 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::33 927 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::34 714 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::35 577 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::36 448 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::40 238 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::43 184 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::49 132 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see |
| 221system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see | 218system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see |
| 222system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see 231system.physmem.bytesPerActivate::samples 92618 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::mean 252.562223 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::gmean 143.207145 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::stdev 307.469960 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::0-127 46921 50.66% 50.66% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::128-255 18876 20.38% 71.04% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::256-383 6855 7.40% 78.44% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::384-511 3600 3.89% 82.33% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::512-639 3008 3.25% 85.58% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::640-767 2120 2.29% 87.87% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::768-895 1341 1.45% 89.31% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::896-1023 1115 1.20% 90.52% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::1024-1151 8782 9.48% 100.00% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::total 92618 # Bytes accessed per row activation 245system.physmem.rdPerTurnAround::samples 7463 # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::mean 29.028407 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::stdev 529.473600 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::0-2047 7462 99.99% 99.99% # Reads before turning the bus around for writes | 219system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see 228system.physmem.bytesPerActivate::samples 93322 # Bytes accessed per row activation 229system.physmem.bytesPerActivate::mean 273.137395 # Bytes accessed per row activation 230system.physmem.bytesPerActivate::gmean 151.655882 # Bytes accessed per row activation 231system.physmem.bytesPerActivate::stdev 326.256113 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::0-127 45588 48.85% 48.85% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::128-255 18736 20.08% 68.93% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::256-383 6915 7.41% 76.34% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::384-511 3558 3.81% 80.15% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::512-639 3108 3.33% 83.48% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::640-767 2062 2.21% 85.69% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::768-895 1352 1.45% 87.14% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::896-1023 1057 1.13% 88.27% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::1024-1151 10946 11.73% 100.00% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::total 93322 # Bytes accessed per row activation 242system.physmem.rdPerTurnAround::samples 7762 # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::mean 27.873744 # Reads before turning the bus around for writes 244system.physmem.rdPerTurnAround::stdev 521.384620 # Reads before turning the bus around for writes 245system.physmem.rdPerTurnAround::0-2047 7761 99.99% 99.99% # Reads before turning the bus around for writes |
| 249system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes | 246system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 250system.physmem.rdPerTurnAround::total 7463 # Reads before turning the bus around for writes 251system.physmem.wrPerTurnAround::samples 7463 # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::mean 19.946134 # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::gmean 18.603737 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::stdev 11.129560 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::16-19 6171 82.69% 82.69% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::20-23 489 6.55% 89.24% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::24-27 84 1.13% 90.37% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::28-31 205 2.75% 93.11% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::32-35 200 2.68% 95.79% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::36-39 17 0.23% 96.02% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::40-43 17 0.23% 96.25% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::44-47 12 0.16% 96.41% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::48-51 25 0.33% 96.74% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::52-55 6 0.08% 96.82% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::56-59 6 0.08% 96.90% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::60-63 3 0.04% 96.94% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::64-67 165 2.21% 99.16% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::68-71 7 0.09% 99.25% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::72-75 6 0.08% 99.33% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::80-83 18 0.24% 99.57% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::84-87 1 0.01% 99.58% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::96-99 7 0.09% 99.71% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::100-103 1 0.01% 99.72% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::112-115 3 0.04% 99.79% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::124-127 1 0.01% 99.81% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::128-131 8 0.11% 99.92% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::136-139 1 0.01% 99.95% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::140-143 3 0.04% 99.99% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::total 7463 # Writes before turning the bus around for reads 287system.physmem.totQLat 7683149500 # Total ticks spent queuing 288system.physmem.totMemAccLat 11745149500 # Total ticks spent from burst creation until serviced by the DRAM 289system.physmem.totBusLat 1083200000 # Total ticks spent in databus transfers 290system.physmem.avgQLat 35465.05 # Average queueing delay per DRAM burst | 247system.physmem.rdPerTurnAround::total 7762 # Reads before turning the bus around for writes 248system.physmem.wrPerTurnAround::samples 7762 # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::mean 23.437387 # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::gmean 19.920909 # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::stdev 21.626862 # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::16-19 6141 79.12% 79.12% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::20-23 490 6.31% 85.43% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::24-27 77 0.99% 86.42% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::28-31 208 2.68% 89.10% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::32-35 144 1.86% 90.96% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::36-39 54 0.70% 91.65% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::40-43 53 0.68% 92.33% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::44-47 34 0.44% 92.77% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::48-51 115 1.48% 94.25% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::52-55 15 0.19% 94.45% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::56-59 16 0.21% 94.65% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::60-63 14 0.18% 94.83% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::64-67 31 0.40% 95.23% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::68-71 17 0.22% 95.45% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::72-75 9 0.12% 95.57% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::76-79 24 0.31% 95.88% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::80-83 61 0.79% 96.66% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::84-87 9 0.12% 96.78% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::88-91 4 0.05% 96.83% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::92-95 7 0.09% 96.92% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::96-99 74 0.95% 97.87% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::100-103 2 0.03% 97.90% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::104-107 12 0.15% 98.05% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::108-111 8 0.10% 98.16% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::112-115 21 0.27% 98.43% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::116-119 7 0.09% 98.52% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::120-123 12 0.15% 98.67% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::124-127 7 0.09% 98.76% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::128-131 28 0.36% 99.12% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::132-135 9 0.12% 99.24% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::136-139 3 0.04% 99.28% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::140-143 2 0.03% 99.30% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::144-147 9 0.12% 99.42% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::148-151 8 0.10% 99.52% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::156-159 3 0.04% 99.57% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::160-163 7 0.09% 99.67% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::164-167 3 0.04% 99.70% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::168-171 1 0.01% 99.72% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::176-179 5 0.06% 99.78% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::180-183 3 0.04% 99.82% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::184-187 3 0.04% 99.86% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::188-191 3 0.04% 99.90% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::200-203 1 0.01% 99.91% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::208-211 2 0.03% 99.94% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::220-223 3 0.04% 99.97% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::total 7762 # Writes before turning the bus around for reads 301system.physmem.totQLat 7644398000 # Total ticks spent queuing 302system.physmem.totMemAccLat 11701073000 # Total ticks spent from burst creation until serviced by the DRAM 303system.physmem.totBusLat 1081780000 # Total ticks spent in databus transfers 304system.physmem.avgQLat 35332.50 # Average queueing delay per DRAM burst |
| 291system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 305system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 292system.physmem.avgMemAccLat 54215.05 # Average memory access latency per DRAM burst 293system.physmem.avgRdBW 4.88 # Average DRAM read bandwidth in MiByte/s 294system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s 295system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s 296system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s | 306system.physmem.avgMemAccLat 54082.50 # Average memory access latency per DRAM burst 307system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s 308system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s 309system.physmem.avgRdBWSys 4.86 # Average system read bandwidth in MiByte/s 310system.physmem.avgWrBWSys 4.13 # Average system write bandwidth in MiByte/s |
| 297system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 311system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 298system.physmem.busUtil 0.06 # Data bus utilization in percentage | 312system.physmem.busUtil 0.07 # Data bus utilization in percentage |
| 299system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 300system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 313system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 314system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 301system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing 302system.physmem.avgWrQLen 26.48 # Average write queue length when enqueuing 303system.physmem.readRowHits 183194 # Number of row buffer hits during reads 304system.physmem.writeRowHits 89685 # Number of row buffer hits during writes 305system.physmem.readRowHitRate 84.56 # Row buffer hit rate for reads 306system.physmem.writeRowHitRate 60.24 # Row buffer hit rate for writes 307system.physmem.avgGap 7692449.94 # Average gap between requests 308system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined 309system.physmem.memoryStateTime::IDLE 2709796310750 # Time in different power states 310system.physmem.memoryStateTime::REF 94955640000 # Time in different power states | 315system.physmem.avgRdQLen 1.94 # Average read queue length when enqueuing 316system.physmem.avgWrQLen 21.48 # Average write queue length when enqueuing 317system.physmem.readRowHits 183280 # Number of row buffer hits during reads 318system.physmem.writeRowHits 121675 # Number of row buffer hits during writes 319system.physmem.readRowHitRate 84.71 # Row buffer hit rate for reads 320system.physmem.writeRowHitRate 66.88 # Row buffer hit rate for writes 321system.physmem.avgGap 7038582.19 # Average gap between requests 322system.physmem.pageHitRate 76.57 # Row buffer hit rate, read and write combined 323system.physmem.memoryStateTime::IDLE 2710525028500 # Time in different power states 324system.physmem.memoryStateTime::REF 94981640000 # Time in different power states |
| 311system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 325system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 312system.physmem.memoryStateTime::ACT 38900516750 # Time in different power states | 326system.physmem.memoryStateTime::ACT 38919724000 # Time in different power states |
| 313system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 327system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 314system.physmem.actEnergy::0 358956360 # Energy for activate commands per rank (pJ) 315system.physmem.actEnergy::1 341235720 # Energy for activate commands per rank (pJ) 316system.physmem.preEnergy::0 195859125 # Energy for precharge commands per rank (pJ) 317system.physmem.preEnergy::1 186190125 # Energy for precharge commands per rank (pJ) 318system.physmem.readEnergy::0 862929600 # Energy for read commands per rank (pJ) 319system.physmem.readEnergy::1 826854600 # Energy for read commands per rank (pJ) 320system.physmem.writeEnergy::0 486680400 # Energy for write commands per rank (pJ) 321system.physmem.writeEnergy::1 477919440 # Energy for write commands per rank (pJ) 322system.physmem.refreshEnergy::0 185733231840 # Energy for refresh commands per rank (pJ) 323system.physmem.refreshEnergy::1 185733231840 # Energy for refresh commands per rank (pJ) 324system.physmem.actBackEnergy::0 81937929780 # Energy for active background per rank (pJ) 325system.physmem.actBackEnergy::1 81435296655 # Energy for active background per rank (pJ) 326system.physmem.preBackEnergy::0 1634313275250 # Energy for precharge background per rank (pJ) 327system.physmem.preBackEnergy::1 1634754181500 # Energy for precharge background per rank (pJ) 328system.physmem.totalEnergy::0 1903888862355 # Total energy per rank (pJ) 329system.physmem.totalEnergy::1 1903754909880 # Total energy per rank (pJ) 330system.physmem.averagePower::0 669.523453 # Core power per rank (mW) 331system.physmem.averagePower::1 669.476347 # Core power per rank (mW) | 328system.physmem.actEnergy::0 365533560 # Energy for activate commands per rank (pJ) 329system.physmem.actEnergy::1 339980760 # Energy for activate commands per rank (pJ) 330system.physmem.preEnergy::0 199447875 # Energy for precharge commands per rank (pJ) 331system.physmem.preEnergy::1 185505375 # Energy for precharge commands per rank (pJ) 332system.physmem.readEnergy::0 870612600 # Energy for read commands per rank (pJ) 333system.physmem.readEnergy::1 816964200 # Energy for read commands per rank (pJ) 334system.physmem.writeEnergy::0 599250960 # Energy for write commands per rank (pJ) 335system.physmem.writeEnergy::1 579597120 # Energy for write commands per rank (pJ) 336system.physmem.refreshEnergy::0 185784087840 # Energy for refresh commands per rank (pJ) 337system.physmem.refreshEnergy::1 185784087840 # Energy for refresh commands per rank (pJ) 338system.physmem.actBackEnergy::0 82151193285 # Energy for active background per rank (pJ) 339system.physmem.actBackEnergy::1 81119552850 # Energy for active background per rank (pJ) 340system.physmem.preBackEnergy::0 1634593377000 # Energy for precharge background per rank (pJ) 341system.physmem.preBackEnergy::1 1635498324750 # Energy for precharge background per rank (pJ) 342system.physmem.totalEnergy::0 1904563503120 # Total energy per rank (pJ) 343system.physmem.totalEnergy::1 1904324012895 # Total energy per rank (pJ) 344system.physmem.averagePower::0 669.577359 # Core power per rank (mW) 345system.physmem.averagePower::1 669.493163 # Core power per rank (mW) |
| 332system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 333system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 334system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 335system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 336system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 337system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 338system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 339system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory --- 8 unchanged lines hidden (view full) --- 348system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 349system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) 350system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 351system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 352system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 353system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 354system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 355system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 346system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory --- 8 unchanged lines hidden (view full) --- 362system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) 364system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 365system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 366system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 367system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 368system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 369system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 356system.cpu0.branchPred.lookups 34892527 # Number of BP lookups 357system.cpu0.branchPred.condPredicted 17126488 # Number of conditional branches predicted 358system.cpu0.branchPred.condIncorrect 1674515 # Number of conditional branches incorrect 359system.cpu0.branchPred.BTBLookups 20008950 # Number of BTB lookups 360system.cpu0.branchPred.BTBHits 14462185 # Number of BTB hits | 370system.cpu0.branchPred.lookups 35736686 # Number of BP lookups 371system.cpu0.branchPred.condPredicted 17706973 # Number of conditional branches predicted 372system.cpu0.branchPred.condIncorrect 1707657 # Number of conditional branches incorrect 373system.cpu0.branchPred.BTBLookups 20554340 # Number of BTB lookups 374system.cpu0.branchPred.BTBHits 14845557 # Number of BTB hits |
| 361system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 375system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 362system.cpu0.branchPred.BTBHitPct 72.278580 # BTB Hit Percentage 363system.cpu0.branchPred.usedRAS 10813099 # Number of times the RAS was used to get a target. 364system.cpu0.branchPred.RASInCorrect 822816 # Number of incorrect RAS predictions. | 376system.cpu0.branchPred.BTBHitPct 72.225900 # BTB Hit Percentage 377system.cpu0.branchPred.usedRAS 10924417 # Number of times the RAS was used to get a target. 378system.cpu0.branchPred.RASInCorrect 815226 # Number of incorrect RAS predictions. |
| 365system.cpu_clk_domain.clock 500 # Clock period in ticks 366system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 367system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 368system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 369system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 370system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 371system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 372system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 381system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 382system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 383system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 384system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 385system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 386system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 387system.cpu0.dtb.inst_hits 0 # ITB inst hits 388system.cpu0.dtb.inst_misses 0 # ITB inst misses | 379system.cpu_clk_domain.clock 500 # Clock period in ticks 380system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 381system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 382system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 383system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 384system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 385system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 386system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 395system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 396system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 397system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 398system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 399system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 400system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 401system.cpu0.dtb.inst_hits 0 # ITB inst hits 402system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 389system.cpu0.dtb.read_hits 23969265 # DTB read hits 390system.cpu0.dtb.read_misses 62663 # DTB read misses 391system.cpu0.dtb.write_hits 17948332 # DTB write hits 392system.cpu0.dtb.write_misses 6711 # DTB write misses | 403system.cpu0.dtb.read_hits 24607000 # DTB read hits 404system.cpu0.dtb.read_misses 66402 # DTB read misses 405system.cpu0.dtb.write_hits 18455953 # DTB write hits 406system.cpu0.dtb.write_misses 6655 # DTB write misses |
| 393system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 394system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 395system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 396system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 407system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 408system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 409system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 410system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 397system.cpu0.dtb.flush_entries 3475 # Number of entries that have been flushed from TLB 398system.cpu0.dtb.align_faults 1396 # Number of TLB faults due to alignment restrictions 399system.cpu0.dtb.prefetch_faults 1982 # Number of TLB faults due to prefetch | 411system.cpu0.dtb.flush_entries 3808 # Number of entries that have been flushed from TLB 412system.cpu0.dtb.align_faults 1234 # Number of TLB faults due to alignment restrictions 413system.cpu0.dtb.prefetch_faults 2108 # Number of TLB faults due to prefetch |
| 400system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 414system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 401system.cpu0.dtb.perms_faults 568 # Number of TLB faults due to permissions restrictions 402system.cpu0.dtb.read_accesses 24031928 # DTB read accesses 403system.cpu0.dtb.write_accesses 17955043 # DTB write accesses | 415system.cpu0.dtb.perms_faults 615 # Number of TLB faults due to permissions restrictions 416system.cpu0.dtb.read_accesses 24673402 # DTB read accesses 417system.cpu0.dtb.write_accesses 18462608 # DTB write accesses |
| 404system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 418system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 405system.cpu0.dtb.hits 41917597 # DTB hits 406system.cpu0.dtb.misses 69374 # DTB misses 407system.cpu0.dtb.accesses 41986971 # DTB accesses | 419system.cpu0.dtb.hits 43062953 # DTB hits 420system.cpu0.dtb.misses 73057 # DTB misses 421system.cpu0.dtb.accesses 43136010 # DTB accesses |
| 408system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 409system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 410system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 411system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 412system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 413system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 414system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 415system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 421system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 422system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 423system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 424system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 425system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 426system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 427system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 428system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 422system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 423system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 424system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 425system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 426system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 427system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 428system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 429system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 435system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 436system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 437system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 438system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 439system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 440system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 441system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 442system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 429system.cpu0.itb.inst_hits 70358748 # ITB inst hits 430system.cpu0.itb.inst_misses 3854 # ITB inst misses | 443system.cpu0.itb.inst_hits 71661808 # ITB inst hits 444system.cpu0.itb.inst_misses 4142 # ITB inst misses |
| 431system.cpu0.itb.read_hits 0 # DTB read hits 432system.cpu0.itb.read_misses 0 # DTB read misses 433system.cpu0.itb.write_hits 0 # DTB write hits 434system.cpu0.itb.write_misses 0 # DTB write misses 435system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 436system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 437system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 438system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 445system.cpu0.itb.read_hits 0 # DTB read hits 446system.cpu0.itb.read_misses 0 # DTB read misses 447system.cpu0.itb.write_hits 0 # DTB write hits 448system.cpu0.itb.write_misses 0 # DTB write misses 449system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 450system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 451system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 452system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 439system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB | 453system.cpu0.itb.flush_entries 2456 # Number of entries that have been flushed from TLB |
| 440system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 441system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 442system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 454system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 455system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 456system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 443system.cpu0.itb.perms_faults 7388 # Number of TLB faults due to permissions restrictions | 457system.cpu0.itb.perms_faults 8241 # Number of TLB faults due to permissions restrictions |
| 444system.cpu0.itb.read_accesses 0 # DTB read accesses 445system.cpu0.itb.write_accesses 0 # DTB write accesses | 458system.cpu0.itb.read_accesses 0 # DTB read accesses 459system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 446system.cpu0.itb.inst_accesses 70362602 # ITB inst accesses 447system.cpu0.itb.hits 70358748 # DTB hits 448system.cpu0.itb.misses 3854 # DTB misses 449system.cpu0.itb.accesses 70362602 # DTB accesses 450system.cpu0.numCycles 229119066 # number of cpu cycles simulated | 460system.cpu0.itb.inst_accesses 71665950 # ITB inst accesses 461system.cpu0.itb.hits 71661808 # DTB hits 462system.cpu0.itb.misses 4142 # DTB misses 463system.cpu0.itb.accesses 71665950 # DTB accesses 464system.cpu0.numCycles 235973632 # number of cpu cycles simulated |
| 451system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 452system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 465system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 466system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 453system.cpu0.committedInsts 109189984 # Number of instructions committed 454system.cpu0.committedOps 132016369 # Number of ops (including micro ops) committed 455system.cpu0.discardedOps 8791665 # Number of ops (including micro ops) which were discarded before commit 456system.cpu0.numFetchSuspends 1828 # Number of times Execute suspended instruction fetching 457system.cpu0.quiesceCycles 5458204948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 458system.cpu0.cpi 2.098352 # CPI: cycles per instruction 459system.cpu0.ipc 0.476564 # IPC: instructions per cycle | 467system.cpu0.committedInsts 111703770 # Number of instructions committed 468system.cpu0.committedOps 135097839 # Number of ops (including micro ops) committed 469system.cpu0.discardedOps 8562554 # Number of ops (including micro ops) which were discarded before commit 470system.cpu0.numFetchSuspends 1855 # Number of times Execute suspended instruction fetching 471system.cpu0.quiesceCycles 5452894525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 472system.cpu0.cpi 2.112495 # CPI: cycles per instruction 473system.cpu0.ipc 0.473374 # IPC: instructions per cycle |
| 460system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 474system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 461system.cpu0.kern.inst.quiesce 1830 # number of quiesce instructions executed 462system.cpu0.tickCycles 193229301 # Number of cycles that the object actually ticked 463system.cpu0.idleCycles 35889765 # Total number of cycles that the object has spent stopped 464system.cpu0.dcache.tags.replacements 714801 # number of replacements 465system.cpu0.dcache.tags.tagsinuse 493.827802 # Cycle average of tags in use 466system.cpu0.dcache.tags.total_refs 40473769 # Total number of references to valid blocks. 467system.cpu0.dcache.tags.sampled_refs 715313 # Sample count of references to valid blocks. 468system.cpu0.dcache.tags.avg_refs 56.581901 # Average number of references to valid blocks. 469system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit. 470system.cpu0.dcache.tags.occ_blocks::cpu0.inst 493.827802 # Average occupied blocks per requestor 471system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.964507 # Average percentage of cache occupancy 472system.cpu0.dcache.tags.occ_percent::total 0.964507 # Average percentage of cache occupancy | 475system.cpu0.kern.inst.quiesce 1855 # number of quiesce instructions executed 476system.cpu0.tickCycles 199544848 # Number of cycles that the object actually ticked 477system.cpu0.idleCycles 36428784 # Total number of cycles that the object has spent stopped 478system.cpu0.dcache.tags.replacements 751860 # number of replacements 479system.cpu0.dcache.tags.tagsinuse 494.262864 # Cycle average of tags in use 480system.cpu0.dcache.tags.total_refs 41566353 # Total number of references to valid blocks. 481system.cpu0.dcache.tags.sampled_refs 752372 # Sample count of references to valid blocks. 482system.cpu0.dcache.tags.avg_refs 55.247076 # Average number of references to valid blocks. 483system.cpu0.dcache.tags.warmup_cycle 306713000 # Cycle when the warmup percentage was hit. 484system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.262864 # Average occupied blocks per requestor 485system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965357 # Average percentage of cache occupancy 486system.cpu0.dcache.tags.occ_percent::total 0.965357 # Average percentage of cache occupancy |
| 473system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 474system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id | 487system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 488system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id |
| 475system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 476system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id | 489system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id 490system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id |
| 477system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 491system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 478system.cpu0.dcache.tags.tag_accesses 83782876 # Number of tag accesses 479system.cpu0.dcache.tags.data_accesses 83782876 # Number of data accesses 480system.cpu0.dcache.ReadReq_hits::cpu0.inst 22802755 # number of ReadReq hits 481system.cpu0.dcache.ReadReq_hits::total 22802755 # number of ReadReq hits 482system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862558 # number of WriteReq hits 483system.cpu0.dcache.WriteReq_hits::total 16862558 # number of WriteReq hits 484system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381551 # number of LoadLockedReq hits 485system.cpu0.dcache.LoadLockedReq_hits::total 381551 # number of LoadLockedReq hits 486system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362630 # number of StoreCondReq hits 487system.cpu0.dcache.StoreCondReq_hits::total 362630 # number of StoreCondReq hits 488system.cpu0.dcache.demand_hits::cpu0.inst 39665313 # number of demand (read+write) hits 489system.cpu0.dcache.demand_hits::total 39665313 # number of demand (read+write) hits 490system.cpu0.dcache.overall_hits::cpu0.inst 39665313 # number of overall hits 491system.cpu0.dcache.overall_hits::total 39665313 # number of overall hits 492system.cpu0.dcache.ReadReq_misses::cpu0.inst 537301 # number of ReadReq misses 493system.cpu0.dcache.ReadReq_misses::total 537301 # number of ReadReq misses 494system.cpu0.dcache.WriteReq_misses::cpu0.inst 532764 # number of WriteReq misses 495system.cpu0.dcache.WriteReq_misses::total 532764 # number of WriteReq misses 496system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6412 # number of LoadLockedReq misses 497system.cpu0.dcache.LoadLockedReq_misses::total 6412 # number of LoadLockedReq misses 498system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20204 # number of StoreCondReq misses 499system.cpu0.dcache.StoreCondReq_misses::total 20204 # number of StoreCondReq misses 500system.cpu0.dcache.demand_misses::cpu0.inst 1070065 # number of demand (read+write) misses 501system.cpu0.dcache.demand_misses::total 1070065 # number of demand (read+write) misses 502system.cpu0.dcache.overall_misses::cpu0.inst 1070065 # number of overall misses 503system.cpu0.dcache.overall_misses::total 1070065 # number of overall misses 504system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609674711 # number of ReadReq miss cycles 505system.cpu0.dcache.ReadReq_miss_latency::total 6609674711 # number of ReadReq miss cycles 506system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8019150247 # number of WriteReq miss cycles 507system.cpu0.dcache.WriteReq_miss_latency::total 8019150247 # number of WriteReq miss cycles 508system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 105707749 # number of LoadLockedReq miss cycles 509system.cpu0.dcache.LoadLockedReq_miss_latency::total 105707749 # number of LoadLockedReq miss cycles 510system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 437634051 # number of StoreCondReq miss cycles 511system.cpu0.dcache.StoreCondReq_miss_latency::total 437634051 # number of StoreCondReq miss cycles 512system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles 513system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles 514system.cpu0.dcache.demand_miss_latency::cpu0.inst 14628824958 # number of demand (read+write) miss cycles 515system.cpu0.dcache.demand_miss_latency::total 14628824958 # number of demand (read+write) miss cycles 516system.cpu0.dcache.overall_miss_latency::cpu0.inst 14628824958 # number of overall miss cycles 517system.cpu0.dcache.overall_miss_latency::total 14628824958 # number of overall miss cycles 518system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23340056 # number of ReadReq accesses(hits+misses) 519system.cpu0.dcache.ReadReq_accesses::total 23340056 # number of ReadReq accesses(hits+misses) 520system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395322 # number of WriteReq accesses(hits+misses) 521system.cpu0.dcache.WriteReq_accesses::total 17395322 # number of WriteReq accesses(hits+misses) 522system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387963 # number of LoadLockedReq accesses(hits+misses) 523system.cpu0.dcache.LoadLockedReq_accesses::total 387963 # number of LoadLockedReq accesses(hits+misses) 524system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382834 # number of StoreCondReq accesses(hits+misses) 525system.cpu0.dcache.StoreCondReq_accesses::total 382834 # number of StoreCondReq accesses(hits+misses) 526system.cpu0.dcache.demand_accesses::cpu0.inst 40735378 # number of demand (read+write) accesses 527system.cpu0.dcache.demand_accesses::total 40735378 # number of demand (read+write) accesses 528system.cpu0.dcache.overall_accesses::cpu0.inst 40735378 # number of overall (read+write) accesses 529system.cpu0.dcache.overall_accesses::total 40735378 # number of overall (read+write) accesses 530system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023021 # miss rate for ReadReq accesses 531system.cpu0.dcache.ReadReq_miss_rate::total 0.023021 # miss rate for ReadReq accesses 532system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030627 # miss rate for WriteReq accesses 533system.cpu0.dcache.WriteReq_miss_rate::total 0.030627 # miss rate for WriteReq accesses 534system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016527 # miss rate for LoadLockedReq accesses 535system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016527 # miss rate for LoadLockedReq accesses 536system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052775 # miss rate for StoreCondReq accesses 537system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052775 # miss rate for StoreCondReq accesses 538system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026269 # miss rate for demand accesses 539system.cpu0.dcache.demand_miss_rate::total 0.026269 # miss rate for demand accesses 540system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026269 # miss rate for overall accesses 541system.cpu0.dcache.overall_miss_rate::total 0.026269 # miss rate for overall accesses 542system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12301.623691 # average ReadReq miss latency 543system.cpu0.dcache.ReadReq_avg_miss_latency::total 12301.623691 # average ReadReq miss latency 544system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15051.974696 # average WriteReq miss latency 545system.cpu0.dcache.WriteReq_avg_miss_latency::total 15051.974696 # average WriteReq miss latency 546system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16485.924672 # average LoadLockedReq miss latency 547system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16485.924672 # average LoadLockedReq miss latency 548system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21660.762770 # average StoreCondReq miss latency 549system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21660.762770 # average StoreCondReq miss latency | 492system.cpu0.dcache.tags.tag_accesses 86104149 # Number of tag accesses 493system.cpu0.dcache.tags.data_accesses 86104149 # Number of data accesses 494system.cpu0.dcache.ReadReq_hits::cpu0.inst 23403701 # number of ReadReq hits 495system.cpu0.dcache.ReadReq_hits::total 23403701 # number of ReadReq hits 496system.cpu0.dcache.WriteReq_hits::cpu0.inst 17336391 # number of WriteReq hits 497system.cpu0.dcache.WriteReq_hits::total 17336391 # number of WriteReq hits 498system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 390425 # number of LoadLockedReq hits 499system.cpu0.dcache.LoadLockedReq_hits::total 390425 # number of LoadLockedReq hits 500system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 371566 # number of StoreCondReq hits 501system.cpu0.dcache.StoreCondReq_hits::total 371566 # number of StoreCondReq hits 502system.cpu0.dcache.demand_hits::cpu0.inst 40740092 # number of demand (read+write) hits 503system.cpu0.dcache.demand_hits::total 40740092 # number of demand (read+write) hits 504system.cpu0.dcache.overall_hits::cpu0.inst 40740092 # number of overall hits 505system.cpu0.dcache.overall_hits::total 40740092 # number of overall hits 506system.cpu0.dcache.ReadReq_misses::cpu0.inst 564897 # number of ReadReq misses 507system.cpu0.dcache.ReadReq_misses::total 564897 # number of ReadReq misses 508system.cpu0.dcache.WriteReq_misses::cpu0.inst 554409 # number of WriteReq misses 509system.cpu0.dcache.WriteReq_misses::total 554409 # number of WriteReq misses 510system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6644 # number of LoadLockedReq misses 511system.cpu0.dcache.LoadLockedReq_misses::total 6644 # number of LoadLockedReq misses 512system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20340 # number of StoreCondReq misses 513system.cpu0.dcache.StoreCondReq_misses::total 20340 # number of StoreCondReq misses 514system.cpu0.dcache.demand_misses::cpu0.inst 1119306 # number of demand (read+write) misses 515system.cpu0.dcache.demand_misses::total 1119306 # number of demand (read+write) misses 516system.cpu0.dcache.overall_misses::cpu0.inst 1119306 # number of overall misses 517system.cpu0.dcache.overall_misses::total 1119306 # number of overall misses 518system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6887885459 # number of ReadReq miss cycles 519system.cpu0.dcache.ReadReq_miss_latency::total 6887885459 # number of ReadReq miss cycles 520system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8219762503 # number of WriteReq miss cycles 521system.cpu0.dcache.WriteReq_miss_latency::total 8219762503 # number of WriteReq miss cycles 522system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 108110000 # number of LoadLockedReq miss cycles 523system.cpu0.dcache.LoadLockedReq_miss_latency::total 108110000 # number of LoadLockedReq miss cycles 524system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 440070983 # number of StoreCondReq miss cycles 525system.cpu0.dcache.StoreCondReq_miss_latency::total 440070983 # number of StoreCondReq miss cycles 526system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq miss cycles 527system.cpu0.dcache.StoreCondFailReq_miss_latency::total 121000 # number of StoreCondFailReq miss cycles 528system.cpu0.dcache.demand_miss_latency::cpu0.inst 15107647962 # number of demand (read+write) miss cycles 529system.cpu0.dcache.demand_miss_latency::total 15107647962 # number of demand (read+write) miss cycles 530system.cpu0.dcache.overall_miss_latency::cpu0.inst 15107647962 # number of overall miss cycles 531system.cpu0.dcache.overall_miss_latency::total 15107647962 # number of overall miss cycles 532system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23968598 # number of ReadReq accesses(hits+misses) 533system.cpu0.dcache.ReadReq_accesses::total 23968598 # number of ReadReq accesses(hits+misses) 534system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17890800 # number of WriteReq accesses(hits+misses) 535system.cpu0.dcache.WriteReq_accesses::total 17890800 # number of WriteReq accesses(hits+misses) 536system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 397069 # number of LoadLockedReq accesses(hits+misses) 537system.cpu0.dcache.LoadLockedReq_accesses::total 397069 # number of LoadLockedReq accesses(hits+misses) 538system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 391906 # number of StoreCondReq accesses(hits+misses) 539system.cpu0.dcache.StoreCondReq_accesses::total 391906 # number of StoreCondReq accesses(hits+misses) 540system.cpu0.dcache.demand_accesses::cpu0.inst 41859398 # number of demand (read+write) accesses 541system.cpu0.dcache.demand_accesses::total 41859398 # number of demand (read+write) accesses 542system.cpu0.dcache.overall_accesses::cpu0.inst 41859398 # number of overall (read+write) accesses 543system.cpu0.dcache.overall_accesses::total 41859398 # number of overall (read+write) accesses 544system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023568 # miss rate for ReadReq accesses 545system.cpu0.dcache.ReadReq_miss_rate::total 0.023568 # miss rate for ReadReq accesses 546system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030988 # miss rate for WriteReq accesses 547system.cpu0.dcache.WriteReq_miss_rate::total 0.030988 # miss rate for WriteReq accesses 548system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016733 # miss rate for LoadLockedReq accesses 549system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016733 # miss rate for LoadLockedReq accesses 550system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051900 # miss rate for StoreCondReq accesses 551system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051900 # miss rate for StoreCondReq accesses 552system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026740 # miss rate for demand accesses 553system.cpu0.dcache.demand_miss_rate::total 0.026740 # miss rate for demand accesses 554system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026740 # miss rate for overall accesses 555system.cpu0.dcache.overall_miss_rate::total 0.026740 # miss rate for overall accesses 556system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12193.170541 # average ReadReq miss latency 557system.cpu0.dcache.ReadReq_avg_miss_latency::total 12193.170541 # average ReadReq miss latency 558system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 14826.170757 # average WriteReq miss latency 559system.cpu0.dcache.WriteReq_avg_miss_latency::total 14826.170757 # average WriteReq miss latency 560system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16271.824202 # average LoadLockedReq miss latency 561system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.824202 # average LoadLockedReq miss latency 562system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21635.741544 # average StoreCondReq miss latency 563system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21635.741544 # average StoreCondReq miss latency |
| 550system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 551system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 564system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 565system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 552system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency 553system.cpu0.dcache.demand_avg_miss_latency::total 13670.968547 # average overall miss latency 554system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency 555system.cpu0.dcache.overall_avg_miss_latency::total 13670.968547 # average overall miss latency | 566system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency 567system.cpu0.dcache.demand_avg_miss_latency::total 13497.334922 # average overall miss latency 568system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency 569system.cpu0.dcache.overall_avg_miss_latency::total 13497.334922 # average overall miss latency |
| 556system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 557system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 558system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 559system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 560system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 561system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 562system.cpu0.dcache.fast_writes 0 # number of fast writes performed 563system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 570system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 571system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 572system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 573system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 574system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 575system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 576system.cpu0.dcache.fast_writes 0 # number of fast writes performed 577system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 564system.cpu0.dcache.writebacks::writebacks 517954 # number of writebacks 565system.cpu0.dcache.writebacks::total 517954 # number of writebacks 566system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42678 # number of ReadReq MSHR hits 567system.cpu0.dcache.ReadReq_mshr_hits::total 42678 # number of ReadReq MSHR hits 568system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230706 # number of WriteReq MSHR hits 569system.cpu0.dcache.WriteReq_mshr_hits::total 230706 # number of WriteReq MSHR hits 570system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits 571system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits 572system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273384 # number of demand (read+write) MSHR hits 573system.cpu0.dcache.demand_mshr_hits::total 273384 # number of demand (read+write) MSHR hits 574system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273384 # number of overall MSHR hits 575system.cpu0.dcache.overall_mshr_hits::total 273384 # number of overall MSHR hits 576system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494623 # number of ReadReq MSHR misses 577system.cpu0.dcache.ReadReq_mshr_misses::total 494623 # number of ReadReq MSHR misses 578system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302058 # number of WriteReq MSHR misses 579system.cpu0.dcache.WriteReq_mshr_misses::total 302058 # number of WriteReq MSHR misses 580system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6411 # number of LoadLockedReq MSHR misses 581system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6411 # number of LoadLockedReq MSHR misses 582system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20204 # number of StoreCondReq MSHR misses 583system.cpu0.dcache.StoreCondReq_mshr_misses::total 20204 # number of StoreCondReq MSHR misses 584system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796681 # number of demand (read+write) MSHR misses 585system.cpu0.dcache.demand_mshr_misses::total 796681 # number of demand (read+write) MSHR misses 586system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796681 # number of overall MSHR misses 587system.cpu0.dcache.overall_mshr_misses::total 796681 # number of overall MSHR misses 588system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5117531439 # number of ReadReq MSHR miss cycles 589system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5117531439 # number of ReadReq MSHR miss cycles 590system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4270825900 # number of WriteReq MSHR miss cycles 591system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4270825900 # number of WriteReq MSHR miss cycles 592system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 92832750 # number of LoadLockedReq MSHR miss cycles 593system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 92832750 # number of LoadLockedReq MSHR miss cycles 594system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 396783949 # number of StoreCondReq MSHR miss cycles 595system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 396783949 # number of StoreCondReq MSHR miss cycles 596system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles 597system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles 598system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9388357339 # number of demand (read+write) MSHR miss cycles 599system.cpu0.dcache.demand_mshr_miss_latency::total 9388357339 # number of demand (read+write) MSHR miss cycles 600system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9388357339 # number of overall MSHR miss cycles 601system.cpu0.dcache.overall_mshr_miss_latency::total 9388357339 # number of overall MSHR miss cycles 602system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191310497 # number of ReadReq MSHR uncacheable cycles 603system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191310497 # number of ReadReq MSHR uncacheable cycles 604system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803760492 # number of WriteReq MSHR uncacheable cycles 605system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803760492 # number of WriteReq MSHR uncacheable cycles 606system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995070989 # number of overall MSHR uncacheable cycles 607system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995070989 # number of overall MSHR uncacheable cycles 608system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021192 # mshr miss rate for ReadReq accesses 609system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021192 # mshr miss rate for ReadReq accesses 610system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017364 # mshr miss rate for WriteReq accesses 611system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017364 # mshr miss rate for WriteReq accesses 612system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016525 # mshr miss rate for LoadLockedReq accesses 613system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016525 # mshr miss rate for LoadLockedReq accesses 614system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052775 # mshr miss rate for StoreCondReq accesses 615system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052775 # mshr miss rate for StoreCondReq accesses 616system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for demand accesses 617system.cpu0.dcache.demand_mshr_miss_rate::total 0.019557 # mshr miss rate for demand accesses 618system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for overall accesses 619system.cpu0.dcache.overall_mshr_miss_rate::total 0.019557 # mshr miss rate for overall accesses 620system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10346.327282 # average ReadReq mshr miss latency 621system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10346.327282 # average ReadReq mshr miss latency 622system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14139.092161 # average WriteReq mshr miss latency 623system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14139.092161 # average WriteReq mshr miss latency 624system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14480.229293 # average LoadLockedReq mshr miss latency 625system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14480.229293 # average LoadLockedReq mshr miss latency 626system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19638.880865 # average StoreCondReq mshr miss latency 627system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19638.880865 # average StoreCondReq mshr miss latency | 578system.cpu0.dcache.writebacks::writebacks 541643 # number of writebacks 579system.cpu0.dcache.writebacks::total 541643 # number of writebacks 580system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 45094 # number of ReadReq MSHR hits 581system.cpu0.dcache.ReadReq_mshr_hits::total 45094 # number of ReadReq MSHR hits 582system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 240822 # number of WriteReq MSHR hits 583system.cpu0.dcache.WriteReq_mshr_hits::total 240822 # number of WriteReq MSHR hits 584system.cpu0.dcache.demand_mshr_hits::cpu0.inst 285916 # number of demand (read+write) MSHR hits 585system.cpu0.dcache.demand_mshr_hits::total 285916 # number of demand (read+write) MSHR hits 586system.cpu0.dcache.overall_mshr_hits::cpu0.inst 285916 # number of overall MSHR hits 587system.cpu0.dcache.overall_mshr_hits::total 285916 # number of overall MSHR hits 588system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 519803 # number of ReadReq MSHR misses 589system.cpu0.dcache.ReadReq_mshr_misses::total 519803 # number of ReadReq MSHR misses 590system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 313587 # number of WriteReq MSHR misses 591system.cpu0.dcache.WriteReq_mshr_misses::total 313587 # number of WriteReq MSHR misses 592system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6644 # number of LoadLockedReq MSHR misses 593system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6644 # number of LoadLockedReq MSHR misses 594system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20340 # number of StoreCondReq MSHR misses 595system.cpu0.dcache.StoreCondReq_mshr_misses::total 20340 # number of StoreCondReq MSHR misses 596system.cpu0.dcache.demand_mshr_misses::cpu0.inst 833390 # number of demand (read+write) MSHR misses 597system.cpu0.dcache.demand_mshr_misses::total 833390 # number of demand (read+write) MSHR misses 598system.cpu0.dcache.overall_mshr_misses::cpu0.inst 833390 # number of overall MSHR misses 599system.cpu0.dcache.overall_mshr_misses::total 833390 # number of overall MSHR misses 600system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5323715430 # number of ReadReq MSHR miss cycles 601system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5323715430 # number of ReadReq MSHR miss cycles 602system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4366940170 # number of WriteReq MSHR miss cycles 603system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4366940170 # number of WriteReq MSHR miss cycles 604system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 94806000 # number of LoadLockedReq MSHR miss cycles 605system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94806000 # number of LoadLockedReq MSHR miss cycles 606system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 398879017 # number of StoreCondReq MSHR miss cycles 607system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 398879017 # number of StoreCondReq MSHR miss cycles 608system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 115000 # number of StoreCondFailReq MSHR miss cycles 609system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 115000 # number of StoreCondFailReq MSHR miss cycles 610system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9690655600 # number of demand (read+write) MSHR miss cycles 611system.cpu0.dcache.demand_mshr_miss_latency::total 9690655600 # number of demand (read+write) MSHR miss cycles 612system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9690655600 # number of overall MSHR miss cycles 613system.cpu0.dcache.overall_mshr_miss_latency::total 9690655600 # number of overall MSHR miss cycles 614system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6196262496 # number of ReadReq MSHR uncacheable cycles 615system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6196262496 # number of ReadReq MSHR uncacheable cycles 616system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4811489492 # number of WriteReq MSHR uncacheable cycles 617system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4811489492 # number of WriteReq MSHR uncacheable cycles 618system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11007751988 # number of overall MSHR uncacheable cycles 619system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11007751988 # number of overall MSHR uncacheable cycles 620system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021687 # mshr miss rate for ReadReq accesses 621system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021687 # mshr miss rate for ReadReq accesses 622system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017528 # mshr miss rate for WriteReq accesses 623system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017528 # mshr miss rate for WriteReq accesses 624system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016733 # mshr miss rate for LoadLockedReq accesses 625system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016733 # mshr miss rate for LoadLockedReq accesses 626system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051900 # mshr miss rate for StoreCondReq accesses 627system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051900 # mshr miss rate for StoreCondReq accesses 628system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for demand accesses 629system.cpu0.dcache.demand_mshr_miss_rate::total 0.019909 # mshr miss rate for demand accesses 630system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for overall accesses 631system.cpu0.dcache.overall_mshr_miss_rate::total 0.019909 # mshr miss rate for overall accesses 632system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10241.794353 # average ReadReq mshr miss latency 633system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10241.794353 # average ReadReq mshr miss latency 634system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13925.769149 # average WriteReq mshr miss latency 635system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13925.769149 # average WriteReq mshr miss latency 636system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14269.416014 # average LoadLockedReq mshr miss latency 637system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14269.416014 # average LoadLockedReq mshr miss latency 638system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19610.571141 # average StoreCondReq mshr miss latency 639system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19610.571141 # average StoreCondReq mshr miss latency |
| 628system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 629system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 640system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 641system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 630system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency 631system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency 632system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency 633system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency | 642system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency 643system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency 644system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency 645system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency |
| 634system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 635system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 636system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 637system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 638system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 639system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 640system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 646system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 648system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 649system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 650system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 651system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 652system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 641system.cpu0.icache.tags.replacements 1983566 # number of replacements 642system.cpu0.icache.tags.tagsinuse 511.796833 # Cycle average of tags in use 643system.cpu0.icache.tags.total_refs 68366923 # Total number of references to valid blocks. 644system.cpu0.icache.tags.sampled_refs 1984078 # Sample count of references to valid blocks. 645system.cpu0.icache.tags.avg_refs 34.457780 # Average number of references to valid blocks. 646system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. 647system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796833 # Average occupied blocks per requestor 648system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy 649system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy | 653system.cpu0.icache.tags.replacements 2070442 # number of replacements 654system.cpu0.icache.tags.tagsinuse 511.797171 # Cycle average of tags in use 655system.cpu0.icache.tags.total_refs 69582233 # Total number of references to valid blocks. 656system.cpu0.icache.tags.sampled_refs 2070954 # Sample count of references to valid blocks. 657system.cpu0.icache.tags.avg_refs 33.599121 # Average number of references to valid blocks. 658system.cpu0.icache.tags.warmup_cycle 6297775000 # Cycle when the warmup percentage was hit. 659system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.797171 # Average occupied blocks per requestor 660system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999604 # Average percentage of cache occupancy 661system.cpu0.icache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy |
| 650system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 662system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 651system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 652system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id 653system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id | 663system.cpu0.icache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id 664system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id 665system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id |
| 654system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 666system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 655system.cpu0.icache.tags.tag_accesses 142686127 # Number of tag accesses 656system.cpu0.icache.tags.data_accesses 142686127 # Number of data accesses 657system.cpu0.icache.ReadReq_hits::cpu0.inst 68366923 # number of ReadReq hits 658system.cpu0.icache.ReadReq_hits::total 68366923 # number of ReadReq hits 659system.cpu0.icache.demand_hits::cpu0.inst 68366923 # number of demand (read+write) hits 660system.cpu0.icache.demand_hits::total 68366923 # number of demand (read+write) hits 661system.cpu0.icache.overall_hits::cpu0.inst 68366923 # number of overall hits 662system.cpu0.icache.overall_hits::total 68366923 # number of overall hits 663system.cpu0.icache.ReadReq_misses::cpu0.inst 1984094 # number of ReadReq misses 664system.cpu0.icache.ReadReq_misses::total 1984094 # number of ReadReq misses 665system.cpu0.icache.demand_misses::cpu0.inst 1984094 # number of demand (read+write) misses 666system.cpu0.icache.demand_misses::total 1984094 # number of demand (read+write) misses 667system.cpu0.icache.overall_misses::cpu0.inst 1984094 # number of overall misses 668system.cpu0.icache.overall_misses::total 1984094 # number of overall misses 669system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16546799645 # number of ReadReq miss cycles 670system.cpu0.icache.ReadReq_miss_latency::total 16546799645 # number of ReadReq miss cycles 671system.cpu0.icache.demand_miss_latency::cpu0.inst 16546799645 # number of demand (read+write) miss cycles 672system.cpu0.icache.demand_miss_latency::total 16546799645 # number of demand (read+write) miss cycles 673system.cpu0.icache.overall_miss_latency::cpu0.inst 16546799645 # number of overall miss cycles 674system.cpu0.icache.overall_miss_latency::total 16546799645 # number of overall miss cycles 675system.cpu0.icache.ReadReq_accesses::cpu0.inst 70351017 # number of ReadReq accesses(hits+misses) 676system.cpu0.icache.ReadReq_accesses::total 70351017 # number of ReadReq accesses(hits+misses) 677system.cpu0.icache.demand_accesses::cpu0.inst 70351017 # number of demand (read+write) accesses 678system.cpu0.icache.demand_accesses::total 70351017 # number of demand (read+write) accesses 679system.cpu0.icache.overall_accesses::cpu0.inst 70351017 # number of overall (read+write) accesses 680system.cpu0.icache.overall_accesses::total 70351017 # number of overall (read+write) accesses 681system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028203 # miss rate for ReadReq accesses 682system.cpu0.icache.ReadReq_miss_rate::total 0.028203 # miss rate for ReadReq accesses 683system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028203 # miss rate for demand accesses 684system.cpu0.icache.demand_miss_rate::total 0.028203 # miss rate for demand accesses 685system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028203 # miss rate for overall accesses 686system.cpu0.icache.overall_miss_rate::total 0.028203 # miss rate for overall accesses 687system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.725661 # average ReadReq miss latency 688system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.725661 # average ReadReq miss latency 689system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency 690system.cpu0.icache.demand_avg_miss_latency::total 8339.725661 # average overall miss latency 691system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency 692system.cpu0.icache.overall_avg_miss_latency::total 8339.725661 # average overall miss latency | 667system.cpu0.icache.tags.tag_accesses 145377375 # Number of tag accesses 668system.cpu0.icache.tags.data_accesses 145377375 # Number of data accesses 669system.cpu0.icache.ReadReq_hits::cpu0.inst 69582233 # number of ReadReq hits 670system.cpu0.icache.ReadReq_hits::total 69582233 # number of ReadReq hits 671system.cpu0.icache.demand_hits::cpu0.inst 69582233 # number of demand (read+write) hits 672system.cpu0.icache.demand_hits::total 69582233 # number of demand (read+write) hits 673system.cpu0.icache.overall_hits::cpu0.inst 69582233 # number of overall hits 674system.cpu0.icache.overall_hits::total 69582233 # number of overall hits 675system.cpu0.icache.ReadReq_misses::cpu0.inst 2070970 # number of ReadReq misses 676system.cpu0.icache.ReadReq_misses::total 2070970 # number of ReadReq misses 677system.cpu0.icache.demand_misses::cpu0.inst 2070970 # number of demand (read+write) misses 678system.cpu0.icache.demand_misses::total 2070970 # number of demand (read+write) misses 679system.cpu0.icache.overall_misses::cpu0.inst 2070970 # number of overall misses 680system.cpu0.icache.overall_misses::total 2070970 # number of overall misses 681system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17258012980 # number of ReadReq miss cycles 682system.cpu0.icache.ReadReq_miss_latency::total 17258012980 # number of ReadReq miss cycles 683system.cpu0.icache.demand_miss_latency::cpu0.inst 17258012980 # number of demand (read+write) miss cycles 684system.cpu0.icache.demand_miss_latency::total 17258012980 # number of demand (read+write) miss cycles 685system.cpu0.icache.overall_miss_latency::cpu0.inst 17258012980 # number of overall miss cycles 686system.cpu0.icache.overall_miss_latency::total 17258012980 # number of overall miss cycles 687system.cpu0.icache.ReadReq_accesses::cpu0.inst 71653203 # number of ReadReq accesses(hits+misses) 688system.cpu0.icache.ReadReq_accesses::total 71653203 # number of ReadReq accesses(hits+misses) 689system.cpu0.icache.demand_accesses::cpu0.inst 71653203 # number of demand (read+write) accesses 690system.cpu0.icache.demand_accesses::total 71653203 # number of demand (read+write) accesses 691system.cpu0.icache.overall_accesses::cpu0.inst 71653203 # number of overall (read+write) accesses 692system.cpu0.icache.overall_accesses::total 71653203 # number of overall (read+write) accesses 693system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028903 # miss rate for ReadReq accesses 694system.cpu0.icache.ReadReq_miss_rate::total 0.028903 # miss rate for ReadReq accesses 695system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028903 # miss rate for demand accesses 696system.cpu0.icache.demand_miss_rate::total 0.028903 # miss rate for demand accesses 697system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028903 # miss rate for overall accesses 698system.cpu0.icache.overall_miss_rate::total 0.028903 # miss rate for overall accesses 699system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8333.299362 # average ReadReq miss latency 700system.cpu0.icache.ReadReq_avg_miss_latency::total 8333.299362 # average ReadReq miss latency 701system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency 702system.cpu0.icache.demand_avg_miss_latency::total 8333.299362 # average overall miss latency 703system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency 704system.cpu0.icache.overall_avg_miss_latency::total 8333.299362 # average overall miss latency |
| 693system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 697system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 698system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 699system.cpu0.icache.fast_writes 0 # number of fast writes performed 700system.cpu0.icache.cache_copies 0 # number of cache copies performed | 705system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 706system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 707system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 708system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 709system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 710system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 711system.cpu0.icache.fast_writes 0 # number of fast writes performed 712system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 701system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1984094 # number of ReadReq MSHR misses 702system.cpu0.icache.ReadReq_mshr_misses::total 1984094 # number of ReadReq MSHR misses 703system.cpu0.icache.demand_mshr_misses::cpu0.inst 1984094 # number of demand (read+write) MSHR misses 704system.cpu0.icache.demand_mshr_misses::total 1984094 # number of demand (read+write) MSHR misses 705system.cpu0.icache.overall_mshr_misses::cpu0.inst 1984094 # number of overall MSHR misses 706system.cpu0.icache.overall_mshr_misses::total 1984094 # number of overall MSHR misses 707system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13568682853 # number of ReadReq MSHR miss cycles 708system.cpu0.icache.ReadReq_mshr_miss_latency::total 13568682853 # number of ReadReq MSHR miss cycles 709system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13568682853 # number of demand (read+write) MSHR miss cycles 710system.cpu0.icache.demand_mshr_miss_latency::total 13568682853 # number of demand (read+write) MSHR miss cycles 711system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13568682853 # number of overall MSHR miss cycles 712system.cpu0.icache.overall_mshr_miss_latency::total 13568682853 # number of overall MSHR miss cycles 713system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276787500 # number of ReadReq MSHR uncacheable cycles 714system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276787500 # number of ReadReq MSHR uncacheable cycles 715system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276787500 # number of overall MSHR uncacheable cycles 716system.cpu0.icache.overall_mshr_uncacheable_latency::total 276787500 # number of overall MSHR uncacheable cycles 717system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for ReadReq accesses 718system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028203 # mshr miss rate for ReadReq accesses 719system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for demand accesses 720system.cpu0.icache.demand_mshr_miss_rate::total 0.028203 # mshr miss rate for demand accesses 721system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for overall accesses 722system.cpu0.icache.overall_mshr_miss_rate::total 0.028203 # mshr miss rate for overall accesses 723system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average ReadReq mshr miss latency 724system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.729845 # average ReadReq mshr miss latency 725system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency 726system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency 727system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency 728system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency | 713system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2070970 # number of ReadReq MSHR misses 714system.cpu0.icache.ReadReq_mshr_misses::total 2070970 # number of ReadReq MSHR misses 715system.cpu0.icache.demand_mshr_misses::cpu0.inst 2070970 # number of demand (read+write) MSHR misses 716system.cpu0.icache.demand_mshr_misses::total 2070970 # number of demand (read+write) MSHR misses 717system.cpu0.icache.overall_mshr_misses::cpu0.inst 2070970 # number of overall MSHR misses 718system.cpu0.icache.overall_mshr_misses::total 2070970 # number of overall MSHR misses 719system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 14149699520 # number of ReadReq MSHR miss cycles 720system.cpu0.icache.ReadReq_mshr_miss_latency::total 14149699520 # number of ReadReq MSHR miss cycles 721system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 14149699520 # number of demand (read+write) MSHR miss cycles 722system.cpu0.icache.demand_mshr_miss_latency::total 14149699520 # number of demand (read+write) MSHR miss cycles 723system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 14149699520 # number of overall MSHR miss cycles 724system.cpu0.icache.overall_mshr_miss_latency::total 14149699520 # number of overall MSHR miss cycles 725system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276493750 # number of ReadReq MSHR uncacheable cycles 726system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276493750 # number of ReadReq MSHR uncacheable cycles 727system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276493750 # number of overall MSHR uncacheable cycles 728system.cpu0.icache.overall_mshr_uncacheable_latency::total 276493750 # number of overall MSHR uncacheable cycles 729system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for ReadReq accesses 730system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028903 # mshr miss rate for ReadReq accesses 731system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for demand accesses 732system.cpu0.icache.demand_mshr_miss_rate::total 0.028903 # mshr miss rate for demand accesses 733system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for overall accesses 734system.cpu0.icache.overall_mshr_miss_rate::total 0.028903 # mshr miss rate for overall accesses 735system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average ReadReq mshr miss latency 736system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6832.401976 # average ReadReq mshr miss latency 737system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency 738system.cpu0.icache.demand_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency 739system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency 740system.cpu0.icache.overall_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency |
| 729system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 730system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 731system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 732system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 733system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 741system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 742system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 743system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 744system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 745system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 734system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17337039 # number of hwpf identified 735system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425762 # number of hwpf that were already in mshr 736system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16383461 # number of hwpf that were already in the cache 737system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9078 # number of hwpf that were already in the prefetch queue | 746system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 18115074 # number of hwpf identified 747system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 431506 # number of hwpf that were already in mshr 748system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 17132776 # number of hwpf that were already in the cache 749system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9283 # number of hwpf that were already in the prefetch queue |
| 738system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 750system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 739system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6456 # number of hwpf removed because MSHR allocated 740system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512279 # number of hwpf issued 741system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329409 # number of hwpf spanning a virtual page | 751system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6596 # number of hwpf removed because MSHR allocated 752system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 534910 # number of hwpf issued 753system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1383846 # number of hwpf spanning a virtual page |
| 742system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 754system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 743system.cpu0.l2cache.tags.replacements 409357 # number of replacements 744system.cpu0.l2cache.tags.tagsinuse 16202.462840 # Cycle average of tags in use 745system.cpu0.l2cache.tags.total_refs 3013500 # Total number of references to valid blocks. 746system.cpu0.l2cache.tags.sampled_refs 425611 # Sample count of references to valid blocks. 747system.cpu0.l2cache.tags.avg_refs 7.080409 # Average number of references to valid blocks. 748system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 749system.cpu0.l2cache.tags.occ_blocks::writebacks 4205.324174 # Average occupied blocks per requestor 750system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 51.364575 # Average occupied blocks per requestor 751system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062072 # Average occupied blocks per requestor 752system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2198.474976 # Average occupied blocks per requestor 753system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.237044 # Average occupied blocks per requestor 754system.cpu0.l2cache.tags.occ_percent::writebacks 0.256673 # Average percentage of cache occupancy 755system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003135 # Average percentage of cache occupancy | 755system.cpu0.l2cache.tags.replacements 428439 # number of replacements 756system.cpu0.l2cache.tags.tagsinuse 16212.256950 # Cycle average of tags in use 757system.cpu0.l2cache.tags.total_refs 3152645 # Total number of references to valid blocks. 758system.cpu0.l2cache.tags.sampled_refs 444682 # Sample count of references to valid blocks. 759system.cpu0.l2cache.tags.avg_refs 7.089662 # Average number of references to valid blocks. 760system.cpu0.l2cache.tags.warmup_cycle 2824980212500 # Cycle when the warmup percentage was hit. 761system.cpu0.l2cache.tags.occ_blocks::writebacks 4226.197620 # Average occupied blocks per requestor 762system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.775812 # Average occupied blocks per requestor 763system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065487 # Average occupied blocks per requestor 764system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2187.555983 # Average occupied blocks per requestor 765system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.662049 # Average occupied blocks per requestor 766system.cpu0.l2cache.tags.occ_percent::writebacks 0.257947 # Average percentage of cache occupancy 767system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003099 # Average percentage of cache occupancy |
| 756system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy | 768system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy |
| 757system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134184 # Average percentage of cache occupancy 758system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594924 # Average percentage of cache occupancy 759system.cpu0.l2cache.tags.occ_percent::total 0.988920 # Average percentage of cache occupancy 760system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8963 # Occupied blocks per task id 761system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 762system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7281 # Occupied blocks per task id 763system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 54 # Occupied blocks per task id 764system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id 765system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2805 # Occupied blocks per task id 766system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5150 # Occupied blocks per task id 767system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 820 # Occupied blocks per task id 768system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 769system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 770system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 771system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 772system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 773system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 774system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id 775system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3125 # Occupied blocks per task id 776system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3482 # Occupied blocks per task id 777system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 341 # Occupied blocks per task id 778system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.547058 # Percentage of cache occupancy per task id 779system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 780system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444397 # Percentage of cache occupancy per task id 781system.cpu0.l2cache.tags.tag_accesses 55309059 # Number of tag accesses 782system.cpu0.l2cache.tags.data_accesses 55309059 # Number of data accesses 783system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77781 # number of ReadReq hits 784system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4268 # number of ReadReq hits 785system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390782 # number of ReadReq hits 786system.cpu0.l2cache.ReadReq_hits::total 2472831 # number of ReadReq hits 787system.cpu0.l2cache.Writeback_hits::writebacks 517951 # number of Writeback hits 788system.cpu0.l2cache.Writeback_hits::total 517951 # number of Writeback hits 789system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4630 # number of UpgradeReq hits 790system.cpu0.l2cache.UpgradeReq_hits::total 4630 # number of UpgradeReq hits 791system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2244 # number of SCUpgradeReq hits 792system.cpu0.l2cache.SCUpgradeReq_hits::total 2244 # number of SCUpgradeReq hits 793system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223140 # number of ReadExReq hits 794system.cpu0.l2cache.ReadExReq_hits::total 223140 # number of ReadExReq hits 795system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77781 # number of demand (read+write) hits 796system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4268 # number of demand (read+write) hits 797system.cpu0.l2cache.demand_hits::cpu0.inst 2613922 # number of demand (read+write) hits 798system.cpu0.l2cache.demand_hits::total 2695971 # number of demand (read+write) hits 799system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77781 # number of overall hits 800system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4268 # number of overall hits 801system.cpu0.l2cache.overall_hits::cpu0.inst 2613922 # number of overall hits 802system.cpu0.l2cache.overall_hits::total 2695971 # number of overall hits 803system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 986 # number of ReadReq misses 804system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses 805system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94341 # number of ReadReq misses 806system.cpu0.l2cache.ReadReq_misses::total 95500 # number of ReadReq misses 807system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27941 # number of UpgradeReq misses 808system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses 809system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17958 # number of SCUpgradeReq misses 810system.cpu0.l2cache.SCUpgradeReq_misses::total 17958 # number of SCUpgradeReq misses 811system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 2 # number of SCUpgradeFailReq misses 812system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 813system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46352 # number of ReadExReq misses 814system.cpu0.l2cache.ReadExReq_misses::total 46352 # number of ReadExReq misses 815system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 986 # number of demand (read+write) misses 816system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses 817system.cpu0.l2cache.demand_misses::cpu0.inst 140693 # number of demand (read+write) misses 818system.cpu0.l2cache.demand_misses::total 141852 # number of demand (read+write) misses 819system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 986 # number of overall misses 820system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses 821system.cpu0.l2cache.overall_misses::cpu0.inst 140693 # number of overall misses 822system.cpu0.l2cache.overall_misses::total 141852 # number of overall misses 823system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 32261749 # number of ReadReq miss cycles 824system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3849999 # number of ReadReq miss cycles 825system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2894443882 # number of ReadReq miss cycles 826system.cpu0.l2cache.ReadReq_miss_latency::total 2930555630 # number of ReadReq miss cycles 827system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 497270548 # number of UpgradeReq miss cycles 828system.cpu0.l2cache.UpgradeReq_miss_latency::total 497270548 # number of UpgradeReq miss cycles 829system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 354837739 # number of SCUpgradeReq miss cycles 830system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 354837739 # number of SCUpgradeReq miss cycles 831system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 117000 # number of SCUpgradeFailReq miss cycles 832system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 117000 # number of SCUpgradeFailReq miss cycles 833system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1925679719 # number of ReadExReq miss cycles 834system.cpu0.l2cache.ReadExReq_miss_latency::total 1925679719 # number of ReadExReq miss cycles 835system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 32261749 # number of demand (read+write) miss cycles 836system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3849999 # number of demand (read+write) miss cycles 837system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4820123601 # number of demand (read+write) miss cycles 838system.cpu0.l2cache.demand_miss_latency::total 4856235349 # number of demand (read+write) miss cycles 839system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 32261749 # number of overall miss cycles 840system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3849999 # number of overall miss cycles 841system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4820123601 # number of overall miss cycles 842system.cpu0.l2cache.overall_miss_latency::total 4856235349 # number of overall miss cycles 843system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78767 # number of ReadReq accesses(hits+misses) 844system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4441 # number of ReadReq accesses(hits+misses) 845system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2485123 # number of ReadReq accesses(hits+misses) 846system.cpu0.l2cache.ReadReq_accesses::total 2568331 # number of ReadReq accesses(hits+misses) 847system.cpu0.l2cache.Writeback_accesses::writebacks 517951 # number of Writeback accesses(hits+misses) 848system.cpu0.l2cache.Writeback_accesses::total 517951 # number of Writeback accesses(hits+misses) 849system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32571 # number of UpgradeReq accesses(hits+misses) 850system.cpu0.l2cache.UpgradeReq_accesses::total 32571 # number of UpgradeReq accesses(hits+misses) 851system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20202 # number of SCUpgradeReq accesses(hits+misses) 852system.cpu0.l2cache.SCUpgradeReq_accesses::total 20202 # number of SCUpgradeReq accesses(hits+misses) 853system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 2 # number of SCUpgradeFailReq accesses(hits+misses) 854system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 855system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 269492 # number of ReadExReq accesses(hits+misses) 856system.cpu0.l2cache.ReadExReq_accesses::total 269492 # number of ReadExReq accesses(hits+misses) 857system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78767 # number of demand (read+write) accesses 858system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4441 # number of demand (read+write) accesses 859system.cpu0.l2cache.demand_accesses::cpu0.inst 2754615 # number of demand (read+write) accesses 860system.cpu0.l2cache.demand_accesses::total 2837823 # number of demand (read+write) accesses 861system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78767 # number of overall (read+write) accesses 862system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4441 # number of overall (read+write) accesses 863system.cpu0.l2cache.overall_accesses::cpu0.inst 2754615 # number of overall (read+write) accesses 864system.cpu0.l2cache.overall_accesses::total 2837823 # number of overall (read+write) accesses 865system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for ReadReq accesses 866system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.038955 # miss rate for ReadReq accesses 867system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037962 # miss rate for ReadReq accesses 868system.cpu0.l2cache.ReadReq_miss_rate::total 0.037184 # miss rate for ReadReq accesses 869system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.857849 # miss rate for UpgradeReq accesses 870system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.857849 # miss rate for UpgradeReq accesses 871system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.888922 # miss rate for SCUpgradeReq accesses 872system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.888922 # miss rate for SCUpgradeReq accesses 873system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses 874system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 875system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.171998 # miss rate for ReadExReq accesses 876system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171998 # miss rate for ReadExReq accesses 877system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for demand accesses 878system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.038955 # miss rate for demand accesses 879system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051075 # miss rate for demand accesses 880system.cpu0.l2cache.demand_miss_rate::total 0.049986 # miss rate for demand accesses 881system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for overall accesses 882system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.038955 # miss rate for overall accesses 883system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051075 # miss rate for overall accesses 884system.cpu0.l2cache.overall_miss_rate::total 0.049986 # miss rate for overall accesses 885system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average ReadReq miss latency 886system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22254.329480 # average ReadReq miss latency 887system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30680.657212 # average ReadReq miss latency 888system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30686.446387 # average ReadReq miss latency 889system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17797.163595 # average UpgradeReq miss latency 890system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17797.163595 # average UpgradeReq miss latency 891system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19759.312785 # average SCUpgradeReq miss latency 892system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19759.312785 # average SCUpgradeReq miss latency 893system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 58500 # average SCUpgradeFailReq miss latency 894system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 58500 # average SCUpgradeFailReq miss latency 895system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41544.695353 # average ReadExReq miss latency 896system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41544.695353 # average ReadExReq miss latency 897system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average overall miss latency 898system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22254.329480 # average overall miss latency 899system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34259.867947 # average overall miss latency 900system.cpu0.l2cache.demand_avg_miss_latency::total 34234.521537 # average overall miss latency 901system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average overall miss latency 902system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22254.329480 # average overall miss latency 903system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34259.867947 # average overall miss latency 904system.cpu0.l2cache.overall_avg_miss_latency::total 34234.521537 # average overall miss latency 905system.cpu0.l2cache.blocked_cycles::no_mshrs 25463 # number of cycles access was blocked | 769system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.133518 # Average percentage of cache occupancy 770system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594950 # Average percentage of cache occupancy 771system.cpu0.l2cache.tags.occ_percent::total 0.989518 # Average percentage of cache occupancy 772system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8981 # Occupied blocks per task id 773system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 774system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7254 # Occupied blocks per task id 775system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 61 # Occupied blocks per task id 776system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 111 # Occupied blocks per task id 777system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2870 # Occupied blocks per task id 778system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5529 # Occupied blocks per task id 779system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 410 # Occupied blocks per task id 780system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 781system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 782system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 783system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id 784system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3049 # Occupied blocks per task id 785system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3651 # Occupied blocks per task id 786system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 230 # Occupied blocks per task id 787system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.548157 # Percentage of cache occupancy per task id 788system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 789system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.442749 # Percentage of cache occupancy per task id 790system.cpu0.l2cache.tags.tag_accesses 57799798 # Number of tag accesses 791system.cpu0.l2cache.tags.data_accesses 57799798 # Number of data accesses 792system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 84149 # number of ReadReq hits 793system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4243 # number of ReadReq hits 794system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2500411 # number of ReadReq hits 795system.cpu0.l2cache.ReadReq_hits::total 2588803 # number of ReadReq hits 796system.cpu0.l2cache.Writeback_hits::writebacks 541643 # number of Writeback hits 797system.cpu0.l2cache.Writeback_hits::total 541643 # number of Writeback hits 798system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4674 # number of UpgradeReq hits 799system.cpu0.l2cache.UpgradeReq_hits::total 4674 # number of UpgradeReq hits 800system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2411 # number of SCUpgradeReq hits 801system.cpu0.l2cache.SCUpgradeReq_hits::total 2411 # number of SCUpgradeReq hits 802system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 234433 # number of ReadExReq hits 803system.cpu0.l2cache.ReadExReq_hits::total 234433 # number of ReadExReq hits 804system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 84149 # number of demand (read+write) hits 805system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4243 # number of demand (read+write) hits 806system.cpu0.l2cache.demand_hits::cpu0.inst 2734844 # number of demand (read+write) hits 807system.cpu0.l2cache.demand_hits::total 2823236 # number of demand (read+write) hits 808system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 84149 # number of overall hits 809system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4243 # number of overall hits 810system.cpu0.l2cache.overall_hits::cpu0.inst 2734844 # number of overall hits 811system.cpu0.l2cache.overall_hits::total 2823236 # number of overall hits 812system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 906 # number of ReadReq misses 813system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses 814system.cpu0.l2cache.ReadReq_misses::cpu0.inst 97001 # number of ReadReq misses 815system.cpu0.l2cache.ReadReq_misses::total 98045 # number of ReadReq misses 816system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27960 # number of UpgradeReq misses 817system.cpu0.l2cache.UpgradeReq_misses::total 27960 # number of UpgradeReq misses 818system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17929 # number of SCUpgradeReq misses 819system.cpu0.l2cache.SCUpgradeReq_misses::total 17929 # number of SCUpgradeReq misses 820system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46525 # number of ReadExReq misses 821system.cpu0.l2cache.ReadExReq_misses::total 46525 # number of ReadExReq misses 822system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 906 # number of demand (read+write) misses 823system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses 824system.cpu0.l2cache.demand_misses::cpu0.inst 143526 # number of demand (read+write) misses 825system.cpu0.l2cache.demand_misses::total 144570 # number of demand (read+write) misses 826system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 906 # number of overall misses 827system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses 828system.cpu0.l2cache.overall_misses::cpu0.inst 143526 # number of overall misses 829system.cpu0.l2cache.overall_misses::total 144570 # number of overall misses 830system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31530500 # number of ReadReq miss cycles 831system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3231999 # number of ReadReq miss cycles 832system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2954004148 # number of ReadReq miss cycles 833system.cpu0.l2cache.ReadReq_miss_latency::total 2988766647 # number of ReadReq miss cycles 834system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 497244183 # number of UpgradeReq miss cycles 835system.cpu0.l2cache.UpgradeReq_miss_latency::total 497244183 # number of UpgradeReq miss cycles 836system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 356127296 # number of SCUpgradeReq miss cycles 837system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356127296 # number of SCUpgradeReq miss cycles 838system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 112000 # number of SCUpgradeFailReq miss cycles 839system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 112000 # number of SCUpgradeFailReq miss cycles 840system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1936152477 # number of ReadExReq miss cycles 841system.cpu0.l2cache.ReadExReq_miss_latency::total 1936152477 # number of ReadExReq miss cycles 842system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31530500 # number of demand (read+write) miss cycles 843system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3231999 # number of demand (read+write) miss cycles 844system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4890156625 # number of demand (read+write) miss cycles 845system.cpu0.l2cache.demand_miss_latency::total 4924919124 # number of demand (read+write) miss cycles 846system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31530500 # number of overall miss cycles 847system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3231999 # number of overall miss cycles 848system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4890156625 # number of overall miss cycles 849system.cpu0.l2cache.overall_miss_latency::total 4924919124 # number of overall miss cycles 850system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 85055 # number of ReadReq accesses(hits+misses) 851system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4381 # number of ReadReq accesses(hits+misses) 852system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2597412 # number of ReadReq accesses(hits+misses) 853system.cpu0.l2cache.ReadReq_accesses::total 2686848 # number of ReadReq accesses(hits+misses) 854system.cpu0.l2cache.Writeback_accesses::writebacks 541643 # number of Writeback accesses(hits+misses) 855system.cpu0.l2cache.Writeback_accesses::total 541643 # number of Writeback accesses(hits+misses) 856system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32634 # number of UpgradeReq accesses(hits+misses) 857system.cpu0.l2cache.UpgradeReq_accesses::total 32634 # number of UpgradeReq accesses(hits+misses) 858system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20340 # number of SCUpgradeReq accesses(hits+misses) 859system.cpu0.l2cache.SCUpgradeReq_accesses::total 20340 # number of SCUpgradeReq accesses(hits+misses) 860system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 280958 # number of ReadExReq accesses(hits+misses) 861system.cpu0.l2cache.ReadExReq_accesses::total 280958 # number of ReadExReq accesses(hits+misses) 862system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 85055 # number of demand (read+write) accesses 863system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4381 # number of demand (read+write) accesses 864system.cpu0.l2cache.demand_accesses::cpu0.inst 2878370 # number of demand (read+write) accesses 865system.cpu0.l2cache.demand_accesses::total 2967806 # number of demand (read+write) accesses 866system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 85055 # number of overall (read+write) accesses 867system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4381 # number of overall (read+write) accesses 868system.cpu0.l2cache.overall_accesses::cpu0.inst 2878370 # number of overall (read+write) accesses 869system.cpu0.l2cache.overall_accesses::total 2967806 # number of overall (read+write) accesses 870system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for ReadReq accesses 871system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031500 # miss rate for ReadReq accesses 872system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037345 # miss rate for ReadReq accesses 873system.cpu0.l2cache.ReadReq_miss_rate::total 0.036491 # miss rate for ReadReq accesses 874system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.856775 # miss rate for UpgradeReq accesses 875system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.856775 # miss rate for UpgradeReq accesses 876system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.881465 # miss rate for SCUpgradeReq accesses 877system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.881465 # miss rate for SCUpgradeReq accesses 878system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.165594 # miss rate for ReadExReq accesses 879system.cpu0.l2cache.ReadExReq_miss_rate::total 0.165594 # miss rate for ReadExReq accesses 880system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for demand accesses 881system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031500 # miss rate for demand accesses 882system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.049864 # miss rate for demand accesses 883system.cpu0.l2cache.demand_miss_rate::total 0.048713 # miss rate for demand accesses 884system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for overall accesses 885system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031500 # miss rate for overall accesses 886system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.049864 # miss rate for overall accesses 887system.cpu0.l2cache.overall_miss_rate::total 0.048713 # miss rate for overall accesses 888system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average ReadReq miss latency 889system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23420.282609 # average ReadReq miss latency 890system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30453.337058 # average ReadReq miss latency 891system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30483.621266 # average ReadReq miss latency 892system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17784.126717 # average UpgradeReq miss latency 893system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17784.126717 # average UpgradeReq miss latency 894system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19863.199063 # average SCUpgradeReq miss latency 895system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19863.199063 # average SCUpgradeReq miss latency 896system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency 897system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 898system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41615.313853 # average ReadExReq miss latency 899system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41615.313853 # average ReadExReq miss latency 900system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average overall miss latency 901system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23420.282609 # average overall miss latency 902system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34071.573269 # average overall miss latency 903system.cpu0.l2cache.demand_avg_miss_latency::total 34065.982735 # average overall miss latency 904system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average overall miss latency 905system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23420.282609 # average overall miss latency 906system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34071.573269 # average overall miss latency 907system.cpu0.l2cache.overall_avg_miss_latency::total 34065.982735 # average overall miss latency 908system.cpu0.l2cache.blocked_cycles::no_mshrs 25119 # number of cycles access was blocked |
| 906system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 909system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 907system.cpu0.l2cache.blocked::no_mshrs 375 # number of cycles access was blocked | 910system.cpu0.l2cache.blocked::no_mshrs 346 # number of cycles access was blocked |
| 908system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 911system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 909system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 67.901333 # average number of cycles each access was blocked | 912system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 72.598266 # average number of cycles each access was blocked |
| 910system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 911system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 912system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 913system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 914system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 915system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 913system.cpu0.l2cache.writebacks::writebacks 214094 # number of writebacks 914system.cpu0.l2cache.writebacks::total 214094 # number of writebacks 915system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7763 # number of ReadReq MSHR hits 916system.cpu0.l2cache.ReadReq_mshr_hits::total 7763 # number of ReadReq MSHR hits 917system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3115 # number of ReadExReq MSHR hits 918system.cpu0.l2cache.ReadExReq_mshr_hits::total 3115 # number of ReadExReq MSHR hits 919system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10878 # number of demand (read+write) MSHR hits 920system.cpu0.l2cache.demand_mshr_hits::total 10878 # number of demand (read+write) MSHR hits 921system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10878 # number of overall MSHR hits 922system.cpu0.l2cache.overall_mshr_hits::total 10878 # number of overall MSHR hits 923system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 986 # number of ReadReq MSHR misses 924system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses 925system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86578 # number of ReadReq MSHR misses 926system.cpu0.l2cache.ReadReq_mshr_misses::total 87737 # number of ReadReq MSHR misses 927system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 512278 # number of HardPFReq MSHR misses 928system.cpu0.l2cache.HardPFReq_mshr_misses::total 512278 # number of HardPFReq MSHR misses 929system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27941 # number of UpgradeReq MSHR misses 930system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27941 # number of UpgradeReq MSHR misses 931system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17958 # number of SCUpgradeReq MSHR misses 932system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17958 # number of SCUpgradeReq MSHR misses 933system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 2 # number of SCUpgradeFailReq MSHR misses 934system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 935system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43237 # number of ReadExReq MSHR misses 936system.cpu0.l2cache.ReadExReq_mshr_misses::total 43237 # number of ReadExReq MSHR misses 937system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 986 # number of demand (read+write) MSHR misses 938system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses 939system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 129815 # number of demand (read+write) MSHR misses 940system.cpu0.l2cache.demand_mshr_misses::total 130974 # number of demand (read+write) MSHR misses 941system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 986 # number of overall MSHR misses 942system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses 943system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 129815 # number of overall MSHR misses 944system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 512278 # number of overall MSHR misses 945system.cpu0.l2cache.overall_mshr_misses::total 643252 # number of overall MSHR misses 946system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of ReadReq MSHR miss cycles 947system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2638999 # number of ReadReq MSHR miss cycles 948system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2121502252 # number of ReadReq MSHR miss cycles 949system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2149486002 # number of ReadReq MSHR miss cycles 950system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21334624793 # number of HardPFReq MSHR miss cycles 951system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21334624793 # number of HardPFReq MSHR miss cycles 952system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 476101816 # number of UpgradeReq MSHR miss cycles 953system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 476101816 # number of UpgradeReq MSHR miss cycles 954system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 237455029 # number of SCUpgradeReq MSHR miss cycles 955system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 237455029 # number of SCUpgradeReq MSHR miss cycles 956system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 89000 # number of SCUpgradeFailReq MSHR miss cycles 957system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 89000 # number of SCUpgradeFailReq MSHR miss cycles 958system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1189409987 # number of ReadExReq MSHR miss cycles 959system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1189409987 # number of ReadExReq MSHR miss cycles 960system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of demand (read+write) MSHR miss cycles 961system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2638999 # number of demand (read+write) MSHR miss cycles 962system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3310912239 # number of demand (read+write) MSHR miss cycles 963system.cpu0.l2cache.demand_mshr_miss_latency::total 3338895989 # number of demand (read+write) MSHR miss cycles 964system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of overall MSHR miss cycles 965system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2638999 # number of overall MSHR miss cycles 966system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3310912239 # number of overall MSHR miss cycles 967system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21334624793 # number of overall MSHR miss cycles 968system.cpu0.l2cache.overall_mshr_miss_latency::total 24673520782 # number of overall MSHR miss cycles 969system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6176243748 # number of ReadReq MSHR uncacheable cycles 970system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6176243748 # number of ReadReq MSHR uncacheable cycles 971system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4587514507 # number of WriteReq MSHR uncacheable cycles 972system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4587514507 # number of WriteReq MSHR uncacheable cycles 973system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10763758255 # number of overall MSHR uncacheable cycles 974system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10763758255 # number of overall MSHR uncacheable cycles 975system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for ReadReq accesses 976system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for ReadReq accesses 977system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034839 # mshr miss rate for ReadReq accesses 978system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034161 # mshr miss rate for ReadReq accesses | 916system.cpu0.l2cache.writebacks::writebacks 220063 # number of writebacks 917system.cpu0.l2cache.writebacks::total 220063 # number of writebacks 918system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 8315 # number of ReadReq MSHR hits 919system.cpu0.l2cache.ReadReq_mshr_hits::total 8315 # number of ReadReq MSHR hits 920system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3034 # number of ReadExReq MSHR hits 921system.cpu0.l2cache.ReadExReq_mshr_hits::total 3034 # number of ReadExReq MSHR hits 922system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11349 # number of demand (read+write) MSHR hits 923system.cpu0.l2cache.demand_mshr_hits::total 11349 # number of demand (read+write) MSHR hits 924system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11349 # number of overall MSHR hits 925system.cpu0.l2cache.overall_mshr_hits::total 11349 # number of overall MSHR hits 926system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 906 # number of ReadReq MSHR misses 927system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 138 # number of ReadReq MSHR misses 928system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 88686 # number of ReadReq MSHR misses 929system.cpu0.l2cache.ReadReq_mshr_misses::total 89730 # number of ReadReq MSHR misses 930system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 534906 # number of HardPFReq MSHR misses 931system.cpu0.l2cache.HardPFReq_mshr_misses::total 534906 # number of HardPFReq MSHR misses 932system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27960 # number of UpgradeReq MSHR misses 933system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27960 # number of UpgradeReq MSHR misses 934system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17929 # number of SCUpgradeReq MSHR misses 935system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17929 # number of SCUpgradeReq MSHR misses 936system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43491 # number of ReadExReq MSHR misses 937system.cpu0.l2cache.ReadExReq_mshr_misses::total 43491 # number of ReadExReq MSHR misses 938system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 906 # number of demand (read+write) MSHR misses 939system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 138 # number of demand (read+write) MSHR misses 940system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 132177 # number of demand (read+write) MSHR misses 941system.cpu0.l2cache.demand_mshr_misses::total 133221 # number of demand (read+write) MSHR misses 942system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 906 # number of overall MSHR misses 943system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 138 # number of overall MSHR misses 944system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 132177 # number of overall MSHR misses 945system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 534906 # number of overall MSHR misses 946system.cpu0.l2cache.overall_mshr_misses::total 668127 # number of overall MSHR misses 947system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of ReadReq MSHR miss cycles 948system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2265999 # number of ReadReq MSHR miss cycles 949system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2160848492 # number of ReadReq MSHR miss cycles 950system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2188282991 # number of ReadReq MSHR miss cycles 951system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21648732719 # number of HardPFReq MSHR miss cycles 952system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21648732719 # number of HardPFReq MSHR miss cycles 953system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 481473058 # number of UpgradeReq MSHR miss cycles 954system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481473058 # number of UpgradeReq MSHR miss cycles 955system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 238593946 # number of SCUpgradeReq MSHR miss cycles 956system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 238593946 # number of SCUpgradeReq MSHR miss cycles 957system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 91000 # number of SCUpgradeFailReq MSHR miss cycles 958system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 91000 # number of SCUpgradeFailReq MSHR miss cycles 959system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1198815233 # number of ReadExReq MSHR miss cycles 960system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1198815233 # number of ReadExReq MSHR miss cycles 961system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of demand (read+write) MSHR miss cycles 962system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2265999 # number of demand (read+write) MSHR miss cycles 963system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3359663725 # number of demand (read+write) MSHR miss cycles 964system.cpu0.l2cache.demand_mshr_miss_latency::total 3387098224 # number of demand (read+write) MSHR miss cycles 965system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of overall MSHR miss cycles 966system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2265999 # number of overall MSHR miss cycles 967system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3359663725 # number of overall MSHR miss cycles 968system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21648732719 # number of overall MSHR miss cycles 969system.cpu0.l2cache.overall_mshr_miss_latency::total 25035830943 # number of overall MSHR miss cycles 970system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6180670251 # number of ReadReq MSHR uncacheable cycles 971system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6180670251 # number of ReadReq MSHR uncacheable cycles 972system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4594924508 # number of WriteReq MSHR uncacheable cycles 973system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4594924508 # number of WriteReq MSHR uncacheable cycles 974system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10775594759 # number of overall MSHR uncacheable cycles 975system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10775594759 # number of overall MSHR uncacheable cycles 976system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for ReadReq accesses 977system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for ReadReq accesses 978system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034144 # mshr miss rate for ReadReq accesses 979system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.033396 # mshr miss rate for ReadReq accesses |
| 979system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 980system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 980system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 981system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 981system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.857849 # mshr miss rate for UpgradeReq accesses 982system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.857849 # mshr miss rate for UpgradeReq accesses 983system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888922 # mshr miss rate for SCUpgradeReq accesses 984system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888922 # mshr miss rate for SCUpgradeReq accesses 985system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 986system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 987system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160439 # mshr miss rate for ReadExReq accesses 988system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160439 # mshr miss rate for ReadExReq accesses 989system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for demand accesses 990system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for demand accesses 991system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for demand accesses 992system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046153 # mshr miss rate for demand accesses 993system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for overall accesses 994system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for overall accesses 995system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for overall accesses | 982system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856775 # mshr miss rate for UpgradeReq accesses 983system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856775 # mshr miss rate for UpgradeReq accesses 984system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.881465 # mshr miss rate for SCUpgradeReq accesses 985system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.881465 # mshr miss rate for SCUpgradeReq accesses 986system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.154795 # mshr miss rate for ReadExReq accesses 987system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154795 # mshr miss rate for ReadExReq accesses 988system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for demand accesses 989system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for demand accesses 990system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for demand accesses 991system.cpu0.l2cache.demand_mshr_miss_rate::total 0.044889 # mshr miss rate for demand accesses 992system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for overall accesses 993system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for overall accesses 994system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for overall accesses |
| 996system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 995system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 997system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226671 # mshr miss rate for overall accesses 998system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average ReadReq mshr miss latency 999system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average ReadReq mshr miss latency 1000system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24503.941556 # average ReadReq mshr miss latency 1001system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24499.196485 # average ReadReq mshr miss latency 1002system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average HardPFReq mshr miss latency 1003system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41646.576259 # average HardPFReq mshr miss latency 1004system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17039.541033 # average UpgradeReq mshr miss latency 1005system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17039.541033 # average UpgradeReq mshr miss latency 1006system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13222.799254 # average SCUpgradeReq mshr miss latency 1007system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13222.799254 # average SCUpgradeReq mshr miss latency 1008system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 44500 # average SCUpgradeFailReq mshr miss latency 1009system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 44500 # average SCUpgradeFailReq mshr miss latency 1010system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27509.077572 # average ReadExReq mshr miss latency 1011system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27509.077572 # average ReadExReq mshr miss latency 1012system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency 1013system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency 1014system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency 1015system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25492.815284 # average overall mshr miss latency 1016system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency 1017system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency 1018system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency 1019system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average overall mshr miss latency 1020system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38357.472316 # average overall mshr miss latency | 996system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225125 # mshr miss rate for overall accesses 997system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average ReadReq mshr miss latency 998system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average ReadReq mshr miss latency 999system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24365.159010 # average ReadReq mshr miss latency 1000system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24387.417709 # average ReadReq mshr miss latency 1001system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average HardPFReq mshr miss latency 1002system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40472.031944 # average HardPFReq mshr miss latency 1003system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17220.066452 # average UpgradeReq mshr miss latency 1004system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17220.066452 # average UpgradeReq mshr miss latency 1005system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13307.710748 # average SCUpgradeReq mshr miss latency 1006system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13307.710748 # average SCUpgradeReq mshr miss latency 1007system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency 1008system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1009system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27564.673910 # average ReadExReq mshr miss latency 1010system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27564.673910 # average ReadExReq mshr miss latency 1011system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency 1012system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency 1013system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency 1014system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25424.656953 # average overall mshr miss latency 1015system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency 1016system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency 1017system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency 1018system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average overall mshr miss latency 1019system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37471.664733 # average overall mshr miss latency |
| 1021system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1022system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1023system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1024system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1025system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1026system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1027system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1020system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1021system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1022system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1023system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1024system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1025system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1026system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1028system.cpu0.toL2Bus.trans_dist::ReadReq 2765429 # Transaction distribution 1029system.cpu0.toL2Bus.trans_dist::ReadResp 2670282 # Transaction distribution 1030system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution 1031system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution 1032system.cpu0.toL2Bus.trans_dist::Writeback 517951 # Transaction distribution 1033system.cpu0.toL2Bus.trans_dist::HardPFReq 696439 # Transaction distribution 1034system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 1035system.cpu0.toL2Bus.trans_dist::UpgradeReq 70465 # Transaction distribution 1036system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42615 # Transaction distribution 1037system.cpu0.toL2Bus.trans_dist::UpgradeResp 93717 # Transaction distribution 1038system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 1039system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution 1040system.cpu0.toL2Bus.trans_dist::ReadExReq 291656 # Transaction distribution 1041system.cpu0.toL2Bus.trans_dist::ReadExResp 282057 # Transaction distribution 1042system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3974309 # Packet count per connected master and slave (bytes) 1043system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393187 # Packet count per connected master and slave (bytes) 1044system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11845 # Packet count per connected master and slave (bytes) 1045system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168040 # Packet count per connected master and slave (bytes) 1046system.cpu0.toL2Bus.pkt_count::total 6547381 # Packet count per connected master and slave (bytes) 1047system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127177856 # Cumulative packet size per connected master and slave (bytes) 1048system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86874167 # Cumulative packet size per connected master and slave (bytes) 1049system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17764 # Cumulative packet size per connected master and slave (bytes) 1050system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 315068 # Cumulative packet size per connected master and slave (bytes) 1051system.cpu0.toL2Bus.pkt_size::total 214384855 # Cumulative packet size per connected master and slave (bytes) 1052system.cpu0.toL2Bus.snoops 1083965 # Total snoops (count) 1053system.cpu0.toL2Bus.snoop_fanout::samples 4385734 # Request fanout histogram 1054system.cpu0.toL2Bus.snoop_fanout::mean 5.219720 # Request fanout histogram 1055system.cpu0.toL2Bus.snoop_fanout::stdev 0.414057 # Request fanout histogram | 1027system.cpu0.toL2Bus.trans_dist::ReadReq 2861093 # Transaction distribution 1028system.cpu0.toL2Bus.trans_dist::ReadResp 2792980 # Transaction distribution 1029system.cpu0.toL2Bus.trans_dist::WriteReq 28855 # Transaction distribution 1030system.cpu0.toL2Bus.trans_dist::WriteResp 28855 # Transaction distribution 1031system.cpu0.toL2Bus.trans_dist::Writeback 541643 # Transaction distribution 1032system.cpu0.toL2Bus.trans_dist::HardPFReq 731101 # Transaction distribution 1033system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1034system.cpu0.toL2Bus.trans_dist::UpgradeReq 68486 # Transaction distribution 1035system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42622 # Transaction distribution 1036system.cpu0.toL2Bus.trans_dist::UpgradeResp 93982 # Transaction distribution 1037system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 1038system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution 1039system.cpu0.toL2Bus.trans_dist::ReadExReq 302729 # Transaction distribution 1040system.cpu0.toL2Bus.trans_dist::ReadExResp 293421 # Transaction distribution 1041system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 4148051 # Packet count per connected master and slave (bytes) 1042system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2491359 # Packet count per connected master and slave (bytes) 1043system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12339 # Packet count per connected master and slave (bytes) 1044system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 183942 # Packet count per connected master and slave (bytes) 1045system.cpu0.toL2Bus.pkt_count::total 6835691 # Packet count per connected master and slave (bytes) 1046system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 132737600 # Cumulative packet size per connected master and slave (bytes) 1047system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90757533 # Cumulative packet size per connected master and slave (bytes) 1048system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17524 # Cumulative packet size per connected master and slave (bytes) 1049system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 340220 # Cumulative packet size per connected master and slave (bytes) 1050system.cpu0.toL2Bus.pkt_size::total 223852877 # Cumulative packet size per connected master and slave (bytes) 1051system.cpu0.toL2Bus.snoops 1093341 # Total snoops (count) 1052system.cpu0.toL2Bus.snoop_fanout::samples 4548807 # Request fanout histogram 1053system.cpu0.toL2Bus.snoop_fanout::mean 5.213001 # Request fanout histogram 1054system.cpu0.toL2Bus.snoop_fanout::stdev 0.409428 # Request fanout histogram |
| 1056system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1057system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1058system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1059system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1060system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1061system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1055system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1056system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1057system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1058system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1059system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1060system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1062system.cpu0.toL2Bus.snoop_fanout::5 3422100 78.03% 78.03% # Request fanout histogram 1063system.cpu0.toL2Bus.snoop_fanout::6 963634 21.97% 100.00% # Request fanout histogram | 1061system.cpu0.toL2Bus.snoop_fanout::5 3579907 78.70% 78.70% # Request fanout histogram 1062system.cpu0.toL2Bus.snoop_fanout::6 968900 21.30% 100.00% # Request fanout histogram |
| 1064system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1065system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1066system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1063system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1064system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1065system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1067system.cpu0.toL2Bus.snoop_fanout::total 4385734 # Request fanout histogram 1068system.cpu0.toL2Bus.reqLayer0.occupancy 2275890990 # Layer occupancy (ticks) | 1066system.cpu0.toL2Bus.snoop_fanout::total 4548807 # Request fanout histogram 1067system.cpu0.toL2Bus.reqLayer0.occupancy 2378574445 # Layer occupancy (ticks) |
| 1069system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1068system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1070system.cpu0.toL2Bus.snoopLayer0.occupancy 119346000 # Layer occupancy (ticks) | 1069system.cpu0.toL2Bus.snoopLayer0.occupancy 119537998 # Layer occupancy (ticks) |
| 1071system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1070system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1072system.cpu0.toL2Bus.respLayer0.occupancy 2982392646 # Layer occupancy (ticks) | 1071system.cpu0.toL2Bus.respLayer0.occupancy 3112636730 # Layer occupancy (ticks) |
| 1073system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1072system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1074system.cpu0.toL2Bus.respLayer1.occupancy 1235371968 # Layer occupancy (ticks) | 1073system.cpu0.toL2Bus.respLayer1.occupancy 1291088389 # Layer occupancy (ticks) |
| 1075system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1074system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1076system.cpu0.toL2Bus.respLayer2.occupancy 7407493 # Layer occupancy (ticks) | 1075system.cpu0.toL2Bus.respLayer2.occupancy 7963988 # Layer occupancy (ticks) |
| 1077system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1076system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1078system.cpu0.toL2Bus.respLayer3.occupancy 89292476 # Layer occupancy (ticks) | 1077system.cpu0.toL2Bus.respLayer3.occupancy 98908477 # Layer occupancy (ticks) |
| 1079system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1078system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1080system.cpu1.branchPred.lookups 4040174 # Number of BP lookups 1081system.cpu1.branchPred.condPredicted 2339682 # Number of conditional branches predicted 1082system.cpu1.branchPred.condIncorrect 248924 # Number of conditional branches incorrect 1083system.cpu1.branchPred.BTBLookups 2652147 # Number of BTB lookups 1084system.cpu1.branchPred.BTBHits 1629183 # Number of BTB hits | 1079system.cpu1.branchPred.lookups 3448752 # Number of BP lookups 1080system.cpu1.branchPred.condPredicted 1941981 # Number of conditional branches predicted 1081system.cpu1.branchPred.condIncorrect 196391 # Number of conditional branches incorrect 1082system.cpu1.branchPred.BTBLookups 2221819 # Number of BTB lookups 1083system.cpu1.branchPred.BTBHits 1396869 # Number of BTB hits |
| 1085system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1084system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1086system.cpu1.branchPred.BTBHitPct 61.428835 # BTB Hit Percentage 1087system.cpu1.branchPred.usedRAS 794888 # Number of times the RAS was used to get a target. 1088system.cpu1.branchPred.RASInCorrect 55483 # Number of incorrect RAS predictions. | 1085system.cpu1.branchPred.BTBHitPct 62.870513 # BTB Hit Percentage 1086system.cpu1.branchPred.usedRAS 715789 # Number of times the RAS was used to get a target. 1087system.cpu1.branchPred.RASInCorrect 52420 # Number of incorrect RAS predictions. |
| 1089system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1090system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1091system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1092system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1093system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1094system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1095system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1096system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1104system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1105system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1106system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1107system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1108system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1109system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1110system.cpu1.dtb.inst_hits 0 # ITB inst hits 1111system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1088system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1089system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1090system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1091system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1092system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1093system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1094system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1095system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1103system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1104system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1105system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1106system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1107system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1108system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1109system.cpu1.dtb.inst_hits 0 # ITB inst hits 1110system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1112system.cpu1.dtb.read_hits 4061400 # DTB read hits 1113system.cpu1.dtb.read_misses 20326 # DTB read misses 1114system.cpu1.dtb.write_hits 3327397 # DTB write hits 1115system.cpu1.dtb.write_misses 1493 # DTB write misses | 1111system.cpu1.dtb.read_hits 3432223 # DTB read hits 1112system.cpu1.dtb.read_misses 19764 # DTB read misses 1113system.cpu1.dtb.write_hits 2826731 # DTB write hits 1114system.cpu1.dtb.write_misses 1392 # DTB write misses |
| 1116system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1117system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1118system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1119system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1115system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1116system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1117system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1118system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1120system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB 1121system.cpu1.dtb.align_faults 130 # Number of TLB faults due to alignment restrictions 1122system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch | 1119system.cpu1.dtb.flush_entries 1674 # Number of entries that have been flushed from TLB 1120system.cpu1.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions 1121system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch |
| 1123system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1122system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1124system.cpu1.dtb.perms_faults 275 # Number of TLB faults due to permissions restrictions 1125system.cpu1.dtb.read_accesses 4081726 # DTB read accesses 1126system.cpu1.dtb.write_accesses 3328890 # DTB write accesses | 1123system.cpu1.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions 1124system.cpu1.dtb.read_accesses 3451987 # DTB read accesses 1125system.cpu1.dtb.write_accesses 2828123 # DTB write accesses |
| 1127system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1126system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1128system.cpu1.dtb.hits 7388797 # DTB hits 1129system.cpu1.dtb.misses 21819 # DTB misses 1130system.cpu1.dtb.accesses 7410616 # DTB accesses | 1127system.cpu1.dtb.hits 6258954 # DTB hits 1128system.cpu1.dtb.misses 21156 # DTB misses 1129system.cpu1.dtb.accesses 6280110 # DTB accesses |
| 1131system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1132system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1133system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1134system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1135system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1136system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1137system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1138system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1144system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1145system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1146system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1147system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1148system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1149system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1150system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1151system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1130system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1131system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1132system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1133system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1134system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1135system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1136system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1137system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1143system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1144system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1145system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1146system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1147system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1148system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1149system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1150system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1152system.cpu1.itb.inst_hits 7665717 # ITB inst hits 1153system.cpu1.itb.inst_misses 2240 # ITB inst misses | 1151system.cpu1.itb.inst_hits 6653879 # ITB inst hits 1152system.cpu1.itb.inst_misses 1856 # ITB inst misses |
| 1154system.cpu1.itb.read_hits 0 # DTB read hits 1155system.cpu1.itb.read_misses 0 # DTB read misses 1156system.cpu1.itb.write_hits 0 # DTB write hits 1157system.cpu1.itb.write_misses 0 # DTB write misses 1158system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1159system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1160system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1161system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1153system.cpu1.itb.read_hits 0 # DTB read hits 1154system.cpu1.itb.read_misses 0 # DTB read misses 1155system.cpu1.itb.write_hits 0 # DTB write hits 1156system.cpu1.itb.write_misses 0 # DTB write misses 1157system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1158system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1159system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1160system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1162system.cpu1.itb.flush_entries 1155 # Number of entries that have been flushed from TLB | 1161system.cpu1.itb.flush_entries 882 # Number of entries that have been flushed from TLB |
| 1163system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1164system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1165system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1162system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1163system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1164system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1166system.cpu1.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions | 1165system.cpu1.itb.perms_faults 1128 # Number of TLB faults due to permissions restrictions |
| 1167system.cpu1.itb.read_accesses 0 # DTB read accesses 1168system.cpu1.itb.write_accesses 0 # DTB write accesses | 1166system.cpu1.itb.read_accesses 0 # DTB read accesses 1167system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1169system.cpu1.itb.inst_accesses 7667957 # ITB inst accesses 1170system.cpu1.itb.hits 7665717 # DTB hits 1171system.cpu1.itb.misses 2240 # DTB misses 1172system.cpu1.itb.accesses 7667957 # DTB accesses 1173system.cpu1.numCycles 40520229 # number of cpu cycles simulated | 1168system.cpu1.itb.inst_accesses 6655735 # ITB inst accesses 1169system.cpu1.itb.hits 6653879 # DTB hits 1170system.cpu1.itb.misses 1856 # DTB misses 1171system.cpu1.itb.accesses 6655735 # DTB accesses 1172system.cpu1.numCycles 36145472 # number of cpu cycles simulated |
| 1174system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1175system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1173system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1174system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1176system.cpu1.committedInsts 15863154 # Number of instructions committed 1177system.cpu1.committedOps 19391289 # Number of ops (including micro ops) committed 1178system.cpu1.discardedOps 1555006 # Number of ops (including micro ops) which were discarded before commit 1179system.cpu1.numFetchSuspends 2808 # Number of times Execute suspended instruction fetching 1180system.cpu1.quiesceCycles 5646190749 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1181system.cpu1.cpi 2.554361 # CPI: cycles per instruction 1182system.cpu1.ipc 0.391487 # IPC: instructions per cycle | 1175system.cpu1.committedInsts 13424165 # Number of instructions committed 1176system.cpu1.committedOps 16401555 # Number of ops (including micro ops) committed 1177system.cpu1.discardedOps 1287407 # Number of ops (including micro ops) which were discarded before commit 1178system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching 1179system.cpu1.quiesceCycles 5652095397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1180system.cpu1.cpi 2.692568 # CPI: cycles per instruction 1181system.cpu1.ipc 0.371393 # IPC: instructions per cycle |
| 1183system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1182system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1184system.cpu1.kern.inst.quiesce 2810 # number of quiesce instructions executed 1185system.cpu1.tickCycles 29462484 # Number of cycles that the object actually ticked 1186system.cpu1.idleCycles 11057745 # Total number of cycles that the object has spent stopped 1187system.cpu1.dcache.tags.replacements 188500 # number of replacements 1188system.cpu1.dcache.tags.tagsinuse 474.724355 # Cycle average of tags in use 1189system.cpu1.dcache.tags.total_refs 6998456 # Total number of references to valid blocks. 1190system.cpu1.dcache.tags.sampled_refs 188865 # Sample count of references to valid blocks. 1191system.cpu1.dcache.tags.avg_refs 37.055336 # Average number of references to valid blocks. 1192system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit. 1193system.cpu1.dcache.tags.occ_blocks::cpu1.inst 474.724355 # Average occupied blocks per requestor 1194system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927196 # Average percentage of cache occupancy 1195system.cpu1.dcache.tags.occ_percent::total 0.927196 # Average percentage of cache occupancy 1196system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 1197system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id 1198system.cpu1.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id 1199system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id 1200system.cpu1.dcache.tags.tag_accesses 14854828 # Number of tag accesses 1201system.cpu1.dcache.tags.data_accesses 14854828 # Number of data accesses 1202system.cpu1.dcache.ReadReq_hits::cpu1.inst 3752021 # number of ReadReq hits 1203system.cpu1.dcache.ReadReq_hits::total 3752021 # number of ReadReq hits 1204system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051608 # number of WriteReq hits 1205system.cpu1.dcache.WriteReq_hits::total 3051608 # number of WriteReq hits 1206system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88860 # number of LoadLockedReq hits 1207system.cpu1.dcache.LoadLockedReq_hits::total 88860 # number of LoadLockedReq hits 1208system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69213 # number of StoreCondReq hits 1209system.cpu1.dcache.StoreCondReq_hits::total 69213 # number of StoreCondReq hits 1210system.cpu1.dcache.demand_hits::cpu1.inst 6803629 # number of demand (read+write) hits 1211system.cpu1.dcache.demand_hits::total 6803629 # number of demand (read+write) hits 1212system.cpu1.dcache.overall_hits::cpu1.inst 6803629 # number of overall hits 1213system.cpu1.dcache.overall_hits::total 6803629 # number of overall hits 1214system.cpu1.dcache.ReadReq_misses::cpu1.inst 182037 # number of ReadReq misses 1215system.cpu1.dcache.ReadReq_misses::total 182037 # number of ReadReq misses 1216system.cpu1.dcache.WriteReq_misses::cpu1.inst 139457 # number of WriteReq misses 1217system.cpu1.dcache.WriteReq_misses::total 139457 # number of WriteReq misses 1218system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5164 # number of LoadLockedReq misses 1219system.cpu1.dcache.LoadLockedReq_misses::total 5164 # number of LoadLockedReq misses 1220system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23160 # number of StoreCondReq misses 1221system.cpu1.dcache.StoreCondReq_misses::total 23160 # number of StoreCondReq misses 1222system.cpu1.dcache.demand_misses::cpu1.inst 321494 # number of demand (read+write) misses 1223system.cpu1.dcache.demand_misses::total 321494 # number of demand (read+write) misses 1224system.cpu1.dcache.overall_misses::cpu1.inst 321494 # number of overall misses 1225system.cpu1.dcache.overall_misses::total 321494 # number of overall misses 1226system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2747896424 # number of ReadReq miss cycles 1227system.cpu1.dcache.ReadReq_miss_latency::total 2747896424 # number of ReadReq miss cycles 1228system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3339347493 # number of WriteReq miss cycles 1229system.cpu1.dcache.WriteReq_miss_latency::total 3339347493 # number of WriteReq miss cycles 1230system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93721501 # number of LoadLockedReq miss cycles 1231system.cpu1.dcache.LoadLockedReq_miss_latency::total 93721501 # number of LoadLockedReq miss cycles 1232system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540094758 # number of StoreCondReq miss cycles 1233system.cpu1.dcache.StoreCondReq_miss_latency::total 540094758 # number of StoreCondReq miss cycles 1234system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 317500 # number of StoreCondFailReq miss cycles 1235system.cpu1.dcache.StoreCondFailReq_miss_latency::total 317500 # number of StoreCondFailReq miss cycles 1236system.cpu1.dcache.demand_miss_latency::cpu1.inst 6087243917 # number of demand (read+write) miss cycles 1237system.cpu1.dcache.demand_miss_latency::total 6087243917 # number of demand (read+write) miss cycles 1238system.cpu1.dcache.overall_miss_latency::cpu1.inst 6087243917 # number of overall miss cycles 1239system.cpu1.dcache.overall_miss_latency::total 6087243917 # number of overall miss cycles 1240system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3934058 # number of ReadReq accesses(hits+misses) 1241system.cpu1.dcache.ReadReq_accesses::total 3934058 # number of ReadReq accesses(hits+misses) 1242system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3191065 # number of WriteReq accesses(hits+misses) 1243system.cpu1.dcache.WriteReq_accesses::total 3191065 # number of WriteReq accesses(hits+misses) 1244system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94024 # number of LoadLockedReq accesses(hits+misses) 1245system.cpu1.dcache.LoadLockedReq_accesses::total 94024 # number of LoadLockedReq accesses(hits+misses) 1246system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92373 # number of StoreCondReq accesses(hits+misses) 1247system.cpu1.dcache.StoreCondReq_accesses::total 92373 # number of StoreCondReq accesses(hits+misses) 1248system.cpu1.dcache.demand_accesses::cpu1.inst 7125123 # number of demand (read+write) accesses 1249system.cpu1.dcache.demand_accesses::total 7125123 # number of demand (read+write) accesses 1250system.cpu1.dcache.overall_accesses::cpu1.inst 7125123 # number of overall (read+write) accesses 1251system.cpu1.dcache.overall_accesses::total 7125123 # number of overall (read+write) accesses 1252system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046272 # miss rate for ReadReq accesses 1253system.cpu1.dcache.ReadReq_miss_rate::total 0.046272 # miss rate for ReadReq accesses 1254system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043702 # miss rate for WriteReq accesses 1255system.cpu1.dcache.WriteReq_miss_rate::total 0.043702 # miss rate for WriteReq accesses 1256system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054922 # miss rate for LoadLockedReq accesses 1257system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054922 # miss rate for LoadLockedReq accesses 1258system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250723 # miss rate for StoreCondReq accesses 1259system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250723 # miss rate for StoreCondReq accesses 1260system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045121 # miss rate for demand accesses 1261system.cpu1.dcache.demand_miss_rate::total 0.045121 # miss rate for demand accesses 1262system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045121 # miss rate for overall accesses 1263system.cpu1.dcache.overall_miss_rate::total 0.045121 # miss rate for overall accesses 1264system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15095.263183 # average ReadReq miss latency 1265system.cpu1.dcache.ReadReq_avg_miss_latency::total 15095.263183 # average ReadReq miss latency 1266system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23945.355866 # average WriteReq miss latency 1267system.cpu1.dcache.WriteReq_avg_miss_latency::total 23945.355866 # average WriteReq miss latency 1268system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18149.012587 # average LoadLockedReq miss latency 1269system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18149.012587 # average LoadLockedReq miss latency 1270system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23320.153627 # average StoreCondReq miss latency 1271system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23320.153627 # average StoreCondReq miss latency | 1183system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed 1184system.cpu1.tickCycles 26236459 # Number of cycles that the object actually ticked 1185system.cpu1.idleCycles 9909013 # Total number of cycles that the object has spent stopped 1186system.cpu1.dcache.tags.replacements 149765 # number of replacements 1187system.cpu1.dcache.tags.tagsinuse 476.829408 # Cycle average of tags in use 1188system.cpu1.dcache.tags.total_refs 5935391 # Total number of references to valid blocks. 1189system.cpu1.dcache.tags.sampled_refs 150124 # Sample count of references to valid blocks. 1190system.cpu1.dcache.tags.avg_refs 39.536590 # Average number of references to valid blocks. 1191system.cpu1.dcache.tags.warmup_cycle 107725830000 # Cycle when the warmup percentage was hit. 1192system.cpu1.dcache.tags.occ_blocks::cpu1.inst 476.829408 # Average occupied blocks per requestor 1193system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.931307 # Average percentage of cache occupancy 1194system.cpu1.dcache.tags.occ_percent::total 0.931307 # Average percentage of cache occupancy 1195system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id 1196system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id 1197system.cpu1.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id 1198system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id 1199system.cpu1.dcache.tags.tag_accesses 12574886 # Number of tag accesses 1200system.cpu1.dcache.tags.data_accesses 12574886 # Number of data accesses 1201system.cpu1.dcache.ReadReq_hits::cpu1.inst 3167382 # number of ReadReq hits 1202system.cpu1.dcache.ReadReq_hits::total 3167382 # number of ReadReq hits 1203system.cpu1.dcache.WriteReq_hits::cpu1.inst 2587127 # number of WriteReq hits 1204system.cpu1.dcache.WriteReq_hits::total 2587127 # number of WriteReq hits 1205system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 79870 # number of LoadLockedReq hits 1206system.cpu1.dcache.LoadLockedReq_hits::total 79870 # number of LoadLockedReq hits 1207system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 60510 # number of StoreCondReq hits 1208system.cpu1.dcache.StoreCondReq_hits::total 60510 # number of StoreCondReq hits 1209system.cpu1.dcache.demand_hits::cpu1.inst 5754509 # number of demand (read+write) hits 1210system.cpu1.dcache.demand_hits::total 5754509 # number of demand (read+write) hits 1211system.cpu1.dcache.overall_hits::cpu1.inst 5754509 # number of overall hits 1212system.cpu1.dcache.overall_hits::total 5754509 # number of overall hits 1213system.cpu1.dcache.ReadReq_misses::cpu1.inst 151161 # number of ReadReq misses 1214system.cpu1.dcache.ReadReq_misses::total 151161 # number of ReadReq misses 1215system.cpu1.dcache.WriteReq_misses::cpu1.inst 116953 # number of WriteReq misses 1216system.cpu1.dcache.WriteReq_misses::total 116953 # number of WriteReq misses 1217system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5079 # number of LoadLockedReq misses 1218system.cpu1.dcache.LoadLockedReq_misses::total 5079 # number of LoadLockedReq misses 1219system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 22818 # number of StoreCondReq misses 1220system.cpu1.dcache.StoreCondReq_misses::total 22818 # number of StoreCondReq misses 1221system.cpu1.dcache.demand_misses::cpu1.inst 268114 # number of demand (read+write) misses 1222system.cpu1.dcache.demand_misses::total 268114 # number of demand (read+write) misses 1223system.cpu1.dcache.overall_misses::cpu1.inst 268114 # number of overall misses 1224system.cpu1.dcache.overall_misses::total 268114 # number of overall misses 1225system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2359046468 # number of ReadReq miss cycles 1226system.cpu1.dcache.ReadReq_miss_latency::total 2359046468 # number of ReadReq miss cycles 1227system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3063915205 # number of WriteReq miss cycles 1228system.cpu1.dcache.WriteReq_miss_latency::total 3063915205 # number of WriteReq miss cycles 1229system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93260000 # number of LoadLockedReq miss cycles 1230system.cpu1.dcache.LoadLockedReq_miss_latency::total 93260000 # number of LoadLockedReq miss cycles 1231system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 534664798 # number of StoreCondReq miss cycles 1232system.cpu1.dcache.StoreCondReq_miss_latency::total 534664798 # number of StoreCondReq miss cycles 1233system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 106500 # number of StoreCondFailReq miss cycles 1234system.cpu1.dcache.StoreCondFailReq_miss_latency::total 106500 # number of StoreCondFailReq miss cycles 1235system.cpu1.dcache.demand_miss_latency::cpu1.inst 5422961673 # number of demand (read+write) miss cycles 1236system.cpu1.dcache.demand_miss_latency::total 5422961673 # number of demand (read+write) miss cycles 1237system.cpu1.dcache.overall_miss_latency::cpu1.inst 5422961673 # number of overall miss cycles 1238system.cpu1.dcache.overall_miss_latency::total 5422961673 # number of overall miss cycles 1239system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3318543 # number of ReadReq accesses(hits+misses) 1240system.cpu1.dcache.ReadReq_accesses::total 3318543 # number of ReadReq accesses(hits+misses) 1241system.cpu1.dcache.WriteReq_accesses::cpu1.inst 2704080 # number of WriteReq accesses(hits+misses) 1242system.cpu1.dcache.WriteReq_accesses::total 2704080 # number of WriteReq accesses(hits+misses) 1243system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 84949 # number of LoadLockedReq accesses(hits+misses) 1244system.cpu1.dcache.LoadLockedReq_accesses::total 84949 # number of LoadLockedReq accesses(hits+misses) 1245system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 83328 # number of StoreCondReq accesses(hits+misses) 1246system.cpu1.dcache.StoreCondReq_accesses::total 83328 # number of StoreCondReq accesses(hits+misses) 1247system.cpu1.dcache.demand_accesses::cpu1.inst 6022623 # number of demand (read+write) accesses 1248system.cpu1.dcache.demand_accesses::total 6022623 # number of demand (read+write) accesses 1249system.cpu1.dcache.overall_accesses::cpu1.inst 6022623 # number of overall (read+write) accesses 1250system.cpu1.dcache.overall_accesses::total 6022623 # number of overall (read+write) accesses 1251system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045550 # miss rate for ReadReq accesses 1252system.cpu1.dcache.ReadReq_miss_rate::total 0.045550 # miss rate for ReadReq accesses 1253system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043251 # miss rate for WriteReq accesses 1254system.cpu1.dcache.WriteReq_miss_rate::total 0.043251 # miss rate for WriteReq accesses 1255system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.059789 # miss rate for LoadLockedReq accesses 1256system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.059789 # miss rate for LoadLockedReq accesses 1257system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.273834 # miss rate for StoreCondReq accesses 1258system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273834 # miss rate for StoreCondReq accesses 1259system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044518 # miss rate for demand accesses 1260system.cpu1.dcache.demand_miss_rate::total 0.044518 # miss rate for demand accesses 1261system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044518 # miss rate for overall accesses 1262system.cpu1.dcache.overall_miss_rate::total 0.044518 # miss rate for overall accesses 1263system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15606.184585 # average ReadReq miss latency 1264system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.184585 # average ReadReq miss latency 1265system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26197.833360 # average WriteReq miss latency 1266system.cpu1.dcache.WriteReq_avg_miss_latency::total 26197.833360 # average WriteReq miss latency 1267system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18361.882260 # average LoadLockedReq miss latency 1268system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18361.882260 # average LoadLockedReq miss latency 1269system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23431.711719 # average StoreCondReq miss latency 1270system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.711719 # average StoreCondReq miss latency |
| 1272system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 1273system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1271system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 1272system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1274system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency 1275system.cpu1.dcache.demand_avg_miss_latency::total 18934.238017 # average overall miss latency 1276system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency 1277system.cpu1.dcache.overall_avg_miss_latency::total 18934.238017 # average overall miss latency | 1273system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency 1274system.cpu1.dcache.demand_avg_miss_latency::total 20226.327879 # average overall miss latency 1275system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency 1276system.cpu1.dcache.overall_avg_miss_latency::total 20226.327879 # average overall miss latency |
| 1278system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1279system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1280system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1281system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1282system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1283system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1284system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1285system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1277system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1278system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1279system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1280system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1281system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1282system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1283system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1284system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1286system.cpu1.dcache.writebacks::writebacks 115754 # number of writebacks 1287system.cpu1.dcache.writebacks::total 115754 # number of writebacks 1288system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15456 # number of ReadReq MSHR hits 1289system.cpu1.dcache.ReadReq_mshr_hits::total 15456 # number of ReadReq MSHR hits 1290system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49471 # number of WriteReq MSHR hits 1291system.cpu1.dcache.WriteReq_mshr_hits::total 49471 # number of WriteReq MSHR hits 1292system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64927 # number of demand (read+write) MSHR hits 1293system.cpu1.dcache.demand_mshr_hits::total 64927 # number of demand (read+write) MSHR hits 1294system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64927 # number of overall MSHR hits 1295system.cpu1.dcache.overall_mshr_hits::total 64927 # number of overall MSHR hits 1296system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166581 # number of ReadReq MSHR misses 1297system.cpu1.dcache.ReadReq_mshr_misses::total 166581 # number of ReadReq MSHR misses 1298system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89986 # number of WriteReq MSHR misses 1299system.cpu1.dcache.WriteReq_mshr_misses::total 89986 # number of WriteReq MSHR misses 1300system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5164 # number of LoadLockedReq MSHR misses 1301system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5164 # number of LoadLockedReq MSHR misses 1302system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23160 # number of StoreCondReq MSHR misses 1303system.cpu1.dcache.StoreCondReq_mshr_misses::total 23160 # number of StoreCondReq MSHR misses 1304system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256567 # number of demand (read+write) MSHR misses 1305system.cpu1.dcache.demand_mshr_misses::total 256567 # number of demand (read+write) MSHR misses 1306system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256567 # number of overall MSHR misses 1307system.cpu1.dcache.overall_mshr_misses::total 256567 # number of overall MSHR misses 1308system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204876516 # number of ReadReq MSHR miss cycles 1309system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204876516 # number of ReadReq MSHR miss cycles 1310system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1996537354 # number of WriteReq MSHR miss cycles 1311system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1996537354 # number of WriteReq MSHR miss cycles 1312system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83385499 # number of LoadLockedReq MSHR miss cycles 1313system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83385499 # number of LoadLockedReq MSHR miss cycles 1314system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492548242 # number of StoreCondReq MSHR miss cycles 1315system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492548242 # number of StoreCondReq MSHR miss cycles 1316system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 303500 # number of StoreCondFailReq MSHR miss cycles 1317system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 303500 # number of StoreCondFailReq MSHR miss cycles 1318system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4201413870 # number of demand (read+write) MSHR miss cycles 1319system.cpu1.dcache.demand_mshr_miss_latency::total 4201413870 # number of demand (read+write) MSHR miss cycles 1320system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4201413870 # number of overall MSHR miss cycles 1321system.cpu1.dcache.overall_mshr_miss_latency::total 4201413870 # number of overall MSHR miss cycles 1322system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329634997 # number of ReadReq MSHR uncacheable cycles 1323system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329634997 # number of ReadReq MSHR uncacheable cycles 1324system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202961999 # number of WriteReq MSHR uncacheable cycles 1325system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202961999 # number of WriteReq MSHR uncacheable cycles 1326system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532596996 # number of overall MSHR uncacheable cycles 1327system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532596996 # number of overall MSHR uncacheable cycles 1328system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042343 # mshr miss rate for ReadReq accesses 1329system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042343 # mshr miss rate for ReadReq accesses 1330system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028199 # mshr miss rate for WriteReq accesses 1331system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028199 # mshr miss rate for WriteReq accesses 1332system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054922 # mshr miss rate for LoadLockedReq accesses 1333system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054922 # mshr miss rate for LoadLockedReq accesses 1334system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250723 # mshr miss rate for StoreCondReq accesses 1335system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250723 # mshr miss rate for StoreCondReq accesses 1336system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for demand accesses 1337system.cpu1.dcache.demand_mshr_miss_rate::total 0.036009 # mshr miss rate for demand accesses 1338system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for overall accesses 1339system.cpu1.dcache.overall_mshr_miss_rate::total 0.036009 # mshr miss rate for overall accesses 1340system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13236.062432 # average ReadReq mshr miss latency 1341system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13236.062432 # average ReadReq mshr miss latency 1342system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22187.199720 # average WriteReq mshr miss latency 1343system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22187.199720 # average WriteReq mshr miss latency 1344system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16147.463013 # average LoadLockedReq mshr miss latency 1345system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.463013 # average LoadLockedReq mshr miss latency 1346system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21267.195250 # average StoreCondReq mshr miss latency 1347system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21267.195250 # average StoreCondReq mshr miss latency | 1285system.cpu1.dcache.writebacks::writebacks 93707 # number of writebacks 1286system.cpu1.dcache.writebacks::total 93707 # number of writebacks 1287system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 11593 # number of ReadReq MSHR hits 1288system.cpu1.dcache.ReadReq_mshr_hits::total 11593 # number of ReadReq MSHR hits 1289system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 39187 # number of WriteReq MSHR hits 1290system.cpu1.dcache.WriteReq_mshr_hits::total 39187 # number of WriteReq MSHR hits 1291system.cpu1.dcache.demand_mshr_hits::cpu1.inst 50780 # number of demand (read+write) MSHR hits 1292system.cpu1.dcache.demand_mshr_hits::total 50780 # number of demand (read+write) MSHR hits 1293system.cpu1.dcache.overall_mshr_hits::cpu1.inst 50780 # number of overall MSHR hits 1294system.cpu1.dcache.overall_mshr_hits::total 50780 # number of overall MSHR hits 1295system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 139568 # number of ReadReq MSHR misses 1296system.cpu1.dcache.ReadReq_mshr_misses::total 139568 # number of ReadReq MSHR misses 1297system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 77766 # number of WriteReq MSHR misses 1298system.cpu1.dcache.WriteReq_mshr_misses::total 77766 # number of WriteReq MSHR misses 1299system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5079 # number of LoadLockedReq MSHR misses 1300system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5079 # number of LoadLockedReq MSHR misses 1301system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 22818 # number of StoreCondReq MSHR misses 1302system.cpu1.dcache.StoreCondReq_mshr_misses::total 22818 # number of StoreCondReq MSHR misses 1303system.cpu1.dcache.demand_mshr_misses::cpu1.inst 217334 # number of demand (read+write) MSHR misses 1304system.cpu1.dcache.demand_mshr_misses::total 217334 # number of demand (read+write) MSHR misses 1305system.cpu1.dcache.overall_mshr_misses::cpu1.inst 217334 # number of overall MSHR misses 1306system.cpu1.dcache.overall_mshr_misses::total 217334 # number of overall MSHR misses 1307system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 1914681986 # number of ReadReq MSHR miss cycles 1308system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914681986 # number of ReadReq MSHR miss cycles 1309system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1867013423 # number of WriteReq MSHR miss cycles 1310system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1867013423 # number of WriteReq MSHR miss cycles 1311system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83091000 # number of LoadLockedReq MSHR miss cycles 1312system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83091000 # number of LoadLockedReq MSHR miss cycles 1313system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 487833202 # number of StoreCondReq MSHR miss cycles 1314system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 487833202 # number of StoreCondReq MSHR miss cycles 1315system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 100500 # number of StoreCondFailReq MSHR miss cycles 1316system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 100500 # number of StoreCondFailReq MSHR miss cycles 1317system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 3781695409 # number of demand (read+write) MSHR miss cycles 1318system.cpu1.dcache.demand_mshr_miss_latency::total 3781695409 # number of demand (read+write) MSHR miss cycles 1319system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 3781695409 # number of overall MSHR miss cycles 1320system.cpu1.dcache.overall_mshr_miss_latency::total 3781695409 # number of overall MSHR miss cycles 1321system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 327471996 # number of ReadReq MSHR uncacheable cycles 1322system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 327471996 # number of ReadReq MSHR uncacheable cycles 1323system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 198424999 # number of WriteReq MSHR uncacheable cycles 1324system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 198424999 # number of WriteReq MSHR uncacheable cycles 1325system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 525896995 # number of overall MSHR uncacheable cycles 1326system.cpu1.dcache.overall_mshr_uncacheable_latency::total 525896995 # number of overall MSHR uncacheable cycles 1327system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042057 # mshr miss rate for ReadReq accesses 1328system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042057 # mshr miss rate for ReadReq accesses 1329system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028759 # mshr miss rate for WriteReq accesses 1330system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028759 # mshr miss rate for WriteReq accesses 1331system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.059789 # mshr miss rate for LoadLockedReq accesses 1332system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059789 # mshr miss rate for LoadLockedReq accesses 1333system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.273834 # mshr miss rate for StoreCondReq accesses 1334system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273834 # mshr miss rate for StoreCondReq accesses 1335system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for demand accesses 1336system.cpu1.dcache.demand_mshr_miss_rate::total 0.036086 # mshr miss rate for demand accesses 1337system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for overall accesses 1338system.cpu1.dcache.overall_mshr_miss_rate::total 0.036086 # mshr miss rate for overall accesses 1339system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13718.631678 # average ReadReq mshr miss latency 1340system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13718.631678 # average ReadReq mshr miss latency 1341system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24008.093807 # average WriteReq mshr miss latency 1342system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24008.093807 # average WriteReq mshr miss latency 1343system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16359.716480 # average LoadLockedReq mshr miss latency 1344system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16359.716480 # average LoadLockedReq mshr miss latency 1345system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21379.314664 # average StoreCondReq mshr miss latency 1346system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21379.314664 # average StoreCondReq mshr miss latency |
| 1348system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 1349system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1347system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 1348system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1350system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency 1351system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency 1352system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency 1353system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency | 1349system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency 1350system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency 1351system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency 1352system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency |
| 1354system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1355system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1356system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1357system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1358system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1359system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1360system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1353system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1354system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1355system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1356system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1357system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1358system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1359system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1361system.cpu1.icache.tags.replacements 893030 # number of replacements 1362system.cpu1.icache.tags.tagsinuse 499.459009 # Cycle average of tags in use 1363system.cpu1.icache.tags.total_refs 6770083 # Total number of references to valid blocks. 1364system.cpu1.icache.tags.sampled_refs 893542 # Sample count of references to valid blocks. 1365system.cpu1.icache.tags.avg_refs 7.576681 # Average number of references to valid blocks. 1366system.cpu1.icache.tags.warmup_cycle 71221486500 # Cycle when the warmup percentage was hit. 1367system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459009 # Average occupied blocks per requestor 1368system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy 1369system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy | 1360system.cpu1.icache.tags.replacements 827152 # number of replacements 1361system.cpu1.icache.tags.tagsinuse 499.447245 # Cycle average of tags in use 1362system.cpu1.icache.tags.total_refs 5824947 # Total number of references to valid blocks. 1363system.cpu1.icache.tags.sampled_refs 827664 # Sample count of references to valid blocks. 1364system.cpu1.icache.tags.avg_refs 7.037816 # Average number of references to valid blocks. 1365system.cpu1.icache.tags.warmup_cycle 71343314500 # Cycle when the warmup percentage was hit. 1366system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.447245 # Average occupied blocks per requestor 1367system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975483 # Average percentage of cache occupancy 1368system.cpu1.icache.tags.occ_percent::total 0.975483 # Average percentage of cache occupancy |
| 1370system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1369system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1371system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id 1372system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id | 1370system.cpu1.icache.tags.age_task_id_blocks_1024::2 469 # Occupied blocks per task id 1371system.cpu1.icache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id 1372system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id |
| 1373system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1373system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1374system.cpu1.icache.tags.tag_accesses 16220792 # Number of tag accesses 1375system.cpu1.icache.tags.data_accesses 16220792 # Number of data accesses 1376system.cpu1.icache.ReadReq_hits::cpu1.inst 6770083 # number of ReadReq hits 1377system.cpu1.icache.ReadReq_hits::total 6770083 # number of ReadReq hits 1378system.cpu1.icache.demand_hits::cpu1.inst 6770083 # number of demand (read+write) hits 1379system.cpu1.icache.demand_hits::total 6770083 # number of demand (read+write) hits 1380system.cpu1.icache.overall_hits::cpu1.inst 6770083 # number of overall hits 1381system.cpu1.icache.overall_hits::total 6770083 # number of overall hits 1382system.cpu1.icache.ReadReq_misses::cpu1.inst 893542 # number of ReadReq misses 1383system.cpu1.icache.ReadReq_misses::total 893542 # number of ReadReq misses 1384system.cpu1.icache.demand_misses::cpu1.inst 893542 # number of demand (read+write) misses 1385system.cpu1.icache.demand_misses::total 893542 # number of demand (read+write) misses 1386system.cpu1.icache.overall_misses::cpu1.inst 893542 # number of overall misses 1387system.cpu1.icache.overall_misses::total 893542 # number of overall misses 1388system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7266670468 # number of ReadReq miss cycles 1389system.cpu1.icache.ReadReq_miss_latency::total 7266670468 # number of ReadReq miss cycles 1390system.cpu1.icache.demand_miss_latency::cpu1.inst 7266670468 # number of demand (read+write) miss cycles 1391system.cpu1.icache.demand_miss_latency::total 7266670468 # number of demand (read+write) miss cycles 1392system.cpu1.icache.overall_miss_latency::cpu1.inst 7266670468 # number of overall miss cycles 1393system.cpu1.icache.overall_miss_latency::total 7266670468 # number of overall miss cycles 1394system.cpu1.icache.ReadReq_accesses::cpu1.inst 7663625 # number of ReadReq accesses(hits+misses) 1395system.cpu1.icache.ReadReq_accesses::total 7663625 # number of ReadReq accesses(hits+misses) 1396system.cpu1.icache.demand_accesses::cpu1.inst 7663625 # number of demand (read+write) accesses 1397system.cpu1.icache.demand_accesses::total 7663625 # number of demand (read+write) accesses 1398system.cpu1.icache.overall_accesses::cpu1.inst 7663625 # number of overall (read+write) accesses 1399system.cpu1.icache.overall_accesses::total 7663625 # number of overall (read+write) accesses 1400system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116595 # miss rate for ReadReq accesses 1401system.cpu1.icache.ReadReq_miss_rate::total 0.116595 # miss rate for ReadReq accesses 1402system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116595 # miss rate for demand accesses 1403system.cpu1.icache.demand_miss_rate::total 0.116595 # miss rate for demand accesses 1404system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116595 # miss rate for overall accesses 1405system.cpu1.icache.overall_miss_rate::total 0.116595 # miss rate for overall accesses 1406system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8132.433023 # average ReadReq miss latency 1407system.cpu1.icache.ReadReq_avg_miss_latency::total 8132.433023 # average ReadReq miss latency 1408system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency 1409system.cpu1.icache.demand_avg_miss_latency::total 8132.433023 # average overall miss latency 1410system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency 1411system.cpu1.icache.overall_avg_miss_latency::total 8132.433023 # average overall miss latency | 1374system.cpu1.icache.tags.tag_accesses 14132886 # Number of tag accesses 1375system.cpu1.icache.tags.data_accesses 14132886 # Number of data accesses 1376system.cpu1.icache.ReadReq_hits::cpu1.inst 5824947 # number of ReadReq hits 1377system.cpu1.icache.ReadReq_hits::total 5824947 # number of ReadReq hits 1378system.cpu1.icache.demand_hits::cpu1.inst 5824947 # number of demand (read+write) hits 1379system.cpu1.icache.demand_hits::total 5824947 # number of demand (read+write) hits 1380system.cpu1.icache.overall_hits::cpu1.inst 5824947 # number of overall hits 1381system.cpu1.icache.overall_hits::total 5824947 # number of overall hits 1382system.cpu1.icache.ReadReq_misses::cpu1.inst 827664 # number of ReadReq misses 1383system.cpu1.icache.ReadReq_misses::total 827664 # number of ReadReq misses 1384system.cpu1.icache.demand_misses::cpu1.inst 827664 # number of demand (read+write) misses 1385system.cpu1.icache.demand_misses::total 827664 # number of demand (read+write) misses 1386system.cpu1.icache.overall_misses::cpu1.inst 827664 # number of overall misses 1387system.cpu1.icache.overall_misses::total 827664 # number of overall misses 1388system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6712177482 # number of ReadReq miss cycles 1389system.cpu1.icache.ReadReq_miss_latency::total 6712177482 # number of ReadReq miss cycles 1390system.cpu1.icache.demand_miss_latency::cpu1.inst 6712177482 # number of demand (read+write) miss cycles 1391system.cpu1.icache.demand_miss_latency::total 6712177482 # number of demand (read+write) miss cycles 1392system.cpu1.icache.overall_miss_latency::cpu1.inst 6712177482 # number of overall miss cycles 1393system.cpu1.icache.overall_miss_latency::total 6712177482 # number of overall miss cycles 1394system.cpu1.icache.ReadReq_accesses::cpu1.inst 6652611 # number of ReadReq accesses(hits+misses) 1395system.cpu1.icache.ReadReq_accesses::total 6652611 # number of ReadReq accesses(hits+misses) 1396system.cpu1.icache.demand_accesses::cpu1.inst 6652611 # number of demand (read+write) accesses 1397system.cpu1.icache.demand_accesses::total 6652611 # number of demand (read+write) accesses 1398system.cpu1.icache.overall_accesses::cpu1.inst 6652611 # number of overall (read+write) accesses 1399system.cpu1.icache.overall_accesses::total 6652611 # number of overall (read+write) accesses 1400system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124412 # miss rate for ReadReq accesses 1401system.cpu1.icache.ReadReq_miss_rate::total 0.124412 # miss rate for ReadReq accesses 1402system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124412 # miss rate for demand accesses 1403system.cpu1.icache.demand_miss_rate::total 0.124412 # miss rate for demand accesses 1404system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124412 # miss rate for overall accesses 1405system.cpu1.icache.overall_miss_rate::total 0.124412 # miss rate for overall accesses 1406system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8109.785471 # average ReadReq miss latency 1407system.cpu1.icache.ReadReq_avg_miss_latency::total 8109.785471 # average ReadReq miss latency 1408system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency 1409system.cpu1.icache.demand_avg_miss_latency::total 8109.785471 # average overall miss latency 1410system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency 1411system.cpu1.icache.overall_avg_miss_latency::total 8109.785471 # average overall miss latency |
| 1412system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1413system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1414system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1415system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1416system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1417system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1418system.cpu1.icache.fast_writes 0 # number of fast writes performed 1419system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1412system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1413system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1414system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1415system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1416system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1417system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1418system.cpu1.icache.fast_writes 0 # number of fast writes performed 1419system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1420system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893542 # number of ReadReq MSHR misses 1421system.cpu1.icache.ReadReq_mshr_misses::total 893542 # number of ReadReq MSHR misses 1422system.cpu1.icache.demand_mshr_misses::cpu1.inst 893542 # number of demand (read+write) MSHR misses 1423system.cpu1.icache.demand_mshr_misses::total 893542 # number of demand (read+write) MSHR misses 1424system.cpu1.icache.overall_mshr_misses::cpu1.inst 893542 # number of overall MSHR misses 1425system.cpu1.icache.overall_mshr_misses::total 893542 # number of overall MSHR misses 1426system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923954530 # number of ReadReq MSHR miss cycles 1427system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923954530 # number of ReadReq MSHR miss cycles 1428system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923954530 # number of demand (read+write) MSHR miss cycles 1429system.cpu1.icache.demand_mshr_miss_latency::total 5923954530 # number of demand (read+write) MSHR miss cycles 1430system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923954530 # number of overall MSHR miss cycles 1431system.cpu1.icache.overall_mshr_miss_latency::total 5923954530 # number of overall MSHR miss cycles 1432system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10589750 # number of ReadReq MSHR uncacheable cycles 1433system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10589750 # number of ReadReq MSHR uncacheable cycles 1434system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10589750 # number of overall MSHR uncacheable cycles 1435system.cpu1.icache.overall_mshr_uncacheable_latency::total 10589750 # number of overall MSHR uncacheable cycles 1436system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for ReadReq accesses 1437system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses 1438system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for demand accesses 1439system.cpu1.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses 1440system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for overall accesses 1441system.cpu1.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses 1442system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average ReadReq mshr miss latency 1443system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.743795 # average ReadReq mshr miss latency 1444system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency 1445system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency 1446system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency 1447system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency | 1420system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 827664 # number of ReadReq MSHR misses 1421system.cpu1.icache.ReadReq_mshr_misses::total 827664 # number of ReadReq MSHR misses 1422system.cpu1.icache.demand_mshr_misses::cpu1.inst 827664 # number of demand (read+write) MSHR misses 1423system.cpu1.icache.demand_mshr_misses::total 827664 # number of demand (read+write) MSHR misses 1424system.cpu1.icache.overall_mshr_misses::cpu1.inst 827664 # number of overall MSHR misses 1425system.cpu1.icache.overall_mshr_misses::total 827664 # number of overall MSHR misses 1426system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5467532518 # number of ReadReq MSHR miss cycles 1427system.cpu1.icache.ReadReq_mshr_miss_latency::total 5467532518 # number of ReadReq MSHR miss cycles 1428system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5467532518 # number of demand (read+write) MSHR miss cycles 1429system.cpu1.icache.demand_mshr_miss_latency::total 5467532518 # number of demand (read+write) MSHR miss cycles 1430system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5467532518 # number of overall MSHR miss cycles 1431system.cpu1.icache.overall_mshr_miss_latency::total 5467532518 # number of overall MSHR miss cycles 1432system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10038000 # number of ReadReq MSHR uncacheable cycles 1433system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10038000 # number of ReadReq MSHR uncacheable cycles 1434system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10038000 # number of overall MSHR uncacheable cycles 1435system.cpu1.icache.overall_mshr_uncacheable_latency::total 10038000 # number of overall MSHR uncacheable cycles 1436system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for ReadReq accesses 1437system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124412 # mshr miss rate for ReadReq accesses 1438system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for demand accesses 1439system.cpu1.icache.demand_mshr_miss_rate::total 0.124412 # mshr miss rate for demand accesses 1440system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for overall accesses 1441system.cpu1.icache.overall_mshr_miss_rate::total 0.124412 # mshr miss rate for overall accesses 1442system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average ReadReq mshr miss latency 1443system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6605.980830 # average ReadReq mshr miss latency 1444system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency 1445system.cpu1.icache.demand_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency 1446system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency 1447system.cpu1.icache.overall_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency |
| 1448system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1449system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1450system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1451system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1452system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1448system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1449system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1450system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1451system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1452system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1453system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7064659 # number of hwpf identified 1454system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40510 # number of hwpf that were already in mshr 1455system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914419 # number of hwpf that were already in the cache 1456system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1409 # number of hwpf that were already in the prefetch queue | 1453system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6453687 # number of hwpf identified 1454system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 29592 # number of hwpf that were already in mshr 1455system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6340817 # number of hwpf that were already in the cache 1456system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 898 # number of hwpf that were already in the prefetch queue |
| 1457system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1457system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1458system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2627 # number of hwpf removed because MSHR allocated 1459system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105694 # number of hwpf issued 1460system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724613 # number of hwpf spanning a virtual page | 1458system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2376 # number of hwpf removed because MSHR allocated 1459system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 80004 # number of hwpf issued 1460system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 668025 # number of hwpf spanning a virtual page |
| 1461system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1461system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1462system.cpu1.l2cache.tags.replacements 80002 # number of replacements 1463system.cpu1.l2cache.tags.tagsinuse 15534.005683 # Cycle average of tags in use 1464system.cpu1.l2cache.tags.total_refs 1138706 # Total number of references to valid blocks. 1465system.cpu1.l2cache.tags.sampled_refs 95380 # Sample count of references to valid blocks. 1466system.cpu1.l2cache.tags.avg_refs 11.938624 # Average number of references to valid blocks. | 1462system.cpu1.l2cache.tags.replacements 52740 # number of replacements 1463system.cpu1.l2cache.tags.tagsinuse 15520.178150 # Cycle average of tags in use 1464system.cpu1.l2cache.tags.total_refs 1029232 # Total number of references to valid blocks. 1465system.cpu1.l2cache.tags.sampled_refs 68128 # Sample count of references to valid blocks. 1466system.cpu1.l2cache.tags.avg_refs 15.107327 # Average number of references to valid blocks. |
| 1467system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1467system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1468system.cpu1.l2cache.tags.occ_blocks::writebacks 6881.050205 # Average occupied blocks per requestor 1469system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.485106 # Average occupied blocks per requestor 1470system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.098583 # Average occupied blocks per requestor 1471system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2338.762949 # Average occupied blocks per requestor 1472system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6287.608842 # Average occupied blocks per requestor 1473system.cpu1.l2cache.tags.occ_percent::writebacks 0.419986 # Average percentage of cache occupancy 1474system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001617 # Average percentage of cache occupancy 1475system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy 1476system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142747 # Average percentage of cache occupancy 1477system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383765 # Average percentage of cache occupancy 1478system.cpu1.l2cache.tags.occ_percent::total 0.948120 # Average percentage of cache occupancy 1479system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10071 # Occupied blocks per task id 1480system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id 1481system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id 1482system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id 1483system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6676 # Occupied blocks per task id 1484system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3263 # Occupied blocks per task id 1485system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id 1486system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id 1487system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 1488system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 237 # Occupied blocks per task id 1489system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id 1490system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1869 # Occupied blocks per task id 1491system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.614685 # Percentage of cache occupancy per task id 1492system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id 1493system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.321838 # Percentage of cache occupancy per task id 1494system.cpu1.l2cache.tags.tag_accesses 21370209 # Number of tag accesses 1495system.cpu1.l2cache.tags.data_accesses 21370209 # Number of data accesses 1496system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22701 # number of ReadReq hits 1497system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2439 # number of ReadReq hits 1498system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993088 # number of ReadReq hits 1499system.cpu1.l2cache.ReadReq_hits::total 1018228 # number of ReadReq hits 1500system.cpu1.l2cache.Writeback_hits::writebacks 115754 # number of Writeback hits 1501system.cpu1.l2cache.Writeback_hits::total 115754 # number of Writeback hits 1502system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits 1503system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits 1504system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 740 # number of SCUpgradeReq hits 1505system.cpu1.l2cache.SCUpgradeReq_hits::total 740 # number of SCUpgradeReq hits 1506system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27796 # number of ReadExReq hits 1507system.cpu1.l2cache.ReadExReq_hits::total 27796 # number of ReadExReq hits 1508system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22701 # number of demand (read+write) hits 1509system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2439 # number of demand (read+write) hits 1510system.cpu1.l2cache.demand_hits::cpu1.inst 1020884 # number of demand (read+write) hits 1511system.cpu1.l2cache.demand_hits::total 1046024 # number of demand (read+write) hits 1512system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22701 # number of overall hits 1513system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2439 # number of overall hits 1514system.cpu1.l2cache.overall_hits::cpu1.inst 1020884 # number of overall hits 1515system.cpu1.l2cache.overall_hits::total 1046024 # number of overall hits 1516system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 604 # number of ReadReq misses 1517system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses 1518system.cpu1.l2cache.ReadReq_misses::cpu1.inst 72199 # number of ReadReq misses 1519system.cpu1.l2cache.ReadReq_misses::total 73046 # number of ReadReq misses 1520system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28140 # number of UpgradeReq misses 1521system.cpu1.l2cache.UpgradeReq_misses::total 28140 # number of UpgradeReq misses 1522system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22420 # number of SCUpgradeReq misses 1523system.cpu1.l2cache.SCUpgradeReq_misses::total 22420 # number of SCUpgradeReq misses 1524system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32240 # number of ReadExReq misses 1525system.cpu1.l2cache.ReadExReq_misses::total 32240 # number of ReadExReq misses 1526system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 604 # number of demand (read+write) misses 1527system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses 1528system.cpu1.l2cache.demand_misses::cpu1.inst 104439 # number of demand (read+write) misses 1529system.cpu1.l2cache.demand_misses::total 105286 # number of demand (read+write) misses 1530system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 604 # number of overall misses 1531system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses 1532system.cpu1.l2cache.overall_misses::cpu1.inst 104439 # number of overall misses 1533system.cpu1.l2cache.overall_misses::total 105286 # number of overall misses 1534system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13239000 # number of ReadReq miss cycles 1535system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4899500 # number of ReadReq miss cycles 1536system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1623706138 # number of ReadReq miss cycles 1537system.cpu1.l2cache.ReadReq_miss_latency::total 1641844638 # number of ReadReq miss cycles 1538system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 531483393 # number of UpgradeReq miss cycles 1539system.cpu1.l2cache.UpgradeReq_miss_latency::total 531483393 # number of UpgradeReq miss cycles 1540system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440502566 # number of SCUpgradeReq miss cycles 1541system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440502566 # number of SCUpgradeReq miss cycles 1542system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 296000 # number of SCUpgradeFailReq miss cycles 1543system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 296000 # number of SCUpgradeFailReq miss cycles 1544system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1126750383 # number of ReadExReq miss cycles 1545system.cpu1.l2cache.ReadExReq_miss_latency::total 1126750383 # number of ReadExReq miss cycles 1546system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13239000 # number of demand (read+write) miss cycles 1547system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4899500 # number of demand (read+write) miss cycles 1548system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2750456521 # number of demand (read+write) miss cycles 1549system.cpu1.l2cache.demand_miss_latency::total 2768595021 # number of demand (read+write) miss cycles 1550system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13239000 # number of overall miss cycles 1551system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4899500 # number of overall miss cycles 1552system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2750456521 # number of overall miss cycles 1553system.cpu1.l2cache.overall_miss_latency::total 2768595021 # number of overall miss cycles 1554system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23305 # number of ReadReq accesses(hits+misses) 1555system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2682 # number of ReadReq accesses(hits+misses) 1556system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1065287 # number of ReadReq accesses(hits+misses) 1557system.cpu1.l2cache.ReadReq_accesses::total 1091274 # number of ReadReq accesses(hits+misses) 1558system.cpu1.l2cache.Writeback_accesses::writebacks 115754 # number of Writeback accesses(hits+misses) 1559system.cpu1.l2cache.Writeback_accesses::total 115754 # number of Writeback accesses(hits+misses) 1560system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29950 # number of UpgradeReq accesses(hits+misses) 1561system.cpu1.l2cache.UpgradeReq_accesses::total 29950 # number of UpgradeReq accesses(hits+misses) 1562system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23160 # number of SCUpgradeReq accesses(hits+misses) 1563system.cpu1.l2cache.SCUpgradeReq_accesses::total 23160 # number of SCUpgradeReq accesses(hits+misses) 1564system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60036 # number of ReadExReq accesses(hits+misses) 1565system.cpu1.l2cache.ReadExReq_accesses::total 60036 # number of ReadExReq accesses(hits+misses) 1566system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23305 # number of demand (read+write) accesses 1567system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2682 # number of demand (read+write) accesses 1568system.cpu1.l2cache.demand_accesses::cpu1.inst 1125323 # number of demand (read+write) accesses 1569system.cpu1.l2cache.demand_accesses::total 1151310 # number of demand (read+write) accesses 1570system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23305 # number of overall (read+write) accesses 1571system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2682 # number of overall (read+write) accesses 1572system.cpu1.l2cache.overall_accesses::cpu1.inst 1125323 # number of overall (read+write) accesses 1573system.cpu1.l2cache.overall_accesses::total 1151310 # number of overall (read+write) accesses 1574system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for ReadReq accesses 1575system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090604 # miss rate for ReadReq accesses 1576system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067774 # miss rate for ReadReq accesses 1577system.cpu1.l2cache.ReadReq_miss_rate::total 0.066936 # miss rate for ReadReq accesses 1578system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.939566 # miss rate for UpgradeReq accesses 1579system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.939566 # miss rate for UpgradeReq accesses 1580system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968048 # miss rate for SCUpgradeReq accesses 1581system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968048 # miss rate for SCUpgradeReq accesses 1582system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.537011 # miss rate for ReadExReq accesses 1583system.cpu1.l2cache.ReadExReq_miss_rate::total 0.537011 # miss rate for ReadExReq accesses 1584system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for demand accesses 1585system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090604 # miss rate for demand accesses 1586system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092808 # miss rate for demand accesses 1587system.cpu1.l2cache.demand_miss_rate::total 0.091449 # miss rate for demand accesses 1588system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for overall accesses 1589system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090604 # miss rate for overall accesses 1590system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092808 # miss rate for overall accesses 1591system.cpu1.l2cache.overall_miss_rate::total 0.091449 # miss rate for overall accesses 1592system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average ReadReq miss latency 1593system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20162.551440 # average ReadReq miss latency 1594system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22489.316168 # average ReadReq miss latency 1595system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22476.858938 # average ReadReq miss latency 1596system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18887.114179 # average UpgradeReq miss latency 1597system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18887.114179 # average UpgradeReq miss latency 1598system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19647.750491 # average SCUpgradeReq miss latency 1599system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19647.750491 # average SCUpgradeReq miss latency | 1468system.cpu1.l2cache.tags.occ_blocks::writebacks 6901.586978 # Average occupied blocks per requestor 1469system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.255538 # Average occupied blocks per requestor 1470system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.084140 # Average occupied blocks per requestor 1471system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2337.993929 # Average occupied blocks per requestor 1472system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6253.257565 # Average occupied blocks per requestor 1473system.cpu1.l2cache.tags.occ_percent::writebacks 0.421239 # Average percentage of cache occupancy 1474system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001664 # Average percentage of cache occupancy 1475system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy 1476system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142700 # Average percentage of cache occupancy 1477system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.381669 # Average percentage of cache occupancy 1478system.cpu1.l2cache.tags.occ_percent::total 0.947276 # Average percentage of cache occupancy 1479system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8859 # Occupied blocks per task id 1480system.cpu1.l2cache.tags.occ_task_id_blocks::1023 87 # Occupied blocks per task id 1481system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6442 # Occupied blocks per task id 1482system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 153 # Occupied blocks per task id 1483system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1624 # Occupied blocks per task id 1484system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 7082 # Occupied blocks per task id 1485system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id 1486system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 1487system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 51 # Occupied blocks per task id 1488system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 256 # Occupied blocks per task id 1489system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1161 # Occupied blocks per task id 1490system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5025 # Occupied blocks per task id 1491system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.540710 # Percentage of cache occupancy per task id 1492system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005310 # Percentage of cache occupancy per task id 1493system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.393188 # Percentage of cache occupancy per task id 1494system.cpu1.l2cache.tags.tag_accesses 19285639 # Number of tag accesses 1495system.cpu1.l2cache.tags.data_accesses 19285639 # Number of data accesses 1496system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22569 # number of ReadReq hits 1497system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2289 # number of ReadReq hits 1498system.cpu1.l2cache.ReadReq_hits::cpu1.inst 905837 # number of ReadReq hits 1499system.cpu1.l2cache.ReadReq_hits::total 930695 # number of ReadReq hits 1500system.cpu1.l2cache.Writeback_hits::writebacks 93707 # number of Writeback hits 1501system.cpu1.l2cache.Writeback_hits::total 93707 # number of Writeback hits 1502system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1549 # number of UpgradeReq hits 1503system.cpu1.l2cache.UpgradeReq_hits::total 1549 # number of UpgradeReq hits 1504system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 533 # number of SCUpgradeReq hits 1505system.cpu1.l2cache.SCUpgradeReq_hits::total 533 # number of SCUpgradeReq hits 1506system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 18299 # number of ReadExReq hits 1507system.cpu1.l2cache.ReadExReq_hits::total 18299 # number of ReadExReq hits 1508system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22569 # number of demand (read+write) hits 1509system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2289 # number of demand (read+write) hits 1510system.cpu1.l2cache.demand_hits::cpu1.inst 924136 # number of demand (read+write) hits 1511system.cpu1.l2cache.demand_hits::total 948994 # number of demand (read+write) hits 1512system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22569 # number of overall hits 1513system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2289 # number of overall hits 1514system.cpu1.l2cache.overall_hits::cpu1.inst 924136 # number of overall hits 1515system.cpu1.l2cache.overall_hits::total 948994 # number of overall hits 1516system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 704 # number of ReadReq misses 1517system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 245 # number of ReadReq misses 1518system.cpu1.l2cache.ReadReq_misses::cpu1.inst 66474 # number of ReadReq misses 1519system.cpu1.l2cache.ReadReq_misses::total 67423 # number of ReadReq misses 1520system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 27781 # number of UpgradeReq misses 1521system.cpu1.l2cache.UpgradeReq_misses::total 27781 # number of UpgradeReq misses 1522system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22285 # number of SCUpgradeReq misses 1523system.cpu1.l2cache.SCUpgradeReq_misses::total 22285 # number of SCUpgradeReq misses 1524system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 30137 # number of ReadExReq misses 1525system.cpu1.l2cache.ReadExReq_misses::total 30137 # number of ReadExReq misses 1526system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 704 # number of demand (read+write) misses 1527system.cpu1.l2cache.demand_misses::cpu1.itb.walker 245 # number of demand (read+write) misses 1528system.cpu1.l2cache.demand_misses::cpu1.inst 96611 # number of demand (read+write) misses 1529system.cpu1.l2cache.demand_misses::total 97560 # number of demand (read+write) misses 1530system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 704 # number of overall misses 1531system.cpu1.l2cache.overall_misses::cpu1.itb.walker 245 # number of overall misses 1532system.cpu1.l2cache.overall_misses::cpu1.inst 96611 # number of overall misses 1533system.cpu1.l2cache.overall_misses::total 97560 # number of overall misses 1534system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14471499 # number of ReadReq miss cycles 1535system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4810998 # number of ReadReq miss cycles 1536system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1464118881 # number of ReadReq miss cycles 1537system.cpu1.l2cache.ReadReq_miss_latency::total 1483401378 # number of ReadReq miss cycles 1538system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 523592810 # number of UpgradeReq miss cycles 1539system.cpu1.l2cache.UpgradeReq_miss_latency::total 523592810 # number of UpgradeReq miss cycles 1540system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 437167020 # number of SCUpgradeReq miss cycles 1541system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 437167020 # number of SCUpgradeReq miss cycles 1542system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 97500 # number of SCUpgradeFailReq miss cycles 1543system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 97500 # number of SCUpgradeFailReq miss cycles 1544system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1078871611 # number of ReadExReq miss cycles 1545system.cpu1.l2cache.ReadExReq_miss_latency::total 1078871611 # number of ReadExReq miss cycles 1546system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14471499 # number of demand (read+write) miss cycles 1547system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4810998 # number of demand (read+write) miss cycles 1548system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2542990492 # number of demand (read+write) miss cycles 1549system.cpu1.l2cache.demand_miss_latency::total 2562272989 # number of demand (read+write) miss cycles 1550system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14471499 # number of overall miss cycles 1551system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4810998 # number of overall miss cycles 1552system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2542990492 # number of overall miss cycles 1553system.cpu1.l2cache.overall_miss_latency::total 2562272989 # number of overall miss cycles 1554system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23273 # number of ReadReq accesses(hits+misses) 1555system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2534 # number of ReadReq accesses(hits+misses) 1556system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 972311 # number of ReadReq accesses(hits+misses) 1557system.cpu1.l2cache.ReadReq_accesses::total 998118 # number of ReadReq accesses(hits+misses) 1558system.cpu1.l2cache.Writeback_accesses::writebacks 93707 # number of Writeback accesses(hits+misses) 1559system.cpu1.l2cache.Writeback_accesses::total 93707 # number of Writeback accesses(hits+misses) 1560system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29330 # number of UpgradeReq accesses(hits+misses) 1561system.cpu1.l2cache.UpgradeReq_accesses::total 29330 # number of UpgradeReq accesses(hits+misses) 1562system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 22818 # number of SCUpgradeReq accesses(hits+misses) 1563system.cpu1.l2cache.SCUpgradeReq_accesses::total 22818 # number of SCUpgradeReq accesses(hits+misses) 1564system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 48436 # number of ReadExReq accesses(hits+misses) 1565system.cpu1.l2cache.ReadExReq_accesses::total 48436 # number of ReadExReq accesses(hits+misses) 1566system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23273 # number of demand (read+write) accesses 1567system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2534 # number of demand (read+write) accesses 1568system.cpu1.l2cache.demand_accesses::cpu1.inst 1020747 # number of demand (read+write) accesses 1569system.cpu1.l2cache.demand_accesses::total 1046554 # number of demand (read+write) accesses 1570system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23273 # number of overall (read+write) accesses 1571system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2534 # number of overall (read+write) accesses 1572system.cpu1.l2cache.overall_accesses::cpu1.inst 1020747 # number of overall (read+write) accesses 1573system.cpu1.l2cache.overall_accesses::total 1046554 # number of overall (read+write) accesses 1574system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for ReadReq accesses 1575system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.096685 # miss rate for ReadReq accesses 1576system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.068367 # miss rate for ReadReq accesses 1577system.cpu1.l2cache.ReadReq_miss_rate::total 0.067550 # miss rate for ReadReq accesses 1578system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.947187 # miss rate for UpgradeReq accesses 1579system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947187 # miss rate for UpgradeReq accesses 1580system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.976641 # miss rate for SCUpgradeReq accesses 1581system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.976641 # miss rate for SCUpgradeReq accesses 1582system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.622202 # miss rate for ReadExReq accesses 1583system.cpu1.l2cache.ReadExReq_miss_rate::total 0.622202 # miss rate for ReadExReq accesses 1584system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for demand accesses 1585system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.096685 # miss rate for demand accesses 1586system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094647 # miss rate for demand accesses 1587system.cpu1.l2cache.demand_miss_rate::total 0.093220 # miss rate for demand accesses 1588system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for overall accesses 1589system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.096685 # miss rate for overall accesses 1590system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094647 # miss rate for overall accesses 1591system.cpu1.l2cache.overall_miss_rate::total 0.093220 # miss rate for overall accesses 1592system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average ReadReq miss latency 1593system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19636.726531 # average ReadReq miss latency 1594system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22025.436727 # average ReadReq miss latency 1595system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22001.414621 # average ReadReq miss latency 1596system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18847.154890 # average UpgradeReq miss latency 1597system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18847.154890 # average UpgradeReq miss latency 1598system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19617.097599 # average SCUpgradeReq miss latency 1599system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.097599 # average SCUpgradeReq miss latency |
| 1600system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency 1601system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency | 1600system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency 1601system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency |
| 1602system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34948.833220 # average ReadExReq miss latency 1603system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34948.833220 # average ReadExReq miss latency 1604system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average overall miss latency 1605system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20162.551440 # average overall miss latency 1606system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26335.530989 # average overall miss latency 1607system.cpu1.l2cache.demand_avg_miss_latency::total 26295.946479 # average overall miss latency 1608system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average overall miss latency 1609system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20162.551440 # average overall miss latency 1610system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26335.530989 # average overall miss latency 1611system.cpu1.l2cache.overall_avg_miss_latency::total 26295.946479 # average overall miss latency 1612system.cpu1.l2cache.blocked_cycles::no_mshrs 4629 # number of cycles access was blocked | 1602system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35798.905365 # average ReadExReq miss latency 1603system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35798.905365 # average ReadExReq miss latency 1604system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average overall miss latency 1605system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19636.726531 # average overall miss latency 1606system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26321.956009 # average overall miss latency 1607system.cpu1.l2cache.demand_avg_miss_latency::total 26263.560773 # average overall miss latency 1608system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average overall miss latency 1609system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19636.726531 # average overall miss latency 1610system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26321.956009 # average overall miss latency 1611system.cpu1.l2cache.overall_avg_miss_latency::total 26263.560773 # average overall miss latency 1612system.cpu1.l2cache.blocked_cycles::no_mshrs 2801 # number of cycles access was blocked |
| 1613system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1613system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1614system.cpu1.l2cache.blocked::no_mshrs 159 # number of cycles access was blocked | 1614system.cpu1.l2cache.blocked::no_mshrs 79 # number of cycles access was blocked |
| 1615system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1615system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1616system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29.113208 # average number of cycles each access was blocked | 1616system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 35.455696 # average number of cycles each access was blocked |
| 1617system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1618system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1619system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1617system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1618system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1619system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1620system.cpu1.l2cache.writebacks::writebacks 38442 # number of writebacks 1621system.cpu1.l2cache.writebacks::total 38442 # number of writebacks 1622system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1604 # number of ReadReq MSHR hits 1623system.cpu1.l2cache.ReadReq_mshr_hits::total 1604 # number of ReadReq MSHR hits 1624system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 322 # number of ReadExReq MSHR hits 1625system.cpu1.l2cache.ReadExReq_mshr_hits::total 322 # number of ReadExReq MSHR hits 1626system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1926 # number of demand (read+write) MSHR hits 1627system.cpu1.l2cache.demand_mshr_hits::total 1926 # number of demand (read+write) MSHR hits 1628system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1926 # number of overall MSHR hits 1629system.cpu1.l2cache.overall_mshr_hits::total 1926 # number of overall MSHR hits 1630system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 604 # number of ReadReq MSHR misses 1631system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 243 # number of ReadReq MSHR misses 1632system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 70595 # number of ReadReq MSHR misses 1633system.cpu1.l2cache.ReadReq_mshr_misses::total 71442 # number of ReadReq MSHR misses 1634system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 105694 # number of HardPFReq MSHR misses 1635system.cpu1.l2cache.HardPFReq_mshr_misses::total 105694 # number of HardPFReq MSHR misses 1636system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28140 # number of UpgradeReq MSHR misses 1637system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28140 # number of UpgradeReq MSHR misses 1638system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22420 # number of SCUpgradeReq MSHR misses 1639system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22420 # number of SCUpgradeReq MSHR misses 1640system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 31918 # number of ReadExReq MSHR misses 1641system.cpu1.l2cache.ReadExReq_mshr_misses::total 31918 # number of ReadExReq MSHR misses 1642system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 604 # number of demand (read+write) MSHR misses 1643system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 243 # number of demand (read+write) MSHR misses 1644system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 102513 # number of demand (read+write) MSHR misses 1645system.cpu1.l2cache.demand_mshr_misses::total 103360 # number of demand (read+write) MSHR misses 1646system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 604 # number of overall MSHR misses 1647system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 243 # number of overall MSHR misses 1648system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 102513 # number of overall MSHR misses 1649system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 105694 # number of overall MSHR misses 1650system.cpu1.l2cache.overall_mshr_misses::total 209054 # number of overall MSHR misses 1651system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of ReadReq MSHR miss cycles 1652system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3198500 # number of ReadReq MSHR miss cycles 1653system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1098179235 # number of ReadReq MSHR miss cycles 1654system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1110385737 # number of ReadReq MSHR miss cycles 1655system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2958247424 # number of HardPFReq MSHR miss cycles 1656system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2958247424 # number of HardPFReq MSHR miss cycles 1657system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 404415795 # number of UpgradeReq MSHR miss cycles 1658system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 404415795 # number of UpgradeReq MSHR miss cycles 1659system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 308218727 # number of SCUpgradeReq MSHR miss cycles 1660system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308218727 # number of SCUpgradeReq MSHR miss cycles 1661system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 247000 # number of SCUpgradeFailReq MSHR miss cycles 1662system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 247000 # number of SCUpgradeFailReq MSHR miss cycles 1663system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 862164082 # number of ReadExReq MSHR miss cycles 1664system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 862164082 # number of ReadExReq MSHR miss cycles 1665system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of demand (read+write) MSHR miss cycles 1666system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3198500 # number of demand (read+write) MSHR miss cycles 1667system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1960343317 # number of demand (read+write) MSHR miss cycles 1668system.cpu1.l2cache.demand_mshr_miss_latency::total 1972549819 # number of demand (read+write) MSHR miss cycles 1669system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of overall MSHR miss cycles 1670system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3198500 # number of overall MSHR miss cycles 1671system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1960343317 # number of overall MSHR miss cycles 1672system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2958247424 # number of overall MSHR miss cycles 1673system.cpu1.l2cache.overall_mshr_miss_latency::total 4930797243 # number of overall MSHR miss cycles 1674system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316625253 # number of ReadReq MSHR uncacheable cycles 1675system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316625253 # number of ReadReq MSHR uncacheable cycles 1676system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 186937501 # number of WriteReq MSHR uncacheable cycles 1677system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 186937501 # number of WriteReq MSHR uncacheable cycles 1678system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 503562754 # number of overall MSHR uncacheable cycles 1679system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 503562754 # number of overall MSHR uncacheable cycles 1680system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for ReadReq accesses 1681system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for ReadReq accesses 1682system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066269 # mshr miss rate for ReadReq accesses 1683system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065467 # mshr miss rate for ReadReq accesses | 1620system.cpu1.l2cache.writebacks::writebacks 30368 # number of writebacks 1621system.cpu1.l2cache.writebacks::total 30368 # number of writebacks 1622system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 950 # number of ReadReq MSHR hits 1623system.cpu1.l2cache.ReadReq_mshr_hits::total 950 # number of ReadReq MSHR hits 1624system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 295 # number of ReadExReq MSHR hits 1625system.cpu1.l2cache.ReadExReq_mshr_hits::total 295 # number of ReadExReq MSHR hits 1626system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1245 # number of demand (read+write) MSHR hits 1627system.cpu1.l2cache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits 1628system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1245 # number of overall MSHR hits 1629system.cpu1.l2cache.overall_mshr_hits::total 1245 # number of overall MSHR hits 1630system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 704 # number of ReadReq MSHR misses 1631system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 245 # number of ReadReq MSHR misses 1632system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 65524 # number of ReadReq MSHR misses 1633system.cpu1.l2cache.ReadReq_mshr_misses::total 66473 # number of ReadReq MSHR misses 1634system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of HardPFReq MSHR misses 1635system.cpu1.l2cache.HardPFReq_mshr_misses::total 80004 # number of HardPFReq MSHR misses 1636system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 27781 # number of UpgradeReq MSHR misses 1637system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27781 # number of UpgradeReq MSHR misses 1638system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22285 # number of SCUpgradeReq MSHR misses 1639system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22285 # number of SCUpgradeReq MSHR misses 1640system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 29842 # number of ReadExReq MSHR misses 1641system.cpu1.l2cache.ReadExReq_mshr_misses::total 29842 # number of ReadExReq MSHR misses 1642system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 704 # number of demand (read+write) MSHR misses 1643system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 245 # number of demand (read+write) MSHR misses 1644system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 95366 # number of demand (read+write) MSHR misses 1645system.cpu1.l2cache.demand_mshr_misses::total 96315 # number of demand (read+write) MSHR misses 1646system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 704 # number of overall MSHR misses 1647system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 245 # number of overall MSHR misses 1648system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 95366 # number of overall MSHR misses 1649system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of overall MSHR misses 1650system.cpu1.l2cache.overall_mshr_misses::total 176319 # number of overall MSHR misses 1651system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of ReadReq MSHR miss cycles 1652system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3095998 # number of ReadReq MSHR miss cycles 1653system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 981688737 # number of ReadReq MSHR miss cycles 1654system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 994327236 # number of ReadReq MSHR miss cycles 1655system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of HardPFReq MSHR miss cycles 1656system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2522312930 # number of HardPFReq MSHR miss cycles 1657system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 396174942 # number of UpgradeReq MSHR miss cycles 1658system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 396174942 # number of UpgradeReq MSHR miss cycles 1659system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 306073762 # number of SCUpgradeReq MSHR miss cycles 1660system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306073762 # number of SCUpgradeReq MSHR miss cycles 1661system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 76500 # number of SCUpgradeFailReq MSHR miss cycles 1662system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 76500 # number of SCUpgradeFailReq MSHR miss cycles 1663system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 831450098 # number of ReadExReq MSHR miss cycles 1664system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 831450098 # number of ReadExReq MSHR miss cycles 1665system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of demand (read+write) MSHR miss cycles 1666system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3095998 # number of demand (read+write) MSHR miss cycles 1667system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1813138835 # number of demand (read+write) MSHR miss cycles 1668system.cpu1.l2cache.demand_mshr_miss_latency::total 1825777334 # number of demand (read+write) MSHR miss cycles 1669system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of overall MSHR miss cycles 1670system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3095998 # number of overall MSHR miss cycles 1671system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1813138835 # number of overall MSHR miss cycles 1672system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of overall MSHR miss cycles 1673system.cpu1.l2cache.overall_mshr_miss_latency::total 4348090264 # number of overall MSHR miss cycles 1674system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 313994504 # number of ReadReq MSHR uncacheable cycles 1675system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 313994504 # number of ReadReq MSHR uncacheable cycles 1676system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 182561501 # number of WriteReq MSHR uncacheable cycles 1677system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 182561501 # number of WriteReq MSHR uncacheable cycles 1678system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 496556005 # number of overall MSHR uncacheable cycles 1679system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 496556005 # number of overall MSHR uncacheable cycles 1680system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for ReadReq accesses 1681system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for ReadReq accesses 1682system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.067390 # mshr miss rate for ReadReq accesses 1683system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.066598 # mshr miss rate for ReadReq accesses |
| 1684system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1685system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1684system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1685system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1686system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.939566 # mshr miss rate for UpgradeReq accesses 1687system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.939566 # mshr miss rate for UpgradeReq accesses 1688system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968048 # mshr miss rate for SCUpgradeReq accesses 1689system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968048 # mshr miss rate for SCUpgradeReq accesses 1690system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.531648 # mshr miss rate for ReadExReq accesses 1691system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.531648 # mshr miss rate for ReadExReq accesses 1692system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for demand accesses 1693system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for demand accesses 1694system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for demand accesses 1695system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089776 # mshr miss rate for demand accesses 1696system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for overall accesses 1697system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for overall accesses 1698system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for overall accesses | 1686system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.947187 # mshr miss rate for UpgradeReq accesses 1687system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947187 # mshr miss rate for UpgradeReq accesses 1688system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.976641 # mshr miss rate for SCUpgradeReq accesses 1689system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.976641 # mshr miss rate for SCUpgradeReq accesses 1690system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.616112 # mshr miss rate for ReadExReq accesses 1691system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.616112 # mshr miss rate for ReadExReq accesses 1692system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for demand accesses 1693system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for demand accesses 1694system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for demand accesses 1695system.cpu1.l2cache.demand_mshr_miss_rate::total 0.092031 # mshr miss rate for demand accesses 1696system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for overall accesses 1697system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for overall accesses 1698system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for overall accesses |
| 1699system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1699system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1700system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181579 # mshr miss rate for overall accesses 1701system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average ReadReq mshr miss latency 1702system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average ReadReq mshr miss latency 1703system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15556.048375 # average ReadReq mshr miss latency 1704system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15542.478332 # average ReadReq mshr miss latency 1705system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average HardPFReq mshr miss latency 1706system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27988.792401 # average HardPFReq mshr miss latency 1707system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14371.563433 # average UpgradeReq mshr miss latency 1708system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14371.563433 # average UpgradeReq mshr miss latency 1709system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13747.490054 # average SCUpgradeReq mshr miss latency 1710system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13747.490054 # average SCUpgradeReq mshr miss latency | 1700system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168476 # mshr miss rate for overall accesses 1701system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average ReadReq mshr miss latency 1702system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average ReadReq mshr miss latency 1703system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14982.124672 # average ReadReq mshr miss latency 1704system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14958.362583 # average ReadReq mshr miss latency 1705system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average HardPFReq mshr miss latency 1706system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31527.335258 # average HardPFReq mshr miss latency 1707system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14260.643677 # average UpgradeReq mshr miss latency 1708system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14260.643677 # average UpgradeReq mshr miss latency 1709system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13734.519273 # average SCUpgradeReq mshr miss latency 1710system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13734.519273 # average SCUpgradeReq mshr miss latency |
| 1711system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency 1712system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency | 1711system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency 1712system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency |
| 1713system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27011.845416 # average ReadExReq mshr miss latency 1714system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27011.845416 # average ReadExReq mshr miss latency 1715system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency 1716system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency 1717system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency 1718system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19084.266825 # average overall mshr miss latency 1719system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency 1720system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency 1721system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency 1722system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average overall mshr miss latency 1723system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23586.237254 # average overall mshr miss latency | 1713system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27861.741773 # average ReadExReq mshr miss latency 1714system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27861.741773 # average ReadExReq mshr miss latency 1715system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency 1716system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency 1717system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency 1718system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18956.313492 # average overall mshr miss latency 1719system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency 1720system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency 1721system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency 1722system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average overall mshr miss latency 1723system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24660.361413 # average overall mshr miss latency |
| 1724system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1725system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1726system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1727system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1728system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1729system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1730system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1724system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1725system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1726system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1727system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1728system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1729system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1730system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1731system.cpu1.toL2Bus.trans_dist::ReadReq 1582615 # Transaction distribution 1732system.cpu1.toL2Bus.trans_dist::ReadResp 1137834 # Transaction distribution 1733system.cpu1.toL2Bus.trans_dist::WriteReq 2120 # Transaction distribution 1734system.cpu1.toL2Bus.trans_dist::WriteResp 2120 # Transaction distribution 1735system.cpu1.toL2Bus.trans_dist::Writeback 115754 # Transaction distribution 1736system.cpu1.toL2Bus.trans_dist::HardPFReq 151048 # Transaction distribution 1737system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 1738system.cpu1.toL2Bus.trans_dist::UpgradeReq 84372 # Transaction distribution 1739system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41116 # Transaction distribution 1740system.cpu1.toL2Bus.trans_dist::UpgradeResp 85179 # Transaction distribution 1741system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 1742system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution 1743system.cpu1.toL2Bus.trans_dist::ReadExReq 76804 # Transaction distribution 1744system.cpu1.toL2Bus.trans_dist::ReadExResp 64396 # Transaction distribution 1745system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787314 # Packet count per connected master and slave (bytes) 1746system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 769072 # Packet count per connected master and slave (bytes) 1747system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6988 # Packet count per connected master and slave (bytes) 1748system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51360 # Packet count per connected master and slave (bytes) 1749system.cpu1.toL2Bus.pkt_count::total 2614734 # Packet count per connected master and slave (bytes) 1750system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57194048 # Cumulative packet size per connected master and slave (bytes) 1751system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24925415 # Cumulative packet size per connected master and slave (bytes) 1752system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10728 # Cumulative packet size per connected master and slave (bytes) 1753system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93220 # Cumulative packet size per connected master and slave (bytes) 1754system.cpu1.toL2Bus.pkt_size::total 82223411 # Cumulative packet size per connected master and slave (bytes) 1755system.cpu1.toL2Bus.snoops 838592 # Total snoops (count) 1756system.cpu1.toL2Bus.snoop_fanout::samples 2085067 # Request fanout histogram 1757system.cpu1.toL2Bus.snoop_fanout::mean 5.363773 # Request fanout histogram 1758system.cpu1.toL2Bus.snoop_fanout::stdev 0.481085 # Request fanout histogram | 1731system.cpu1.toL2Bus.trans_dist::ReadReq 1502965 # Transaction distribution 1732system.cpu1.toL2Bus.trans_dist::ReadResp 1041469 # Transaction distribution 1733system.cpu1.toL2Bus.trans_dist::WriteReq 2098 # Transaction distribution 1734system.cpu1.toL2Bus.trans_dist::WriteResp 2098 # Transaction distribution 1735system.cpu1.toL2Bus.trans_dist::Writeback 93707 # Transaction distribution 1736system.cpu1.toL2Bus.trans_dist::HardPFReq 114724 # Transaction distribution 1737system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1738system.cpu1.toL2Bus.trans_dist::UpgradeReq 83933 # Transaction distribution 1739system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40744 # Transaction distribution 1740system.cpu1.toL2Bus.trans_dist::UpgradeResp 84523 # Transaction distribution 1741system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 1742system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution 1743system.cpu1.toL2Bus.trans_dist::ReadExReq 65298 # Transaction distribution 1744system.cpu1.toL2Bus.trans_dist::ReadExResp 52790 # Transaction distribution 1745system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1655558 # Packet count per connected master and slave (bytes) 1746system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 667978 # Packet count per connected master and slave (bytes) 1747system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6105 # Packet count per connected master and slave (bytes) 1748system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48641 # Packet count per connected master and slave (bytes) 1749system.cpu1.toL2Bus.pkt_count::total 2378282 # Packet count per connected master and slave (bytes) 1750system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 52977856 # Cumulative packet size per connected master and slave (bytes) 1751system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21039827 # Cumulative packet size per connected master and slave (bytes) 1752system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10136 # Cumulative packet size per connected master and slave (bytes) 1753system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93092 # Cumulative packet size per connected master and slave (bytes) 1754system.cpu1.toL2Bus.pkt_size::total 74120911 # Cumulative packet size per connected master and slave (bytes) 1755system.cpu1.toL2Bus.snoops 816365 # Total snoops (count) 1756system.cpu1.toL2Bus.snoop_fanout::samples 1934720 # Request fanout histogram 1757system.cpu1.toL2Bus.snoop_fanout::mean 5.382054 # Request fanout histogram 1758system.cpu1.toL2Bus.snoop_fanout::stdev 0.485890 # Request fanout histogram |
| 1759system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1760system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1761system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1762system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1763system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1764system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1759system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1760system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1761system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1762system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1763system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1764system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1765system.cpu1.toL2Bus.snoop_fanout::5 1326575 63.62% 63.62% # Request fanout histogram 1766system.cpu1.toL2Bus.snoop_fanout::6 758492 36.38% 100.00% # Request fanout histogram | 1765system.cpu1.toL2Bus.snoop_fanout::5 1195552 61.79% 61.79% # Request fanout histogram 1766system.cpu1.toL2Bus.snoop_fanout::6 739168 38.21% 100.00% # Request fanout histogram |
| 1767system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1768system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1769system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1767system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1768system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1769system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1770system.cpu1.toL2Bus.snoop_fanout::total 2085067 # Request fanout histogram 1771system.cpu1.toL2Bus.reqLayer0.occupancy 782771935 # Layer occupancy (ticks) | 1770system.cpu1.toL2Bus.snoop_fanout::total 1934720 # Request fanout histogram 1771system.cpu1.toL2Bus.reqLayer0.occupancy 695166718 # Layer occupancy (ticks) |
| 1772system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1772system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1773system.cpu1.toL2Bus.snoopLayer0.occupancy 78513000 # Layer occupancy (ticks) | 1773system.cpu1.toL2Bus.snoopLayer0.occupancy 78719500 # Layer occupancy (ticks) |
| 1774system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1774system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1775system.cpu1.toL2Bus.respLayer0.occupancy 1341710719 # Layer occupancy (ticks) | 1775system.cpu1.toL2Bus.respLayer0.occupancy 1243267482 # Layer occupancy (ticks) |
| 1776system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1776system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1777system.cpu1.toL2Bus.respLayer1.occupancy 381436893 # Layer occupancy (ticks) | 1777system.cpu1.toL2Bus.respLayer1.occupancy 322631890 # Layer occupancy (ticks) |
| 1778system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1778system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1779system.cpu1.toL2Bus.respLayer2.occupancy 4307996 # Layer occupancy (ticks) | 1779system.cpu1.toL2Bus.respLayer2.occupancy 3571998 # Layer occupancy (ticks) |
| 1780system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1780system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1781system.cpu1.toL2Bus.respLayer3.occupancy 28057498 # Layer occupancy (ticks) | 1781system.cpu1.toL2Bus.respLayer3.occupancy 25370995 # Layer occupancy (ticks) |
| 1782system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1782system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1783system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 1784system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 1785system.iobus.trans_dist::WriteReq 59407 # Transaction distribution 1786system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 1787system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution 1788system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) | 1783system.iobus.trans_dist::ReadReq 31020 # Transaction distribution 1784system.iobus.trans_dist::ReadResp 31020 # Transaction distribution 1785system.iobus.trans_dist::WriteReq 59447 # Transaction distribution 1786system.iobus.trans_dist::WriteResp 23223 # Transaction distribution 1787system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1788system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56686 # Packet count per connected master and slave (bytes) |
| 1789system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1790system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1791system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1792system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1793system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1794system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1795system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1796system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1801system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1802system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1803system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1804system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1805system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1806system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1807system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1808system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 1789system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1790system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1791system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1792system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1793system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1794system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1795system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1796system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1801system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1802system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1803system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1804system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1805system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1806system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1807system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1808system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 1809system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) | 1809system.iobus.pkt_count_system.bridge.master::total 108000 # Packet count per connected master and slave (bytes) |
| 1810system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 1811system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) | 1810system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 1811system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) |
| 1812system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) 1813system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) | 1812system.iobus.pkt_count::total 180934 # Packet count per connected master and slave (bytes) 1813system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71630 # Cumulative packet size per connected master and slave (bytes) |
| 1814system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1815system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1816system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1817system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1818system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1819system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1820system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1821system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1826system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1827system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1828system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1829system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1830system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1831system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1832system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1833system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 1814system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1815system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1816system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1817system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1818system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1819system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1820system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1821system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1826system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1827system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1828system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1829system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1830system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1831system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1832system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1833system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 1834system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) | 1834system.iobus.pkt_size_system.bridge.master::total 162880 # Cumulative packet size per connected master and slave (bytes) |
| 1835system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 1836system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) | 1835system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 1836system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) |
| 1837system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) 1838system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) | 1837system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) 1838system.iobus.reqLayer0.occupancy 40158000 # Layer occupancy (ticks) |
| 1839system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1840system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 1841system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1842system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1843system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1844system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1845system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1846system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 1870system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1871system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1872system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1873system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1874system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1875system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1876system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1877system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1839system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1840system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 1841system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1842system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1843system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1844system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1845system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1846system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 1870system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1871system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1872system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1873system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1874system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1875system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1876system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1877system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1878system.iobus.reqLayer27.occupancy 326658321 # Layer occupancy (ticks) | 1878system.iobus.reqLayer27.occupancy 347075142 # Layer occupancy (ticks) |
| 1879system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1880system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1881system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1879system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1880system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1881system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1882system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) | 1882system.iobus.respLayer0.occupancy 84777000 # Layer occupancy (ticks) |
| 1883system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1883system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1884system.iobus.respLayer3.occupancy 36824131 # Layer occupancy (ticks) | 1884system.iobus.respLayer3.occupancy 36822606 # Layer occupancy (ticks) |
| 1885system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1885system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1886system.iocache.tags.replacements 36417 # number of replacements 1887system.iocache.tags.tagsinuse 0.992159 # Cycle average of tags in use | 1886system.iocache.tags.replacements 36433 # number of replacements 1887system.iocache.tags.tagsinuse 0.995239 # Cycle average of tags in use |
| 1888system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1888system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1889system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. | 1889system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. |
| 1890system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1890system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1891system.iocache.tags.warmup_cycle 268855800000 # Cycle when the warmup percentage was hit. 1892system.iocache.tags.occ_blocks::realview.ide 0.992159 # Average occupied blocks per requestor 1893system.iocache.tags.occ_percent::realview.ide 0.062010 # Average percentage of cache occupancy 1894system.iocache.tags.occ_percent::total 0.062010 # Average percentage of cache occupancy | 1891system.iocache.tags.warmup_cycle 269184120000 # Cycle when the warmup percentage was hit. 1892system.iocache.tags.occ_blocks::realview.ide 0.995239 # Average occupied blocks per requestor 1893system.iocache.tags.occ_percent::realview.ide 0.062202 # Average percentage of cache occupancy 1894system.iocache.tags.occ_percent::total 0.062202 # Average percentage of cache occupancy |
| 1895system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1896system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1897system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1895system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1896system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1897system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1898system.iocache.tags.tag_accesses 328467 # Number of tag accesses 1899system.iocache.tags.data_accesses 328467 # Number of data accesses 1900system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1901system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits | 1898system.iocache.tags.tag_accesses 328203 # Number of tag accesses 1899system.iocache.tags.data_accesses 328203 # Number of data accesses |
| 1902system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 1903system.iocache.ReadReq_misses::total 243 # number of ReadReq misses | 1900system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 1901system.iocache.ReadReq_misses::total 243 # number of ReadReq misses |
| 1904system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses 1905system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses | 1902system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1903system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses |
| 1906system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 1907system.iocache.demand_misses::total 243 # number of demand (read+write) misses 1908system.iocache.overall_misses::realview.ide 243 # number of overall misses 1909system.iocache.overall_misses::total 243 # number of overall misses | 1904system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 1905system.iocache.demand_misses::total 243 # number of demand (read+write) misses 1906system.iocache.overall_misses::realview.ide 243 # number of overall misses 1907system.iocache.overall_misses::total 243 # number of overall misses |
| 1910system.iocache.ReadReq_miss_latency::realview.ide 31254127 # number of ReadReq miss cycles 1911system.iocache.ReadReq_miss_latency::total 31254127 # number of ReadReq miss cycles 1912system.iocache.demand_miss_latency::realview.ide 31254127 # number of demand (read+write) miss cycles 1913system.iocache.demand_miss_latency::total 31254127 # number of demand (read+write) miss cycles 1914system.iocache.overall_miss_latency::realview.ide 31254127 # number of overall miss cycles 1915system.iocache.overall_miss_latency::total 31254127 # number of overall miss cycles | 1908system.iocache.ReadReq_miss_latency::realview.ide 30315377 # number of ReadReq miss cycles 1909system.iocache.ReadReq_miss_latency::total 30315377 # number of ReadReq miss cycles 1910system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9644186159 # number of WriteInvalidateReq miss cycles 1911system.iocache.WriteInvalidateReq_miss_latency::total 9644186159 # number of WriteInvalidateReq miss cycles 1912system.iocache.demand_miss_latency::realview.ide 30315377 # number of demand (read+write) miss cycles 1913system.iocache.demand_miss_latency::total 30315377 # number of demand (read+write) miss cycles 1914system.iocache.overall_miss_latency::realview.ide 30315377 # number of overall miss cycles 1915system.iocache.overall_miss_latency::total 30315377 # number of overall miss cycles |
| 1916system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 1917system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) | 1916system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 1917system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) |
| 1918system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) 1919system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) | 1918system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1919system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) |
| 1920system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 1921system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 1922system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 1923system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 1924system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1925system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 1920system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 1921system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 1922system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 1923system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 1924system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1925system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 1926system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses 1927system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses | 1926system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1927system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses |
| 1928system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1929system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1930system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1931system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1928system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1929system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1930system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1931system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1932system.iocache.ReadReq_avg_miss_latency::realview.ide 128617.806584 # average ReadReq miss latency 1933system.iocache.ReadReq_avg_miss_latency::total 128617.806584 # average ReadReq miss latency 1934system.iocache.demand_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency 1935system.iocache.demand_avg_miss_latency::total 128617.806584 # average overall miss latency 1936system.iocache.overall_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency 1937system.iocache.overall_avg_miss_latency::total 128617.806584 # average overall miss latency 1938system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1932system.iocache.ReadReq_avg_miss_latency::realview.ide 124754.637860 # average ReadReq miss latency 1933system.iocache.ReadReq_avg_miss_latency::total 124754.637860 # average ReadReq miss latency 1934system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266237.471262 # average WriteInvalidateReq miss latency 1935system.iocache.WriteInvalidateReq_avg_miss_latency::total 266237.471262 # average WriteInvalidateReq miss latency 1936system.iocache.demand_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency 1937system.iocache.demand_avg_miss_latency::total 124754.637860 # average overall miss latency 1938system.iocache.overall_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency 1939system.iocache.overall_avg_miss_latency::total 124754.637860 # average overall miss latency 1940system.iocache.blocked_cycles::no_mshrs 57278 # number of cycles access was blocked |
| 1939system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1941system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1940system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked | 1942system.iocache.blocked::no_mshrs 7269 # number of cycles access was blocked |
| 1941system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1943system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1942system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1944system.iocache.avg_blocked_cycles::no_mshrs 7.879763 # average number of cycles each access was blocked |
| 1943system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1945system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1944system.iocache.fast_writes 36224 # number of fast writes performed | 1946system.iocache.fast_writes 0 # number of fast writes performed |
| 1945system.iocache.cache_copies 0 # number of cache copies performed | 1947system.iocache.cache_copies 0 # number of cache copies performed |
| 1948system.iocache.writebacks::writebacks 36190 # number of writebacks 1949system.iocache.writebacks::total 36190 # number of writebacks |
|
| 1946system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 1947system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses | 1950system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 1951system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses |
| 1952system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1953system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses |
|
| 1948system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 1949system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 1950system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 1951system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses | 1954system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 1955system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 1956system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 1957system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses |
| 1952system.iocache.ReadReq_mshr_miss_latency::realview.ide 18617627 # number of ReadReq MSHR miss cycles 1953system.iocache.ReadReq_mshr_miss_latency::total 18617627 # number of ReadReq MSHR miss cycles 1954system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2261621825 # number of WriteInvalidateReq MSHR miss cycles 1955system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2261621825 # number of WriteInvalidateReq MSHR miss cycles 1956system.iocache.demand_mshr_miss_latency::realview.ide 18617627 # number of demand (read+write) MSHR miss cycles 1957system.iocache.demand_mshr_miss_latency::total 18617627 # number of demand (read+write) MSHR miss cycles 1958system.iocache.overall_mshr_miss_latency::realview.ide 18617627 # number of overall MSHR miss cycles 1959system.iocache.overall_mshr_miss_latency::total 18617627 # number of overall MSHR miss cycles | 1958system.iocache.ReadReq_mshr_miss_latency::realview.ide 17678377 # number of ReadReq MSHR miss cycles 1959system.iocache.ReadReq_mshr_miss_latency::total 17678377 # number of ReadReq MSHR miss cycles 1960system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7760326371 # number of WriteInvalidateReq MSHR miss cycles 1961system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7760326371 # number of WriteInvalidateReq MSHR miss cycles 1962system.iocache.demand_mshr_miss_latency::realview.ide 17678377 # number of demand (read+write) MSHR miss cycles 1963system.iocache.demand_mshr_miss_latency::total 17678377 # number of demand (read+write) MSHR miss cycles 1964system.iocache.overall_mshr_miss_latency::realview.ide 17678377 # number of overall MSHR miss cycles 1965system.iocache.overall_mshr_miss_latency::total 17678377 # number of overall MSHR miss cycles |
| 1960system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1961system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 1966system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1967system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 1968system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1969system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses |
|
| 1962system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1963system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1964system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1965system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1970system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1971system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1972system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1973system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1966system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76615.748971 # average ReadReq mshr miss latency 1967system.iocache.ReadReq_avg_mshr_miss_latency::total 76615.748971 # average ReadReq mshr miss latency 1968system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1969system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1970system.iocache.demand_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency 1971system.iocache.demand_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency 1972system.iocache.overall_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency 1973system.iocache.overall_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency | 1974system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72750.522634 # average ReadReq mshr miss latency 1975system.iocache.ReadReq_avg_mshr_miss_latency::total 72750.522634 # average ReadReq mshr miss latency 1976system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214231.624641 # average WriteInvalidateReq mshr miss latency 1977system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214231.624641 # average WriteInvalidateReq mshr miss latency 1978system.iocache.demand_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency 1979system.iocache.demand_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency 1980system.iocache.overall_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency 1981system.iocache.overall_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency |
| 1974system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1982system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1975system.l2c.tags.replacements 151810 # number of replacements 1976system.l2c.tags.tagsinuse 64480.586594 # Cycle average of tags in use 1977system.l2c.tags.total_refs 529933 # Total number of references to valid blocks. 1978system.l2c.tags.sampled_refs 216565 # Sample count of references to valid blocks. 1979system.l2c.tags.avg_refs 2.446993 # Average number of references to valid blocks. | 1983system.l2c.tags.replacements 150396 # number of replacements 1984system.l2c.tags.tagsinuse 64479.883220 # Cycle average of tags in use 1985system.l2c.tags.total_refs 522727 # Total number of references to valid blocks. 1986system.l2c.tags.sampled_refs 215317 # Sample count of references to valid blocks. 1987system.l2c.tags.avg_refs 2.427709 # Average number of references to valid blocks. |
| 1980system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1988system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1981system.l2c.tags.occ_blocks::writebacks 12374.174406 # Average occupied blocks per requestor 1982system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831156 # Average occupied blocks per requestor 1983system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030524 # Average occupied blocks per requestor 1984system.l2c.tags.occ_blocks::cpu0.inst 3874.361594 # Average occupied blocks per requestor 1985system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42727.383721 # Average occupied blocks per requestor 1986system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.891665 # Average occupied blocks per requestor 1987system.l2c.tags.occ_blocks::cpu1.inst 757.615436 # Average occupied blocks per requestor 1988system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4654.298093 # Average occupied blocks per requestor 1989system.l2c.tags.occ_percent::writebacks 0.188815 # Average percentage of cache occupancy 1990system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy 1991system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1992system.l2c.tags.occ_percent::cpu0.inst 0.059118 # Average percentage of cache occupancy 1993system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.651968 # Average percentage of cache occupancy 1994system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy 1995system.l2c.tags.occ_percent::cpu1.inst 0.011560 # Average percentage of cache occupancy 1996system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071019 # Average percentage of cache occupancy 1997system.l2c.tags.occ_percent::total 0.983896 # Average percentage of cache occupancy 1998system.l2c.tags.occ_task_id_blocks::1022 46322 # Occupied blocks per task id 1999system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id 2000system.l2c.tags.occ_task_id_blocks::1024 18386 # Occupied blocks per task id 2001system.l2c.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id 2002system.l2c.tags.age_task_id_blocks_1022::3 6596 # Occupied blocks per task id 2003system.l2c.tags.age_task_id_blocks_1022::4 39440 # Occupied blocks per task id 2004system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id 2005system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 2006system.l2c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 2007system.l2c.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id 2008system.l2c.tags.age_task_id_blocks_1024::3 2604 # Occupied blocks per task id 2009system.l2c.tags.age_task_id_blocks_1024::4 15495 # Occupied blocks per task id 2010system.l2c.tags.occ_task_id_percent::1022 0.706818 # Percentage of cache occupancy per task id 2011system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id 2012system.l2c.tags.occ_task_id_percent::1024 0.280548 # Percentage of cache occupancy per task id 2013system.l2c.tags.tag_accesses 6644341 # Number of tag accesses 2014system.l2c.tags.data_accesses 6644341 # Number of data accesses 2015system.l2c.ReadReq_hits::cpu0.dtb.walker 563 # number of ReadReq hits 2016system.l2c.ReadReq_hits::cpu0.itb.walker 116 # number of ReadReq hits 2017system.l2c.ReadReq_hits::cpu0.inst 36701 # number of ReadReq hits 2018system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207577 # number of ReadReq hits 2019system.l2c.ReadReq_hits::cpu1.dtb.walker 129 # number of ReadReq hits 2020system.l2c.ReadReq_hits::cpu1.itb.walker 56 # number of ReadReq hits 2021system.l2c.ReadReq_hits::cpu1.inst 11433 # number of ReadReq hits 2022system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45418 # number of ReadReq hits 2023system.l2c.ReadReq_hits::total 301993 # number of ReadReq hits 2024system.l2c.Writeback_hits::writebacks 252536 # number of Writeback hits 2025system.l2c.Writeback_hits::total 252536 # number of Writeback hits 2026system.l2c.UpgradeReq_hits::cpu0.inst 11942 # number of UpgradeReq hits 2027system.l2c.UpgradeReq_hits::cpu1.inst 830 # number of UpgradeReq hits 2028system.l2c.UpgradeReq_hits::total 12772 # number of UpgradeReq hits 2029system.l2c.SCUpgradeReq_hits::cpu0.inst 205 # number of SCUpgradeReq hits 2030system.l2c.SCUpgradeReq_hits::cpu1.inst 179 # number of SCUpgradeReq hits 2031system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits 2032system.l2c.ReadExReq_hits::cpu0.inst 3525 # number of ReadExReq hits 2033system.l2c.ReadExReq_hits::cpu1.inst 1107 # number of ReadExReq hits 2034system.l2c.ReadExReq_hits::total 4632 # number of ReadExReq hits 2035system.l2c.demand_hits::cpu0.dtb.walker 563 # number of demand (read+write) hits 2036system.l2c.demand_hits::cpu0.itb.walker 116 # number of demand (read+write) hits 2037system.l2c.demand_hits::cpu0.inst 40226 # number of demand (read+write) hits 2038system.l2c.demand_hits::cpu0.l2cache.prefetcher 207577 # number of demand (read+write) hits 2039system.l2c.demand_hits::cpu1.dtb.walker 129 # number of demand (read+write) hits 2040system.l2c.demand_hits::cpu1.itb.walker 56 # number of demand (read+write) hits 2041system.l2c.demand_hits::cpu1.inst 12540 # number of demand (read+write) hits 2042system.l2c.demand_hits::cpu1.l2cache.prefetcher 45418 # number of demand (read+write) hits 2043system.l2c.demand_hits::total 306625 # number of demand (read+write) hits 2044system.l2c.overall_hits::cpu0.dtb.walker 563 # number of overall hits 2045system.l2c.overall_hits::cpu0.itb.walker 116 # number of overall hits 2046system.l2c.overall_hits::cpu0.inst 40226 # number of overall hits 2047system.l2c.overall_hits::cpu0.l2cache.prefetcher 207577 # number of overall hits 2048system.l2c.overall_hits::cpu1.dtb.walker 129 # number of overall hits 2049system.l2c.overall_hits::cpu1.itb.walker 56 # number of overall hits 2050system.l2c.overall_hits::cpu1.inst 12540 # number of overall hits 2051system.l2c.overall_hits::cpu1.l2cache.prefetcher 45418 # number of overall hits 2052system.l2c.overall_hits::total 306625 # number of overall hits 2053system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses | 1989system.l2c.tags.occ_blocks::writebacks 12469.492368 # Average occupied blocks per requestor 1990system.l2c.tags.occ_blocks::cpu0.dtb.walker 93.733463 # Average occupied blocks per requestor 1991system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999899 # Average occupied blocks per requestor 1992system.l2c.tags.occ_blocks::cpu0.inst 3818.005633 # Average occupied blocks per requestor 1993system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42810.602787 # Average occupied blocks per requestor 1994system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.718540 # Average occupied blocks per requestor 1995system.l2c.tags.occ_blocks::cpu1.inst 732.215158 # Average occupied blocks per requestor 1996system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4549.115372 # Average occupied blocks per requestor 1997system.l2c.tags.occ_percent::writebacks 0.190269 # Average percentage of cache occupancy 1998system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001430 # Average percentage of cache occupancy 1999system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 2000system.l2c.tags.occ_percent::cpu0.inst 0.058258 # Average percentage of cache occupancy 2001system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.653238 # Average percentage of cache occupancy 2002system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy 2003system.l2c.tags.occ_percent::cpu1.inst 0.011173 # Average percentage of cache occupancy 2004system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.069414 # Average percentage of cache occupancy 2005system.l2c.tags.occ_percent::total 0.983885 # Average percentage of cache occupancy 2006system.l2c.tags.occ_task_id_blocks::1022 47457 # Occupied blocks per task id 2007system.l2c.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 2008system.l2c.tags.occ_task_id_blocks::1024 17396 # Occupied blocks per task id 2009system.l2c.tags.age_task_id_blocks_1022::2 475 # Occupied blocks per task id 2010system.l2c.tags.age_task_id_blocks_1022::3 6086 # Occupied blocks per task id 2011system.l2c.tags.age_task_id_blocks_1022::4 40896 # Occupied blocks per task id 2012system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2013system.l2c.tags.age_task_id_blocks_1023::4 67 # Occupied blocks per task id 2014system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2015system.l2c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 2016system.l2c.tags.age_task_id_blocks_1024::2 270 # Occupied blocks per task id 2017system.l2c.tags.age_task_id_blocks_1024::3 2310 # Occupied blocks per task id 2018system.l2c.tags.age_task_id_blocks_1024::4 14797 # Occupied blocks per task id 2019system.l2c.tags.occ_task_id_percent::1022 0.724136 # Percentage of cache occupancy per task id 2020system.l2c.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id 2021system.l2c.tags.occ_task_id_percent::1024 0.265442 # Percentage of cache occupancy per task id 2022system.l2c.tags.tag_accesses 6561930 # Number of tag accesses 2023system.l2c.tags.data_accesses 6561930 # Number of data accesses 2024system.l2c.ReadReq_hits::cpu0.dtb.walker 576 # number of ReadReq hits 2025system.l2c.ReadReq_hits::cpu0.itb.walker 131 # number of ReadReq hits 2026system.l2c.ReadReq_hits::cpu0.inst 39519 # number of ReadReq hits 2027system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 221242 # number of ReadReq hits 2028system.l2c.ReadReq_hits::cpu1.dtb.walker 94 # number of ReadReq hits 2029system.l2c.ReadReq_hits::cpu1.itb.walker 19 # number of ReadReq hits 2030system.l2c.ReadReq_hits::cpu1.inst 6900 # number of ReadReq hits 2031system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 25945 # number of ReadReq hits 2032system.l2c.ReadReq_hits::total 294426 # number of ReadReq hits 2033system.l2c.Writeback_hits::writebacks 250431 # number of Writeback hits 2034system.l2c.Writeback_hits::total 250431 # number of Writeback hits 2035system.l2c.UpgradeReq_hits::cpu0.inst 11782 # number of UpgradeReq hits 2036system.l2c.UpgradeReq_hits::cpu1.inst 481 # number of UpgradeReq hits 2037system.l2c.UpgradeReq_hits::total 12263 # number of UpgradeReq hits 2038system.l2c.SCUpgradeReq_hits::cpu0.inst 184 # number of SCUpgradeReq hits 2039system.l2c.SCUpgradeReq_hits::cpu1.inst 192 # number of SCUpgradeReq hits 2040system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits 2041system.l2c.ReadExReq_hits::cpu0.inst 3646 # number of ReadExReq hits 2042system.l2c.ReadExReq_hits::cpu1.inst 908 # number of ReadExReq hits 2043system.l2c.ReadExReq_hits::total 4554 # number of ReadExReq hits 2044system.l2c.demand_hits::cpu0.dtb.walker 576 # number of demand (read+write) hits 2045system.l2c.demand_hits::cpu0.itb.walker 131 # number of demand (read+write) hits 2046system.l2c.demand_hits::cpu0.inst 43165 # number of demand (read+write) hits 2047system.l2c.demand_hits::cpu0.l2cache.prefetcher 221242 # number of demand (read+write) hits 2048system.l2c.demand_hits::cpu1.dtb.walker 94 # number of demand (read+write) hits 2049system.l2c.demand_hits::cpu1.itb.walker 19 # number of demand (read+write) hits 2050system.l2c.demand_hits::cpu1.inst 7808 # number of demand (read+write) hits 2051system.l2c.demand_hits::cpu1.l2cache.prefetcher 25945 # number of demand (read+write) hits 2052system.l2c.demand_hits::total 298980 # number of demand (read+write) hits 2053system.l2c.overall_hits::cpu0.dtb.walker 576 # number of overall hits 2054system.l2c.overall_hits::cpu0.itb.walker 131 # number of overall hits 2055system.l2c.overall_hits::cpu0.inst 43165 # number of overall hits 2056system.l2c.overall_hits::cpu0.l2cache.prefetcher 221242 # number of overall hits 2057system.l2c.overall_hits::cpu1.dtb.walker 94 # number of overall hits 2058system.l2c.overall_hits::cpu1.itb.walker 19 # number of overall hits 2059system.l2c.overall_hits::cpu1.inst 7808 # number of overall hits 2060system.l2c.overall_hits::cpu1.l2cache.prefetcher 25945 # number of overall hits 2061system.l2c.overall_hits::total 298980 # number of overall hits 2062system.l2c.ReadReq_misses::cpu0.dtb.walker 161 # number of ReadReq misses |
| 2054system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses | 2063system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses |
| 2055system.l2c.ReadReq_misses::cpu0.inst 11286 # number of ReadReq misses 2056system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq misses 2057system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses 2058system.l2c.ReadReq_misses::cpu1.inst 1852 # number of ReadReq misses 2059system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18208 # number of ReadReq misses 2060system.l2c.ReadReq_misses::total 199810 # number of ReadReq misses 2061system.l2c.UpgradeReq_misses::cpu0.inst 9028 # number of UpgradeReq misses 2062system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses 2063system.l2c.UpgradeReq_misses::total 11693 # number of UpgradeReq misses 2064system.l2c.SCUpgradeReq_misses::cpu0.inst 461 # number of SCUpgradeReq misses 2065system.l2c.SCUpgradeReq_misses::cpu1.inst 1254 # number of SCUpgradeReq misses 2066system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses 2067system.l2c.ReadExReq_misses::cpu0.inst 7011 # number of ReadExReq misses 2068system.l2c.ReadExReq_misses::cpu1.inst 6410 # number of ReadExReq misses 2069system.l2c.ReadExReq_misses::total 13421 # number of ReadExReq misses 2070system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses | 2064system.l2c.ReadReq_misses::cpu0.inst 11256 # number of ReadReq misses 2065system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 169617 # number of ReadReq misses 2066system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses 2067system.l2c.ReadReq_misses::cpu1.inst 1341 # number of ReadReq misses 2068system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 17501 # number of ReadReq misses 2069system.l2c.ReadReq_misses::total 199885 # number of ReadReq misses 2070system.l2c.UpgradeReq_misses::cpu0.inst 9580 # number of UpgradeReq misses 2071system.l2c.UpgradeReq_misses::cpu1.inst 2241 # number of UpgradeReq misses 2072system.l2c.UpgradeReq_misses::total 11821 # number of UpgradeReq misses 2073system.l2c.SCUpgradeReq_misses::cpu0.inst 527 # number of SCUpgradeReq misses 2074system.l2c.SCUpgradeReq_misses::cpu1.inst 1214 # number of SCUpgradeReq misses 2075system.l2c.SCUpgradeReq_misses::total 1741 # number of SCUpgradeReq misses 2076system.l2c.ReadExReq_misses::cpu0.inst 6969 # number of ReadExReq misses 2077system.l2c.ReadExReq_misses::cpu1.inst 6429 # number of ReadExReq misses 2078system.l2c.ReadExReq_misses::total 13398 # number of ReadExReq misses 2079system.l2c.demand_misses::cpu0.dtb.walker 161 # number of demand (read+write) misses |
| 2071system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses | 2080system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses |
| 2072system.l2c.demand_misses::cpu0.inst 18297 # number of demand (read+write) misses 2073system.l2c.demand_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) misses 2074system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses 2075system.l2c.demand_misses::cpu1.inst 8262 # number of demand (read+write) misses 2076system.l2c.demand_misses::cpu1.l2cache.prefetcher 18208 # number of demand (read+write) misses 2077system.l2c.demand_misses::total 213231 # number of demand (read+write) misses 2078system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses | 2081system.l2c.demand_misses::cpu0.inst 18225 # number of demand (read+write) misses 2082system.l2c.demand_misses::cpu0.l2cache.prefetcher 169617 # number of demand (read+write) misses 2083system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses 2084system.l2c.demand_misses::cpu1.inst 7770 # number of demand (read+write) misses 2085system.l2c.demand_misses::cpu1.l2cache.prefetcher 17501 # number of demand (read+write) misses 2086system.l2c.demand_misses::total 213283 # number of demand (read+write) misses 2087system.l2c.overall_misses::cpu0.dtb.walker 161 # number of overall misses |
| 2079system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses | 2088system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses |
| 2080system.l2c.overall_misses::cpu0.inst 18297 # number of overall misses 2081system.l2c.overall_misses::cpu0.l2cache.prefetcher 168297 # number of overall misses 2082system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses 2083system.l2c.overall_misses::cpu1.inst 8262 # number of overall misses 2084system.l2c.overall_misses::cpu1.l2cache.prefetcher 18208 # number of overall misses 2085system.l2c.overall_misses::total 213231 # number of overall misses 2086system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles | 2089system.l2c.overall_misses::cpu0.inst 18225 # number of overall misses 2090system.l2c.overall_misses::cpu0.l2cache.prefetcher 169617 # number of overall misses 2091system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses 2092system.l2c.overall_misses::cpu1.inst 7770 # number of overall misses 2093system.l2c.overall_misses::cpu1.l2cache.prefetcher 17501 # number of overall misses 2094system.l2c.overall_misses::total 213283 # number of overall misses 2095system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 12824000 # number of ReadReq miss cycles |
| 2087system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles | 2096system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles |
| 2088system.l2c.ReadReq_miss_latency::cpu0.inst 955847998 # number of ReadReq miss cycles 2089system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of ReadReq miss cycles 2090system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1150500 # number of ReadReq miss cycles 2091system.l2c.ReadReq_miss_latency::cpu1.inst 151717498 # number of ReadReq miss cycles 2092system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of ReadReq miss cycles 2093system.l2c.ReadReq_miss_latency::total 21276600608 # number of ReadReq miss cycles 2094system.l2c.UpgradeReq_miss_latency::cpu0.inst 10528075 # number of UpgradeReq miss cycles 2095system.l2c.UpgradeReq_miss_latency::cpu1.inst 2736385 # number of UpgradeReq miss cycles 2096system.l2c.UpgradeReq_miss_latency::total 13264460 # number of UpgradeReq miss cycles 2097system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1131453 # number of SCUpgradeReq miss cycles 2098system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1006958 # number of SCUpgradeReq miss cycles 2099system.l2c.SCUpgradeReq_miss_latency::total 2138411 # number of SCUpgradeReq miss cycles 2100system.l2c.ReadExReq_miss_latency::cpu0.inst 592519659 # number of ReadExReq miss cycles 2101system.l2c.ReadExReq_miss_latency::cpu1.inst 475914481 # number of ReadExReq miss cycles 2102system.l2c.ReadExReq_miss_latency::total 1068434140 # number of ReadExReq miss cycles 2103system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles | 2097system.l2c.ReadReq_miss_latency::cpu0.inst 957656246 # number of ReadReq miss cycles 2098system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of ReadReq miss cycles 2099system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 597000 # number of ReadReq miss cycles 2100system.l2c.ReadReq_miss_latency::cpu1.inst 113197750 # number of ReadReq miss cycles 2101system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of ReadReq miss cycles 2102system.l2c.ReadReq_miss_latency::total 21264707667 # number of ReadReq miss cycles 2103system.l2c.UpgradeReq_miss_latency::cpu0.inst 10249624 # number of UpgradeReq miss cycles 2104system.l2c.UpgradeReq_miss_latency::cpu1.inst 2389898 # number of UpgradeReq miss cycles 2105system.l2c.UpgradeReq_miss_latency::total 12639522 # number of UpgradeReq miss cycles 2106system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1315451 # number of SCUpgradeReq miss cycles 2107system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1074955 # number of SCUpgradeReq miss cycles 2108system.l2c.SCUpgradeReq_miss_latency::total 2390406 # number of SCUpgradeReq miss cycles 2109system.l2c.ReadExReq_miss_latency::cpu0.inst 593841904 # number of ReadExReq miss cycles 2110system.l2c.ReadExReq_miss_latency::cpu1.inst 477642745 # number of ReadExReq miss cycles 2111system.l2c.ReadExReq_miss_latency::total 1071484649 # number of ReadExReq miss cycles 2112system.l2c.demand_miss_latency::cpu0.dtb.walker 12824000 # number of demand (read+write) miss cycles |
| 2104system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles | 2113system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles |
| 2105system.l2c.demand_miss_latency::cpu0.inst 1548367657 # number of demand (read+write) miss cycles 2106system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of demand (read+write) miss cycles 2107system.l2c.demand_miss_latency::cpu1.dtb.walker 1150500 # number of demand (read+write) miss cycles 2108system.l2c.demand_miss_latency::cpu1.inst 627631979 # number of demand (read+write) miss cycles 2109system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of demand (read+write) miss cycles 2110system.l2c.demand_miss_latency::total 22345034748 # number of demand (read+write) miss cycles 2111system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles | 2114system.l2c.demand_miss_latency::cpu0.inst 1551498150 # number of demand (read+write) miss cycles 2115system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of demand (read+write) miss cycles 2116system.l2c.demand_miss_latency::cpu1.dtb.walker 597000 # number of demand (read+write) miss cycles 2117system.l2c.demand_miss_latency::cpu1.inst 590840495 # number of demand (read+write) miss cycles 2118system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of demand (read+write) miss cycles 2119system.l2c.demand_miss_latency::total 22336192316 # number of demand (read+write) miss cycles 2120system.l2c.overall_miss_latency::cpu0.dtb.walker 12824000 # number of overall miss cycles |
| 2112system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles | 2121system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles |
| 2113system.l2c.overall_miss_latency::cpu0.inst 1548367657 # number of overall miss cycles 2114system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of overall miss cycles 2115system.l2c.overall_miss_latency::cpu1.dtb.walker 1150500 # number of overall miss cycles 2116system.l2c.overall_miss_latency::cpu1.inst 627631979 # number of overall miss cycles 2117system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of overall miss cycles 2118system.l2c.overall_miss_latency::total 22345034748 # number of overall miss cycles 2119system.l2c.ReadReq_accesses::cpu0.dtb.walker 714 # number of ReadReq accesses(hits+misses) 2120system.l2c.ReadReq_accesses::cpu0.itb.walker 117 # number of ReadReq accesses(hits+misses) 2121system.l2c.ReadReq_accesses::cpu0.inst 47987 # number of ReadReq accesses(hits+misses) 2122system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 375874 # number of ReadReq accesses(hits+misses) 2123system.l2c.ReadReq_accesses::cpu1.dtb.walker 144 # number of ReadReq accesses(hits+misses) 2124system.l2c.ReadReq_accesses::cpu1.itb.walker 56 # number of ReadReq accesses(hits+misses) 2125system.l2c.ReadReq_accesses::cpu1.inst 13285 # number of ReadReq accesses(hits+misses) 2126system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63626 # number of ReadReq accesses(hits+misses) 2127system.l2c.ReadReq_accesses::total 501803 # number of ReadReq accesses(hits+misses) 2128system.l2c.Writeback_accesses::writebacks 252536 # number of Writeback accesses(hits+misses) 2129system.l2c.Writeback_accesses::total 252536 # number of Writeback accesses(hits+misses) 2130system.l2c.UpgradeReq_accesses::cpu0.inst 20970 # number of UpgradeReq accesses(hits+misses) 2131system.l2c.UpgradeReq_accesses::cpu1.inst 3495 # number of UpgradeReq accesses(hits+misses) 2132system.l2c.UpgradeReq_accesses::total 24465 # number of UpgradeReq accesses(hits+misses) 2133system.l2c.SCUpgradeReq_accesses::cpu0.inst 666 # number of SCUpgradeReq accesses(hits+misses) 2134system.l2c.SCUpgradeReq_accesses::cpu1.inst 1433 # number of SCUpgradeReq accesses(hits+misses) 2135system.l2c.SCUpgradeReq_accesses::total 2099 # number of SCUpgradeReq accesses(hits+misses) 2136system.l2c.ReadExReq_accesses::cpu0.inst 10536 # number of ReadExReq accesses(hits+misses) 2137system.l2c.ReadExReq_accesses::cpu1.inst 7517 # number of ReadExReq accesses(hits+misses) 2138system.l2c.ReadExReq_accesses::total 18053 # number of ReadExReq accesses(hits+misses) 2139system.l2c.demand_accesses::cpu0.dtb.walker 714 # number of demand (read+write) accesses 2140system.l2c.demand_accesses::cpu0.itb.walker 117 # number of demand (read+write) accesses 2141system.l2c.demand_accesses::cpu0.inst 58523 # number of demand (read+write) accesses 2142system.l2c.demand_accesses::cpu0.l2cache.prefetcher 375874 # number of demand (read+write) accesses 2143system.l2c.demand_accesses::cpu1.dtb.walker 144 # number of demand (read+write) accesses 2144system.l2c.demand_accesses::cpu1.itb.walker 56 # number of demand (read+write) accesses 2145system.l2c.demand_accesses::cpu1.inst 20802 # number of demand (read+write) accesses 2146system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63626 # number of demand (read+write) accesses 2147system.l2c.demand_accesses::total 519856 # number of demand (read+write) accesses 2148system.l2c.overall_accesses::cpu0.dtb.walker 714 # number of overall (read+write) accesses 2149system.l2c.overall_accesses::cpu0.itb.walker 117 # number of overall (read+write) accesses 2150system.l2c.overall_accesses::cpu0.inst 58523 # number of overall (read+write) accesses 2151system.l2c.overall_accesses::cpu0.l2cache.prefetcher 375874 # number of overall (read+write) accesses 2152system.l2c.overall_accesses::cpu1.dtb.walker 144 # number of overall (read+write) accesses 2153system.l2c.overall_accesses::cpu1.itb.walker 56 # number of overall (read+write) accesses 2154system.l2c.overall_accesses::cpu1.inst 20802 # number of overall (read+write) accesses 2155system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63626 # number of overall (read+write) accesses 2156system.l2c.overall_accesses::total 519856 # number of overall (read+write) accesses 2157system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for ReadReq accesses 2158system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008547 # miss rate for ReadReq accesses 2159system.l2c.ReadReq_miss_rate::cpu0.inst 0.235189 # miss rate for ReadReq accesses 2160system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for ReadReq accesses 2161system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for ReadReq accesses 2162system.l2c.ReadReq_miss_rate::cpu1.inst 0.139405 # miss rate for ReadReq accesses 2163system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for ReadReq accesses 2164system.l2c.ReadReq_miss_rate::total 0.398184 # miss rate for ReadReq accesses 2165system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430520 # miss rate for UpgradeReq accesses 2166system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.762518 # miss rate for UpgradeReq accesses 2167system.l2c.UpgradeReq_miss_rate::total 0.477948 # miss rate for UpgradeReq accesses 2168system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.692192 # miss rate for SCUpgradeReq accesses 2169system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.875087 # miss rate for SCUpgradeReq accesses 2170system.l2c.SCUpgradeReq_miss_rate::total 0.817056 # miss rate for SCUpgradeReq accesses 2171system.l2c.ReadExReq_miss_rate::cpu0.inst 0.665433 # miss rate for ReadExReq accesses 2172system.l2c.ReadExReq_miss_rate::cpu1.inst 0.852734 # miss rate for ReadExReq accesses 2173system.l2c.ReadExReq_miss_rate::total 0.743422 # miss rate for ReadExReq accesses 2174system.l2c.demand_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for demand accesses 2175system.l2c.demand_miss_rate::cpu0.itb.walker 0.008547 # miss rate for demand accesses 2176system.l2c.demand_miss_rate::cpu0.inst 0.312646 # miss rate for demand accesses 2177system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for demand accesses 2178system.l2c.demand_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for demand accesses 2179system.l2c.demand_miss_rate::cpu1.inst 0.397173 # miss rate for demand accesses 2180system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for demand accesses 2181system.l2c.demand_miss_rate::total 0.410173 # miss rate for demand accesses 2182system.l2c.overall_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for overall accesses 2183system.l2c.overall_miss_rate::cpu0.itb.walker 0.008547 # miss rate for overall accesses 2184system.l2c.overall_miss_rate::cpu0.inst 0.312646 # miss rate for overall accesses 2185system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for overall accesses 2186system.l2c.overall_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for overall accesses 2187system.l2c.overall_miss_rate::cpu1.inst 0.397173 # miss rate for overall accesses 2188system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for overall accesses 2189system.l2c.overall_miss_rate::total 0.410173 # miss rate for overall accesses 2190system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency | 2122system.l2c.overall_miss_latency::cpu0.inst 1551498150 # number of overall miss cycles 2123system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of overall miss cycles 2124system.l2c.overall_miss_latency::cpu1.dtb.walker 597000 # number of overall miss cycles 2125system.l2c.overall_miss_latency::cpu1.inst 590840495 # number of overall miss cycles 2126system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of overall miss cycles 2127system.l2c.overall_miss_latency::total 22336192316 # number of overall miss cycles 2128system.l2c.ReadReq_accesses::cpu0.dtb.walker 737 # number of ReadReq accesses(hits+misses) 2129system.l2c.ReadReq_accesses::cpu0.itb.walker 132 # number of ReadReq accesses(hits+misses) 2130system.l2c.ReadReq_accesses::cpu0.inst 50775 # number of ReadReq accesses(hits+misses) 2131system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 390859 # number of ReadReq accesses(hits+misses) 2132system.l2c.ReadReq_accesses::cpu1.dtb.walker 102 # number of ReadReq accesses(hits+misses) 2133system.l2c.ReadReq_accesses::cpu1.itb.walker 19 # number of ReadReq accesses(hits+misses) 2134system.l2c.ReadReq_accesses::cpu1.inst 8241 # number of ReadReq accesses(hits+misses) 2135system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 43446 # number of ReadReq accesses(hits+misses) 2136system.l2c.ReadReq_accesses::total 494311 # number of ReadReq accesses(hits+misses) 2137system.l2c.Writeback_accesses::writebacks 250431 # number of Writeback accesses(hits+misses) 2138system.l2c.Writeback_accesses::total 250431 # number of Writeback accesses(hits+misses) 2139system.l2c.UpgradeReq_accesses::cpu0.inst 21362 # number of UpgradeReq accesses(hits+misses) 2140system.l2c.UpgradeReq_accesses::cpu1.inst 2722 # number of UpgradeReq accesses(hits+misses) 2141system.l2c.UpgradeReq_accesses::total 24084 # number of UpgradeReq accesses(hits+misses) 2142system.l2c.SCUpgradeReq_accesses::cpu0.inst 711 # number of SCUpgradeReq accesses(hits+misses) 2143system.l2c.SCUpgradeReq_accesses::cpu1.inst 1406 # number of SCUpgradeReq accesses(hits+misses) 2144system.l2c.SCUpgradeReq_accesses::total 2117 # number of SCUpgradeReq accesses(hits+misses) 2145system.l2c.ReadExReq_accesses::cpu0.inst 10615 # number of ReadExReq accesses(hits+misses) 2146system.l2c.ReadExReq_accesses::cpu1.inst 7337 # number of ReadExReq accesses(hits+misses) 2147system.l2c.ReadExReq_accesses::total 17952 # number of ReadExReq accesses(hits+misses) 2148system.l2c.demand_accesses::cpu0.dtb.walker 737 # number of demand (read+write) accesses 2149system.l2c.demand_accesses::cpu0.itb.walker 132 # number of demand (read+write) accesses 2150system.l2c.demand_accesses::cpu0.inst 61390 # number of demand (read+write) accesses 2151system.l2c.demand_accesses::cpu0.l2cache.prefetcher 390859 # number of demand (read+write) accesses 2152system.l2c.demand_accesses::cpu1.dtb.walker 102 # number of demand (read+write) accesses 2153system.l2c.demand_accesses::cpu1.itb.walker 19 # number of demand (read+write) accesses 2154system.l2c.demand_accesses::cpu1.inst 15578 # number of demand (read+write) accesses 2155system.l2c.demand_accesses::cpu1.l2cache.prefetcher 43446 # number of demand (read+write) accesses 2156system.l2c.demand_accesses::total 512263 # number of demand (read+write) accesses 2157system.l2c.overall_accesses::cpu0.dtb.walker 737 # number of overall (read+write) accesses 2158system.l2c.overall_accesses::cpu0.itb.walker 132 # number of overall (read+write) accesses 2159system.l2c.overall_accesses::cpu0.inst 61390 # number of overall (read+write) accesses 2160system.l2c.overall_accesses::cpu0.l2cache.prefetcher 390859 # number of overall (read+write) accesses 2161system.l2c.overall_accesses::cpu1.dtb.walker 102 # number of overall (read+write) accesses 2162system.l2c.overall_accesses::cpu1.itb.walker 19 # number of overall (read+write) accesses 2163system.l2c.overall_accesses::cpu1.inst 15578 # number of overall (read+write) accesses 2164system.l2c.overall_accesses::cpu1.l2cache.prefetcher 43446 # number of overall (read+write) accesses 2165system.l2c.overall_accesses::total 512263 # number of overall (read+write) accesses 2166system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for ReadReq accesses 2167system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007576 # miss rate for ReadReq accesses 2168system.l2c.ReadReq_miss_rate::cpu0.inst 0.221684 # miss rate for ReadReq accesses 2169system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for ReadReq accesses 2170system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for ReadReq accesses 2171system.l2c.ReadReq_miss_rate::cpu1.inst 0.162723 # miss rate for ReadReq accesses 2172system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for ReadReq accesses 2173system.l2c.ReadReq_miss_rate::total 0.404371 # miss rate for ReadReq accesses 2174system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.448460 # miss rate for UpgradeReq accesses 2175system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.823292 # miss rate for UpgradeReq accesses 2176system.l2c.UpgradeReq_miss_rate::total 0.490824 # miss rate for UpgradeReq accesses 2177system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.741210 # miss rate for SCUpgradeReq accesses 2178system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.863442 # miss rate for SCUpgradeReq accesses 2179system.l2c.SCUpgradeReq_miss_rate::total 0.822390 # miss rate for SCUpgradeReq accesses 2180system.l2c.ReadExReq_miss_rate::cpu0.inst 0.656524 # miss rate for ReadExReq accesses 2181system.l2c.ReadExReq_miss_rate::cpu1.inst 0.876244 # miss rate for ReadExReq accesses 2182system.l2c.ReadExReq_miss_rate::total 0.746324 # miss rate for ReadExReq accesses 2183system.l2c.demand_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for demand accesses 2184system.l2c.demand_miss_rate::cpu0.itb.walker 0.007576 # miss rate for demand accesses 2185system.l2c.demand_miss_rate::cpu0.inst 0.296872 # miss rate for demand accesses 2186system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for demand accesses 2187system.l2c.demand_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for demand accesses 2188system.l2c.demand_miss_rate::cpu1.inst 0.498780 # miss rate for demand accesses 2189system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for demand accesses 2190system.l2c.demand_miss_rate::total 0.416354 # miss rate for demand accesses 2191system.l2c.overall_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for overall accesses 2192system.l2c.overall_miss_rate::cpu0.itb.walker 0.007576 # miss rate for overall accesses 2193system.l2c.overall_miss_rate::cpu0.inst 0.296872 # miss rate for overall accesses 2194system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for overall accesses 2195system.l2c.overall_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for overall accesses 2196system.l2c.overall_miss_rate::cpu1.inst 0.498780 # miss rate for overall accesses 2197system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for overall accesses 2198system.l2c.overall_miss_rate::total 0.416354 # miss rate for overall accesses 2199system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average ReadReq miss latency |
| 2191system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency | 2200system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency |
| 2192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84693.248095 # average ReadReq miss latency 2193system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average ReadReq miss latency 2194system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76700 # average ReadReq miss latency 2195system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81920.895248 # average ReadReq miss latency 2196system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average ReadReq miss latency 2197system.l2c.ReadReq_avg_miss_latency::total 106484.162995 # average ReadReq miss latency 2198system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1166.158064 # average UpgradeReq miss latency 2199system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1026.786116 # average UpgradeReq miss latency 2200system.l2c.UpgradeReq_avg_miss_latency::total 1134.393227 # average UpgradeReq miss latency 2201system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2454.344902 # average SCUpgradeReq miss latency 2202system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 802.996810 # average SCUpgradeReq miss latency 2203system.l2c.SCUpgradeReq_avg_miss_latency::total 1246.886880 # average SCUpgradeReq miss latency 2204system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84512.859649 # average ReadExReq miss latency 2205system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74245.628861 # average ReadExReq miss latency 2206system.l2c.ReadExReq_avg_miss_latency::total 79609.130467 # average ReadExReq miss latency 2207system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency | 2201system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85079.623845 # average ReadReq miss latency 2202system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average ReadReq miss latency 2203system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74625 # average ReadReq miss latency 2204system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84412.938106 # average ReadReq miss latency 2205system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average ReadReq miss latency 2206system.l2c.ReadReq_avg_miss_latency::total 106384.709543 # average ReadReq miss latency 2207system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1069.898121 # average UpgradeReq miss latency 2208system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1066.442660 # average UpgradeReq miss latency 2209system.l2c.UpgradeReq_avg_miss_latency::total 1069.243042 # average UpgradeReq miss latency 2210system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2496.111954 # average SCUpgradeReq miss latency 2211system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 885.465404 # average SCUpgradeReq miss latency 2212system.l2c.SCUpgradeReq_avg_miss_latency::total 1373.007467 # average SCUpgradeReq miss latency 2213system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 85211.924810 # average ReadExReq miss latency 2214system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74295.029554 # average ReadExReq miss latency 2215system.l2c.ReadExReq_avg_miss_latency::total 79973.477310 # average ReadExReq miss latency 2216system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average overall miss latency |
| 2208system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 2217system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 2209system.l2c.demand_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency 2210system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency 2211system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency 2212system.l2c.demand_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency 2213system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency 2214system.l2c.demand_avg_miss_latency::total 104792.618090 # average overall miss latency 2215system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency | 2218system.l2c.demand_avg_miss_latency::cpu0.inst 85130.213992 # average overall miss latency 2219system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average overall miss latency 2220system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74625 # average overall miss latency 2221system.l2c.demand_avg_miss_latency::cpu1.inst 76041.247748 # average overall miss latency 2222system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average overall miss latency 2223system.l2c.demand_avg_miss_latency::total 104725.610180 # average overall miss latency 2224system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average overall miss latency |
| 2216system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 2225system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 2217system.l2c.overall_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency 2218system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency 2219system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency 2220system.l2c.overall_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency 2221system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency 2222system.l2c.overall_avg_miss_latency::total 104792.618090 # average overall miss latency 2223system.l2c.blocked_cycles::no_mshrs 845 # number of cycles access was blocked | 2226system.l2c.overall_avg_miss_latency::cpu0.inst 85130.213992 # average overall miss latency 2227system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average overall miss latency 2228system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74625 # average overall miss latency 2229system.l2c.overall_avg_miss_latency::cpu1.inst 76041.247748 # average overall miss latency 2230system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average overall miss latency 2231system.l2c.overall_avg_miss_latency::total 104725.610180 # average overall miss latency 2232system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 2224system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2233system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2225system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked | 2234system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked |
| 2226system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 2235system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 2227system.l2c.avg_blocked_cycles::no_mshrs 32.500000 # average number of cycles each access was blocked | 2236system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 2228system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2229system.l2c.fast_writes 0 # number of fast writes performed 2230system.l2c.cache_copies 0 # number of cache copies performed | 2237system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2238system.l2c.fast_writes 0 # number of fast writes performed 2239system.l2c.cache_copies 0 # number of cache copies performed |
| 2231system.l2c.writebacks::writebacks 112127 # number of writebacks 2232system.l2c.writebacks::total 112127 # number of writebacks 2233system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits | 2240system.l2c.writebacks::writebacks 110752 # number of writebacks 2241system.l2c.writebacks::total 110752 # number of writebacks 2242system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits |
| 2234system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits | 2243system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits |
| 2235system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits | 2244system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits |
| 2236system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits | 2245system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits |
| 2237system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits | 2246system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits |
| 2238system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits | 2247system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 2239system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses | 2248system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 161 # number of ReadReq MSHR misses |
| 2240system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses | 2249system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses |
| 2241system.l2c.ReadReq_mshr_misses::cpu0.inst 11286 # number of ReadReq MSHR misses 2242system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq MSHR misses 2243system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses 2244system.l2c.ReadReq_mshr_misses::cpu1.inst 1852 # number of ReadReq MSHR misses 2245system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of ReadReq MSHR misses 2246system.l2c.ReadReq_mshr_misses::total 199809 # number of ReadReq MSHR misses 2247system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9028 # number of UpgradeReq MSHR misses 2248system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses 2249system.l2c.UpgradeReq_mshr_misses::total 11693 # number of UpgradeReq MSHR misses 2250system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 461 # number of SCUpgradeReq MSHR misses 2251system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1254 # number of SCUpgradeReq MSHR misses 2252system.l2c.SCUpgradeReq_mshr_misses::total 1715 # number of SCUpgradeReq MSHR misses 2253system.l2c.ReadExReq_mshr_misses::cpu0.inst 7011 # number of ReadExReq MSHR misses 2254system.l2c.ReadExReq_mshr_misses::cpu1.inst 6410 # number of ReadExReq MSHR misses 2255system.l2c.ReadExReq_mshr_misses::total 13421 # number of ReadExReq MSHR misses 2256system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses | 2250system.l2c.ReadReq_mshr_misses::cpu0.inst 11256 # number of ReadReq MSHR misses 2251system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of ReadReq MSHR misses 2252system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses 2253system.l2c.ReadReq_mshr_misses::cpu1.inst 1341 # number of ReadReq MSHR misses 2254system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of ReadReq MSHR misses 2255system.l2c.ReadReq_mshr_misses::total 199884 # number of ReadReq MSHR misses 2256system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9580 # number of UpgradeReq MSHR misses 2257system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2241 # number of UpgradeReq MSHR misses 2258system.l2c.UpgradeReq_mshr_misses::total 11821 # number of UpgradeReq MSHR misses 2259system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 527 # number of SCUpgradeReq MSHR misses 2260system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1214 # number of SCUpgradeReq MSHR misses 2261system.l2c.SCUpgradeReq_mshr_misses::total 1741 # number of SCUpgradeReq MSHR misses 2262system.l2c.ReadExReq_mshr_misses::cpu0.inst 6969 # number of ReadExReq MSHR misses 2263system.l2c.ReadExReq_mshr_misses::cpu1.inst 6429 # number of ReadExReq MSHR misses 2264system.l2c.ReadExReq_mshr_misses::total 13398 # number of ReadExReq MSHR misses 2265system.l2c.demand_mshr_misses::cpu0.dtb.walker 161 # number of demand (read+write) MSHR misses |
| 2257system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses | 2266system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses |
| 2258system.l2c.demand_mshr_misses::cpu0.inst 18297 # number of demand (read+write) MSHR misses 2259system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) MSHR misses 2260system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses 2261system.l2c.demand_mshr_misses::cpu1.inst 8262 # number of demand (read+write) MSHR misses 2262system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of demand (read+write) MSHR misses 2263system.l2c.demand_mshr_misses::total 213230 # number of demand (read+write) MSHR misses 2264system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses | 2267system.l2c.demand_mshr_misses::cpu0.inst 18225 # number of demand (read+write) MSHR misses 2268system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of demand (read+write) MSHR misses 2269system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses 2270system.l2c.demand_mshr_misses::cpu1.inst 7770 # number of demand (read+write) MSHR misses 2271system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of demand (read+write) MSHR misses 2272system.l2c.demand_mshr_misses::total 213282 # number of demand (read+write) MSHR misses 2273system.l2c.overall_mshr_misses::cpu0.dtb.walker 161 # number of overall MSHR misses |
| 2265system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses | 2274system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses |
| 2266system.l2c.overall_mshr_misses::cpu0.inst 18297 # number of overall MSHR misses 2267system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of overall MSHR misses 2268system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses 2269system.l2c.overall_mshr_misses::cpu1.inst 8262 # number of overall MSHR misses 2270system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of overall MSHR misses 2271system.l2c.overall_mshr_misses::total 213230 # number of overall MSHR misses 2272system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of ReadReq MSHR miss cycles | 2275system.l2c.overall_mshr_misses::cpu0.inst 18225 # number of overall MSHR misses 2276system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of overall MSHR misses 2277system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses 2278system.l2c.overall_mshr_misses::cpu1.inst 7770 # number of overall MSHR misses 2279system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of overall MSHR misses 2280system.l2c.overall_mshr_misses::total 213282 # number of overall MSHR misses 2281system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of ReadReq MSHR miss cycles |
| 2273system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles | 2282system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles |
| 2274system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 815475498 # number of ReadReq MSHR miss cycles 2275system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of ReadReq MSHR miss cycles 2276system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 965000 # number of ReadReq MSHR miss cycles 2277system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 128728998 # number of ReadReq MSHR miss cycles 2278system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of ReadReq MSHR miss cycles 2279system.l2c.ReadReq_mshr_miss_latency::total 18816537858 # number of ReadReq MSHR miss cycles 2280system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91196953 # number of UpgradeReq MSHR miss cycles 2281system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26828647 # number of UpgradeReq MSHR miss cycles 2282system.l2c.UpgradeReq_mshr_miss_latency::total 118025600 # number of UpgradeReq MSHR miss cycles 2283system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4664957 # number of SCUpgradeReq MSHR miss cycles 2284system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12607247 # number of SCUpgradeReq MSHR miss cycles 2285system.l2c.SCUpgradeReq_mshr_miss_latency::total 17272204 # number of SCUpgradeReq MSHR miss cycles 2286system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 505062337 # number of ReadExReq MSHR miss cycles 2287system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 394979019 # number of ReadExReq MSHR miss cycles 2288system.l2c.ReadExReq_mshr_miss_latency::total 900041356 # number of ReadExReq MSHR miss cycles 2289system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles | 2283system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 817788246 # number of ReadReq MSHR miss cycles 2284system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of ReadReq MSHR miss cycles 2285system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 500000 # number of ReadReq MSHR miss cycles 2286system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 96492250 # number of ReadReq MSHR miss cycles 2287system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of ReadReq MSHR miss cycles 2288system.l2c.ReadReq_mshr_miss_latency::total 18800812917 # number of ReadReq MSHR miss cycles 2289system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 97817994 # number of UpgradeReq MSHR miss cycles 2290system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 22626723 # number of UpgradeReq MSHR miss cycles 2291system.l2c.UpgradeReq_mshr_miss_latency::total 120444717 # number of UpgradeReq MSHR miss cycles 2292system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 5423023 # number of SCUpgradeReq MSHR miss cycles 2293system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12163710 # number of SCUpgradeReq MSHR miss cycles 2294system.l2c.SCUpgradeReq_mshr_miss_latency::total 17586733 # number of SCUpgradeReq MSHR miss cycles 2295system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 506879094 # number of ReadExReq MSHR miss cycles 2296system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 396754755 # number of ReadExReq MSHR miss cycles 2297system.l2c.ReadExReq_mshr_miss_latency::total 903633849 # number of ReadExReq MSHR miss cycles 2298system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of demand (read+write) MSHR miss cycles |
| 2290system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles | 2299system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles |
| 2291system.l2c.demand_mshr_miss_latency::cpu0.inst 1320537835 # number of demand (read+write) MSHR miss cycles 2292system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of demand (read+write) MSHR miss cycles 2293system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 965000 # number of demand (read+write) MSHR miss cycles 2294system.l2c.demand_mshr_miss_latency::cpu1.inst 523708017 # number of demand (read+write) MSHR miss cycles 2295system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of demand (read+write) MSHR miss cycles 2296system.l2c.demand_mshr_miss_latency::total 19716579214 # number of demand (read+write) MSHR miss cycles 2297system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles | 2300system.l2c.demand_mshr_miss_latency::cpu0.inst 1324667340 # number of demand (read+write) MSHR miss cycles 2301system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of demand (read+write) MSHR miss cycles 2302system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 500000 # number of demand (read+write) MSHR miss cycles 2303system.l2c.demand_mshr_miss_latency::cpu1.inst 493247005 # number of demand (read+write) MSHR miss cycles 2304system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of demand (read+write) MSHR miss cycles 2305system.l2c.demand_mshr_miss_latency::total 19704446766 # number of demand (read+write) MSHR miss cycles 2306system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of overall MSHR miss cycles |
| 2298system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles | 2307system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles |
| 2299system.l2c.overall_mshr_miss_latency::cpu0.inst 1320537835 # number of overall MSHR miss cycles 2300system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of overall MSHR miss cycles 2301system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 965000 # number of overall MSHR miss cycles 2302system.l2c.overall_mshr_miss_latency::cpu1.inst 523708017 # number of overall MSHR miss cycles 2303system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of overall MSHR miss cycles 2304system.l2c.overall_mshr_miss_latency::total 19716579214 # number of overall MSHR miss cycles 2305system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518590247 # number of ReadReq MSHR uncacheable cycles 2306system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263108750 # number of ReadReq MSHR uncacheable cycles 2307system.l2c.ReadReq_mshr_uncacheable_latency::total 5781698997 # number of ReadReq MSHR uncacheable cycles 2308system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4096001500 # number of WriteReq MSHR uncacheable cycles 2309system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150494000 # number of WriteReq MSHR uncacheable cycles 2310system.l2c.WriteReq_mshr_uncacheable_latency::total 4246495500 # number of WriteReq MSHR uncacheable cycles 2311system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614591747 # number of overall MSHR uncacheable cycles 2312system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413602750 # number of overall MSHR uncacheable cycles 2313system.l2c.overall_mshr_uncacheable_latency::total 10028194497 # number of overall MSHR uncacheable cycles 2314system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for ReadReq accesses 2315system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for ReadReq accesses 2316system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235189 # mshr miss rate for ReadReq accesses 2317system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for ReadReq accesses 2318system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for ReadReq accesses 2319system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.139405 # mshr miss rate for ReadReq accesses 2320system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for ReadReq accesses 2321system.l2c.ReadReq_mshr_miss_rate::total 0.398182 # mshr miss rate for ReadReq accesses 2322system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430520 # mshr miss rate for UpgradeReq accesses 2323system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.762518 # mshr miss rate for UpgradeReq accesses 2324system.l2c.UpgradeReq_mshr_miss_rate::total 0.477948 # mshr miss rate for UpgradeReq accesses 2325system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.692192 # mshr miss rate for SCUpgradeReq accesses 2326system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.875087 # mshr miss rate for SCUpgradeReq accesses 2327system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817056 # mshr miss rate for SCUpgradeReq accesses 2328system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.665433 # mshr miss rate for ReadExReq accesses 2329system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.852734 # mshr miss rate for ReadExReq accesses 2330system.l2c.ReadExReq_mshr_miss_rate::total 0.743422 # mshr miss rate for ReadExReq accesses 2331system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for demand accesses 2332system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for demand accesses 2333system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for demand accesses 2334system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for demand accesses 2335system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for demand accesses 2336system.l2c.demand_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for demand accesses 2337system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for demand accesses 2338system.l2c.demand_mshr_miss_rate::total 0.410171 # mshr miss rate for demand accesses 2339system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for overall accesses 2340system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for overall accesses 2341system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for overall accesses 2342system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for overall accesses 2343system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for overall accesses 2344system.l2c.overall_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for overall accesses 2345system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for overall accesses 2346system.l2c.overall_mshr_miss_rate::total 0.410171 # mshr miss rate for overall accesses 2347system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency | 2308system.l2c.overall_mshr_miss_latency::cpu0.inst 1324667340 # number of overall MSHR miss cycles 2309system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of overall MSHR miss cycles 2310system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 500000 # number of overall MSHR miss cycles 2311system.l2c.overall_mshr_miss_latency::cpu1.inst 493247005 # number of overall MSHR miss cycles 2312system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of overall MSHR miss cycles 2313system.l2c.overall_mshr_miss_latency::total 19704446766 # number of overall MSHR miss cycles 2314system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5522428749 # number of ReadReq MSHR uncacheable cycles 2315system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 260648000 # number of ReadReq MSHR uncacheable cycles 2316system.l2c.ReadReq_mshr_uncacheable_latency::total 5783076749 # number of ReadReq MSHR uncacheable cycles 2317system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4102579499 # number of WriteReq MSHR uncacheable cycles 2318system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 146450000 # number of WriteReq MSHR uncacheable cycles 2319system.l2c.WriteReq_mshr_uncacheable_latency::total 4249029499 # number of WriteReq MSHR uncacheable cycles 2320system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9625008248 # number of overall MSHR uncacheable cycles 2321system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 407098000 # number of overall MSHR uncacheable cycles 2322system.l2c.overall_mshr_uncacheable_latency::total 10032106248 # number of overall MSHR uncacheable cycles 2323system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for ReadReq accesses 2324system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for ReadReq accesses 2325system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.221684 # mshr miss rate for ReadReq accesses 2326system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for ReadReq accesses 2327system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for ReadReq accesses 2328system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.162723 # mshr miss rate for ReadReq accesses 2329system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for ReadReq accesses 2330system.l2c.ReadReq_mshr_miss_rate::total 0.404369 # mshr miss rate for ReadReq accesses 2331system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.448460 # mshr miss rate for UpgradeReq accesses 2332system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.823292 # mshr miss rate for UpgradeReq accesses 2333system.l2c.UpgradeReq_mshr_miss_rate::total 0.490824 # mshr miss rate for UpgradeReq accesses 2334system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.741210 # mshr miss rate for SCUpgradeReq accesses 2335system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.863442 # mshr miss rate for SCUpgradeReq accesses 2336system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.822390 # mshr miss rate for SCUpgradeReq accesses 2337system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.656524 # mshr miss rate for ReadExReq accesses 2338system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.876244 # mshr miss rate for ReadExReq accesses 2339system.l2c.ReadExReq_mshr_miss_rate::total 0.746324 # mshr miss rate for ReadExReq accesses 2340system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for demand accesses 2341system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for demand accesses 2342system.l2c.demand_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for demand accesses 2343system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for demand accesses 2344system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for demand accesses 2345system.l2c.demand_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for demand accesses 2346system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for demand accesses 2347system.l2c.demand_mshr_miss_rate::total 0.416353 # mshr miss rate for demand accesses 2348system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for overall accesses 2349system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for overall accesses 2350system.l2c.overall_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for overall accesses 2351system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for overall accesses 2352system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for overall accesses 2353system.l2c.overall_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for overall accesses 2354system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for overall accesses 2355system.l2c.overall_mshr_miss_rate::total 0.416353 # mshr miss rate for overall accesses 2356system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average ReadReq mshr miss latency |
| 2348system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 2357system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 2349system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72255.493355 # average ReadReq mshr miss latency 2350system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average ReadReq mshr miss latency 2351system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average ReadReq mshr miss latency 2352system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69508.098272 # average ReadReq mshr miss latency 2353system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average ReadReq mshr miss latency 2354system.l2c.ReadReq_avg_mshr_miss_latency::total 94172.624146 # average ReadReq mshr miss latency 2355system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10101.567678 # average UpgradeReq mshr miss latency 2356system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10067.034522 # average UpgradeReq mshr miss latency 2357system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.697084 # average UpgradeReq mshr miss latency 2358system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10119.212581 # average SCUpgradeReq mshr miss latency 2359system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10053.625997 # average SCUpgradeReq mshr miss latency 2360system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.255977 # average SCUpgradeReq mshr miss latency 2361system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72038.558979 # average ReadExReq mshr miss latency 2362system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61619.191732 # average ReadExReq mshr miss latency 2363system.l2c.ReadExReq_avg_mshr_miss_latency::total 67062.167946 # average ReadExReq mshr miss latency 2364system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency | 2358system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72653.539979 # average ReadReq mshr miss latency 2359system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average ReadReq mshr miss latency 2360system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency 2361system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71955.443699 # average ReadReq mshr miss latency 2362system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average ReadReq mshr miss latency 2363system.l2c.ReadReq_avg_mshr_miss_latency::total 94058.618584 # average ReadReq mshr miss latency 2364system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.646555 # average UpgradeReq mshr miss latency 2365system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10096.708166 # average UpgradeReq mshr miss latency 2366system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10189.046358 # average UpgradeReq mshr miss latency 2367system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10290.366224 # average SCUpgradeReq mshr miss latency 2368system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10019.530478 # average SCUpgradeReq mshr miss latency 2369system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10101.512349 # average SCUpgradeReq mshr miss latency 2370system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72733.404219 # average ReadExReq mshr miss latency 2371system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61713.292114 # average ReadExReq mshr miss latency 2372system.l2c.ReadExReq_avg_mshr_miss_latency::total 67445.428348 # average ReadExReq mshr miss latency 2373system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency |
| 2365system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 2374system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 2366system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency 2367system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency 2368system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency 2369system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency 2370system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency 2371system.l2c.demand_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency 2372system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency | 2375system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency 2376system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency 2377system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2378system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency 2379system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency 2380system.l2c.demand_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency 2381system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency |
| 2373system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 2382system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 2374system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency 2375system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency 2376system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency 2377system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency 2378system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency 2379system.l2c.overall_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency | 2383system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency 2384system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency 2385system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2386system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency 2387system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency 2388system.l2c.overall_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency |
| 2380system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2381system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2382system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2383system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 2384system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2385system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2386system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2387system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2388system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2389system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 2389system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2390system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2391system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2392system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 2393system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2394system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2395system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2396system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2397system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2398system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2390system.membus.trans_dist::ReadReq 238091 # Transaction distribution 2391system.membus.trans_dist::ReadResp 238091 # Transaction distribution 2392system.membus.trans_dist::WriteReq 30933 # Transaction distribution 2393system.membus.trans_dist::WriteResp 30933 # Transaction distribution 2394system.membus.trans_dist::Writeback 112127 # Transaction distribution | 2399system.membus.trans_dist::ReadReq 238185 # Transaction distribution 2400system.membus.trans_dist::ReadResp 238185 # Transaction distribution 2401system.membus.trans_dist::WriteReq 30953 # Transaction distribution 2402system.membus.trans_dist::WriteResp 30953 # Transaction distribution 2403system.membus.trans_dist::Writeback 146942 # Transaction distribution |
| 2395system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2396system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 2404system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2405system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2397system.membus.trans_dist::UpgradeReq 79652 # Transaction distribution 2398system.membus.trans_dist::SCUpgradeReq 39985 # Transaction distribution 2399system.membus.trans_dist::UpgradeResp 13516 # Transaction distribution 2400system.membus.trans_dist::ReadExReq 30363 # Transaction distribution 2401system.membus.trans_dist::ReadExResp 13313 # Transaction distribution 2402system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) | 2406system.membus.trans_dist::UpgradeReq 78292 # Transaction distribution 2407system.membus.trans_dist::SCUpgradeReq 39832 # Transaction distribution 2408system.membus.trans_dist::UpgradeResp 13662 # Transaction distribution 2409system.membus.trans_dist::ReadExReq 30241 # Transaction distribution 2410system.membus.trans_dist::ReadExResp 13298 # Transaction distribution 2411system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 108000 # Packet count per connected master and slave (bytes) |
| 2403system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) | 2412system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) |
| 2404system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13576 # Packet count per connected master and slave (bytes) 2405system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704934 # Packet count per connected master and slave (bytes) 2406system.membus.pkt_count_system.l2c.mem_side::total 826518 # Packet count per connected master and slave (bytes) 2407system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes) 2408system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes) 2409system.membus.pkt_count::total 899224 # Packet count per connected master and slave (bytes) 2410system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) | 2413system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13634 # Packet count per connected master and slave (bytes) 2414system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 701758 # Packet count per connected master and slave (bytes) 2415system.membus.pkt_count_system.l2c.mem_side::total 823430 # Packet count per connected master and slave (bytes) 2416system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) 2417system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) 2418system.membus.pkt_count::total 932326 # Packet count per connected master and slave (bytes) 2419system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162880 # Cumulative packet size per connected master and slave (bytes) |
| 2411system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) | 2420system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) |
| 2412system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27152 # Cumulative packet size per connected master and slave (bytes) 2413system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21038188 # Cumulative packet size per connected master and slave (bytes) 2414system.membus.pkt_size_system.l2c.mem_side::total 21229406 # Cumulative packet size per connected master and slave (bytes) 2415system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 2416system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 2417system.membus.pkt_size::total 23548702 # Cumulative packet size per connected master and slave (bytes) 2418system.membus.snoops 123399 # Total snoops (count) 2419system.membus.snoop_fanout::samples 498406 # Request fanout histogram | 2421system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27268 # Cumulative packet size per connected master and slave (bytes) 2422system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 20926892 # Cumulative packet size per connected master and slave (bytes) 2423system.membus.pkt_size_system.l2c.mem_side::total 21118256 # Cumulative packet size per connected master and slave (bytes) 2424system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 2425system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 2426system.membus.pkt_size::total 25753712 # Cumulative packet size per connected master and slave (bytes) 2427system.membus.snoops 122070 # Total snoops (count) 2428system.membus.snoop_fanout::samples 531658 # Request fanout histogram |
| 2420system.membus.snoop_fanout::mean 1 # Request fanout histogram 2421system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2422system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2423system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2429system.membus.snoop_fanout::mean 1 # Request fanout histogram 2430system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2431system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2432system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2424system.membus.snoop_fanout::1 498406 100.00% 100.00% # Request fanout histogram | 2433system.membus.snoop_fanout::1 531658 100.00% 100.00% # Request fanout histogram |
| 2425system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2426system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2427system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2428system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2434system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2435system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2436system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2437system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2429system.membus.snoop_fanout::total 498406 # Request fanout histogram 2430system.membus.reqLayer0.occupancy 87864494 # Layer occupancy (ticks) | 2438system.membus.snoop_fanout::total 531658 # Request fanout histogram 2439system.membus.reqLayer0.occupancy 88755994 # Layer occupancy (ticks) |
| 2431system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2432system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) 2433system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2440system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2441system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) 2442system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2434system.membus.reqLayer2.occupancy 11666999 # Layer occupancy (ticks) | 2443system.membus.reqLayer2.occupancy 11894500 # Layer occupancy (ticks) |
| 2435system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2444system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2436system.membus.reqLayer5.occupancy 1620379248 # Layer occupancy (ticks) | 2445system.membus.reqLayer5.occupancy 1935574499 # Layer occupancy (ticks) |
| 2437system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) | 2446system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) |
| 2438system.membus.respLayer2.occupancy 2120601580 # Layer occupancy (ticks) | 2447system.membus.respLayer2.occupancy 2123782192 # Layer occupancy (ticks) |
| 2439system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 2448system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 2440system.membus.respLayer3.occupancy 38542869 # Layer occupancy (ticks) | 2449system.membus.respLayer3.occupancy 38517394 # Layer occupancy (ticks) |
| 2441system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2442system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2443system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2444system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2445system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2446system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2447system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2448system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2465system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2466system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2467system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2468system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2469system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2470system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2471system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2472system.realview.ethernet.droppedPackets 0 # number of packets dropped | 2450system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2451system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2452system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2453system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2454system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2455system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2456system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2457system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2474system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2475system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2476system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2477system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2478system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2479system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2480system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2481system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 2473system.toL2Bus.trans_dist::ReadReq 668340 # Transaction distribution 2474system.toL2Bus.trans_dist::ReadResp 668325 # Transaction distribution 2475system.toL2Bus.trans_dist::WriteReq 30933 # Transaction distribution 2476system.toL2Bus.trans_dist::WriteResp 30933 # Transaction distribution 2477system.toL2Bus.trans_dist::Writeback 252536 # Transaction distribution 2478system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 2479system.toL2Bus.trans_dist::UpgradeReq 92316 # Transaction distribution 2480system.toL2Bus.trans_dist::SCUpgradeReq 40369 # Transaction distribution 2481system.toL2Bus.trans_dist::UpgradeResp 132685 # Transaction distribution 2482system.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution 2483system.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution 2484system.toL2Bus.trans_dist::ReadExReq 38932 # Transaction distribution 2485system.toL2Bus.trans_dist::ReadExResp 38932 # Transaction distribution 2486system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370044 # Packet count per connected master and slave (bytes) 2487system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368770 # Packet count per connected master and slave (bytes) 2488system.toL2Bus.pkt_count::total 1738814 # Packet count per connected master and slave (bytes) 2489system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41959415 # Cumulative packet size per connected master and slave (bytes) 2490system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7901735 # Cumulative packet size per connected master and slave (bytes) 2491system.toL2Bus.pkt_size::total 49861150 # Cumulative packet size per connected master and slave (bytes) 2492system.toL2Bus.snoops 291964 # Total snoops (count) 2493system.toL2Bus.snoop_fanout::samples 1090717 # Request fanout histogram 2494system.toL2Bus.snoop_fanout::mean 1.033437 # Request fanout histogram 2495system.toL2Bus.snoop_fanout::stdev 0.179774 # Request fanout histogram | 2482system.toL2Bus.trans_dist::ReadReq 658320 # Transaction distribution 2483system.toL2Bus.trans_dist::ReadResp 658305 # Transaction distribution 2484system.toL2Bus.trans_dist::WriteReq 30953 # Transaction distribution 2485system.toL2Bus.trans_dist::WriteResp 30953 # Transaction distribution 2486system.toL2Bus.trans_dist::Writeback 250431 # Transaction distribution 2487system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2488system.toL2Bus.trans_dist::UpgradeReq 90455 # Transaction distribution 2489system.toL2Bus.trans_dist::SCUpgradeReq 40208 # Transaction distribution 2490system.toL2Bus.trans_dist::UpgradeResp 130663 # Transaction distribution 2491system.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 2492system.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution 2493system.toL2Bus.trans_dist::ReadExReq 38633 # Transaction distribution 2494system.toL2Bus.trans_dist::ReadExResp 38633 # Transaction distribution 2495system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1411505 # Packet count per connected master and slave (bytes) 2496system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 304961 # Packet count per connected master and slave (bytes) 2497system.toL2Bus.pkt_count::total 1716466 # Packet count per connected master and slave (bytes) 2498system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 43486557 # Cumulative packet size per connected master and slave (bytes) 2499system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5753747 # Cumulative packet size per connected master and slave (bytes) 2500system.toL2Bus.pkt_size::total 49240304 # Cumulative packet size per connected master and slave (bytes) 2501system.toL2Bus.snoops 287552 # Total snoops (count) 2502system.toL2Bus.snoop_fanout::samples 1076220 # Request fanout histogram 2503system.toL2Bus.snoop_fanout::mean 1.033884 # Request fanout histogram 2504system.toL2Bus.snoop_fanout::stdev 0.180932 # Request fanout histogram |
| 2496system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2497system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2505system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2506system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2498system.toL2Bus.snoop_fanout::1 1054247 96.66% 96.66% # Request fanout histogram 2499system.toL2Bus.snoop_fanout::2 36470 3.34% 100.00% # Request fanout histogram | 2507system.toL2Bus.snoop_fanout::1 1039753 96.61% 96.61% # Request fanout histogram 2508system.toL2Bus.snoop_fanout::2 36467 3.39% 100.00% # Request fanout histogram |
| 2500system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2501system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2502system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2509system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2510system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2511system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2503system.toL2Bus.snoop_fanout::total 1090717 # Request fanout histogram 2504system.toL2Bus.reqLayer0.occupancy 1589301055 # Layer occupancy (ticks) | 2512system.toL2Bus.snoop_fanout::total 1076220 # Request fanout histogram 2513system.toL2Bus.reqLayer0.occupancy 1573537018 # Layer occupancy (ticks) |
| 2505system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2506system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) 2507system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2514system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2515system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) 2516system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2508system.toL2Bus.respLayer0.occupancy 2361799867 # Layer occupancy (ticks) | 2517system.toL2Bus.respLayer0.occupancy 2438104006 # Layer occupancy (ticks) |
| 2509system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 2518system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 2510system.toL2Bus.respLayer1.occupancy 804005619 # Layer occupancy (ticks) | 2519system.toL2Bus.respLayer1.occupancy 680349684 # Layer occupancy (ticks) |
| 2511system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2512 2513---------- End Simulation Statistics ---------- | 2520system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2521 2522---------- End Simulation Statistics ---------- |