| stats.txt (10513:ca4438b6e39a) | stats.txt (10517:ba51f8572571) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.843718 # Number of seconds simulated 4sim_ticks 2843718094000 # Number of ticks simulated 5final_tick 2843718094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.843665 # Number of seconds simulated 4sim_ticks 2843665155500 # Number of ticks simulated 5final_tick 2843665155500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 161241 # Simulator instruction rate (inst/s) 8host_op_rate 195251 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3650642703 # Simulator tick rate (ticks/s) 10host_mem_usage 606904 # Number of bytes of host memory used 11host_seconds 778.96 # Real time elapsed on the host 12sim_insts 125601128 # Number of instructions simulated 13sim_ops 152093417 # Number of ops (including micro ops) simulated | 7host_inst_rate 158211 # Simulator instruction rate (inst/s) 8host_op_rate 191554 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3597700350 # Simulator tick rate (ticks/s) 10host_mem_usage 605956 # Number of bytes of host memory used 11host_seconds 790.41 # Real time elapsed on the host 12sim_insts 125052080 # Number of instructions simulated 13sim_ops 151406456 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) |
|
| 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 34system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.dtb.walker 10240 # Number of bytes read from this memory | 35system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory | 36system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu0.inst 1341052 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 10709120 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 541088 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.l2cache.prefetcher 1237760 # Number of bytes read from this memory 24system.physmem.bytes_read::total 13841180 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 411264 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 443200 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 7176832 # Number of bytes written to this memory | 37system.physmem.bytes_read::cpu0.inst 1364476 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766720 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.inst 533600 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.l2cache.prefetcher 1164672 # Number of bytes read from this memory 42system.physmem.bytes_read::total 13841116 # Number of bytes read from this memory 43system.physmem.bytes_inst_read::cpu0.inst 419072 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::cpu1.inst 26240 # Number of instructions bytes read from this memory 45system.physmem.bytes_inst_read::total 445312 # Number of instructions bytes read from this memory 46system.physmem.bytes_written::writebacks 7174080 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory | 47system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 48system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory 49system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::total 9512912 # Number of bytes written to this memory | 50system.physmem.bytes_written::total 9510160 # Number of bytes written to this memory |
| 33system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 51system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu0.dtb.walker 160 # Number of read requests responded to by this memory | 52system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory | 53system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::cpu0.inst 21479 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.l2cache.prefetcher 167330 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 8478 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.l2cache.prefetcher 19340 # Number of read requests responded to by this memory 41system.physmem.num_reads::total 216817 # Number of read requests responded to by this memory 42system.physmem.num_writes::writebacks 112138 # Number of write requests responded to by this memory | 54system.physmem.num_reads::cpu0.inst 21845 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu0.l2cache.prefetcher 168230 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu1.inst 8361 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu1.l2cache.prefetcher 18198 # Number of read requests responded to by this memory 59system.physmem.num_reads::total 216816 # Number of read requests responded to by this memory 60system.physmem.num_writes::writebacks 112095 # Number of write requests responded to by this memory |
| 43system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory | 61system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 62system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory 63system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory |
| 46system.physmem.num_writes::total 152798 # Number of write requests responded to by this memory | 64system.physmem.num_writes::total 152755 # Number of write requests responded to by this memory |
| 47system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) | 65system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_read::cpu0.dtb.walker 3601 # Total read bandwidth from this memory (bytes/s) | 66system.physmem.bw_read::cpu0.dtb.walker 3398 # Total read bandwidth from this memory (bytes/s) |
| 49system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) | 67system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) |
| 50system.physmem.bw_read::cpu0.inst 471584 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.l2cache.prefetcher 3765887 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.dtb.walker 315 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 190275 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.l2cache.prefetcher 435261 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::total 4867283 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu0.inst 144622 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::total 155852 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_write::writebacks 2523749 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::realview.ide 815248 # Write bandwidth from this memory (bytes/s) | 68system.physmem.bw_read::cpu0.inst 479830 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu0.l2cache.prefetcher 3786212 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu1.dtb.walker 338 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu1.inst 187645 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu1.l2cache.prefetcher 409567 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::total 4867351 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_inst_read::cpu0.inst 147370 # Instruction read bandwidth from this memory (bytes/s) 75system.physmem.bw_inst_read::cpu1.inst 9228 # Instruction read bandwidth from this memory (bytes/s) 76system.physmem.bw_inst_read::total 156598 # Instruction read bandwidth from this memory (bytes/s) 77system.physmem.bw_write::writebacks 2522829 # Write bandwidth from this memory (bytes/s) 78system.physmem.bw_write::realview.ide 815263 # Write bandwidth from this memory (bytes/s) |
| 61system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) | 79system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) 80system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) |
| 63system.physmem.bw_write::total 3345237 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2523749 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::realview.ide 815586 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 3601 # Total bandwidth to/from this memory (bytes/s) | 81system.physmem.bw_write::total 3344332 # Write bandwidth from this memory (bytes/s) 82system.physmem.bw_total::writebacks 2522829 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::realview.ide 815601 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu0.dtb.walker 3398 # Total bandwidth to/from this memory (bytes/s) |
| 67system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) | 85system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) |
| 68system.physmem.bw_total::cpu0.inst 477810 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.l2cache.prefetcher 3765887 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.dtb.walker 315 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 190289 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.l2cache.prefetcher 435261 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::total 8212520 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.readReqs 216817 # Number of read requests accepted 75system.physmem.writeReqs 152798 # Number of write requests accepted 76system.physmem.readBursts 216817 # Number of DRAM read bursts, including those serviced by the write queue 77system.physmem.writeBursts 152798 # Number of DRAM write bursts, including those merged in the write queue 78system.physmem.bytesReadDRAM 13860672 # Total number of bytes read from DRAM 79system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue 80system.physmem.bytesWritten 9527424 # Total number of bytes written to DRAM 81system.physmem.bytesReadSys 13841180 # Total read bytes from the system interface side 82system.physmem.bytesWrittenSys 9512912 # Total written bytes from the system interface side 83system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue 84system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one 85system.physmem.neitherReadNorWriteReqs 13461 # Number of requests that are neither read nor write 86system.physmem.perBankRdBursts::0 14081 # Per bank write bursts 87system.physmem.perBankRdBursts::1 13907 # Per bank write bursts 88system.physmem.perBankRdBursts::2 14464 # Per bank write bursts 89system.physmem.perBankRdBursts::3 13988 # Per bank write bursts 90system.physmem.perBankRdBursts::4 16210 # Per bank write bursts 91system.physmem.perBankRdBursts::5 13087 # Per bank write bursts 92system.physmem.perBankRdBursts::6 13697 # Per bank write bursts 93system.physmem.perBankRdBursts::7 13930 # Per bank write bursts 94system.physmem.perBankRdBursts::8 13098 # Per bank write bursts 95system.physmem.perBankRdBursts::9 13410 # Per bank write bursts 96system.physmem.perBankRdBursts::10 13015 # Per bank write bursts 97system.physmem.perBankRdBursts::11 11706 # Per bank write bursts 98system.physmem.perBankRdBursts::12 12947 # Per bank write bursts 99system.physmem.perBankRdBursts::13 13659 # Per bank write bursts 100system.physmem.perBankRdBursts::14 12722 # Per bank write bursts 101system.physmem.perBankRdBursts::15 12652 # Per bank write bursts 102system.physmem.perBankWrBursts::0 9756 # Per bank write bursts 103system.physmem.perBankWrBursts::1 10039 # Per bank write bursts 104system.physmem.perBankWrBursts::2 10215 # Per bank write bursts 105system.physmem.perBankWrBursts::3 9785 # Per bank write bursts 106system.physmem.perBankWrBursts::4 9214 # Per bank write bursts 107system.physmem.perBankWrBursts::5 9161 # Per bank write bursts 108system.physmem.perBankWrBursts::6 9492 # Per bank write bursts 109system.physmem.perBankWrBursts::7 9434 # Per bank write bursts 110system.physmem.perBankWrBursts::8 9026 # Per bank write bursts 111system.physmem.perBankWrBursts::9 9356 # Per bank write bursts 112system.physmem.perBankWrBursts::10 9095 # Per bank write bursts 113system.physmem.perBankWrBursts::11 8550 # Per bank write bursts 114system.physmem.perBankWrBursts::12 9129 # Per bank write bursts 115system.physmem.perBankWrBursts::13 9225 # Per bank write bursts 116system.physmem.perBankWrBursts::14 8893 # Per bank write bursts 117system.physmem.perBankWrBursts::15 8496 # Per bank write bursts | 86system.physmem.bw_total::cpu0.inst 486056 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu0.l2cache.prefetcher 3786212 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu1.dtb.walker 338 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu1.inst 187659 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::cpu1.l2cache.prefetcher 409567 # Total bandwidth to/from this memory (bytes/s) 91system.physmem.bw_total::total 8211683 # Total bandwidth to/from this memory (bytes/s) 92system.physmem.readReqs 216816 # Number of read requests accepted 93system.physmem.writeReqs 152755 # Number of write requests accepted 94system.physmem.readBursts 216816 # Number of DRAM read bursts, including those serviced by the write queue 95system.physmem.writeBursts 152755 # Number of DRAM write bursts, including those merged in the write queue 96system.physmem.bytesReadDRAM 13860032 # Total number of bytes read from DRAM 97system.physmem.bytesReadWrQ 16192 # Total number of bytes read from write queue 98system.physmem.bytesWritten 9524672 # Total number of bytes written to DRAM 99system.physmem.bytesReadSys 13841116 # Total read bytes from the system interface side 100system.physmem.bytesWrittenSys 9510160 # Total written bytes from the system interface side 101system.physmem.servicedByWrQ 253 # Number of DRAM read bursts serviced by the write queue 102system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one 103system.physmem.neitherReadNorWriteReqs 13536 # Number of requests that are neither read nor write 104system.physmem.perBankRdBursts::0 13436 # Per bank write bursts 105system.physmem.perBankRdBursts::1 13084 # Per bank write bursts 106system.physmem.perBankRdBursts::2 14401 # Per bank write bursts 107system.physmem.perBankRdBursts::3 13747 # Per bank write bursts 108system.physmem.perBankRdBursts::4 15799 # Per bank write bursts 109system.physmem.perBankRdBursts::5 12797 # Per bank write bursts 110system.physmem.perBankRdBursts::6 13572 # Per bank write bursts 111system.physmem.perBankRdBursts::7 13744 # Per bank write bursts 112system.physmem.perBankRdBursts::8 13565 # Per bank write bursts 113system.physmem.perBankRdBursts::9 13602 # Per bank write bursts 114system.physmem.perBankRdBursts::10 13295 # Per bank write bursts 115system.physmem.perBankRdBursts::11 11895 # Per bank write bursts 116system.physmem.perBankRdBursts::12 13378 # Per bank write bursts 117system.physmem.perBankRdBursts::13 13725 # Per bank write bursts 118system.physmem.perBankRdBursts::14 13486 # Per bank write bursts 119system.physmem.perBankRdBursts::15 13037 # Per bank write bursts 120system.physmem.perBankWrBursts::0 9315 # Per bank write bursts 121system.physmem.perBankWrBursts::1 9418 # Per bank write bursts 122system.physmem.perBankWrBursts::2 10151 # Per bank write bursts 123system.physmem.perBankWrBursts::3 9572 # Per bank write bursts 124system.physmem.perBankWrBursts::4 8971 # Per bank write bursts 125system.physmem.perBankWrBursts::5 8910 # Per bank write bursts 126system.physmem.perBankWrBursts::6 9379 # Per bank write bursts 127system.physmem.perBankWrBursts::7 9378 # Per bank write bursts 128system.physmem.perBankWrBursts::8 9384 # Per bank write bursts 129system.physmem.perBankWrBursts::9 9425 # Per bank write bursts 130system.physmem.perBankWrBursts::10 9360 # Per bank write bursts 131system.physmem.perBankWrBursts::11 8832 # Per bank write bursts 132system.physmem.perBankWrBursts::12 9377 # Per bank write bursts 133system.physmem.perBankWrBursts::13 9192 # Per bank write bursts 134system.physmem.perBankWrBursts::14 9288 # Per bank write bursts 135system.physmem.perBankWrBursts::15 8871 # Per bank write bursts |
| 118system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 136system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 119system.physmem.numWrRetry 3 # Number of times write queue was full causing retry 120system.physmem.totGap 2843715756500 # Total gap between requests | 137system.physmem.numWrRetry 7 # Number of times write queue was full causing retry 138system.physmem.totGap 2843662895000 # Total gap between requests |
| 121system.physmem.readPktSize::0 0 # Read request sizes (log2) 122system.physmem.readPktSize::1 0 # Read request sizes (log2) 123system.physmem.readPktSize::2 559 # Read request sizes (log2) 124system.physmem.readPktSize::3 28 # Read request sizes (log2) 125system.physmem.readPktSize::4 0 # Read request sizes (log2) 126system.physmem.readPktSize::5 0 # Read request sizes (log2) | 139system.physmem.readPktSize::0 0 # Read request sizes (log2) 140system.physmem.readPktSize::1 0 # Read request sizes (log2) 141system.physmem.readPktSize::2 559 # Read request sizes (log2) 142system.physmem.readPktSize::3 28 # Read request sizes (log2) 143system.physmem.readPktSize::4 0 # Read request sizes (log2) 144system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 127system.physmem.readPktSize::6 216230 # Read request sizes (log2) | 145system.physmem.readPktSize::6 216229 # Read request sizes (log2) |
| 128system.physmem.writePktSize::0 0 # Write request sizes (log2) 129system.physmem.writePktSize::1 0 # Write request sizes (log2) 130system.physmem.writePktSize::2 4436 # Write request sizes (log2) 131system.physmem.writePktSize::3 0 # Write request sizes (log2) 132system.physmem.writePktSize::4 0 # Write request sizes (log2) 133system.physmem.writePktSize::5 0 # Write request sizes (log2) | 146system.physmem.writePktSize::0 0 # Write request sizes (log2) 147system.physmem.writePktSize::1 0 # Write request sizes (log2) 148system.physmem.writePktSize::2 4436 # Write request sizes (log2) 149system.physmem.writePktSize::3 0 # Write request sizes (log2) 150system.physmem.writePktSize::4 0 # Write request sizes (log2) 151system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 134system.physmem.writePktSize::6 148362 # Write request sizes (log2) 135system.physmem.rdQLenPdf::0 79662 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::1 62454 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::2 17878 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::3 12202 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::4 10651 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::5 9329 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::6 8314 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::7 7470 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::10 438 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::11 316 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see | 152system.physmem.writePktSize::6 148319 # Write request sizes (log2) 153system.physmem.rdQLenPdf::0 79263 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::1 62843 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::2 17911 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::3 12269 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::4 10663 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::5 9296 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::6 8295 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::7 7452 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::8 6012 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::9 1182 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::10 433 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::11 321 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::12 208 # What read queue length does an incoming req see |
| 148system.physmem.rdQLenPdf::13 169 # What read queue length does an incoming req see | 166system.physmem.rdQLenPdf::13 169 # What read queue length does an incoming req see |
| 149system.physmem.rdQLenPdf::14 140 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see | 167system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see |
| 151system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see | 169system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see |
| 152system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see | 170system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see |
| 155system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 174system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 173system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 192system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 182system.physmem.wrQLenPdf::15 2965 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::16 3559 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::17 4302 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::18 5372 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::19 6291 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::20 7531 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::21 8122 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::22 8991 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::23 9788 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::24 10919 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::25 10684 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::26 10534 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::27 10395 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::28 10863 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::29 9042 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::30 8791 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::31 8805 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::32 8230 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::35 299 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::36 247 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::39 157 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::41 106 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::42 107 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see 231system.physmem.bytesPerActivate::samples 92355 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::mean 253.241254 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::gmean 143.538036 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::stdev 308.020470 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::0-127 46699 50.56% 50.56% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::128-255 18860 20.42% 70.99% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::256-383 6817 7.38% 78.37% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::384-511 3583 3.88% 82.25% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::512-639 3053 3.31% 85.55% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::640-767 2112 2.29% 87.84% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::768-895 1277 1.38% 89.22% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::896-1023 1140 1.23% 90.46% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::1024-1151 8814 9.54% 100.00% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::total 92355 # Bytes accessed per row activation 245system.physmem.rdPerTurnAround::samples 7471 # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::mean 28.988355 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::stdev 530.902810 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::0-2047 7470 99.99% 99.99% # Reads before turning the bus around for writes | 200system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::16 3556 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::17 4340 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::18 5395 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::19 6276 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::20 7496 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::21 8100 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::22 8979 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::23 9748 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::24 10867 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::25 10670 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::26 10519 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::27 10413 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::28 10861 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::29 9033 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::30 8788 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::31 8722 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::32 8168 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::33 580 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::34 377 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::35 321 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::36 240 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::39 178 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::42 144 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::46 144 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::51 61 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see 243system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see 244system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see 245system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see 246system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see 247system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see 248system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see 249system.physmem.bytesPerActivate::samples 92579 # Bytes accessed per row activation 250system.physmem.bytesPerActivate::mean 252.591884 # Bytes accessed per row activation 251system.physmem.bytesPerActivate::gmean 143.134462 # Bytes accessed per row activation 252system.physmem.bytesPerActivate::stdev 307.650054 # Bytes accessed per row activation 253system.physmem.bytesPerActivate::0-127 46986 50.75% 50.75% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::128-255 18789 20.30% 71.05% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::256-383 6843 7.39% 78.44% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::384-511 3586 3.87% 82.31% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::512-639 3022 3.26% 85.58% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::640-767 2120 2.29% 87.87% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::768-895 1307 1.41% 89.28% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::896-1023 1131 1.22% 90.50% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::1024-1151 8795 9.50% 100.00% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::total 92579 # Bytes accessed per row activation 263system.physmem.rdPerTurnAround::samples 7460 # Reads before turning the bus around for writes 264system.physmem.rdPerTurnAround::mean 29.029759 # Reads before turning the bus around for writes 265system.physmem.rdPerTurnAround::stdev 529.579779 # Reads before turning the bus around for writes 266system.physmem.rdPerTurnAround::0-2047 7459 99.99% 99.99% # Reads before turning the bus around for writes |
| 249system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes | 267system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 250system.physmem.rdPerTurnAround::total 7471 # Reads before turning the bus around for writes 251system.physmem.wrPerTurnAround::samples 7471 # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::mean 19.925847 # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::gmean 18.607688 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::stdev 10.837629 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::16-19 6200 82.99% 82.99% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::20-23 464 6.21% 89.20% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::24-27 76 1.02% 90.22% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::28-31 210 2.81% 93.03% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::32-35 192 2.57% 95.60% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::36-39 15 0.20% 95.80% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::40-43 27 0.36% 96.16% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::44-47 15 0.20% 96.36% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::48-51 29 0.39% 96.75% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::52-55 10 0.13% 96.88% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::56-59 9 0.12% 97.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::60-63 6 0.08% 97.08% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::64-67 163 2.18% 99.26% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::68-71 4 0.05% 99.32% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::72-75 5 0.07% 99.38% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::76-79 4 0.05% 99.44% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::80-83 14 0.19% 99.63% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::84-87 1 0.01% 99.64% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::100-103 4 0.05% 99.75% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::104-107 1 0.01% 99.76% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::108-111 3 0.04% 99.80% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::112-115 2 0.03% 99.83% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::116-119 2 0.03% 99.85% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::120-123 2 0.03% 99.88% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::128-131 8 0.11% 99.99% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::136-139 1 0.01% 100.00% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::total 7471 # Writes before turning the bus around for reads 284system.physmem.totQLat 7621074500 # Total ticks spent queuing 285system.physmem.totMemAccLat 11681818250 # Total ticks spent from burst creation until serviced by the DRAM 286system.physmem.totBusLat 1082865000 # Total ticks spent in databus transfers 287system.physmem.avgQLat 35189.40 # Average queueing delay per DRAM burst | 268system.physmem.rdPerTurnAround::total 7460 # Reads before turning the bus around for writes 269system.physmem.wrPerTurnAround::samples 7460 # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::mean 19.949464 # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::gmean 18.624141 # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::stdev 10.915893 # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::16-19 6155 82.51% 82.51% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::20-23 493 6.61% 89.12% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::24-27 89 1.19% 90.31% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::28-31 200 2.68% 92.99% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::32-35 188 2.52% 95.51% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::36-39 17 0.23% 95.74% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::40-43 27 0.36% 96.10% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::44-47 16 0.21% 96.31% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::48-51 36 0.48% 96.80% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::52-55 10 0.13% 96.93% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::56-59 5 0.07% 97.00% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::60-63 4 0.05% 97.05% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::64-67 168 2.25% 99.30% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::68-71 5 0.07% 99.37% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::72-75 3 0.04% 99.41% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::76-79 4 0.05% 99.46% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::80-83 10 0.13% 99.60% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::88-91 1 0.01% 99.62% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::92-95 1 0.01% 99.64% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::96-99 2 0.03% 99.66% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::112-115 5 0.07% 99.83% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::116-119 4 0.05% 99.88% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::120-123 1 0.01% 99.89% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::124-127 1 0.01% 99.91% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::128-131 3 0.04% 99.95% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::140-143 4 0.05% 100.00% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::total 7460 # Writes before turning the bus around for reads 304system.physmem.totQLat 7660076750 # Total ticks spent queuing 305system.physmem.totMemAccLat 11720633000 # Total ticks spent from burst creation until serviced by the DRAM 306system.physmem.totBusLat 1082815000 # Total ticks spent in databus transfers 307system.physmem.avgQLat 35371.12 # Average queueing delay per DRAM burst |
| 288system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 308system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 289system.physmem.avgMemAccLat 53939.40 # Average memory access latency per DRAM burst | 309system.physmem.avgMemAccLat 54121.12 # Average memory access latency per DRAM burst |
| 290system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s 291system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s 292system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s | 310system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s 311system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s 312system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s |
| 293system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s | 313system.physmem.avgWrBWSys 3.34 # Average system write bandwidth in MiByte/s |
| 294system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 295system.physmem.busUtil 0.06 # Data bus utilization in percentage 296system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 297system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 314system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 315system.physmem.busUtil 0.06 # Data bus utilization in percentage 316system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 317system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 298system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing 299system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing 300system.physmem.readRowHits 183248 # Number of row buffer hits during reads 301system.physmem.writeRowHits 89836 # Number of row buffer hits during writes 302system.physmem.readRowHitRate 84.61 # Row buffer hit rate for reads 303system.physmem.writeRowHitRate 60.34 # Row buffer hit rate for writes 304system.physmem.avgGap 7693723.89 # Average gap between requests 305system.physmem.pageHitRate 74.72 # Row buffer hit rate, read and write combined 306system.physmem.memoryStateTime::IDLE 2710028687250 # Time in different power states 307system.physmem.memoryStateTime::REF 94957980000 # Time in different power states | 318system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing 319system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing 320system.physmem.readRowHits 183124 # Number of row buffer hits during reads 321system.physmem.writeRowHits 89683 # Number of row buffer hits during writes 322system.physmem.readRowHitRate 84.56 # Row buffer hit rate for reads 323system.physmem.writeRowHitRate 60.25 # Row buffer hit rate for writes 324system.physmem.avgGap 7694496.85 # Average gap between requests 325system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined 326system.physmem.memoryStateTime::IDLE 2709761139750 # Time in different power states 327system.physmem.memoryStateTime::REF 94956160000 # Time in different power states |
| 308system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 328system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 309system.physmem.memoryStateTime::ACT 38731176500 # Time in different power states | 329system.physmem.memoryStateTime::ACT 38946040250 # Time in different power states |
| 310system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 330system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 311system.physmem.actEnergy::0 365654520 # Energy for activate commands per rank (pJ) 312system.physmem.actEnergy::1 332549280 # Energy for activate commands per rank (pJ) 313system.physmem.preEnergy::0 199513875 # Energy for precharge commands per rank (pJ) 314system.physmem.preEnergy::1 181450500 # Energy for precharge commands per rank (pJ) 315system.physmem.readEnergy::0 884239200 # Energy for read commands per rank (pJ) 316system.physmem.readEnergy::1 805030200 # Energy for read commands per rank (pJ) 317system.physmem.writeEnergy::0 499582080 # Energy for write commands per rank (pJ) 318system.physmem.writeEnergy::1 465069600 # Energy for write commands per rank (pJ) 319system.physmem.refreshEnergy::0 185737808880 # Energy for refresh commands per rank (pJ) 320system.physmem.refreshEnergy::1 185737808880 # Energy for refresh commands per rank (pJ) 321system.physmem.actBackEnergy::0 82126203345 # Energy for active background per rank (pJ) 322system.physmem.actBackEnergy::1 81336736530 # Energy for active background per rank (pJ) 323system.physmem.preBackEnergy::0 1634190168750 # Energy for precharge background per rank (pJ) 324system.physmem.preBackEnergy::1 1634882683500 # Energy for precharge background per rank (pJ) 325system.physmem.totalEnergy::0 1904003170650 # Total energy per rank (pJ) 326system.physmem.totalEnergy::1 1903741328490 # Total energy per rank (pJ) 327system.physmem.averagePower::0 669.547151 # Core power per rank (mW) 328system.physmem.averagePower::1 669.455073 # Core power per rank (mW) 329system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 330system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 331system.realview.nvmem.bytes_read::total 1280 # Number of bytes read from this memory 332system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 333system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 334system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 335system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 336system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 337system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 338system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 339system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_read::total 450 # Total read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_inst_read::total 450 # Instruction read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 345system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::total 450 # Total bandwidth to/from this memory (bytes/s) 347system.membus.trans_dist::ReadReq 238282 # Transaction distribution 348system.membus.trans_dist::ReadResp 238282 # Transaction distribution 349system.membus.trans_dist::WriteReq 31054 # Transaction distribution 350system.membus.trans_dist::WriteResp 31054 # Transaction distribution 351system.membus.trans_dist::Writeback 112138 # Transaction distribution | 331system.physmem.actEnergy::0 358880760 # Energy for activate commands per rank (pJ) 332system.physmem.actEnergy::1 341016480 # Energy for activate commands per rank (pJ) 333system.physmem.preEnergy::0 195817875 # Energy for precharge commands per rank (pJ) 334system.physmem.preEnergy::1 186070500 # Energy for precharge commands per rank (pJ) 335system.physmem.readEnergy::0 862524000 # Energy for read commands per rank (pJ) 336system.physmem.readEnergy::1 826667400 # Energy for read commands per rank (pJ) 337system.physmem.writeEnergy::0 486609120 # Energy for write commands per rank (pJ) 338system.physmem.writeEnergy::1 477763920 # Energy for write commands per rank (pJ) 339system.physmem.refreshEnergy::0 185734248960 # Energy for refresh commands per rank (pJ) 340system.physmem.refreshEnergy::1 185734248960 # Energy for refresh commands per rank (pJ) 341system.physmem.actBackEnergy::0 81966350835 # Energy for active background per rank (pJ) 342system.physmem.actBackEnergy::1 81438405435 # Energy for active background per rank (pJ) 343system.physmem.preBackEnergy::0 1634297688000 # Energy for precharge background per rank (pJ) 344system.physmem.preBackEnergy::1 1634760798000 # Energy for precharge background per rank (pJ) 345system.physmem.totalEnergy::0 1903902119550 # Total energy per rank (pJ) 346system.physmem.totalEnergy::1 1903764970695 # Total energy per rank (pJ) 347system.physmem.averagePower::0 669.524448 # Core power per rank (mW) 348system.physmem.averagePower::1 669.476219 # Core power per rank (mW) 349system.membus.trans_dist::ReadReq 238011 # Transaction distribution 350system.membus.trans_dist::ReadResp 238011 # Transaction distribution 351system.membus.trans_dist::WriteReq 30931 # Transaction distribution 352system.membus.trans_dist::WriteResp 30931 # Transaction distribution 353system.membus.trans_dist::Writeback 112095 # Transaction distribution |
| 352system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 353system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 354system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 355system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 354system.membus.trans_dist::UpgradeReq 80328 # Transaction distribution 355system.membus.trans_dist::SCUpgradeReq 40430 # Transaction distribution 356system.membus.trans_dist::UpgradeResp 13461 # Transaction distribution 357system.membus.trans_dist::ReadExReq 30145 # Transaction distribution 358system.membus.trans_dist::ReadExResp 13182 # Transaction distribution | 356system.membus.trans_dist::UpgradeReq 79719 # Transaction distribution 357system.membus.trans_dist::SCUpgradeReq 39980 # Transaction distribution 358system.membus.trans_dist::UpgradeResp 13536 # Transaction distribution 359system.membus.trans_dist::ReadExReq 30379 # Transaction distribution 360system.membus.trans_dist::ReadExResp 13328 # Transaction distribution |
| 359system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) | 361system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) |
| 360system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 361system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14040 # Packet count per connected master and slave (bytes) 362system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 705796 # Packet count per connected master and slave (bytes) 363system.membus.pkt_count_system.l2c.mem_side::total 827846 # Packet count per connected master and slave (bytes) 364system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72718 # Packet count per connected master and slave (bytes) 365system.membus.pkt_count_system.iocache.mem_side::total 72718 # Packet count per connected master and slave (bytes) 366system.membus.pkt_count::total 900564 # Packet count per connected master and slave (bytes) | 362system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) 363system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes) 364system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704855 # Packet count per connected master and slave (bytes) 365system.membus.pkt_count_system.l2c.mem_side::total 826435 # Packet count per connected master and slave (bytes) 366system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes) 367system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes) 368system.membus.pkt_count::total 899141 # Packet count per connected master and slave (bytes) |
| 367system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) | 369system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) |
| 368system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1280 # Cumulative packet size per connected master and slave (bytes) 369system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28080 # Cumulative packet size per connected master and slave (bytes) 370system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21034796 # Cumulative packet size per connected master and slave (bytes) 371system.membus.pkt_size_system.l2c.mem_side::total 21227006 # Cumulative packet size per connected master and slave (bytes) | 370system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) 371system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes) 372system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21031980 # Cumulative packet size per connected master and slave (bytes) 373system.membus.pkt_size_system.l2c.mem_side::total 21223190 # Cumulative packet size per connected master and slave (bytes) |
| 372system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 373system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) | 374system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 375system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) |
| 374system.membus.pkt_size::total 23546302 # Cumulative packet size per connected master and slave (bytes) 375system.membus.snoops 124500 # Total snoops (count) 376system.membus.snoop_fanout::samples 499399 # Request fanout histogram | 376system.membus.pkt_size::total 23542486 # Cumulative packet size per connected master and slave (bytes) 377system.membus.snoops 123442 # Total snoops (count) 378system.membus.snoop_fanout::samples 498376 # Request fanout histogram |
| 377system.membus.snoop_fanout::mean 1 # Request fanout histogram 378system.membus.snoop_fanout::stdev 0 # Request fanout histogram 379system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 380system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 379system.membus.snoop_fanout::mean 1 # Request fanout histogram 380system.membus.snoop_fanout::stdev 0 # Request fanout histogram 381system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 382system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 381system.membus.snoop_fanout::1 499399 100.00% 100.00% # Request fanout histogram | 383system.membus.snoop_fanout::1 498376 100.00% 100.00% # Request fanout histogram |
| 382system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 383system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 384system.membus.snoop_fanout::min_value 1 # Request fanout histogram 385system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 384system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 385system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 386system.membus.snoop_fanout::min_value 1 # Request fanout histogram 387system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 386system.membus.snoop_fanout::total 499399 # Request fanout histogram 387system.membus.reqLayer0.occupancy 87896996 # Layer occupancy (ticks) | 388system.membus.snoop_fanout::total 498376 # Request fanout histogram 389system.membus.reqLayer0.occupancy 87914995 # Layer occupancy (ticks) |
| 388system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 390system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 389system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) | 391system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) |
| 390system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 392system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 391system.membus.reqLayer2.occupancy 12141500 # Layer occupancy (ticks) | 393system.membus.reqLayer2.occupancy 11673499 # Layer occupancy (ticks) |
| 392system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 394system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 393system.membus.reqLayer5.occupancy 1620346498 # Layer occupancy (ticks) | 395system.membus.reqLayer5.occupancy 1620072999 # Layer occupancy (ticks) |
| 394system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) | 396system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) |
| 395system.membus.respLayer2.occupancy 2120331885 # Layer occupancy (ticks) | 397system.membus.respLayer2.occupancy 2120142312 # Layer occupancy (ticks) |
| 396system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 398system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 397system.membus.respLayer3.occupancy 38636884 # Layer occupancy (ticks) | 399system.membus.respLayer3.occupancy 38549614 # Layer occupancy (ticks) |
| 398system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 399system.cpu_clk_domain.clock 500 # Clock period in ticks | 400system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 401system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 400system.l2c.tags.replacements 151104 # number of replacements 401system.l2c.tags.tagsinuse 64343.342453 # Cycle average of tags in use 402system.l2c.tags.total_refs 537709 # Total number of references to valid blocks. 403system.l2c.tags.sampled_refs 215892 # Sample count of references to valid blocks. 404system.l2c.tags.avg_refs 2.490639 # Average number of references to valid blocks. | 402system.l2c.tags.replacements 151709 # number of replacements 403system.l2c.tags.tagsinuse 64474.290498 # Cycle average of tags in use 404system.l2c.tags.total_refs 529875 # Total number of references to valid blocks. 405system.l2c.tags.sampled_refs 216478 # Sample count of references to valid blocks. 406system.l2c.tags.avg_refs 2.447708 # Average number of references to valid blocks. |
| 405system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 407system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 406system.l2c.tags.occ_blocks::writebacks 13312.566907 # Average occupied blocks per requestor 407system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.661228 # Average occupied blocks per requestor 408system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033237 # Average occupied blocks per requestor 409system.l2c.tags.occ_blocks::cpu0.inst 3627.484276 # Average occupied blocks per requestor 410system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 40388.691608 # Average occupied blocks per requestor 411system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.364745 # Average occupied blocks per requestor 412system.l2c.tags.occ_blocks::cpu1.inst 878.502916 # Average occupied blocks per requestor 413system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6044.037536 # Average occupied blocks per requestor 414system.l2c.tags.occ_percent::writebacks 0.203134 # Average percentage of cache occupancy 415system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001246 # Average percentage of cache occupancy 416system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 417system.l2c.tags.occ_percent::cpu0.inst 0.055351 # Average percentage of cache occupancy 418system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.616283 # Average percentage of cache occupancy 419system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000158 # Average percentage of cache occupancy 420system.l2c.tags.occ_percent::cpu1.inst 0.013405 # Average percentage of cache occupancy 421system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.092225 # Average percentage of cache occupancy 422system.l2c.tags.occ_percent::total 0.981801 # Average percentage of cache occupancy 423system.l2c.tags.occ_task_id_blocks::1022 46495 # Occupied blocks per task id 424system.l2c.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id 425system.l2c.tags.occ_task_id_blocks::1024 18259 # Occupied blocks per task id 426system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 427system.l2c.tags.age_task_id_blocks_1022::2 432 # Occupied blocks per task id 428system.l2c.tags.age_task_id_blocks_1022::3 6889 # Occupied blocks per task id 429system.l2c.tags.age_task_id_blocks_1022::4 39173 # Occupied blocks per task id 430system.l2c.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id 431system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 432system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id 433system.l2c.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id 434system.l2c.tags.age_task_id_blocks_1024::3 2341 # Occupied blocks per task id 435system.l2c.tags.age_task_id_blocks_1024::4 15618 # Occupied blocks per task id 436system.l2c.tags.occ_task_id_percent::1022 0.709457 # Percentage of cache occupancy per task id 437system.l2c.tags.occ_task_id_percent::1023 0.000519 # Percentage of cache occupancy per task id 438system.l2c.tags.occ_task_id_percent::1024 0.278610 # Percentage of cache occupancy per task id 439system.l2c.tags.tag_accesses 6702696 # Number of tag accesses 440system.l2c.tags.data_accesses 6702696 # Number of data accesses 441system.l2c.ReadReq_hits::cpu0.dtb.walker 575 # number of ReadReq hits 442system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits 443system.l2c.ReadReq_hits::cpu0.inst 36632 # number of ReadReq hits 444system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 209337 # number of ReadReq hits 445system.l2c.ReadReq_hits::cpu1.dtb.walker 139 # number of ReadReq hits 446system.l2c.ReadReq_hits::cpu1.itb.walker 45 # number of ReadReq hits 447system.l2c.ReadReq_hits::cpu1.inst 12148 # number of ReadReq hits 448system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 48809 # number of ReadReq hits 449system.l2c.ReadReq_hits::total 307807 # number of ReadReq hits 450system.l2c.Writeback_hits::writebacks 253703 # number of Writeback hits 451system.l2c.Writeback_hits::total 253703 # number of Writeback hits 452system.l2c.UpgradeReq_hits::cpu0.inst 11935 # number of UpgradeReq hits 453system.l2c.UpgradeReq_hits::cpu1.inst 1029 # number of UpgradeReq hits 454system.l2c.UpgradeReq_hits::total 12964 # number of UpgradeReq hits 455system.l2c.SCUpgradeReq_hits::cpu0.inst 208 # number of SCUpgradeReq hits 456system.l2c.SCUpgradeReq_hits::cpu1.inst 174 # number of SCUpgradeReq hits 457system.l2c.SCUpgradeReq_hits::total 382 # number of SCUpgradeReq hits 458system.l2c.ReadExReq_hits::cpu0.inst 3683 # number of ReadExReq hits 459system.l2c.ReadExReq_hits::cpu1.inst 1200 # number of ReadExReq hits 460system.l2c.ReadExReq_hits::total 4883 # number of ReadExReq hits 461system.l2c.demand_hits::cpu0.dtb.walker 575 # number of demand (read+write) hits 462system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits 463system.l2c.demand_hits::cpu0.inst 40315 # number of demand (read+write) hits 464system.l2c.demand_hits::cpu0.l2cache.prefetcher 209337 # number of demand (read+write) hits 465system.l2c.demand_hits::cpu1.dtb.walker 139 # number of demand (read+write) hits 466system.l2c.demand_hits::cpu1.itb.walker 45 # number of demand (read+write) hits 467system.l2c.demand_hits::cpu1.inst 13348 # number of demand (read+write) hits 468system.l2c.demand_hits::cpu1.l2cache.prefetcher 48809 # number of demand (read+write) hits 469system.l2c.demand_hits::total 312690 # number of demand (read+write) hits 470system.l2c.overall_hits::cpu0.dtb.walker 575 # number of overall hits 471system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits 472system.l2c.overall_hits::cpu0.inst 40315 # number of overall hits 473system.l2c.overall_hits::cpu0.l2cache.prefetcher 209337 # number of overall hits 474system.l2c.overall_hits::cpu1.dtb.walker 139 # number of overall hits 475system.l2c.overall_hits::cpu1.itb.walker 45 # number of overall hits 476system.l2c.overall_hits::cpu1.inst 13348 # number of overall hits 477system.l2c.overall_hits::cpu1.l2cache.prefetcher 48809 # number of overall hits 478system.l2c.overall_hits::total 312690 # number of overall hits 479system.l2c.ReadReq_misses::cpu0.dtb.walker 160 # number of ReadReq misses | 408system.l2c.tags.occ_blocks::writebacks 12364.739343 # Average occupied blocks per requestor 409system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831819 # Average occupied blocks per requestor 410system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030523 # Average occupied blocks per requestor 411system.l2c.tags.occ_blocks::cpu0.inst 3875.049948 # Average occupied blocks per requestor 412system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42732.474457 # Average occupied blocks per requestor 413system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.614781 # Average occupied blocks per requestor 414system.l2c.tags.occ_blocks::cpu1.inst 756.297533 # Average occupied blocks per requestor 415system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4653.252093 # Average occupied blocks per requestor 416system.l2c.tags.occ_percent::writebacks 0.188671 # Average percentage of cache occupancy 417system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy 418system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 419system.l2c.tags.occ_percent::cpu0.inst 0.059129 # Average percentage of cache occupancy 420system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.652046 # Average percentage of cache occupancy 421system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy 422system.l2c.tags.occ_percent::cpu1.inst 0.011540 # Average percentage of cache occupancy 423system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071003 # Average percentage of cache occupancy 424system.l2c.tags.occ_percent::total 0.983800 # Average percentage of cache occupancy 425system.l2c.tags.occ_task_id_blocks::1022 46265 # Occupied blocks per task id 426system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id 427system.l2c.tags.occ_task_id_blocks::1024 18457 # Occupied blocks per task id 428system.l2c.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id 429system.l2c.tags.age_task_id_blocks_1022::3 6570 # Occupied blocks per task id 430system.l2c.tags.age_task_id_blocks_1022::4 39426 # Occupied blocks per task id 431system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id 432system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 433system.l2c.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id 434system.l2c.tags.age_task_id_blocks_1024::3 2643 # Occupied blocks per task id 435system.l2c.tags.age_task_id_blocks_1024::4 15559 # Occupied blocks per task id 436system.l2c.tags.occ_task_id_percent::1022 0.705948 # Percentage of cache occupancy per task id 437system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id 438system.l2c.tags.occ_task_id_percent::1024 0.281631 # Percentage of cache occupancy per task id 439system.l2c.tags.tag_accesses 6643854 # Number of tag accesses 440system.l2c.tags.data_accesses 6643854 # Number of data accesses 441system.l2c.ReadReq_hits::cpu0.dtb.walker 549 # number of ReadReq hits 442system.l2c.ReadReq_hits::cpu0.itb.walker 114 # number of ReadReq hits 443system.l2c.ReadReq_hits::cpu0.inst 36725 # number of ReadReq hits 444system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207902 # number of ReadReq hits 445system.l2c.ReadReq_hits::cpu1.dtb.walker 116 # number of ReadReq hits 446system.l2c.ReadReq_hits::cpu1.itb.walker 47 # number of ReadReq hits 447system.l2c.ReadReq_hits::cpu1.inst 11423 # number of ReadReq hits 448system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45111 # number of ReadReq hits 449system.l2c.ReadReq_hits::total 301987 # number of ReadReq hits 450system.l2c.Writeback_hits::writebacks 252491 # number of Writeback hits 451system.l2c.Writeback_hits::total 252491 # number of Writeback hits 452system.l2c.UpgradeReq_hits::cpu0.inst 11970 # number of UpgradeReq hits 453system.l2c.UpgradeReq_hits::cpu1.inst 853 # number of UpgradeReq hits 454system.l2c.UpgradeReq_hits::total 12823 # number of UpgradeReq hits 455system.l2c.SCUpgradeReq_hits::cpu0.inst 185 # number of SCUpgradeReq hits 456system.l2c.SCUpgradeReq_hits::cpu1.inst 180 # number of SCUpgradeReq hits 457system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits 458system.l2c.ReadExReq_hits::cpu0.inst 3516 # number of ReadExReq hits 459system.l2c.ReadExReq_hits::cpu1.inst 1122 # number of ReadExReq hits 460system.l2c.ReadExReq_hits::total 4638 # number of ReadExReq hits 461system.l2c.demand_hits::cpu0.dtb.walker 549 # number of demand (read+write) hits 462system.l2c.demand_hits::cpu0.itb.walker 114 # number of demand (read+write) hits 463system.l2c.demand_hits::cpu0.inst 40241 # number of demand (read+write) hits 464system.l2c.demand_hits::cpu0.l2cache.prefetcher 207902 # number of demand (read+write) hits 465system.l2c.demand_hits::cpu1.dtb.walker 116 # number of demand (read+write) hits 466system.l2c.demand_hits::cpu1.itb.walker 47 # number of demand (read+write) hits 467system.l2c.demand_hits::cpu1.inst 12545 # number of demand (read+write) hits 468system.l2c.demand_hits::cpu1.l2cache.prefetcher 45111 # number of demand (read+write) hits 469system.l2c.demand_hits::total 306625 # number of demand (read+write) hits 470system.l2c.overall_hits::cpu0.dtb.walker 549 # number of overall hits 471system.l2c.overall_hits::cpu0.itb.walker 114 # number of overall hits 472system.l2c.overall_hits::cpu0.inst 40241 # number of overall hits 473system.l2c.overall_hits::cpu0.l2cache.prefetcher 207902 # number of overall hits 474system.l2c.overall_hits::cpu1.dtb.walker 116 # number of overall hits 475system.l2c.overall_hits::cpu1.itb.walker 47 # number of overall hits 476system.l2c.overall_hits::cpu1.inst 12545 # number of overall hits 477system.l2c.overall_hits::cpu1.l2cache.prefetcher 45111 # number of overall hits 478system.l2c.overall_hits::total 306625 # number of overall hits 479system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses |
| 480system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses | 480system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses |
| 481system.l2c.ReadReq_misses::cpu0.inst 11021 # number of ReadReq misses 482system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 167331 # number of ReadReq misses 483system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses 484system.l2c.ReadReq_misses::cpu1.inst 2011 # number of ReadReq misses 485system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 19340 # number of ReadReq misses 486system.l2c.ReadReq_misses::total 199878 # number of ReadReq misses 487system.l2c.UpgradeReq_misses::cpu0.inst 8877 # number of UpgradeReq misses 488system.l2c.UpgradeReq_misses::cpu1.inst 2752 # number of UpgradeReq misses 489system.l2c.UpgradeReq_misses::total 11629 # number of UpgradeReq misses 490system.l2c.SCUpgradeReq_misses::cpu0.inst 464 # number of SCUpgradeReq misses 491system.l2c.SCUpgradeReq_misses::cpu1.inst 1248 # number of SCUpgradeReq misses 492system.l2c.SCUpgradeReq_misses::total 1712 # number of SCUpgradeReq misses 493system.l2c.ReadExReq_misses::cpu0.inst 6943 # number of ReadExReq misses 494system.l2c.ReadExReq_misses::cpu1.inst 6359 # number of ReadExReq misses 495system.l2c.ReadExReq_misses::total 13302 # number of ReadExReq misses 496system.l2c.demand_misses::cpu0.dtb.walker 160 # number of demand (read+write) misses | 481system.l2c.ReadReq_misses::cpu0.inst 11298 # number of ReadReq misses 482system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq misses 483system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses 484system.l2c.ReadReq_misses::cpu1.inst 1836 # number of ReadReq misses 485system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18199 # number of ReadReq misses 486system.l2c.ReadReq_misses::total 199730 # number of ReadReq misses 487system.l2c.UpgradeReq_misses::cpu0.inst 9030 # number of UpgradeReq misses 488system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses 489system.l2c.UpgradeReq_misses::total 11695 # number of UpgradeReq misses 490system.l2c.SCUpgradeReq_misses::cpu0.inst 470 # number of SCUpgradeReq misses 491system.l2c.SCUpgradeReq_misses::cpu1.inst 1259 # number of SCUpgradeReq misses 492system.l2c.SCUpgradeReq_misses::total 1729 # number of SCUpgradeReq misses 493system.l2c.ReadExReq_misses::cpu0.inst 7024 # number of ReadExReq misses 494system.l2c.ReadExReq_misses::cpu1.inst 6416 # number of ReadExReq misses 495system.l2c.ReadExReq_misses::total 13440 # number of ReadExReq misses 496system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses |
| 497system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses | 497system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses |
| 498system.l2c.demand_misses::cpu0.inst 17964 # number of demand (read+write) misses 499system.l2c.demand_misses::cpu0.l2cache.prefetcher 167331 # number of demand (read+write) misses 500system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses 501system.l2c.demand_misses::cpu1.inst 8370 # number of demand (read+write) misses 502system.l2c.demand_misses::cpu1.l2cache.prefetcher 19340 # number of demand (read+write) misses 503system.l2c.demand_misses::total 213180 # number of demand (read+write) misses 504system.l2c.overall_misses::cpu0.dtb.walker 160 # number of overall misses | 498system.l2c.demand_misses::cpu0.inst 18322 # number of demand (read+write) misses 499system.l2c.demand_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) misses 500system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses 501system.l2c.demand_misses::cpu1.inst 8252 # number of demand (read+write) misses 502system.l2c.demand_misses::cpu1.l2cache.prefetcher 18199 # number of demand (read+write) misses 503system.l2c.demand_misses::total 213170 # number of demand (read+write) misses 504system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses |
| 505system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses | 505system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses |
| 506system.l2c.overall_misses::cpu0.inst 17964 # number of overall misses 507system.l2c.overall_misses::cpu0.l2cache.prefetcher 167331 # number of overall misses 508system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses 509system.l2c.overall_misses::cpu1.inst 8370 # number of overall misses 510system.l2c.overall_misses::cpu1.l2cache.prefetcher 19340 # number of overall misses 511system.l2c.overall_misses::total 213180 # number of overall misses 512system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 13245499 # number of ReadReq miss cycles | 506system.l2c.overall_misses::cpu0.inst 18322 # number of overall misses 507system.l2c.overall_misses::cpu0.l2cache.prefetcher 168230 # number of overall misses 508system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses 509system.l2c.overall_misses::cpu1.inst 8252 # number of overall misses 510system.l2c.overall_misses::cpu1.l2cache.prefetcher 18199 # number of overall misses 511system.l2c.overall_misses::total 213170 # number of overall misses 512system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles |
| 513system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles | 513system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles |
| 514system.l2c.ReadReq_miss_latency::cpu0.inst 927632991 # number of ReadReq miss cycles 515system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of ReadReq miss cycles 516system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1117750 # number of ReadReq miss cycles 517system.l2c.ReadReq_miss_latency::cpu1.inst 171510999 # number of ReadReq miss cycles 518system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of ReadReq miss cycles 519system.l2c.ReadReq_miss_latency::total 21228443106 # number of ReadReq miss cycles 520system.l2c.UpgradeReq_miss_latency::cpu0.inst 10247078 # number of UpgradeReq miss cycles 521system.l2c.UpgradeReq_miss_latency::cpu1.inst 3439358 # number of UpgradeReq miss cycles 522system.l2c.UpgradeReq_miss_latency::total 13686436 # number of UpgradeReq miss cycles 523system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1071455 # number of SCUpgradeReq miss cycles 524system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1047955 # number of SCUpgradeReq miss cycles 525system.l2c.SCUpgradeReq_miss_latency::total 2119410 # number of SCUpgradeReq miss cycles 526system.l2c.ReadExReq_miss_latency::cpu0.inst 585218901 # number of ReadExReq miss cycles 527system.l2c.ReadExReq_miss_latency::cpu1.inst 465754979 # number of ReadExReq miss cycles 528system.l2c.ReadExReq_miss_latency::total 1050973880 # number of ReadExReq miss cycles 529system.l2c.demand_miss_latency::cpu0.dtb.walker 13245499 # number of demand (read+write) miss cycles | 514system.l2c.ReadReq_miss_latency::cpu0.inst 956701998 # number of ReadReq miss cycles 515system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of ReadReq miss cycles 516system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1343500 # number of ReadReq miss cycles 517system.l2c.ReadReq_miss_latency::cpu1.inst 150016000 # number of ReadReq miss cycles 518system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of ReadReq miss cycles 519system.l2c.ReadReq_miss_latency::total 21240863385 # number of ReadReq miss cycles 520system.l2c.UpgradeReq_miss_latency::cpu0.inst 10890561 # number of UpgradeReq miss cycles 521system.l2c.UpgradeReq_miss_latency::cpu1.inst 2732384 # number of UpgradeReq miss cycles 522system.l2c.UpgradeReq_miss_latency::total 13622945 # number of UpgradeReq miss cycles 523system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1227450 # number of SCUpgradeReq miss cycles 524system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 930960 # number of SCUpgradeReq miss cycles 525system.l2c.SCUpgradeReq_miss_latency::total 2158410 # number of SCUpgradeReq miss cycles 526system.l2c.ReadExReq_miss_latency::cpu0.inst 595061904 # number of ReadExReq miss cycles 527system.l2c.ReadExReq_miss_latency::cpu1.inst 477250480 # number of ReadExReq miss cycles 528system.l2c.ReadExReq_miss_latency::total 1072312384 # number of ReadExReq miss cycles 529system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles |
| 530system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles | 530system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles |
| 531system.l2c.demand_miss_latency::cpu0.inst 1512851892 # number of demand (read+write) miss cycles 532system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of demand (read+write) miss cycles 533system.l2c.demand_miss_latency::cpu1.dtb.walker 1117750 # number of demand (read+write) miss cycles 534system.l2c.demand_miss_latency::cpu1.inst 637265978 # number of demand (read+write) miss cycles 535system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of demand (read+write) miss cycles 536system.l2c.demand_miss_latency::total 22279416986 # number of demand (read+write) miss cycles 537system.l2c.overall_miss_latency::cpu0.dtb.walker 13245499 # number of overall miss cycles | 531system.l2c.demand_miss_latency::cpu0.inst 1551763902 # number of demand (read+write) miss cycles 532system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of demand (read+write) miss cycles 533system.l2c.demand_miss_latency::cpu1.dtb.walker 1343500 # number of demand (read+write) miss cycles 534system.l2c.demand_miss_latency::cpu1.inst 627266480 # number of demand (read+write) miss cycles 535system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of demand (read+write) miss cycles 536system.l2c.demand_miss_latency::total 22313175769 # number of demand (read+write) miss cycles 537system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles |
| 538system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles | 538system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles |
| 539system.l2c.overall_miss_latency::cpu0.inst 1512851892 # number of overall miss cycles 540system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of overall miss cycles 541system.l2c.overall_miss_latency::cpu1.dtb.walker 1117750 # number of overall miss cycles 542system.l2c.overall_miss_latency::cpu1.inst 637265978 # number of overall miss cycles 543system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of overall miss cycles 544system.l2c.overall_miss_latency::total 22279416986 # number of overall miss cycles 545system.l2c.ReadReq_accesses::cpu0.dtb.walker 735 # number of ReadReq accesses(hits+misses) 546system.l2c.ReadReq_accesses::cpu0.itb.walker 123 # number of ReadReq accesses(hits+misses) 547system.l2c.ReadReq_accesses::cpu0.inst 47653 # number of ReadReq accesses(hits+misses) 548system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 376668 # number of ReadReq accesses(hits+misses) 549system.l2c.ReadReq_accesses::cpu1.dtb.walker 153 # number of ReadReq accesses(hits+misses) 550system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses) 551system.l2c.ReadReq_accesses::cpu1.inst 14159 # number of ReadReq accesses(hits+misses) 552system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68149 # number of ReadReq accesses(hits+misses) 553system.l2c.ReadReq_accesses::total 507685 # number of ReadReq accesses(hits+misses) 554system.l2c.Writeback_accesses::writebacks 253703 # number of Writeback accesses(hits+misses) 555system.l2c.Writeback_accesses::total 253703 # number of Writeback accesses(hits+misses) 556system.l2c.UpgradeReq_accesses::cpu0.inst 20812 # number of UpgradeReq accesses(hits+misses) 557system.l2c.UpgradeReq_accesses::cpu1.inst 3781 # number of UpgradeReq accesses(hits+misses) 558system.l2c.UpgradeReq_accesses::total 24593 # number of UpgradeReq accesses(hits+misses) 559system.l2c.SCUpgradeReq_accesses::cpu0.inst 672 # number of SCUpgradeReq accesses(hits+misses) 560system.l2c.SCUpgradeReq_accesses::cpu1.inst 1422 # number of SCUpgradeReq accesses(hits+misses) | 539system.l2c.overall_miss_latency::cpu0.inst 1551763902 # number of overall miss cycles 540system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of overall miss cycles 541system.l2c.overall_miss_latency::cpu1.dtb.walker 1343500 # number of overall miss cycles 542system.l2c.overall_miss_latency::cpu1.inst 627266480 # number of overall miss cycles 543system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of overall miss cycles 544system.l2c.overall_miss_latency::total 22313175769 # number of overall miss cycles 545system.l2c.ReadReq_accesses::cpu0.dtb.walker 700 # number of ReadReq accesses(hits+misses) 546system.l2c.ReadReq_accesses::cpu0.itb.walker 115 # number of ReadReq accesses(hits+misses) 547system.l2c.ReadReq_accesses::cpu0.inst 48023 # number of ReadReq accesses(hits+misses) 548system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 376132 # number of ReadReq accesses(hits+misses) 549system.l2c.ReadReq_accesses::cpu1.dtb.walker 131 # number of ReadReq accesses(hits+misses) 550system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses) 551system.l2c.ReadReq_accesses::cpu1.inst 13259 # number of ReadReq accesses(hits+misses) 552system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63310 # number of ReadReq accesses(hits+misses) 553system.l2c.ReadReq_accesses::total 501717 # number of ReadReq accesses(hits+misses) 554system.l2c.Writeback_accesses::writebacks 252491 # number of Writeback accesses(hits+misses) 555system.l2c.Writeback_accesses::total 252491 # number of Writeback accesses(hits+misses) 556system.l2c.UpgradeReq_accesses::cpu0.inst 21000 # number of UpgradeReq accesses(hits+misses) 557system.l2c.UpgradeReq_accesses::cpu1.inst 3518 # number of UpgradeReq accesses(hits+misses) 558system.l2c.UpgradeReq_accesses::total 24518 # number of UpgradeReq accesses(hits+misses) 559system.l2c.SCUpgradeReq_accesses::cpu0.inst 655 # number of SCUpgradeReq accesses(hits+misses) 560system.l2c.SCUpgradeReq_accesses::cpu1.inst 1439 # number of SCUpgradeReq accesses(hits+misses) |
| 561system.l2c.SCUpgradeReq_accesses::total 2094 # number of SCUpgradeReq accesses(hits+misses) | 561system.l2c.SCUpgradeReq_accesses::total 2094 # number of SCUpgradeReq accesses(hits+misses) |
| 562system.l2c.ReadExReq_accesses::cpu0.inst 10626 # number of ReadExReq accesses(hits+misses) 563system.l2c.ReadExReq_accesses::cpu1.inst 7559 # number of ReadExReq accesses(hits+misses) 564system.l2c.ReadExReq_accesses::total 18185 # number of ReadExReq accesses(hits+misses) 565system.l2c.demand_accesses::cpu0.dtb.walker 735 # number of demand (read+write) accesses 566system.l2c.demand_accesses::cpu0.itb.walker 123 # number of demand (read+write) accesses 567system.l2c.demand_accesses::cpu0.inst 58279 # number of demand (read+write) accesses 568system.l2c.demand_accesses::cpu0.l2cache.prefetcher 376668 # number of demand (read+write) accesses 569system.l2c.demand_accesses::cpu1.dtb.walker 153 # number of demand (read+write) accesses 570system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses 571system.l2c.demand_accesses::cpu1.inst 21718 # number of demand (read+write) accesses 572system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68149 # number of demand (read+write) accesses 573system.l2c.demand_accesses::total 525870 # number of demand (read+write) accesses 574system.l2c.overall_accesses::cpu0.dtb.walker 735 # number of overall (read+write) accesses 575system.l2c.overall_accesses::cpu0.itb.walker 123 # number of overall (read+write) accesses 576system.l2c.overall_accesses::cpu0.inst 58279 # number of overall (read+write) accesses 577system.l2c.overall_accesses::cpu0.l2cache.prefetcher 376668 # number of overall (read+write) accesses 578system.l2c.overall_accesses::cpu1.dtb.walker 153 # number of overall (read+write) accesses 579system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses 580system.l2c.overall_accesses::cpu1.inst 21718 # number of overall (read+write) accesses 581system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68149 # number of overall (read+write) accesses 582system.l2c.overall_accesses::total 525870 # number of overall (read+write) accesses 583system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for ReadReq accesses 584system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008130 # miss rate for ReadReq accesses 585system.l2c.ReadReq_miss_rate::cpu0.inst 0.231276 # miss rate for ReadReq accesses 586system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for ReadReq accesses 587system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for ReadReq accesses 588system.l2c.ReadReq_miss_rate::cpu1.inst 0.142030 # miss rate for ReadReq accesses 589system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for ReadReq accesses 590system.l2c.ReadReq_miss_rate::total 0.393705 # miss rate for ReadReq accesses 591system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.426533 # miss rate for UpgradeReq accesses 592system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.727850 # miss rate for UpgradeReq accesses 593system.l2c.UpgradeReq_miss_rate::total 0.472858 # miss rate for UpgradeReq accesses 594system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.690476 # miss rate for SCUpgradeReq accesses 595system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.877637 # miss rate for SCUpgradeReq accesses 596system.l2c.SCUpgradeReq_miss_rate::total 0.817574 # miss rate for SCUpgradeReq accesses 597system.l2c.ReadExReq_miss_rate::cpu0.inst 0.653397 # miss rate for ReadExReq accesses 598system.l2c.ReadExReq_miss_rate::cpu1.inst 0.841249 # miss rate for ReadExReq accesses 599system.l2c.ReadExReq_miss_rate::total 0.731482 # miss rate for ReadExReq accesses 600system.l2c.demand_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for demand accesses 601system.l2c.demand_miss_rate::cpu0.itb.walker 0.008130 # miss rate for demand accesses 602system.l2c.demand_miss_rate::cpu0.inst 0.308241 # miss rate for demand accesses 603system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for demand accesses 604system.l2c.demand_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for demand accesses 605system.l2c.demand_miss_rate::cpu1.inst 0.385395 # miss rate for demand accesses 606system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for demand accesses 607system.l2c.demand_miss_rate::total 0.405385 # miss rate for demand accesses 608system.l2c.overall_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for overall accesses 609system.l2c.overall_miss_rate::cpu0.itb.walker 0.008130 # miss rate for overall accesses 610system.l2c.overall_miss_rate::cpu0.inst 0.308241 # miss rate for overall accesses 611system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for overall accesses 612system.l2c.overall_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for overall accesses 613system.l2c.overall_miss_rate::cpu1.inst 0.385395 # miss rate for overall accesses 614system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for overall accesses 615system.l2c.overall_miss_rate::total 0.405385 # miss rate for overall accesses 616system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average ReadReq miss latency | 562system.l2c.ReadExReq_accesses::cpu0.inst 10540 # number of ReadExReq accesses(hits+misses) 563system.l2c.ReadExReq_accesses::cpu1.inst 7538 # number of ReadExReq accesses(hits+misses) 564system.l2c.ReadExReq_accesses::total 18078 # number of ReadExReq accesses(hits+misses) 565system.l2c.demand_accesses::cpu0.dtb.walker 700 # number of demand (read+write) accesses 566system.l2c.demand_accesses::cpu0.itb.walker 115 # number of demand (read+write) accesses 567system.l2c.demand_accesses::cpu0.inst 58563 # number of demand (read+write) accesses 568system.l2c.demand_accesses::cpu0.l2cache.prefetcher 376132 # number of demand (read+write) accesses 569system.l2c.demand_accesses::cpu1.dtb.walker 131 # number of demand (read+write) accesses 570system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses 571system.l2c.demand_accesses::cpu1.inst 20797 # number of demand (read+write) accesses 572system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63310 # number of demand (read+write) accesses 573system.l2c.demand_accesses::total 519795 # number of demand (read+write) accesses 574system.l2c.overall_accesses::cpu0.dtb.walker 700 # number of overall (read+write) accesses 575system.l2c.overall_accesses::cpu0.itb.walker 115 # number of overall (read+write) accesses 576system.l2c.overall_accesses::cpu0.inst 58563 # number of overall (read+write) accesses 577system.l2c.overall_accesses::cpu0.l2cache.prefetcher 376132 # number of overall (read+write) accesses 578system.l2c.overall_accesses::cpu1.dtb.walker 131 # number of overall (read+write) accesses 579system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses 580system.l2c.overall_accesses::cpu1.inst 20797 # number of overall (read+write) accesses 581system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63310 # number of overall (read+write) accesses 582system.l2c.overall_accesses::total 519795 # number of overall (read+write) accesses 583system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for ReadReq accesses 584system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008696 # miss rate for ReadReq accesses 585system.l2c.ReadReq_miss_rate::cpu0.inst 0.235262 # miss rate for ReadReq accesses 586system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for ReadReq accesses 587system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for ReadReq accesses 588system.l2c.ReadReq_miss_rate::cpu1.inst 0.138472 # miss rate for ReadReq accesses 589system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for ReadReq accesses 590system.l2c.ReadReq_miss_rate::total 0.398093 # miss rate for ReadReq accesses 591system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430000 # miss rate for UpgradeReq accesses 592system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.757533 # miss rate for UpgradeReq accesses 593system.l2c.UpgradeReq_miss_rate::total 0.476996 # miss rate for UpgradeReq accesses 594system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.717557 # miss rate for SCUpgradeReq accesses 595system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.874913 # miss rate for SCUpgradeReq accesses 596system.l2c.SCUpgradeReq_miss_rate::total 0.825692 # miss rate for SCUpgradeReq accesses 597system.l2c.ReadExReq_miss_rate::cpu0.inst 0.666414 # miss rate for ReadExReq accesses 598system.l2c.ReadExReq_miss_rate::cpu1.inst 0.851154 # miss rate for ReadExReq accesses 599system.l2c.ReadExReq_miss_rate::total 0.743445 # miss rate for ReadExReq accesses 600system.l2c.demand_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for demand accesses 601system.l2c.demand_miss_rate::cpu0.itb.walker 0.008696 # miss rate for demand accesses 602system.l2c.demand_miss_rate::cpu0.inst 0.312860 # miss rate for demand accesses 603system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for demand accesses 604system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for demand accesses 605system.l2c.demand_miss_rate::cpu1.inst 0.396788 # miss rate for demand accesses 606system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for demand accesses 607system.l2c.demand_miss_rate::total 0.410104 # miss rate for demand accesses 608system.l2c.overall_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for overall accesses 609system.l2c.overall_miss_rate::cpu0.itb.walker 0.008696 # miss rate for overall accesses 610system.l2c.overall_miss_rate::cpu0.inst 0.312860 # miss rate for overall accesses 611system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for overall accesses 612system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for overall accesses 613system.l2c.overall_miss_rate::cpu1.inst 0.396788 # miss rate for overall accesses 614system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for overall accesses 615system.l2c.overall_miss_rate::total 0.410104 # miss rate for overall accesses 616system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency |
| 617system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency | 617system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency |
| 618system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84169.584520 # average ReadReq miss latency 619system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average ReadReq miss latency 620system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average ReadReq miss latency 621system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85286.424167 # average ReadReq miss latency 622system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average ReadReq miss latency 623system.l2c.ReadReq_avg_miss_latency::total 106207.001801 # average ReadReq miss latency 624system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1154.340205 # average UpgradeReq miss latency 625system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1249.766715 # average UpgradeReq miss latency 626system.l2c.UpgradeReq_avg_miss_latency::total 1176.922865 # average UpgradeReq miss latency 627system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2309.170259 # average SCUpgradeReq miss latency 628system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 839.707532 # average SCUpgradeReq miss latency 629system.l2c.SCUpgradeReq_avg_miss_latency::total 1237.973131 # average SCUpgradeReq miss latency 630system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84289.053867 # average ReadExReq miss latency 631system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73243.431200 # average ReadExReq miss latency 632system.l2c.ReadExReq_avg_miss_latency::total 79008.711472 # average ReadExReq miss latency 633system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average overall miss latency | 618system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84678.881041 # average ReadReq miss latency 619system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average ReadReq miss latency 620system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average ReadReq miss latency 621system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81708.061002 # average ReadReq miss latency 622system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average ReadReq miss latency 623system.l2c.ReadReq_avg_miss_latency::total 106347.886572 # average ReadReq miss latency 624system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1206.042193 # average UpgradeReq miss latency 625system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1025.284803 # average UpgradeReq miss latency 626system.l2c.UpgradeReq_avg_miss_latency::total 1164.852074 # average UpgradeReq miss latency 627system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2611.595745 # average SCUpgradeReq miss latency 628system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 739.444003 # average SCUpgradeReq miss latency 629system.l2c.SCUpgradeReq_avg_miss_latency::total 1248.357432 # average SCUpgradeReq miss latency 630system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84718.380410 # average ReadExReq miss latency 631system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74384.426434 # average ReadExReq miss latency 632system.l2c.ReadExReq_avg_miss_latency::total 79785.147619 # average ReadExReq miss latency 633system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency |
| 634system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 634system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 635system.l2c.demand_avg_miss_latency::cpu0.inst 84215.758851 # average overall miss latency 636system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average overall miss latency 637system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average overall miss latency 638system.l2c.demand_avg_miss_latency::cpu1.inst 76136.914934 # average overall miss latency 639system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average overall miss latency 640system.l2c.demand_avg_miss_latency::total 104509.883601 # average overall miss latency 641system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average overall miss latency | 635system.l2c.demand_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency 636system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency 637system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency 638system.l2c.demand_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency 639system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency 640system.l2c.demand_avg_miss_latency::total 104673.151799 # average overall miss latency 641system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency |
| 642system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 642system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 643system.l2c.overall_avg_miss_latency::cpu0.inst 84215.758851 # average overall miss latency 644system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average overall miss latency 645system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average overall miss latency 646system.l2c.overall_avg_miss_latency::cpu1.inst 76136.914934 # average overall miss latency 647system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average overall miss latency 648system.l2c.overall_avg_miss_latency::total 104509.883601 # average overall miss latency 649system.l2c.blocked_cycles::no_mshrs 27 # number of cycles access was blocked | 643system.l2c.overall_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency 644system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency 645system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency 646system.l2c.overall_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency 647system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency 648system.l2c.overall_avg_miss_latency::total 104673.151799 # average overall miss latency 649system.l2c.blocked_cycles::no_mshrs 758 # number of cycles access was blocked |
| 650system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 650system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 651system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked | 651system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked |
| 652system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 652system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 653system.l2c.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked | 653system.l2c.avg_blocked_cycles::no_mshrs 36.095238 # average number of cycles each access was blocked |
| 654system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.l2c.fast_writes 0 # number of fast writes performed 656system.l2c.cache_copies 0 # number of cache copies performed | 654system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.l2c.fast_writes 0 # number of fast writes performed 656system.l2c.cache_copies 0 # number of cache copies performed |
| 657system.l2c.writebacks::writebacks 112138 # number of writebacks 658system.l2c.writebacks::total 112138 # number of writebacks 659system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 660system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits 661system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 662system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 663system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 664system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 665system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 666system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits 667system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits 668system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 160 # number of ReadReq MSHR misses | 657system.l2c.writebacks::writebacks 112095 # number of writebacks 658system.l2c.writebacks::total 112095 # number of writebacks 659system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits 660system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 661system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 662system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 663system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits 664system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 665system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses |
| 669system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses | 666system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses |
| 670system.l2c.ReadReq_mshr_misses::cpu0.inst 11020 # number of ReadReq MSHR misses 671system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of ReadReq MSHR misses 672system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses 673system.l2c.ReadReq_mshr_misses::cpu1.inst 2011 # number of ReadReq MSHR misses 674system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of ReadReq MSHR misses 675system.l2c.ReadReq_mshr_misses::total 199876 # number of ReadReq MSHR misses 676system.l2c.UpgradeReq_mshr_misses::cpu0.inst 8877 # number of UpgradeReq MSHR misses 677system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2752 # number of UpgradeReq MSHR misses 678system.l2c.UpgradeReq_mshr_misses::total 11629 # number of UpgradeReq MSHR misses 679system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 464 # number of SCUpgradeReq MSHR misses 680system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1248 # number of SCUpgradeReq MSHR misses 681system.l2c.SCUpgradeReq_mshr_misses::total 1712 # number of SCUpgradeReq MSHR misses 682system.l2c.ReadExReq_mshr_misses::cpu0.inst 6943 # number of ReadExReq MSHR misses 683system.l2c.ReadExReq_mshr_misses::cpu1.inst 6359 # number of ReadExReq MSHR misses 684system.l2c.ReadExReq_mshr_misses::total 13302 # number of ReadExReq MSHR misses 685system.l2c.demand_mshr_misses::cpu0.dtb.walker 160 # number of demand (read+write) MSHR misses | 667system.l2c.ReadReq_mshr_misses::cpu0.inst 11298 # number of ReadReq MSHR misses 668system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq MSHR misses 669system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses 670system.l2c.ReadReq_mshr_misses::cpu1.inst 1836 # number of ReadReq MSHR misses 671system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of ReadReq MSHR misses 672system.l2c.ReadReq_mshr_misses::total 199729 # number of ReadReq MSHR misses 673system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9030 # number of UpgradeReq MSHR misses 674system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses 675system.l2c.UpgradeReq_mshr_misses::total 11695 # number of UpgradeReq MSHR misses 676system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 470 # number of SCUpgradeReq MSHR misses 677system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1259 # number of SCUpgradeReq MSHR misses 678system.l2c.SCUpgradeReq_mshr_misses::total 1729 # number of SCUpgradeReq MSHR misses 679system.l2c.ReadExReq_mshr_misses::cpu0.inst 7024 # number of ReadExReq MSHR misses 680system.l2c.ReadExReq_mshr_misses::cpu1.inst 6416 # number of ReadExReq MSHR misses 681system.l2c.ReadExReq_mshr_misses::total 13440 # number of ReadExReq MSHR misses 682system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses |
| 686system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses | 683system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses |
| 687system.l2c.demand_mshr_misses::cpu0.inst 17963 # number of demand (read+write) MSHR misses 688system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of demand (read+write) MSHR misses 689system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses 690system.l2c.demand_mshr_misses::cpu1.inst 8370 # number of demand (read+write) MSHR misses 691system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of demand (read+write) MSHR misses 692system.l2c.demand_mshr_misses::total 213178 # number of demand (read+write) MSHR misses 693system.l2c.overall_mshr_misses::cpu0.dtb.walker 160 # number of overall MSHR misses | 684system.l2c.demand_mshr_misses::cpu0.inst 18322 # number of demand (read+write) MSHR misses 685system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) MSHR misses 686system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses 687system.l2c.demand_mshr_misses::cpu1.inst 8252 # number of demand (read+write) MSHR misses 688system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of demand (read+write) MSHR misses 689system.l2c.demand_mshr_misses::total 213169 # number of demand (read+write) MSHR misses 690system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses |
| 694system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses | 691system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses |
| 695system.l2c.overall_mshr_misses::cpu0.inst 17963 # number of overall MSHR misses 696system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of overall MSHR misses 697system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses 698system.l2c.overall_mshr_misses::cpu1.inst 8370 # number of overall MSHR misses 699system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of overall MSHR misses 700system.l2c.overall_mshr_misses::total 213178 # number of overall MSHR misses 701system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of ReadReq MSHR miss cycles | 692system.l2c.overall_mshr_misses::cpu0.inst 18322 # number of overall MSHR misses 693system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of overall MSHR misses 694system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses 695system.l2c.overall_mshr_misses::cpu1.inst 8252 # number of overall MSHR misses 696system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of overall MSHR misses 697system.l2c.overall_mshr_misses::total 213169 # number of overall MSHR misses 698system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of ReadReq MSHR miss cycles |
| 702system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles | 699system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles |
| 703system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 790589241 # number of ReadReq MSHR miss cycles 704system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of ReadReq MSHR miss cycles 705system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 946250 # number of ReadReq MSHR miss cycles 706system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 146552499 # number of ReadReq MSHR miss cycles 707system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of ReadReq MSHR miss cycles 708system.l2c.ReadReq_mshr_miss_latency::total 18767530106 # number of ReadReq MSHR miss cycles 709system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 89623803 # number of UpgradeReq MSHR miss cycles 710system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 27822731 # number of UpgradeReq MSHR miss cycles 711system.l2c.UpgradeReq_mshr_miss_latency::total 117446534 # number of UpgradeReq MSHR miss cycles 712system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4677961 # number of SCUpgradeReq MSHR miss cycles 713system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12575743 # number of SCUpgradeReq MSHR miss cycles 714system.l2c.SCUpgradeReq_mshr_miss_latency::total 17253704 # number of SCUpgradeReq MSHR miss cycles 715system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 498567599 # number of ReadExReq MSHR miss cycles 716system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 385443021 # number of ReadExReq MSHR miss cycles 717system.l2c.ReadExReq_mshr_miss_latency::total 884010620 # number of ReadExReq MSHR miss cycles 718system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of demand (read+write) MSHR miss cycles | 700system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 816212498 # number of ReadReq MSHR miss cycles 701system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of ReadReq MSHR miss cycles 702system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of ReadReq MSHR miss cycles 703system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 127225500 # number of ReadReq MSHR miss cycles 704system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of ReadReq MSHR miss cycles 705system.l2c.ReadReq_mshr_miss_latency::total 18781676635 # number of ReadReq MSHR miss cycles 706system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91207456 # number of UpgradeReq MSHR miss cycles 707system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26838142 # number of UpgradeReq MSHR miss cycles 708system.l2c.UpgradeReq_mshr_miss_latency::total 118045598 # number of UpgradeReq MSHR miss cycles 709system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4758966 # number of SCUpgradeReq MSHR miss cycles 710system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12646753 # number of SCUpgradeReq MSHR miss cycles 711system.l2c.SCUpgradeReq_mshr_miss_latency::total 17405719 # number of SCUpgradeReq MSHR miss cycles 712system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 507430588 # number of ReadExReq MSHR miss cycles 713system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 396239520 # number of ReadExReq MSHR miss cycles 714system.l2c.ReadExReq_mshr_miss_latency::total 903670108 # number of ReadExReq MSHR miss cycles 715system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles |
| 719system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles | 716system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles |
| 720system.l2c.demand_mshr_miss_latency::cpu0.inst 1289156840 # number of demand (read+write) MSHR miss cycles 721system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of demand (read+write) MSHR miss cycles 722system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 946250 # number of demand (read+write) MSHR miss cycles 723system.l2c.demand_mshr_miss_latency::cpu1.inst 531995520 # number of demand (read+write) MSHR miss cycles 724system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of demand (read+write) MSHR miss cycles 725system.l2c.demand_mshr_miss_latency::total 19651540726 # number of demand (read+write) MSHR miss cycles 726system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of overall MSHR miss cycles | 717system.l2c.demand_mshr_miss_latency::cpu0.inst 1323643086 # number of demand (read+write) MSHR miss cycles 718system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of demand (read+write) MSHR miss cycles 719system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of demand (read+write) MSHR miss cycles 720system.l2c.demand_mshr_miss_latency::cpu1.inst 523465020 # number of demand (read+write) MSHR miss cycles 721system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of demand (read+write) MSHR miss cycles 722system.l2c.demand_mshr_miss_latency::total 19685346743 # number of demand (read+write) MSHR miss cycles 723system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles |
| 727system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles | 724system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles |
| 728system.l2c.overall_mshr_miss_latency::cpu0.inst 1289156840 # number of overall MSHR miss cycles 729system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of overall MSHR miss cycles 730system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 946250 # number of overall MSHR miss cycles 731system.l2c.overall_mshr_miss_latency::cpu1.inst 531995520 # number of overall MSHR miss cycles 732system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of overall MSHR miss cycles 733system.l2c.overall_mshr_miss_latency::total 19651540726 # number of overall MSHR miss cycles 734system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5455196250 # number of ReadReq MSHR uncacheable cycles 735system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 328328000 # number of ReadReq MSHR uncacheable cycles 736system.l2c.ReadReq_mshr_uncacheable_latency::total 5783524250 # number of ReadReq MSHR uncacheable cycles 737system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4031988000 # number of WriteReq MSHR uncacheable cycles 738system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 216852500 # number of WriteReq MSHR uncacheable cycles 739system.l2c.WriteReq_mshr_uncacheable_latency::total 4248840500 # number of WriteReq MSHR uncacheable cycles 740system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9487184250 # number of overall MSHR uncacheable cycles 741system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 545180500 # number of overall MSHR uncacheable cycles 742system.l2c.overall_mshr_uncacheable_latency::total 10032364750 # number of overall MSHR uncacheable cycles 743system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for ReadReq accesses 744system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for ReadReq accesses 745system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.231255 # mshr miss rate for ReadReq accesses 746system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for ReadReq accesses 747system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for ReadReq accesses 748system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.142030 # mshr miss rate for ReadReq accesses 749system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for ReadReq accesses 750system.l2c.ReadReq_mshr_miss_rate::total 0.393701 # mshr miss rate for ReadReq accesses 751system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.426533 # mshr miss rate for UpgradeReq accesses 752system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.727850 # mshr miss rate for UpgradeReq accesses 753system.l2c.UpgradeReq_mshr_miss_rate::total 0.472858 # mshr miss rate for UpgradeReq accesses 754system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.690476 # mshr miss rate for SCUpgradeReq accesses 755system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.877637 # mshr miss rate for SCUpgradeReq accesses 756system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817574 # mshr miss rate for SCUpgradeReq accesses 757system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.653397 # mshr miss rate for ReadExReq accesses 758system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.841249 # mshr miss rate for ReadExReq accesses 759system.l2c.ReadExReq_mshr_miss_rate::total 0.731482 # mshr miss rate for ReadExReq accesses 760system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for demand accesses 761system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for demand accesses 762system.l2c.demand_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for demand accesses 763system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for demand accesses 764system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for demand accesses 765system.l2c.demand_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for demand accesses 766system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for demand accesses 767system.l2c.demand_mshr_miss_rate::total 0.405382 # mshr miss rate for demand accesses 768system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for overall accesses 769system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for overall accesses 770system.l2c.overall_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for overall accesses 771system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for overall accesses 772system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for overall accesses 773system.l2c.overall_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for overall accesses 774system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for overall accesses 775system.l2c.overall_mshr_miss_rate::total 0.405382 # mshr miss rate for overall accesses 776system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average ReadReq mshr miss latency | 725system.l2c.overall_mshr_miss_latency::cpu0.inst 1323643086 # number of overall MSHR miss cycles 726system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of overall MSHR miss cycles 727system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of overall MSHR miss cycles 728system.l2c.overall_mshr_miss_latency::cpu1.inst 523465020 # number of overall MSHR miss cycles 729system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of overall MSHR miss cycles 730system.l2c.overall_mshr_miss_latency::total 19685346743 # number of overall MSHR miss cycles 731system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518668247 # number of ReadReq MSHR uncacheable cycles 732system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263087751 # number of ReadReq MSHR uncacheable cycles 733system.l2c.ReadReq_mshr_uncacheable_latency::total 5781755998 # number of ReadReq MSHR uncacheable cycles 734system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4095979500 # number of WriteReq MSHR uncacheable cycles 735system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150492500 # number of WriteReq MSHR uncacheable cycles 736system.l2c.WriteReq_mshr_uncacheable_latency::total 4246472000 # number of WriteReq MSHR uncacheable cycles 737system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614647747 # number of overall MSHR uncacheable cycles 738system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413580251 # number of overall MSHR uncacheable cycles 739system.l2c.overall_mshr_uncacheable_latency::total 10028227998 # number of overall MSHR uncacheable cycles 740system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for ReadReq accesses 741system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for ReadReq accesses 742system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235262 # mshr miss rate for ReadReq accesses 743system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for ReadReq accesses 744system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for ReadReq accesses 745system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138472 # mshr miss rate for ReadReq accesses 746system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for ReadReq accesses 747system.l2c.ReadReq_mshr_miss_rate::total 0.398091 # mshr miss rate for ReadReq accesses 748system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430000 # mshr miss rate for UpgradeReq accesses 749system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.757533 # mshr miss rate for UpgradeReq accesses 750system.l2c.UpgradeReq_mshr_miss_rate::total 0.476996 # mshr miss rate for UpgradeReq accesses 751system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.717557 # mshr miss rate for SCUpgradeReq accesses 752system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.874913 # mshr miss rate for SCUpgradeReq accesses 753system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.825692 # mshr miss rate for SCUpgradeReq accesses 754system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.666414 # mshr miss rate for ReadExReq accesses 755system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.851154 # mshr miss rate for ReadExReq accesses 756system.l2c.ReadExReq_mshr_miss_rate::total 0.743445 # mshr miss rate for ReadExReq accesses 757system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for demand accesses 758system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for demand accesses 759system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for demand accesses 760system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for demand accesses 761system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for demand accesses 762system.l2c.demand_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for demand accesses 763system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for demand accesses 764system.l2c.demand_mshr_miss_rate::total 0.410102 # mshr miss rate for demand accesses 765system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for overall accesses 766system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for overall accesses 767system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for overall accesses 768system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for overall accesses 769system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for overall accesses 770system.l2c.overall_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for overall accesses 771system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for overall accesses 772system.l2c.overall_mshr_miss_rate::total 0.410102 # mshr miss rate for overall accesses 773system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency |
| 777system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 774system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 778system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71741.310436 # average ReadReq mshr miss latency 779system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average ReadReq mshr miss latency 780system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average ReadReq mshr miss latency 781system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72875.434610 # average ReadReq mshr miss latency 782system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average ReadReq mshr miss latency 783system.l2c.ReadReq_avg_mshr_miss_latency::total 93895.865967 # average ReadReq mshr miss latency 784system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10096.181480 # average UpgradeReq mshr miss latency 785system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10110.003997 # average UpgradeReq mshr miss latency 786system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10099.452575 # average UpgradeReq mshr miss latency 787system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10081.812500 # average SCUpgradeReq mshr miss latency 788system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.717147 # average SCUpgradeReq mshr miss latency 789system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.098131 # average SCUpgradeReq mshr miss latency 790system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 71808.670459 # average ReadExReq mshr miss latency 791system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60613.779053 # average ReadExReq mshr miss latency 792system.l2c.ReadExReq_avg_mshr_miss_latency::total 66456.970380 # average ReadExReq mshr miss latency 793system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency | 775system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72243.981059 # average ReadReq mshr miss latency 776system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average ReadReq mshr miss latency 777system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average ReadReq mshr miss latency 778system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69294.934641 # average ReadReq mshr miss latency 779system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average ReadReq mshr miss latency 780system.l2c.ReadReq_avg_mshr_miss_latency::total 94035.801686 # average ReadReq mshr miss latency 781system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10100.493466 # average UpgradeReq mshr miss latency 782system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.597373 # average UpgradeReq mshr miss latency 783system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.680889 # average UpgradeReq mshr miss latency 784system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10125.459574 # average SCUpgradeReq mshr miss latency 785system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10045.077840 # average SCUpgradeReq mshr miss latency 786system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10066.928282 # average SCUpgradeReq mshr miss latency 787system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72242.395786 # average ReadExReq mshr miss latency 788system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61758.029925 # average ReadExReq mshr miss latency 789system.l2c.ReadExReq_avg_mshr_miss_latency::total 67237.359226 # average ReadExReq mshr miss latency 790system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency |
| 794system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 791system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 795system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency 796system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency 797system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency 798system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency 799system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency 800system.l2c.demand_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency 801system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency | 792system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency 793system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency 794system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency 795system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency 796system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency 797system.l2c.demand_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency 798system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency |
| 802system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 799system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 803system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency 804system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency 805system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency 806system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency 807system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency 808system.l2c.overall_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency | 800system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency 801system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency 802system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency 803system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency 804system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency 805system.l2c.overall_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency |
| 809system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 810system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 811system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 812system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 813system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 814system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 815system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 816system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency --- 31 unchanged lines hidden (view full) --- 848system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 849system.realview.ethernet.droppedPackets 0 # number of packets dropped 850system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 851system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 852system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 853system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 854system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 855system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 806system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 807system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 808system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 809system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 810system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 811system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 812system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 813system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency --- 31 unchanged lines hidden (view full) --- 845system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 846system.realview.ethernet.droppedPackets 0 # number of packets dropped 847system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 848system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 849system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 850system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 851system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 852system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 856system.toL2Bus.trans_dist::ReadReq 675950 # Transaction distribution 857system.toL2Bus.trans_dist::ReadResp 675935 # Transaction distribution 858system.toL2Bus.trans_dist::WriteReq 31054 # Transaction distribution 859system.toL2Bus.trans_dist::WriteResp 31054 # Transaction distribution 860system.toL2Bus.trans_dist::Writeback 253703 # Transaction distribution 861system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 862system.toL2Bus.trans_dist::UpgradeReq 93172 # Transaction distribution 863system.toL2Bus.trans_dist::SCUpgradeReq 40812 # Transaction distribution 864system.toL2Bus.trans_dist::UpgradeResp 133984 # Transaction distribution 865system.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 866system.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution 867system.toL2Bus.trans_dist::ReadExReq 39254 # Transaction distribution 868system.toL2Bus.trans_dist::ReadExResp 39254 # Transaction distribution 869system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372089 # Packet count per connected master and slave (bytes) 870system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 383613 # Packet count per connected master and slave (bytes) 871system.toL2Bus.pkt_count::total 1755702 # Packet count per connected master and slave (bytes) 872system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 42006746 # Cumulative packet size per connected master and slave (bytes) 873system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8315748 # Cumulative packet size per connected master and slave (bytes) 874system.toL2Bus.pkt_size::total 50322494 # Cumulative packet size per connected master and slave (bytes) 875system.toL2Bus.snoops 294957 # Total snoops (count) 876system.toL2Bus.snoop_fanout::samples 1100978 # Request fanout histogram 877system.toL2Bus.snoop_fanout::mean 1.033136 # Request fanout histogram 878system.toL2Bus.snoop_fanout::stdev 0.178992 # Request fanout histogram | 853system.toL2Bus.trans_dist::ReadReq 668242 # Transaction distribution 854system.toL2Bus.trans_dist::ReadResp 668227 # Transaction distribution 855system.toL2Bus.trans_dist::WriteReq 30931 # Transaction distribution 856system.toL2Bus.trans_dist::WriteResp 30931 # Transaction distribution 857system.toL2Bus.trans_dist::Writeback 252491 # Transaction distribution 858system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 859system.toL2Bus.trans_dist::UpgradeReq 92430 # Transaction distribution 860system.toL2Bus.trans_dist::SCUpgradeReq 40345 # Transaction distribution 861system.toL2Bus.trans_dist::UpgradeResp 132775 # Transaction distribution 862system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 863system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution 864system.toL2Bus.trans_dist::ReadExReq 38935 # Transaction distribution 865system.toL2Bus.trans_dist::ReadExResp 38935 # Transaction distribution 866system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370727 # Packet count per connected master and slave (bytes) 867system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368021 # Packet count per connected master and slave (bytes) 868system.toL2Bus.pkt_count::total 1738748 # Packet count per connected master and slave (bytes) 869system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41983735 # Cumulative packet size per connected master and slave (bytes) 870system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7870623 # Cumulative packet size per connected master and slave (bytes) 871system.toL2Bus.pkt_size::total 49854358 # Cumulative packet size per connected master and slave (bytes) 872system.toL2Bus.snoops 291977 # Total snoops (count) 873system.toL2Bus.snoop_fanout::samples 1090667 # Request fanout histogram 874system.toL2Bus.snoop_fanout::mean 1.033442 # Request fanout histogram 875system.toL2Bus.snoop_fanout::stdev 0.179788 # Request fanout histogram |
| 879system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 880system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 876system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 877system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 881system.toL2Bus.snoop_fanout::1 1064496 96.69% 96.69% # Request fanout histogram 882system.toL2Bus.snoop_fanout::2 36482 3.31% 100.00% # Request fanout histogram | 878system.toL2Bus.snoop_fanout::1 1054193 96.66% 96.66% # Request fanout histogram 879system.toL2Bus.snoop_fanout::2 36474 3.34% 100.00% # Request fanout histogram |
| 883system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 884system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 885system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 880system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 881system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 882system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 886system.toL2Bus.snoop_fanout::total 1100978 # Request fanout histogram 887system.toL2Bus.reqLayer0.occupancy 1599263913 # Layer occupancy (ticks) | 883system.toL2Bus.snoop_fanout::total 1090667 # Request fanout histogram 884system.toL2Bus.reqLayer0.occupancy 1589069612 # Layer occupancy (ticks) |
| 888system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 885system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 889system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) | 886system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) |
| 890system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 887system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 891system.toL2Bus.respLayer0.occupancy 2370465695 # Layer occupancy (ticks) | 888system.toL2Bus.respLayer0.occupancy 2362873368 # Layer occupancy (ticks) |
| 892system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 889system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 893system.toL2Bus.respLayer1.occupancy 831346703 # Layer occupancy (ticks) | 890system.toL2Bus.respLayer1.occupancy 802585372 # Layer occupancy (ticks) |
| 894system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 891system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 895system.iobus.trans_dist::ReadReq 31024 # Transaction distribution 896system.iobus.trans_dist::ReadResp 31024 # Transaction distribution 897system.iobus.trans_dist::WriteReq 59407 # Transaction distribution | 892system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 893system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 894system.iobus.trans_dist::WriteReq 59405 # Transaction distribution |
| 898system.iobus.trans_dist::WriteResp 59440 # Transaction distribution | 895system.iobus.trans_dist::WriteResp 59440 # Transaction distribution |
| 899system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution | 896system.iobus.trans_dist::WriteInvalidateReq 35 # Transaction distribution |
| 900system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 901system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 902system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 903system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 904system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 905system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 906system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 907system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 914system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 915system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 916system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 917system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 918system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 919system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 920system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 921system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) | 897system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 898system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 899system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 900system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 901system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 902system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 903system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 904system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 911system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 912system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 913system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 914system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 915system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 916system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 917system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 918system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) |
| 922system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 923system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 924system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) | 919system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 920system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 921system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) |
| 925system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 926system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 927system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 928system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 929system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 930system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 931system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 932system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 939system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 940system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 941system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 942system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 943system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 944system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 945system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 946system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) | 922system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 923system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 924system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 925system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 926system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 927system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 928system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 929system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 936system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 937system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 938system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 939system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 940system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 941system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 942system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 943system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) |
| 947system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 948system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 949system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) | 944system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 945system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 946system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) |
| 950system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) 951system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 952system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 953system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 954system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 955system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 956system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 957system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 24 unchanged lines hidden (view full) --- 982system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 983system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 984system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 985system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 986system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 987system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 988system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 989system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 947system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) 948system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 949system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 950system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 951system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 952system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 953system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 954system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 24 unchanged lines hidden (view full) --- 979system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 980system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 981system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 982system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 983system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 984system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 985system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 986system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 990system.iobus.reqLayer27.occupancy 326680325 # Layer occupancy (ticks) | 987system.iobus.reqLayer27.occupancy 326655076 # Layer occupancy (ticks) |
| 991system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 992system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 993system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 994system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) 995system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 988system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 989system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 990system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 991system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) 992system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 996system.iobus.respLayer3.occupancy 36847116 # Layer occupancy (ticks) | 993system.iobus.respLayer3.occupancy 36825386 # Layer occupancy (ticks) |
| 997system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 994system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 998system.cpu0.branchPred.lookups 34854856 # Number of BP lookups 999system.cpu0.branchPred.condPredicted 17109626 # Number of conditional branches predicted 1000system.cpu0.branchPred.condIncorrect 1616877 # Number of conditional branches incorrect 1001system.cpu0.branchPred.BTBLookups 20006820 # Number of BTB lookups 1002system.cpu0.branchPred.BTBHits 14503231 # Number of BTB hits | 995system.cpu0.branchPred.lookups 34893743 # Number of BP lookups 996system.cpu0.branchPred.condPredicted 17129146 # Number of conditional branches predicted 997system.cpu0.branchPred.condIncorrect 1674704 # Number of conditional branches incorrect 998system.cpu0.branchPred.BTBLookups 20005904 # Number of BTB lookups 999system.cpu0.branchPred.BTBHits 14465623 # Number of BTB hits |
| 1003system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1000system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1004system.cpu0.branchPred.BTBHitPct 72.491435 # BTB Hit Percentage 1005system.cpu0.branchPred.usedRAS 10748202 # Number of times the RAS was used to get a target. 1006system.cpu0.branchPred.RASInCorrect 771222 # Number of incorrect RAS predictions. | 1001system.cpu0.branchPred.BTBHitPct 72.306770 # BTB Hit Percentage 1002system.cpu0.branchPred.usedRAS 10813555 # Number of times the RAS was used to get a target. 1003system.cpu0.branchPred.RASInCorrect 822515 # Number of incorrect RAS predictions. |
| 1007system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1008system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1009system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1010system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1011system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1012system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1013system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1014system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1022system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1023system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1024system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1025system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1026system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1027system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1028system.cpu0.dtb.inst_hits 0 # ITB inst hits 1029system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1004system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1005system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1006system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1007system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1008system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1009system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1010system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1011system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1019system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1020system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1021system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1022system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1023system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1024system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1025system.cpu0.dtb.inst_hits 0 # ITB inst hits 1026system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1030system.cpu0.dtb.read_hits 23968692 # DTB read hits 1031system.cpu0.dtb.read_misses 61651 # DTB read misses 1032system.cpu0.dtb.write_hits 17871018 # DTB write hits 1033system.cpu0.dtb.write_misses 6619 # DTB write misses | 1027system.cpu0.dtb.read_hits 23970791 # DTB read hits 1028system.cpu0.dtb.read_misses 62431 # DTB read misses 1029system.cpu0.dtb.write_hits 17948475 # DTB write hits 1030system.cpu0.dtb.write_misses 6765 # DTB write misses |
| 1034system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1035system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1036system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1037system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1031system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1032system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1033system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1034system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1038system.cpu0.dtb.flush_entries 3502 # Number of entries that have been flushed from TLB 1039system.cpu0.dtb.align_faults 1211 # Number of TLB faults due to alignment restrictions 1040system.cpu0.dtb.prefetch_faults 1921 # Number of TLB faults due to prefetch | 1035system.cpu0.dtb.flush_entries 3473 # Number of entries that have been flushed from TLB 1036system.cpu0.dtb.align_faults 1381 # Number of TLB faults due to alignment restrictions 1037system.cpu0.dtb.prefetch_faults 1976 # Number of TLB faults due to prefetch |
| 1041system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1038system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1042system.cpu0.dtb.perms_faults 566 # Number of TLB faults due to permissions restrictions 1043system.cpu0.dtb.read_accesses 24030343 # DTB read accesses 1044system.cpu0.dtb.write_accesses 17877637 # DTB write accesses | 1039system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions 1040system.cpu0.dtb.read_accesses 24033222 # DTB read accesses 1041system.cpu0.dtb.write_accesses 17955240 # DTB write accesses |
| 1045system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1042system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1046system.cpu0.dtb.hits 41839710 # DTB hits 1047system.cpu0.dtb.misses 68270 # DTB misses 1048system.cpu0.dtb.accesses 41907980 # DTB accesses | 1043system.cpu0.dtb.hits 41919266 # DTB hits 1044system.cpu0.dtb.misses 69196 # DTB misses 1045system.cpu0.dtb.accesses 41988462 # DTB accesses |
| 1049system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1050system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1051system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1052system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1053system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1054system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1055system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1056system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1062system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1063system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1064system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1065system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1066system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1067system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1068system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1069system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1046system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1047system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1048system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1049system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1050system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1051system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1052system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1053system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1059system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1060system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1061system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1062system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1063system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1064system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1065system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1066system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1070system.cpu0.itb.inst_hits 70097291 # ITB inst hits 1071system.cpu0.itb.inst_misses 3844 # ITB inst misses | 1067system.cpu0.itb.inst_hits 70366530 # ITB inst hits 1068system.cpu0.itb.inst_misses 3846 # ITB inst misses |
| 1072system.cpu0.itb.read_hits 0 # DTB read hits 1073system.cpu0.itb.read_misses 0 # DTB read misses 1074system.cpu0.itb.write_hits 0 # DTB write hits 1075system.cpu0.itb.write_misses 0 # DTB write misses 1076system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1077system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1078system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1079system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1080system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB 1081system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1082system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1083system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1069system.cpu0.itb.read_hits 0 # DTB read hits 1070system.cpu0.itb.read_misses 0 # DTB read misses 1071system.cpu0.itb.write_hits 0 # DTB write hits 1072system.cpu0.itb.write_misses 0 # DTB write misses 1073system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1074system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1075system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1076system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1077system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB 1078system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1079system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1080system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1084system.cpu0.itb.perms_faults 7362 # Number of TLB faults due to permissions restrictions | 1081system.cpu0.itb.perms_faults 7369 # Number of TLB faults due to permissions restrictions |
| 1085system.cpu0.itb.read_accesses 0 # DTB read accesses 1086system.cpu0.itb.write_accesses 0 # DTB write accesses | 1082system.cpu0.itb.read_accesses 0 # DTB read accesses 1083system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1087system.cpu0.itb.inst_accesses 70101135 # ITB inst accesses 1088system.cpu0.itb.hits 70097291 # DTB hits 1089system.cpu0.itb.misses 3844 # DTB misses 1090system.cpu0.itb.accesses 70101135 # DTB accesses 1091system.cpu0.numCycles 227722348 # number of cpu cycles simulated | 1084system.cpu0.itb.inst_accesses 70370376 # ITB inst accesses 1085system.cpu0.itb.hits 70366530 # DTB hits 1086system.cpu0.itb.misses 3846 # DTB misses 1087system.cpu0.itb.accesses 70370376 # DTB accesses 1088system.cpu0.numCycles 229133691 # number of cpu cycles simulated |
| 1092system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1093system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1089system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1090system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1094system.cpu0.committedInsts 109201964 # Number of instructions committed 1095system.cpu0.committedOps 132004483 # Number of ops (including micro ops) committed 1096system.cpu0.discardedOps 8817575 # Number of ops (including micro ops) which were discarded before commit 1097system.cpu0.numFetchSuspends 1858 # Number of times Execute suspended instruction fetching 1098system.cpu0.quiesceCycles 5459726684 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1099system.cpu0.cpi 2.085332 # CPI: cycles per instruction 1100system.cpu0.ipc 0.479540 # IPC: instructions per cycle | 1091system.cpu0.committedInsts 109191897 # Number of instructions committed 1092system.cpu0.committedOps 132018821 # Number of ops (including micro ops) committed 1093system.cpu0.discardedOps 8795011 # Number of ops (including micro ops) which were discarded before commit 1094system.cpu0.numFetchSuspends 1826 # Number of times Execute suspended instruction fetching 1095system.cpu0.quiesceCycles 5458210303 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1096system.cpu0.cpi 2.098450 # CPI: cycles per instruction 1097system.cpu0.ipc 0.476542 # IPC: instructions per cycle |
| 1101system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1098system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1102system.cpu0.kern.inst.quiesce 1864 # number of quiesce instructions executed 1103system.cpu0.tickCycles 192189087 # Number of cycles that the object actually ticked 1104system.cpu0.idleCycles 35533261 # Total number of cycles that the object has spent stopped 1105system.cpu0.icache.tags.replacements 1960423 # number of replacements 1106system.cpu0.icache.tags.tagsinuse 511.796865 # Cycle average of tags in use 1107system.cpu0.icache.tags.total_refs 68128653 # Total number of references to valid blocks. 1108system.cpu0.icache.tags.sampled_refs 1960935 # Sample count of references to valid blocks. 1109system.cpu0.icache.tags.avg_refs 34.742943 # Average number of references to valid blocks. | 1099system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed 1100system.cpu0.tickCycles 193242697 # Number of cycles that the object actually ticked 1101system.cpu0.idleCycles 35890994 # Total number of cycles that the object has spent stopped 1102system.cpu0.icache.tags.replacements 1983122 # number of replacements 1103system.cpu0.icache.tags.tagsinuse 511.796419 # Cycle average of tags in use 1104system.cpu0.icache.tags.total_refs 68375163 # Total number of references to valid blocks. 1105system.cpu0.icache.tags.sampled_refs 1983634 # Sample count of references to valid blocks. 1106system.cpu0.icache.tags.avg_refs 34.469647 # Average number of references to valid blocks. |
| 1110system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. | 1107system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. |
| 1111system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796865 # Average occupied blocks per requestor 1112system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy 1113system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy | 1108system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796419 # Average occupied blocks per requestor 1109system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999602 # Average percentage of cache occupancy 1110system.cpu0.icache.tags.occ_percent::total 0.999602 # Average percentage of cache occupancy |
| 1114system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1115system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id | 1111system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1112system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id |
| 1116system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 1117system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id | 1113system.cpu0.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id 1114system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id |
| 1118system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1115system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1119system.cpu0.icache.tags.tag_accesses 142140155 # Number of tag accesses 1120system.cpu0.icache.tags.data_accesses 142140155 # Number of data accesses 1121system.cpu0.icache.ReadReq_hits::cpu0.inst 68128653 # number of ReadReq hits 1122system.cpu0.icache.ReadReq_hits::total 68128653 # number of ReadReq hits 1123system.cpu0.icache.demand_hits::cpu0.inst 68128653 # number of demand (read+write) hits 1124system.cpu0.icache.demand_hits::total 68128653 # number of demand (read+write) hits 1125system.cpu0.icache.overall_hits::cpu0.inst 68128653 # number of overall hits 1126system.cpu0.icache.overall_hits::total 68128653 # number of overall hits 1127system.cpu0.icache.ReadReq_misses::cpu0.inst 1960950 # number of ReadReq misses 1128system.cpu0.icache.ReadReq_misses::total 1960950 # number of ReadReq misses 1129system.cpu0.icache.demand_misses::cpu0.inst 1960950 # number of demand (read+write) misses 1130system.cpu0.icache.demand_misses::total 1960950 # number of demand (read+write) misses 1131system.cpu0.icache.overall_misses::cpu0.inst 1960950 # number of overall misses 1132system.cpu0.icache.overall_misses::total 1960950 # number of overall misses 1133system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16347715808 # number of ReadReq miss cycles 1134system.cpu0.icache.ReadReq_miss_latency::total 16347715808 # number of ReadReq miss cycles 1135system.cpu0.icache.demand_miss_latency::cpu0.inst 16347715808 # number of demand (read+write) miss cycles 1136system.cpu0.icache.demand_miss_latency::total 16347715808 # number of demand (read+write) miss cycles 1137system.cpu0.icache.overall_miss_latency::cpu0.inst 16347715808 # number of overall miss cycles 1138system.cpu0.icache.overall_miss_latency::total 16347715808 # number of overall miss cycles 1139system.cpu0.icache.ReadReq_accesses::cpu0.inst 70089603 # number of ReadReq accesses(hits+misses) 1140system.cpu0.icache.ReadReq_accesses::total 70089603 # number of ReadReq accesses(hits+misses) 1141system.cpu0.icache.demand_accesses::cpu0.inst 70089603 # number of demand (read+write) accesses 1142system.cpu0.icache.demand_accesses::total 70089603 # number of demand (read+write) accesses 1143system.cpu0.icache.overall_accesses::cpu0.inst 70089603 # number of overall (read+write) accesses 1144system.cpu0.icache.overall_accesses::total 70089603 # number of overall (read+write) accesses 1145system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027978 # miss rate for ReadReq accesses 1146system.cpu0.icache.ReadReq_miss_rate::total 0.027978 # miss rate for ReadReq accesses 1147system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027978 # miss rate for demand accesses 1148system.cpu0.icache.demand_miss_rate::total 0.027978 # miss rate for demand accesses 1149system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027978 # miss rate for overall accesses 1150system.cpu0.icache.overall_miss_rate::total 0.027978 # miss rate for overall accesses 1151system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8336.630617 # average ReadReq miss latency 1152system.cpu0.icache.ReadReq_avg_miss_latency::total 8336.630617 # average ReadReq miss latency 1153system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency 1154system.cpu0.icache.demand_avg_miss_latency::total 8336.630617 # average overall miss latency 1155system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency 1156system.cpu0.icache.overall_avg_miss_latency::total 8336.630617 # average overall miss latency | 1116system.cpu0.icache.tags.tag_accesses 142701293 # Number of tag accesses 1117system.cpu0.icache.tags.data_accesses 142701293 # Number of data accesses 1118system.cpu0.icache.ReadReq_hits::cpu0.inst 68375163 # number of ReadReq hits 1119system.cpu0.icache.ReadReq_hits::total 68375163 # number of ReadReq hits 1120system.cpu0.icache.demand_hits::cpu0.inst 68375163 # number of demand (read+write) hits 1121system.cpu0.icache.demand_hits::total 68375163 # number of demand (read+write) hits 1122system.cpu0.icache.overall_hits::cpu0.inst 68375163 # number of overall hits 1123system.cpu0.icache.overall_hits::total 68375163 # number of overall hits 1124system.cpu0.icache.ReadReq_misses::cpu0.inst 1983656 # number of ReadReq misses 1125system.cpu0.icache.ReadReq_misses::total 1983656 # number of ReadReq misses 1126system.cpu0.icache.demand_misses::cpu0.inst 1983656 # number of demand (read+write) misses 1127system.cpu0.icache.demand_misses::total 1983656 # number of demand (read+write) misses 1128system.cpu0.icache.overall_misses::cpu0.inst 1983656 # number of overall misses 1129system.cpu0.icache.overall_misses::total 1983656 # number of overall misses 1130system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16542962894 # number of ReadReq miss cycles 1131system.cpu0.icache.ReadReq_miss_latency::total 16542962894 # number of ReadReq miss cycles 1132system.cpu0.icache.demand_miss_latency::cpu0.inst 16542962894 # number of demand (read+write) miss cycles 1133system.cpu0.icache.demand_miss_latency::total 16542962894 # number of demand (read+write) miss cycles 1134system.cpu0.icache.overall_miss_latency::cpu0.inst 16542962894 # number of overall miss cycles 1135system.cpu0.icache.overall_miss_latency::total 16542962894 # number of overall miss cycles 1136system.cpu0.icache.ReadReq_accesses::cpu0.inst 70358819 # number of ReadReq accesses(hits+misses) 1137system.cpu0.icache.ReadReq_accesses::total 70358819 # number of ReadReq accesses(hits+misses) 1138system.cpu0.icache.demand_accesses::cpu0.inst 70358819 # number of demand (read+write) accesses 1139system.cpu0.icache.demand_accesses::total 70358819 # number of demand (read+write) accesses 1140system.cpu0.icache.overall_accesses::cpu0.inst 70358819 # number of overall (read+write) accesses 1141system.cpu0.icache.overall_accesses::total 70358819 # number of overall (read+write) accesses 1142system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028193 # miss rate for ReadReq accesses 1143system.cpu0.icache.ReadReq_miss_rate::total 0.028193 # miss rate for ReadReq accesses 1144system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028193 # miss rate for demand accesses 1145system.cpu0.icache.demand_miss_rate::total 0.028193 # miss rate for demand accesses 1146system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028193 # miss rate for overall accesses 1147system.cpu0.icache.overall_miss_rate::total 0.028193 # miss rate for overall accesses 1148system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.632927 # average ReadReq miss latency 1149system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.632927 # average ReadReq miss latency 1150system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency 1151system.cpu0.icache.demand_avg_miss_latency::total 8339.632927 # average overall miss latency 1152system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency 1153system.cpu0.icache.overall_avg_miss_latency::total 8339.632927 # average overall miss latency |
| 1157system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1158system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1159system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1160system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1161system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1162system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1163system.cpu0.icache.fast_writes 0 # number of fast writes performed 1164system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1154system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1155system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1156system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1157system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1158system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1159system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1160system.cpu0.icache.fast_writes 0 # number of fast writes performed 1161system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1165system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1960950 # number of ReadReq MSHR misses 1166system.cpu0.icache.ReadReq_mshr_misses::total 1960950 # number of ReadReq MSHR misses 1167system.cpu0.icache.demand_mshr_misses::cpu0.inst 1960950 # number of demand (read+write) MSHR misses 1168system.cpu0.icache.demand_mshr_misses::total 1960950 # number of demand (read+write) MSHR misses 1169system.cpu0.icache.overall_mshr_misses::cpu0.inst 1960950 # number of overall MSHR misses 1170system.cpu0.icache.overall_mshr_misses::total 1960950 # number of overall MSHR misses 1171system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13404270692 # number of ReadReq MSHR miss cycles 1172system.cpu0.icache.ReadReq_mshr_miss_latency::total 13404270692 # number of ReadReq MSHR miss cycles 1173system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13404270692 # number of demand (read+write) MSHR miss cycles 1174system.cpu0.icache.demand_mshr_miss_latency::total 13404270692 # number of demand (read+write) MSHR miss cycles 1175system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13404270692 # number of overall MSHR miss cycles 1176system.cpu0.icache.overall_mshr_miss_latency::total 13404270692 # number of overall MSHR miss cycles 1177system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276968500 # number of ReadReq MSHR uncacheable cycles 1178system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276968500 # number of ReadReq MSHR uncacheable cycles 1179system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276968500 # number of overall MSHR uncacheable cycles 1180system.cpu0.icache.overall_mshr_uncacheable_latency::total 276968500 # number of overall MSHR uncacheable cycles 1181system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for ReadReq accesses 1182system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027978 # mshr miss rate for ReadReq accesses 1183system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for demand accesses 1184system.cpu0.icache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses 1185system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for overall accesses 1186system.cpu0.icache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses 1187system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average ReadReq mshr miss latency 1188system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6835.600445 # average ReadReq mshr miss latency 1189system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency 1190system.cpu0.icache.demand_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency 1191system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency 1192system.cpu0.icache.overall_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency | 1162system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1983656 # number of ReadReq MSHR misses 1163system.cpu0.icache.ReadReq_mshr_misses::total 1983656 # number of ReadReq MSHR misses 1164system.cpu0.icache.demand_mshr_misses::cpu0.inst 1983656 # number of demand (read+write) MSHR misses 1165system.cpu0.icache.demand_mshr_misses::total 1983656 # number of demand (read+write) MSHR misses 1166system.cpu0.icache.overall_mshr_misses::cpu0.inst 1983656 # number of overall MSHR misses 1167system.cpu0.icache.overall_mshr_misses::total 1983656 # number of overall MSHR misses 1168system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13565509604 # number of ReadReq MSHR miss cycles 1169system.cpu0.icache.ReadReq_mshr_miss_latency::total 13565509604 # number of ReadReq MSHR miss cycles 1170system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13565509604 # number of demand (read+write) MSHR miss cycles 1171system.cpu0.icache.demand_mshr_miss_latency::total 13565509604 # number of demand (read+write) MSHR miss cycles 1172system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13565509604 # number of overall MSHR miss cycles 1173system.cpu0.icache.overall_mshr_miss_latency::total 13565509604 # number of overall MSHR miss cycles 1174system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276787500 # number of ReadReq MSHR uncacheable cycles 1175system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276787500 # number of ReadReq MSHR uncacheable cycles 1176system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276787500 # number of overall MSHR uncacheable cycles 1177system.cpu0.icache.overall_mshr_uncacheable_latency::total 276787500 # number of overall MSHR uncacheable cycles 1178system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for ReadReq accesses 1179system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028193 # mshr miss rate for ReadReq accesses 1180system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for demand accesses 1181system.cpu0.icache.demand_mshr_miss_rate::total 0.028193 # mshr miss rate for demand accesses 1182system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for overall accesses 1183system.cpu0.icache.overall_mshr_miss_rate::total 0.028193 # mshr miss rate for overall accesses 1184system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average ReadReq mshr miss latency 1185system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.640169 # average ReadReq mshr miss latency 1186system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency 1187system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency 1188system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency 1189system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency |
| 1193system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1194system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1195system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1196system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1197system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1190system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1191system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1192system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1193system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1194system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1198system.cpu0.toL2Bus.trans_dist::ReadReq 2745512 # Transaction distribution 1199system.cpu0.toL2Bus.trans_dist::ReadResp 2644445 # Transaction distribution 1200system.cpu0.toL2Bus.trans_dist::WriteReq 28520 # Transaction distribution 1201system.cpu0.toL2Bus.trans_dist::WriteResp 28520 # Transaction distribution 1202system.cpu0.toL2Bus.trans_dist::Writeback 513053 # Transaction distribution 1203system.cpu0.toL2Bus.trans_dist::HardPFReq 701523 # Transaction distribution 1204system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 1205system.cpu0.toL2Bus.trans_dist::UpgradeReq 70947 # Transaction distribution 1206system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43092 # Transaction distribution 1207system.cpu0.toL2Bus.trans_dist::UpgradeResp 94006 # Transaction distribution 1208system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution 1209system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution 1210system.cpu0.toL2Bus.trans_dist::ReadExReq 290299 # Transaction distribution 1211system.cpu0.toL2Bus.trans_dist::ReadExResp 280446 # Transaction distribution 1212system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3928023 # Packet count per connected master and slave (bytes) 1213system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2381529 # Packet count per connected master and slave (bytes) 1214system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11804 # Packet count per connected master and slave (bytes) 1215system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166842 # Packet count per connected master and slave (bytes) 1216system.cpu0.toL2Bus.pkt_count::total 6488198 # Packet count per connected master and slave (bytes) 1217system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 125696704 # Cumulative packet size per connected master and slave (bytes) 1218system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86351322 # Cumulative packet size per connected master and slave (bytes) 1219system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17688 # Cumulative packet size per connected master and slave (bytes) 1220system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313268 # Cumulative packet size per connected master and slave (bytes) 1221system.cpu0.toL2Bus.pkt_size::total 212378982 # Cumulative packet size per connected master and slave (bytes) 1222system.cpu0.toL2Bus.snoops 1094951 # Total snoops (count) 1223system.cpu0.toL2Bus.snoop_fanout::samples 4365889 # Request fanout histogram 1224system.cpu0.toL2Bus.snoop_fanout::mean 5.223377 # Request fanout histogram 1225system.cpu0.toL2Bus.snoop_fanout::stdev 0.416509 # Request fanout histogram | 1195system.cpu0.toL2Bus.trans_dist::ReadReq 2764616 # Transaction distribution 1196system.cpu0.toL2Bus.trans_dist::ReadResp 2669805 # Transaction distribution 1197system.cpu0.toL2Bus.trans_dist::WriteReq 28812 # Transaction distribution 1198system.cpu0.toL2Bus.trans_dist::WriteResp 28812 # Transaction distribution 1199system.cpu0.toL2Bus.trans_dist::Writeback 518092 # Transaction distribution 1200system.cpu0.toL2Bus.trans_dist::HardPFReq 696796 # Transaction distribution 1201system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 1202system.cpu0.toL2Bus.trans_dist::UpgradeReq 70569 # Transaction distribution 1203system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42644 # Transaction distribution 1204system.cpu0.toL2Bus.trans_dist::UpgradeResp 93797 # Transaction distribution 1205system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 1206system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution 1207system.cpu0.toL2Bus.trans_dist::ReadExReq 291655 # Transaction distribution 1208system.cpu0.toL2Bus.trans_dist::ReadExResp 282058 # Transaction distribution 1209system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3973433 # Packet count per connected master and slave (bytes) 1210system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393866 # Packet count per connected master and slave (bytes) 1211system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11794 # Packet count per connected master and slave (bytes) 1212system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167556 # Packet count per connected master and slave (bytes) 1213system.cpu0.toL2Bus.pkt_count::total 6546649 # Packet count per connected master and slave (bytes) 1214system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127149824 # Cumulative packet size per connected master and slave (bytes) 1215system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86895095 # Cumulative packet size per connected master and slave (bytes) 1216system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17624 # Cumulative packet size per connected master and slave (bytes) 1217system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313964 # Cumulative packet size per connected master and slave (bytes) 1218system.cpu0.toL2Bus.pkt_size::total 214376507 # Cumulative packet size per connected master and slave (bytes) 1219system.cpu0.toL2Bus.snoops 1084116 # Total snoops (count) 1220system.cpu0.toL2Bus.snoop_fanout::samples 4385551 # Request fanout histogram 1221system.cpu0.toL2Bus.snoop_fanout::mean 5.219745 # Request fanout histogram 1222system.cpu0.toL2Bus.snoop_fanout::stdev 0.414074 # Request fanout histogram |
| 1226system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1227system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1228system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1229system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1230system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1231system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1223system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1224system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1225system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1226system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1227system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1228system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1232system.cpu0.toL2Bus.snoop_fanout::5 3390648 77.66% 77.66% # Request fanout histogram 1233system.cpu0.toL2Bus.snoop_fanout::6 975241 22.34% 100.00% # Request fanout histogram | 1229system.cpu0.toL2Bus.snoop_fanout::5 3421847 78.03% 78.03% # Request fanout histogram 1230system.cpu0.toL2Bus.snoop_fanout::6 963704 21.97% 100.00% # Request fanout histogram |
| 1234system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1235system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1236system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1231system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1232system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1233system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1237system.cpu0.toL2Bus.snoop_fanout::total 4365889 # Request fanout histogram 1238system.cpu0.toL2Bus.reqLayer0.occupancy 2254798560 # Layer occupancy (ticks) | 1234system.cpu0.toL2Bus.snoop_fanout::total 4385551 # Request fanout histogram 1235system.cpu0.toL2Bus.reqLayer0.occupancy 2275908733 # Layer occupancy (ticks) |
| 1239system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1236system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1240system.cpu0.toL2Bus.snoopLayer0.occupancy 118870000 # Layer occupancy (ticks) | 1237system.cpu0.toL2Bus.snoopLayer0.occupancy 119359000 # Layer occupancy (ticks) |
| 1241system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1238system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1242system.cpu0.toL2Bus.respLayer0.occupancy 2947700808 # Layer occupancy (ticks) | 1239system.cpu0.toL2Bus.respLayer0.occupancy 2981732395 # Layer occupancy (ticks) |
| 1243system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1240system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1244system.cpu0.toL2Bus.respLayer1.occupancy 1230574902 # Layer occupancy (ticks) | 1241system.cpu0.toL2Bus.respLayer1.occupancy 1235696460 # Layer occupancy (ticks) |
| 1245system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1242system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1246system.cpu0.toL2Bus.respLayer2.occupancy 7385992 # Layer occupancy (ticks) | 1243system.cpu0.toL2Bus.respLayer2.occupancy 7392491 # Layer occupancy (ticks) |
| 1247system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1244system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1248system.cpu0.toL2Bus.respLayer3.occupancy 88548223 # Layer occupancy (ticks) | 1245system.cpu0.toL2Bus.respLayer3.occupancy 89085972 # Layer occupancy (ticks) |
| 1249system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1246system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1250system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17144913 # number of hwpf identified 1251system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425558 # number of hwpf that were already in mshr 1252system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16187872 # number of hwpf that were already in the cache 1253system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8427 # number of hwpf that were already in the prefetch queue | 1247system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17333419 # number of hwpf identified 1248system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425629 # number of hwpf that were already in mshr 1249system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16380209 # number of hwpf that were already in the cache 1250system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9025 # number of hwpf that were already in the prefetch queue |
| 1254system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1251system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1255system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6267 # number of hwpf removed because MSHR allocated 1256system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 516786 # number of hwpf issued 1257system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1326511 # number of hwpf spanning a virtual page | 1252system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6465 # number of hwpf removed because MSHR allocated 1253system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512088 # number of hwpf issued 1254system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329549 # number of hwpf spanning a virtual page |
| 1258system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1255system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1259system.cpu0.l2cache.tags.replacements 410501 # number of replacements 1260system.cpu0.l2cache.tags.tagsinuse 16214.104593 # Cycle average of tags in use 1261system.cpu0.l2cache.tags.total_refs 2982888 # Total number of references to valid blocks. 1262system.cpu0.l2cache.tags.sampled_refs 426752 # Sample count of references to valid blocks. 1263system.cpu0.l2cache.tags.avg_refs 6.989746 # Average number of references to valid blocks. 1264system.cpu0.l2cache.tags.warmup_cycle 2824483316500 # Cycle when the warmup percentage was hit. 1265system.cpu0.l2cache.tags.occ_blocks::writebacks 4342.913069 # Average occupied blocks per requestor 1266system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.461328 # Average occupied blocks per requestor 1267system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076713 # Average occupied blocks per requestor 1268system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2208.018647 # Average occupied blocks per requestor 1269system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9615.634836 # Average occupied blocks per requestor 1270system.cpu0.l2cache.tags.occ_percent::writebacks 0.265070 # Average percentage of cache occupancy 1271system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002897 # Average percentage of cache occupancy 1272system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 1273system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134767 # Average percentage of cache occupancy 1274system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.586892 # Average percentage of cache occupancy 1275system.cpu0.l2cache.tags.occ_percent::total 0.989630 # Average percentage of cache occupancy 1276system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8959 # Occupied blocks per task id 1277system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 1278system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7283 # Occupied blocks per task id 1279system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 66 # Occupied blocks per task id 1280system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id 1281system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2957 # Occupied blocks per task id 1282system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5162 # Occupied blocks per task id 1283system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 667 # Occupied blocks per task id 1284system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id | 1256system.cpu0.l2cache.tags.replacements 409658 # number of replacements 1257system.cpu0.l2cache.tags.tagsinuse 16201.472263 # Cycle average of tags in use 1258system.cpu0.l2cache.tags.total_refs 3013143 # Total number of references to valid blocks. 1259system.cpu0.l2cache.tags.sampled_refs 425913 # Sample count of references to valid blocks. 1260system.cpu0.l2cache.tags.avg_refs 7.074550 # Average number of references to valid blocks. 1261system.cpu0.l2cache.tags.warmup_cycle 2824446064500 # Cycle when the warmup percentage was hit. 1262system.cpu0.l2cache.tags.occ_blocks::writebacks 4208.967244 # Average occupied blocks per requestor 1263system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.817277 # Average occupied blocks per requestor 1264system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.069510 # Average occupied blocks per requestor 1265system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2196.768436 # Average occupied blocks per requestor 1266system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.849796 # Average occupied blocks per requestor 1267system.cpu0.l2cache.tags.occ_percent::writebacks 0.256895 # Average percentage of cache occupancy 1268system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002919 # Average percentage of cache occupancy 1269system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 1270system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134080 # Average percentage of cache occupancy 1271system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594962 # Average percentage of cache occupancy 1272system.cpu0.l2cache.tags.occ_percent::total 0.988859 # Average percentage of cache occupancy 1273system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8953 # Occupied blocks per task id 1274system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1275system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7296 # Occupied blocks per task id 1276system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id 1277system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id 1278system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2849 # Occupied blocks per task id 1279system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5159 # Occupied blocks per task id 1280system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 779 # Occupied blocks per task id |
| 1285system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id | 1281system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id |
| 1286system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 1287system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 1288system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id 1289system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3107 # Occupied blocks per task id 1290system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3633 # Occupied blocks per task id 1291system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 224 # Occupied blocks per task id 1292system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546814 # Percentage of cache occupancy per task id 1293system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 1294system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444519 # Percentage of cache occupancy per task id 1295system.cpu0.l2cache.tags.tag_accesses 54811525 # Number of tag accesses 1296system.cpu0.l2cache.tags.data_accesses 54811525 # Number of data accesses 1297system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77296 # number of ReadReq hits 1298system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4241 # number of ReadReq hits 1299system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2365837 # number of ReadReq hits 1300system.cpu0.l2cache.ReadReq_hits::total 2447374 # number of ReadReq hits 1301system.cpu0.l2cache.Writeback_hits::writebacks 513053 # number of Writeback hits 1302system.cpu0.l2cache.Writeback_hits::total 513053 # number of Writeback hits 1303system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4545 # number of UpgradeReq hits 1304system.cpu0.l2cache.UpgradeReq_hits::total 4545 # number of UpgradeReq hits 1305system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2277 # number of SCUpgradeReq hits 1306system.cpu0.l2cache.SCUpgradeReq_hits::total 2277 # number of SCUpgradeReq hits 1307system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 221177 # number of ReadExReq hits 1308system.cpu0.l2cache.ReadExReq_hits::total 221177 # number of ReadExReq hits 1309system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77296 # number of demand (read+write) hits 1310system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4241 # number of demand (read+write) hits 1311system.cpu0.l2cache.demand_hits::cpu0.inst 2587014 # number of demand (read+write) hits 1312system.cpu0.l2cache.demand_hits::total 2668551 # number of demand (read+write) hits 1313system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77296 # number of overall hits 1314system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4241 # number of overall hits 1315system.cpu0.l2cache.overall_hits::cpu0.inst 2587014 # number of overall hits 1316system.cpu0.l2cache.overall_hits::total 2668551 # number of overall hits 1317system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 1021 # number of ReadReq misses 1318system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 181 # number of ReadReq misses 1319system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94620 # number of ReadReq misses 1320system.cpu0.l2cache.ReadReq_misses::total 95822 # number of ReadReq misses 1321system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 28011 # number of UpgradeReq misses 1322system.cpu0.l2cache.UpgradeReq_misses::total 28011 # number of UpgradeReq misses 1323system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 18233 # number of SCUpgradeReq misses 1324system.cpu0.l2cache.SCUpgradeReq_misses::total 18233 # number of SCUpgradeReq misses 1325system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46900 # number of ReadExReq misses 1326system.cpu0.l2cache.ReadExReq_misses::total 46900 # number of ReadExReq misses 1327system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 1021 # number of demand (read+write) misses 1328system.cpu0.l2cache.demand_misses::cpu0.itb.walker 181 # number of demand (read+write) misses 1329system.cpu0.l2cache.demand_misses::cpu0.inst 141520 # number of demand (read+write) misses 1330system.cpu0.l2cache.demand_misses::total 142722 # number of demand (read+write) misses 1331system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 1021 # number of overall misses 1332system.cpu0.l2cache.overall_misses::cpu0.itb.walker 181 # number of overall misses 1333system.cpu0.l2cache.overall_misses::cpu0.inst 141520 # number of overall misses 1334system.cpu0.l2cache.overall_misses::total 142722 # number of overall misses 1335system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 34165499 # number of ReadReq miss cycles 1336system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4027498 # number of ReadReq miss cycles 1337system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2870753873 # number of ReadReq miss cycles 1338system.cpu0.l2cache.ReadReq_miss_latency::total 2908946870 # number of ReadReq miss cycles 1339system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 500227988 # number of UpgradeReq miss cycles 1340system.cpu0.l2cache.UpgradeReq_miss_latency::total 500227988 # number of UpgradeReq miss cycles 1341system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 361106760 # number of SCUpgradeReq miss cycles 1342system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 361106760 # number of SCUpgradeReq miss cycles 1343system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 90500 # number of SCUpgradeFailReq miss cycles 1344system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 90500 # number of SCUpgradeFailReq miss cycles 1345system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1915708255 # number of ReadExReq miss cycles 1346system.cpu0.l2cache.ReadExReq_miss_latency::total 1915708255 # number of ReadExReq miss cycles 1347system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 34165499 # number of demand (read+write) miss cycles 1348system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4027498 # number of demand (read+write) miss cycles 1349system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4786462128 # number of demand (read+write) miss cycles 1350system.cpu0.l2cache.demand_miss_latency::total 4824655125 # number of demand (read+write) miss cycles 1351system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 34165499 # number of overall miss cycles 1352system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4027498 # number of overall miss cycles 1353system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4786462128 # number of overall miss cycles 1354system.cpu0.l2cache.overall_miss_latency::total 4824655125 # number of overall miss cycles 1355system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78317 # number of ReadReq accesses(hits+misses) 1356system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4422 # number of ReadReq accesses(hits+misses) 1357system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2460457 # number of ReadReq accesses(hits+misses) 1358system.cpu0.l2cache.ReadReq_accesses::total 2543196 # number of ReadReq accesses(hits+misses) 1359system.cpu0.l2cache.Writeback_accesses::writebacks 513053 # number of Writeback accesses(hits+misses) 1360system.cpu0.l2cache.Writeback_accesses::total 513053 # number of Writeback accesses(hits+misses) 1361system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32556 # number of UpgradeReq accesses(hits+misses) 1362system.cpu0.l2cache.UpgradeReq_accesses::total 32556 # number of UpgradeReq accesses(hits+misses) 1363system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20510 # number of SCUpgradeReq accesses(hits+misses) 1364system.cpu0.l2cache.SCUpgradeReq_accesses::total 20510 # number of SCUpgradeReq accesses(hits+misses) 1365system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 268077 # number of ReadExReq accesses(hits+misses) 1366system.cpu0.l2cache.ReadExReq_accesses::total 268077 # number of ReadExReq accesses(hits+misses) 1367system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78317 # number of demand (read+write) accesses 1368system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4422 # number of demand (read+write) accesses 1369system.cpu0.l2cache.demand_accesses::cpu0.inst 2728534 # number of demand (read+write) accesses 1370system.cpu0.l2cache.demand_accesses::total 2811273 # number of demand (read+write) accesses 1371system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78317 # number of overall (read+write) accesses 1372system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4422 # number of overall (read+write) accesses 1373system.cpu0.l2cache.overall_accesses::cpu0.inst 2728534 # number of overall (read+write) accesses 1374system.cpu0.l2cache.overall_accesses::total 2811273 # number of overall (read+write) accesses 1375system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for ReadReq accesses 1376system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040932 # miss rate for ReadReq accesses 1377system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.038456 # miss rate for ReadReq accesses 1378system.cpu0.l2cache.ReadReq_miss_rate::total 0.037678 # miss rate for ReadReq accesses 1379system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.860394 # miss rate for UpgradeReq accesses 1380system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.860394 # miss rate for UpgradeReq accesses 1381system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.888981 # miss rate for SCUpgradeReq accesses 1382system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.888981 # miss rate for SCUpgradeReq accesses 1383system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.174950 # miss rate for ReadExReq accesses 1384system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174950 # miss rate for ReadExReq accesses 1385system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for demand accesses 1386system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040932 # miss rate for demand accesses 1387system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051867 # miss rate for demand accesses 1388system.cpu0.l2cache.demand_miss_rate::total 0.050768 # miss rate for demand accesses 1389system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for overall accesses 1390system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040932 # miss rate for overall accesses 1391system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051867 # miss rate for overall accesses 1392system.cpu0.l2cache.overall_miss_rate::total 0.050768 # miss rate for overall accesses 1393system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average ReadReq miss latency 1394system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22251.370166 # average ReadReq miss latency 1395system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30339.821105 # average ReadReq miss latency 1396system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30357.818351 # average ReadReq miss latency 1397system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17858.269537 # average UpgradeReq miss latency 1398system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17858.269537 # average UpgradeReq miss latency 1399system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19805.120386 # average SCUpgradeReq miss latency 1400system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19805.120386 # average SCUpgradeReq miss latency 1401system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency 1402system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1403system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 40846.657889 # average ReadExReq miss latency 1404system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 40846.657889 # average ReadExReq miss latency 1405system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average overall miss latency 1406system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22251.370166 # average overall miss latency 1407system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33821.807010 # average overall miss latency 1408system.cpu0.l2cache.demand_avg_miss_latency::total 33804.564993 # average overall miss latency 1409system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average overall miss latency 1410system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22251.370166 # average overall miss latency 1411system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33821.807010 # average overall miss latency 1412system.cpu0.l2cache.overall_avg_miss_latency::total 33804.564993 # average overall miss latency 1413system.cpu0.l2cache.blocked_cycles::no_mshrs 27297 # number of cycles access was blocked | 1282system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 1283system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1284system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 1285system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id 1286system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3166 # Occupied blocks per task id 1287system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id 1288system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 286 # Occupied blocks per task id 1289system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546448 # Percentage of cache occupancy per task id 1290system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 1291system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.445312 # Percentage of cache occupancy per task id 1292system.cpu0.l2cache.tags.tag_accesses 55304097 # Number of tag accesses 1293system.cpu0.l2cache.tags.data_accesses 55304097 # Number of data accesses 1294system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77521 # number of ReadReq hits 1295system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4240 # number of ReadReq hits 1296system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390628 # number of ReadReq hits 1297system.cpu0.l2cache.ReadReq_hits::total 2472389 # number of ReadReq hits 1298system.cpu0.l2cache.Writeback_hits::writebacks 518092 # number of Writeback hits 1299system.cpu0.l2cache.Writeback_hits::total 518092 # number of Writeback hits 1300system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4676 # number of UpgradeReq hits 1301system.cpu0.l2cache.UpgradeReq_hits::total 4676 # number of UpgradeReq hits 1302system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2297 # number of SCUpgradeReq hits 1303system.cpu0.l2cache.SCUpgradeReq_hits::total 2297 # number of SCUpgradeReq hits 1304system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223112 # number of ReadExReq hits 1305system.cpu0.l2cache.ReadExReq_hits::total 223112 # number of ReadExReq hits 1306system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77521 # number of demand (read+write) hits 1307system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4240 # number of demand (read+write) hits 1308system.cpu0.l2cache.demand_hits::cpu0.inst 2613740 # number of demand (read+write) hits 1309system.cpu0.l2cache.demand_hits::total 2695501 # number of demand (read+write) hits 1310system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77521 # number of overall hits 1311system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4240 # number of overall hits 1312system.cpu0.l2cache.overall_hits::cpu0.inst 2613740 # number of overall hits 1313system.cpu0.l2cache.overall_hits::total 2695501 # number of overall hits 1314system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 970 # number of ReadReq misses 1315system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 166 # number of ReadReq misses 1316system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94231 # number of ReadReq misses 1317system.cpu0.l2cache.ReadReq_misses::total 95367 # number of ReadReq misses 1318system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27951 # number of UpgradeReq misses 1319system.cpu0.l2cache.UpgradeReq_misses::total 27951 # number of UpgradeReq misses 1320system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17951 # number of SCUpgradeReq misses 1321system.cpu0.l2cache.SCUpgradeReq_misses::total 17951 # number of SCUpgradeReq misses 1322system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 2 # number of SCUpgradeFailReq misses 1323system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1324system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46376 # number of ReadExReq misses 1325system.cpu0.l2cache.ReadExReq_misses::total 46376 # number of ReadExReq misses 1326system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 970 # number of demand (read+write) misses 1327system.cpu0.l2cache.demand_misses::cpu0.itb.walker 166 # number of demand (read+write) misses 1328system.cpu0.l2cache.demand_misses::cpu0.inst 140607 # number of demand (read+write) misses 1329system.cpu0.l2cache.demand_misses::total 141743 # number of demand (read+write) misses 1330system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 970 # number of overall misses 1331system.cpu0.l2cache.overall_misses::cpu0.itb.walker 166 # number of overall misses 1332system.cpu0.l2cache.overall_misses::cpu0.inst 140607 # number of overall misses 1333system.cpu0.l2cache.overall_misses::total 141743 # number of overall misses 1334system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31913749 # number of ReadReq miss cycles 1335system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3705999 # number of ReadReq miss cycles 1336system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2892277884 # number of ReadReq miss cycles 1337system.cpu0.l2cache.ReadReq_miss_latency::total 2927897632 # number of ReadReq miss cycles 1338system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 496957551 # number of UpgradeReq miss cycles 1339system.cpu0.l2cache.UpgradeReq_miss_latency::total 496957551 # number of UpgradeReq miss cycles 1340system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 355013747 # number of SCUpgradeReq miss cycles 1341system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 355013747 # number of SCUpgradeReq miss cycles 1342system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 117000 # number of SCUpgradeFailReq miss cycles 1343system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 117000 # number of SCUpgradeFailReq miss cycles 1344system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1927567955 # number of ReadExReq miss cycles 1345system.cpu0.l2cache.ReadExReq_miss_latency::total 1927567955 # number of ReadExReq miss cycles 1346system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31913749 # number of demand (read+write) miss cycles 1347system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3705999 # number of demand (read+write) miss cycles 1348system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4819845839 # number of demand (read+write) miss cycles 1349system.cpu0.l2cache.demand_miss_latency::total 4855465587 # number of demand (read+write) miss cycles 1350system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31913749 # number of overall miss cycles 1351system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3705999 # number of overall miss cycles 1352system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4819845839 # number of overall miss cycles 1353system.cpu0.l2cache.overall_miss_latency::total 4855465587 # number of overall miss cycles 1354system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78491 # number of ReadReq accesses(hits+misses) 1355system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4406 # number of ReadReq accesses(hits+misses) 1356system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2484859 # number of ReadReq accesses(hits+misses) 1357system.cpu0.l2cache.ReadReq_accesses::total 2567756 # number of ReadReq accesses(hits+misses) 1358system.cpu0.l2cache.Writeback_accesses::writebacks 518092 # number of Writeback accesses(hits+misses) 1359system.cpu0.l2cache.Writeback_accesses::total 518092 # number of Writeback accesses(hits+misses) 1360system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32627 # number of UpgradeReq accesses(hits+misses) 1361system.cpu0.l2cache.UpgradeReq_accesses::total 32627 # number of UpgradeReq accesses(hits+misses) 1362system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20248 # number of SCUpgradeReq accesses(hits+misses) 1363system.cpu0.l2cache.SCUpgradeReq_accesses::total 20248 # number of SCUpgradeReq accesses(hits+misses) 1364system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 2 # number of SCUpgradeFailReq accesses(hits+misses) 1365system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1366system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 269488 # number of ReadExReq accesses(hits+misses) 1367system.cpu0.l2cache.ReadExReq_accesses::total 269488 # number of ReadExReq accesses(hits+misses) 1368system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78491 # number of demand (read+write) accesses 1369system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4406 # number of demand (read+write) accesses 1370system.cpu0.l2cache.demand_accesses::cpu0.inst 2754347 # number of demand (read+write) accesses 1371system.cpu0.l2cache.demand_accesses::total 2837244 # number of demand (read+write) accesses 1372system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78491 # number of overall (read+write) accesses 1373system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4406 # number of overall (read+write) accesses 1374system.cpu0.l2cache.overall_accesses::cpu0.inst 2754347 # number of overall (read+write) accesses 1375system.cpu0.l2cache.overall_accesses::total 2837244 # number of overall (read+write) accesses 1376system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for ReadReq accesses 1377system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037676 # miss rate for ReadReq accesses 1378system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037922 # miss rate for ReadReq accesses 1379system.cpu0.l2cache.ReadReq_miss_rate::total 0.037140 # miss rate for ReadReq accesses 1380system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.856683 # miss rate for UpgradeReq accesses 1381system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.856683 # miss rate for UpgradeReq accesses 1382system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.886557 # miss rate for SCUpgradeReq accesses 1383system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.886557 # miss rate for SCUpgradeReq accesses 1384system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses 1385system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1386system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.172089 # miss rate for ReadExReq accesses 1387system.cpu0.l2cache.ReadExReq_miss_rate::total 0.172089 # miss rate for ReadExReq accesses 1388system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for demand accesses 1389system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037676 # miss rate for demand accesses 1390system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051049 # miss rate for demand accesses 1391system.cpu0.l2cache.demand_miss_rate::total 0.049958 # miss rate for demand accesses 1392system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for overall accesses 1393system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037676 # miss rate for overall accesses 1394system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051049 # miss rate for overall accesses 1395system.cpu0.l2cache.overall_miss_rate::total 0.049958 # miss rate for overall accesses 1396system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average ReadReq miss latency 1397system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22325.295181 # average ReadReq miss latency 1398system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30693.486050 # average ReadReq miss latency 1399system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30701.370831 # average ReadReq miss latency 1400system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17779.598261 # average UpgradeReq miss latency 1401system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17779.598261 # average UpgradeReq miss latency 1402system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19776.822851 # average SCUpgradeReq miss latency 1403system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19776.822851 # average SCUpgradeReq miss latency 1404system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 58500 # average SCUpgradeFailReq miss latency 1405system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 58500 # average SCUpgradeFailReq miss latency 1406system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41563.911398 # average ReadExReq miss latency 1407system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41563.911398 # average ReadExReq miss latency 1408system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average overall miss latency 1409system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22325.295181 # average overall miss latency 1410system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34278.846992 # average overall miss latency 1411system.cpu0.l2cache.demand_avg_miss_latency::total 34255.417107 # average overall miss latency 1412system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average overall miss latency 1413system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22325.295181 # average overall miss latency 1414system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34278.846992 # average overall miss latency 1415system.cpu0.l2cache.overall_avg_miss_latency::total 34255.417107 # average overall miss latency 1416system.cpu0.l2cache.blocked_cycles::no_mshrs 26197 # number of cycles access was blocked |
| 1414system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1417system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1415system.cpu0.l2cache.blocked::no_mshrs 390 # number of cycles access was blocked | 1418system.cpu0.l2cache.blocked::no_mshrs 374 # number of cycles access was blocked |
| 1416system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1419system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1417system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 69.992308 # average number of cycles each access was blocked | 1420system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 70.045455 # average number of cycles each access was blocked |
| 1418system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1419system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1420system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1421system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1422system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1423system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1421system.cpu0.l2cache.writebacks::writebacks 214261 # number of writebacks 1422system.cpu0.l2cache.writebacks::total 214261 # number of writebacks 1423system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7719 # number of ReadReq MSHR hits 1424system.cpu0.l2cache.ReadReq_mshr_hits::total 7719 # number of ReadReq MSHR hits 1425system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3119 # number of ReadExReq MSHR hits 1426system.cpu0.l2cache.ReadExReq_mshr_hits::total 3119 # number of ReadExReq MSHR hits 1427system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10838 # number of demand (read+write) MSHR hits 1428system.cpu0.l2cache.demand_mshr_hits::total 10838 # number of demand (read+write) MSHR hits 1429system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10838 # number of overall MSHR hits 1430system.cpu0.l2cache.overall_mshr_hits::total 10838 # number of overall MSHR hits 1431system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 1021 # number of ReadReq MSHR misses 1432system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 181 # number of ReadReq MSHR misses 1433system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86901 # number of ReadReq MSHR misses 1434system.cpu0.l2cache.ReadReq_mshr_misses::total 88103 # number of ReadReq MSHR misses 1435system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 516784 # number of HardPFReq MSHR misses 1436system.cpu0.l2cache.HardPFReq_mshr_misses::total 516784 # number of HardPFReq MSHR misses 1437system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 28011 # number of UpgradeReq MSHR misses 1438system.cpu0.l2cache.UpgradeReq_mshr_misses::total 28011 # number of UpgradeReq MSHR misses 1439system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 18233 # number of SCUpgradeReq MSHR misses 1440system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18233 # number of SCUpgradeReq MSHR misses 1441system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43781 # number of ReadExReq MSHR misses 1442system.cpu0.l2cache.ReadExReq_mshr_misses::total 43781 # number of ReadExReq MSHR misses 1443system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 1021 # number of demand (read+write) MSHR misses 1444system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 181 # number of demand (read+write) MSHR misses 1445system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 130682 # number of demand (read+write) MSHR misses 1446system.cpu0.l2cache.demand_mshr_misses::total 131884 # number of demand (read+write) MSHR misses 1447system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 1021 # number of overall MSHR misses 1448system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 181 # number of overall MSHR misses 1449system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 130682 # number of overall MSHR misses 1450system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 516784 # number of overall MSHR misses 1451system.cpu0.l2cache.overall_mshr_misses::total 648668 # number of overall MSHR misses 1452system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of ReadReq MSHR miss cycles 1453system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2760498 # number of ReadReq MSHR miss cycles 1454system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2099218995 # number of ReadReq MSHR miss cycles 1455system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2128978496 # number of ReadReq MSHR miss cycles 1456system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21179021871 # number of HardPFReq MSHR miss cycles 1457system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21179021871 # number of HardPFReq MSHR miss cycles 1458system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 474290503 # number of UpgradeReq MSHR miss cycles 1459system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 474290503 # number of UpgradeReq MSHR miss cycles 1460system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 241043533 # number of SCUpgradeReq MSHR miss cycles 1461system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 241043533 # number of SCUpgradeReq MSHR miss cycles 1462system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 69500 # number of SCUpgradeFailReq MSHR miss cycles 1463system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 69500 # number of SCUpgradeFailReq MSHR miss cycles 1464system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1189749710 # number of ReadExReq MSHR miss cycles 1465system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1189749710 # number of ReadExReq MSHR miss cycles 1466system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of demand (read+write) MSHR miss cycles 1467system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2760498 # number of demand (read+write) MSHR miss cycles 1468system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3288968705 # number of demand (read+write) MSHR miss cycles 1469system.cpu0.l2cache.demand_mshr_miss_latency::total 3318728206 # number of demand (read+write) MSHR miss cycles 1470system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of overall MSHR miss cycles 1471system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2760498 # number of overall MSHR miss cycles 1472system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3288968705 # number of overall MSHR miss cycles 1473system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21179021871 # number of overall MSHR miss cycles 1474system.cpu0.l2cache.overall_mshr_miss_latency::total 24497750077 # number of overall MSHR miss cycles 1475system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6107809749 # number of ReadReq MSHR uncacheable cycles 1476system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6107809749 # number of ReadReq MSHR uncacheable cycles 1477system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4518638513 # number of WriteReq MSHR uncacheable cycles 1478system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4518638513 # number of WriteReq MSHR uncacheable cycles 1479system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10626448262 # number of overall MSHR uncacheable cycles 1480system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10626448262 # number of overall MSHR uncacheable cycles 1481system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for ReadReq accesses 1482system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for ReadReq accesses 1483system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.035319 # mshr miss rate for ReadReq accesses 1484system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034643 # mshr miss rate for ReadReq accesses | 1424system.cpu0.l2cache.writebacks::writebacks 214192 # number of writebacks 1425system.cpu0.l2cache.writebacks::total 214192 # number of writebacks 1426system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7707 # number of ReadReq MSHR hits 1427system.cpu0.l2cache.ReadReq_mshr_hits::total 7707 # number of ReadReq MSHR hits 1428system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3080 # number of ReadExReq MSHR hits 1429system.cpu0.l2cache.ReadExReq_mshr_hits::total 3080 # number of ReadExReq MSHR hits 1430system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10787 # number of demand (read+write) MSHR hits 1431system.cpu0.l2cache.demand_mshr_hits::total 10787 # number of demand (read+write) MSHR hits 1432system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10787 # number of overall MSHR hits 1433system.cpu0.l2cache.overall_mshr_hits::total 10787 # number of overall MSHR hits 1434system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 970 # number of ReadReq MSHR misses 1435system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 166 # number of ReadReq MSHR misses 1436system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86524 # number of ReadReq MSHR misses 1437system.cpu0.l2cache.ReadReq_mshr_misses::total 87660 # number of ReadReq MSHR misses 1438system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 512085 # number of HardPFReq MSHR misses 1439system.cpu0.l2cache.HardPFReq_mshr_misses::total 512085 # number of HardPFReq MSHR misses 1440system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27951 # number of UpgradeReq MSHR misses 1441system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27951 # number of UpgradeReq MSHR misses 1442system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17951 # number of SCUpgradeReq MSHR misses 1443system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17951 # number of SCUpgradeReq MSHR misses 1444system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 2 # number of SCUpgradeFailReq MSHR misses 1445system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1446system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43296 # number of ReadExReq MSHR misses 1447system.cpu0.l2cache.ReadExReq_mshr_misses::total 43296 # number of ReadExReq MSHR misses 1448system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 970 # number of demand (read+write) MSHR misses 1449system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 166 # number of demand (read+write) MSHR misses 1450system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 129820 # number of demand (read+write) MSHR misses 1451system.cpu0.l2cache.demand_mshr_misses::total 130956 # number of demand (read+write) MSHR misses 1452system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 970 # number of overall MSHR misses 1453system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 166 # number of overall MSHR misses 1454system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 129820 # number of overall MSHR misses 1455system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 512085 # number of overall MSHR misses 1456system.cpu0.l2cache.overall_mshr_misses::total 643041 # number of overall MSHR misses 1457system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of ReadReq MSHR miss cycles 1458system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2543999 # number of ReadReq MSHR miss cycles 1459system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2121731252 # number of ReadReq MSHR miss cycles 1460system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2149385000 # number of ReadReq MSHR miss cycles 1461system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21314968847 # number of HardPFReq MSHR miss cycles 1462system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21314968847 # number of HardPFReq MSHR miss cycles 1463system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 476593305 # number of UpgradeReq MSHR miss cycles 1464system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 476593305 # number of UpgradeReq MSHR miss cycles 1465system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 237494522 # number of SCUpgradeReq MSHR miss cycles 1466system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 237494522 # number of SCUpgradeReq MSHR miss cycles 1467system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 89000 # number of SCUpgradeFailReq MSHR miss cycles 1468system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 89000 # number of SCUpgradeFailReq MSHR miss cycles 1469system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1192659250 # number of ReadExReq MSHR miss cycles 1470system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1192659250 # number of ReadExReq MSHR miss cycles 1471system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of demand (read+write) MSHR miss cycles 1472system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2543999 # number of demand (read+write) MSHR miss cycles 1473system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3314390502 # number of demand (read+write) MSHR miss cycles 1474system.cpu0.l2cache.demand_mshr_miss_latency::total 3342044250 # number of demand (read+write) MSHR miss cycles 1475system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of overall MSHR miss cycles 1476system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2543999 # number of overall MSHR miss cycles 1477system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3314390502 # number of overall MSHR miss cycles 1478system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21314968847 # number of overall MSHR miss cycles 1479system.cpu0.l2cache.overall_mshr_miss_latency::total 24657013097 # number of overall MSHR miss cycles 1480system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6176307748 # number of ReadReq MSHR uncacheable cycles 1481system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6176307748 # number of ReadReq MSHR uncacheable cycles 1482system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4587485503 # number of WriteReq MSHR uncacheable cycles 1483system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4587485503 # number of WriteReq MSHR uncacheable cycles 1484system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10763793251 # number of overall MSHR uncacheable cycles 1485system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10763793251 # number of overall MSHR uncacheable cycles 1486system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for ReadReq accesses 1487system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for ReadReq accesses 1488system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034820 # mshr miss rate for ReadReq accesses 1489system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034139 # mshr miss rate for ReadReq accesses |
| 1485system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1486system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1490system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1491system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1487system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.860394 # mshr miss rate for UpgradeReq accesses 1488system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.860394 # mshr miss rate for UpgradeReq accesses 1489system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888981 # mshr miss rate for SCUpgradeReq accesses 1490system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888981 # mshr miss rate for SCUpgradeReq accesses 1491system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.163315 # mshr miss rate for ReadExReq accesses 1492system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163315 # mshr miss rate for ReadExReq accesses 1493system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for demand accesses 1494system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for demand accesses 1495system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047895 # mshr miss rate for demand accesses 1496system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046913 # mshr miss rate for demand accesses 1497system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for overall accesses 1498system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for overall accesses 1499system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047895 # mshr miss rate for overall accesses | 1492system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856683 # mshr miss rate for UpgradeReq accesses 1493system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856683 # mshr miss rate for UpgradeReq accesses 1494system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.886557 # mshr miss rate for SCUpgradeReq accesses 1495system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.886557 # mshr miss rate for SCUpgradeReq accesses 1496system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 1497system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1498system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160660 # mshr miss rate for ReadExReq accesses 1499system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160660 # mshr miss rate for ReadExReq accesses 1500system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for demand accesses 1501system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for demand accesses 1502system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for demand accesses 1503system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046156 # mshr miss rate for demand accesses 1504system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for overall accesses 1505system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for overall accesses 1506system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for overall accesses |
| 1500system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1507system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1501system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230738 # mshr miss rate for overall accesses 1502system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average ReadReq mshr miss latency 1503system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average ReadReq mshr miss latency 1504system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24156.442331 # average ReadReq mshr miss latency 1505system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24164.653826 # average ReadReq mshr miss latency 1506system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275 # average HardPFReq mshr miss latency 1507system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40982.348275 # average HardPFReq mshr miss latency 1508system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16932.294563 # average UpgradeReq mshr miss latency 1509system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16932.294563 # average UpgradeReq mshr miss latency 1510system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13220.179510 # average SCUpgradeReq mshr miss latency 1511system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13220.179510 # average SCUpgradeReq mshr miss latency 1512system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency 1513system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1514system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27175.023640 # average ReadExReq mshr miss latency 1515system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27175.023640 # average ReadExReq mshr miss latency 1516system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average overall mshr miss latency 1517system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average overall mshr miss latency 1518system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency 1519system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25163.994162 # average overall mshr miss latency 1520system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average overall mshr miss latency 1521system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average overall mshr miss latency 1522system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency 1523system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275 # average overall mshr miss latency 1524system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37766.238009 # average overall mshr miss latency | 1508system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226643 # mshr miss rate for overall accesses 1509system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average ReadReq mshr miss latency 1510system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average ReadReq mshr miss latency 1511system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24521.881235 # average ReadReq mshr miss latency 1512system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24519.564225 # average ReadReq mshr miss latency 1513system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average HardPFReq mshr miss latency 1514system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41623.888313 # average HardPFReq mshr miss latency 1515system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17051.028765 # average UpgradeReq mshr miss latency 1516system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17051.028765 # average UpgradeReq mshr miss latency 1517system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13230.155535 # average SCUpgradeReq mshr miss latency 1518system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13230.155535 # average SCUpgradeReq mshr miss latency 1519system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 44500 # average SCUpgradeFailReq mshr miss latency 1520system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 44500 # average SCUpgradeFailReq mshr miss latency 1521system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27546.638258 # average ReadExReq mshr miss latency 1522system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27546.638258 # average ReadExReq mshr miss latency 1523system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency 1524system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency 1525system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency 1526system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25520.359892 # average overall mshr miss latency 1527system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency 1528system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency 1529system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency 1530system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average overall mshr miss latency 1531system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38344.387212 # average overall mshr miss latency |
| 1525system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1526system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1527system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1528system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1529system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1530system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1531system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1532system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1533system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1534system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1535system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1536system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1537system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1538system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1532system.cpu0.dcache.tags.replacements 712097 # number of replacements 1533system.cpu0.dcache.tags.tagsinuse 497.191982 # Cycle average of tags in use 1534system.cpu0.dcache.tags.total_refs 40404438 # Total number of references to valid blocks. 1535system.cpu0.dcache.tags.sampled_refs 712609 # Sample count of references to valid blocks. 1536system.cpu0.dcache.tags.avg_refs 56.699309 # Average number of references to valid blocks. 1537system.cpu0.dcache.tags.warmup_cycle 306793500 # Cycle when the warmup percentage was hit. 1538system.cpu0.dcache.tags.occ_blocks::cpu0.inst 497.191982 # Average occupied blocks per requestor 1539system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.971078 # Average percentage of cache occupancy 1540system.cpu0.dcache.tags.occ_percent::total 0.971078 # Average percentage of cache occupancy | 1539system.cpu0.dcache.tags.replacements 714989 # number of replacements 1540system.cpu0.dcache.tags.tagsinuse 494.379861 # Cycle average of tags in use 1541system.cpu0.dcache.tags.total_refs 40475201 # Total number of references to valid blocks. 1542system.cpu0.dcache.tags.sampled_refs 715501 # Sample count of references to valid blocks. 1543system.cpu0.dcache.tags.avg_refs 56.569035 # Average number of references to valid blocks. 1544system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit. 1545system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.379861 # Average occupied blocks per requestor 1546system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965586 # Average percentage of cache occupancy 1547system.cpu0.dcache.tags.occ_percent::total 0.965586 # Average percentage of cache occupancy |
| 1541system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1548system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1542system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id 1543system.cpu0.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id 1544system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id | 1549system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id 1550system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 1551system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id |
| 1545system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1552system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1546system.cpu0.dcache.tags.tag_accesses 83631959 # Number of tag accesses 1547system.cpu0.dcache.tags.data_accesses 83631959 # Number of data accesses 1548system.cpu0.dcache.ReadReq_hits::cpu0.inst 22807107 # number of ReadReq hits 1549system.cpu0.dcache.ReadReq_hits::total 22807107 # number of ReadReq hits 1550system.cpu0.dcache.WriteReq_hits::cpu0.inst 16791710 # number of WriteReq hits 1551system.cpu0.dcache.WriteReq_hits::total 16791710 # number of WriteReq hits 1552system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 380026 # number of LoadLockedReq hits 1553system.cpu0.dcache.LoadLockedReq_hits::total 380026 # number of LoadLockedReq hits 1554system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 361110 # number of StoreCondReq hits 1555system.cpu0.dcache.StoreCondReq_hits::total 361110 # number of StoreCondReq hits 1556system.cpu0.dcache.demand_hits::cpu0.inst 39598817 # number of demand (read+write) hits 1557system.cpu0.dcache.demand_hits::total 39598817 # number of demand (read+write) hits 1558system.cpu0.dcache.overall_hits::cpu0.inst 39598817 # number of overall hits 1559system.cpu0.dcache.overall_hits::total 39598817 # number of overall hits 1560system.cpu0.dcache.ReadReq_misses::cpu0.inst 535335 # number of ReadReq misses 1561system.cpu0.dcache.ReadReq_misses::total 535335 # number of ReadReq misses 1562system.cpu0.dcache.WriteReq_misses::cpu0.inst 529873 # number of WriteReq misses 1563system.cpu0.dcache.WriteReq_misses::total 529873 # number of WriteReq misses 1564system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6515 # number of LoadLockedReq misses 1565system.cpu0.dcache.LoadLockedReq_misses::total 6515 # number of LoadLockedReq misses 1566system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20510 # number of StoreCondReq misses 1567system.cpu0.dcache.StoreCondReq_misses::total 20510 # number of StoreCondReq misses 1568system.cpu0.dcache.demand_misses::cpu0.inst 1065208 # number of demand (read+write) misses 1569system.cpu0.dcache.demand_misses::total 1065208 # number of demand (read+write) misses 1570system.cpu0.dcache.overall_misses::cpu0.inst 1065208 # number of overall misses 1571system.cpu0.dcache.overall_misses::total 1065208 # number of overall misses 1572system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6583386279 # number of ReadReq miss cycles 1573system.cpu0.dcache.ReadReq_miss_latency::total 6583386279 # number of ReadReq miss cycles 1574system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 7974270273 # number of WriteReq miss cycles 1575system.cpu0.dcache.WriteReq_miss_latency::total 7974270273 # number of WriteReq miss cycles 1576system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 107544752 # number of LoadLockedReq miss cycles 1577system.cpu0.dcache.LoadLockedReq_miss_latency::total 107544752 # number of LoadLockedReq miss cycles 1578system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 444281550 # number of StoreCondReq miss cycles 1579system.cpu0.dcache.StoreCondReq_miss_latency::total 444281550 # number of StoreCondReq miss cycles 1580system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 99500 # number of StoreCondFailReq miss cycles 1581system.cpu0.dcache.StoreCondFailReq_miss_latency::total 99500 # number of StoreCondFailReq miss cycles 1582system.cpu0.dcache.demand_miss_latency::cpu0.inst 14557656552 # number of demand (read+write) miss cycles 1583system.cpu0.dcache.demand_miss_latency::total 14557656552 # number of demand (read+write) miss cycles 1584system.cpu0.dcache.overall_miss_latency::cpu0.inst 14557656552 # number of overall miss cycles 1585system.cpu0.dcache.overall_miss_latency::total 14557656552 # number of overall miss cycles 1586system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23342442 # number of ReadReq accesses(hits+misses) 1587system.cpu0.dcache.ReadReq_accesses::total 23342442 # number of ReadReq accesses(hits+misses) 1588system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17321583 # number of WriteReq accesses(hits+misses) 1589system.cpu0.dcache.WriteReq_accesses::total 17321583 # number of WriteReq accesses(hits+misses) 1590system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 386541 # number of LoadLockedReq accesses(hits+misses) 1591system.cpu0.dcache.LoadLockedReq_accesses::total 386541 # number of LoadLockedReq accesses(hits+misses) 1592system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 381620 # number of StoreCondReq accesses(hits+misses) 1593system.cpu0.dcache.StoreCondReq_accesses::total 381620 # number of StoreCondReq accesses(hits+misses) 1594system.cpu0.dcache.demand_accesses::cpu0.inst 40664025 # number of demand (read+write) accesses 1595system.cpu0.dcache.demand_accesses::total 40664025 # number of demand (read+write) accesses 1596system.cpu0.dcache.overall_accesses::cpu0.inst 40664025 # number of overall (read+write) accesses 1597system.cpu0.dcache.overall_accesses::total 40664025 # number of overall (read+write) accesses 1598system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.022934 # miss rate for ReadReq accesses 1599system.cpu0.dcache.ReadReq_miss_rate::total 0.022934 # miss rate for ReadReq accesses 1600system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030590 # miss rate for WriteReq accesses 1601system.cpu0.dcache.WriteReq_miss_rate::total 0.030590 # miss rate for WriteReq accesses 1602system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016855 # miss rate for LoadLockedReq accesses 1603system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016855 # miss rate for LoadLockedReq accesses 1604system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.053745 # miss rate for StoreCondReq accesses 1605system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053745 # miss rate for StoreCondReq accesses 1606system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026195 # miss rate for demand accesses 1607system.cpu0.dcache.demand_miss_rate::total 0.026195 # miss rate for demand accesses 1608system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026195 # miss rate for overall accesses 1609system.cpu0.dcache.overall_miss_rate::total 0.026195 # miss rate for overall accesses 1610system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12297.694488 # average ReadReq miss latency 1611system.cpu0.dcache.ReadReq_avg_miss_latency::total 12297.694488 # average ReadReq miss latency 1612system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15049.399145 # average WriteReq miss latency 1613system.cpu0.dcache.WriteReq_avg_miss_latency::total 15049.399145 # average WriteReq miss latency 1614system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16507.252801 # average LoadLockedReq miss latency 1615system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16507.252801 # average LoadLockedReq miss latency 1616system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21661.704047 # average StoreCondReq miss latency 1617system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21661.704047 # average StoreCondReq miss latency | 1553system.cpu0.dcache.tags.tag_accesses 83786238 # Number of tag accesses 1554system.cpu0.dcache.tags.data_accesses 83786238 # Number of data accesses 1555system.cpu0.dcache.ReadReq_hits::cpu0.inst 22803865 # number of ReadReq hits 1556system.cpu0.dcache.ReadReq_hits::total 22803865 # number of ReadReq hits 1557system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862785 # number of WriteReq hits 1558system.cpu0.dcache.WriteReq_hits::total 16862785 # number of WriteReq hits 1559system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381543 # number of LoadLockedReq hits 1560system.cpu0.dcache.LoadLockedReq_hits::total 381543 # number of LoadLockedReq hits 1561system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362585 # number of StoreCondReq hits 1562system.cpu0.dcache.StoreCondReq_hits::total 362585 # number of StoreCondReq hits 1563system.cpu0.dcache.demand_hits::cpu0.inst 39666650 # number of demand (read+write) hits 1564system.cpu0.dcache.demand_hits::total 39666650 # number of demand (read+write) hits 1565system.cpu0.dcache.overall_hits::cpu0.inst 39666650 # number of overall hits 1566system.cpu0.dcache.overall_hits::total 39666650 # number of overall hits 1567system.cpu0.dcache.ReadReq_misses::cpu0.inst 537471 # number of ReadReq misses 1568system.cpu0.dcache.ReadReq_misses::total 537471 # number of ReadReq misses 1569system.cpu0.dcache.WriteReq_misses::cpu0.inst 532850 # number of WriteReq misses 1570system.cpu0.dcache.WriteReq_misses::total 532850 # number of WriteReq misses 1571system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6422 # number of LoadLockedReq misses 1572system.cpu0.dcache.LoadLockedReq_misses::total 6422 # number of LoadLockedReq misses 1573system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20250 # number of StoreCondReq misses 1574system.cpu0.dcache.StoreCondReq_misses::total 20250 # number of StoreCondReq misses 1575system.cpu0.dcache.demand_misses::cpu0.inst 1070321 # number of demand (read+write) misses 1576system.cpu0.dcache.demand_misses::total 1070321 # number of demand (read+write) misses 1577system.cpu0.dcache.overall_misses::cpu0.inst 1070321 # number of overall misses 1578system.cpu0.dcache.overall_misses::total 1070321 # number of overall misses 1579system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609205728 # number of ReadReq miss cycles 1580system.cpu0.dcache.ReadReq_miss_latency::total 6609205728 # number of ReadReq miss cycles 1581system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8024129751 # number of WriteReq miss cycles 1582system.cpu0.dcache.WriteReq_miss_latency::total 8024129751 # number of WriteReq miss cycles 1583system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 106247249 # number of LoadLockedReq miss cycles 1584system.cpu0.dcache.LoadLockedReq_miss_latency::total 106247249 # number of LoadLockedReq miss cycles 1585system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 438093543 # number of StoreCondReq miss cycles 1586system.cpu0.dcache.StoreCondReq_miss_latency::total 438093543 # number of StoreCondReq miss cycles 1587system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles 1588system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles 1589system.cpu0.dcache.demand_miss_latency::cpu0.inst 14633335479 # number of demand (read+write) miss cycles 1590system.cpu0.dcache.demand_miss_latency::total 14633335479 # number of demand (read+write) miss cycles 1591system.cpu0.dcache.overall_miss_latency::cpu0.inst 14633335479 # number of overall miss cycles 1592system.cpu0.dcache.overall_miss_latency::total 14633335479 # number of overall miss cycles 1593system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23341336 # number of ReadReq accesses(hits+misses) 1594system.cpu0.dcache.ReadReq_accesses::total 23341336 # number of ReadReq accesses(hits+misses) 1595system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395635 # number of WriteReq accesses(hits+misses) 1596system.cpu0.dcache.WriteReq_accesses::total 17395635 # number of WriteReq accesses(hits+misses) 1597system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387965 # number of LoadLockedReq accesses(hits+misses) 1598system.cpu0.dcache.LoadLockedReq_accesses::total 387965 # number of LoadLockedReq accesses(hits+misses) 1599system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382835 # number of StoreCondReq accesses(hits+misses) 1600system.cpu0.dcache.StoreCondReq_accesses::total 382835 # number of StoreCondReq accesses(hits+misses) 1601system.cpu0.dcache.demand_accesses::cpu0.inst 40736971 # number of demand (read+write) accesses 1602system.cpu0.dcache.demand_accesses::total 40736971 # number of demand (read+write) accesses 1603system.cpu0.dcache.overall_accesses::cpu0.inst 40736971 # number of overall (read+write) accesses 1604system.cpu0.dcache.overall_accesses::total 40736971 # number of overall (read+write) accesses 1605system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023027 # miss rate for ReadReq accesses 1606system.cpu0.dcache.ReadReq_miss_rate::total 0.023027 # miss rate for ReadReq accesses 1607system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030631 # miss rate for WriteReq accesses 1608system.cpu0.dcache.WriteReq_miss_rate::total 0.030631 # miss rate for WriteReq accesses 1609system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016553 # miss rate for LoadLockedReq accesses 1610system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016553 # miss rate for LoadLockedReq accesses 1611system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052895 # miss rate for StoreCondReq accesses 1612system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052895 # miss rate for StoreCondReq accesses 1613system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026274 # miss rate for demand accesses 1614system.cpu0.dcache.demand_miss_rate::total 0.026274 # miss rate for demand accesses 1615system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026274 # miss rate for overall accesses 1616system.cpu0.dcache.overall_miss_rate::total 0.026274 # miss rate for overall accesses 1617system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12296.860162 # average ReadReq miss latency 1618system.cpu0.dcache.ReadReq_avg_miss_latency::total 12296.860162 # average ReadReq miss latency 1619system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15058.890403 # average WriteReq miss latency 1620system.cpu0.dcache.WriteReq_avg_miss_latency::total 15058.890403 # average WriteReq miss latency 1621system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16544.261756 # average LoadLockedReq miss latency 1622system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16544.261756 # average LoadLockedReq miss latency 1623system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21634.249037 # average StoreCondReq miss latency 1624system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21634.249037 # average StoreCondReq miss latency |
| 1618system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 1619system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1625system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 1626system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1620system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13666.491945 # average overall miss latency 1621system.cpu0.dcache.demand_avg_miss_latency::total 13666.491945 # average overall miss latency 1622system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13666.491945 # average overall miss latency 1623system.cpu0.dcache.overall_avg_miss_latency::total 13666.491945 # average overall miss latency | 1627system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency 1628system.cpu0.dcache.demand_avg_miss_latency::total 13671.912892 # average overall miss latency 1629system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency 1630system.cpu0.dcache.overall_avg_miss_latency::total 13671.912892 # average overall miss latency |
| 1624system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1625system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1626system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1627system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1628system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1629system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1630system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1631system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1631system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1632system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1633system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1634system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1635system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1636system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1637system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1638system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1632system.cpu0.dcache.writebacks::writebacks 513055 # number of writebacks 1633system.cpu0.dcache.writebacks::total 513055 # number of writebacks 1634system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42339 # number of ReadReq MSHR hits 1635system.cpu0.dcache.ReadReq_mshr_hits::total 42339 # number of ReadReq MSHR hits 1636system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 229244 # number of WriteReq MSHR hits 1637system.cpu0.dcache.WriteReq_mshr_hits::total 229244 # number of WriteReq MSHR hits 1638system.cpu0.dcache.demand_mshr_hits::cpu0.inst 271583 # number of demand (read+write) MSHR hits 1639system.cpu0.dcache.demand_mshr_hits::total 271583 # number of demand (read+write) MSHR hits 1640system.cpu0.dcache.overall_mshr_hits::cpu0.inst 271583 # number of overall MSHR hits 1641system.cpu0.dcache.overall_mshr_hits::total 271583 # number of overall MSHR hits 1642system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 492996 # number of ReadReq MSHR misses 1643system.cpu0.dcache.ReadReq_mshr_misses::total 492996 # number of ReadReq MSHR misses 1644system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 300629 # number of WriteReq MSHR misses 1645system.cpu0.dcache.WriteReq_mshr_misses::total 300629 # number of WriteReq MSHR misses 1646system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6515 # number of LoadLockedReq MSHR misses 1647system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6515 # number of LoadLockedReq MSHR misses 1648system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20510 # number of StoreCondReq MSHR misses 1649system.cpu0.dcache.StoreCondReq_mshr_misses::total 20510 # number of StoreCondReq MSHR misses 1650system.cpu0.dcache.demand_mshr_misses::cpu0.inst 793625 # number of demand (read+write) MSHR misses 1651system.cpu0.dcache.demand_mshr_misses::total 793625 # number of demand (read+write) MSHR misses 1652system.cpu0.dcache.overall_mshr_misses::cpu0.inst 793625 # number of overall MSHR misses 1653system.cpu0.dcache.overall_mshr_misses::total 793625 # number of overall MSHR misses 1654system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5093716162 # number of ReadReq MSHR miss cycles 1655system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5093716162 # number of ReadReq MSHR miss cycles 1656system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4246170249 # number of WriteReq MSHR miss cycles 1657system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4246170249 # number of WriteReq MSHR miss cycles 1658system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 94499248 # number of LoadLockedReq MSHR miss cycles 1659system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94499248 # number of LoadLockedReq MSHR miss cycles 1660system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 402814450 # number of StoreCondReq MSHR miss cycles 1661system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 402814450 # number of StoreCondReq MSHR miss cycles 1662system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 93500 # number of StoreCondFailReq MSHR miss cycles 1663system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 93500 # number of StoreCondFailReq MSHR miss cycles 1664system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9339886411 # number of demand (read+write) MSHR miss cycles 1665system.cpu0.dcache.demand_mshr_miss_latency::total 9339886411 # number of demand (read+write) MSHR miss cycles 1666system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9339886411 # number of overall MSHR miss cycles 1667system.cpu0.dcache.overall_mshr_miss_latency::total 9339886411 # number of overall MSHR miss cycles 1668system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6120470998 # number of ReadReq MSHR uncacheable cycles 1669system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6120470998 # number of ReadReq MSHR uncacheable cycles 1670system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4732689487 # number of WriteReq MSHR uncacheable cycles 1671system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4732689487 # number of WriteReq MSHR uncacheable cycles 1672system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10853160485 # number of overall MSHR uncacheable cycles 1673system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10853160485 # number of overall MSHR uncacheable cycles 1674system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021120 # mshr miss rate for ReadReq accesses 1675system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021120 # mshr miss rate for ReadReq accesses 1676system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017356 # mshr miss rate for WriteReq accesses 1677system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017356 # mshr miss rate for WriteReq accesses 1678system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016855 # mshr miss rate for LoadLockedReq accesses 1679system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016855 # mshr miss rate for LoadLockedReq accesses 1680system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.053745 # mshr miss rate for StoreCondReq accesses 1681system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053745 # mshr miss rate for StoreCondReq accesses 1682system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for demand accesses 1683system.cpu0.dcache.demand_mshr_miss_rate::total 0.019517 # mshr miss rate for demand accesses 1684system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for overall accesses 1685system.cpu0.dcache.overall_mshr_miss_rate::total 0.019517 # mshr miss rate for overall accesses 1686system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10332.165295 # average ReadReq mshr miss latency 1687system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10332.165295 # average ReadReq mshr miss latency 1688system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14124.286908 # average WriteReq mshr miss latency 1689system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14124.286908 # average WriteReq mshr miss latency 1690system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14504.873062 # average LoadLockedReq mshr miss latency 1691system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.873062 # average LoadLockedReq mshr miss latency 1692system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19639.904924 # average StoreCondReq mshr miss latency 1693system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19639.904924 # average StoreCondReq mshr miss latency | 1639system.cpu0.dcache.writebacks::writebacks 518095 # number of writebacks 1640system.cpu0.dcache.writebacks::total 518095 # number of writebacks 1641system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42683 # number of ReadReq MSHR hits 1642system.cpu0.dcache.ReadReq_mshr_hits::total 42683 # number of ReadReq MSHR hits 1643system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230741 # number of WriteReq MSHR hits 1644system.cpu0.dcache.WriteReq_mshr_hits::total 230741 # number of WriteReq MSHR hits 1645system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits 1646system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits 1647system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273424 # number of demand (read+write) MSHR hits 1648system.cpu0.dcache.demand_mshr_hits::total 273424 # number of demand (read+write) MSHR hits 1649system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273424 # number of overall MSHR hits 1650system.cpu0.dcache.overall_mshr_hits::total 273424 # number of overall MSHR hits 1651system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494788 # number of ReadReq MSHR misses 1652system.cpu0.dcache.ReadReq_mshr_misses::total 494788 # number of ReadReq MSHR misses 1653system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302109 # number of WriteReq MSHR misses 1654system.cpu0.dcache.WriteReq_mshr_misses::total 302109 # number of WriteReq MSHR misses 1655system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6421 # number of LoadLockedReq MSHR misses 1656system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6421 # number of LoadLockedReq MSHR misses 1657system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20250 # number of StoreCondReq MSHR misses 1658system.cpu0.dcache.StoreCondReq_mshr_misses::total 20250 # number of StoreCondReq MSHR misses 1659system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796897 # number of demand (read+write) MSHR misses 1660system.cpu0.dcache.demand_mshr_misses::total 796897 # number of demand (read+write) MSHR misses 1661system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796897 # number of overall MSHR misses 1662system.cpu0.dcache.overall_mshr_misses::total 796897 # number of overall MSHR misses 1663system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5118044180 # number of ReadReq MSHR miss cycles 1664system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5118044180 # number of ReadReq MSHR miss cycles 1665system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4273159157 # number of WriteReq MSHR miss cycles 1666system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4273159157 # number of WriteReq MSHR miss cycles 1667system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 93352250 # number of LoadLockedReq MSHR miss cycles 1668system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93352250 # number of LoadLockedReq MSHR miss cycles 1669system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 397142457 # number of StoreCondReq MSHR miss cycles 1670system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397142457 # number of StoreCondReq MSHR miss cycles 1671system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles 1672system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles 1673system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9391203337 # number of demand (read+write) MSHR miss cycles 1674system.cpu0.dcache.demand_mshr_miss_latency::total 9391203337 # number of demand (read+write) MSHR miss cycles 1675system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9391203337 # number of overall MSHR miss cycles 1676system.cpu0.dcache.overall_mshr_miss_latency::total 9391203337 # number of overall MSHR miss cycles 1677system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191390497 # number of ReadReq MSHR uncacheable cycles 1678system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191390497 # number of ReadReq MSHR uncacheable cycles 1679system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803718496 # number of WriteReq MSHR uncacheable cycles 1680system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803718496 # number of WriteReq MSHR uncacheable cycles 1681system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995108993 # number of overall MSHR uncacheable cycles 1682system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995108993 # number of overall MSHR uncacheable cycles 1683system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021198 # mshr miss rate for ReadReq accesses 1684system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021198 # mshr miss rate for ReadReq accesses 1685system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017367 # mshr miss rate for WriteReq accesses 1686system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017367 # mshr miss rate for WriteReq accesses 1687system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016550 # mshr miss rate for LoadLockedReq accesses 1688system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016550 # mshr miss rate for LoadLockedReq accesses 1689system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052895 # mshr miss rate for StoreCondReq accesses 1690system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052895 # mshr miss rate for StoreCondReq accesses 1691system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for demand accesses 1692system.cpu0.dcache.demand_mshr_miss_rate::total 0.019562 # mshr miss rate for demand accesses 1693system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for overall accesses 1694system.cpu0.dcache.overall_mshr_miss_rate::total 0.019562 # mshr miss rate for overall accesses 1695system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10343.913312 # average ReadReq mshr miss latency 1696system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10343.913312 # average ReadReq mshr miss latency 1697system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14144.428524 # average WriteReq mshr miss latency 1698system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14144.428524 # average WriteReq mshr miss latency 1699system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14538.584333 # average LoadLockedReq mshr miss latency 1700system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14538.584333 # average LoadLockedReq mshr miss latency 1701system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19611.973185 # average StoreCondReq mshr miss latency 1702system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19611.973185 # average StoreCondReq mshr miss latency |
| 1694system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 1695system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1703system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 1704system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1696system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency 1697system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency 1698system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency 1699system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency | 1705system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency 1706system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency 1707system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency 1708system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency |
| 1700system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1701system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1702system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1703system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1704system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1705system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1706system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1709system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1710system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1711system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1712system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1713system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1714system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1715system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1707system.cpu1.branchPred.lookups 4191050 # Number of BP lookups 1708system.cpu1.branchPred.condPredicted 2447557 # Number of conditional branches predicted 1709system.cpu1.branchPred.condIncorrect 261619 # Number of conditional branches incorrect 1710system.cpu1.branchPred.BTBLookups 2683528 # Number of BTB lookups 1711system.cpu1.branchPred.BTBHits 1692147 # Number of BTB hits | 1716system.cpu1.branchPred.lookups 4041852 # Number of BP lookups 1717system.cpu1.branchPred.condPredicted 2340524 # Number of conditional branches predicted 1718system.cpu1.branchPred.condIncorrect 248983 # Number of conditional branches incorrect 1719system.cpu1.branchPred.BTBLookups 2647417 # Number of BTB lookups 1720system.cpu1.branchPred.BTBHits 1629039 # Number of BTB hits |
| 1712system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1721system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1713system.cpu1.branchPred.BTBHitPct 63.056804 # BTB Hit Percentage 1714system.cpu1.branchPred.usedRAS 827495 # Number of times the RAS was used to get a target. 1715system.cpu1.branchPred.RASInCorrect 59633 # Number of incorrect RAS predictions. | 1722system.cpu1.branchPred.BTBHitPct 61.533147 # BTB Hit Percentage 1723system.cpu1.branchPred.usedRAS 795039 # Number of times the RAS was used to get a target. 1724system.cpu1.branchPred.RASInCorrect 55831 # Number of incorrect RAS predictions. |
| 1716system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1717system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1718system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1719system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1720system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1721system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1722system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1723system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1731system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1732system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1733system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1734system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1735system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1736system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1737system.cpu1.dtb.inst_hits 0 # ITB inst hits 1738system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1725system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1726system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1727system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1728system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1729system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1730system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1731system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1732system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1740system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1741system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1742system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1743system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1744system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1745system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1746system.cpu1.dtb.inst_hits 0 # ITB inst hits 1747system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1739system.cpu1.dtb.read_hits 4177995 # DTB read hits 1740system.cpu1.dtb.read_misses 21525 # DTB read misses 1741system.cpu1.dtb.write_hits 3468676 # DTB write hits 1742system.cpu1.dtb.write_misses 1889 # DTB write misses | 1748system.cpu1.dtb.read_hits 4061119 # DTB read hits 1749system.cpu1.dtb.read_misses 20366 # DTB read misses 1750system.cpu1.dtb.write_hits 3327004 # DTB write hits 1751system.cpu1.dtb.write_misses 1507 # DTB write misses |
| 1743system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1744system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1745system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1746system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1752system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1753system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1754system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1755system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1747system.cpu1.dtb.flush_entries 2064 # Number of entries that have been flushed from TLB 1748system.cpu1.dtb.align_faults 236 # Number of TLB faults due to alignment restrictions 1749system.cpu1.dtb.prefetch_faults 360 # Number of TLB faults due to prefetch | 1756system.cpu1.dtb.flush_entries 2038 # Number of entries that have been flushed from TLB 1757system.cpu1.dtb.align_faults 134 # Number of TLB faults due to alignment restrictions 1758system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch |
| 1750system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1759system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1751system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions 1752system.cpu1.dtb.read_accesses 4199520 # DTB read accesses 1753system.cpu1.dtb.write_accesses 3470565 # DTB write accesses | 1760system.cpu1.dtb.perms_faults 275 # Number of TLB faults due to permissions restrictions 1761system.cpu1.dtb.read_accesses 4081485 # DTB read accesses 1762system.cpu1.dtb.write_accesses 3328511 # DTB write accesses |
| 1754system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1763system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1755system.cpu1.dtb.hits 7646671 # DTB hits 1756system.cpu1.dtb.misses 23414 # DTB misses 1757system.cpu1.dtb.accesses 7670085 # DTB accesses | 1764system.cpu1.dtb.hits 7388123 # DTB hits 1765system.cpu1.dtb.misses 21873 # DTB misses 1766system.cpu1.dtb.accesses 7409996 # DTB accesses |
| 1758system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1759system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1760system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1761system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1762system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1763system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1764system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1765system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1771system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1772system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1773system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1774system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1775system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1776system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1777system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1778system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1767system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1768system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1769system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1770system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1771system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1772system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1773system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1774system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1780system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1781system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1782system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1783system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1784system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1785system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1786system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1787system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1779system.cpu1.itb.inst_hits 7954981 # ITB inst hits 1780system.cpu1.itb.inst_misses 2237 # ITB inst misses | 1788system.cpu1.itb.inst_hits 7667797 # ITB inst hits 1789system.cpu1.itb.inst_misses 2228 # ITB inst misses |
| 1781system.cpu1.itb.read_hits 0 # DTB read hits 1782system.cpu1.itb.read_misses 0 # DTB read misses 1783system.cpu1.itb.write_hits 0 # DTB write hits 1784system.cpu1.itb.write_misses 0 # DTB write misses 1785system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1786system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1787system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1788system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1789system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB 1790system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1791system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1792system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1790system.cpu1.itb.read_hits 0 # DTB read hits 1791system.cpu1.itb.read_misses 0 # DTB read misses 1792system.cpu1.itb.write_hits 0 # DTB write hits 1793system.cpu1.itb.write_misses 0 # DTB write misses 1794system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1795system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1796system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1797system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1798system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB 1799system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1800system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1801system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1793system.cpu1.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions | 1802system.cpu1.itb.perms_faults 1890 # Number of TLB faults due to permissions restrictions |
| 1794system.cpu1.itb.read_accesses 0 # DTB read accesses 1795system.cpu1.itb.write_accesses 0 # DTB write accesses | 1803system.cpu1.itb.read_accesses 0 # DTB read accesses 1804system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1796system.cpu1.itb.inst_accesses 7957218 # ITB inst accesses 1797system.cpu1.itb.hits 7954981 # DTB hits 1798system.cpu1.itb.misses 2237 # DTB misses 1799system.cpu1.itb.accesses 7957218 # DTB accesses 1800system.cpu1.numCycles 42108230 # number of cpu cycles simulated | 1805system.cpu1.itb.inst_accesses 7670025 # ITB inst accesses 1806system.cpu1.itb.hits 7667797 # DTB hits 1807system.cpu1.itb.misses 2228 # DTB misses 1808system.cpu1.itb.accesses 7670025 # DTB accesses 1809system.cpu1.numCycles 40526065 # number of cpu cycles simulated |
| 1801system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1802system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1810system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1811system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1803system.cpu1.committedInsts 16399164 # Number of instructions committed 1804system.cpu1.committedOps 20088934 # Number of ops (including micro ops) committed 1805system.cpu1.discardedOps 1607897 # Number of ops (including micro ops) which were discarded before commit 1806system.cpu1.numFetchSuspends 2744 # Number of times Execute suspended instruction fetching 1807system.cpu1.quiesceCycles 5644728223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1808system.cpu1.cpi 2.567706 # CPI: cycles per instruction 1809system.cpu1.ipc 0.389453 # IPC: instructions per cycle | 1812system.cpu1.committedInsts 15860183 # Number of instructions committed 1813system.cpu1.committedOps 19387635 # Number of ops (including micro ops) committed 1814system.cpu1.discardedOps 1556469 # Number of ops (including micro ops) which were discarded before commit 1815system.cpu1.numFetchSuspends 2802 # Number of times Execute suspended instruction fetching 1816system.cpu1.quiesceCycles 5646205885 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1817system.cpu1.cpi 2.555208 # CPI: cycles per instruction 1818system.cpu1.ipc 0.391358 # IPC: instructions per cycle |
| 1810system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1819system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1811system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed 1812system.cpu1.tickCycles 30601119 # Number of cycles that the object actually ticked 1813system.cpu1.idleCycles 11507111 # Total number of cycles that the object has spent stopped 1814system.cpu1.icache.tags.replacements 921368 # number of replacements 1815system.cpu1.icache.tags.tagsinuse 499.459165 # Cycle average of tags in use 1816system.cpu1.icache.tags.total_refs 7030999 # Total number of references to valid blocks. 1817system.cpu1.icache.tags.sampled_refs 921880 # Sample count of references to valid blocks. 1818system.cpu1.icache.tags.avg_refs 7.626805 # Average number of references to valid blocks. 1819system.cpu1.icache.tags.warmup_cycle 71222254500 # Cycle when the warmup percentage was hit. 1820system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459165 # Average occupied blocks per requestor | 1820system.cpu1.kern.inst.quiesce 2803 # number of quiesce instructions executed 1821system.cpu1.tickCycles 29467033 # Number of cycles that the object actually ticked 1822system.cpu1.idleCycles 11059032 # Total number of cycles that the object has spent stopped 1823system.cpu1.icache.tags.replacements 893075 # number of replacements 1824system.cpu1.icache.tags.tagsinuse 499.459055 # Cycle average of tags in use 1825system.cpu1.icache.tags.total_refs 6772156 # Total number of references to valid blocks. 1826system.cpu1.icache.tags.sampled_refs 893587 # Sample count of references to valid blocks. 1827system.cpu1.icache.tags.avg_refs 7.578620 # Average number of references to valid blocks. 1828system.cpu1.icache.tags.warmup_cycle 71221486500 # Cycle when the warmup percentage was hit. 1829system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459055 # Average occupied blocks per requestor |
| 1821system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy 1822system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy 1823system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1830system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy 1831system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy 1832system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1824system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id 1825system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id | 1833system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id 1834system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id |
| 1826system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1835system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1827system.cpu1.icache.tags.tag_accesses 16827638 # Number of tag accesses 1828system.cpu1.icache.tags.data_accesses 16827638 # Number of data accesses 1829system.cpu1.icache.ReadReq_hits::cpu1.inst 7030999 # number of ReadReq hits 1830system.cpu1.icache.ReadReq_hits::total 7030999 # number of ReadReq hits 1831system.cpu1.icache.demand_hits::cpu1.inst 7030999 # number of demand (read+write) hits 1832system.cpu1.icache.demand_hits::total 7030999 # number of demand (read+write) hits 1833system.cpu1.icache.overall_hits::cpu1.inst 7030999 # number of overall hits 1834system.cpu1.icache.overall_hits::total 7030999 # number of overall hits 1835system.cpu1.icache.ReadReq_misses::cpu1.inst 921880 # number of ReadReq misses 1836system.cpu1.icache.ReadReq_misses::total 921880 # number of ReadReq misses 1837system.cpu1.icache.demand_misses::cpu1.inst 921880 # number of demand (read+write) misses 1838system.cpu1.icache.demand_misses::total 921880 # number of demand (read+write) misses 1839system.cpu1.icache.overall_misses::cpu1.inst 921880 # number of overall misses 1840system.cpu1.icache.overall_misses::total 921880 # number of overall misses 1841system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7511609427 # number of ReadReq miss cycles 1842system.cpu1.icache.ReadReq_miss_latency::total 7511609427 # number of ReadReq miss cycles 1843system.cpu1.icache.demand_miss_latency::cpu1.inst 7511609427 # number of demand (read+write) miss cycles 1844system.cpu1.icache.demand_miss_latency::total 7511609427 # number of demand (read+write) miss cycles 1845system.cpu1.icache.overall_miss_latency::cpu1.inst 7511609427 # number of overall miss cycles 1846system.cpu1.icache.overall_miss_latency::total 7511609427 # number of overall miss cycles 1847system.cpu1.icache.ReadReq_accesses::cpu1.inst 7952879 # number of ReadReq accesses(hits+misses) 1848system.cpu1.icache.ReadReq_accesses::total 7952879 # number of ReadReq accesses(hits+misses) 1849system.cpu1.icache.demand_accesses::cpu1.inst 7952879 # number of demand (read+write) accesses 1850system.cpu1.icache.demand_accesses::total 7952879 # number of demand (read+write) accesses 1851system.cpu1.icache.overall_accesses::cpu1.inst 7952879 # number of overall (read+write) accesses 1852system.cpu1.icache.overall_accesses::total 7952879 # number of overall (read+write) accesses 1853system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115918 # miss rate for ReadReq accesses 1854system.cpu1.icache.ReadReq_miss_rate::total 0.115918 # miss rate for ReadReq accesses 1855system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115918 # miss rate for demand accesses 1856system.cpu1.icache.demand_miss_rate::total 0.115918 # miss rate for demand accesses 1857system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115918 # miss rate for overall accesses 1858system.cpu1.icache.overall_miss_rate::total 0.115918 # miss rate for overall accesses 1859system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8148.142304 # average ReadReq miss latency 1860system.cpu1.icache.ReadReq_avg_miss_latency::total 8148.142304 # average ReadReq miss latency 1861system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency 1862system.cpu1.icache.demand_avg_miss_latency::total 8148.142304 # average overall miss latency 1863system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency 1864system.cpu1.icache.overall_avg_miss_latency::total 8148.142304 # average overall miss latency | 1836system.cpu1.icache.tags.tag_accesses 16225073 # Number of tag accesses 1837system.cpu1.icache.tags.data_accesses 16225073 # Number of data accesses 1838system.cpu1.icache.ReadReq_hits::cpu1.inst 6772156 # number of ReadReq hits 1839system.cpu1.icache.ReadReq_hits::total 6772156 # number of ReadReq hits 1840system.cpu1.icache.demand_hits::cpu1.inst 6772156 # number of demand (read+write) hits 1841system.cpu1.icache.demand_hits::total 6772156 # number of demand (read+write) hits 1842system.cpu1.icache.overall_hits::cpu1.inst 6772156 # number of overall hits 1843system.cpu1.icache.overall_hits::total 6772156 # number of overall hits 1844system.cpu1.icache.ReadReq_misses::cpu1.inst 893587 # number of ReadReq misses 1845system.cpu1.icache.ReadReq_misses::total 893587 # number of ReadReq misses 1846system.cpu1.icache.demand_misses::cpu1.inst 893587 # number of demand (read+write) misses 1847system.cpu1.icache.demand_misses::total 893587 # number of demand (read+write) misses 1848system.cpu1.icache.overall_misses::cpu1.inst 893587 # number of overall misses 1849system.cpu1.icache.overall_misses::total 893587 # number of overall misses 1850system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7266352748 # number of ReadReq miss cycles 1851system.cpu1.icache.ReadReq_miss_latency::total 7266352748 # number of ReadReq miss cycles 1852system.cpu1.icache.demand_miss_latency::cpu1.inst 7266352748 # number of demand (read+write) miss cycles 1853system.cpu1.icache.demand_miss_latency::total 7266352748 # number of demand (read+write) miss cycles 1854system.cpu1.icache.overall_miss_latency::cpu1.inst 7266352748 # number of overall miss cycles 1855system.cpu1.icache.overall_miss_latency::total 7266352748 # number of overall miss cycles 1856system.cpu1.icache.ReadReq_accesses::cpu1.inst 7665743 # number of ReadReq accesses(hits+misses) 1857system.cpu1.icache.ReadReq_accesses::total 7665743 # number of ReadReq accesses(hits+misses) 1858system.cpu1.icache.demand_accesses::cpu1.inst 7665743 # number of demand (read+write) accesses 1859system.cpu1.icache.demand_accesses::total 7665743 # number of demand (read+write) accesses 1860system.cpu1.icache.overall_accesses::cpu1.inst 7665743 # number of overall (read+write) accesses 1861system.cpu1.icache.overall_accesses::total 7665743 # number of overall (read+write) accesses 1862system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116569 # miss rate for ReadReq accesses 1863system.cpu1.icache.ReadReq_miss_rate::total 0.116569 # miss rate for ReadReq accesses 1864system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116569 # miss rate for demand accesses 1865system.cpu1.icache.demand_miss_rate::total 0.116569 # miss rate for demand accesses 1866system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116569 # miss rate for overall accesses 1867system.cpu1.icache.overall_miss_rate::total 0.116569 # miss rate for overall accesses 1868system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8131.667927 # average ReadReq miss latency 1869system.cpu1.icache.ReadReq_avg_miss_latency::total 8131.667927 # average ReadReq miss latency 1870system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency 1871system.cpu1.icache.demand_avg_miss_latency::total 8131.667927 # average overall miss latency 1872system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency 1873system.cpu1.icache.overall_avg_miss_latency::total 8131.667927 # average overall miss latency |
| 1865system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1866system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1867system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1868system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1869system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1870system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1871system.cpu1.icache.fast_writes 0 # number of fast writes performed 1872system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1874system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1875system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1876system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1877system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1878system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1879system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1880system.cpu1.icache.fast_writes 0 # number of fast writes performed 1881system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1873system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 921880 # number of ReadReq MSHR misses 1874system.cpu1.icache.ReadReq_mshr_misses::total 921880 # number of ReadReq MSHR misses 1875system.cpu1.icache.demand_mshr_misses::cpu1.inst 921880 # number of demand (read+write) MSHR misses 1876system.cpu1.icache.demand_mshr_misses::total 921880 # number of demand (read+write) MSHR misses 1877system.cpu1.icache.overall_mshr_misses::cpu1.inst 921880 # number of overall MSHR misses 1878system.cpu1.icache.overall_mshr_misses::total 921880 # number of overall MSHR misses 1879system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6126335573 # number of ReadReq MSHR miss cycles 1880system.cpu1.icache.ReadReq_mshr_miss_latency::total 6126335573 # number of ReadReq MSHR miss cycles 1881system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6126335573 # number of demand (read+write) MSHR miss cycles 1882system.cpu1.icache.demand_mshr_miss_latency::total 6126335573 # number of demand (read+write) MSHR miss cycles 1883system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6126335573 # number of overall MSHR miss cycles 1884system.cpu1.icache.overall_mshr_miss_latency::total 6126335573 # number of overall MSHR miss cycles 1885system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10451250 # number of ReadReq MSHR uncacheable cycles 1886system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10451250 # number of ReadReq MSHR uncacheable cycles 1887system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10451250 # number of overall MSHR uncacheable cycles 1888system.cpu1.icache.overall_mshr_uncacheable_latency::total 10451250 # number of overall MSHR uncacheable cycles 1889system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for ReadReq accesses 1890system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.115918 # mshr miss rate for ReadReq accesses 1891system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for demand accesses 1892system.cpu1.icache.demand_mshr_miss_rate::total 0.115918 # mshr miss rate for demand accesses 1893system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for overall accesses 1894system.cpu1.icache.overall_mshr_miss_rate::total 0.115918 # mshr miss rate for overall accesses 1895system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average ReadReq mshr miss latency 1896system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6645.480510 # average ReadReq mshr miss latency 1897system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency 1898system.cpu1.icache.demand_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency 1899system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency 1900system.cpu1.icache.overall_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency | 1882system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893587 # number of ReadReq MSHR misses 1883system.cpu1.icache.ReadReq_mshr_misses::total 893587 # number of ReadReq MSHR misses 1884system.cpu1.icache.demand_mshr_misses::cpu1.inst 893587 # number of demand (read+write) MSHR misses 1885system.cpu1.icache.demand_mshr_misses::total 893587 # number of demand (read+write) MSHR misses 1886system.cpu1.icache.overall_mshr_misses::cpu1.inst 893587 # number of overall MSHR misses 1887system.cpu1.icache.overall_mshr_misses::total 893587 # number of overall MSHR misses 1888system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923590752 # number of ReadReq MSHR miss cycles 1889system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923590752 # number of ReadReq MSHR miss cycles 1890system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923590752 # number of demand (read+write) MSHR miss cycles 1891system.cpu1.icache.demand_mshr_miss_latency::total 5923590752 # number of demand (read+write) MSHR miss cycles 1892system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923590752 # number of overall MSHR miss cycles 1893system.cpu1.icache.overall_mshr_miss_latency::total 5923590752 # number of overall MSHR miss cycles 1894system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10589750 # number of ReadReq MSHR uncacheable cycles 1895system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10589750 # number of ReadReq MSHR uncacheable cycles 1896system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10589750 # number of overall MSHR uncacheable cycles 1897system.cpu1.icache.overall_mshr_uncacheable_latency::total 10589750 # number of overall MSHR uncacheable cycles 1898system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for ReadReq accesses 1899system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116569 # mshr miss rate for ReadReq accesses 1900system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for demand accesses 1901system.cpu1.icache.demand_mshr_miss_rate::total 0.116569 # mshr miss rate for demand accesses 1902system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for overall accesses 1903system.cpu1.icache.overall_mshr_miss_rate::total 0.116569 # mshr miss rate for overall accesses 1904system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average ReadReq mshr miss latency 1905system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.002830 # average ReadReq mshr miss latency 1906system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency 1907system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency 1908system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency 1909system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency |
| 1901system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1902system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1903system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1904system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1905system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1910system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1911system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1912system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1913system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1914system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1906system.cpu1.toL2Bus.trans_dist::ReadReq 1617912 # Transaction distribution 1907system.cpu1.toL2Bus.trans_dist::ReadResp 1172300 # Transaction distribution 1908system.cpu1.toL2Bus.trans_dist::WriteReq 2534 # Transaction distribution 1909system.cpu1.toL2Bus.trans_dist::WriteResp 2534 # Transaction distribution 1910system.cpu1.toL2Bus.trans_dist::Writeback 119069 # Transaction distribution 1911system.cpu1.toL2Bus.trans_dist::HardPFReq 160310 # Transaction distribution 1912system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 1913system.cpu1.toL2Bus.trans_dist::UpgradeReq 84990 # Transaction distribution 1914system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41555 # Transaction distribution 1915system.cpu1.toL2Bus.trans_dist::UpgradeResp 86189 # Transaction distribution 1916system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 1917system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution 1918system.cpu1.toL2Bus.trans_dist::ReadExReq 79780 # Transaction distribution 1919system.cpu1.toL2Bus.trans_dist::ReadExResp 67226 # Transaction distribution 1920system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1843990 # Packet count per connected master and slave (bytes) 1921system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 788213 # Packet count per connected master and slave (bytes) 1922system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6991 # Packet count per connected master and slave (bytes) 1923system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 54848 # Packet count per connected master and slave (bytes) 1924system.cpu1.toL2Bus.pkt_count::total 2694042 # Packet count per connected master and slave (bytes) 1925system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59007680 # Cumulative packet size per connected master and slave (bytes) 1926system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25579748 # Cumulative packet size per connected master and slave (bytes) 1927system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10764 # Cumulative packet size per connected master and slave (bytes) 1928system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 100400 # Cumulative packet size per connected master and slave (bytes) 1929system.cpu1.toL2Bus.pkt_size::total 84698592 # Cumulative packet size per connected master and slave (bytes) 1930system.cpu1.toL2Bus.snoops 851885 # Total snoops (count) 1931system.cpu1.toL2Bus.snoop_fanout::samples 2136582 # Request fanout histogram 1932system.cpu1.toL2Bus.snoop_fanout::mean 5.360548 # Request fanout histogram 1933system.cpu1.toL2Bus.snoop_fanout::stdev 0.480160 # Request fanout histogram | 1915system.cpu1.toL2Bus.trans_dist::ReadReq 1582924 # Transaction distribution 1916system.cpu1.toL2Bus.trans_dist::ReadResp 1137885 # Transaction distribution 1917system.cpu1.toL2Bus.trans_dist::WriteReq 2119 # Transaction distribution 1918system.cpu1.toL2Bus.trans_dist::WriteResp 2119 # Transaction distribution 1919system.cpu1.toL2Bus.trans_dist::Writeback 115746 # Transaction distribution 1920system.cpu1.toL2Bus.trans_dist::HardPFReq 150971 # Transaction distribution 1921system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 1922system.cpu1.toL2Bus.trans_dist::UpgradeReq 84405 # Transaction distribution 1923system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41125 # Transaction distribution 1924system.cpu1.toL2Bus.trans_dist::UpgradeResp 85149 # Transaction distribution 1925system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 1926system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution 1927system.cpu1.toL2Bus.trans_dist::ReadExReq 76810 # Transaction distribution 1928system.cpu1.toL2Bus.trans_dist::ReadExResp 64398 # Transaction distribution 1929system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787404 # Packet count per connected master and slave (bytes) 1930system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 768912 # Packet count per connected master and slave (bytes) 1931system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6948 # Packet count per connected master and slave (bytes) 1932system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51790 # Packet count per connected master and slave (bytes) 1933system.cpu1.toL2Bus.pkt_count::total 2615054 # Packet count per connected master and slave (bytes) 1934system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57196928 # Cumulative packet size per connected master and slave (bytes) 1935system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24920351 # Cumulative packet size per connected master and slave (bytes) 1936system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10668 # Cumulative packet size per connected master and slave (bytes) 1937system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 94516 # Cumulative packet size per connected master and slave (bytes) 1938system.cpu1.toL2Bus.pkt_size::total 82222463 # Cumulative packet size per connected master and slave (bytes) 1939system.cpu1.toL2Bus.snoops 838516 # Total snoops (count) 1940system.cpu1.toL2Bus.snoop_fanout::samples 2085340 # Request fanout histogram 1941system.cpu1.toL2Bus.snoop_fanout::mean 5.363825 # Request fanout histogram 1942system.cpu1.toL2Bus.snoop_fanout::stdev 0.481099 # Request fanout histogram |
| 1934system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1935system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1936system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1937system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1938system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1939system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1943system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1944system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1945system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1946system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1947system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1948system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1940system.cpu1.toL2Bus.snoop_fanout::5 1366242 63.95% 63.95% # Request fanout histogram 1941system.cpu1.toL2Bus.snoop_fanout::6 770340 36.05% 100.00% # Request fanout histogram | 1949system.cpu1.toL2Bus.snoop_fanout::5 1326642 63.62% 63.62% # Request fanout histogram 1950system.cpu1.toL2Bus.snoop_fanout::6 758698 36.38% 100.00% # Request fanout histogram |
| 1942system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1943system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1944system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1951system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1952system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1953system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1945system.cpu1.toL2Bus.snoop_fanout::total 2136582 # Request fanout histogram 1946system.cpu1.toL2Bus.reqLayer0.occupancy 806533923 # Layer occupancy (ticks) | 1954system.cpu1.toL2Bus.snoop_fanout::total 2085340 # Request fanout histogram 1955system.cpu1.toL2Bus.reqLayer0.occupancy 782793185 # Layer occupancy (ticks) |
| 1947system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1956system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1948system.cpu1.toL2Bus.snoopLayer0.occupancy 80269000 # Layer occupancy (ticks) | 1957system.cpu1.toL2Bus.snoopLayer0.occupancy 78444000 # Layer occupancy (ticks) |
| 1949system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1958system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1950system.cpu1.toL2Bus.respLayer0.occupancy 1384243177 # Layer occupancy (ticks) | 1959system.cpu1.toL2Bus.respLayer0.occupancy 1341767498 # Layer occupancy (ticks) |
| 1951system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1960system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1952system.cpu1.toL2Bus.respLayer1.occupancy 391135835 # Layer occupancy (ticks) | 1961system.cpu1.toL2Bus.respLayer1.occupancy 381370915 # Layer occupancy (ticks) |
| 1953system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1962system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1954system.cpu1.toL2Bus.respLayer2.occupancy 4300499 # Layer occupancy (ticks) | 1963system.cpu1.toL2Bus.respLayer2.occupancy 4282497 # Layer occupancy (ticks) |
| 1955system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1964system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1956system.cpu1.toL2Bus.respLayer3.occupancy 29750249 # Layer occupancy (ticks) | 1965system.cpu1.toL2Bus.respLayer3.occupancy 28163996 # Layer occupancy (ticks) |
| 1957system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1966system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1958system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7297386 # number of hwpf identified 1959system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43768 # number of hwpf that were already in mshr 1960system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7137149 # number of hwpf that were already in the cache 1961system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1402 # number of hwpf that were already in the prefetch queue | 1967system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7065047 # number of hwpf identified 1968system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40428 # number of hwpf that were already in mshr 1969system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914930 # number of hwpf that were already in the cache 1970system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1457 # number of hwpf that were already in the prefetch queue |
| 1962system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1971system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1963system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2677 # number of hwpf removed because MSHR allocated 1964system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 112390 # number of hwpf issued 1965system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 731398 # number of hwpf spanning a virtual page | 1972system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2607 # number of hwpf removed because MSHR allocated 1973system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105625 # number of hwpf issued 1974system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724673 # number of hwpf spanning a virtual page |
| 1966system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1975system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1967system.cpu1.l2cache.tags.replacements 85101 # number of replacements 1968system.cpu1.l2cache.tags.tagsinuse 15525.587179 # Cycle average of tags in use 1969system.cpu1.l2cache.tags.total_refs 1172424 # Total number of references to valid blocks. 1970system.cpu1.l2cache.tags.sampled_refs 100275 # Sample count of references to valid blocks. 1971system.cpu1.l2cache.tags.avg_refs 11.692087 # Average number of references to valid blocks. | 1976system.cpu1.l2cache.tags.replacements 79629 # number of replacements 1977system.cpu1.l2cache.tags.tagsinuse 15528.716598 # Cycle average of tags in use 1978system.cpu1.l2cache.tags.total_refs 1138081 # Total number of references to valid blocks. 1979system.cpu1.l2cache.tags.sampled_refs 94994 # Sample count of references to valid blocks. 1980system.cpu1.l2cache.tags.avg_refs 11.980557 # Average number of references to valid blocks. |
| 1972system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1981system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1973system.cpu1.l2cache.tags.occ_blocks::writebacks 5967.757550 # Average occupied blocks per requestor 1974system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.503310 # Average occupied blocks per requestor 1975system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.105046 # Average occupied blocks per requestor 1976system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2342.307731 # Average occupied blocks per requestor 1977system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7188.913541 # Average occupied blocks per requestor 1978system.cpu1.l2cache.tags.occ_percent::writebacks 0.364243 # Average percentage of cache occupancy 1979system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001618 # Average percentage of cache occupancy 1980system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy 1981system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142963 # Average percentage of cache occupancy 1982system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.438776 # Average percentage of cache occupancy 1983system.cpu1.l2cache.tags.occ_percent::total 0.947607 # Average percentage of cache occupancy 1984system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10134 # Occupied blocks per task id 1985system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id 1986system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5006 # Occupied blocks per task id 1987system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 136 # Occupied blocks per task id 1988system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6712 # Occupied blocks per task id 1989system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3286 # Occupied blocks per task id 1990system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 1991system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 1992system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id | 1982system.cpu1.l2cache.tags.occ_blocks::writebacks 6912.222509 # Average occupied blocks per requestor 1983system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 24.793124 # Average occupied blocks per requestor 1984system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.117245 # Average occupied blocks per requestor 1985system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2315.760796 # Average occupied blocks per requestor 1986system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6275.822923 # Average occupied blocks per requestor 1987system.cpu1.l2cache.tags.occ_percent::writebacks 0.421889 # Average percentage of cache occupancy 1988system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001513 # Average percentage of cache occupancy 1989system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy 1990system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.141343 # Average percentage of cache occupancy 1991system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383046 # Average percentage of cache occupancy 1992system.cpu1.l2cache.tags.occ_percent::total 0.947798 # Average percentage of cache occupancy 1993system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10144 # Occupied blocks per task id 1994system.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id 1995system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5192 # Occupied blocks per task id 1996system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id 1997system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6818 # Occupied blocks per task id 1998system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3193 # Occupied blocks per task id 1999system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id 2000system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 2001system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id |
| 1993system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id | 2002system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id |
| 1994system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2980 # Occupied blocks per task id 1995system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1783 # Occupied blocks per task id 1996system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.618530 # Percentage of cache occupancy per task id 1997system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id 1998system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.305542 # Percentage of cache occupancy per task id 1999system.cpu1.l2cache.tags.tag_accesses 22015192 # Number of tag accesses 2000system.cpu1.l2cache.tags.data_accesses 22015192 # Number of data accesses 2001system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24492 # number of ReadReq hits 2002system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2447 # number of ReadReq hits 2003system.cpu1.l2cache.ReadReq_hits::cpu1.inst 1023306 # number of ReadReq hits 2004system.cpu1.l2cache.ReadReq_hits::total 1050245 # number of ReadReq hits 2005system.cpu1.l2cache.Writeback_hits::writebacks 119069 # number of Writeback hits 2006system.cpu1.l2cache.Writeback_hits::total 119069 # number of Writeback hits 2007system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1895 # number of UpgradeReq hits 2008system.cpu1.l2cache.UpgradeReq_hits::total 1895 # number of UpgradeReq hits 2009system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 736 # number of SCUpgradeReq hits 2010system.cpu1.l2cache.SCUpgradeReq_hits::total 736 # number of SCUpgradeReq hits 2011system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 30109 # number of ReadExReq hits 2012system.cpu1.l2cache.ReadExReq_hits::total 30109 # number of ReadExReq hits 2013system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24492 # number of demand (read+write) hits 2014system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2447 # number of demand (read+write) hits 2015system.cpu1.l2cache.demand_hits::cpu1.inst 1053415 # number of demand (read+write) hits 2016system.cpu1.l2cache.demand_hits::total 1080354 # number of demand (read+write) hits 2017system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24492 # number of overall hits 2018system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2447 # number of overall hits 2019system.cpu1.l2cache.overall_hits::cpu1.inst 1053415 # number of overall hits 2020system.cpu1.l2cache.overall_hits::total 1080354 # number of overall hits 2021system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 608 # number of ReadReq misses 2022system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 244 # number of ReadReq misses 2023system.cpu1.l2cache.ReadReq_misses::cpu1.inst 73509 # number of ReadReq misses 2024system.cpu1.l2cache.ReadReq_misses::total 74361 # number of ReadReq misses 2025system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28314 # number of UpgradeReq misses 2026system.cpu1.l2cache.UpgradeReq_misses::total 28314 # number of UpgradeReq misses 2027system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22589 # number of SCUpgradeReq misses 2028system.cpu1.l2cache.SCUpgradeReq_misses::total 22589 # number of SCUpgradeReq misses 2029system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32639 # number of ReadExReq misses 2030system.cpu1.l2cache.ReadExReq_misses::total 32639 # number of ReadExReq misses 2031system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 608 # number of demand (read+write) misses 2032system.cpu1.l2cache.demand_misses::cpu1.itb.walker 244 # number of demand (read+write) misses 2033system.cpu1.l2cache.demand_misses::cpu1.inst 106148 # number of demand (read+write) misses 2034system.cpu1.l2cache.demand_misses::total 107000 # number of demand (read+write) misses 2035system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 608 # number of overall misses 2036system.cpu1.l2cache.overall_misses::cpu1.itb.walker 244 # number of overall misses 2037system.cpu1.l2cache.overall_misses::cpu1.inst 106148 # number of overall misses 2038system.cpu1.l2cache.overall_misses::total 107000 # number of overall misses 2039system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13309748 # number of ReadReq miss cycles 2040system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4879000 # number of ReadReq miss cycles 2041system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1671503870 # number of ReadReq miss cycles 2042system.cpu1.l2cache.ReadReq_miss_latency::total 1689692618 # number of ReadReq miss cycles 2043system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 534018919 # number of UpgradeReq miss cycles 2044system.cpu1.l2cache.UpgradeReq_miss_latency::total 534018919 # number of UpgradeReq miss cycles 2045system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 443647551 # number of SCUpgradeReq miss cycles 2046system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443647551 # number of SCUpgradeReq miss cycles 2047system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 303500 # number of SCUpgradeFailReq miss cycles 2048system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 303500 # number of SCUpgradeFailReq miss cycles 2049system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1129954380 # number of ReadExReq miss cycles 2050system.cpu1.l2cache.ReadExReq_miss_latency::total 1129954380 # number of ReadExReq miss cycles 2051system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13309748 # number of demand (read+write) miss cycles 2052system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4879000 # number of demand (read+write) miss cycles 2053system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2801458250 # number of demand (read+write) miss cycles 2054system.cpu1.l2cache.demand_miss_latency::total 2819646998 # number of demand (read+write) miss cycles 2055system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13309748 # number of overall miss cycles 2056system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4879000 # number of overall miss cycles 2057system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2801458250 # number of overall miss cycles 2058system.cpu1.l2cache.overall_miss_latency::total 2819646998 # number of overall miss cycles 2059system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 25100 # number of ReadReq accesses(hits+misses) 2060system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2691 # number of ReadReq accesses(hits+misses) 2061system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1096815 # number of ReadReq accesses(hits+misses) 2062system.cpu1.l2cache.ReadReq_accesses::total 1124606 # number of ReadReq accesses(hits+misses) 2063system.cpu1.l2cache.Writeback_accesses::writebacks 119069 # number of Writeback accesses(hits+misses) 2064system.cpu1.l2cache.Writeback_accesses::total 119069 # number of Writeback accesses(hits+misses) 2065system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 30209 # number of UpgradeReq accesses(hits+misses) 2066system.cpu1.l2cache.UpgradeReq_accesses::total 30209 # number of UpgradeReq accesses(hits+misses) 2067system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23325 # number of SCUpgradeReq accesses(hits+misses) 2068system.cpu1.l2cache.SCUpgradeReq_accesses::total 23325 # number of SCUpgradeReq accesses(hits+misses) 2069system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 62748 # number of ReadExReq accesses(hits+misses) 2070system.cpu1.l2cache.ReadExReq_accesses::total 62748 # number of ReadExReq accesses(hits+misses) 2071system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 25100 # number of demand (read+write) accesses 2072system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2691 # number of demand (read+write) accesses 2073system.cpu1.l2cache.demand_accesses::cpu1.inst 1159563 # number of demand (read+write) accesses 2074system.cpu1.l2cache.demand_accesses::total 1187354 # number of demand (read+write) accesses 2075system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 25100 # number of overall (read+write) accesses 2076system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2691 # number of overall (read+write) accesses 2077system.cpu1.l2cache.overall_accesses::cpu1.inst 1159563 # number of overall (read+write) accesses 2078system.cpu1.l2cache.overall_accesses::total 1187354 # number of overall (read+write) accesses 2079system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for ReadReq accesses 2080system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090673 # miss rate for ReadReq accesses 2081system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067020 # miss rate for ReadReq accesses 2082system.cpu1.l2cache.ReadReq_miss_rate::total 0.066122 # miss rate for ReadReq accesses 2083system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.937270 # miss rate for UpgradeReq accesses 2084system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937270 # miss rate for UpgradeReq accesses 2085system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968446 # miss rate for SCUpgradeReq accesses 2086system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968446 # miss rate for SCUpgradeReq accesses 2087system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.520160 # miss rate for ReadExReq accesses 2088system.cpu1.l2cache.ReadExReq_miss_rate::total 0.520160 # miss rate for ReadExReq accesses 2089system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for demand accesses 2090system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090673 # miss rate for demand accesses 2091system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091541 # miss rate for demand accesses 2092system.cpu1.l2cache.demand_miss_rate::total 0.090116 # miss rate for demand accesses 2093system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for overall accesses 2094system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090673 # miss rate for overall accesses 2095system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091541 # miss rate for overall accesses 2096system.cpu1.l2cache.overall_miss_rate::total 0.090116 # miss rate for overall accesses 2097system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average ReadReq miss latency 2098system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19995.901639 # average ReadReq miss latency 2099system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22738.764913 # average ReadReq miss latency 2100system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22722.833448 # average ReadReq miss latency 2101system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18860.596136 # average UpgradeReq miss latency 2102system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18860.596136 # average UpgradeReq miss latency 2103system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19639.981894 # average SCUpgradeReq miss latency 2104system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19639.981894 # average SCUpgradeReq miss latency | 2003system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3095 # Occupied blocks per task id 2004system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1854 # Occupied blocks per task id 2005system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.619141 # Percentage of cache occupancy per task id 2006system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001770 # Percentage of cache occupancy per task id 2007system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.316895 # Percentage of cache occupancy per task id 2008system.cpu1.l2cache.tags.tag_accesses 21374644 # Number of tag accesses 2009system.cpu1.l2cache.tags.data_accesses 21374644 # Number of data accesses 2010system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23037 # number of ReadReq hits 2011system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2415 # number of ReadReq hits 2012system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993214 # number of ReadReq hits 2013system.cpu1.l2cache.ReadReq_hits::total 1018666 # number of ReadReq hits 2014system.cpu1.l2cache.Writeback_hits::writebacks 115746 # number of Writeback hits 2015system.cpu1.l2cache.Writeback_hits::total 115746 # number of Writeback hits 2016system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1782 # number of UpgradeReq hits 2017system.cpu1.l2cache.UpgradeReq_hits::total 1782 # number of UpgradeReq hits 2018system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 772 # number of SCUpgradeReq hits 2019system.cpu1.l2cache.SCUpgradeReq_hits::total 772 # number of SCUpgradeReq hits 2020system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27747 # number of ReadExReq hits 2021system.cpu1.l2cache.ReadExReq_hits::total 27747 # number of ReadExReq hits 2022system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23037 # number of demand (read+write) hits 2023system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2415 # number of demand (read+write) hits 2024system.cpu1.l2cache.demand_hits::cpu1.inst 1020961 # number of demand (read+write) hits 2025system.cpu1.l2cache.demand_hits::total 1046413 # number of demand (read+write) hits 2026system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23037 # number of overall hits 2027system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2415 # number of overall hits 2028system.cpu1.l2cache.overall_hits::cpu1.inst 1020961 # number of overall hits 2029system.cpu1.l2cache.overall_hits::total 1046413 # number of overall hits 2030system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 592 # number of ReadReq misses 2031system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 252 # number of ReadReq misses 2032system.cpu1.l2cache.ReadReq_misses::cpu1.inst 72082 # number of ReadReq misses 2033system.cpu1.l2cache.ReadReq_misses::total 72926 # number of ReadReq misses 2034system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28135 # number of UpgradeReq misses 2035system.cpu1.l2cache.UpgradeReq_misses::total 28135 # number of UpgradeReq misses 2036system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22404 # number of SCUpgradeReq misses 2037system.cpu1.l2cache.SCUpgradeReq_misses::total 22404 # number of SCUpgradeReq misses 2038system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32295 # number of ReadExReq misses 2039system.cpu1.l2cache.ReadExReq_misses::total 32295 # number of ReadExReq misses 2040system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 592 # number of demand (read+write) misses 2041system.cpu1.l2cache.demand_misses::cpu1.itb.walker 252 # number of demand (read+write) misses 2042system.cpu1.l2cache.demand_misses::cpu1.inst 104377 # number of demand (read+write) misses 2043system.cpu1.l2cache.demand_misses::total 105221 # number of demand (read+write) misses 2044system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 592 # number of overall misses 2045system.cpu1.l2cache.overall_misses::cpu1.itb.walker 252 # number of overall misses 2046system.cpu1.l2cache.overall_misses::cpu1.inst 104377 # number of overall misses 2047system.cpu1.l2cache.overall_misses::total 105221 # number of overall misses 2048system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13156500 # number of ReadReq miss cycles 2049system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5072997 # number of ReadReq miss cycles 2050system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1619935379 # number of ReadReq miss cycles 2051system.cpu1.l2cache.ReadReq_miss_latency::total 1638164876 # number of ReadReq miss cycles 2052system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 531136882 # number of UpgradeReq miss cycles 2053system.cpu1.l2cache.UpgradeReq_miss_latency::total 531136882 # number of UpgradeReq miss cycles 2054system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440134565 # number of SCUpgradeReq miss cycles 2055system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440134565 # number of SCUpgradeReq miss cycles 2056system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 329000 # number of SCUpgradeFailReq miss cycles 2057system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 329000 # number of SCUpgradeFailReq miss cycles 2058system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1130691878 # number of ReadExReq miss cycles 2059system.cpu1.l2cache.ReadExReq_miss_latency::total 1130691878 # number of ReadExReq miss cycles 2060system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13156500 # number of demand (read+write) miss cycles 2061system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5072997 # number of demand (read+write) miss cycles 2062system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2750627257 # number of demand (read+write) miss cycles 2063system.cpu1.l2cache.demand_miss_latency::total 2768856754 # number of demand (read+write) miss cycles 2064system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13156500 # number of overall miss cycles 2065system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5072997 # number of overall miss cycles 2066system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2750627257 # number of overall miss cycles 2067system.cpu1.l2cache.overall_miss_latency::total 2768856754 # number of overall miss cycles 2068system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23629 # number of ReadReq accesses(hits+misses) 2069system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2667 # number of ReadReq accesses(hits+misses) 2070system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1065296 # number of ReadReq accesses(hits+misses) 2071system.cpu1.l2cache.ReadReq_accesses::total 1091592 # number of ReadReq accesses(hits+misses) 2072system.cpu1.l2cache.Writeback_accesses::writebacks 115746 # number of Writeback accesses(hits+misses) 2073system.cpu1.l2cache.Writeback_accesses::total 115746 # number of Writeback accesses(hits+misses) 2074system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29917 # number of UpgradeReq accesses(hits+misses) 2075system.cpu1.l2cache.UpgradeReq_accesses::total 29917 # number of UpgradeReq accesses(hits+misses) 2076system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23176 # number of SCUpgradeReq accesses(hits+misses) 2077system.cpu1.l2cache.SCUpgradeReq_accesses::total 23176 # number of SCUpgradeReq accesses(hits+misses) 2078system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60042 # number of ReadExReq accesses(hits+misses) 2079system.cpu1.l2cache.ReadExReq_accesses::total 60042 # number of ReadExReq accesses(hits+misses) 2080system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23629 # number of demand (read+write) accesses 2081system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2667 # number of demand (read+write) accesses 2082system.cpu1.l2cache.demand_accesses::cpu1.inst 1125338 # number of demand (read+write) accesses 2083system.cpu1.l2cache.demand_accesses::total 1151634 # number of demand (read+write) accesses 2084system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23629 # number of overall (read+write) accesses 2085system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2667 # number of overall (read+write) accesses 2086system.cpu1.l2cache.overall_accesses::cpu1.inst 1125338 # number of overall (read+write) accesses 2087system.cpu1.l2cache.overall_accesses::total 1151634 # number of overall (read+write) accesses 2088system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for ReadReq accesses 2089system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.094488 # miss rate for ReadReq accesses 2090system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067664 # miss rate for ReadReq accesses 2091system.cpu1.l2cache.ReadReq_miss_rate::total 0.066807 # miss rate for ReadReq accesses 2092system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.940435 # miss rate for UpgradeReq accesses 2093system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.940435 # miss rate for UpgradeReq accesses 2094system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.966690 # miss rate for SCUpgradeReq accesses 2095system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.966690 # miss rate for SCUpgradeReq accesses 2096system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.537873 # miss rate for ReadExReq accesses 2097system.cpu1.l2cache.ReadExReq_miss_rate::total 0.537873 # miss rate for ReadExReq accesses 2098system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for demand accesses 2099system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.094488 # miss rate for demand accesses 2100system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092752 # miss rate for demand accesses 2101system.cpu1.l2cache.demand_miss_rate::total 0.091367 # miss rate for demand accesses 2102system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for overall accesses 2103system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.094488 # miss rate for overall accesses 2104system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092752 # miss rate for overall accesses 2105system.cpu1.l2cache.overall_miss_rate::total 0.091367 # miss rate for overall accesses 2106system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average ReadReq miss latency 2107system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20130.940476 # average ReadReq miss latency 2108system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22473.507658 # average ReadReq miss latency 2109system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22463.385843 # average ReadReq miss latency 2110system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18878.154683 # average UpgradeReq miss latency 2111system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18878.154683 # average UpgradeReq miss latency 2112system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19645.356410 # average SCUpgradeReq miss latency 2113system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19645.356410 # average SCUpgradeReq miss latency |
| 2105system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency 2106system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency | 2114system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency 2115system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency |
| 2107system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34619.761022 # average ReadExReq miss latency 2108system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34619.761022 # average ReadExReq miss latency 2109system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average overall miss latency 2110system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19995.901639 # average overall miss latency 2111system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26392.002204 # average overall miss latency 2112system.cpu1.l2cache.demand_avg_miss_latency::total 26351.841103 # average overall miss latency 2113system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average overall miss latency 2114system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19995.901639 # average overall miss latency 2115system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26392.002204 # average overall miss latency 2116system.cpu1.l2cache.overall_avg_miss_latency::total 26351.841103 # average overall miss latency 2117system.cpu1.l2cache.blocked_cycles::no_mshrs 5254 # number of cycles access was blocked | 2116system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35011.360211 # average ReadExReq miss latency 2117system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35011.360211 # average ReadExReq miss latency 2118system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average overall miss latency 2119system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20130.940476 # average overall miss latency 2120system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26352.810073 # average overall miss latency 2121system.cpu1.l2cache.demand_avg_miss_latency::total 26314.678192 # average overall miss latency 2122system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average overall miss latency 2123system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20130.940476 # average overall miss latency 2124system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26352.810073 # average overall miss latency 2125system.cpu1.l2cache.overall_avg_miss_latency::total 26314.678192 # average overall miss latency 2126system.cpu1.l2cache.blocked_cycles::no_mshrs 4757 # number of cycles access was blocked |
| 2118system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2127system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2119system.cpu1.l2cache.blocked::no_mshrs 187 # number of cycles access was blocked | 2128system.cpu1.l2cache.blocked::no_mshrs 158 # number of cycles access was blocked |
| 2120system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2129system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2121system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.096257 # average number of cycles each access was blocked | 2130system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.107595 # average number of cycles each access was blocked |
| 2122system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2123system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2124system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2131system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2132system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2133system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2125system.cpu1.l2cache.writebacks::writebacks 39442 # number of writebacks 2126system.cpu1.l2cache.writebacks::total 39442 # number of writebacks 2127system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1735 # number of ReadReq MSHR hits 2128system.cpu1.l2cache.ReadReq_mshr_hits::total 1735 # number of ReadReq MSHR hits 2129system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 340 # number of ReadExReq MSHR hits 2130system.cpu1.l2cache.ReadExReq_mshr_hits::total 340 # number of ReadExReq MSHR hits 2131system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2075 # number of demand (read+write) MSHR hits 2132system.cpu1.l2cache.demand_mshr_hits::total 2075 # number of demand (read+write) MSHR hits 2133system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2075 # number of overall MSHR hits 2134system.cpu1.l2cache.overall_mshr_hits::total 2075 # number of overall MSHR hits 2135system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 608 # number of ReadReq MSHR misses 2136system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 244 # number of ReadReq MSHR misses 2137system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 71774 # number of ReadReq MSHR misses 2138system.cpu1.l2cache.ReadReq_mshr_misses::total 72626 # number of ReadReq MSHR misses 2139system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 112390 # number of HardPFReq MSHR misses 2140system.cpu1.l2cache.HardPFReq_mshr_misses::total 112390 # number of HardPFReq MSHR misses 2141system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28314 # number of UpgradeReq MSHR misses 2142system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28314 # number of UpgradeReq MSHR misses 2143system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22589 # number of SCUpgradeReq MSHR misses 2144system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22589 # number of SCUpgradeReq MSHR misses 2145system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 32299 # number of ReadExReq MSHR misses 2146system.cpu1.l2cache.ReadExReq_mshr_misses::total 32299 # number of ReadExReq MSHR misses 2147system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 608 # number of demand (read+write) MSHR misses 2148system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 244 # number of demand (read+write) MSHR misses 2149system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 104073 # number of demand (read+write) MSHR misses 2150system.cpu1.l2cache.demand_mshr_misses::total 104925 # number of demand (read+write) MSHR misses 2151system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 608 # number of overall MSHR misses 2152system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 244 # number of overall MSHR misses 2153system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 104073 # number of overall MSHR misses 2154system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 112390 # number of overall MSHR misses 2155system.cpu1.l2cache.overall_mshr_misses::total 217315 # number of overall MSHR misses 2156system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of ReadReq MSHR miss cycles 2157system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3171000 # number of ReadReq MSHR miss cycles 2158system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1134657222 # number of ReadReq MSHR miss cycles 2159system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1146878474 # number of ReadReq MSHR miss cycles 2160system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3172675528 # number of HardPFReq MSHR miss cycles 2161system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3172675528 # number of HardPFReq MSHR miss cycles 2162system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 408265220 # number of UpgradeReq MSHR miss cycles 2163system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 408265220 # number of UpgradeReq MSHR miss cycles 2164system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 310198725 # number of SCUpgradeReq MSHR miss cycles 2165system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 310198725 # number of SCUpgradeReq MSHR miss cycles 2166system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 254500 # number of SCUpgradeFailReq MSHR miss cycles 2167system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 254500 # number of SCUpgradeFailReq MSHR miss cycles 2168system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 858509328 # number of ReadExReq MSHR miss cycles 2169system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 858509328 # number of ReadExReq MSHR miss cycles 2170system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of demand (read+write) MSHR miss cycles 2171system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3171000 # number of demand (read+write) MSHR miss cycles 2172system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1993166550 # number of demand (read+write) MSHR miss cycles 2173system.cpu1.l2cache.demand_mshr_miss_latency::total 2005387802 # number of demand (read+write) MSHR miss cycles 2174system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of overall MSHR miss cycles 2175system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3171000 # number of overall MSHR miss cycles 2176system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1993166550 # number of overall MSHR miss cycles 2177system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3172675528 # number of overall MSHR miss cycles 2178system.cpu1.l2cache.overall_mshr_miss_latency::total 5178063330 # number of overall MSHR miss cycles 2179system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 388960005 # number of ReadReq MSHR uncacheable cycles 2180system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 388960005 # number of ReadReq MSHR uncacheable cycles 2181system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 260468006 # number of WriteReq MSHR uncacheable cycles 2182system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 260468006 # number of WriteReq MSHR uncacheable cycles 2183system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 649428011 # number of overall MSHR uncacheable cycles 2184system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 649428011 # number of overall MSHR uncacheable cycles 2185system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for ReadReq accesses 2186system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for ReadReq accesses 2187system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.065439 # mshr miss rate for ReadReq accesses 2188system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.064579 # mshr miss rate for ReadReq accesses | 2134system.cpu1.l2cache.writebacks::writebacks 38299 # number of writebacks 2135system.cpu1.l2cache.writebacks::total 38299 # number of writebacks 2136system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1547 # number of ReadReq MSHR hits 2137system.cpu1.l2cache.ReadReq_mshr_hits::total 1547 # number of ReadReq MSHR hits 2138system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 321 # number of ReadExReq MSHR hits 2139system.cpu1.l2cache.ReadExReq_mshr_hits::total 321 # number of ReadExReq MSHR hits 2140system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1868 # number of demand (read+write) MSHR hits 2141system.cpu1.l2cache.demand_mshr_hits::total 1868 # number of demand (read+write) MSHR hits 2142system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1868 # number of overall MSHR hits 2143system.cpu1.l2cache.overall_mshr_hits::total 1868 # number of overall MSHR hits 2144system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 592 # number of ReadReq MSHR misses 2145system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 252 # number of ReadReq MSHR misses 2146system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 70535 # number of ReadReq MSHR misses 2147system.cpu1.l2cache.ReadReq_mshr_misses::total 71379 # number of ReadReq MSHR misses 2148system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 105624 # number of HardPFReq MSHR misses 2149system.cpu1.l2cache.HardPFReq_mshr_misses::total 105624 # number of HardPFReq MSHR misses 2150system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28135 # number of UpgradeReq MSHR misses 2151system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28135 # number of UpgradeReq MSHR misses 2152system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22404 # number of SCUpgradeReq MSHR misses 2153system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22404 # number of SCUpgradeReq MSHR misses 2154system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 31974 # number of ReadExReq MSHR misses 2155system.cpu1.l2cache.ReadExReq_mshr_misses::total 31974 # number of ReadExReq MSHR misses 2156system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 592 # number of demand (read+write) MSHR misses 2157system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 252 # number of demand (read+write) MSHR misses 2158system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 102509 # number of demand (read+write) MSHR misses 2159system.cpu1.l2cache.demand_mshr_misses::total 103353 # number of demand (read+write) MSHR misses 2160system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 592 # number of overall MSHR misses 2161system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 252 # number of overall MSHR misses 2162system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 102509 # number of overall MSHR misses 2163system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 105624 # number of overall MSHR misses 2164system.cpu1.l2cache.overall_mshr_misses::total 208977 # number of overall MSHR misses 2165system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of ReadReq MSHR miss cycles 2166system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3308997 # number of ReadReq MSHR miss cycles 2167system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1095971987 # number of ReadReq MSHR miss cycles 2168system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1108291484 # number of ReadReq MSHR miss cycles 2169system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2952900698 # number of HardPFReq MSHR miss cycles 2170system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2952900698 # number of HardPFReq MSHR miss cycles 2171system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 404207806 # number of UpgradeReq MSHR miss cycles 2172system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 404207806 # number of UpgradeReq MSHR miss cycles 2173system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 308121722 # number of SCUpgradeReq MSHR miss cycles 2174system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308121722 # number of SCUpgradeReq MSHR miss cycles 2175system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 273000 # number of SCUpgradeFailReq MSHR miss cycles 2176system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 273000 # number of SCUpgradeFailReq MSHR miss cycles 2177system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 864621339 # number of ReadExReq MSHR miss cycles 2178system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 864621339 # number of ReadExReq MSHR miss cycles 2179system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of demand (read+write) MSHR miss cycles 2180system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3308997 # number of demand (read+write) MSHR miss cycles 2181system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1960593326 # number of demand (read+write) MSHR miss cycles 2182system.cpu1.l2cache.demand_mshr_miss_latency::total 1972912823 # number of demand (read+write) MSHR miss cycles 2183system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of overall MSHR miss cycles 2184system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3308997 # number of overall MSHR miss cycles 2185system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1960593326 # number of overall MSHR miss cycles 2186system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2952900698 # number of overall MSHR miss cycles 2187system.cpu1.l2cache.overall_mshr_miss_latency::total 4925813521 # number of overall MSHR miss cycles 2188system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316590752 # number of ReadReq MSHR uncacheable cycles 2189system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316590752 # number of ReadReq MSHR uncacheable cycles 2190system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 186920002 # number of WriteReq MSHR uncacheable cycles 2191system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 186920002 # number of WriteReq MSHR uncacheable cycles 2192system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 503510754 # number of overall MSHR uncacheable cycles 2193system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 503510754 # number of overall MSHR uncacheable cycles 2194system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for ReadReq accesses 2195system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for ReadReq accesses 2196system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066212 # mshr miss rate for ReadReq accesses 2197system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065390 # mshr miss rate for ReadReq accesses |
| 2189system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2190system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2198system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2199system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2191system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.937270 # mshr miss rate for UpgradeReq accesses 2192system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937270 # mshr miss rate for UpgradeReq accesses 2193system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968446 # mshr miss rate for SCUpgradeReq accesses 2194system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968446 # mshr miss rate for SCUpgradeReq accesses 2195system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.514742 # mshr miss rate for ReadExReq accesses 2196system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.514742 # mshr miss rate for ReadExReq accesses 2197system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for demand accesses 2198system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for demand accesses 2199system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.089752 # mshr miss rate for demand accesses 2200system.cpu1.l2cache.demand_mshr_miss_rate::total 0.088369 # mshr miss rate for demand accesses 2201system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for overall accesses 2202system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for overall accesses 2203system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.089752 # mshr miss rate for overall accesses | 2200system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.940435 # mshr miss rate for UpgradeReq accesses 2201system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.940435 # mshr miss rate for UpgradeReq accesses 2202system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.966690 # mshr miss rate for SCUpgradeReq accesses 2203system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.966690 # mshr miss rate for SCUpgradeReq accesses 2204system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.532527 # mshr miss rate for ReadExReq accesses 2205system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.532527 # mshr miss rate for ReadExReq accesses 2206system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for demand accesses 2207system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for demand accesses 2208system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for demand accesses 2209system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089745 # mshr miss rate for demand accesses 2210system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for overall accesses 2211system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for overall accesses 2212system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for overall accesses |
| 2204system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2213system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2205system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183025 # mshr miss rate for overall accesses 2206system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average ReadReq mshr miss latency 2207system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average ReadReq mshr miss latency 2208system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15808.749993 # average ReadReq mshr miss latency 2209system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15791.568777 # average ReadReq mshr miss latency 2210system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096 # average HardPFReq mshr miss latency 2211system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28229.162096 # average HardPFReq mshr miss latency 2212system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14419.199689 # average UpgradeReq mshr miss latency 2213system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14419.199689 # average UpgradeReq mshr miss latency 2214system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13732.291159 # average SCUpgradeReq mshr miss latency 2215system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13732.291159 # average SCUpgradeReq mshr miss latency | 2214system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181461 # mshr miss rate for overall accesses 2215system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average ReadReq mshr miss latency 2216system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average ReadReq mshr miss latency 2217system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15537.988048 # average ReadReq mshr miss latency 2218system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15526.856414 # average ReadReq mshr miss latency 2219system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average HardPFReq mshr miss latency 2220system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27956.720991 # average HardPFReq mshr miss latency 2221system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14366.724933 # average UpgradeReq mshr miss latency 2222system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14366.724933 # average UpgradeReq mshr miss latency 2223system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13752.978129 # average SCUpgradeReq mshr miss latency 2224system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13752.978129 # average SCUpgradeReq mshr miss latency |
| 2216system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency 2217system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency | 2225system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency 2226system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency |
| 2218system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 26580.059073 # average ReadExReq mshr miss latency 2219system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26580.059073 # average ReadExReq mshr miss latency 2220system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average overall mshr miss latency 2221system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average overall mshr miss latency 2222system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19151.620017 # average overall mshr miss latency 2223system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19112.583293 # average overall mshr miss latency 2224system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average overall mshr miss latency 2225system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average overall mshr miss latency 2226system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19151.620017 # average overall mshr miss latency 2227system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096 # average overall mshr miss latency 2228system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23827.454755 # average overall mshr miss latency | 2227system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27041.387971 # average ReadExReq mshr miss latency 2228system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27041.387971 # average ReadExReq mshr miss latency 2229system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency 2230system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency 2231system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency 2232system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19089.071657 # average overall mshr miss latency 2233system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency 2234system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency 2235system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency 2236system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average overall mshr miss latency 2237system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23571.079693 # average overall mshr miss latency |
| 2229system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2230system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2231system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2232system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2233system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2234system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2235system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2238system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2239system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2240system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2241system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2242system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2243system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2244system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2236system.cpu1.dcache.tags.replacements 193696 # number of replacements 2237system.cpu1.dcache.tags.tagsinuse 469.979850 # Cycle average of tags in use 2238system.cpu1.dcache.tags.total_refs 7249545 # Total number of references to valid blocks. 2239system.cpu1.dcache.tags.sampled_refs 194043 # Sample count of references to valid blocks. 2240system.cpu1.dcache.tags.avg_refs 37.360508 # Average number of references to valid blocks. 2241system.cpu1.dcache.tags.warmup_cycle 107387908500 # Cycle when the warmup percentage was hit. 2242system.cpu1.dcache.tags.occ_blocks::cpu1.inst 469.979850 # Average occupied blocks per requestor 2243system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.917929 # Average percentage of cache occupancy 2244system.cpu1.dcache.tags.occ_percent::total 0.917929 # Average percentage of cache occupancy 2245system.cpu1.dcache.tags.occ_task_id_blocks::1024 347 # Occupied blocks per task id 2246system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 2247system.cpu1.dcache.tags.age_task_id_blocks_1024::3 67 # Occupied blocks per task id 2248system.cpu1.dcache.tags.occ_task_id_percent::1024 0.677734 # Percentage of cache occupancy per task id 2249system.cpu1.dcache.tags.tag_accesses 15373685 # Number of tag accesses 2250system.cpu1.dcache.tags.data_accesses 15373685 # Number of data accesses 2251system.cpu1.dcache.ReadReq_hits::cpu1.inst 3863317 # number of ReadReq hits 2252system.cpu1.dcache.ReadReq_hits::total 3863317 # number of ReadReq hits 2253system.cpu1.dcache.WriteReq_hits::cpu1.inst 3184030 # number of WriteReq hits 2254system.cpu1.dcache.WriteReq_hits::total 3184030 # number of WriteReq hits 2255system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 91016 # number of LoadLockedReq hits 2256system.cpu1.dcache.LoadLockedReq_hits::total 91016 # number of LoadLockedReq hits 2257system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 71184 # number of StoreCondReq hits 2258system.cpu1.dcache.StoreCondReq_hits::total 71184 # number of StoreCondReq hits 2259system.cpu1.dcache.demand_hits::cpu1.inst 7047347 # number of demand (read+write) hits 2260system.cpu1.dcache.demand_hits::total 7047347 # number of demand (read+write) hits 2261system.cpu1.dcache.overall_hits::cpu1.inst 7047347 # number of overall hits 2262system.cpu1.dcache.overall_hits::total 7047347 # number of overall hits 2263system.cpu1.dcache.ReadReq_misses::cpu1.inst 184713 # number of ReadReq misses 2264system.cpu1.dcache.ReadReq_misses::total 184713 # number of ReadReq misses 2265system.cpu1.dcache.WriteReq_misses::cpu1.inst 145139 # number of WriteReq misses 2266system.cpu1.dcache.WriteReq_misses::total 145139 # number of WriteReq misses 2267system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5273 # number of LoadLockedReq misses 2268system.cpu1.dcache.LoadLockedReq_misses::total 5273 # number of LoadLockedReq misses 2269system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23325 # number of StoreCondReq misses 2270system.cpu1.dcache.StoreCondReq_misses::total 23325 # number of StoreCondReq misses 2271system.cpu1.dcache.demand_misses::cpu1.inst 329852 # number of demand (read+write) misses 2272system.cpu1.dcache.demand_misses::total 329852 # number of demand (read+write) misses 2273system.cpu1.dcache.overall_misses::cpu1.inst 329852 # number of overall misses 2274system.cpu1.dcache.overall_misses::total 329852 # number of overall misses 2275system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2791622179 # number of ReadReq miss cycles 2276system.cpu1.dcache.ReadReq_miss_latency::total 2791622179 # number of ReadReq miss cycles 2277system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3393821873 # number of WriteReq miss cycles 2278system.cpu1.dcache.WriteReq_miss_latency::total 3393821873 # number of WriteReq miss cycles 2279system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 95816000 # number of LoadLockedReq miss cycles 2280system.cpu1.dcache.LoadLockedReq_miss_latency::total 95816000 # number of LoadLockedReq miss cycles 2281system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 543674761 # number of StoreCondReq miss cycles 2282system.cpu1.dcache.StoreCondReq_miss_latency::total 543674761 # number of StoreCondReq miss cycles 2283system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 324500 # number of StoreCondFailReq miss cycles 2284system.cpu1.dcache.StoreCondFailReq_miss_latency::total 324500 # number of StoreCondFailReq miss cycles 2285system.cpu1.dcache.demand_miss_latency::cpu1.inst 6185444052 # number of demand (read+write) miss cycles 2286system.cpu1.dcache.demand_miss_latency::total 6185444052 # number of demand (read+write) miss cycles 2287system.cpu1.dcache.overall_miss_latency::cpu1.inst 6185444052 # number of overall miss cycles 2288system.cpu1.dcache.overall_miss_latency::total 6185444052 # number of overall miss cycles 2289system.cpu1.dcache.ReadReq_accesses::cpu1.inst 4048030 # number of ReadReq accesses(hits+misses) 2290system.cpu1.dcache.ReadReq_accesses::total 4048030 # number of ReadReq accesses(hits+misses) 2291system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3329169 # number of WriteReq accesses(hits+misses) 2292system.cpu1.dcache.WriteReq_accesses::total 3329169 # number of WriteReq accesses(hits+misses) 2293system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 96289 # number of LoadLockedReq accesses(hits+misses) 2294system.cpu1.dcache.LoadLockedReq_accesses::total 96289 # number of LoadLockedReq accesses(hits+misses) 2295system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 94509 # number of StoreCondReq accesses(hits+misses) 2296system.cpu1.dcache.StoreCondReq_accesses::total 94509 # number of StoreCondReq accesses(hits+misses) 2297system.cpu1.dcache.demand_accesses::cpu1.inst 7377199 # number of demand (read+write) accesses 2298system.cpu1.dcache.demand_accesses::total 7377199 # number of demand (read+write) accesses 2299system.cpu1.dcache.overall_accesses::cpu1.inst 7377199 # number of overall (read+write) accesses 2300system.cpu1.dcache.overall_accesses::total 7377199 # number of overall (read+write) accesses 2301system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045630 # miss rate for ReadReq accesses 2302system.cpu1.dcache.ReadReq_miss_rate::total 0.045630 # miss rate for ReadReq accesses 2303system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043596 # miss rate for WriteReq accesses 2304system.cpu1.dcache.WriteReq_miss_rate::total 0.043596 # miss rate for WriteReq accesses 2305system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054762 # miss rate for LoadLockedReq accesses 2306system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054762 # miss rate for LoadLockedReq accesses 2307system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.246802 # miss rate for StoreCondReq accesses 2308system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246802 # miss rate for StoreCondReq accesses 2309system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044712 # miss rate for demand accesses 2310system.cpu1.dcache.demand_miss_rate::total 0.044712 # miss rate for demand accesses 2311system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044712 # miss rate for overall accesses 2312system.cpu1.dcache.overall_miss_rate::total 0.044712 # miss rate for overall accesses 2313system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15113.295648 # average ReadReq miss latency 2314system.cpu1.dcache.ReadReq_avg_miss_latency::total 15113.295648 # average ReadReq miss latency 2315system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23383.252420 # average WriteReq miss latency 2316system.cpu1.dcache.WriteReq_avg_miss_latency::total 23383.252420 # average WriteReq miss latency 2317system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18171.060118 # average LoadLockedReq miss latency 2318system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18171.060118 # average LoadLockedReq miss latency 2319system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23308.671426 # average StoreCondReq miss latency 2320system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23308.671426 # average StoreCondReq miss latency | 2245system.cpu1.dcache.tags.replacements 188481 # number of replacements 2246system.cpu1.dcache.tags.tagsinuse 475.009191 # Cycle average of tags in use 2247system.cpu1.dcache.tags.total_refs 6997616 # Total number of references to valid blocks. 2248system.cpu1.dcache.tags.sampled_refs 188846 # Sample count of references to valid blocks. 2249system.cpu1.dcache.tags.avg_refs 37.054616 # Average number of references to valid blocks. 2250system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit. 2251system.cpu1.dcache.tags.occ_blocks::cpu1.inst 475.009191 # Average occupied blocks per requestor 2252system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927752 # Average percentage of cache occupancy 2253system.cpu1.dcache.tags.occ_percent::total 0.927752 # Average percentage of cache occupancy 2254system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 2255system.cpu1.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id 2256system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id 2257system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id 2258system.cpu1.dcache.tags.tag_accesses 14853075 # Number of tag accesses 2259system.cpu1.dcache.tags.data_accesses 14853075 # Number of data accesses 2260system.cpu1.dcache.ReadReq_hits::cpu1.inst 3751603 # number of ReadReq hits 2261system.cpu1.dcache.ReadReq_hits::total 3751603 # number of ReadReq hits 2262system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051213 # number of WriteReq hits 2263system.cpu1.dcache.WriteReq_hits::total 3051213 # number of WriteReq hits 2264system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88863 # number of LoadLockedReq hits 2265system.cpu1.dcache.LoadLockedReq_hits::total 88863 # number of LoadLockedReq hits 2266system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69198 # number of StoreCondReq hits 2267system.cpu1.dcache.StoreCondReq_hits::total 69198 # number of StoreCondReq hits 2268system.cpu1.dcache.demand_hits::cpu1.inst 6802816 # number of demand (read+write) hits 2269system.cpu1.dcache.demand_hits::total 6802816 # number of demand (read+write) hits 2270system.cpu1.dcache.overall_hits::cpu1.inst 6802816 # number of overall hits 2271system.cpu1.dcache.overall_hits::total 6802816 # number of overall hits 2272system.cpu1.dcache.ReadReq_misses::cpu1.inst 182008 # number of ReadReq misses 2273system.cpu1.dcache.ReadReq_misses::total 182008 # number of ReadReq misses 2274system.cpu1.dcache.WriteReq_misses::cpu1.inst 139434 # number of WriteReq misses 2275system.cpu1.dcache.WriteReq_misses::total 139434 # number of WriteReq misses 2276system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5163 # number of LoadLockedReq misses 2277system.cpu1.dcache.LoadLockedReq_misses::total 5163 # number of LoadLockedReq misses 2278system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23176 # number of StoreCondReq misses 2279system.cpu1.dcache.StoreCondReq_misses::total 23176 # number of StoreCondReq misses 2280system.cpu1.dcache.demand_misses::cpu1.inst 321442 # number of demand (read+write) misses 2281system.cpu1.dcache.demand_misses::total 321442 # number of demand (read+write) misses 2282system.cpu1.dcache.overall_misses::cpu1.inst 321442 # number of overall misses 2283system.cpu1.dcache.overall_misses::total 321442 # number of overall misses 2284system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2744686684 # number of ReadReq miss cycles 2285system.cpu1.dcache.ReadReq_miss_latency::total 2744686684 # number of ReadReq miss cycles 2286system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3345931004 # number of WriteReq miss cycles 2287system.cpu1.dcache.WriteReq_miss_latency::total 3345931004 # number of WriteReq miss cycles 2288system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93833250 # number of LoadLockedReq miss cycles 2289system.cpu1.dcache.LoadLockedReq_miss_latency::total 93833250 # number of LoadLockedReq miss cycles 2290system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540125753 # number of StoreCondReq miss cycles 2291system.cpu1.dcache.StoreCondReq_miss_latency::total 540125753 # number of StoreCondReq miss cycles 2292system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 353500 # number of StoreCondFailReq miss cycles 2293system.cpu1.dcache.StoreCondFailReq_miss_latency::total 353500 # number of StoreCondFailReq miss cycles 2294system.cpu1.dcache.demand_miss_latency::cpu1.inst 6090617688 # number of demand (read+write) miss cycles 2295system.cpu1.dcache.demand_miss_latency::total 6090617688 # number of demand (read+write) miss cycles 2296system.cpu1.dcache.overall_miss_latency::cpu1.inst 6090617688 # number of overall miss cycles 2297system.cpu1.dcache.overall_miss_latency::total 6090617688 # number of overall miss cycles 2298system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3933611 # number of ReadReq accesses(hits+misses) 2299system.cpu1.dcache.ReadReq_accesses::total 3933611 # number of ReadReq accesses(hits+misses) 2300system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3190647 # number of WriteReq accesses(hits+misses) 2301system.cpu1.dcache.WriteReq_accesses::total 3190647 # number of WriteReq accesses(hits+misses) 2302system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94026 # number of LoadLockedReq accesses(hits+misses) 2303system.cpu1.dcache.LoadLockedReq_accesses::total 94026 # number of LoadLockedReq accesses(hits+misses) 2304system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92374 # number of StoreCondReq accesses(hits+misses) 2305system.cpu1.dcache.StoreCondReq_accesses::total 92374 # number of StoreCondReq accesses(hits+misses) 2306system.cpu1.dcache.demand_accesses::cpu1.inst 7124258 # number of demand (read+write) accesses 2307system.cpu1.dcache.demand_accesses::total 7124258 # number of demand (read+write) accesses 2308system.cpu1.dcache.overall_accesses::cpu1.inst 7124258 # number of overall (read+write) accesses 2309system.cpu1.dcache.overall_accesses::total 7124258 # number of overall (read+write) accesses 2310system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046270 # miss rate for ReadReq accesses 2311system.cpu1.dcache.ReadReq_miss_rate::total 0.046270 # miss rate for ReadReq accesses 2312system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043701 # miss rate for WriteReq accesses 2313system.cpu1.dcache.WriteReq_miss_rate::total 0.043701 # miss rate for WriteReq accesses 2314system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054910 # miss rate for LoadLockedReq accesses 2315system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054910 # miss rate for LoadLockedReq accesses 2316system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250893 # miss rate for StoreCondReq accesses 2317system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250893 # miss rate for StoreCondReq accesses 2318system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045119 # miss rate for demand accesses 2319system.cpu1.dcache.demand_miss_rate::total 0.045119 # miss rate for demand accesses 2320system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045119 # miss rate for overall accesses 2321system.cpu1.dcache.overall_miss_rate::total 0.045119 # miss rate for overall accesses 2322system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15080.033207 # average ReadReq miss latency 2323system.cpu1.dcache.ReadReq_avg_miss_latency::total 15080.033207 # average ReadReq miss latency 2324system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23996.521681 # average WriteReq miss latency 2325system.cpu1.dcache.WriteReq_avg_miss_latency::total 23996.521681 # average WriteReq miss latency 2326system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18174.171993 # average LoadLockedReq miss latency 2327system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18174.171993 # average LoadLockedReq miss latency 2328system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23305.391483 # average StoreCondReq miss latency 2329system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23305.391483 # average StoreCondReq miss latency |
| 2321system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 2322system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 2330system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 2331system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2323system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency 2324system.cpu1.dcache.demand_avg_miss_latency::total 18752.179923 # average overall miss latency 2325system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency 2326system.cpu1.dcache.overall_avg_miss_latency::total 18752.179923 # average overall miss latency | 2332system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency 2333system.cpu1.dcache.demand_avg_miss_latency::total 18947.796766 # average overall miss latency 2334system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency 2335system.cpu1.dcache.overall_avg_miss_latency::total 18947.796766 # average overall miss latency |
| 2327system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2328system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2329system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2330system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2331system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2332system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2333system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2334system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 2336system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2337system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2338system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2339system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2340system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2341system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2342system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2343system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 2335system.cpu1.dcache.writebacks::writebacks 119069 # number of writebacks 2336system.cpu1.dcache.writebacks::total 119069 # number of writebacks 2337system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15047 # number of ReadReq MSHR hits 2338system.cpu1.dcache.ReadReq_mshr_hits::total 15047 # number of ReadReq MSHR hits 2339system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 52186 # number of WriteReq MSHR hits 2340system.cpu1.dcache.WriteReq_mshr_hits::total 52186 # number of WriteReq MSHR hits 2341system.cpu1.dcache.demand_mshr_hits::cpu1.inst 67233 # number of demand (read+write) MSHR hits 2342system.cpu1.dcache.demand_mshr_hits::total 67233 # number of demand (read+write) MSHR hits 2343system.cpu1.dcache.overall_mshr_hits::cpu1.inst 67233 # number of overall MSHR hits 2344system.cpu1.dcache.overall_mshr_hits::total 67233 # number of overall MSHR hits 2345system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 169666 # number of ReadReq MSHR misses 2346system.cpu1.dcache.ReadReq_mshr_misses::total 169666 # number of ReadReq MSHR misses 2347system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 92953 # number of WriteReq MSHR misses 2348system.cpu1.dcache.WriteReq_mshr_misses::total 92953 # number of WriteReq MSHR misses 2349system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5273 # number of LoadLockedReq MSHR misses 2350system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5273 # number of LoadLockedReq MSHR misses 2351system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23325 # number of StoreCondReq MSHR misses 2352system.cpu1.dcache.StoreCondReq_mshr_misses::total 23325 # number of StoreCondReq MSHR misses 2353system.cpu1.dcache.demand_mshr_misses::cpu1.inst 262619 # number of demand (read+write) MSHR misses 2354system.cpu1.dcache.demand_mshr_misses::total 262619 # number of demand (read+write) MSHR misses 2355system.cpu1.dcache.overall_mshr_misses::cpu1.inst 262619 # number of overall MSHR misses 2356system.cpu1.dcache.overall_mshr_misses::total 262619 # number of overall MSHR misses 2357system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2247676267 # number of ReadReq MSHR miss cycles 2358system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247676267 # number of ReadReq MSHR miss cycles 2359system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2022089921 # number of WriteReq MSHR miss cycles 2360system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2022089921 # number of WriteReq MSHR miss cycles 2361system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 85260000 # number of LoadLockedReq MSHR miss cycles 2362system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85260000 # number of LoadLockedReq MSHR miss cycles 2363system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 495802239 # number of StoreCondReq MSHR miss cycles 2364system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495802239 # number of StoreCondReq MSHR miss cycles 2365system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 310500 # number of StoreCondFailReq MSHR miss cycles 2366system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 310500 # number of StoreCondFailReq MSHR miss cycles 2367system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4269766188 # number of demand (read+write) MSHR miss cycles 2368system.cpu1.dcache.demand_mshr_miss_latency::total 4269766188 # number of demand (read+write) MSHR miss cycles 2369system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4269766188 # number of overall MSHR miss cycles 2370system.cpu1.dcache.overall_mshr_miss_latency::total 4269766188 # number of overall MSHR miss cycles 2371system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 405245745 # number of ReadReq MSHR uncacheable cycles 2372system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 405245745 # number of ReadReq MSHR uncacheable cycles 2373system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 279561993 # number of WriteReq MSHR uncacheable cycles 2374system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279561993 # number of WriteReq MSHR uncacheable cycles 2375system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 684807738 # number of overall MSHR uncacheable cycles 2376system.cpu1.dcache.overall_mshr_uncacheable_latency::total 684807738 # number of overall MSHR uncacheable cycles 2377system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.041913 # mshr miss rate for ReadReq accesses 2378system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041913 # mshr miss rate for ReadReq accesses 2379system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027921 # mshr miss rate for WriteReq accesses 2380system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027921 # mshr miss rate for WriteReq accesses 2381system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054762 # mshr miss rate for LoadLockedReq accesses 2382system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054762 # mshr miss rate for LoadLockedReq accesses 2383system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.246802 # mshr miss rate for StoreCondReq accesses 2384system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246802 # mshr miss rate for StoreCondReq accesses 2385system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for demand accesses 2386system.cpu1.dcache.demand_mshr_miss_rate::total 0.035599 # mshr miss rate for demand accesses 2387system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for overall accesses 2388system.cpu1.dcache.overall_mshr_miss_rate::total 0.035599 # mshr miss rate for overall accesses 2389system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13247.652841 # average ReadReq mshr miss latency 2390system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13247.652841 # average ReadReq mshr miss latency 2391system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 21753.896281 # average WriteReq mshr miss latency 2392system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21753.896281 # average WriteReq mshr miss latency 2393system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16169.163664 # average LoadLockedReq mshr miss latency 2394system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16169.163664 # average LoadLockedReq mshr miss latency 2395system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21256.258907 # average StoreCondReq mshr miss latency 2396system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21256.258907 # average StoreCondReq mshr miss latency | 2344system.cpu1.dcache.writebacks::writebacks 115746 # number of writebacks 2345system.cpu1.dcache.writebacks::total 115746 # number of writebacks 2346system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15462 # number of ReadReq MSHR hits 2347system.cpu1.dcache.ReadReq_mshr_hits::total 15462 # number of ReadReq MSHR hits 2348system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49475 # number of WriteReq MSHR hits 2349system.cpu1.dcache.WriteReq_mshr_hits::total 49475 # number of WriteReq MSHR hits 2350system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64937 # number of demand (read+write) MSHR hits 2351system.cpu1.dcache.demand_mshr_hits::total 64937 # number of demand (read+write) MSHR hits 2352system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64937 # number of overall MSHR hits 2353system.cpu1.dcache.overall_mshr_hits::total 64937 # number of overall MSHR hits 2354system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166546 # number of ReadReq MSHR misses 2355system.cpu1.dcache.ReadReq_mshr_misses::total 166546 # number of ReadReq MSHR misses 2356system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89959 # number of WriteReq MSHR misses 2357system.cpu1.dcache.WriteReq_mshr_misses::total 89959 # number of WriteReq MSHR misses 2358system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5163 # number of LoadLockedReq MSHR misses 2359system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5163 # number of LoadLockedReq MSHR misses 2360system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23176 # number of StoreCondReq MSHR misses 2361system.cpu1.dcache.StoreCondReq_mshr_misses::total 23176 # number of StoreCondReq MSHR misses 2362system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256505 # number of demand (read+write) MSHR misses 2363system.cpu1.dcache.demand_mshr_misses::total 256505 # number of demand (read+write) MSHR misses 2364system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256505 # number of overall MSHR misses 2365system.cpu1.dcache.overall_mshr_misses::total 256505 # number of overall MSHR misses 2366system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202025254 # number of ReadReq MSHR miss cycles 2367system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202025254 # number of ReadReq MSHR miss cycles 2368system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2000006836 # number of WriteReq MSHR miss cycles 2369system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2000006836 # number of WriteReq MSHR miss cycles 2370system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83498750 # number of LoadLockedReq MSHR miss cycles 2371system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83498750 # number of LoadLockedReq MSHR miss cycles 2372system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492542247 # number of StoreCondReq MSHR miss cycles 2373system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492542247 # number of StoreCondReq MSHR miss cycles 2374system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 337500 # number of StoreCondFailReq MSHR miss cycles 2375system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 337500 # number of StoreCondFailReq MSHR miss cycles 2376system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4202032090 # number of demand (read+write) MSHR miss cycles 2377system.cpu1.dcache.demand_mshr_miss_latency::total 4202032090 # number of demand (read+write) MSHR miss cycles 2378system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4202032090 # number of overall MSHR miss cycles 2379system.cpu1.dcache.overall_mshr_miss_latency::total 4202032090 # number of overall MSHR miss cycles 2380system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329591498 # number of ReadReq MSHR uncacheable cycles 2381system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329591498 # number of ReadReq MSHR uncacheable cycles 2382system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202938498 # number of WriteReq MSHR uncacheable cycles 2383system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202938498 # number of WriteReq MSHR uncacheable cycles 2384system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532529996 # number of overall MSHR uncacheable cycles 2385system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532529996 # number of overall MSHR uncacheable cycles 2386system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042339 # mshr miss rate for ReadReq accesses 2387system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042339 # mshr miss rate for ReadReq accesses 2388system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028195 # mshr miss rate for WriteReq accesses 2389system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028195 # mshr miss rate for WriteReq accesses 2390system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054910 # mshr miss rate for LoadLockedReq accesses 2391system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054910 # mshr miss rate for LoadLockedReq accesses 2392system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250893 # mshr miss rate for StoreCondReq accesses 2393system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250893 # mshr miss rate for StoreCondReq accesses 2394system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for demand accesses 2395system.cpu1.dcache.demand_mshr_miss_rate::total 0.036004 # mshr miss rate for demand accesses 2396system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for overall accesses 2397system.cpu1.dcache.overall_mshr_miss_rate::total 0.036004 # mshr miss rate for overall accesses 2398system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13221.724052 # average ReadReq mshr miss latency 2399system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13221.724052 # average ReadReq mshr miss latency 2400system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22232.426283 # average WriteReq mshr miss latency 2401system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22232.426283 # average WriteReq mshr miss latency 2402system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16172.525663 # average LoadLockedReq mshr miss latency 2403system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16172.525663 # average LoadLockedReq mshr miss latency 2404system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21252.254358 # average StoreCondReq mshr miss latency 2405system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21252.254358 # average StoreCondReq mshr miss latency |
| 2397system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 2398system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2406system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 2407system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2399system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency 2400system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency 2401system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency 2402system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency | 2408system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency 2409system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency 2410system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency 2411system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency |
| 2403system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2404system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2405system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2406system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2407system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2408system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2409system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2412system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2413system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2414system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2415system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2416system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2417system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2418system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2410system.iocache.tags.replacements 36445 # number of replacements 2411system.iocache.tags.tagsinuse 14.485749 # Cycle average of tags in use | 2419system.iocache.tags.replacements 36417 # number of replacements 2420system.iocache.tags.tagsinuse 0.992209 # Cycle average of tags in use |
| 2412system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 2421system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 2413system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. | 2422system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. |
| 2414system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2423system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2415system.iocache.tags.warmup_cycle 268964842000 # Cycle when the warmup percentage was hit. 2416system.iocache.tags.occ_blocks::realview.ide 14.485749 # Average occupied blocks per requestor 2417system.iocache.tags.occ_percent::realview.ide 0.905359 # Average percentage of cache occupancy 2418system.iocache.tags.occ_percent::total 0.905359 # Average percentage of cache occupancy | 2424system.iocache.tags.warmup_cycle 268855800000 # Cycle when the warmup percentage was hit. 2425system.iocache.tags.occ_blocks::realview.ide 0.992209 # Average occupied blocks per requestor 2426system.iocache.tags.occ_percent::realview.ide 0.062013 # Average percentage of cache occupancy 2427system.iocache.tags.occ_percent::total 0.062013 # Average percentage of cache occupancy |
| 2419system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2420system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2421system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2428system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2429system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2430system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2422system.iocache.tags.tag_accesses 328575 # Number of tag accesses 2423system.iocache.tags.data_accesses 328575 # Number of data accesses | 2431system.iocache.tags.tag_accesses 328483 # Number of tag accesses 2432system.iocache.tags.data_accesses 328483 # Number of data accesses |
| 2424system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2425system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits | 2433system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2434system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits |
| 2426system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2427system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2428system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses 2429system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses 2430system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2431system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2432system.iocache.overall_misses::realview.ide 255 # number of overall misses 2433system.iocache.overall_misses::total 255 # number of overall misses 2434system.iocache.ReadReq_miss_latency::realview.ide 31822377 # number of ReadReq miss cycles 2435system.iocache.ReadReq_miss_latency::total 31822377 # number of ReadReq miss cycles 2436system.iocache.demand_miss_latency::realview.ide 31822377 # number of demand (read+write) miss cycles 2437system.iocache.demand_miss_latency::total 31822377 # number of demand (read+write) miss cycles 2438system.iocache.overall_miss_latency::realview.ide 31822377 # number of overall miss cycles 2439system.iocache.overall_miss_latency::total 31822377 # number of overall miss cycles 2440system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2441system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2442system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) 2443system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) 2444system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2445system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2446system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2447system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses | 2435system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2436system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2437system.iocache.WriteInvalidateReq_misses::realview.ide 35 # number of WriteInvalidateReq misses 2438system.iocache.WriteInvalidateReq_misses::total 35 # number of WriteInvalidateReq misses 2439system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2440system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2441system.iocache.overall_misses::realview.ide 243 # number of overall misses 2442system.iocache.overall_misses::total 243 # number of overall misses 2443system.iocache.ReadReq_miss_latency::realview.ide 31692627 # number of ReadReq miss cycles 2444system.iocache.ReadReq_miss_latency::total 31692627 # number of ReadReq miss cycles 2445system.iocache.demand_miss_latency::realview.ide 31692627 # number of demand (read+write) miss cycles 2446system.iocache.demand_miss_latency::total 31692627 # number of demand (read+write) miss cycles 2447system.iocache.overall_miss_latency::realview.ide 31692627 # number of overall miss cycles 2448system.iocache.overall_miss_latency::total 31692627 # number of overall miss cycles 2449system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2450system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2451system.iocache.WriteInvalidateReq_accesses::realview.ide 36259 # number of WriteInvalidateReq accesses(hits+misses) 2452system.iocache.WriteInvalidateReq_accesses::total 36259 # number of WriteInvalidateReq accesses(hits+misses) 2453system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2454system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2455system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2456system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses |
| 2448system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2449system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 2457system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2458system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 2450system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses 2451system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses | 2459system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000965 # miss rate for WriteInvalidateReq accesses 2460system.iocache.WriteInvalidateReq_miss_rate::total 0.000965 # miss rate for WriteInvalidateReq accesses |
| 2452system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2453system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2454system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2455system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2461system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2462system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2463system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2464system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2456system.iocache.ReadReq_avg_miss_latency::realview.ide 124793.635294 # average ReadReq miss latency 2457system.iocache.ReadReq_avg_miss_latency::total 124793.635294 # average ReadReq miss latency 2458system.iocache.demand_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency 2459system.iocache.demand_avg_miss_latency::total 124793.635294 # average overall miss latency 2460system.iocache.overall_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency 2461system.iocache.overall_avg_miss_latency::total 124793.635294 # average overall miss latency | 2465system.iocache.ReadReq_avg_miss_latency::realview.ide 130422.333333 # average ReadReq miss latency 2466system.iocache.ReadReq_avg_miss_latency::total 130422.333333 # average ReadReq miss latency 2467system.iocache.demand_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency 2468system.iocache.demand_avg_miss_latency::total 130422.333333 # average overall miss latency 2469system.iocache.overall_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency 2470system.iocache.overall_avg_miss_latency::total 130422.333333 # average overall miss latency |
| 2462system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2463system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2464system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2465system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2466system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2467system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2468system.iocache.fast_writes 36224 # number of fast writes performed 2469system.iocache.cache_copies 0 # number of cache copies performed | 2471system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2472system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2473system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2474system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2475system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2476system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2477system.iocache.fast_writes 36224 # number of fast writes performed 2478system.iocache.cache_copies 0 # number of cache copies performed |
| 2470system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2471system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2472system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2473system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2474system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2475system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses 2476system.iocache.ReadReq_mshr_miss_latency::realview.ide 18561377 # number of ReadReq MSHR miss cycles 2477system.iocache.ReadReq_mshr_miss_latency::total 18561377 # number of ReadReq MSHR miss cycles 2478system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2257984064 # number of WriteInvalidateReq MSHR miss cycles 2479system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2257984064 # number of WriteInvalidateReq MSHR miss cycles 2480system.iocache.demand_mshr_miss_latency::realview.ide 18561377 # number of demand (read+write) MSHR miss cycles 2481system.iocache.demand_mshr_miss_latency::total 18561377 # number of demand (read+write) MSHR miss cycles 2482system.iocache.overall_mshr_miss_latency::realview.ide 18561377 # number of overall MSHR miss cycles 2483system.iocache.overall_mshr_miss_latency::total 18561377 # number of overall MSHR miss cycles | 2479system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2480system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2481system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2482system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2483system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2484system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses 2485system.iocache.ReadReq_mshr_miss_latency::realview.ide 19056127 # number of ReadReq MSHR miss cycles 2486system.iocache.ReadReq_mshr_miss_latency::total 19056127 # number of ReadReq MSHR miss cycles 2487system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2259252335 # number of WriteInvalidateReq MSHR miss cycles 2488system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2259252335 # number of WriteInvalidateReq MSHR miss cycles 2489system.iocache.demand_mshr_miss_latency::realview.ide 19056127 # number of demand (read+write) MSHR miss cycles 2490system.iocache.demand_mshr_miss_latency::total 19056127 # number of demand (read+write) MSHR miss cycles 2491system.iocache.overall_mshr_miss_latency::realview.ide 19056127 # number of overall MSHR miss cycles 2492system.iocache.overall_mshr_miss_latency::total 19056127 # number of overall MSHR miss cycles |
| 2484system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2485system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2486system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2487system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2488system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2489system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2493system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2494system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2495system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2496system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2497system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2498system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2490system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72789.713725 # average ReadReq mshr miss latency 2491system.iocache.ReadReq_avg_mshr_miss_latency::total 72789.713725 # average ReadReq mshr miss latency | 2499system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78420.275720 # average ReadReq mshr miss latency 2500system.iocache.ReadReq_avg_mshr_miss_latency::total 78420.275720 # average ReadReq mshr miss latency |
| 2492system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2493system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency | 2501system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2502system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 2494system.iocache.demand_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency 2495system.iocache.demand_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency 2496system.iocache.overall_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency 2497system.iocache.overall_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency | 2503system.iocache.demand_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency 2504system.iocache.demand_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency 2505system.iocache.overall_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency 2506system.iocache.overall_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency |
| 2498system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2499 2500---------- End Simulation Statistics ---------- | 2507system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2508 2509---------- End Simulation Statistics ---------- |