| stats.txt (10433:821cbe4a183b) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.658488 # Number of seconds simulated 4sim_ticks 2658488068000 # Number of ticks simulated 5final_tick 2658488068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.843718 # Number of seconds simulated 4sim_ticks 2843718094000 # Number of ticks simulated 5final_tick 2843718094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 70694 # Simulator instruction rate (inst/s) 8host_op_rate 85127 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2981704600 # Simulator tick rate (ticks/s) 10host_mem_usage 438480 # Number of bytes of host memory used 11host_seconds 891.60 # Real time elapsed on the host 12sim_insts 63030433 # Number of instructions simulated 13sim_ops 75898814 # Number of ops (including micro ops) simulated | 7host_inst_rate 161241 # Simulator instruction rate (inst/s) 8host_op_rate 195251 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3650642703 # Simulator tick rate (ticks/s) 10host_mem_usage 606904 # Number of bytes of host memory used 11host_seconds 778.96 # Real time elapsed on the host 12sim_insts 125601128 # Number of instructions simulated 13sim_ops 152093417 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 674300 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 5028416 # Number of bytes read from this memory | 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 10240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1341052 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 10709120 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::cpu1.inst 495096 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.l2cache.prefetcher 5148352 # Number of bytes read from this memory 24system.physmem.bytes_read::total 134030836 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 219456 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 61376 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 280832 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 4344000 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory 31system.physmem.bytes_written::total 7373136 # Number of bytes written to this memory 32system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 10595 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.l2cache.prefetcher 78569 # Number of read requests responded to by this memory | 22system.physmem.bytes_read::cpu1.inst 541088 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.l2cache.prefetcher 1237760 # Number of bytes read from this memory 24system.physmem.bytes_read::total 13841180 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 411264 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 443200 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 7176832 # Number of bytes written to this memory 29system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory 32system.physmem.bytes_written::total 9512912 # Number of bytes written to this memory 33system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.dtb.walker 160 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 21479 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.l2cache.prefetcher 167330 # Number of read requests responded to by this memory |
| 37system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory | 38system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory |
| 38system.physmem.num_reads::cpu1.inst 7754 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.l2cache.prefetcher 80443 # Number of read requests responded to by this memory 40system.physmem.num_reads::total 15512805 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 67875 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory 44system.physmem.num_writes::total 825159 # Number of write requests responded to by this memory 45system.physmem.bw_read::realview.clcd 46147806 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.dtb.walker 96 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.inst 253640 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.l2cache.prefetcher 1891457 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.dtb.walker 337 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.inst 186232 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.l2cache.prefetcher 1936571 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 50416189 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 82549 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 23087 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 105636 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 1634011 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu1.inst 1133026 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::total 2773432 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 1634011 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::realview.clcd 46147806 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.dtb.walker 96 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.inst 260035 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.l2cache.prefetcher 1891457 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.dtb.walker 337 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.inst 1319258 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.l2cache.prefetcher 1936571 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 53189621 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.readReqs 15512805 # Number of read requests accepted 72system.physmem.writeReqs 825159 # Number of write requests accepted 73system.physmem.readBursts 15512805 # Number of DRAM read bursts, including those serviced by the write queue 74system.physmem.writeBursts 825159 # Number of DRAM write bursts, including those merged in the write queue 75system.physmem.bytesReadDRAM 992712960 # Total number of bytes read from DRAM 76system.physmem.bytesReadWrQ 106560 # Total number of bytes read from write queue 77system.physmem.bytesWritten 7389248 # Total number of bytes written to DRAM 78system.physmem.bytesReadSys 134030836 # Total read bytes from the system interface side 79system.physmem.bytesWrittenSys 7373136 # Total written bytes from the system interface side 80system.physmem.servicedByWrQ 1665 # Number of DRAM read bursts serviced by the write queue 81system.physmem.mergedWrBursts 709677 # Number of DRAM write bursts merged with an existing one 82system.physmem.neitherReadNorWriteReqs 15674 # Number of requests that are neither read nor write 83system.physmem.perBankRdBursts::0 969393 # Per bank write bursts 84system.physmem.perBankRdBursts::1 969270 # Per bank write bursts 85system.physmem.perBankRdBursts::2 969024 # Per bank write bursts 86system.physmem.perBankRdBursts::3 969581 # Per bank write bursts 87system.physmem.perBankRdBursts::4 971912 # Per bank write bursts 88system.physmem.perBankRdBursts::5 969565 # Per bank write bursts 89system.physmem.perBankRdBursts::6 969152 # Per bank write bursts 90system.physmem.perBankRdBursts::7 969036 # Per bank write bursts 91system.physmem.perBankRdBursts::8 969555 # Per bank write bursts 92system.physmem.perBankRdBursts::9 969606 # Per bank write bursts 93system.physmem.perBankRdBursts::10 969469 # Per bank write bursts 94system.physmem.perBankRdBursts::11 968910 # Per bank write bursts 95system.physmem.perBankRdBursts::12 969137 # Per bank write bursts 96system.physmem.perBankRdBursts::13 969414 # Per bank write bursts 97system.physmem.perBankRdBursts::14 969294 # Per bank write bursts 98system.physmem.perBankRdBursts::15 968822 # Per bank write bursts 99system.physmem.perBankWrBursts::0 7303 # Per bank write bursts 100system.physmem.perBankWrBursts::1 7359 # Per bank write bursts 101system.physmem.perBankWrBursts::2 6981 # Per bank write bursts 102system.physmem.perBankWrBursts::3 7260 # Per bank write bursts 103system.physmem.perBankWrBursts::4 7486 # Per bank write bursts 104system.physmem.perBankWrBursts::5 7442 # Per bank write bursts 105system.physmem.perBankWrBursts::6 7374 # Per bank write bursts 106system.physmem.perBankWrBursts::7 7195 # Per bank write bursts 107system.physmem.perBankWrBursts::8 7413 # Per bank write bursts 108system.physmem.perBankWrBursts::9 7378 # Per bank write bursts 109system.physmem.perBankWrBursts::10 7327 # Per bank write bursts 110system.physmem.perBankWrBursts::11 7067 # Per bank write bursts 111system.physmem.perBankWrBursts::12 6951 # Per bank write bursts 112system.physmem.perBankWrBursts::13 7051 # Per bank write bursts 113system.physmem.perBankWrBursts::14 7072 # Per bank write bursts 114system.physmem.perBankWrBursts::15 6798 # Per bank write bursts | 39system.physmem.num_reads::cpu1.inst 8478 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.l2cache.prefetcher 19340 # Number of read requests responded to by this memory 41system.physmem.num_reads::total 216817 # Number of read requests responded to by this memory 42system.physmem.num_writes::writebacks 112138 # Number of write requests responded to by this memory 43system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 152798 # Number of write requests responded to by this memory 47system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.dtb.walker 3601 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 471584 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.l2cache.prefetcher 3765887 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.dtb.walker 315 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 190275 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.l2cache.prefetcher 435261 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::total 4867283 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu0.inst 144622 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::total 155852 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_write::writebacks 2523749 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::realview.ide 815248 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 3345237 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2523749 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::realview.ide 815586 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 3601 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 477810 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.l2cache.prefetcher 3765887 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.dtb.walker 315 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 190289 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.l2cache.prefetcher 435261 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::total 8212520 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.readReqs 216817 # Number of read requests accepted 75system.physmem.writeReqs 152798 # Number of write requests accepted 76system.physmem.readBursts 216817 # Number of DRAM read bursts, including those serviced by the write queue 77system.physmem.writeBursts 152798 # Number of DRAM write bursts, including those merged in the write queue 78system.physmem.bytesReadDRAM 13860672 # Total number of bytes read from DRAM 79system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue 80system.physmem.bytesWritten 9527424 # Total number of bytes written to DRAM 81system.physmem.bytesReadSys 13841180 # Total read bytes from the system interface side 82system.physmem.bytesWrittenSys 9512912 # Total written bytes from the system interface side 83system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue 84system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one 85system.physmem.neitherReadNorWriteReqs 13461 # Number of requests that are neither read nor write 86system.physmem.perBankRdBursts::0 14081 # Per bank write bursts 87system.physmem.perBankRdBursts::1 13907 # Per bank write bursts 88system.physmem.perBankRdBursts::2 14464 # Per bank write bursts 89system.physmem.perBankRdBursts::3 13988 # Per bank write bursts 90system.physmem.perBankRdBursts::4 16210 # Per bank write bursts 91system.physmem.perBankRdBursts::5 13087 # Per bank write bursts 92system.physmem.perBankRdBursts::6 13697 # Per bank write bursts 93system.physmem.perBankRdBursts::7 13930 # Per bank write bursts 94system.physmem.perBankRdBursts::8 13098 # Per bank write bursts 95system.physmem.perBankRdBursts::9 13410 # Per bank write bursts 96system.physmem.perBankRdBursts::10 13015 # Per bank write bursts 97system.physmem.perBankRdBursts::11 11706 # Per bank write bursts 98system.physmem.perBankRdBursts::12 12947 # Per bank write bursts 99system.physmem.perBankRdBursts::13 13659 # Per bank write bursts 100system.physmem.perBankRdBursts::14 12722 # Per bank write bursts 101system.physmem.perBankRdBursts::15 12652 # Per bank write bursts 102system.physmem.perBankWrBursts::0 9756 # Per bank write bursts 103system.physmem.perBankWrBursts::1 10039 # Per bank write bursts 104system.physmem.perBankWrBursts::2 10215 # Per bank write bursts 105system.physmem.perBankWrBursts::3 9785 # Per bank write bursts 106system.physmem.perBankWrBursts::4 9214 # Per bank write bursts 107system.physmem.perBankWrBursts::5 9161 # Per bank write bursts 108system.physmem.perBankWrBursts::6 9492 # Per bank write bursts 109system.physmem.perBankWrBursts::7 9434 # Per bank write bursts 110system.physmem.perBankWrBursts::8 9026 # Per bank write bursts 111system.physmem.perBankWrBursts::9 9356 # Per bank write bursts 112system.physmem.perBankWrBursts::10 9095 # Per bank write bursts 113system.physmem.perBankWrBursts::11 8550 # Per bank write bursts 114system.physmem.perBankWrBursts::12 9129 # Per bank write bursts 115system.physmem.perBankWrBursts::13 9225 # Per bank write bursts 116system.physmem.perBankWrBursts::14 8893 # Per bank write bursts 117system.physmem.perBankWrBursts::15 8496 # Per bank write bursts |
| 115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 118system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 117system.physmem.totGap 2658486560500 # Total gap between requests | 119system.physmem.numWrRetry 3 # Number of times write queue was full causing retry 120system.physmem.totGap 2843715756500 # Total gap between requests |
| 118system.physmem.readPktSize::0 0 # Read request sizes (log2) 119system.physmem.readPktSize::1 0 # Read request sizes (log2) | 121system.physmem.readPktSize::0 0 # Read request sizes (log2) 122system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 120system.physmem.readPktSize::2 59 # Read request sizes (log2) 121system.physmem.readPktSize::3 15335449 # Read request sizes (log2) | 123system.physmem.readPktSize::2 559 # Read request sizes (log2) 124system.physmem.readPktSize::3 28 # Read request sizes (log2) |
| 122system.physmem.readPktSize::4 0 # Read request sizes (log2) 123system.physmem.readPktSize::5 0 # Read request sizes (log2) | 125system.physmem.readPktSize::4 0 # Read request sizes (log2) 126system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 124system.physmem.readPktSize::6 177297 # Read request sizes (log2) | 127system.physmem.readPktSize::6 216230 # Read request sizes (log2) |
| 125system.physmem.writePktSize::0 0 # Write request sizes (log2) 126system.physmem.writePktSize::1 0 # Write request sizes (log2) | 128system.physmem.writePktSize::0 0 # Write request sizes (log2) 129system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| 127system.physmem.writePktSize::2 757284 # Write request sizes (log2) | 130system.physmem.writePktSize::2 4436 # Write request sizes (log2) |
| 128system.physmem.writePktSize::3 0 # Write request sizes (log2) 129system.physmem.writePktSize::4 0 # Write request sizes (log2) 130system.physmem.writePktSize::5 0 # Write request sizes (log2) | 131system.physmem.writePktSize::3 0 # Write request sizes (log2) 132system.physmem.writePktSize::4 0 # Write request sizes (log2) 133system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 131system.physmem.writePktSize::6 67875 # Write request sizes (log2) 132system.physmem.rdQLenPdf::0 1046149 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::1 1019751 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::2 986849 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::3 1098941 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::4 993476 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::5 1059379 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::6 2733951 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::7 2632980 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::8 3427107 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::9 133098 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::10 114256 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::11 105608 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::12 102115 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::13 19625 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::14 18867 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::16 143 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::20 20 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::22 10 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::23 7 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see | 134system.physmem.writePktSize::6 148362 # Write request sizes (log2) 135system.physmem.rdQLenPdf::0 79662 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::1 62454 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::2 17878 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::3 12202 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::4 10651 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::5 9329 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::6 8314 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::7 7470 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::10 438 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::11 316 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::13 169 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::14 140 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| 161system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 164system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 164system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 167system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 179system.physmem.wrQLenPdf::15 4048 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 4083 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 4691 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 5817 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 6304 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 6519 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 6785 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 6904 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 7081 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 7290 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 7348 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 7580 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 7259 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 7270 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 7345 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 7006 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::33 166 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 228system.physmem.bytesPerActivate::samples 1037609 # Bytes accessed per row activation 229system.physmem.bytesPerActivate::mean 963.852673 # Bytes accessed per row activation 230system.physmem.bytesPerActivate::gmean 885.641044 # Bytes accessed per row activation 231system.physmem.bytesPerActivate::stdev 219.370096 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::0-127 32112 3.09% 3.09% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::128-255 21277 2.05% 5.15% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::256-383 9254 0.89% 6.04% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::384-511 2543 0.25% 6.28% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::512-639 3048 0.29% 6.58% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::640-767 2181 0.21% 6.79% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::768-895 8654 0.83% 7.62% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::896-1023 1069 0.10% 7.72% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::1024-1151 957471 92.28% 100.00% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::total 1037609 # Bytes accessed per row activation 242system.physmem.rdPerTurnAround::samples 6645 # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::mean 2334.257336 # Reads before turning the bus around for writes 244system.physmem.rdPerTurnAround::stdev 73724.534105 # Reads before turning the bus around for writes 245system.physmem.rdPerTurnAround::0-262143 6636 99.86% 99.86% # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.89% # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.92% # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::4.71859e+06-4.98074e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 6645 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 6645 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 17.375019 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 17.329909 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 1.281758 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16 2539 38.21% 38.21% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::17 27 0.41% 38.62% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::18 3660 55.08% 93.69% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::19 195 2.93% 96.63% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::20 85 1.28% 97.91% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::21 57 0.86% 98.77% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::22 40 0.60% 99.37% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::24 11 0.17% 99.80% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::25 9 0.14% 99.94% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::26 2 0.03% 99.97% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 6645 # Writes before turning the bus around for reads 271system.physmem.totQLat 404032545000 # Total ticks spent queuing 272system.physmem.totMemAccLat 694866420000 # Total ticks spent from burst creation until serviced by the DRAM 273system.physmem.totBusLat 77555700000 # Total ticks spent in databus transfers 274system.physmem.avgQLat 26047.89 # Average queueing delay per DRAM burst | 182system.physmem.wrQLenPdf::15 2965 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::16 3559 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::17 4302 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::18 5372 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::19 6291 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::20 7531 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::21 8122 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::22 8991 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::23 9788 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::24 10919 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::25 10684 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::26 10534 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::27 10395 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::28 10863 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::29 9042 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::30 8791 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::31 8805 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::32 8230 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::35 299 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::36 247 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::39 157 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::41 106 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::42 107 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see 231system.physmem.bytesPerActivate::samples 92355 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::mean 253.241254 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::gmean 143.538036 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::stdev 308.020470 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::0-127 46699 50.56% 50.56% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::128-255 18860 20.42% 70.99% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::256-383 6817 7.38% 78.37% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::384-511 3583 3.88% 82.25% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::512-639 3053 3.31% 85.55% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::640-767 2112 2.29% 87.84% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::768-895 1277 1.38% 89.22% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::896-1023 1140 1.23% 90.46% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::1024-1151 8814 9.54% 100.00% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::total 92355 # Bytes accessed per row activation 245system.physmem.rdPerTurnAround::samples 7471 # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::mean 28.988355 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::stdev 530.902810 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::0-2047 7470 99.99% 99.99% # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::total 7471 # Reads before turning the bus around for writes 251system.physmem.wrPerTurnAround::samples 7471 # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::mean 19.925847 # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::gmean 18.607688 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::stdev 10.837629 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::16-19 6200 82.99% 82.99% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::20-23 464 6.21% 89.20% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::24-27 76 1.02% 90.22% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::28-31 210 2.81% 93.03% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::32-35 192 2.57% 95.60% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::36-39 15 0.20% 95.80% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::40-43 27 0.36% 96.16% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::44-47 15 0.20% 96.36% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::48-51 29 0.39% 96.75% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::52-55 10 0.13% 96.88% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::56-59 9 0.12% 97.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::60-63 6 0.08% 97.08% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::64-67 163 2.18% 99.26% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::68-71 4 0.05% 99.32% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::72-75 5 0.07% 99.38% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::76-79 4 0.05% 99.44% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::80-83 14 0.19% 99.63% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::84-87 1 0.01% 99.64% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::100-103 4 0.05% 99.75% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::104-107 1 0.01% 99.76% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::108-111 3 0.04% 99.80% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::112-115 2 0.03% 99.83% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::116-119 2 0.03% 99.85% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::120-123 2 0.03% 99.88% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::128-131 8 0.11% 99.99% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::136-139 1 0.01% 100.00% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::total 7471 # Writes before turning the bus around for reads 284system.physmem.totQLat 7621074500 # Total ticks spent queuing 285system.physmem.totMemAccLat 11681818250 # Total ticks spent from burst creation until serviced by the DRAM 286system.physmem.totBusLat 1082865000 # Total ticks spent in databus transfers 287system.physmem.avgQLat 35189.40 # Average queueing delay per DRAM burst |
| 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 288system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 276system.physmem.avgMemAccLat 44797.89 # Average memory access latency per DRAM burst 277system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s | 289system.physmem.avgMemAccLat 53939.40 # Average memory access latency per DRAM burst 290system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s 291system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s 292system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s 293system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s |
| 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 294system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 282system.physmem.busUtil 2.94 # Data bus utilization in percentage 283system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 6.34 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing 287system.physmem.readRowHits 14503540 # Number of row buffer hits during reads 288system.physmem.writeRowHits 85448 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes 291system.physmem.avgGap 162718.35 # Average gap between requests 292system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined 293system.physmem.memoryStateTime::IDLE 2316452257000 # Time in different power states 294system.physmem.memoryStateTime::REF 88772580000 # Time in different power states | 295system.physmem.busUtil 0.06 # Data bus utilization in percentage 296system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 297system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 298system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing 299system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing 300system.physmem.readRowHits 183248 # Number of row buffer hits during reads 301system.physmem.writeRowHits 89836 # Number of row buffer hits during writes 302system.physmem.readRowHitRate 84.61 # Row buffer hit rate for reads 303system.physmem.writeRowHitRate 60.34 # Row buffer hit rate for writes 304system.physmem.avgGap 7693723.89 # Average gap between requests 305system.physmem.pageHitRate 74.72 # Row buffer hit rate, read and write combined 306system.physmem.memoryStateTime::IDLE 2710028687250 # Time in different power states 307system.physmem.memoryStateTime::REF 94957980000 # Time in different power states |
| 295system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 308system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 296system.physmem.memoryStateTime::ACT 253258119250 # Time in different power states | 309system.physmem.memoryStateTime::ACT 38731176500 # Time in different power states |
| 297system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 310system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 298system.physmem.actEnergy::0 3923753400 # Energy for activate commands per rank (pJ) 299system.physmem.actEnergy::1 3920570640 # Energy for activate commands per rank (pJ) 300system.physmem.preEnergy::0 2140936875 # Energy for precharge commands per rank (pJ) 301system.physmem.preEnergy::1 2139200250 # Energy for precharge commands per rank (pJ) 302system.physmem.readEnergy::0 60504077400 # Energy for read commands per rank (pJ) 303system.physmem.readEnergy::1 60482814600 # Energy for read commands per rank (pJ) 304system.physmem.writeEnergy::0 378432000 # Energy for write commands per rank (pJ) 305system.physmem.writeEnergy::1 369729360 # Energy for write commands per rank (pJ) 306system.physmem.refreshEnergy::0 173639166480 # Energy for refresh commands per rank (pJ) 307system.physmem.refreshEnergy::1 173639166480 # Energy for refresh commands per rank (pJ) 308system.physmem.actBackEnergy::0 146077789680 # Energy for active background per rank (pJ) 309system.physmem.actBackEnergy::1 145345956705 # Energy for active background per rank (pJ) 310system.physmem.preBackEnergy::0 1466951353500 # Energy for precharge background per rank (pJ) 311system.physmem.preBackEnergy::1 1467593312250 # Energy for precharge background per rank (pJ) 312system.physmem.totalEnergy::0 1853615509335 # Total energy per rank (pJ) 313system.physmem.totalEnergy::1 1853490750285 # Total energy per rank (pJ) 314system.physmem.averagePower::0 697.245591 # Core power per rank (mW) 315system.physmem.averagePower::1 697.198662 # Core power per rank (mW) 316system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory 318system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory 319system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory 320system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory 321system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 322system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory 323system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory 324system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory 325system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s) 332system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s) 333system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s) 334system.membus.trans_dist::ReadReq 16692376 # Transaction distribution 335system.membus.trans_dist::ReadResp 16692376 # Transaction distribution 336system.membus.trans_dist::WriteReq 768869 # Transaction distribution 337system.membus.trans_dist::WriteResp 768869 # Transaction distribution 338system.membus.trans_dist::Writeback 67875 # Transaction distribution 339system.membus.trans_dist::UpgradeReq 55188 # Transaction distribution 340system.membus.trans_dist::SCUpgradeReq 22300 # Transaction distribution 341system.membus.trans_dist::UpgradeResp 15674 # Transaction distribution 342system.membus.trans_dist::ReadExReq 15293 # Transaction distribution 343system.membus.trans_dist::ReadExResp 8420 # Transaction distribution 344system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384484 # Packet count per connected master and slave (bytes) 345system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) 346system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12552 # Packet count per connected master and slave (bytes) 347system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 348system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes) 349system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037240 # Packet count per connected master and slave (bytes) 350system.membus.pkt_count_system.l2c.mem_side::total 4436392 # Packet count per connected master and slave (bytes) 351system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 352system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) 353system.membus.pkt_count::total 35107240 # Packet count per connected master and slave (bytes) 354system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392912 # Cumulative packet size per connected master and slave (bytes) 355system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) 356system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25104 # Cumulative packet size per connected master and slave (bytes) 357system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 358system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes) 359system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18720580 # Cumulative packet size per connected master and slave (bytes) 360system.membus.pkt_size_system.l2c.mem_side::total 21143488 # Cumulative packet size per connected master and slave (bytes) 361system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 362system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) 363system.membus.pkt_size::total 143826880 # Cumulative packet size per connected master and slave (bytes) 364system.membus.snoops 68687 # Total snoops (count) 365system.membus.snoop_fanout::samples 327086 # Request fanout histogram | 311system.physmem.actEnergy::0 365654520 # Energy for activate commands per rank (pJ) 312system.physmem.actEnergy::1 332549280 # Energy for activate commands per rank (pJ) 313system.physmem.preEnergy::0 199513875 # Energy for precharge commands per rank (pJ) 314system.physmem.preEnergy::1 181450500 # Energy for precharge commands per rank (pJ) 315system.physmem.readEnergy::0 884239200 # Energy for read commands per rank (pJ) 316system.physmem.readEnergy::1 805030200 # Energy for read commands per rank (pJ) 317system.physmem.writeEnergy::0 499582080 # Energy for write commands per rank (pJ) 318system.physmem.writeEnergy::1 465069600 # Energy for write commands per rank (pJ) 319system.physmem.refreshEnergy::0 185737808880 # Energy for refresh commands per rank (pJ) 320system.physmem.refreshEnergy::1 185737808880 # Energy for refresh commands per rank (pJ) 321system.physmem.actBackEnergy::0 82126203345 # Energy for active background per rank (pJ) 322system.physmem.actBackEnergy::1 81336736530 # Energy for active background per rank (pJ) 323system.physmem.preBackEnergy::0 1634190168750 # Energy for precharge background per rank (pJ) 324system.physmem.preBackEnergy::1 1634882683500 # Energy for precharge background per rank (pJ) 325system.physmem.totalEnergy::0 1904003170650 # Total energy per rank (pJ) 326system.physmem.totalEnergy::1 1903741328490 # Total energy per rank (pJ) 327system.physmem.averagePower::0 669.547151 # Core power per rank (mW) 328system.physmem.averagePower::1 669.455073 # Core power per rank (mW) 329system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 330system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 331system.realview.nvmem.bytes_read::total 1280 # Number of bytes read from this memory 332system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 333system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 334system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 335system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 336system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 337system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory 338system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 339system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_read::total 450 # Total read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_inst_read::total 450 # Instruction read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 345system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::total 450 # Total bandwidth to/from this memory (bytes/s) 347system.membus.trans_dist::ReadReq 238282 # Transaction distribution 348system.membus.trans_dist::ReadResp 238282 # Transaction distribution 349system.membus.trans_dist::WriteReq 31054 # Transaction distribution 350system.membus.trans_dist::WriteResp 31054 # Transaction distribution 351system.membus.trans_dist::Writeback 112138 # Transaction distribution 352system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 353system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 354system.membus.trans_dist::UpgradeReq 80328 # Transaction distribution 355system.membus.trans_dist::SCUpgradeReq 40430 # Transaction distribution 356system.membus.trans_dist::UpgradeResp 13461 # Transaction distribution 357system.membus.trans_dist::ReadExReq 30145 # Transaction distribution 358system.membus.trans_dist::ReadExResp 13182 # Transaction distribution 359system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) 360system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) 361system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14040 # Packet count per connected master and slave (bytes) 362system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 705796 # Packet count per connected master and slave (bytes) 363system.membus.pkt_count_system.l2c.mem_side::total 827846 # Packet count per connected master and slave (bytes) 364system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72718 # Packet count per connected master and slave (bytes) 365system.membus.pkt_count_system.iocache.mem_side::total 72718 # Packet count per connected master and slave (bytes) 366system.membus.pkt_count::total 900564 # Packet count per connected master and slave (bytes) 367system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) 368system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1280 # Cumulative packet size per connected master and slave (bytes) 369system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28080 # Cumulative packet size per connected master and slave (bytes) 370system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21034796 # Cumulative packet size per connected master and slave (bytes) 371system.membus.pkt_size_system.l2c.mem_side::total 21227006 # Cumulative packet size per connected master and slave (bytes) 372system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 373system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 374system.membus.pkt_size::total 23546302 # Cumulative packet size per connected master and slave (bytes) 375system.membus.snoops 124500 # Total snoops (count) 376system.membus.snoop_fanout::samples 499399 # Request fanout histogram |
| 366system.membus.snoop_fanout::mean 1 # Request fanout histogram 367system.membus.snoop_fanout::stdev 0 # Request fanout histogram 368system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 369system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 377system.membus.snoop_fanout::mean 1 # Request fanout histogram 378system.membus.snoop_fanout::stdev 0 # Request fanout histogram 379system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 380system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 370system.membus.snoop_fanout::1 327086 100.00% 100.00% # Request fanout histogram | 381system.membus.snoop_fanout::1 499399 100.00% 100.00% # Request fanout histogram |
| 371system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 372system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 373system.membus.snoop_fanout::min_value 1 # Request fanout histogram 374system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 382system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 383system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 384system.membus.snoop_fanout::min_value 1 # Request fanout histogram 385system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 375system.membus.snoop_fanout::total 327086 # Request fanout histogram 376system.membus.reqLayer0.occupancy 1769125500 # Layer occupancy (ticks) 377system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 378system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) | 386system.membus.snoop_fanout::total 499399 # Request fanout histogram 387system.membus.reqLayer0.occupancy 87896996 # Layer occupancy (ticks) 388system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 389system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) |
| 379system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 390system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 380system.membus.reqLayer2.occupancy 11055000 # Layer occupancy (ticks) | 391system.membus.reqLayer2.occupancy 12141500 # Layer occupancy (ticks) |
| 381system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 392system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 382system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) 383system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 384system.membus.reqLayer5.occupancy 1598500 # Layer occupancy (ticks) 385system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 386system.membus.reqLayer6.occupancy 17877285000 # Layer occupancy (ticks) 387system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 388system.membus.respLayer1.occupancy 5004493562 # Layer occupancy (ticks) 389system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 390system.membus.respLayer2.occupancy 37922455685 # Layer occupancy (ticks) 391system.membus.respLayer2.utilization 1.4 # Layer utilization (%) | 393system.membus.reqLayer5.occupancy 1620346498 # Layer occupancy (ticks) 394system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 395system.membus.respLayer2.occupancy 2120331885 # Layer occupancy (ticks) 396system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 397system.membus.respLayer3.occupancy 38636884 # Layer occupancy (ticks) 398system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 392system.cpu_clk_domain.clock 500 # Clock period in ticks | 399system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 393system.l2c.tags.replacements 92119 # number of replacements 394system.l2c.tags.tagsinuse 55174.117162 # Cycle average of tags in use 395system.l2c.tags.total_refs 396231 # Total number of references to valid blocks. 396system.l2c.tags.sampled_refs 156723 # Sample count of references to valid blocks. 397system.l2c.tags.avg_refs 2.528225 # Average number of references to valid blocks. | 400system.l2c.tags.replacements 151104 # number of replacements 401system.l2c.tags.tagsinuse 64343.342453 # Cycle average of tags in use 402system.l2c.tags.total_refs 537709 # Total number of references to valid blocks. 403system.l2c.tags.sampled_refs 215892 # Sample count of references to valid blocks. 404system.l2c.tags.avg_refs 2.490639 # Average number of references to valid blocks. |
| 398system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 405system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 399system.l2c.tags.occ_blocks::writebacks 8029.027858 # Average occupied blocks per requestor 400system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.830738 # Average occupied blocks per requestor 401system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029129 # Average occupied blocks per requestor 402system.l2c.tags.occ_blocks::cpu0.inst 2503.920237 # Average occupied blocks per requestor 403system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29498.221526 # Average occupied blocks per requestor 404system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.298488 # Average occupied blocks per requestor 405system.l2c.tags.occ_blocks::cpu1.inst 2007.480710 # Average occupied blocks per requestor 406system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13123.308478 # Average occupied blocks per requestor 407system.l2c.tags.occ_percent::writebacks 0.122513 # Average percentage of cache occupancy 408system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000043 # Average percentage of cache occupancy 409system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 410system.l2c.tags.occ_percent::cpu0.inst 0.038207 # Average percentage of cache occupancy 411system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.450107 # Average percentage of cache occupancy 412system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000127 # Average percentage of cache occupancy 413system.l2c.tags.occ_percent::cpu1.inst 0.030632 # Average percentage of cache occupancy 414system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200246 # Average percentage of cache occupancy 415system.l2c.tags.occ_percent::total 0.841890 # Average percentage of cache occupancy 416system.l2c.tags.occ_task_id_blocks::1022 53228 # Occupied blocks per task id 417system.l2c.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 418system.l2c.tags.occ_task_id_blocks::1024 11362 # Occupied blocks per task id | 406system.l2c.tags.occ_blocks::writebacks 13312.566907 # Average occupied blocks per requestor 407system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.661228 # Average occupied blocks per requestor 408system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033237 # Average occupied blocks per requestor 409system.l2c.tags.occ_blocks::cpu0.inst 3627.484276 # Average occupied blocks per requestor 410system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 40388.691608 # Average occupied blocks per requestor 411system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.364745 # Average occupied blocks per requestor 412system.l2c.tags.occ_blocks::cpu1.inst 878.502916 # Average occupied blocks per requestor 413system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6044.037536 # Average occupied blocks per requestor 414system.l2c.tags.occ_percent::writebacks 0.203134 # Average percentage of cache occupancy 415system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001246 # Average percentage of cache occupancy 416system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 417system.l2c.tags.occ_percent::cpu0.inst 0.055351 # Average percentage of cache occupancy 418system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.616283 # Average percentage of cache occupancy 419system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000158 # Average percentage of cache occupancy 420system.l2c.tags.occ_percent::cpu1.inst 0.013405 # Average percentage of cache occupancy 421system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.092225 # Average percentage of cache occupancy 422system.l2c.tags.occ_percent::total 0.981801 # Average percentage of cache occupancy 423system.l2c.tags.occ_task_id_blocks::1022 46495 # Occupied blocks per task id 424system.l2c.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id 425system.l2c.tags.occ_task_id_blocks::1024 18259 # Occupied blocks per task id |
| 419system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id | 426system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id |
| 420system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id 421system.l2c.tags.age_task_id_blocks_1022::3 4763 # Occupied blocks per task id 422system.l2c.tags.age_task_id_blocks_1022::4 48327 # Occupied blocks per task id 423system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 424system.l2c.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 425system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 426system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 427system.l2c.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id 428system.l2c.tags.age_task_id_blocks_1024::3 1719 # Occupied blocks per task id 429system.l2c.tags.age_task_id_blocks_1024::4 9346 # Occupied blocks per task id 430system.l2c.tags.occ_task_id_percent::1022 0.812195 # Percentage of cache occupancy per task id 431system.l2c.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id 432system.l2c.tags.occ_task_id_percent::1024 0.173370 # Percentage of cache occupancy per task id 433system.l2c.tags.tag_accesses 5120698 # Number of tag accesses 434system.l2c.tags.data_accesses 5120698 # Number of data accesses 435system.l2c.ReadReq_hits::cpu0.dtb.walker 193 # number of ReadReq hits 436system.l2c.ReadReq_hits::cpu0.itb.walker 42 # number of ReadReq hits 437system.l2c.ReadReq_hits::cpu0.inst 14931 # number of ReadReq hits 438system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88016 # number of ReadReq hits 439system.l2c.ReadReq_hits::cpu1.dtb.walker 237 # number of ReadReq hits 440system.l2c.ReadReq_hits::cpu1.itb.walker 59 # number of ReadReq hits 441system.l2c.ReadReq_hits::cpu1.inst 19686 # number of ReadReq hits 442system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76288 # number of ReadReq hits 443system.l2c.ReadReq_hits::total 199452 # number of ReadReq hits 444system.l2c.Writeback_hits::writebacks 215010 # number of Writeback hits 445system.l2c.Writeback_hits::total 215010 # number of Writeback hits 446system.l2c.UpgradeReq_hits::cpu0.inst 3051 # number of UpgradeReq hits 447system.l2c.UpgradeReq_hits::cpu1.inst 2025 # number of UpgradeReq hits 448system.l2c.UpgradeReq_hits::total 5076 # number of UpgradeReq hits 449system.l2c.SCUpgradeReq_hits::cpu0.inst 100 # number of SCUpgradeReq hits 450system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits 451system.l2c.SCUpgradeReq_hits::total 313 # number of SCUpgradeReq hits 452system.l2c.ReadExReq_hits::cpu0.inst 2211 # number of ReadExReq hits 453system.l2c.ReadExReq_hits::cpu1.inst 2397 # number of ReadExReq hits 454system.l2c.ReadExReq_hits::total 4608 # number of ReadExReq hits 455system.l2c.demand_hits::cpu0.dtb.walker 193 # number of demand (read+write) hits 456system.l2c.demand_hits::cpu0.itb.walker 42 # number of demand (read+write) hits 457system.l2c.demand_hits::cpu0.inst 17142 # number of demand (read+write) hits 458system.l2c.demand_hits::cpu0.l2cache.prefetcher 88016 # number of demand (read+write) hits 459system.l2c.demand_hits::cpu1.dtb.walker 237 # number of demand (read+write) hits 460system.l2c.demand_hits::cpu1.itb.walker 59 # number of demand (read+write) hits 461system.l2c.demand_hits::cpu1.inst 22083 # number of demand (read+write) hits 462system.l2c.demand_hits::cpu1.l2cache.prefetcher 76288 # number of demand (read+write) hits 463system.l2c.demand_hits::total 204060 # number of demand (read+write) hits 464system.l2c.overall_hits::cpu0.dtb.walker 193 # number of overall hits 465system.l2c.overall_hits::cpu0.itb.walker 42 # number of overall hits 466system.l2c.overall_hits::cpu0.inst 17142 # number of overall hits 467system.l2c.overall_hits::cpu0.l2cache.prefetcher 88016 # number of overall hits 468system.l2c.overall_hits::cpu1.dtb.walker 237 # number of overall hits 469system.l2c.overall_hits::cpu1.itb.walker 59 # number of overall hits 470system.l2c.overall_hits::cpu1.inst 22083 # number of overall hits 471system.l2c.overall_hits::cpu1.l2cache.prefetcher 76288 # number of overall hits 472system.l2c.overall_hits::total 204060 # number of overall hits 473system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses 474system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 475system.l2c.ReadReq_misses::cpu0.inst 4222 # number of ReadReq misses 476system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq misses | 427system.l2c.tags.age_task_id_blocks_1022::2 432 # Occupied blocks per task id 428system.l2c.tags.age_task_id_blocks_1022::3 6889 # Occupied blocks per task id 429system.l2c.tags.age_task_id_blocks_1022::4 39173 # Occupied blocks per task id 430system.l2c.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id 431system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 432system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id 433system.l2c.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id 434system.l2c.tags.age_task_id_blocks_1024::3 2341 # Occupied blocks per task id 435system.l2c.tags.age_task_id_blocks_1024::4 15618 # Occupied blocks per task id 436system.l2c.tags.occ_task_id_percent::1022 0.709457 # Percentage of cache occupancy per task id 437system.l2c.tags.occ_task_id_percent::1023 0.000519 # Percentage of cache occupancy per task id 438system.l2c.tags.occ_task_id_percent::1024 0.278610 # Percentage of cache occupancy per task id 439system.l2c.tags.tag_accesses 6702696 # Number of tag accesses 440system.l2c.tags.data_accesses 6702696 # Number of data accesses 441system.l2c.ReadReq_hits::cpu0.dtb.walker 575 # number of ReadReq hits 442system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits 443system.l2c.ReadReq_hits::cpu0.inst 36632 # number of ReadReq hits 444system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 209337 # number of ReadReq hits 445system.l2c.ReadReq_hits::cpu1.dtb.walker 139 # number of ReadReq hits 446system.l2c.ReadReq_hits::cpu1.itb.walker 45 # number of ReadReq hits 447system.l2c.ReadReq_hits::cpu1.inst 12148 # number of ReadReq hits 448system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 48809 # number of ReadReq hits 449system.l2c.ReadReq_hits::total 307807 # number of ReadReq hits 450system.l2c.Writeback_hits::writebacks 253703 # number of Writeback hits 451system.l2c.Writeback_hits::total 253703 # number of Writeback hits 452system.l2c.UpgradeReq_hits::cpu0.inst 11935 # number of UpgradeReq hits 453system.l2c.UpgradeReq_hits::cpu1.inst 1029 # number of UpgradeReq hits 454system.l2c.UpgradeReq_hits::total 12964 # number of UpgradeReq hits 455system.l2c.SCUpgradeReq_hits::cpu0.inst 208 # number of SCUpgradeReq hits 456system.l2c.SCUpgradeReq_hits::cpu1.inst 174 # number of SCUpgradeReq hits 457system.l2c.SCUpgradeReq_hits::total 382 # number of SCUpgradeReq hits 458system.l2c.ReadExReq_hits::cpu0.inst 3683 # number of ReadExReq hits 459system.l2c.ReadExReq_hits::cpu1.inst 1200 # number of ReadExReq hits 460system.l2c.ReadExReq_hits::total 4883 # number of ReadExReq hits 461system.l2c.demand_hits::cpu0.dtb.walker 575 # number of demand (read+write) hits 462system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits 463system.l2c.demand_hits::cpu0.inst 40315 # number of demand (read+write) hits 464system.l2c.demand_hits::cpu0.l2cache.prefetcher 209337 # number of demand (read+write) hits 465system.l2c.demand_hits::cpu1.dtb.walker 139 # number of demand (read+write) hits 466system.l2c.demand_hits::cpu1.itb.walker 45 # number of demand (read+write) hits 467system.l2c.demand_hits::cpu1.inst 13348 # number of demand (read+write) hits 468system.l2c.demand_hits::cpu1.l2cache.prefetcher 48809 # number of demand (read+write) hits 469system.l2c.demand_hits::total 312690 # number of demand (read+write) hits 470system.l2c.overall_hits::cpu0.dtb.walker 575 # number of overall hits 471system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits 472system.l2c.overall_hits::cpu0.inst 40315 # number of overall hits 473system.l2c.overall_hits::cpu0.l2cache.prefetcher 209337 # number of overall hits 474system.l2c.overall_hits::cpu1.dtb.walker 139 # number of overall hits 475system.l2c.overall_hits::cpu1.itb.walker 45 # number of overall hits 476system.l2c.overall_hits::cpu1.inst 13348 # number of overall hits 477system.l2c.overall_hits::cpu1.l2cache.prefetcher 48809 # number of overall hits 478system.l2c.overall_hits::total 312690 # number of overall hits 479system.l2c.ReadReq_misses::cpu0.dtb.walker 160 # number of ReadReq misses 480system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses 481system.l2c.ReadReq_misses::cpu0.inst 11021 # number of ReadReq misses 482system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 167331 # number of ReadReq misses |
| 477system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses | 483system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses |
| 478system.l2c.ReadReq_misses::cpu1.inst 3178 # number of ReadReq misses 479system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80451 # number of ReadReq misses 480system.l2c.ReadReq_misses::total 166440 # number of ReadReq misses 481system.l2c.UpgradeReq_misses::cpu0.inst 7948 # number of UpgradeReq misses 482system.l2c.UpgradeReq_misses::cpu1.inst 5460 # number of UpgradeReq misses 483system.l2c.UpgradeReq_misses::total 13408 # number of UpgradeReq misses 484system.l2c.SCUpgradeReq_misses::cpu0.inst 1046 # number of SCUpgradeReq misses 485system.l2c.SCUpgradeReq_misses::cpu1.inst 1101 # number of SCUpgradeReq misses 486system.l2c.SCUpgradeReq_misses::total 2147 # number of SCUpgradeReq misses 487system.l2c.ReadExReq_misses::cpu0.inst 4019 # number of ReadExReq misses 488system.l2c.ReadExReq_misses::cpu1.inst 4520 # number of ReadExReq misses 489system.l2c.ReadExReq_misses::total 8539 # number of ReadExReq misses 490system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses 491system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 492system.l2c.demand_misses::cpu0.inst 8241 # number of demand (read+write) misses 493system.l2c.demand_misses::cpu0.l2cache.prefetcher 78569 # number of demand (read+write) misses | 484system.l2c.ReadReq_misses::cpu1.inst 2011 # number of ReadReq misses 485system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 19340 # number of ReadReq misses 486system.l2c.ReadReq_misses::total 199878 # number of ReadReq misses 487system.l2c.UpgradeReq_misses::cpu0.inst 8877 # number of UpgradeReq misses 488system.l2c.UpgradeReq_misses::cpu1.inst 2752 # number of UpgradeReq misses 489system.l2c.UpgradeReq_misses::total 11629 # number of UpgradeReq misses 490system.l2c.SCUpgradeReq_misses::cpu0.inst 464 # number of SCUpgradeReq misses 491system.l2c.SCUpgradeReq_misses::cpu1.inst 1248 # number of SCUpgradeReq misses 492system.l2c.SCUpgradeReq_misses::total 1712 # number of SCUpgradeReq misses 493system.l2c.ReadExReq_misses::cpu0.inst 6943 # number of ReadExReq misses 494system.l2c.ReadExReq_misses::cpu1.inst 6359 # number of ReadExReq misses 495system.l2c.ReadExReq_misses::total 13302 # number of ReadExReq misses 496system.l2c.demand_misses::cpu0.dtb.walker 160 # number of demand (read+write) misses 497system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 498system.l2c.demand_misses::cpu0.inst 17964 # number of demand (read+write) misses 499system.l2c.demand_misses::cpu0.l2cache.prefetcher 167331 # number of demand (read+write) misses |
| 494system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses | 500system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses |
| 495system.l2c.demand_misses::cpu1.inst 7698 # number of demand (read+write) misses 496system.l2c.demand_misses::cpu1.l2cache.prefetcher 80451 # number of demand (read+write) misses 497system.l2c.demand_misses::total 174979 # number of demand (read+write) misses 498system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses 499system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 500system.l2c.overall_misses::cpu0.inst 8241 # number of overall misses 501system.l2c.overall_misses::cpu0.l2cache.prefetcher 78569 # number of overall misses | 501system.l2c.demand_misses::cpu1.inst 8370 # number of demand (read+write) misses 502system.l2c.demand_misses::cpu1.l2cache.prefetcher 19340 # number of demand (read+write) misses 503system.l2c.demand_misses::total 213180 # number of demand (read+write) misses 504system.l2c.overall_misses::cpu0.dtb.walker 160 # number of overall misses 505system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 506system.l2c.overall_misses::cpu0.inst 17964 # number of overall misses 507system.l2c.overall_misses::cpu0.l2cache.prefetcher 167331 # number of overall misses |
| 502system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses | 508system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses |
| 503system.l2c.overall_misses::cpu1.inst 7698 # number of overall misses 504system.l2c.overall_misses::cpu1.l2cache.prefetcher 80451 # number of overall misses 505system.l2c.overall_misses::total 174979 # number of overall misses 506system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 256500 # number of ReadReq miss cycles 507system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles 508system.l2c.ReadReq_miss_latency::cpu0.inst 326360000 # number of ReadReq miss cycles 509system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of ReadReq miss cycles 510system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1107250 # number of ReadReq miss cycles 511system.l2c.ReadReq_miss_latency::cpu1.inst 255357749 # number of ReadReq miss cycles 512system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of ReadReq miss cycles 513system.l2c.ReadReq_miss_latency::total 16477212323 # number of ReadReq miss cycles 514system.l2c.UpgradeReq_miss_latency::cpu0.inst 13294932 # number of UpgradeReq miss cycles 515system.l2c.UpgradeReq_miss_latency::cpu1.inst 6165736 # number of UpgradeReq miss cycles 516system.l2c.UpgradeReq_miss_latency::total 19460668 # number of UpgradeReq miss cycles 517system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 621976 # number of SCUpgradeReq miss cycles 518system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 4504808 # number of SCUpgradeReq miss cycles 519system.l2c.SCUpgradeReq_miss_latency::total 5126784 # number of SCUpgradeReq miss cycles 520system.l2c.ReadExReq_miss_latency::cpu0.inst 291276419 # number of ReadExReq miss cycles 521system.l2c.ReadExReq_miss_latency::cpu1.inst 332394712 # number of ReadExReq miss cycles 522system.l2c.ReadExReq_miss_latency::total 623671131 # number of ReadExReq miss cycles 523system.l2c.demand_miss_latency::cpu0.dtb.walker 256500 # number of demand (read+write) miss cycles 524system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles 525system.l2c.demand_miss_latency::cpu0.inst 617636419 # number of demand (read+write) miss cycles 526system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of demand (read+write) miss cycles 527system.l2c.demand_miss_latency::cpu1.dtb.walker 1107250 # number of demand (read+write) miss cycles 528system.l2c.demand_miss_latency::cpu1.inst 587752461 # number of demand (read+write) miss cycles 529system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of demand (read+write) miss cycles 530system.l2c.demand_miss_latency::total 17100883454 # number of demand (read+write) miss cycles 531system.l2c.overall_miss_latency::cpu0.dtb.walker 256500 # number of overall miss cycles 532system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles 533system.l2c.overall_miss_latency::cpu0.inst 617636419 # number of overall miss cycles 534system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 7141877944 # number of overall miss cycles 535system.l2c.overall_miss_latency::cpu1.dtb.walker 1107250 # number of overall miss cycles 536system.l2c.overall_miss_latency::cpu1.inst 587752461 # number of overall miss cycles 537system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 8752102880 # number of overall miss cycles 538system.l2c.overall_miss_latency::total 17100883454 # number of overall miss cycles 539system.l2c.ReadReq_accesses::cpu0.dtb.walker 197 # number of ReadReq accesses(hits+misses) 540system.l2c.ReadReq_accesses::cpu0.itb.walker 44 # number of ReadReq accesses(hits+misses) 541system.l2c.ReadReq_accesses::cpu0.inst 19153 # number of ReadReq accesses(hits+misses) 542system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 166585 # number of ReadReq accesses(hits+misses) 543system.l2c.ReadReq_accesses::cpu1.dtb.walker 251 # number of ReadReq accesses(hits+misses) 544system.l2c.ReadReq_accesses::cpu1.itb.walker 59 # number of ReadReq accesses(hits+misses) 545system.l2c.ReadReq_accesses::cpu1.inst 22864 # number of ReadReq accesses(hits+misses) 546system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 156739 # number of ReadReq accesses(hits+misses) 547system.l2c.ReadReq_accesses::total 365892 # number of ReadReq accesses(hits+misses) 548system.l2c.Writeback_accesses::writebacks 215010 # number of Writeback accesses(hits+misses) 549system.l2c.Writeback_accesses::total 215010 # number of Writeback accesses(hits+misses) 550system.l2c.UpgradeReq_accesses::cpu0.inst 10999 # number of UpgradeReq accesses(hits+misses) 551system.l2c.UpgradeReq_accesses::cpu1.inst 7485 # number of UpgradeReq accesses(hits+misses) 552system.l2c.UpgradeReq_accesses::total 18484 # number of UpgradeReq accesses(hits+misses) 553system.l2c.SCUpgradeReq_accesses::cpu0.inst 1146 # number of SCUpgradeReq accesses(hits+misses) 554system.l2c.SCUpgradeReq_accesses::cpu1.inst 1314 # number of SCUpgradeReq accesses(hits+misses) 555system.l2c.SCUpgradeReq_accesses::total 2460 # number of SCUpgradeReq accesses(hits+misses) 556system.l2c.ReadExReq_accesses::cpu0.inst 6230 # number of ReadExReq accesses(hits+misses) 557system.l2c.ReadExReq_accesses::cpu1.inst 6917 # number of ReadExReq accesses(hits+misses) 558system.l2c.ReadExReq_accesses::total 13147 # number of ReadExReq accesses(hits+misses) 559system.l2c.demand_accesses::cpu0.dtb.walker 197 # number of demand (read+write) accesses 560system.l2c.demand_accesses::cpu0.itb.walker 44 # number of demand (read+write) accesses 561system.l2c.demand_accesses::cpu0.inst 25383 # number of demand (read+write) accesses 562system.l2c.demand_accesses::cpu0.l2cache.prefetcher 166585 # number of demand (read+write) accesses 563system.l2c.demand_accesses::cpu1.dtb.walker 251 # number of demand (read+write) accesses 564system.l2c.demand_accesses::cpu1.itb.walker 59 # number of demand (read+write) accesses 565system.l2c.demand_accesses::cpu1.inst 29781 # number of demand (read+write) accesses 566system.l2c.demand_accesses::cpu1.l2cache.prefetcher 156739 # number of demand (read+write) accesses 567system.l2c.demand_accesses::total 379039 # number of demand (read+write) accesses 568system.l2c.overall_accesses::cpu0.dtb.walker 197 # number of overall (read+write) accesses 569system.l2c.overall_accesses::cpu0.itb.walker 44 # number of overall (read+write) accesses 570system.l2c.overall_accesses::cpu0.inst 25383 # number of overall (read+write) accesses 571system.l2c.overall_accesses::cpu0.l2cache.prefetcher 166585 # number of overall (read+write) accesses 572system.l2c.overall_accesses::cpu1.dtb.walker 251 # number of overall (read+write) accesses 573system.l2c.overall_accesses::cpu1.itb.walker 59 # number of overall (read+write) accesses 574system.l2c.overall_accesses::cpu1.inst 29781 # number of overall (read+write) accesses 575system.l2c.overall_accesses::cpu1.l2cache.prefetcher 156739 # number of overall (read+write) accesses 576system.l2c.overall_accesses::total 379039 # number of overall (read+write) accesses 577system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for ReadReq accesses 578system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.045455 # miss rate for ReadReq accesses 579system.l2c.ReadReq_miss_rate::cpu0.inst 0.220435 # miss rate for ReadReq accesses 580system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for ReadReq accesses 581system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for ReadReq accesses 582system.l2c.ReadReq_miss_rate::cpu1.inst 0.138996 # miss rate for ReadReq accesses 583system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for ReadReq accesses 584system.l2c.ReadReq_miss_rate::total 0.454888 # miss rate for ReadReq accesses 585system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.722611 # miss rate for UpgradeReq accesses 586system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.729459 # miss rate for UpgradeReq accesses 587system.l2c.UpgradeReq_miss_rate::total 0.725384 # miss rate for UpgradeReq accesses 588system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.912740 # miss rate for SCUpgradeReq accesses 589system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.837900 # miss rate for SCUpgradeReq accesses 590system.l2c.SCUpgradeReq_miss_rate::total 0.872764 # miss rate for SCUpgradeReq accesses 591system.l2c.ReadExReq_miss_rate::cpu0.inst 0.645104 # miss rate for ReadExReq accesses 592system.l2c.ReadExReq_miss_rate::cpu1.inst 0.653462 # miss rate for ReadExReq accesses 593system.l2c.ReadExReq_miss_rate::total 0.649502 # miss rate for ReadExReq accesses 594system.l2c.demand_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for demand accesses 595system.l2c.demand_miss_rate::cpu0.itb.walker 0.045455 # miss rate for demand accesses 596system.l2c.demand_miss_rate::cpu0.inst 0.324666 # miss rate for demand accesses 597system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for demand accesses 598system.l2c.demand_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for demand accesses 599system.l2c.demand_miss_rate::cpu1.inst 0.258487 # miss rate for demand accesses 600system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for demand accesses 601system.l2c.demand_miss_rate::total 0.461639 # miss rate for demand accesses 602system.l2c.overall_miss_rate::cpu0.dtb.walker 0.020305 # miss rate for overall accesses 603system.l2c.overall_miss_rate::cpu0.itb.walker 0.045455 # miss rate for overall accesses 604system.l2c.overall_miss_rate::cpu0.inst 0.324666 # miss rate for overall accesses 605system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.471645 # miss rate for overall accesses 606system.l2c.overall_miss_rate::cpu1.dtb.walker 0.055777 # miss rate for overall accesses 607system.l2c.overall_miss_rate::cpu1.inst 0.258487 # miss rate for overall accesses 608system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.513280 # miss rate for overall accesses 609system.l2c.overall_miss_rate::total 0.461639 # miss rate for overall accesses 610system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 64125 # average ReadReq miss latency | 509system.l2c.overall_misses::cpu1.inst 8370 # number of overall misses 510system.l2c.overall_misses::cpu1.l2cache.prefetcher 19340 # number of overall misses 511system.l2c.overall_misses::total 213180 # number of overall misses 512system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 13245499 # number of ReadReq miss cycles 513system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles 514system.l2c.ReadReq_miss_latency::cpu0.inst 927632991 # number of ReadReq miss cycles 515system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of ReadReq miss cycles 516system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1117750 # number of ReadReq miss cycles 517system.l2c.ReadReq_miss_latency::cpu1.inst 171510999 # number of ReadReq miss cycles 518system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of ReadReq miss cycles 519system.l2c.ReadReq_miss_latency::total 21228443106 # number of ReadReq miss cycles 520system.l2c.UpgradeReq_miss_latency::cpu0.inst 10247078 # number of UpgradeReq miss cycles 521system.l2c.UpgradeReq_miss_latency::cpu1.inst 3439358 # number of UpgradeReq miss cycles 522system.l2c.UpgradeReq_miss_latency::total 13686436 # number of UpgradeReq miss cycles 523system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1071455 # number of SCUpgradeReq miss cycles 524system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1047955 # number of SCUpgradeReq miss cycles 525system.l2c.SCUpgradeReq_miss_latency::total 2119410 # number of SCUpgradeReq miss cycles 526system.l2c.ReadExReq_miss_latency::cpu0.inst 585218901 # number of ReadExReq miss cycles 527system.l2c.ReadExReq_miss_latency::cpu1.inst 465754979 # number of ReadExReq miss cycles 528system.l2c.ReadExReq_miss_latency::total 1050973880 # number of ReadExReq miss cycles 529system.l2c.demand_miss_latency::cpu0.dtb.walker 13245499 # number of demand (read+write) miss cycles 530system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles 531system.l2c.demand_miss_latency::cpu0.inst 1512851892 # number of demand (read+write) miss cycles 532system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of demand (read+write) miss cycles 533system.l2c.demand_miss_latency::cpu1.dtb.walker 1117750 # number of demand (read+write) miss cycles 534system.l2c.demand_miss_latency::cpu1.inst 637265978 # number of demand (read+write) miss cycles 535system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of demand (read+write) miss cycles 536system.l2c.demand_miss_latency::total 22279416986 # number of demand (read+write) miss cycles 537system.l2c.overall_miss_latency::cpu0.dtb.walker 13245499 # number of overall miss cycles 538system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles 539system.l2c.overall_miss_latency::cpu0.inst 1512851892 # number of overall miss cycles 540system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 17938370695 # number of overall miss cycles 541system.l2c.overall_miss_latency::cpu1.dtb.walker 1117750 # number of overall miss cycles 542system.l2c.overall_miss_latency::cpu1.inst 637265978 # number of overall miss cycles 543system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2176490172 # number of overall miss cycles 544system.l2c.overall_miss_latency::total 22279416986 # number of overall miss cycles 545system.l2c.ReadReq_accesses::cpu0.dtb.walker 735 # number of ReadReq accesses(hits+misses) 546system.l2c.ReadReq_accesses::cpu0.itb.walker 123 # number of ReadReq accesses(hits+misses) 547system.l2c.ReadReq_accesses::cpu0.inst 47653 # number of ReadReq accesses(hits+misses) 548system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 376668 # number of ReadReq accesses(hits+misses) 549system.l2c.ReadReq_accesses::cpu1.dtb.walker 153 # number of ReadReq accesses(hits+misses) 550system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses) 551system.l2c.ReadReq_accesses::cpu1.inst 14159 # number of ReadReq accesses(hits+misses) 552system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68149 # number of ReadReq accesses(hits+misses) 553system.l2c.ReadReq_accesses::total 507685 # number of ReadReq accesses(hits+misses) 554system.l2c.Writeback_accesses::writebacks 253703 # number of Writeback accesses(hits+misses) 555system.l2c.Writeback_accesses::total 253703 # number of Writeback accesses(hits+misses) 556system.l2c.UpgradeReq_accesses::cpu0.inst 20812 # number of UpgradeReq accesses(hits+misses) 557system.l2c.UpgradeReq_accesses::cpu1.inst 3781 # number of UpgradeReq accesses(hits+misses) 558system.l2c.UpgradeReq_accesses::total 24593 # number of UpgradeReq accesses(hits+misses) 559system.l2c.SCUpgradeReq_accesses::cpu0.inst 672 # number of SCUpgradeReq accesses(hits+misses) 560system.l2c.SCUpgradeReq_accesses::cpu1.inst 1422 # number of SCUpgradeReq accesses(hits+misses) 561system.l2c.SCUpgradeReq_accesses::total 2094 # number of SCUpgradeReq accesses(hits+misses) 562system.l2c.ReadExReq_accesses::cpu0.inst 10626 # number of ReadExReq accesses(hits+misses) 563system.l2c.ReadExReq_accesses::cpu1.inst 7559 # number of ReadExReq accesses(hits+misses) 564system.l2c.ReadExReq_accesses::total 18185 # number of ReadExReq accesses(hits+misses) 565system.l2c.demand_accesses::cpu0.dtb.walker 735 # number of demand (read+write) accesses 566system.l2c.demand_accesses::cpu0.itb.walker 123 # number of demand (read+write) accesses 567system.l2c.demand_accesses::cpu0.inst 58279 # number of demand (read+write) accesses 568system.l2c.demand_accesses::cpu0.l2cache.prefetcher 376668 # number of demand (read+write) accesses 569system.l2c.demand_accesses::cpu1.dtb.walker 153 # number of demand (read+write) accesses 570system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses 571system.l2c.demand_accesses::cpu1.inst 21718 # number of demand (read+write) accesses 572system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68149 # number of demand (read+write) accesses 573system.l2c.demand_accesses::total 525870 # number of demand (read+write) accesses 574system.l2c.overall_accesses::cpu0.dtb.walker 735 # number of overall (read+write) accesses 575system.l2c.overall_accesses::cpu0.itb.walker 123 # number of overall (read+write) accesses 576system.l2c.overall_accesses::cpu0.inst 58279 # number of overall (read+write) accesses 577system.l2c.overall_accesses::cpu0.l2cache.prefetcher 376668 # number of overall (read+write) accesses 578system.l2c.overall_accesses::cpu1.dtb.walker 153 # number of overall (read+write) accesses 579system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses 580system.l2c.overall_accesses::cpu1.inst 21718 # number of overall (read+write) accesses 581system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68149 # number of overall (read+write) accesses 582system.l2c.overall_accesses::total 525870 # number of overall (read+write) accesses 583system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for ReadReq accesses 584system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008130 # miss rate for ReadReq accesses 585system.l2c.ReadReq_miss_rate::cpu0.inst 0.231276 # miss rate for ReadReq accesses 586system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for ReadReq accesses 587system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for ReadReq accesses 588system.l2c.ReadReq_miss_rate::cpu1.inst 0.142030 # miss rate for ReadReq accesses 589system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for ReadReq accesses 590system.l2c.ReadReq_miss_rate::total 0.393705 # miss rate for ReadReq accesses 591system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.426533 # miss rate for UpgradeReq accesses 592system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.727850 # miss rate for UpgradeReq accesses 593system.l2c.UpgradeReq_miss_rate::total 0.472858 # miss rate for UpgradeReq accesses 594system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.690476 # miss rate for SCUpgradeReq accesses 595system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.877637 # miss rate for SCUpgradeReq accesses 596system.l2c.SCUpgradeReq_miss_rate::total 0.817574 # miss rate for SCUpgradeReq accesses 597system.l2c.ReadExReq_miss_rate::cpu0.inst 0.653397 # miss rate for ReadExReq accesses 598system.l2c.ReadExReq_miss_rate::cpu1.inst 0.841249 # miss rate for ReadExReq accesses 599system.l2c.ReadExReq_miss_rate::total 0.731482 # miss rate for ReadExReq accesses 600system.l2c.demand_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for demand accesses 601system.l2c.demand_miss_rate::cpu0.itb.walker 0.008130 # miss rate for demand accesses 602system.l2c.demand_miss_rate::cpu0.inst 0.308241 # miss rate for demand accesses 603system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for demand accesses 604system.l2c.demand_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for demand accesses 605system.l2c.demand_miss_rate::cpu1.inst 0.385395 # miss rate for demand accesses 606system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for demand accesses 607system.l2c.demand_miss_rate::total 0.405385 # miss rate for demand accesses 608system.l2c.overall_miss_rate::cpu0.dtb.walker 0.217687 # miss rate for overall accesses 609system.l2c.overall_miss_rate::cpu0.itb.walker 0.008130 # miss rate for overall accesses 610system.l2c.overall_miss_rate::cpu0.inst 0.308241 # miss rate for overall accesses 611system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.444240 # miss rate for overall accesses 612system.l2c.overall_miss_rate::cpu1.dtb.walker 0.091503 # miss rate for overall accesses 613system.l2c.overall_miss_rate::cpu1.inst 0.385395 # miss rate for overall accesses 614system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.283790 # miss rate for overall accesses 615system.l2c.overall_miss_rate::total 0.405385 # miss rate for overall accesses 616system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average ReadReq miss latency |
| 611system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency | 617system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency |
| 612system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77299.857887 # average ReadReq miss latency 613system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average ReadReq miss latency 614system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average ReadReq miss latency 615system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80351.714600 # average ReadReq miss latency 616system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average ReadReq miss latency 617system.l2c.ReadReq_avg_miss_latency::total 98997.911097 # average ReadReq miss latency 618system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1672.739305 # average UpgradeReq miss latency 619system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1129.255678 # average UpgradeReq miss latency 620system.l2c.UpgradeReq_avg_miss_latency::total 1451.422136 # average UpgradeReq miss latency 621system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 594.623327 # average SCUpgradeReq miss latency 622system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 4091.560400 # average SCUpgradeReq miss latency 623system.l2c.SCUpgradeReq_avg_miss_latency::total 2387.882627 # average SCUpgradeReq miss latency 624system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 72474.849216 # average ReadExReq miss latency 625system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73538.653097 # average ReadExReq miss latency 626system.l2c.ReadExReq_avg_miss_latency::total 73037.958894 # average ReadExReq miss latency 627system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 64125 # average overall miss latency | 618system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84169.584520 # average ReadReq miss latency 619system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average ReadReq miss latency 620system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average ReadReq miss latency 621system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85286.424167 # average ReadReq miss latency 622system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average ReadReq miss latency 623system.l2c.ReadReq_avg_miss_latency::total 106207.001801 # average ReadReq miss latency 624system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1154.340205 # average UpgradeReq miss latency 625system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1249.766715 # average UpgradeReq miss latency 626system.l2c.UpgradeReq_avg_miss_latency::total 1176.922865 # average UpgradeReq miss latency 627system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2309.170259 # average SCUpgradeReq miss latency 628system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 839.707532 # average SCUpgradeReq miss latency 629system.l2c.SCUpgradeReq_avg_miss_latency::total 1237.973131 # average SCUpgradeReq miss latency 630system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84289.053867 # average ReadExReq miss latency 631system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73243.431200 # average ReadExReq miss latency 632system.l2c.ReadExReq_avg_miss_latency::total 79008.711472 # average ReadExReq miss latency 633system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average overall miss latency |
| 628system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 634system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 629system.l2c.demand_avg_miss_latency::cpu0.inst 74946.780609 # average overall miss latency 630system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average overall miss latency 631system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average overall miss latency 632system.l2c.demand_avg_miss_latency::cpu1.inst 76351.319953 # average overall miss latency 633system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average overall miss latency 634system.l2c.demand_avg_miss_latency::total 97731.061750 # average overall miss latency 635system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 64125 # average overall miss latency | 635system.l2c.demand_avg_miss_latency::cpu0.inst 84215.758851 # average overall miss latency 636system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average overall miss latency 637system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average overall miss latency 638system.l2c.demand_avg_miss_latency::cpu1.inst 76136.914934 # average overall miss latency 639system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average overall miss latency 640system.l2c.demand_avg_miss_latency::total 104509.883601 # average overall miss latency 641system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 82784.368750 # average overall miss latency |
| 636system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 642system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 637system.l2c.overall_avg_miss_latency::cpu0.inst 74946.780609 # average overall miss latency 638system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 90899.437997 # average overall miss latency 639system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79089.285714 # average overall miss latency 640system.l2c.overall_avg_miss_latency::cpu1.inst 76351.319953 # average overall miss latency 641system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 108787.993686 # average overall miss latency 642system.l2c.overall_avg_miss_latency::total 97731.061750 # average overall miss latency 643system.l2c.blocked_cycles::no_mshrs 255 # number of cycles access was blocked | 643system.l2c.overall_avg_miss_latency::cpu0.inst 84215.758851 # average overall miss latency 644system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107202.913357 # average overall miss latency 645system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79839.285714 # average overall miss latency 646system.l2c.overall_avg_miss_latency::cpu1.inst 76136.914934 # average overall miss latency 647system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112538.271562 # average overall miss latency 648system.l2c.overall_avg_miss_latency::total 104509.883601 # average overall miss latency 649system.l2c.blocked_cycles::no_mshrs 27 # number of cycles access was blocked |
| 644system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 650system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 645system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked | 651system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked |
| 646system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 652system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 647system.l2c.avg_blocked_cycles::no_mshrs 42.500000 # average number of cycles each access was blocked | 653system.l2c.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked |
| 648system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 649system.l2c.fast_writes 0 # number of fast writes performed 650system.l2c.cache_copies 0 # number of cache copies performed | 654system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.l2c.fast_writes 0 # number of fast writes performed 656system.l2c.cache_copies 0 # number of cache copies performed |
| 651system.l2c.writebacks::writebacks 67875 # number of writebacks 652system.l2c.writebacks::total 67875 # number of writebacks 653system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits 654system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 8 # number of ReadReq MSHR hits 655system.l2c.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits 656system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 657system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 8 # number of demand (read+write) MSHR hits 658system.l2c.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits 659system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 660system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 8 # number of overall MSHR hits 661system.l2c.overall_mshr_hits::total 10 # number of overall MSHR hits 662system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses 663system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 664system.l2c.ReadReq_mshr_misses::cpu0.inst 4222 # number of ReadReq MSHR misses 665system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq MSHR misses | 657system.l2c.writebacks::writebacks 112138 # number of writebacks 658system.l2c.writebacks::total 112138 # number of writebacks 659system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 660system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits 661system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 662system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 663system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 664system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 665system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 666system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits 667system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits 668system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 160 # number of ReadReq MSHR misses 669system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses 670system.l2c.ReadReq_mshr_misses::cpu0.inst 11020 # number of ReadReq MSHR misses 671system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of ReadReq MSHR misses |
| 666system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses | 672system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses |
| 667system.l2c.ReadReq_mshr_misses::cpu1.inst 3176 # number of ReadReq MSHR misses 668system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of ReadReq MSHR misses 669system.l2c.ReadReq_mshr_misses::total 166430 # number of ReadReq MSHR misses 670system.l2c.UpgradeReq_mshr_misses::cpu0.inst 7948 # number of UpgradeReq MSHR misses 671system.l2c.UpgradeReq_mshr_misses::cpu1.inst 5460 # number of UpgradeReq MSHR misses 672system.l2c.UpgradeReq_mshr_misses::total 13408 # number of UpgradeReq MSHR misses 673system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 1046 # number of SCUpgradeReq MSHR misses 674system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1101 # number of SCUpgradeReq MSHR misses 675system.l2c.SCUpgradeReq_mshr_misses::total 2147 # number of SCUpgradeReq MSHR misses 676system.l2c.ReadExReq_mshr_misses::cpu0.inst 4019 # number of ReadExReq MSHR misses 677system.l2c.ReadExReq_mshr_misses::cpu1.inst 4520 # number of ReadExReq MSHR misses 678system.l2c.ReadExReq_mshr_misses::total 8539 # number of ReadExReq MSHR misses 679system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses 680system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 681system.l2c.demand_mshr_misses::cpu0.inst 8241 # number of demand (read+write) MSHR misses 682system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of demand (read+write) MSHR misses | 673system.l2c.ReadReq_mshr_misses::cpu1.inst 2011 # number of ReadReq MSHR misses 674system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of ReadReq MSHR misses 675system.l2c.ReadReq_mshr_misses::total 199876 # number of ReadReq MSHR misses 676system.l2c.UpgradeReq_mshr_misses::cpu0.inst 8877 # number of UpgradeReq MSHR misses 677system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2752 # number of UpgradeReq MSHR misses 678system.l2c.UpgradeReq_mshr_misses::total 11629 # number of UpgradeReq MSHR misses 679system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 464 # number of SCUpgradeReq MSHR misses 680system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1248 # number of SCUpgradeReq MSHR misses 681system.l2c.SCUpgradeReq_mshr_misses::total 1712 # number of SCUpgradeReq MSHR misses 682system.l2c.ReadExReq_mshr_misses::cpu0.inst 6943 # number of ReadExReq MSHR misses 683system.l2c.ReadExReq_mshr_misses::cpu1.inst 6359 # number of ReadExReq MSHR misses 684system.l2c.ReadExReq_mshr_misses::total 13302 # number of ReadExReq MSHR misses 685system.l2c.demand_mshr_misses::cpu0.dtb.walker 160 # number of demand (read+write) MSHR misses 686system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 687system.l2c.demand_mshr_misses::cpu0.inst 17963 # number of demand (read+write) MSHR misses 688system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of demand (read+write) MSHR misses |
| 683system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses | 689system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses |
| 684system.l2c.demand_mshr_misses::cpu1.inst 7696 # number of demand (read+write) MSHR misses 685system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of demand (read+write) MSHR misses 686system.l2c.demand_mshr_misses::total 174969 # number of demand (read+write) MSHR misses 687system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses 688system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 689system.l2c.overall_mshr_misses::cpu0.inst 8241 # number of overall MSHR misses 690system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 78569 # number of overall MSHR misses | 690system.l2c.demand_mshr_misses::cpu1.inst 8370 # number of demand (read+write) MSHR misses 691system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of demand (read+write) MSHR misses 692system.l2c.demand_mshr_misses::total 213178 # number of demand (read+write) MSHR misses 693system.l2c.overall_mshr_misses::cpu0.dtb.walker 160 # number of overall MSHR misses 694system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 695system.l2c.overall_mshr_misses::cpu0.inst 17963 # number of overall MSHR misses 696system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 167330 # number of overall MSHR misses |
| 691system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses | 697system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses |
| 692system.l2c.overall_mshr_misses::cpu1.inst 7696 # number of overall MSHR misses 693system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 80443 # number of overall MSHR misses 694system.l2c.overall_mshr_misses::total 174969 # number of overall MSHR misses 695system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 207500 # number of ReadReq MSHR miss cycles 696system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles 697system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 273765000 # number of ReadReq MSHR miss cycles 698system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of ReadReq MSHR miss cycles 699system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 936250 # number of ReadReq MSHR miss cycles 700system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 215773749 # number of ReadReq MSHR miss cycles 701system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of ReadReq MSHR miss cycles 702system.l2c.ReadReq_mshr_miss_latency::total 14418655831 # number of ReadReq MSHR miss cycles 703system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 80020888 # number of UpgradeReq MSHR miss cycles 704system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 54949416 # number of UpgradeReq MSHR miss cycles 705system.l2c.UpgradeReq_mshr_miss_latency::total 134970304 # number of UpgradeReq MSHR miss cycles 706system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 10533533 # number of SCUpgradeReq MSHR miss cycles 707system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 11044096 # number of SCUpgradeReq MSHR miss cycles 708system.l2c.SCUpgradeReq_mshr_miss_latency::total 21577629 # number of SCUpgradeReq MSHR miss cycles 709system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 240707081 # number of ReadExReq MSHR miss cycles 710system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 275649788 # number of ReadExReq MSHR miss cycles 711system.l2c.ReadExReq_mshr_miss_latency::total 516356869 # number of ReadExReq MSHR miss cycles 712system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 207500 # number of demand (read+write) MSHR miss cycles 713system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 714system.l2c.demand_mshr_miss_latency::cpu0.inst 514472081 # number of demand (read+write) MSHR miss cycles 715system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of demand (read+write) MSHR miss cycles 716system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 936250 # number of demand (read+write) MSHR miss cycles 717system.l2c.demand_mshr_miss_latency::cpu1.inst 491423537 # number of demand (read+write) MSHR miss cycles 718system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of demand (read+write) MSHR miss cycles 719system.l2c.demand_mshr_miss_latency::total 14935012700 # number of demand (read+write) MSHR miss cycles 720system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 207500 # number of overall MSHR miss cycles 721system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles 722system.l2c.overall_mshr_miss_latency::cpu0.inst 514472081 # number of overall MSHR miss cycles 723system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of overall MSHR miss cycles 724system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 936250 # number of overall MSHR miss cycles 725system.l2c.overall_mshr_miss_latency::cpu1.inst 491423537 # number of overall MSHR miss cycles 726system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of overall MSHR miss cycles 727system.l2c.overall_mshr_miss_latency::total 14935012700 # number of overall MSHR miss cycles 728system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12573700750 # number of ReadReq MSHR uncacheable cycles 729system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155061349748 # number of ReadReq MSHR uncacheable cycles 730system.l2c.ReadReq_mshr_uncacheable_latency::total 167635050498 # number of ReadReq MSHR uncacheable cycles 731system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125597500 # number of WriteReq MSHR uncacheable cycles 732system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721355858 # number of WriteReq MSHR uncacheable cycles 733system.l2c.WriteReq_mshr_uncacheable_latency::total 16846953358 # number of WriteReq MSHR uncacheable cycles 734system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13699298250 # number of overall MSHR uncacheable cycles 735system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170782705606 # number of overall MSHR uncacheable cycles 736system.l2c.overall_mshr_uncacheable_latency::total 184482003856 # number of overall MSHR uncacheable cycles 737system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for ReadReq accesses 738system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for ReadReq accesses 739system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.220435 # mshr miss rate for ReadReq accesses 740system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for ReadReq accesses 741system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for ReadReq accesses 742system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138908 # mshr miss rate for ReadReq accesses 743system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for ReadReq accesses 744system.l2c.ReadReq_mshr_miss_rate::total 0.454861 # mshr miss rate for ReadReq accesses 745system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.722611 # mshr miss rate for UpgradeReq accesses 746system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.729459 # mshr miss rate for UpgradeReq accesses 747system.l2c.UpgradeReq_mshr_miss_rate::total 0.725384 # mshr miss rate for UpgradeReq accesses 748system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.912740 # mshr miss rate for SCUpgradeReq accesses 749system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837900 # mshr miss rate for SCUpgradeReq accesses 750system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.872764 # mshr miss rate for SCUpgradeReq accesses 751system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.645104 # mshr miss rate for ReadExReq accesses 752system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.653462 # mshr miss rate for ReadExReq accesses 753system.l2c.ReadExReq_mshr_miss_rate::total 0.649502 # mshr miss rate for ReadExReq accesses 754system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for demand accesses 755system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for demand accesses 756system.l2c.demand_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for demand accesses 757system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for demand accesses 758system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for demand accesses 759system.l2c.demand_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for demand accesses 760system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for demand accesses 761system.l2c.demand_mshr_miss_rate::total 0.461612 # mshr miss rate for demand accesses 762system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for overall accesses 763system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for overall accesses 764system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for overall accesses 765system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for overall accesses 766system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for overall accesses 767system.l2c.overall_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for overall accesses 768system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for overall accesses 769system.l2c.overall_mshr_miss_rate::total 0.461612 # mshr miss rate for overall accesses 770system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average ReadReq mshr miss latency | 698system.l2c.overall_mshr_misses::cpu1.inst 8370 # number of overall MSHR misses 699system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 19340 # number of overall MSHR misses 700system.l2c.overall_mshr_misses::total 213178 # number of overall MSHR misses 701system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of ReadReq MSHR miss cycles 702system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles 703system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 790589241 # number of ReadReq MSHR miss cycles 704system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of ReadReq MSHR miss cycles 705system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 946250 # number of ReadReq MSHR miss cycles 706system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 146552499 # number of ReadReq MSHR miss cycles 707system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of ReadReq MSHR miss cycles 708system.l2c.ReadReq_mshr_miss_latency::total 18767530106 # number of ReadReq MSHR miss cycles 709system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 89623803 # number of UpgradeReq MSHR miss cycles 710system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 27822731 # number of UpgradeReq MSHR miss cycles 711system.l2c.UpgradeReq_mshr_miss_latency::total 117446534 # number of UpgradeReq MSHR miss cycles 712system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4677961 # number of SCUpgradeReq MSHR miss cycles 713system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12575743 # number of SCUpgradeReq MSHR miss cycles 714system.l2c.SCUpgradeReq_mshr_miss_latency::total 17253704 # number of SCUpgradeReq MSHR miss cycles 715system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 498567599 # number of ReadExReq MSHR miss cycles 716system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 385443021 # number of ReadExReq MSHR miss cycles 717system.l2c.ReadExReq_mshr_miss_latency::total 884010620 # number of ReadExReq MSHR miss cycles 718system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of demand (read+write) MSHR miss cycles 719system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 720system.l2c.demand_mshr_miss_latency::cpu0.inst 1289156840 # number of demand (read+write) MSHR miss cycles 721system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of demand (read+write) MSHR miss cycles 722system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 946250 # number of demand (read+write) MSHR miss cycles 723system.l2c.demand_mshr_miss_latency::cpu1.inst 531995520 # number of demand (read+write) MSHR miss cycles 724system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of demand (read+write) MSHR miss cycles 725system.l2c.demand_mshr_miss_latency::total 19651540726 # number of demand (read+write) MSHR miss cycles 726system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 11265999 # number of overall MSHR miss cycles 727system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles 728system.l2c.overall_mshr_miss_latency::cpu0.inst 1289156840 # number of overall MSHR miss cycles 729system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15877737945 # number of overall MSHR miss cycles 730system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 946250 # number of overall MSHR miss cycles 731system.l2c.overall_mshr_miss_latency::cpu1.inst 531995520 # number of overall MSHR miss cycles 732system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1940375672 # number of overall MSHR miss cycles 733system.l2c.overall_mshr_miss_latency::total 19651540726 # number of overall MSHR miss cycles 734system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5455196250 # number of ReadReq MSHR uncacheable cycles 735system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 328328000 # number of ReadReq MSHR uncacheable cycles 736system.l2c.ReadReq_mshr_uncacheable_latency::total 5783524250 # number of ReadReq MSHR uncacheable cycles 737system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4031988000 # number of WriteReq MSHR uncacheable cycles 738system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 216852500 # number of WriteReq MSHR uncacheable cycles 739system.l2c.WriteReq_mshr_uncacheable_latency::total 4248840500 # number of WriteReq MSHR uncacheable cycles 740system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9487184250 # number of overall MSHR uncacheable cycles 741system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 545180500 # number of overall MSHR uncacheable cycles 742system.l2c.overall_mshr_uncacheable_latency::total 10032364750 # number of overall MSHR uncacheable cycles 743system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for ReadReq accesses 744system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for ReadReq accesses 745system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.231255 # mshr miss rate for ReadReq accesses 746system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for ReadReq accesses 747system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for ReadReq accesses 748system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.142030 # mshr miss rate for ReadReq accesses 749system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for ReadReq accesses 750system.l2c.ReadReq_mshr_miss_rate::total 0.393701 # mshr miss rate for ReadReq accesses 751system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.426533 # mshr miss rate for UpgradeReq accesses 752system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.727850 # mshr miss rate for UpgradeReq accesses 753system.l2c.UpgradeReq_mshr_miss_rate::total 0.472858 # mshr miss rate for UpgradeReq accesses 754system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.690476 # mshr miss rate for SCUpgradeReq accesses 755system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.877637 # mshr miss rate for SCUpgradeReq accesses 756system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817574 # mshr miss rate for SCUpgradeReq accesses 757system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.653397 # mshr miss rate for ReadExReq accesses 758system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.841249 # mshr miss rate for ReadExReq accesses 759system.l2c.ReadExReq_mshr_miss_rate::total 0.731482 # mshr miss rate for ReadExReq accesses 760system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for demand accesses 761system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for demand accesses 762system.l2c.demand_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for demand accesses 763system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for demand accesses 764system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for demand accesses 765system.l2c.demand_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for demand accesses 766system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for demand accesses 767system.l2c.demand_mshr_miss_rate::total 0.405382 # mshr miss rate for demand accesses 768system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.217687 # mshr miss rate for overall accesses 769system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008130 # mshr miss rate for overall accesses 770system.l2c.overall_mshr_miss_rate::cpu0.inst 0.308224 # mshr miss rate for overall accesses 771system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.444237 # mshr miss rate for overall accesses 772system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.091503 # mshr miss rate for overall accesses 773system.l2c.overall_mshr_miss_rate::cpu1.inst 0.385395 # mshr miss rate for overall accesses 774system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.283790 # mshr miss rate for overall accesses 775system.l2c.overall_mshr_miss_rate::total 0.405382 # mshr miss rate for overall accesses 776system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average ReadReq mshr miss latency |
| 771system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 777system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 772system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64842.491710 # average ReadReq mshr miss latency 773system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average ReadReq mshr miss latency 774system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average ReadReq mshr miss latency 775system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67938.837846 # average ReadReq mshr miss latency 776system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average ReadReq mshr miss latency 777system.l2c.ReadReq_avg_mshr_miss_latency::total 86634.956624 # average ReadReq mshr miss latency 778system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10068.053347 # average UpgradeReq mshr miss latency 779system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10063.995604 # average UpgradeReq mshr miss latency 780system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.400955 # average UpgradeReq mshr miss latency 781system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.299235 # average SCUpgradeReq mshr miss latency 782system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10030.968211 # average SCUpgradeReq mshr miss latency 783system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10050.129949 # average SCUpgradeReq mshr miss latency 784system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 59892.281911 # average ReadExReq mshr miss latency 785system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60984.466372 # average ReadExReq mshr miss latency 786system.l2c.ReadExReq_avg_mshr_miss_latency::total 60470.414451 # average ReadExReq mshr miss latency 787system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency | 778system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71741.310436 # average ReadReq mshr miss latency 779system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average ReadReq mshr miss latency 780system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average ReadReq mshr miss latency 781system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72875.434610 # average ReadReq mshr miss latency 782system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average ReadReq mshr miss latency 783system.l2c.ReadReq_avg_mshr_miss_latency::total 93895.865967 # average ReadReq mshr miss latency 784system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10096.181480 # average UpgradeReq mshr miss latency 785system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10110.003997 # average UpgradeReq mshr miss latency 786system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10099.452575 # average UpgradeReq mshr miss latency 787system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10081.812500 # average SCUpgradeReq mshr miss latency 788system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.717147 # average SCUpgradeReq mshr miss latency 789system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.098131 # average SCUpgradeReq mshr miss latency 790system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 71808.670459 # average ReadExReq mshr miss latency 791system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60613.779053 # average ReadExReq mshr miss latency 792system.l2c.ReadExReq_avg_mshr_miss_latency::total 66456.970380 # average ReadExReq mshr miss latency 793system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency |
| 788system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 794system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 789system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency 790system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency 791system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency 792system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency 793system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency 794system.l2c.demand_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency 795system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency | 795system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency 796system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency 797system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency 798system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency 799system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency 800system.l2c.demand_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency 801system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency |
| 796system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 802system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 797system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency 798system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency 799system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency 800system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency 801system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency 802system.l2c.overall_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency | 803system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency 804system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency 805system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency 806system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency 807system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency 808system.l2c.overall_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency |
| 803system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 804system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 805system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 806system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 807system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 808system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 809system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 810system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 811system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 812system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 809system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 810system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 811system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 812system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 813system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 814system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 815system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 816system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 817system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 818system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 819system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 820system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 821system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 822system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 823system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 824system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 825system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 826system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 827system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 828system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 829system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 830system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 831system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 832system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 833system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 834system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 835system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 836system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 837system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 838system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 839system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 840system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 841system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 842system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 843system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 844system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 845system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 846system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 847system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 848system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 849system.realview.ethernet.droppedPackets 0 # number of packets dropped |
|
| 813system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). | 850system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
| 814system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 815system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 816system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 817system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 818system.cf0.dma_write_txs 0 # Number of DMA write transactions. 819system.toL2Bus.trans_dist::ReadReq 1655552 # Transaction distribution 820system.toL2Bus.trans_dist::ReadResp 1655552 # Transaction distribution 821system.toL2Bus.trans_dist::WriteReq 768869 # Transaction distribution 822system.toL2Bus.trans_dist::WriteResp 768869 # Transaction distribution 823system.toL2Bus.trans_dist::Writeback 215010 # Transaction distribution 824system.toL2Bus.trans_dist::UpgradeReq 60145 # Transaction distribution 825system.toL2Bus.trans_dist::SCUpgradeReq 22613 # Transaction distribution 826system.toL2Bus.trans_dist::UpgradeResp 82758 # Transaction distribution 827system.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution 828system.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution 829system.toL2Bus.trans_dist::ReadExReq 22833 # Transaction distribution 830system.toL2Bus.trans_dist::ReadExResp 22833 # Transaction distribution 831system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 801778 # Packet count per connected master and slave (bytes) 832system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302678 # Packet count per connected master and slave (bytes) 833system.toL2Bus.pkt_count::total 5104456 # Packet count per connected master and slave (bytes) 834system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20000696 # Cumulative packet size per connected master and slave (bytes) 835system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23627528 # Cumulative packet size per connected master and slave (bytes) 836system.toL2Bus.pkt_size::total 43628224 # Cumulative packet size per connected master and slave (bytes) 837system.toL2Bus.snoops 170698 # Total snoops (count) 838system.toL2Bus.snoop_fanout::samples 785697 # Request fanout histogram 839system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 840system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 851system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 852system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 853system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 854system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 855system.cf0.dma_write_txs 631 # Number of DMA write transactions. 856system.toL2Bus.trans_dist::ReadReq 675950 # Transaction distribution 857system.toL2Bus.trans_dist::ReadResp 675935 # Transaction distribution 858system.toL2Bus.trans_dist::WriteReq 31054 # Transaction distribution 859system.toL2Bus.trans_dist::WriteResp 31054 # Transaction distribution 860system.toL2Bus.trans_dist::Writeback 253703 # Transaction distribution 861system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 862system.toL2Bus.trans_dist::UpgradeReq 93172 # Transaction distribution 863system.toL2Bus.trans_dist::SCUpgradeReq 40812 # Transaction distribution 864system.toL2Bus.trans_dist::UpgradeResp 133984 # Transaction distribution 865system.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 866system.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution 867system.toL2Bus.trans_dist::ReadExReq 39254 # Transaction distribution 868system.toL2Bus.trans_dist::ReadExResp 39254 # Transaction distribution 869system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372089 # Packet count per connected master and slave (bytes) 870system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 383613 # Packet count per connected master and slave (bytes) 871system.toL2Bus.pkt_count::total 1755702 # Packet count per connected master and slave (bytes) 872system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 42006746 # Cumulative packet size per connected master and slave (bytes) 873system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8315748 # Cumulative packet size per connected master and slave (bytes) 874system.toL2Bus.pkt_size::total 50322494 # Cumulative packet size per connected master and slave (bytes) 875system.toL2Bus.snoops 294957 # Total snoops (count) 876system.toL2Bus.snoop_fanout::samples 1100978 # Request fanout histogram 877system.toL2Bus.snoop_fanout::mean 1.033136 # Request fanout histogram 878system.toL2Bus.snoop_fanout::stdev 0.178992 # Request fanout histogram |
| 841system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 842system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 879system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 880system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 843system.toL2Bus.snoop_fanout::1 785697 100.00% 100.00% # Request fanout histogram 844system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram | 881system.toL2Bus.snoop_fanout::1 1064496 96.69% 96.69% # Request fanout histogram 882system.toL2Bus.snoop_fanout::2 36482 3.31% 100.00% # Request fanout histogram |
| 845system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 846system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 883system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 884system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram |
| 847system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 848system.toL2Bus.snoop_fanout::total 785697 # Request fanout histogram 849system.toL2Bus.reqLayer0.occupancy 2618065998 # Layer occupancy (ticks) | 885system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 886system.toL2Bus.snoop_fanout::total 1100978 # Request fanout histogram 887system.toL2Bus.reqLayer0.occupancy 1599263913 # Layer occupancy (ticks) |
| 850system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 888system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 851system.toL2Bus.respLayer0.occupancy 1234480729 # Layer occupancy (ticks) 852system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 853system.toL2Bus.respLayer1.occupancy 2606264414 # Layer occupancy (ticks) 854system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 855system.iobus.trans_dist::ReadReq 16519582 # Transaction distribution 856system.iobus.trans_dist::ReadResp 16519582 # Transaction distribution 857system.iobus.trans_dist::WriteReq 8084 # Transaction distribution 858system.iobus.trans_dist::WriteResp 8084 # Transaction distribution 859system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) 860system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8940 # Packet count per connected master and slave (bytes) | 889system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) 890system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 891system.toL2Bus.respLayer0.occupancy 2370465695 # Layer occupancy (ticks) 892system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 893system.toL2Bus.respLayer1.occupancy 831346703 # Layer occupancy (ticks) 894system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 895system.iobus.trans_dist::ReadReq 31024 # Transaction distribution 896system.iobus.trans_dist::ReadResp 31024 # Transaction distribution 897system.iobus.trans_dist::WriteReq 59407 # Transaction distribution 898system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 899system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution 900system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 901system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) |
| 861system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) | 902system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) |
| 862system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) 863system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) | 903system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) |
| 864system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) | 904system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
| 865system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) 866system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 867system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) | 905system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 906system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) |
| 868system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 869system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 870system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) | 907system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 908system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 909system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 871system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 872system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) | 910system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) |
| 873system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) | 911system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 874system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 875system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 876system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 877system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 878system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) | |
| 879system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) | 912system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 913system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 914system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) |
|
| 880system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) | 915system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 881system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 882system.iobus.pkt_count_system.bridge.master::total 2384484 # Packet count per connected master and slave (bytes) 883system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 884system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) 885system.iobus.pkt_count::total 33055332 # Packet count per connected master and slave (bytes) 886system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) 887system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17880 # Cumulative packet size per connected master and slave (bytes) | 916system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 917system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 918system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 919system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 920system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 921system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) 922system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 923system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 924system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) 925system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 926system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) |
| 888system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) | 927system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) |
| 889system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 890system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) | 928system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) |
| 891system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) | 929system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) |
| 892system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) 893system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 894system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 930system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 931system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) |
| 895system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 896system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 932system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 933system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 934system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 898system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 899system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) | 935system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) |
| 900system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 936system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 901system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 902system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 903system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 904system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 905system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | |
| 906system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 937system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 938system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 939system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) |
|
| 907system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 940system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 908system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 909system.iobus.pkt_size_system.bridge.master::total 2392912 # Cumulative packet size per connected master and slave (bytes) 910system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 911system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) 912system.iobus.pkt_size::total 125076304 # Cumulative packet size per connected master and slave (bytes) 913system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) | 941system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 942system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 943system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 944system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 945system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 946system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) 947system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 948system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 949system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) 950system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) |
| 914system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 951system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 915system.iobus.reqLayer1.occupancy 4476000 # Layer occupancy (ticks) | 952system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) |
| 916system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 953system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 917system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) | 954system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) |
| 918system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 955system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 919system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) | 956system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) |
| 920system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 957system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 921system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 922system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 923system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 924system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 925system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) | 958system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) |
| 926system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) | 959system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
| 927system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) | 960system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) |
| 928system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 961system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 929system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 930system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 931system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) | 962system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) |
| 932system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) | 963system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) |
| 933system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 934system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 935system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 936system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) | |
| 937system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 938system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) | 964system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 965system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) |
| 939system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) | 966system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) |
| 940system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 941system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 942system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 967system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 968system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 969system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 943system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) | 970system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) |
| 944system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 945system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 946system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 947system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 948system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) | 971system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 972system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 973system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 974system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 975system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
| 949system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) | 976system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) |
| 950system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 951system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 952system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 953system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 954system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 977system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 978system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 979system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 980system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 981system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 955system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 956system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 957system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) | 982system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) |
| 958system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 983system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 959system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) 960system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) 961system.iobus.respLayer0.occupancy 2376400000 # Layer occupancy (ticks) 962system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 963system.iobus.respLayer1.occupancy 38686704315 # Layer occupancy (ticks) 964system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 965system.cpu0.branchPred.lookups 7252165 # Number of BP lookups 966system.cpu0.branchPred.condPredicted 5142285 # Number of conditional branches predicted 967system.cpu0.branchPred.condIncorrect 425056 # Number of conditional branches incorrect 968system.cpu0.branchPred.BTBLookups 4634449 # Number of BTB lookups 969system.cpu0.branchPred.BTBHits 3350199 # Number of BTB hits | 984system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 985system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 986system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 987system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 988system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 989system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 990system.iobus.reqLayer27.occupancy 326680325 # Layer occupancy (ticks) 991system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 992system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 993system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 994system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) 995system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 996system.iobus.respLayer3.occupancy 36847116 # Layer occupancy (ticks) 997system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 998system.cpu0.branchPred.lookups 34854856 # Number of BP lookups 999system.cpu0.branchPred.condPredicted 17109626 # Number of conditional branches predicted 1000system.cpu0.branchPred.condIncorrect 1616877 # Number of conditional branches incorrect 1001system.cpu0.branchPred.BTBLookups 20006820 # Number of BTB lookups 1002system.cpu0.branchPred.BTBHits 14503231 # Number of BTB hits |
| 970system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1003system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 971system.cpu0.branchPred.BTBHitPct 72.289047 # BTB Hit Percentage 972system.cpu0.branchPred.usedRAS 946301 # Number of times the RAS was used to get a target. 973system.cpu0.branchPred.RASInCorrect 66428 # Number of incorrect RAS predictions. | 1004system.cpu0.branchPred.BTBHitPct 72.491435 # BTB Hit Percentage 1005system.cpu0.branchPred.usedRAS 10748202 # Number of times the RAS was used to get a target. 1006system.cpu0.branchPred.RASInCorrect 771222 # Number of incorrect RAS predictions. |
| 974system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 975system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 976system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 977system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 978system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 979system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 980system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 981system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 989system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 990system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 991system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 992system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 993system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 994system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 995system.cpu0.dtb.inst_hits 0 # ITB inst hits 996system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1007system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1008system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1009system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1010system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1011system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1012system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1013system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1014system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1022system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1023system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1024system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1025system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1026system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1027system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1028system.cpu0.dtb.inst_hits 0 # ITB inst hits 1029system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 997system.cpu0.dtb.read_hits 6449087 # DTB read hits 998system.cpu0.dtb.read_misses 22394 # DTB read misses 999system.cpu0.dtb.write_hits 5803603 # DTB write hits 1000system.cpu0.dtb.write_misses 1784 # DTB write misses 1001system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1002system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1003system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1004system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1005system.cpu0.dtb.flush_entries 1724 # Number of entries that have been flushed from TLB 1006system.cpu0.dtb.align_faults 1623 # Number of TLB faults due to alignment restrictions 1007system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch | 1030system.cpu0.dtb.read_hits 23968692 # DTB read hits 1031system.cpu0.dtb.read_misses 61651 # DTB read misses 1032system.cpu0.dtb.write_hits 17871018 # DTB write hits 1033system.cpu0.dtb.write_misses 6619 # DTB write misses 1034system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1035system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1036system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1037system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1038system.cpu0.dtb.flush_entries 3502 # Number of entries that have been flushed from TLB 1039system.cpu0.dtb.align_faults 1211 # Number of TLB faults due to alignment restrictions 1040system.cpu0.dtb.prefetch_faults 1921 # Number of TLB faults due to prefetch |
| 1008system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1041system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1009system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions 1010system.cpu0.dtb.read_accesses 6471481 # DTB read accesses 1011system.cpu0.dtb.write_accesses 5805387 # DTB write accesses | 1042system.cpu0.dtb.perms_faults 566 # Number of TLB faults due to permissions restrictions 1043system.cpu0.dtb.read_accesses 24030343 # DTB read accesses 1044system.cpu0.dtb.write_accesses 17877637 # DTB write accesses |
| 1012system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1045system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1013system.cpu0.dtb.hits 12252690 # DTB hits 1014system.cpu0.dtb.misses 24178 # DTB misses 1015system.cpu0.dtb.accesses 12276868 # DTB accesses | 1046system.cpu0.dtb.hits 41839710 # DTB hits 1047system.cpu0.dtb.misses 68270 # DTB misses 1048system.cpu0.dtb.accesses 41907980 # DTB accesses |
| 1016system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1017system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1018system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1019system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1020system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1021system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1022system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1023system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1029system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1030system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1031system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1032system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1033system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1034system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1035system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1036system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1049system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1050system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1051system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1052system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1053system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1054system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1055system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1056system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1062system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1063system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1064system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1065system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1066system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1067system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1068system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1069system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1037system.cpu0.itb.inst_hits 13302311 # ITB inst hits 1038system.cpu0.itb.inst_misses 3954 # ITB inst misses | 1070system.cpu0.itb.inst_hits 70097291 # ITB inst hits 1071system.cpu0.itb.inst_misses 3844 # ITB inst misses |
| 1039system.cpu0.itb.read_hits 0 # DTB read hits 1040system.cpu0.itb.read_misses 0 # DTB read misses 1041system.cpu0.itb.write_hits 0 # DTB write hits 1042system.cpu0.itb.write_misses 0 # DTB write misses | 1072system.cpu0.itb.read_hits 0 # DTB read hits 1073system.cpu0.itb.read_misses 0 # DTB read misses 1074system.cpu0.itb.write_hits 0 # DTB write hits 1075system.cpu0.itb.write_misses 0 # DTB write misses |
| 1043system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1044system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1045system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1046system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1047system.cpu0.itb.flush_entries 1195 # Number of entries that have been flushed from TLB | 1076system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1077system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1078system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1079system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1080system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB |
| 1048system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1049system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1050system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1081system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1082system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1083system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1051system.cpu0.itb.perms_faults 3570 # Number of TLB faults due to permissions restrictions | 1084system.cpu0.itb.perms_faults 7362 # Number of TLB faults due to permissions restrictions |
| 1052system.cpu0.itb.read_accesses 0 # DTB read accesses 1053system.cpu0.itb.write_accesses 0 # DTB write accesses | 1085system.cpu0.itb.read_accesses 0 # DTB read accesses 1086system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1054system.cpu0.itb.inst_accesses 13306265 # ITB inst accesses 1055system.cpu0.itb.hits 13302311 # DTB hits 1056system.cpu0.itb.misses 3954 # DTB misses 1057system.cpu0.itb.accesses 13306265 # DTB accesses 1058system.cpu0.numCycles 86799146 # number of cpu cycles simulated | 1087system.cpu0.itb.inst_accesses 70101135 # ITB inst accesses 1088system.cpu0.itb.hits 70097291 # DTB hits 1089system.cpu0.itb.misses 3844 # DTB misses 1090system.cpu0.itb.accesses 70101135 # DTB accesses 1091system.cpu0.numCycles 227722348 # number of cpu cycles simulated |
| 1059system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1060system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1092system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1093system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1061system.cpu0.committedInsts 29471412 # Number of instructions committed 1062system.cpu0.committedOps 35693999 # Number of ops (including micro ops) committed 1063system.cpu0.discardedOps 1972340 # Number of ops (including micro ops) which were discarded before commit 1064system.cpu0.numFetchSuspends 41075 # Number of times Execute suspended instruction fetching 1065system.cpu0.quiesceCycles 5234564326 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1066system.cpu0.cpi 2.945198 # CPI: cycles per instruction 1067system.cpu0.ipc 0.339536 # IPC: instructions per cycle | 1094system.cpu0.committedInsts 109201964 # Number of instructions committed 1095system.cpu0.committedOps 132004483 # Number of ops (including micro ops) committed 1096system.cpu0.discardedOps 8817575 # Number of ops (including micro ops) which were discarded before commit 1097system.cpu0.numFetchSuspends 1858 # Number of times Execute suspended instruction fetching 1098system.cpu0.quiesceCycles 5459726684 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1099system.cpu0.cpi 2.085332 # CPI: cycles per instruction 1100system.cpu0.ipc 0.479540 # IPC: instructions per cycle |
| 1068system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1101system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1069system.cpu0.kern.inst.quiesce 47489 # number of quiesce instructions executed 1070system.cpu0.tickCycles 68192545 # Number of cycles that the object actually ticked 1071system.cpu0.idleCycles 18606601 # Total number of cycles that the object has spent stopped 1072system.cpu0.icache.tags.replacements 670908 # number of replacements 1073system.cpu0.icache.tags.tagsinuse 511.780495 # Cycle average of tags in use 1074system.cpu0.icache.tags.total_refs 12627162 # Total number of references to valid blocks. 1075system.cpu0.icache.tags.sampled_refs 671420 # Sample count of references to valid blocks. 1076system.cpu0.icache.tags.avg_refs 18.806652 # Average number of references to valid blocks. 1077system.cpu0.icache.tags.warmup_cycle 6076833000 # Cycle when the warmup percentage was hit. 1078system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780495 # Average occupied blocks per requestor 1079system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy 1080system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy | 1102system.cpu0.kern.inst.quiesce 1864 # number of quiesce instructions executed 1103system.cpu0.tickCycles 192189087 # Number of cycles that the object actually ticked 1104system.cpu0.idleCycles 35533261 # Total number of cycles that the object has spent stopped 1105system.cpu0.icache.tags.replacements 1960423 # number of replacements 1106system.cpu0.icache.tags.tagsinuse 511.796865 # Cycle average of tags in use 1107system.cpu0.icache.tags.total_refs 68128653 # Total number of references to valid blocks. 1108system.cpu0.icache.tags.sampled_refs 1960935 # Sample count of references to valid blocks. 1109system.cpu0.icache.tags.avg_refs 34.742943 # Average number of references to valid blocks. 1110system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. 1111system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796865 # Average occupied blocks per requestor 1112system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy 1113system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy |
| 1081system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1114system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1082system.cpu0.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 1083system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id 1084system.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id | 1115system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 1116system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 1117system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id |
| 1085system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1118system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1086system.cpu0.icache.tags.tag_accesses 27268595 # Number of tag accesses 1087system.cpu0.icache.tags.data_accesses 27268595 # Number of data accesses 1088system.cpu0.icache.ReadReq_hits::cpu0.inst 12627162 # number of ReadReq hits 1089system.cpu0.icache.ReadReq_hits::total 12627162 # number of ReadReq hits 1090system.cpu0.icache.demand_hits::cpu0.inst 12627162 # number of demand (read+write) hits 1091system.cpu0.icache.demand_hits::total 12627162 # number of demand (read+write) hits 1092system.cpu0.icache.overall_hits::cpu0.inst 12627162 # number of overall hits 1093system.cpu0.icache.overall_hits::total 12627162 # number of overall hits 1094system.cpu0.icache.ReadReq_misses::cpu0.inst 671424 # number of ReadReq misses 1095system.cpu0.icache.ReadReq_misses::total 671424 # number of ReadReq misses 1096system.cpu0.icache.demand_misses::cpu0.inst 671424 # number of demand (read+write) misses 1097system.cpu0.icache.demand_misses::total 671424 # number of demand (read+write) misses 1098system.cpu0.icache.overall_misses::cpu0.inst 671424 # number of overall misses 1099system.cpu0.icache.overall_misses::total 671424 # number of overall misses 1100system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5600052378 # number of ReadReq miss cycles 1101system.cpu0.icache.ReadReq_miss_latency::total 5600052378 # number of ReadReq miss cycles 1102system.cpu0.icache.demand_miss_latency::cpu0.inst 5600052378 # number of demand (read+write) miss cycles 1103system.cpu0.icache.demand_miss_latency::total 5600052378 # number of demand (read+write) miss cycles 1104system.cpu0.icache.overall_miss_latency::cpu0.inst 5600052378 # number of overall miss cycles 1105system.cpu0.icache.overall_miss_latency::total 5600052378 # number of overall miss cycles 1106system.cpu0.icache.ReadReq_accesses::cpu0.inst 13298586 # number of ReadReq accesses(hits+misses) 1107system.cpu0.icache.ReadReq_accesses::total 13298586 # number of ReadReq accesses(hits+misses) 1108system.cpu0.icache.demand_accesses::cpu0.inst 13298586 # number of demand (read+write) accesses 1109system.cpu0.icache.demand_accesses::total 13298586 # number of demand (read+write) accesses 1110system.cpu0.icache.overall_accesses::cpu0.inst 13298586 # number of overall (read+write) accesses 1111system.cpu0.icache.overall_accesses::total 13298586 # number of overall (read+write) accesses 1112system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050488 # miss rate for ReadReq accesses 1113system.cpu0.icache.ReadReq_miss_rate::total 0.050488 # miss rate for ReadReq accesses 1114system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050488 # miss rate for demand accesses 1115system.cpu0.icache.demand_miss_rate::total 0.050488 # miss rate for demand accesses 1116system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050488 # miss rate for overall accesses 1117system.cpu0.icache.overall_miss_rate::total 0.050488 # miss rate for overall accesses 1118system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8340.560328 # average ReadReq miss latency 1119system.cpu0.icache.ReadReq_avg_miss_latency::total 8340.560328 # average ReadReq miss latency 1120system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency 1121system.cpu0.icache.demand_avg_miss_latency::total 8340.560328 # average overall miss latency 1122system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency 1123system.cpu0.icache.overall_avg_miss_latency::total 8340.560328 # average overall miss latency | 1119system.cpu0.icache.tags.tag_accesses 142140155 # Number of tag accesses 1120system.cpu0.icache.tags.data_accesses 142140155 # Number of data accesses 1121system.cpu0.icache.ReadReq_hits::cpu0.inst 68128653 # number of ReadReq hits 1122system.cpu0.icache.ReadReq_hits::total 68128653 # number of ReadReq hits 1123system.cpu0.icache.demand_hits::cpu0.inst 68128653 # number of demand (read+write) hits 1124system.cpu0.icache.demand_hits::total 68128653 # number of demand (read+write) hits 1125system.cpu0.icache.overall_hits::cpu0.inst 68128653 # number of overall hits 1126system.cpu0.icache.overall_hits::total 68128653 # number of overall hits 1127system.cpu0.icache.ReadReq_misses::cpu0.inst 1960950 # number of ReadReq misses 1128system.cpu0.icache.ReadReq_misses::total 1960950 # number of ReadReq misses 1129system.cpu0.icache.demand_misses::cpu0.inst 1960950 # number of demand (read+write) misses 1130system.cpu0.icache.demand_misses::total 1960950 # number of demand (read+write) misses 1131system.cpu0.icache.overall_misses::cpu0.inst 1960950 # number of overall misses 1132system.cpu0.icache.overall_misses::total 1960950 # number of overall misses 1133system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16347715808 # number of ReadReq miss cycles 1134system.cpu0.icache.ReadReq_miss_latency::total 16347715808 # number of ReadReq miss cycles 1135system.cpu0.icache.demand_miss_latency::cpu0.inst 16347715808 # number of demand (read+write) miss cycles 1136system.cpu0.icache.demand_miss_latency::total 16347715808 # number of demand (read+write) miss cycles 1137system.cpu0.icache.overall_miss_latency::cpu0.inst 16347715808 # number of overall miss cycles 1138system.cpu0.icache.overall_miss_latency::total 16347715808 # number of overall miss cycles 1139system.cpu0.icache.ReadReq_accesses::cpu0.inst 70089603 # number of ReadReq accesses(hits+misses) 1140system.cpu0.icache.ReadReq_accesses::total 70089603 # number of ReadReq accesses(hits+misses) 1141system.cpu0.icache.demand_accesses::cpu0.inst 70089603 # number of demand (read+write) accesses 1142system.cpu0.icache.demand_accesses::total 70089603 # number of demand (read+write) accesses 1143system.cpu0.icache.overall_accesses::cpu0.inst 70089603 # number of overall (read+write) accesses 1144system.cpu0.icache.overall_accesses::total 70089603 # number of overall (read+write) accesses 1145system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027978 # miss rate for ReadReq accesses 1146system.cpu0.icache.ReadReq_miss_rate::total 0.027978 # miss rate for ReadReq accesses 1147system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027978 # miss rate for demand accesses 1148system.cpu0.icache.demand_miss_rate::total 0.027978 # miss rate for demand accesses 1149system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027978 # miss rate for overall accesses 1150system.cpu0.icache.overall_miss_rate::total 0.027978 # miss rate for overall accesses 1151system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8336.630617 # average ReadReq miss latency 1152system.cpu0.icache.ReadReq_avg_miss_latency::total 8336.630617 # average ReadReq miss latency 1153system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency 1154system.cpu0.icache.demand_avg_miss_latency::total 8336.630617 # average overall miss latency 1155system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency 1156system.cpu0.icache.overall_avg_miss_latency::total 8336.630617 # average overall miss latency |
| 1124system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1125system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1126system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1127system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1128system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1129system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1130system.cpu0.icache.fast_writes 0 # number of fast writes performed 1131system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1157system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1158system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1159system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1160system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1161system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1162system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1163system.cpu0.icache.fast_writes 0 # number of fast writes performed 1164system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1132system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 671424 # number of ReadReq MSHR misses 1133system.cpu0.icache.ReadReq_mshr_misses::total 671424 # number of ReadReq MSHR misses 1134system.cpu0.icache.demand_mshr_misses::cpu0.inst 671424 # number of demand (read+write) MSHR misses 1135system.cpu0.icache.demand_mshr_misses::total 671424 # number of demand (read+write) MSHR misses 1136system.cpu0.icache.overall_mshr_misses::cpu0.inst 671424 # number of overall MSHR misses 1137system.cpu0.icache.overall_mshr_misses::total 671424 # number of overall MSHR misses 1138system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4592017122 # number of ReadReq MSHR miss cycles 1139system.cpu0.icache.ReadReq_mshr_miss_latency::total 4592017122 # number of ReadReq MSHR miss cycles 1140system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4592017122 # number of demand (read+write) MSHR miss cycles 1141system.cpu0.icache.demand_mshr_miss_latency::total 4592017122 # number of demand (read+write) MSHR miss cycles 1142system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4592017122 # number of overall MSHR miss cycles 1143system.cpu0.icache.overall_mshr_miss_latency::total 4592017122 # number of overall MSHR miss cycles 1144system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 214843000 # number of ReadReq MSHR uncacheable cycles 1145system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 214843000 # number of ReadReq MSHR uncacheable cycles 1146system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 214843000 # number of overall MSHR uncacheable cycles 1147system.cpu0.icache.overall_mshr_uncacheable_latency::total 214843000 # number of overall MSHR uncacheable cycles 1148system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for ReadReq accesses 1149system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050488 # mshr miss rate for ReadReq accesses 1150system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for demand accesses 1151system.cpu0.icache.demand_mshr_miss_rate::total 0.050488 # mshr miss rate for demand accesses 1152system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for overall accesses 1153system.cpu0.icache.overall_mshr_miss_rate::total 0.050488 # mshr miss rate for overall accesses 1154system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average ReadReq mshr miss latency 1155system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6839.221002 # average ReadReq mshr miss latency 1156system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency 1157system.cpu0.icache.demand_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency 1158system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency 1159system.cpu0.icache.overall_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency | 1165system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1960950 # number of ReadReq MSHR misses 1166system.cpu0.icache.ReadReq_mshr_misses::total 1960950 # number of ReadReq MSHR misses 1167system.cpu0.icache.demand_mshr_misses::cpu0.inst 1960950 # number of demand (read+write) MSHR misses 1168system.cpu0.icache.demand_mshr_misses::total 1960950 # number of demand (read+write) MSHR misses 1169system.cpu0.icache.overall_mshr_misses::cpu0.inst 1960950 # number of overall MSHR misses 1170system.cpu0.icache.overall_mshr_misses::total 1960950 # number of overall MSHR misses 1171system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13404270692 # number of ReadReq MSHR miss cycles 1172system.cpu0.icache.ReadReq_mshr_miss_latency::total 13404270692 # number of ReadReq MSHR miss cycles 1173system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13404270692 # number of demand (read+write) MSHR miss cycles 1174system.cpu0.icache.demand_mshr_miss_latency::total 13404270692 # number of demand (read+write) MSHR miss cycles 1175system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13404270692 # number of overall MSHR miss cycles 1176system.cpu0.icache.overall_mshr_miss_latency::total 13404270692 # number of overall MSHR miss cycles 1177system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276968500 # number of ReadReq MSHR uncacheable cycles 1178system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276968500 # number of ReadReq MSHR uncacheable cycles 1179system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276968500 # number of overall MSHR uncacheable cycles 1180system.cpu0.icache.overall_mshr_uncacheable_latency::total 276968500 # number of overall MSHR uncacheable cycles 1181system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for ReadReq accesses 1182system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027978 # mshr miss rate for ReadReq accesses 1183system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for demand accesses 1184system.cpu0.icache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses 1185system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for overall accesses 1186system.cpu0.icache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses 1187system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average ReadReq mshr miss latency 1188system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6835.600445 # average ReadReq mshr miss latency 1189system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency 1190system.cpu0.icache.demand_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency 1191system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency 1192system.cpu0.icache.overall_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency |
| 1160system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1161system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1162system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1163system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1164system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1193system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1194system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1195system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1196system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1197system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1165system.cpu0.toL2Bus.trans_dist::ReadReq 1296970 # Transaction distribution 1166system.cpu0.toL2Bus.trans_dist::ReadResp 1098887 # Transaction distribution 1167system.cpu0.toL2Bus.trans_dist::WriteReq 10913 # Transaction distribution 1168system.cpu0.toL2Bus.trans_dist::WriteResp 10913 # Transaction distribution 1169system.cpu0.toL2Bus.trans_dist::Writeback 275708 # Transaction distribution 1170system.cpu0.toL2Bus.trans_dist::HardPFReq 308200 # Transaction distribution 1171system.cpu0.toL2Bus.trans_dist::UpgradeReq 48588 # Transaction distribution 1172system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23370 # Transaction distribution 1173system.cpu0.toL2Bus.trans_dist::UpgradeResp 54742 # Transaction distribution 1174system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution 1175system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution 1176system.cpu0.toL2Bus.trans_dist::ReadExReq 144812 # Transaction distribution 1177system.cpu0.toL2Bus.trans_dist::ReadExResp 136646 # Transaction distribution 1178system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1347493 # Packet count per connected master and slave (bytes) 1179system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1381165 # Packet count per connected master and slave (bytes) 1180system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13298 # Packet count per connected master and slave (bytes) 1181system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 66487 # Packet count per connected master and slave (bytes) 1182system.cpu0.toL2Bus.pkt_count::total 2808443 # Packet count per connected master and slave (bytes) 1183system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43116416 # Cumulative packet size per connected master and slave (bytes) 1184system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45547448 # Cumulative packet size per connected master and slave (bytes) 1185system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21688 # Cumulative packet size per connected master and slave (bytes) 1186system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119336 # Cumulative packet size per connected master and slave (bytes) 1187system.cpu0.toL2Bus.pkt_size::total 88804888 # Cumulative packet size per connected master and slave (bytes) 1188system.cpu0.toL2Bus.snoops 661783 # Total snoops (count) 1189system.cpu0.toL2Bus.snoop_fanout::samples 2010538 # Request fanout histogram 1190system.cpu0.toL2Bus.snoop_fanout::mean 5.294459 # Request fanout histogram 1191system.cpu0.toL2Bus.snoop_fanout::stdev 0.455799 # Request fanout histogram | 1198system.cpu0.toL2Bus.trans_dist::ReadReq 2745512 # Transaction distribution 1199system.cpu0.toL2Bus.trans_dist::ReadResp 2644445 # Transaction distribution 1200system.cpu0.toL2Bus.trans_dist::WriteReq 28520 # Transaction distribution 1201system.cpu0.toL2Bus.trans_dist::WriteResp 28520 # Transaction distribution 1202system.cpu0.toL2Bus.trans_dist::Writeback 513053 # Transaction distribution 1203system.cpu0.toL2Bus.trans_dist::HardPFReq 701523 # Transaction distribution 1204system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 1205system.cpu0.toL2Bus.trans_dist::UpgradeReq 70947 # Transaction distribution 1206system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43092 # Transaction distribution 1207system.cpu0.toL2Bus.trans_dist::UpgradeResp 94006 # Transaction distribution 1208system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution 1209system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution 1210system.cpu0.toL2Bus.trans_dist::ReadExReq 290299 # Transaction distribution 1211system.cpu0.toL2Bus.trans_dist::ReadExResp 280446 # Transaction distribution 1212system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3928023 # Packet count per connected master and slave (bytes) 1213system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2381529 # Packet count per connected master and slave (bytes) 1214system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11804 # Packet count per connected master and slave (bytes) 1215system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166842 # Packet count per connected master and slave (bytes) 1216system.cpu0.toL2Bus.pkt_count::total 6488198 # Packet count per connected master and slave (bytes) 1217system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 125696704 # Cumulative packet size per connected master and slave (bytes) 1218system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86351322 # Cumulative packet size per connected master and slave (bytes) 1219system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17688 # Cumulative packet size per connected master and slave (bytes) 1220system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313268 # Cumulative packet size per connected master and slave (bytes) 1221system.cpu0.toL2Bus.pkt_size::total 212378982 # Cumulative packet size per connected master and slave (bytes) 1222system.cpu0.toL2Bus.snoops 1094951 # Total snoops (count) 1223system.cpu0.toL2Bus.snoop_fanout::samples 4365889 # Request fanout histogram 1224system.cpu0.toL2Bus.snoop_fanout::mean 5.223377 # Request fanout histogram 1225system.cpu0.toL2Bus.snoop_fanout::stdev 0.416509 # Request fanout histogram |
| 1192system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1193system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1194system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1195system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1196system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1197system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1226system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1227system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1228system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1229system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1230system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1231system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1198system.cpu0.toL2Bus.snoop_fanout::5 1418517 70.55% 70.55% # Request fanout histogram 1199system.cpu0.toL2Bus.snoop_fanout::6 592021 29.45% 100.00% # Request fanout histogram | 1232system.cpu0.toL2Bus.snoop_fanout::5 3390648 77.66% 77.66% # Request fanout histogram 1233system.cpu0.toL2Bus.snoop_fanout::6 975241 22.34% 100.00% # Request fanout histogram |
| 1200system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1201system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1202system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1234system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1235system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1236system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1203system.cpu0.toL2Bus.snoop_fanout::total 2010538 # Request fanout histogram 1204system.cpu0.toL2Bus.reqLayer0.occupancy 1039622669 # Layer occupancy (ticks) 1205system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1206system.cpu0.toL2Bus.snoopLayer0.occupancy 67426500 # Layer occupancy (ticks) | 1237system.cpu0.toL2Bus.snoop_fanout::total 4365889 # Request fanout histogram 1238system.cpu0.toL2Bus.reqLayer0.occupancy 2254798560 # Layer occupancy (ticks) 1239system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1240system.cpu0.toL2Bus.snoopLayer0.occupancy 118870000 # Layer occupancy (ticks) |
| 1207system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1241system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1208system.cpu0.toL2Bus.respLayer0.occupancy 1011659878 # Layer occupancy (ticks) 1209system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1210system.cpu0.toL2Bus.respLayer1.occupancy 704346240 # Layer occupancy (ticks) | 1242system.cpu0.toL2Bus.respLayer0.occupancy 2947700808 # Layer occupancy (ticks) 1243system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1244system.cpu0.toL2Bus.respLayer1.occupancy 1230574902 # Layer occupancy (ticks) |
| 1211system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1245system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1212system.cpu0.toL2Bus.respLayer2.occupancy 7877498 # Layer occupancy (ticks) | 1246system.cpu0.toL2Bus.respLayer2.occupancy 7385992 # Layer occupancy (ticks) |
| 1213system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1247system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1214system.cpu0.toL2Bus.respLayer3.occupancy 36655495 # Layer occupancy (ticks) | 1248system.cpu0.toL2Bus.respLayer3.occupancy 88548223 # Layer occupancy (ticks) |
| 1215system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1249system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1216system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6510276 # number of hwpf identified 1217system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 198706 # number of hwpf that were already in mshr 1218system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6081219 # number of hwpf that were already in the cache 1219system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2295 # number of hwpf that were already in the prefetch queue | 1250system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17144913 # number of hwpf identified 1251system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425558 # number of hwpf that were already in mshr 1252system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16187872 # number of hwpf that were already in the cache 1253system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8427 # number of hwpf that were already in the prefetch queue |
| 1220system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1254system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1221system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2119 # number of hwpf removed because MSHR allocated 1222system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 225934 # number of hwpf issued 1223system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 452636 # number of hwpf spanning a virtual page | 1255system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6267 # number of hwpf removed because MSHR allocated 1256system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 516786 # number of hwpf issued 1257system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1326511 # number of hwpf spanning a virtual page |
| 1224system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1258system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1225system.cpu0.l2cache.tags.replacements 185629 # number of replacements 1226system.cpu0.l2cache.tags.tagsinuse 16039.205043 # Cycle average of tags in use 1227system.cpu0.l2cache.tags.total_refs 1209112 # Total number of references to valid blocks. 1228system.cpu0.l2cache.tags.sampled_refs 201843 # Sample count of references to valid blocks. 1229system.cpu0.l2cache.tags.avg_refs 5.990359 # Average number of references to valid blocks. 1230system.cpu0.l2cache.tags.warmup_cycle 5120294500 # Cycle when the warmup percentage was hit. 1231system.cpu0.l2cache.tags.occ_blocks::writebacks 4761.005363 # Average occupied blocks per requestor 1232system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 22.831562 # Average occupied blocks per requestor 1233system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.161164 # Average occupied blocks per requestor 1234system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2118.524351 # Average occupied blocks per requestor 1235system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9136.682602 # Average occupied blocks per requestor 1236system.cpu0.l2cache.tags.occ_percent::writebacks 0.290589 # Average percentage of cache occupancy 1237system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001394 # Average percentage of cache occupancy 1238system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy 1239system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.129304 # Average percentage of cache occupancy 1240system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.557659 # Average percentage of cache occupancy 1241system.cpu0.l2cache.tags.occ_percent::total 0.978955 # Average percentage of cache occupancy 1242system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8350 # Occupied blocks per task id 1243system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1244system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7848 # Occupied blocks per task id 1245system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id 1246system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 57 # Occupied blocks per task id 1247system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 864 # Occupied blocks per task id 1248system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5964 # Occupied blocks per task id 1249system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1431 # Occupied blocks per task id 1250system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 1251system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1252system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1253system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 1254system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 1255system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1438 # Occupied blocks per task id 1256system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5471 # Occupied blocks per task id 1257system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509644 # Percentage of cache occupancy per task id 1259system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id 1260system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.479004 # Percentage of cache occupancy per task id 1261system.cpu0.l2cache.tags.tag_accesses 22924468 # Number of tag accesses 1262system.cpu0.l2cache.tags.data_accesses 22924468 # Number of data accesses 1263system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29315 # number of ReadReq hits 1264system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5251 # number of ReadReq hits 1265system.cpu0.l2cache.ReadReq_hits::cpu0.inst 886043 # number of ReadReq hits 1266system.cpu0.l2cache.ReadReq_hits::total 920609 # number of ReadReq hits 1267system.cpu0.l2cache.Writeback_hits::writebacks 275708 # number of Writeback hits 1268system.cpu0.l2cache.Writeback_hits::total 275708 # number of Writeback hits 1269system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1811 # number of UpgradeReq hits 1270system.cpu0.l2cache.UpgradeReq_hits::total 1811 # number of UpgradeReq hits 1271system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 729 # number of SCUpgradeReq hits 1272system.cpu0.l2cache.SCUpgradeReq_hits::total 729 # number of SCUpgradeReq hits 1273system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107812 # number of ReadExReq hits 1274system.cpu0.l2cache.ReadExReq_hits::total 107812 # number of ReadExReq hits 1275system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29315 # number of demand (read+write) hits 1276system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5251 # number of demand (read+write) hits 1277system.cpu0.l2cache.demand_hits::cpu0.inst 993855 # number of demand (read+write) hits 1278system.cpu0.l2cache.demand_hits::total 1028421 # number of demand (read+write) hits 1279system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29315 # number of overall hits 1280system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5251 # number of overall hits 1281system.cpu0.l2cache.overall_hits::cpu0.inst 993855 # number of overall hits 1282system.cpu0.l2cache.overall_hits::total 1028421 # number of overall hits 1283system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 519 # number of ReadReq misses 1284system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses 1285system.cpu0.l2cache.ReadReq_misses::cpu0.inst 49158 # number of ReadReq misses 1286system.cpu0.l2cache.ReadReq_misses::total 49848 # number of ReadReq misses 1287system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 18945 # number of UpgradeReq misses 1288system.cpu0.l2cache.UpgradeReq_misses::total 18945 # number of UpgradeReq misses 1289system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 10134 # number of SCUpgradeReq misses 1290system.cpu0.l2cache.SCUpgradeReq_misses::total 10134 # number of SCUpgradeReq misses 1291system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 6 # number of SCUpgradeFailReq misses 1292system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1293system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 23532 # number of ReadExReq misses 1294system.cpu0.l2cache.ReadExReq_misses::total 23532 # number of ReadExReq misses 1295system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 519 # number of demand (read+write) misses 1296system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses 1297system.cpu0.l2cache.demand_misses::cpu0.inst 72690 # number of demand (read+write) misses 1298system.cpu0.l2cache.demand_misses::total 73380 # number of demand (read+write) misses 1299system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 519 # number of overall misses 1300system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses 1301system.cpu0.l2cache.overall_misses::cpu0.inst 72690 # number of overall misses 1302system.cpu0.l2cache.overall_misses::total 73380 # number of overall misses 1303system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11037500 # number of ReadReq miss cycles 1304system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3618999 # number of ReadReq miss cycles 1305system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1323798925 # number of ReadReq miss cycles 1306system.cpu0.l2cache.ReadReq_miss_latency::total 1338455424 # number of ReadReq miss cycles 1307system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312100526 # number of UpgradeReq miss cycles 1308system.cpu0.l2cache.UpgradeReq_miss_latency::total 312100526 # number of UpgradeReq miss cycles 1309system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 201024600 # number of SCUpgradeReq miss cycles 1310system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 201024600 # number of SCUpgradeReq miss cycles 1311system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1393500 # number of SCUpgradeFailReq miss cycles 1312system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1393500 # number of SCUpgradeFailReq miss cycles 1313system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 857324396 # number of ReadExReq miss cycles 1314system.cpu0.l2cache.ReadExReq_miss_latency::total 857324396 # number of ReadExReq miss cycles 1315system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11037500 # number of demand (read+write) miss cycles 1316system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3618999 # number of demand (read+write) miss cycles 1317system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2181123321 # number of demand (read+write) miss cycles 1318system.cpu0.l2cache.demand_miss_latency::total 2195779820 # number of demand (read+write) miss cycles 1319system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11037500 # number of overall miss cycles 1320system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3618999 # number of overall miss cycles 1321system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2181123321 # number of overall miss cycles 1322system.cpu0.l2cache.overall_miss_latency::total 2195779820 # number of overall miss cycles 1323system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 29834 # number of ReadReq accesses(hits+misses) 1324system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5422 # number of ReadReq accesses(hits+misses) 1325system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 935201 # number of ReadReq accesses(hits+misses) 1326system.cpu0.l2cache.ReadReq_accesses::total 970457 # number of ReadReq accesses(hits+misses) 1327system.cpu0.l2cache.Writeback_accesses::writebacks 275708 # number of Writeback accesses(hits+misses) 1328system.cpu0.l2cache.Writeback_accesses::total 275708 # number of Writeback accesses(hits+misses) 1329system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 20756 # number of UpgradeReq accesses(hits+misses) 1330system.cpu0.l2cache.UpgradeReq_accesses::total 20756 # number of UpgradeReq accesses(hits+misses) 1331system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 10863 # number of SCUpgradeReq accesses(hits+misses) 1332system.cpu0.l2cache.SCUpgradeReq_accesses::total 10863 # number of SCUpgradeReq accesses(hits+misses) 1333system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 6 # number of SCUpgradeFailReq accesses(hits+misses) 1334system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1335system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 131344 # number of ReadExReq accesses(hits+misses) 1336system.cpu0.l2cache.ReadExReq_accesses::total 131344 # number of ReadExReq accesses(hits+misses) 1337system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 29834 # number of demand (read+write) accesses 1338system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5422 # number of demand (read+write) accesses 1339system.cpu0.l2cache.demand_accesses::cpu0.inst 1066545 # number of demand (read+write) accesses 1340system.cpu0.l2cache.demand_accesses::total 1101801 # number of demand (read+write) accesses 1341system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 29834 # number of overall (read+write) accesses 1342system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5422 # number of overall (read+write) accesses 1343system.cpu0.l2cache.overall_accesses::cpu0.inst 1066545 # number of overall (read+write) accesses 1344system.cpu0.l2cache.overall_accesses::total 1101801 # number of overall (read+write) accesses 1345system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for ReadReq accesses 1346system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031538 # miss rate for ReadReq accesses 1347system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052564 # miss rate for ReadReq accesses 1348system.cpu0.l2cache.ReadReq_miss_rate::total 0.051365 # miss rate for ReadReq accesses 1349system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.912748 # miss rate for UpgradeReq accesses 1350system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.912748 # miss rate for UpgradeReq accesses 1351system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.932891 # miss rate for SCUpgradeReq accesses 1352system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.932891 # miss rate for SCUpgradeReq accesses 1353system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses 1354system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1355system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.179163 # miss rate for ReadExReq accesses 1356system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179163 # miss rate for ReadExReq accesses 1357system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for demand accesses 1358system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031538 # miss rate for demand accesses 1359system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.068155 # miss rate for demand accesses 1360system.cpu0.l2cache.demand_miss_rate::total 0.066600 # miss rate for demand accesses 1361system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for overall accesses 1362system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031538 # miss rate for overall accesses 1363system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.068155 # miss rate for overall accesses 1364system.cpu0.l2cache.overall_miss_rate::total 0.066600 # miss rate for overall accesses 1365system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average ReadReq miss latency 1366system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21163.736842 # average ReadReq miss latency 1367system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26929.470788 # average ReadReq miss latency 1368system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26850.734714 # average ReadReq miss latency 1369system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16474.031459 # average UpgradeReq miss latency 1370system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16474.031459 # average UpgradeReq miss latency 1371system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19836.648905 # average SCUpgradeReq miss latency 1372system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19836.648905 # average SCUpgradeReq miss latency 1373system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 232250 # average SCUpgradeFailReq miss latency 1374system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 232250 # average SCUpgradeFailReq miss latency 1375system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 36432.279279 # average ReadExReq miss latency 1376system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 36432.279279 # average ReadExReq miss latency 1377system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency 1378system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency 1379system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency 1380system.cpu0.l2cache.demand_avg_miss_latency::total 29923.409921 # average overall miss latency 1381system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency 1382system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency 1383system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency 1384system.cpu0.l2cache.overall_avg_miss_latency::total 29923.409921 # average overall miss latency 1385system.cpu0.l2cache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked | 1259system.cpu0.l2cache.tags.replacements 410501 # number of replacements 1260system.cpu0.l2cache.tags.tagsinuse 16214.104593 # Cycle average of tags in use 1261system.cpu0.l2cache.tags.total_refs 2982888 # Total number of references to valid blocks. 1262system.cpu0.l2cache.tags.sampled_refs 426752 # Sample count of references to valid blocks. 1263system.cpu0.l2cache.tags.avg_refs 6.989746 # Average number of references to valid blocks. 1264system.cpu0.l2cache.tags.warmup_cycle 2824483316500 # Cycle when the warmup percentage was hit. 1265system.cpu0.l2cache.tags.occ_blocks::writebacks 4342.913069 # Average occupied blocks per requestor 1266system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.461328 # Average occupied blocks per requestor 1267system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076713 # Average occupied blocks per requestor 1268system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2208.018647 # Average occupied blocks per requestor 1269system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9615.634836 # Average occupied blocks per requestor 1270system.cpu0.l2cache.tags.occ_percent::writebacks 0.265070 # Average percentage of cache occupancy 1271system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002897 # Average percentage of cache occupancy 1272system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 1273system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134767 # Average percentage of cache occupancy 1274system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.586892 # Average percentage of cache occupancy 1275system.cpu0.l2cache.tags.occ_percent::total 0.989630 # Average percentage of cache occupancy 1276system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8959 # Occupied blocks per task id 1277system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 1278system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7283 # Occupied blocks per task id 1279system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 66 # Occupied blocks per task id 1280system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id 1281system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2957 # Occupied blocks per task id 1282system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5162 # Occupied blocks per task id 1283system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 667 # Occupied blocks per task id 1284system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1285system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1286system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 1287system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 1288system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id 1289system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3107 # Occupied blocks per task id 1290system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3633 # Occupied blocks per task id 1291system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 224 # Occupied blocks per task id 1292system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546814 # Percentage of cache occupancy per task id 1293system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 1294system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444519 # Percentage of cache occupancy per task id 1295system.cpu0.l2cache.tags.tag_accesses 54811525 # Number of tag accesses 1296system.cpu0.l2cache.tags.data_accesses 54811525 # Number of data accesses 1297system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77296 # number of ReadReq hits 1298system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4241 # number of ReadReq hits 1299system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2365837 # number of ReadReq hits 1300system.cpu0.l2cache.ReadReq_hits::total 2447374 # number of ReadReq hits 1301system.cpu0.l2cache.Writeback_hits::writebacks 513053 # number of Writeback hits 1302system.cpu0.l2cache.Writeback_hits::total 513053 # number of Writeback hits 1303system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4545 # number of UpgradeReq hits 1304system.cpu0.l2cache.UpgradeReq_hits::total 4545 # number of UpgradeReq hits 1305system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2277 # number of SCUpgradeReq hits 1306system.cpu0.l2cache.SCUpgradeReq_hits::total 2277 # number of SCUpgradeReq hits 1307system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 221177 # number of ReadExReq hits 1308system.cpu0.l2cache.ReadExReq_hits::total 221177 # number of ReadExReq hits 1309system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77296 # number of demand (read+write) hits 1310system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4241 # number of demand (read+write) hits 1311system.cpu0.l2cache.demand_hits::cpu0.inst 2587014 # number of demand (read+write) hits 1312system.cpu0.l2cache.demand_hits::total 2668551 # number of demand (read+write) hits 1313system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77296 # number of overall hits 1314system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4241 # number of overall hits 1315system.cpu0.l2cache.overall_hits::cpu0.inst 2587014 # number of overall hits 1316system.cpu0.l2cache.overall_hits::total 2668551 # number of overall hits 1317system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 1021 # number of ReadReq misses 1318system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 181 # number of ReadReq misses 1319system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94620 # number of ReadReq misses 1320system.cpu0.l2cache.ReadReq_misses::total 95822 # number of ReadReq misses 1321system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 28011 # number of UpgradeReq misses 1322system.cpu0.l2cache.UpgradeReq_misses::total 28011 # number of UpgradeReq misses 1323system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 18233 # number of SCUpgradeReq misses 1324system.cpu0.l2cache.SCUpgradeReq_misses::total 18233 # number of SCUpgradeReq misses 1325system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46900 # number of ReadExReq misses 1326system.cpu0.l2cache.ReadExReq_misses::total 46900 # number of ReadExReq misses 1327system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 1021 # number of demand (read+write) misses 1328system.cpu0.l2cache.demand_misses::cpu0.itb.walker 181 # number of demand (read+write) misses 1329system.cpu0.l2cache.demand_misses::cpu0.inst 141520 # number of demand (read+write) misses 1330system.cpu0.l2cache.demand_misses::total 142722 # number of demand (read+write) misses 1331system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 1021 # number of overall misses 1332system.cpu0.l2cache.overall_misses::cpu0.itb.walker 181 # number of overall misses 1333system.cpu0.l2cache.overall_misses::cpu0.inst 141520 # number of overall misses 1334system.cpu0.l2cache.overall_misses::total 142722 # number of overall misses 1335system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 34165499 # number of ReadReq miss cycles 1336system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4027498 # number of ReadReq miss cycles 1337system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2870753873 # number of ReadReq miss cycles 1338system.cpu0.l2cache.ReadReq_miss_latency::total 2908946870 # number of ReadReq miss cycles 1339system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 500227988 # number of UpgradeReq miss cycles 1340system.cpu0.l2cache.UpgradeReq_miss_latency::total 500227988 # number of UpgradeReq miss cycles 1341system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 361106760 # number of SCUpgradeReq miss cycles 1342system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 361106760 # number of SCUpgradeReq miss cycles 1343system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 90500 # number of SCUpgradeFailReq miss cycles 1344system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 90500 # number of SCUpgradeFailReq miss cycles 1345system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1915708255 # number of ReadExReq miss cycles 1346system.cpu0.l2cache.ReadExReq_miss_latency::total 1915708255 # number of ReadExReq miss cycles 1347system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 34165499 # number of demand (read+write) miss cycles 1348system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4027498 # number of demand (read+write) miss cycles 1349system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4786462128 # number of demand (read+write) miss cycles 1350system.cpu0.l2cache.demand_miss_latency::total 4824655125 # number of demand (read+write) miss cycles 1351system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 34165499 # number of overall miss cycles 1352system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4027498 # number of overall miss cycles 1353system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4786462128 # number of overall miss cycles 1354system.cpu0.l2cache.overall_miss_latency::total 4824655125 # number of overall miss cycles 1355system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78317 # number of ReadReq accesses(hits+misses) 1356system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4422 # number of ReadReq accesses(hits+misses) 1357system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2460457 # number of ReadReq accesses(hits+misses) 1358system.cpu0.l2cache.ReadReq_accesses::total 2543196 # number of ReadReq accesses(hits+misses) 1359system.cpu0.l2cache.Writeback_accesses::writebacks 513053 # number of Writeback accesses(hits+misses) 1360system.cpu0.l2cache.Writeback_accesses::total 513053 # number of Writeback accesses(hits+misses) 1361system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32556 # number of UpgradeReq accesses(hits+misses) 1362system.cpu0.l2cache.UpgradeReq_accesses::total 32556 # number of UpgradeReq accesses(hits+misses) 1363system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20510 # number of SCUpgradeReq accesses(hits+misses) 1364system.cpu0.l2cache.SCUpgradeReq_accesses::total 20510 # number of SCUpgradeReq accesses(hits+misses) 1365system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 268077 # number of ReadExReq accesses(hits+misses) 1366system.cpu0.l2cache.ReadExReq_accesses::total 268077 # number of ReadExReq accesses(hits+misses) 1367system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78317 # number of demand (read+write) accesses 1368system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4422 # number of demand (read+write) accesses 1369system.cpu0.l2cache.demand_accesses::cpu0.inst 2728534 # number of demand (read+write) accesses 1370system.cpu0.l2cache.demand_accesses::total 2811273 # number of demand (read+write) accesses 1371system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78317 # number of overall (read+write) accesses 1372system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4422 # number of overall (read+write) accesses 1373system.cpu0.l2cache.overall_accesses::cpu0.inst 2728534 # number of overall (read+write) accesses 1374system.cpu0.l2cache.overall_accesses::total 2811273 # number of overall (read+write) accesses 1375system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for ReadReq accesses 1376system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040932 # miss rate for ReadReq accesses 1377system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.038456 # miss rate for ReadReq accesses 1378system.cpu0.l2cache.ReadReq_miss_rate::total 0.037678 # miss rate for ReadReq accesses 1379system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.860394 # miss rate for UpgradeReq accesses 1380system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.860394 # miss rate for UpgradeReq accesses 1381system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.888981 # miss rate for SCUpgradeReq accesses 1382system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.888981 # miss rate for SCUpgradeReq accesses 1383system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.174950 # miss rate for ReadExReq accesses 1384system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174950 # miss rate for ReadExReq accesses 1385system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for demand accesses 1386system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040932 # miss rate for demand accesses 1387system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051867 # miss rate for demand accesses 1388system.cpu0.l2cache.demand_miss_rate::total 0.050768 # miss rate for demand accesses 1389system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013037 # miss rate for overall accesses 1390system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040932 # miss rate for overall accesses 1391system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051867 # miss rate for overall accesses 1392system.cpu0.l2cache.overall_miss_rate::total 0.050768 # miss rate for overall accesses 1393system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average ReadReq miss latency 1394system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22251.370166 # average ReadReq miss latency 1395system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30339.821105 # average ReadReq miss latency 1396system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30357.818351 # average ReadReq miss latency 1397system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17858.269537 # average UpgradeReq miss latency 1398system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17858.269537 # average UpgradeReq miss latency 1399system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19805.120386 # average SCUpgradeReq miss latency 1400system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19805.120386 # average SCUpgradeReq miss latency 1401system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency 1402system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1403system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 40846.657889 # average ReadExReq miss latency 1404system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 40846.657889 # average ReadExReq miss latency 1405system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average overall miss latency 1406system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22251.370166 # average overall miss latency 1407system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33821.807010 # average overall miss latency 1408system.cpu0.l2cache.demand_avg_miss_latency::total 33804.564993 # average overall miss latency 1409system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33462.780607 # average overall miss latency 1410system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22251.370166 # average overall miss latency 1411system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33821.807010 # average overall miss latency 1412system.cpu0.l2cache.overall_avg_miss_latency::total 33804.564993 # average overall miss latency 1413system.cpu0.l2cache.blocked_cycles::no_mshrs 27297 # number of cycles access was blocked |
| 1386system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1414system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1387system.cpu0.l2cache.blocked::no_mshrs 30 # number of cycles access was blocked | 1415system.cpu0.l2cache.blocked::no_mshrs 390 # number of cycles access was blocked |
| 1388system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1416system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1389system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 24.300000 # average number of cycles each access was blocked | 1417system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 69.992308 # average number of cycles each access was blocked |
| 1390system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1391system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1392system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1418system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1419system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1420system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1393system.cpu0.l2cache.writebacks::writebacks 114449 # number of writebacks 1394system.cpu0.l2cache.writebacks::total 114449 # number of writebacks 1395system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2940 # number of ReadReq MSHR hits 1396system.cpu0.l2cache.ReadReq_mshr_hits::total 2940 # number of ReadReq MSHR hits 1397system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 800 # number of ReadExReq MSHR hits 1398system.cpu0.l2cache.ReadExReq_mshr_hits::total 800 # number of ReadExReq MSHR hits 1399system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3740 # number of demand (read+write) MSHR hits 1400system.cpu0.l2cache.demand_mshr_hits::total 3740 # number of demand (read+write) MSHR hits 1401system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3740 # number of overall MSHR hits 1402system.cpu0.l2cache.overall_mshr_hits::total 3740 # number of overall MSHR hits 1403system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 519 # number of ReadReq MSHR misses 1404system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 171 # number of ReadReq MSHR misses 1405system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 46218 # number of ReadReq MSHR misses 1406system.cpu0.l2cache.ReadReq_mshr_misses::total 46908 # number of ReadReq MSHR misses 1407system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 225933 # number of HardPFReq MSHR misses 1408system.cpu0.l2cache.HardPFReq_mshr_misses::total 225933 # number of HardPFReq MSHR misses 1409system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 18945 # number of UpgradeReq MSHR misses 1410system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18945 # number of UpgradeReq MSHR misses 1411system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 10134 # number of SCUpgradeReq MSHR misses 1412system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10134 # number of SCUpgradeReq MSHR misses 1413system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 6 # number of SCUpgradeFailReq MSHR misses 1414system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 1415system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 22732 # number of ReadExReq MSHR misses 1416system.cpu0.l2cache.ReadExReq_mshr_misses::total 22732 # number of ReadExReq MSHR misses 1417system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 519 # number of demand (read+write) MSHR misses 1418system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 171 # number of demand (read+write) MSHR misses 1419system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 68950 # number of demand (read+write) MSHR misses 1420system.cpu0.l2cache.demand_mshr_misses::total 69640 # number of demand (read+write) MSHR misses 1421system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 519 # number of overall MSHR misses 1422system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 171 # number of overall MSHR misses 1423system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 68950 # number of overall MSHR misses 1424system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 225933 # number of overall MSHR misses 1425system.cpu0.l2cache.overall_mshr_misses::total 295573 # number of overall MSHR misses 1426system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of ReadReq MSHR miss cycles 1427system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2421001 # number of ReadReq MSHR miss cycles 1428system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 946752983 # number of ReadReq MSHR miss cycles 1429system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 956578484 # number of ReadReq MSHR miss cycles 1430system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8634543726 # number of HardPFReq MSHR miss cycles 1431system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8634543726 # number of HardPFReq MSHR miss cycles 1432system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 342474562 # number of UpgradeReq MSHR miss cycles 1433system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 342474562 # number of UpgradeReq MSHR miss cycles 1434system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 146006456 # number of SCUpgradeReq MSHR miss cycles 1435system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 146006456 # number of SCUpgradeReq MSHR miss cycles 1436system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1155500 # number of SCUpgradeFailReq MSHR miss cycles 1437system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1155500 # number of SCUpgradeFailReq MSHR miss cycles 1438system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 598541592 # number of ReadExReq MSHR miss cycles 1439system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 598541592 # number of ReadExReq MSHR miss cycles 1440system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of demand (read+write) MSHR miss cycles 1441system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2421001 # number of demand (read+write) MSHR miss cycles 1442system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1545294575 # number of demand (read+write) MSHR miss cycles 1443system.cpu0.l2cache.demand_mshr_miss_latency::total 1555120076 # number of demand (read+write) MSHR miss cycles 1444system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7404500 # number of overall MSHR miss cycles 1445system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2421001 # number of overall MSHR miss cycles 1446system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1545294575 # number of overall MSHR miss cycles 1447system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8634543726 # number of overall MSHR miss cycles 1448system.cpu0.l2cache.overall_mshr_miss_latency::total 10189663802 # number of overall MSHR miss cycles 1449system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14161707249 # number of ReadReq MSHR uncacheable cycles 1450system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14161707249 # number of ReadReq MSHR uncacheable cycles 1451system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1312859997 # number of WriteReq MSHR uncacheable cycles 1452system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1312859997 # number of WriteReq MSHR uncacheable cycles 1453system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15474567246 # number of overall MSHR uncacheable cycles 1454system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15474567246 # number of overall MSHR uncacheable cycles 1455system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for ReadReq accesses 1456system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for ReadReq accesses 1457system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.049420 # mshr miss rate for ReadReq accesses 1458system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.048336 # mshr miss rate for ReadReq accesses | 1421system.cpu0.l2cache.writebacks::writebacks 214261 # number of writebacks 1422system.cpu0.l2cache.writebacks::total 214261 # number of writebacks 1423system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7719 # number of ReadReq MSHR hits 1424system.cpu0.l2cache.ReadReq_mshr_hits::total 7719 # number of ReadReq MSHR hits 1425system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3119 # number of ReadExReq MSHR hits 1426system.cpu0.l2cache.ReadExReq_mshr_hits::total 3119 # number of ReadExReq MSHR hits 1427system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10838 # number of demand (read+write) MSHR hits 1428system.cpu0.l2cache.demand_mshr_hits::total 10838 # number of demand (read+write) MSHR hits 1429system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10838 # number of overall MSHR hits 1430system.cpu0.l2cache.overall_mshr_hits::total 10838 # number of overall MSHR hits 1431system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 1021 # number of ReadReq MSHR misses 1432system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 181 # number of ReadReq MSHR misses 1433system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86901 # number of ReadReq MSHR misses 1434system.cpu0.l2cache.ReadReq_mshr_misses::total 88103 # number of ReadReq MSHR misses 1435system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 516784 # number of HardPFReq MSHR misses 1436system.cpu0.l2cache.HardPFReq_mshr_misses::total 516784 # number of HardPFReq MSHR misses 1437system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 28011 # number of UpgradeReq MSHR misses 1438system.cpu0.l2cache.UpgradeReq_mshr_misses::total 28011 # number of UpgradeReq MSHR misses 1439system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 18233 # number of SCUpgradeReq MSHR misses 1440system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18233 # number of SCUpgradeReq MSHR misses 1441system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43781 # number of ReadExReq MSHR misses 1442system.cpu0.l2cache.ReadExReq_mshr_misses::total 43781 # number of ReadExReq MSHR misses 1443system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 1021 # number of demand (read+write) MSHR misses 1444system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 181 # number of demand (read+write) MSHR misses 1445system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 130682 # number of demand (read+write) MSHR misses 1446system.cpu0.l2cache.demand_mshr_misses::total 131884 # number of demand (read+write) MSHR misses 1447system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 1021 # number of overall MSHR misses 1448system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 181 # number of overall MSHR misses 1449system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 130682 # number of overall MSHR misses 1450system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 516784 # number of overall MSHR misses 1451system.cpu0.l2cache.overall_mshr_misses::total 648668 # number of overall MSHR misses 1452system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of ReadReq MSHR miss cycles 1453system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2760498 # number of ReadReq MSHR miss cycles 1454system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2099218995 # number of ReadReq MSHR miss cycles 1455system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2128978496 # number of ReadReq MSHR miss cycles 1456system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21179021871 # number of HardPFReq MSHR miss cycles 1457system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21179021871 # number of HardPFReq MSHR miss cycles 1458system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 474290503 # number of UpgradeReq MSHR miss cycles 1459system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 474290503 # number of UpgradeReq MSHR miss cycles 1460system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 241043533 # number of SCUpgradeReq MSHR miss cycles 1461system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 241043533 # number of SCUpgradeReq MSHR miss cycles 1462system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 69500 # number of SCUpgradeFailReq MSHR miss cycles 1463system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 69500 # number of SCUpgradeFailReq MSHR miss cycles 1464system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1189749710 # number of ReadExReq MSHR miss cycles 1465system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1189749710 # number of ReadExReq MSHR miss cycles 1466system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of demand (read+write) MSHR miss cycles 1467system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2760498 # number of demand (read+write) MSHR miss cycles 1468system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3288968705 # number of demand (read+write) MSHR miss cycles 1469system.cpu0.l2cache.demand_mshr_miss_latency::total 3318728206 # number of demand (read+write) MSHR miss cycles 1470system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 26999003 # number of overall MSHR miss cycles 1471system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2760498 # number of overall MSHR miss cycles 1472system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3288968705 # number of overall MSHR miss cycles 1473system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21179021871 # number of overall MSHR miss cycles 1474system.cpu0.l2cache.overall_mshr_miss_latency::total 24497750077 # number of overall MSHR miss cycles 1475system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6107809749 # number of ReadReq MSHR uncacheable cycles 1476system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6107809749 # number of ReadReq MSHR uncacheable cycles 1477system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4518638513 # number of WriteReq MSHR uncacheable cycles 1478system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4518638513 # number of WriteReq MSHR uncacheable cycles 1479system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10626448262 # number of overall MSHR uncacheable cycles 1480system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10626448262 # number of overall MSHR uncacheable cycles 1481system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for ReadReq accesses 1482system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for ReadReq accesses 1483system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.035319 # mshr miss rate for ReadReq accesses 1484system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034643 # mshr miss rate for ReadReq accesses |
| 1459system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1460system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1485system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1486system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1461system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.912748 # mshr miss rate for UpgradeReq accesses 1462system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.912748 # mshr miss rate for UpgradeReq accesses 1463system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.932891 # mshr miss rate for SCUpgradeReq accesses 1464system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.932891 # mshr miss rate for SCUpgradeReq accesses 1465system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 1466system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1467system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.173072 # mshr miss rate for ReadExReq accesses 1468system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.173072 # mshr miss rate for ReadExReq accesses 1469system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for demand accesses 1470system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for demand accesses 1471system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for demand accesses 1472system.cpu0.l2cache.demand_mshr_miss_rate::total 0.063206 # mshr miss rate for demand accesses 1473system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017396 # mshr miss rate for overall accesses 1474system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031538 # mshr miss rate for overall accesses 1475system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for overall accesses | 1487system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.860394 # mshr miss rate for UpgradeReq accesses 1488system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.860394 # mshr miss rate for UpgradeReq accesses 1489system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888981 # mshr miss rate for SCUpgradeReq accesses 1490system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888981 # mshr miss rate for SCUpgradeReq accesses 1491system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.163315 # mshr miss rate for ReadExReq accesses 1492system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163315 # mshr miss rate for ReadExReq accesses 1493system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for demand accesses 1494system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for demand accesses 1495system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047895 # mshr miss rate for demand accesses 1496system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046913 # mshr miss rate for demand accesses 1497system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for overall accesses 1498system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for overall accesses 1499system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047895 # mshr miss rate for overall accesses |
| 1476system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1500system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1477system.cpu0.l2cache.overall_mshr_miss_rate::total 0.268264 # mshr miss rate for overall accesses 1478system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average ReadReq mshr miss latency 1479system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average ReadReq mshr miss latency 1480system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20484.507832 # average ReadReq mshr miss latency 1481system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20392.651232 # average ReadReq mshr miss latency 1482system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average HardPFReq mshr miss latency 1483system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 38217.275591 # average HardPFReq mshr miss latency 1484system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18077.305991 # average UpgradeReq mshr miss latency 1485system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18077.305991 # average UpgradeReq mshr miss latency 1486system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14407.583975 # average SCUpgradeReq mshr miss latency 1487system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14407.583975 # average SCUpgradeReq mshr miss latency 1488system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 192583.333333 # average SCUpgradeFailReq mshr miss latency 1489system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192583.333333 # average SCUpgradeFailReq mshr miss latency 1490system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 26330.353335 # average ReadExReq mshr miss latency 1491system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26330.353335 # average ReadExReq mshr miss latency 1492system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency 1493system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency 1494system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency 1495system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22330.845434 # average overall mshr miss latency 1496system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency 1497system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency 1498system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency 1499system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average overall mshr miss latency 1500system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34474.271337 # average overall mshr miss latency | 1501system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230738 # mshr miss rate for overall accesses 1502system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average ReadReq mshr miss latency 1503system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average ReadReq mshr miss latency 1504system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24156.442331 # average ReadReq mshr miss latency 1505system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24164.653826 # average ReadReq mshr miss latency 1506system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275 # average HardPFReq mshr miss latency 1507system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40982.348275 # average HardPFReq mshr miss latency 1508system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16932.294563 # average UpgradeReq mshr miss latency 1509system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16932.294563 # average UpgradeReq mshr miss latency 1510system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13220.179510 # average SCUpgradeReq mshr miss latency 1511system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13220.179510 # average SCUpgradeReq mshr miss latency 1512system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency 1513system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1514system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27175.023640 # average ReadExReq mshr miss latency 1515system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27175.023640 # average ReadExReq mshr miss latency 1516system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average overall mshr miss latency 1517system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average overall mshr miss latency 1518system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency 1519system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25163.994162 # average overall mshr miss latency 1520system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average overall mshr miss latency 1521system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # average overall mshr miss latency 1522system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25167.725509 # average overall mshr miss latency 1523system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40982.348275 # average overall mshr miss latency 1524system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37766.238009 # average overall mshr miss latency |
| 1501system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1502system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1503system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1504system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1505system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1506system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1507system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1525system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1526system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1527system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1528system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1529system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1530system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1531system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1508system.cpu0.dcache.tags.replacements 362294 # number of replacements 1509system.cpu0.dcache.tags.tagsinuse 472.891448 # Cycle average of tags in use 1510system.cpu0.dcache.tags.total_refs 11414416 # Total number of references to valid blocks. 1511system.cpu0.dcache.tags.sampled_refs 362806 # Sample count of references to valid blocks. 1512system.cpu0.dcache.tags.avg_refs 31.461486 # Average number of references to valid blocks. 1513system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit. 1514system.cpu0.dcache.tags.occ_blocks::cpu0.inst 472.891448 # Average occupied blocks per requestor 1515system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.923616 # Average percentage of cache occupancy 1516system.cpu0.dcache.tags.occ_percent::total 0.923616 # Average percentage of cache occupancy | 1532system.cpu0.dcache.tags.replacements 712097 # number of replacements 1533system.cpu0.dcache.tags.tagsinuse 497.191982 # Cycle average of tags in use 1534system.cpu0.dcache.tags.total_refs 40404438 # Total number of references to valid blocks. 1535system.cpu0.dcache.tags.sampled_refs 712609 # Sample count of references to valid blocks. 1536system.cpu0.dcache.tags.avg_refs 56.699309 # Average number of references to valid blocks. 1537system.cpu0.dcache.tags.warmup_cycle 306793500 # Cycle when the warmup percentage was hit. 1538system.cpu0.dcache.tags.occ_blocks::cpu0.inst 497.191982 # Average occupied blocks per requestor 1539system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.971078 # Average percentage of cache occupancy 1540system.cpu0.dcache.tags.occ_percent::total 0.971078 # Average percentage of cache occupancy |
| 1517system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1541system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1518system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id 1519system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 1520system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id 1521system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 1542system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id 1543system.cpu0.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id 1544system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id |
| 1522system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1545system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1523system.cpu0.dcache.tags.tag_accesses 24357333 # Number of tag accesses 1524system.cpu0.dcache.tags.data_accesses 24357333 # Number of data accesses 1525system.cpu0.dcache.ReadReq_hits::cpu0.inst 5805631 # number of ReadReq hits 1526system.cpu0.dcache.ReadReq_hits::total 5805631 # number of ReadReq hits 1527system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275579 # number of WriteReq hits 1528system.cpu0.dcache.WriteReq_hits::total 5275579 # number of WriteReq hits 1529system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147422 # number of LoadLockedReq hits 1530system.cpu0.dcache.LoadLockedReq_hits::total 147422 # number of LoadLockedReq hits 1531system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146630 # number of StoreCondReq hits 1532system.cpu0.dcache.StoreCondReq_hits::total 146630 # number of StoreCondReq hits 1533system.cpu0.dcache.demand_hits::cpu0.inst 11081210 # number of demand (read+write) hits 1534system.cpu0.dcache.demand_hits::total 11081210 # number of demand (read+write) hits 1535system.cpu0.dcache.overall_hits::cpu0.inst 11081210 # number of overall hits 1536system.cpu0.dcache.overall_hits::total 11081210 # number of overall hits 1537system.cpu0.dcache.ReadReq_misses::cpu0.inst 308329 # number of ReadReq misses 1538system.cpu0.dcache.ReadReq_misses::total 308329 # number of ReadReq misses 1539system.cpu0.dcache.WriteReq_misses::cpu0.inst 276386 # number of WriteReq misses 1540system.cpu0.dcache.WriteReq_misses::total 276386 # number of WriteReq misses 1541system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 10191 # number of LoadLockedReq misses 1542system.cpu0.dcache.LoadLockedReq_misses::total 10191 # number of LoadLockedReq misses 1543system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 10869 # number of StoreCondReq misses 1544system.cpu0.dcache.StoreCondReq_misses::total 10869 # number of StoreCondReq misses 1545system.cpu0.dcache.demand_misses::cpu0.inst 584715 # number of demand (read+write) misses 1546system.cpu0.dcache.demand_misses::total 584715 # number of demand (read+write) misses 1547system.cpu0.dcache.overall_misses::cpu0.inst 584715 # number of overall misses 1548system.cpu0.dcache.overall_misses::total 584715 # number of overall misses 1549system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3680932639 # number of ReadReq miss cycles 1550system.cpu0.dcache.ReadReq_miss_latency::total 3680932639 # number of ReadReq miss cycles 1551system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 4210104069 # number of WriteReq miss cycles 1552system.cpu0.dcache.WriteReq_miss_latency::total 4210104069 # number of WriteReq miss cycles 1553system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 167480751 # number of LoadLockedReq miss cycles 1554system.cpu0.dcache.LoadLockedReq_miss_latency::total 167480751 # number of LoadLockedReq miss cycles 1555system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 254581965 # number of StoreCondReq miss cycles 1556system.cpu0.dcache.StoreCondReq_miss_latency::total 254581965 # number of StoreCondReq miss cycles 1557system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1495500 # number of StoreCondFailReq miss cycles 1558system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1495500 # number of StoreCondFailReq miss cycles 1559system.cpu0.dcache.demand_miss_latency::cpu0.inst 7891036708 # number of demand (read+write) miss cycles 1560system.cpu0.dcache.demand_miss_latency::total 7891036708 # number of demand (read+write) miss cycles 1561system.cpu0.dcache.overall_miss_latency::cpu0.inst 7891036708 # number of overall miss cycles 1562system.cpu0.dcache.overall_miss_latency::total 7891036708 # number of overall miss cycles 1563system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113960 # number of ReadReq accesses(hits+misses) 1564system.cpu0.dcache.ReadReq_accesses::total 6113960 # number of ReadReq accesses(hits+misses) 1565system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5551965 # number of WriteReq accesses(hits+misses) 1566system.cpu0.dcache.WriteReq_accesses::total 5551965 # number of WriteReq accesses(hits+misses) 1567system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157613 # number of LoadLockedReq accesses(hits+misses) 1568system.cpu0.dcache.LoadLockedReq_accesses::total 157613 # number of LoadLockedReq accesses(hits+misses) 1569system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157499 # number of StoreCondReq accesses(hits+misses) 1570system.cpu0.dcache.StoreCondReq_accesses::total 157499 # number of StoreCondReq accesses(hits+misses) 1571system.cpu0.dcache.demand_accesses::cpu0.inst 11665925 # number of demand (read+write) accesses 1572system.cpu0.dcache.demand_accesses::total 11665925 # number of demand (read+write) accesses 1573system.cpu0.dcache.overall_accesses::cpu0.inst 11665925 # number of overall (read+write) accesses 1574system.cpu0.dcache.overall_accesses::total 11665925 # number of overall (read+write) accesses 1575system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050430 # miss rate for ReadReq accesses 1576system.cpu0.dcache.ReadReq_miss_rate::total 0.050430 # miss rate for ReadReq accesses 1577system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049782 # miss rate for WriteReq accesses 1578system.cpu0.dcache.WriteReq_miss_rate::total 0.049782 # miss rate for WriteReq accesses 1579system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064658 # miss rate for LoadLockedReq accesses 1580system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064658 # miss rate for LoadLockedReq accesses 1581system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069010 # miss rate for StoreCondReq accesses 1582system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069010 # miss rate for StoreCondReq accesses 1583system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050122 # miss rate for demand accesses 1584system.cpu0.dcache.demand_miss_rate::total 0.050122 # miss rate for demand accesses 1585system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050122 # miss rate for overall accesses 1586system.cpu0.dcache.overall_miss_rate::total 0.050122 # miss rate for overall accesses 1587system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11938.327692 # average ReadReq miss latency 1588system.cpu0.dcache.ReadReq_avg_miss_latency::total 11938.327692 # average ReadReq miss latency 1589system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15232.696551 # average WriteReq miss latency 1590system.cpu0.dcache.WriteReq_avg_miss_latency::total 15232.696551 # average WriteReq miss latency 1591system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16434.182220 # average LoadLockedReq miss latency 1592system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16434.182220 # average LoadLockedReq miss latency 1593system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23422.758763 # average StoreCondReq miss latency 1594system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23422.758763 # average StoreCondReq miss latency | 1546system.cpu0.dcache.tags.tag_accesses 83631959 # Number of tag accesses 1547system.cpu0.dcache.tags.data_accesses 83631959 # Number of data accesses 1548system.cpu0.dcache.ReadReq_hits::cpu0.inst 22807107 # number of ReadReq hits 1549system.cpu0.dcache.ReadReq_hits::total 22807107 # number of ReadReq hits 1550system.cpu0.dcache.WriteReq_hits::cpu0.inst 16791710 # number of WriteReq hits 1551system.cpu0.dcache.WriteReq_hits::total 16791710 # number of WriteReq hits 1552system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 380026 # number of LoadLockedReq hits 1553system.cpu0.dcache.LoadLockedReq_hits::total 380026 # number of LoadLockedReq hits 1554system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 361110 # number of StoreCondReq hits 1555system.cpu0.dcache.StoreCondReq_hits::total 361110 # number of StoreCondReq hits 1556system.cpu0.dcache.demand_hits::cpu0.inst 39598817 # number of demand (read+write) hits 1557system.cpu0.dcache.demand_hits::total 39598817 # number of demand (read+write) hits 1558system.cpu0.dcache.overall_hits::cpu0.inst 39598817 # number of overall hits 1559system.cpu0.dcache.overall_hits::total 39598817 # number of overall hits 1560system.cpu0.dcache.ReadReq_misses::cpu0.inst 535335 # number of ReadReq misses 1561system.cpu0.dcache.ReadReq_misses::total 535335 # number of ReadReq misses 1562system.cpu0.dcache.WriteReq_misses::cpu0.inst 529873 # number of WriteReq misses 1563system.cpu0.dcache.WriteReq_misses::total 529873 # number of WriteReq misses 1564system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6515 # number of LoadLockedReq misses 1565system.cpu0.dcache.LoadLockedReq_misses::total 6515 # number of LoadLockedReq misses 1566system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20510 # number of StoreCondReq misses 1567system.cpu0.dcache.StoreCondReq_misses::total 20510 # number of StoreCondReq misses 1568system.cpu0.dcache.demand_misses::cpu0.inst 1065208 # number of demand (read+write) misses 1569system.cpu0.dcache.demand_misses::total 1065208 # number of demand (read+write) misses 1570system.cpu0.dcache.overall_misses::cpu0.inst 1065208 # number of overall misses 1571system.cpu0.dcache.overall_misses::total 1065208 # number of overall misses 1572system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6583386279 # number of ReadReq miss cycles 1573system.cpu0.dcache.ReadReq_miss_latency::total 6583386279 # number of ReadReq miss cycles 1574system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 7974270273 # number of WriteReq miss cycles 1575system.cpu0.dcache.WriteReq_miss_latency::total 7974270273 # number of WriteReq miss cycles 1576system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 107544752 # number of LoadLockedReq miss cycles 1577system.cpu0.dcache.LoadLockedReq_miss_latency::total 107544752 # number of LoadLockedReq miss cycles 1578system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 444281550 # number of StoreCondReq miss cycles 1579system.cpu0.dcache.StoreCondReq_miss_latency::total 444281550 # number of StoreCondReq miss cycles 1580system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 99500 # number of StoreCondFailReq miss cycles 1581system.cpu0.dcache.StoreCondFailReq_miss_latency::total 99500 # number of StoreCondFailReq miss cycles 1582system.cpu0.dcache.demand_miss_latency::cpu0.inst 14557656552 # number of demand (read+write) miss cycles 1583system.cpu0.dcache.demand_miss_latency::total 14557656552 # number of demand (read+write) miss cycles 1584system.cpu0.dcache.overall_miss_latency::cpu0.inst 14557656552 # number of overall miss cycles 1585system.cpu0.dcache.overall_miss_latency::total 14557656552 # number of overall miss cycles 1586system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23342442 # number of ReadReq accesses(hits+misses) 1587system.cpu0.dcache.ReadReq_accesses::total 23342442 # number of ReadReq accesses(hits+misses) 1588system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17321583 # number of WriteReq accesses(hits+misses) 1589system.cpu0.dcache.WriteReq_accesses::total 17321583 # number of WriteReq accesses(hits+misses) 1590system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 386541 # number of LoadLockedReq accesses(hits+misses) 1591system.cpu0.dcache.LoadLockedReq_accesses::total 386541 # number of LoadLockedReq accesses(hits+misses) 1592system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 381620 # number of StoreCondReq accesses(hits+misses) 1593system.cpu0.dcache.StoreCondReq_accesses::total 381620 # number of StoreCondReq accesses(hits+misses) 1594system.cpu0.dcache.demand_accesses::cpu0.inst 40664025 # number of demand (read+write) accesses 1595system.cpu0.dcache.demand_accesses::total 40664025 # number of demand (read+write) accesses 1596system.cpu0.dcache.overall_accesses::cpu0.inst 40664025 # number of overall (read+write) accesses 1597system.cpu0.dcache.overall_accesses::total 40664025 # number of overall (read+write) accesses 1598system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.022934 # miss rate for ReadReq accesses 1599system.cpu0.dcache.ReadReq_miss_rate::total 0.022934 # miss rate for ReadReq accesses 1600system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030590 # miss rate for WriteReq accesses 1601system.cpu0.dcache.WriteReq_miss_rate::total 0.030590 # miss rate for WriteReq accesses 1602system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016855 # miss rate for LoadLockedReq accesses 1603system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016855 # miss rate for LoadLockedReq accesses 1604system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.053745 # miss rate for StoreCondReq accesses 1605system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053745 # miss rate for StoreCondReq accesses 1606system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026195 # miss rate for demand accesses 1607system.cpu0.dcache.demand_miss_rate::total 0.026195 # miss rate for demand accesses 1608system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026195 # miss rate for overall accesses 1609system.cpu0.dcache.overall_miss_rate::total 0.026195 # miss rate for overall accesses 1610system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12297.694488 # average ReadReq miss latency 1611system.cpu0.dcache.ReadReq_avg_miss_latency::total 12297.694488 # average ReadReq miss latency 1612system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15049.399145 # average WriteReq miss latency 1613system.cpu0.dcache.WriteReq_avg_miss_latency::total 15049.399145 # average WriteReq miss latency 1614system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16507.252801 # average LoadLockedReq miss latency 1615system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16507.252801 # average LoadLockedReq miss latency 1616system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21661.704047 # average StoreCondReq miss latency 1617system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21661.704047 # average StoreCondReq miss latency |
| 1595system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 1596system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1618system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 1619system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1597system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency 1598system.cpu0.dcache.demand_avg_miss_latency::total 13495.526381 # average overall miss latency 1599system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency 1600system.cpu0.dcache.overall_avg_miss_latency::total 13495.526381 # average overall miss latency | 1620system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13666.491945 # average overall miss latency 1621system.cpu0.dcache.demand_avg_miss_latency::total 13666.491945 # average overall miss latency 1622system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13666.491945 # average overall miss latency 1623system.cpu0.dcache.overall_avg_miss_latency::total 13666.491945 # average overall miss latency |
| 1601system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1602system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1603system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1604system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1605system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1606system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1607system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1608system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1624system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1625system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1626system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1627system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1628system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1629system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1630system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1631system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1609system.cpu0.dcache.writebacks::writebacks 275708 # number of writebacks 1610system.cpu0.dcache.writebacks::total 275708 # number of writebacks 1611system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54553 # number of ReadReq MSHR hits 1612system.cpu0.dcache.ReadReq_mshr_hits::total 54553 # number of ReadReq MSHR hits 1613system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124298 # number of WriteReq MSHR hits 1614system.cpu0.dcache.WriteReq_mshr_hits::total 124298 # number of WriteReq MSHR hits 1615system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits 1616system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits 1617system.cpu0.dcache.demand_mshr_hits::cpu0.inst 178851 # number of demand (read+write) MSHR hits 1618system.cpu0.dcache.demand_mshr_hits::total 178851 # number of demand (read+write) MSHR hits 1619system.cpu0.dcache.overall_mshr_hits::cpu0.inst 178851 # number of overall MSHR hits 1620system.cpu0.dcache.overall_mshr_hits::total 178851 # number of overall MSHR hits 1621system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 253776 # number of ReadReq MSHR misses 1622system.cpu0.dcache.ReadReq_mshr_misses::total 253776 # number of ReadReq MSHR misses 1623system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152088 # number of WriteReq MSHR misses 1624system.cpu0.dcache.WriteReq_mshr_misses::total 152088 # number of WriteReq MSHR misses 1625system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10117 # number of LoadLockedReq MSHR misses 1626system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10117 # number of LoadLockedReq MSHR misses 1627system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10869 # number of StoreCondReq MSHR misses 1628system.cpu0.dcache.StoreCondReq_mshr_misses::total 10869 # number of StoreCondReq MSHR misses 1629system.cpu0.dcache.demand_mshr_misses::cpu0.inst 405864 # number of demand (read+write) MSHR misses 1630system.cpu0.dcache.demand_mshr_misses::total 405864 # number of demand (read+write) MSHR misses 1631system.cpu0.dcache.overall_mshr_misses::cpu0.inst 405864 # number of overall MSHR misses 1632system.cpu0.dcache.overall_mshr_misses::total 405864 # number of overall MSHR misses 1633system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2514607539 # number of ReadReq MSHR miss cycles 1634system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2514607539 # number of ReadReq MSHR miss cycles 1635system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2141849701 # number of WriteReq MSHR miss cycles 1636system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2141849701 # number of WriteReq MSHR miss cycles 1637system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 146522249 # number of LoadLockedReq MSHR miss cycles 1638system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146522249 # number of LoadLockedReq MSHR miss cycles 1639system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231876035 # number of StoreCondReq MSHR miss cycles 1640system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231876035 # number of StoreCondReq MSHR miss cycles 1641system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1427500 # number of StoreCondFailReq MSHR miss cycles 1642system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1427500 # number of StoreCondFailReq MSHR miss cycles 1643system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4656457240 # number of demand (read+write) MSHR miss cycles 1644system.cpu0.dcache.demand_mshr_miss_latency::total 4656457240 # number of demand (read+write) MSHR miss cycles 1645system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4656457240 # number of overall MSHR miss cycles 1646system.cpu0.dcache.overall_mshr_miss_latency::total 4656457240 # number of overall MSHR miss cycles 1647system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14652229736 # number of ReadReq MSHR uncacheable cycles 1648system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14652229736 # number of ReadReq MSHR uncacheable cycles 1649system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394826498 # number of WriteReq MSHR uncacheable cycles 1650system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394826498 # number of WriteReq MSHR uncacheable cycles 1651system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16047056234 # number of overall MSHR uncacheable cycles 1652system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16047056234 # number of overall MSHR uncacheable cycles 1653system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041508 # mshr miss rate for ReadReq accesses 1654system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041508 # mshr miss rate for ReadReq accesses 1655system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027394 # mshr miss rate for WriteReq accesses 1656system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027394 # mshr miss rate for WriteReq accesses 1657system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064189 # mshr miss rate for LoadLockedReq accesses 1658system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064189 # mshr miss rate for LoadLockedReq accesses 1659system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069010 # mshr miss rate for StoreCondReq accesses 1660system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069010 # mshr miss rate for StoreCondReq accesses 1661system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for demand accesses 1662system.cpu0.dcache.demand_mshr_miss_rate::total 0.034791 # mshr miss rate for demand accesses 1663system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for overall accesses 1664system.cpu0.dcache.overall_mshr_miss_rate::total 0.034791 # mshr miss rate for overall accesses 1665system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9908.768122 # average ReadReq mshr miss latency 1666system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9908.768122 # average ReadReq mshr miss latency 1667system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14082.963159 # average WriteReq mshr miss latency 1668system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14082.963159 # average WriteReq mshr miss latency 1669system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14482.776416 # average LoadLockedReq mshr miss latency 1670system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14482.776416 # average LoadLockedReq mshr miss latency 1671system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21333.704573 # average StoreCondReq mshr miss latency 1672system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21333.704573 # average StoreCondReq mshr miss latency | 1632system.cpu0.dcache.writebacks::writebacks 513055 # number of writebacks 1633system.cpu0.dcache.writebacks::total 513055 # number of writebacks 1634system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42339 # number of ReadReq MSHR hits 1635system.cpu0.dcache.ReadReq_mshr_hits::total 42339 # number of ReadReq MSHR hits 1636system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 229244 # number of WriteReq MSHR hits 1637system.cpu0.dcache.WriteReq_mshr_hits::total 229244 # number of WriteReq MSHR hits 1638system.cpu0.dcache.demand_mshr_hits::cpu0.inst 271583 # number of demand (read+write) MSHR hits 1639system.cpu0.dcache.demand_mshr_hits::total 271583 # number of demand (read+write) MSHR hits 1640system.cpu0.dcache.overall_mshr_hits::cpu0.inst 271583 # number of overall MSHR hits 1641system.cpu0.dcache.overall_mshr_hits::total 271583 # number of overall MSHR hits 1642system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 492996 # number of ReadReq MSHR misses 1643system.cpu0.dcache.ReadReq_mshr_misses::total 492996 # number of ReadReq MSHR misses 1644system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 300629 # number of WriteReq MSHR misses 1645system.cpu0.dcache.WriteReq_mshr_misses::total 300629 # number of WriteReq MSHR misses 1646system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6515 # number of LoadLockedReq MSHR misses 1647system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6515 # number of LoadLockedReq MSHR misses 1648system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20510 # number of StoreCondReq MSHR misses 1649system.cpu0.dcache.StoreCondReq_mshr_misses::total 20510 # number of StoreCondReq MSHR misses 1650system.cpu0.dcache.demand_mshr_misses::cpu0.inst 793625 # number of demand (read+write) MSHR misses 1651system.cpu0.dcache.demand_mshr_misses::total 793625 # number of demand (read+write) MSHR misses 1652system.cpu0.dcache.overall_mshr_misses::cpu0.inst 793625 # number of overall MSHR misses 1653system.cpu0.dcache.overall_mshr_misses::total 793625 # number of overall MSHR misses 1654system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5093716162 # number of ReadReq MSHR miss cycles 1655system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5093716162 # number of ReadReq MSHR miss cycles 1656system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4246170249 # number of WriteReq MSHR miss cycles 1657system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4246170249 # number of WriteReq MSHR miss cycles 1658system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 94499248 # number of LoadLockedReq MSHR miss cycles 1659system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94499248 # number of LoadLockedReq MSHR miss cycles 1660system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 402814450 # number of StoreCondReq MSHR miss cycles 1661system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 402814450 # number of StoreCondReq MSHR miss cycles 1662system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 93500 # number of StoreCondFailReq MSHR miss cycles 1663system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 93500 # number of StoreCondFailReq MSHR miss cycles 1664system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9339886411 # number of demand (read+write) MSHR miss cycles 1665system.cpu0.dcache.demand_mshr_miss_latency::total 9339886411 # number of demand (read+write) MSHR miss cycles 1666system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9339886411 # number of overall MSHR miss cycles 1667system.cpu0.dcache.overall_mshr_miss_latency::total 9339886411 # number of overall MSHR miss cycles 1668system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6120470998 # number of ReadReq MSHR uncacheable cycles 1669system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6120470998 # number of ReadReq MSHR uncacheable cycles 1670system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4732689487 # number of WriteReq MSHR uncacheable cycles 1671system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4732689487 # number of WriteReq MSHR uncacheable cycles 1672system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10853160485 # number of overall MSHR uncacheable cycles 1673system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10853160485 # number of overall MSHR uncacheable cycles 1674system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021120 # mshr miss rate for ReadReq accesses 1675system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021120 # mshr miss rate for ReadReq accesses 1676system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017356 # mshr miss rate for WriteReq accesses 1677system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017356 # mshr miss rate for WriteReq accesses 1678system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016855 # mshr miss rate for LoadLockedReq accesses 1679system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016855 # mshr miss rate for LoadLockedReq accesses 1680system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.053745 # mshr miss rate for StoreCondReq accesses 1681system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053745 # mshr miss rate for StoreCondReq accesses 1682system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for demand accesses 1683system.cpu0.dcache.demand_mshr_miss_rate::total 0.019517 # mshr miss rate for demand accesses 1684system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for overall accesses 1685system.cpu0.dcache.overall_mshr_miss_rate::total 0.019517 # mshr miss rate for overall accesses 1686system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10332.165295 # average ReadReq mshr miss latency 1687system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10332.165295 # average ReadReq mshr miss latency 1688system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14124.286908 # average WriteReq mshr miss latency 1689system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14124.286908 # average WriteReq mshr miss latency 1690system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14504.873062 # average LoadLockedReq mshr miss latency 1691system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.873062 # average LoadLockedReq mshr miss latency 1692system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19639.904924 # average StoreCondReq mshr miss latency 1693system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19639.904924 # average StoreCondReq mshr miss latency |
| 1673system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 1674system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1694system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 1695system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1675system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency 1676system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency 1677system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency 1678system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency | 1696system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency 1697system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency 1698system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency 1699system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency |
| 1679system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1680system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1681system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1682system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1683system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1684system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1685system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1700system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1701system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1702system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1703system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1704system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1705system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1706system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1686system.cpu1.branchPred.lookups 7012649 # Number of BP lookups 1687system.cpu1.branchPred.condPredicted 5102138 # Number of conditional branches predicted 1688system.cpu1.branchPred.condIncorrect 681212 # Number of conditional branches incorrect 1689system.cpu1.branchPred.BTBLookups 4956162 # Number of BTB lookups 1690system.cpu1.branchPred.BTBHits 3806104 # Number of BTB hits | 1707system.cpu1.branchPred.lookups 4191050 # Number of BP lookups 1708system.cpu1.branchPred.condPredicted 2447557 # Number of conditional branches predicted 1709system.cpu1.branchPred.condIncorrect 261619 # Number of conditional branches incorrect 1710system.cpu1.branchPred.BTBLookups 2683528 # Number of BTB lookups 1711system.cpu1.branchPred.BTBHits 1692147 # Number of BTB hits |
| 1691system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1712system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1692system.cpu1.branchPred.BTBHitPct 76.795391 # BTB Hit Percentage 1693system.cpu1.branchPred.usedRAS 854817 # Number of times the RAS was used to get a target. 1694system.cpu1.branchPred.RASInCorrect 71801 # Number of incorrect RAS predictions. | 1713system.cpu1.branchPred.BTBHitPct 63.056804 # BTB Hit Percentage 1714system.cpu1.branchPred.usedRAS 827495 # Number of times the RAS was used to get a target. 1715system.cpu1.branchPred.RASInCorrect 59633 # Number of incorrect RAS predictions. |
| 1695system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1696system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1697system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1698system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1699system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1700system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1701system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1702system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1710system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1711system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1712system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1713system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1714system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1715system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1716system.cpu1.dtb.inst_hits 0 # ITB inst hits 1717system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1716system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1717system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1718system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1719system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1720system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1721system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1722system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1723system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1731system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1732system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1733system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1734system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1735system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1736system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1737system.cpu1.dtb.inst_hits 0 # ITB inst hits 1738system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1718system.cpu1.dtb.read_hits 7899300 # DTB read hits 1719system.cpu1.dtb.read_misses 20789 # DTB read misses 1720system.cpu1.dtb.write_hits 6047693 # DTB write hits 1721system.cpu1.dtb.write_misses 2209 # DTB write misses 1722system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1723system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1724system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1725system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1726system.cpu1.dtb.flush_entries 1917 # Number of entries that have been flushed from TLB 1727system.cpu1.dtb.align_faults 3619 # Number of TLB faults due to alignment restrictions 1728system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch | 1739system.cpu1.dtb.read_hits 4177995 # DTB read hits 1740system.cpu1.dtb.read_misses 21525 # DTB read misses 1741system.cpu1.dtb.write_hits 3468676 # DTB write hits 1742system.cpu1.dtb.write_misses 1889 # DTB write misses 1743system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1744system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1745system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1746system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1747system.cpu1.dtb.flush_entries 2064 # Number of entries that have been flushed from TLB 1748system.cpu1.dtb.align_faults 236 # Number of TLB faults due to alignment restrictions 1749system.cpu1.dtb.prefetch_faults 360 # Number of TLB faults due to prefetch |
| 1729system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1750system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1730system.cpu1.dtb.perms_faults 329 # Number of TLB faults due to permissions restrictions 1731system.cpu1.dtb.read_accesses 7920089 # DTB read accesses 1732system.cpu1.dtb.write_accesses 6049902 # DTB write accesses | 1751system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions 1752system.cpu1.dtb.read_accesses 4199520 # DTB read accesses 1753system.cpu1.dtb.write_accesses 3470565 # DTB write accesses |
| 1733system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1754system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1734system.cpu1.dtb.hits 13946993 # DTB hits 1735system.cpu1.dtb.misses 22998 # DTB misses 1736system.cpu1.dtb.accesses 13969991 # DTB accesses | 1755system.cpu1.dtb.hits 7646671 # DTB hits 1756system.cpu1.dtb.misses 23414 # DTB misses 1757system.cpu1.dtb.accesses 7670085 # DTB accesses |
| 1737system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1738system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1739system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1740system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1741system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1742system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1743system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1744system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1750system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1751system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1752system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1753system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1754system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1755system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1756system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1757system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1758system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1759system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1760system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1761system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1762system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1763system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1764system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1765system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1771system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1772system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1773system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1774system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1775system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1776system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1777system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1778system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1758system.cpu1.itb.inst_hits 14215184 # ITB inst hits 1759system.cpu1.itb.inst_misses 5010 # ITB inst misses | 1779system.cpu1.itb.inst_hits 7954981 # ITB inst hits 1780system.cpu1.itb.inst_misses 2237 # ITB inst misses |
| 1760system.cpu1.itb.read_hits 0 # DTB read hits 1761system.cpu1.itb.read_misses 0 # DTB read misses 1762system.cpu1.itb.write_hits 0 # DTB write hits 1763system.cpu1.itb.write_misses 0 # DTB write misses | 1781system.cpu1.itb.read_hits 0 # DTB read hits 1782system.cpu1.itb.read_misses 0 # DTB read misses 1783system.cpu1.itb.write_hits 0 # DTB write hits 1784system.cpu1.itb.write_misses 0 # DTB write misses |
| 1764system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1765system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1766system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1767system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1768system.cpu1.itb.flush_entries 1291 # Number of entries that have been flushed from TLB | 1785system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1786system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1787system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1788system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1789system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB |
| 1769system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1770system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1771system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1790system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1791system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1792system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1772system.cpu1.itb.perms_faults 3360 # Number of TLB faults due to permissions restrictions | 1793system.cpu1.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions |
| 1773system.cpu1.itb.read_accesses 0 # DTB read accesses 1774system.cpu1.itb.write_accesses 0 # DTB write accesses | 1794system.cpu1.itb.read_accesses 0 # DTB read accesses 1795system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1775system.cpu1.itb.inst_accesses 14220194 # ITB inst accesses 1776system.cpu1.itb.hits 14215184 # DTB hits 1777system.cpu1.itb.misses 5010 # DTB misses 1778system.cpu1.itb.accesses 14220194 # DTB accesses 1779system.cpu1.numCycles 502294457 # number of cpu cycles simulated | 1796system.cpu1.itb.inst_accesses 7957218 # ITB inst accesses 1797system.cpu1.itb.hits 7954981 # DTB hits 1798system.cpu1.itb.misses 2237 # DTB misses 1799system.cpu1.itb.accesses 7957218 # DTB accesses 1800system.cpu1.numCycles 42108230 # number of cpu cycles simulated |
| 1780system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1781system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1801system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1802system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1782system.cpu1.committedInsts 33559021 # Number of instructions committed 1783system.cpu1.committedOps 40204815 # Number of ops (including micro ops) committed 1784system.cpu1.discardedOps 2028180 # Number of ops (including micro ops) which were discarded before commit 1785system.cpu1.numFetchSuspends 40425 # Number of times Execute suspended instruction fetching 1786system.cpu1.quiesceCycles 4816571571 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1787system.cpu1.cpi 14.967494 # CPI: cycles per instruction 1788system.cpu1.ipc 0.066811 # IPC: instructions per cycle | 1803system.cpu1.committedInsts 16399164 # Number of instructions committed 1804system.cpu1.committedOps 20088934 # Number of ops (including micro ops) committed 1805system.cpu1.discardedOps 1607897 # Number of ops (including micro ops) which were discarded before commit 1806system.cpu1.numFetchSuspends 2744 # Number of times Execute suspended instruction fetching 1807system.cpu1.quiesceCycles 5644728223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1808system.cpu1.cpi 2.567706 # CPI: cycles per instruction 1809system.cpu1.ipc 0.389453 # IPC: instructions per cycle |
| 1789system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1810system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1790system.cpu1.kern.inst.quiesce 45433 # number of quiesce instructions executed 1791system.cpu1.tickCycles 438597056 # Number of cycles that the object actually ticked 1792system.cpu1.idleCycles 63697401 # Total number of cycles that the object has spent stopped 1793system.cpu1.icache.tags.replacements 777492 # number of replacements 1794system.cpu1.icache.tags.tagsinuse 499.131548 # Cycle average of tags in use 1795system.cpu1.icache.tags.total_refs 13433657 # Total number of references to valid blocks. 1796system.cpu1.icache.tags.sampled_refs 778004 # Sample count of references to valid blocks. 1797system.cpu1.icache.tags.avg_refs 17.266823 # Average number of references to valid blocks. 1798system.cpu1.icache.tags.warmup_cycle 71929000500 # Cycle when the warmup percentage was hit. 1799system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.131548 # Average occupied blocks per requestor 1800system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974866 # Average percentage of cache occupancy 1801system.cpu1.icache.tags.occ_percent::total 0.974866 # Average percentage of cache occupancy | 1811system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed 1812system.cpu1.tickCycles 30601119 # Number of cycles that the object actually ticked 1813system.cpu1.idleCycles 11507111 # Total number of cycles that the object has spent stopped 1814system.cpu1.icache.tags.replacements 921368 # number of replacements 1815system.cpu1.icache.tags.tagsinuse 499.459165 # Cycle average of tags in use 1816system.cpu1.icache.tags.total_refs 7030999 # Total number of references to valid blocks. 1817system.cpu1.icache.tags.sampled_refs 921880 # Sample count of references to valid blocks. 1818system.cpu1.icache.tags.avg_refs 7.626805 # Average number of references to valid blocks. 1819system.cpu1.icache.tags.warmup_cycle 71222254500 # Cycle when the warmup percentage was hit. 1820system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459165 # Average occupied blocks per requestor 1821system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy 1822system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy |
| 1802system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1823system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1803system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id | 1824system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id 1825system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id |
| 1804system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1826system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1805system.cpu1.icache.tags.tag_accesses 29201326 # Number of tag accesses 1806system.cpu1.icache.tags.data_accesses 29201326 # Number of data accesses 1807system.cpu1.icache.ReadReq_hits::cpu1.inst 13433657 # number of ReadReq hits 1808system.cpu1.icache.ReadReq_hits::total 13433657 # number of ReadReq hits 1809system.cpu1.icache.demand_hits::cpu1.inst 13433657 # number of demand (read+write) hits 1810system.cpu1.icache.demand_hits::total 13433657 # number of demand (read+write) hits 1811system.cpu1.icache.overall_hits::cpu1.inst 13433657 # number of overall hits 1812system.cpu1.icache.overall_hits::total 13433657 # number of overall hits 1813system.cpu1.icache.ReadReq_misses::cpu1.inst 778004 # number of ReadReq misses 1814system.cpu1.icache.ReadReq_misses::total 778004 # number of ReadReq misses 1815system.cpu1.icache.demand_misses::cpu1.inst 778004 # number of demand (read+write) misses 1816system.cpu1.icache.demand_misses::total 778004 # number of demand (read+write) misses 1817system.cpu1.icache.overall_misses::cpu1.inst 778004 # number of overall misses 1818system.cpu1.icache.overall_misses::total 778004 # number of overall misses 1819system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6472911750 # number of ReadReq miss cycles 1820system.cpu1.icache.ReadReq_miss_latency::total 6472911750 # number of ReadReq miss cycles 1821system.cpu1.icache.demand_miss_latency::cpu1.inst 6472911750 # number of demand (read+write) miss cycles 1822system.cpu1.icache.demand_miss_latency::total 6472911750 # number of demand (read+write) miss cycles 1823system.cpu1.icache.overall_miss_latency::cpu1.inst 6472911750 # number of overall miss cycles 1824system.cpu1.icache.overall_miss_latency::total 6472911750 # number of overall miss cycles 1825system.cpu1.icache.ReadReq_accesses::cpu1.inst 14211661 # number of ReadReq accesses(hits+misses) 1826system.cpu1.icache.ReadReq_accesses::total 14211661 # number of ReadReq accesses(hits+misses) 1827system.cpu1.icache.demand_accesses::cpu1.inst 14211661 # number of demand (read+write) accesses 1828system.cpu1.icache.demand_accesses::total 14211661 # number of demand (read+write) accesses 1829system.cpu1.icache.overall_accesses::cpu1.inst 14211661 # number of overall (read+write) accesses 1830system.cpu1.icache.overall_accesses::total 14211661 # number of overall (read+write) accesses 1831system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054744 # miss rate for ReadReq accesses 1832system.cpu1.icache.ReadReq_miss_rate::total 0.054744 # miss rate for ReadReq accesses 1833system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054744 # miss rate for demand accesses 1834system.cpu1.icache.demand_miss_rate::total 0.054744 # miss rate for demand accesses 1835system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054744 # miss rate for overall accesses 1836system.cpu1.icache.overall_miss_rate::total 0.054744 # miss rate for overall accesses 1837system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8319.895206 # average ReadReq miss latency 1838system.cpu1.icache.ReadReq_avg_miss_latency::total 8319.895206 # average ReadReq miss latency 1839system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency 1840system.cpu1.icache.demand_avg_miss_latency::total 8319.895206 # average overall miss latency 1841system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency 1842system.cpu1.icache.overall_avg_miss_latency::total 8319.895206 # average overall miss latency | 1827system.cpu1.icache.tags.tag_accesses 16827638 # Number of tag accesses 1828system.cpu1.icache.tags.data_accesses 16827638 # Number of data accesses 1829system.cpu1.icache.ReadReq_hits::cpu1.inst 7030999 # number of ReadReq hits 1830system.cpu1.icache.ReadReq_hits::total 7030999 # number of ReadReq hits 1831system.cpu1.icache.demand_hits::cpu1.inst 7030999 # number of demand (read+write) hits 1832system.cpu1.icache.demand_hits::total 7030999 # number of demand (read+write) hits 1833system.cpu1.icache.overall_hits::cpu1.inst 7030999 # number of overall hits 1834system.cpu1.icache.overall_hits::total 7030999 # number of overall hits 1835system.cpu1.icache.ReadReq_misses::cpu1.inst 921880 # number of ReadReq misses 1836system.cpu1.icache.ReadReq_misses::total 921880 # number of ReadReq misses 1837system.cpu1.icache.demand_misses::cpu1.inst 921880 # number of demand (read+write) misses 1838system.cpu1.icache.demand_misses::total 921880 # number of demand (read+write) misses 1839system.cpu1.icache.overall_misses::cpu1.inst 921880 # number of overall misses 1840system.cpu1.icache.overall_misses::total 921880 # number of overall misses 1841system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7511609427 # number of ReadReq miss cycles 1842system.cpu1.icache.ReadReq_miss_latency::total 7511609427 # number of ReadReq miss cycles 1843system.cpu1.icache.demand_miss_latency::cpu1.inst 7511609427 # number of demand (read+write) miss cycles 1844system.cpu1.icache.demand_miss_latency::total 7511609427 # number of demand (read+write) miss cycles 1845system.cpu1.icache.overall_miss_latency::cpu1.inst 7511609427 # number of overall miss cycles 1846system.cpu1.icache.overall_miss_latency::total 7511609427 # number of overall miss cycles 1847system.cpu1.icache.ReadReq_accesses::cpu1.inst 7952879 # number of ReadReq accesses(hits+misses) 1848system.cpu1.icache.ReadReq_accesses::total 7952879 # number of ReadReq accesses(hits+misses) 1849system.cpu1.icache.demand_accesses::cpu1.inst 7952879 # number of demand (read+write) accesses 1850system.cpu1.icache.demand_accesses::total 7952879 # number of demand (read+write) accesses 1851system.cpu1.icache.overall_accesses::cpu1.inst 7952879 # number of overall (read+write) accesses 1852system.cpu1.icache.overall_accesses::total 7952879 # number of overall (read+write) accesses 1853system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115918 # miss rate for ReadReq accesses 1854system.cpu1.icache.ReadReq_miss_rate::total 0.115918 # miss rate for ReadReq accesses 1855system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115918 # miss rate for demand accesses 1856system.cpu1.icache.demand_miss_rate::total 0.115918 # miss rate for demand accesses 1857system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115918 # miss rate for overall accesses 1858system.cpu1.icache.overall_miss_rate::total 0.115918 # miss rate for overall accesses 1859system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8148.142304 # average ReadReq miss latency 1860system.cpu1.icache.ReadReq_avg_miss_latency::total 8148.142304 # average ReadReq miss latency 1861system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency 1862system.cpu1.icache.demand_avg_miss_latency::total 8148.142304 # average overall miss latency 1863system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency 1864system.cpu1.icache.overall_avg_miss_latency::total 8148.142304 # average overall miss latency |
| 1843system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1844system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1845system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1846system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1847system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1848system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1849system.cpu1.icache.fast_writes 0 # number of fast writes performed 1850system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1865system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1866system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1867system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1868system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1869system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1870system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1871system.cpu1.icache.fast_writes 0 # number of fast writes performed 1872system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1851system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 778004 # number of ReadReq MSHR misses 1852system.cpu1.icache.ReadReq_mshr_misses::total 778004 # number of ReadReq MSHR misses 1853system.cpu1.icache.demand_mshr_misses::cpu1.inst 778004 # number of demand (read+write) MSHR misses 1854system.cpu1.icache.demand_mshr_misses::total 778004 # number of demand (read+write) MSHR misses 1855system.cpu1.icache.overall_mshr_misses::cpu1.inst 778004 # number of overall MSHR misses 1856system.cpu1.icache.overall_mshr_misses::total 778004 # number of overall MSHR misses 1857system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5304159248 # number of ReadReq MSHR miss cycles 1858system.cpu1.icache.ReadReq_mshr_miss_latency::total 5304159248 # number of ReadReq MSHR miss cycles 1859system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5304159248 # number of demand (read+write) MSHR miss cycles 1860system.cpu1.icache.demand_mshr_miss_latency::total 5304159248 # number of demand (read+write) MSHR miss cycles 1861system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5304159248 # number of overall MSHR miss cycles 1862system.cpu1.icache.overall_mshr_miss_latency::total 5304159248 # number of overall MSHR miss cycles 1863system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7302500 # number of ReadReq MSHR uncacheable cycles 1864system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7302500 # number of ReadReq MSHR uncacheable cycles 1865system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7302500 # number of overall MSHR uncacheable cycles 1866system.cpu1.icache.overall_mshr_uncacheable_latency::total 7302500 # number of overall MSHR uncacheable cycles 1867system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for ReadReq accesses 1868system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054744 # mshr miss rate for ReadReq accesses 1869system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for demand accesses 1870system.cpu1.icache.demand_mshr_miss_rate::total 0.054744 # mshr miss rate for demand accesses 1871system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for overall accesses 1872system.cpu1.icache.overall_mshr_miss_rate::total 0.054744 # mshr miss rate for overall accesses 1873system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average ReadReq mshr miss latency 1874system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6817.650357 # average ReadReq mshr miss latency 1875system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency 1876system.cpu1.icache.demand_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency 1877system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency 1878system.cpu1.icache.overall_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency | 1873system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 921880 # number of ReadReq MSHR misses 1874system.cpu1.icache.ReadReq_mshr_misses::total 921880 # number of ReadReq MSHR misses 1875system.cpu1.icache.demand_mshr_misses::cpu1.inst 921880 # number of demand (read+write) MSHR misses 1876system.cpu1.icache.demand_mshr_misses::total 921880 # number of demand (read+write) MSHR misses 1877system.cpu1.icache.overall_mshr_misses::cpu1.inst 921880 # number of overall MSHR misses 1878system.cpu1.icache.overall_mshr_misses::total 921880 # number of overall MSHR misses 1879system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6126335573 # number of ReadReq MSHR miss cycles 1880system.cpu1.icache.ReadReq_mshr_miss_latency::total 6126335573 # number of ReadReq MSHR miss cycles 1881system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6126335573 # number of demand (read+write) MSHR miss cycles 1882system.cpu1.icache.demand_mshr_miss_latency::total 6126335573 # number of demand (read+write) MSHR miss cycles 1883system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6126335573 # number of overall MSHR miss cycles 1884system.cpu1.icache.overall_mshr_miss_latency::total 6126335573 # number of overall MSHR miss cycles 1885system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10451250 # number of ReadReq MSHR uncacheable cycles 1886system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10451250 # number of ReadReq MSHR uncacheable cycles 1887system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10451250 # number of overall MSHR uncacheable cycles 1888system.cpu1.icache.overall_mshr_uncacheable_latency::total 10451250 # number of overall MSHR uncacheable cycles 1889system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for ReadReq accesses 1890system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.115918 # mshr miss rate for ReadReq accesses 1891system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for demand accesses 1892system.cpu1.icache.demand_mshr_miss_rate::total 0.115918 # mshr miss rate for demand accesses 1893system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for overall accesses 1894system.cpu1.icache.overall_mshr_miss_rate::total 0.115918 # mshr miss rate for overall accesses 1895system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average ReadReq mshr miss latency 1896system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6645.480510 # average ReadReq mshr miss latency 1897system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency 1898system.cpu1.icache.demand_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency 1899system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency 1900system.cpu1.icache.overall_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency |
| 1879system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1880system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1881system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1882system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1883system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1901system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1902system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1903system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1904system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1905system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1884system.cpu1.toL2Bus.trans_dist::ReadReq 2373135 # Transaction distribution 1885system.cpu1.toL2Bus.trans_dist::ReadResp 2161912 # Transaction distribution 1886system.cpu1.toL2Bus.trans_dist::WriteReq 757956 # Transaction distribution 1887system.cpu1.toL2Bus.trans_dist::WriteResp 757956 # Transaction distribution 1888system.cpu1.toL2Bus.trans_dist::Writeback 242084 # Transaction distribution 1889system.cpu1.toL2Bus.trans_dist::HardPFReq 267987 # Transaction distribution 1890system.cpu1.toL2Bus.trans_dist::UpgradeReq 52917 # Transaction distribution 1891system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23794 # Transaction distribution 1892system.cpu1.toL2Bus.trans_dist::UpgradeResp 50912 # Transaction distribution 1893system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution 1894system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution 1895system.cpu1.toL2Bus.trans_dist::ReadExReq 145700 # Transaction distribution 1896system.cpu1.toL2Bus.trans_dist::ReadExResp 137856 # Transaction distribution 1897system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1555984 # Packet count per connected master and slave (bytes) 1898system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4768118 # Packet count per connected master and slave (bytes) 1899system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17545 # Packet count per connected master and slave (bytes) 1900system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66434 # Packet count per connected master and slave (bytes) 1901system.cpu1.toL2Bus.pkt_count::total 6408081 # Packet count per connected master and slave (bytes) 1902system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49785408 # Cumulative packet size per connected master and slave (bytes) 1903system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44521800 # Cumulative packet size per connected master and slave (bytes) 1904system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30416 # Cumulative packet size per connected master and slave (bytes) 1905system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119152 # Cumulative packet size per connected master and slave (bytes) 1906system.cpu1.toL2Bus.pkt_size::total 94456776 # Cumulative packet size per connected master and slave (bytes) 1907system.cpu1.toL2Bus.snoops 606235 # Total snoops (count) 1908system.cpu1.toL2Bus.snoop_fanout::samples 2002284 # Request fanout histogram 1909system.cpu1.toL2Bus.snoop_fanout::mean 5.277104 # Request fanout histogram 1910system.cpu1.toL2Bus.snoop_fanout::stdev 0.447568 # Request fanout histogram | 1906system.cpu1.toL2Bus.trans_dist::ReadReq 1617912 # Transaction distribution 1907system.cpu1.toL2Bus.trans_dist::ReadResp 1172300 # Transaction distribution 1908system.cpu1.toL2Bus.trans_dist::WriteReq 2534 # Transaction distribution 1909system.cpu1.toL2Bus.trans_dist::WriteResp 2534 # Transaction distribution 1910system.cpu1.toL2Bus.trans_dist::Writeback 119069 # Transaction distribution 1911system.cpu1.toL2Bus.trans_dist::HardPFReq 160310 # Transaction distribution 1912system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 1913system.cpu1.toL2Bus.trans_dist::UpgradeReq 84990 # Transaction distribution 1914system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41555 # Transaction distribution 1915system.cpu1.toL2Bus.trans_dist::UpgradeResp 86189 # Transaction distribution 1916system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 1917system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution 1918system.cpu1.toL2Bus.trans_dist::ReadExReq 79780 # Transaction distribution 1919system.cpu1.toL2Bus.trans_dist::ReadExResp 67226 # Transaction distribution 1920system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1843990 # Packet count per connected master and slave (bytes) 1921system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 788213 # Packet count per connected master and slave (bytes) 1922system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6991 # Packet count per connected master and slave (bytes) 1923system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 54848 # Packet count per connected master and slave (bytes) 1924system.cpu1.toL2Bus.pkt_count::total 2694042 # Packet count per connected master and slave (bytes) 1925system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59007680 # Cumulative packet size per connected master and slave (bytes) 1926system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25579748 # Cumulative packet size per connected master and slave (bytes) 1927system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10764 # Cumulative packet size per connected master and slave (bytes) 1928system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 100400 # Cumulative packet size per connected master and slave (bytes) 1929system.cpu1.toL2Bus.pkt_size::total 84698592 # Cumulative packet size per connected master and slave (bytes) 1930system.cpu1.toL2Bus.snoops 851885 # Total snoops (count) 1931system.cpu1.toL2Bus.snoop_fanout::samples 2136582 # Request fanout histogram 1932system.cpu1.toL2Bus.snoop_fanout::mean 5.360548 # Request fanout histogram 1933system.cpu1.toL2Bus.snoop_fanout::stdev 0.480160 # Request fanout histogram |
| 1911system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1912system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1913system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1914system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1915system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1916system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1934system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1935system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1936system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1937system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1938system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1939system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1917system.cpu1.toL2Bus.snoop_fanout::5 1447444 72.29% 72.29% # Request fanout histogram 1918system.cpu1.toL2Bus.snoop_fanout::6 554840 27.71% 100.00% # Request fanout histogram | 1940system.cpu1.toL2Bus.snoop_fanout::5 1366242 63.95% 63.95% # Request fanout histogram 1941system.cpu1.toL2Bus.snoop_fanout::6 770340 36.05% 100.00% # Request fanout histogram |
| 1919system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1920system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1921system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1942system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1943system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1944system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1922system.cpu1.toL2Bus.snoop_fanout::total 2002284 # Request fanout histogram 1923system.cpu1.toL2Bus.reqLayer0.occupancy 2275579743 # Layer occupancy (ticks) 1924system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1925system.cpu1.toL2Bus.snoopLayer0.occupancy 46369000 # Layer occupancy (ticks) | 1945system.cpu1.toL2Bus.snoop_fanout::total 2136582 # Request fanout histogram 1946system.cpu1.toL2Bus.reqLayer0.occupancy 806533923 # Layer occupancy (ticks) 1947system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1948system.cpu1.toL2Bus.snoopLayer0.occupancy 80269000 # Layer occupancy (ticks) |
| 1926system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1949system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1927system.cpu1.toL2Bus.respLayer0.occupancy 1168020751 # Layer occupancy (ticks) | 1950system.cpu1.toL2Bus.respLayer0.occupancy 1384243177 # Layer occupancy (ticks) |
| 1928system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1951system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1929system.cpu1.toL2Bus.respLayer1.occupancy 2025918980 # Layer occupancy (ticks) 1930system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1931system.cpu1.toL2Bus.respLayer2.occupancy 9945491 # Layer occupancy (ticks) | 1952system.cpu1.toL2Bus.respLayer1.occupancy 391135835 # Layer occupancy (ticks) 1953system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1954system.cpu1.toL2Bus.respLayer2.occupancy 4300499 # Layer occupancy (ticks) |
| 1932system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1955system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1933system.cpu1.toL2Bus.respLayer3.occupancy 36649244 # Layer occupancy (ticks) | 1956system.cpu1.toL2Bus.respLayer3.occupancy 29750249 # Layer occupancy (ticks) |
| 1934system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1957system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1935system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6850018 # number of hwpf identified 1936system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163294 # number of hwpf that were already in mshr 1937system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6486593 # number of hwpf that were already in the cache 1938system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2687 # number of hwpf that were already in the prefetch queue | 1958system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7297386 # number of hwpf identified 1959system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43768 # number of hwpf that were already in mshr 1960system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7137149 # number of hwpf that were already in the cache 1961system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1402 # number of hwpf that were already in the prefetch queue |
| 1939system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1962system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1940system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2014 # number of hwpf removed because MSHR allocated 1941system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 195430 # number of hwpf issued 1942system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564382 # number of hwpf spanning a virtual page | 1963system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2677 # number of hwpf removed because MSHR allocated 1964system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 112390 # number of hwpf issued 1965system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 731398 # number of hwpf spanning a virtual page |
| 1943system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1966system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1944system.cpu1.l2cache.tags.replacements 179644 # number of replacements 1945system.cpu1.l2cache.tags.tagsinuse 15634.197458 # Cycle average of tags in use 1946system.cpu1.l2cache.tags.total_refs 1195685 # Total number of references to valid blocks. 1947system.cpu1.l2cache.tags.sampled_refs 195044 # Sample count of references to valid blocks. 1948system.cpu1.l2cache.tags.avg_refs 6.130335 # Average number of references to valid blocks. 1949system.cpu1.l2cache.tags.warmup_cycle 2581359096500 # Cycle when the warmup percentage was hit. 1950system.cpu1.l2cache.tags.occ_blocks::writebacks 4491.320198 # Average occupied blocks per requestor 1951system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.341759 # Average occupied blocks per requestor 1952system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.933743 # Average occupied blocks per requestor 1953system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.115946 # Average occupied blocks per requestor 1954system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8353.485812 # Average occupied blocks per requestor 1955system.cpu1.l2cache.tags.occ_percent::writebacks 0.274128 # Average percentage of cache occupancy 1956system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001425 # Average percentage of cache occupancy 1957system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy 1958system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168708 # Average percentage of cache occupancy 1959system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.509856 # Average percentage of cache occupancy 1960system.cpu1.l2cache.tags.occ_percent::total 0.954236 # Average percentage of cache occupancy 1961system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9491 # Occupied blocks per task id 1962system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id 1963system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5898 # Occupied blocks per task id 1964system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2061 # Occupied blocks per task id 1965system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1580 # Occupied blocks per task id 1966system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5850 # Occupied blocks per task id 1967system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1968system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 1969system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2269 # Occupied blocks per task id 1970system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id 1971system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2711 # Occupied blocks per task id 1972system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.579285 # Percentage of cache occupancy per task id 1973system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 1974system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359985 # Percentage of cache occupancy per task id 1975system.cpu1.l2cache.tags.tag_accesses 23405517 # Number of tag accesses 1976system.cpu1.l2cache.tags.data_accesses 23405517 # Number of data accesses 1977system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29293 # number of ReadReq hits 1978system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7458 # number of ReadReq hits 1979system.cpu1.l2cache.ReadReq_hits::cpu1.inst 926354 # number of ReadReq hits 1980system.cpu1.l2cache.ReadReq_hits::total 963105 # number of ReadReq hits 1981system.cpu1.l2cache.Writeback_hits::writebacks 242084 # number of Writeback hits 1982system.cpu1.l2cache.Writeback_hits::total 242084 # number of Writeback hits 1983system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1948 # number of UpgradeReq hits 1984system.cpu1.l2cache.UpgradeReq_hits::total 1948 # number of UpgradeReq hits 1985system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1158 # number of SCUpgradeReq hits 1986system.cpu1.l2cache.SCUpgradeReq_hits::total 1158 # number of SCUpgradeReq hits 1987system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112338 # number of ReadExReq hits 1988system.cpu1.l2cache.ReadExReq_hits::total 112338 # number of ReadExReq hits 1989system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29293 # number of demand (read+write) hits 1990system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7458 # number of demand (read+write) hits 1991system.cpu1.l2cache.demand_hits::cpu1.inst 1038692 # number of demand (read+write) hits 1992system.cpu1.l2cache.demand_hits::total 1075443 # number of demand (read+write) hits 1993system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29293 # number of overall hits 1994system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7458 # number of overall hits 1995system.cpu1.l2cache.overall_hits::cpu1.inst 1038692 # number of overall hits 1996system.cpu1.l2cache.overall_hits::total 1075443 # number of overall hits 1997system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 495 # number of ReadReq misses 1998system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 146 # number of ReadReq misses 1999system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61595 # number of ReadReq misses 2000system.cpu1.l2cache.ReadReq_misses::total 62236 # number of ReadReq misses 2001system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18656 # number of UpgradeReq misses 2002system.cpu1.l2cache.UpgradeReq_misses::total 18656 # number of UpgradeReq misses 2003system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12530 # number of SCUpgradeReq misses 2004system.cpu1.l2cache.SCUpgradeReq_misses::total 12530 # number of SCUpgradeReq misses 2005system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 3 # number of SCUpgradeFailReq misses 2006system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 2007system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 23997 # number of ReadExReq misses 2008system.cpu1.l2cache.ReadExReq_misses::total 23997 # number of ReadExReq misses 2009system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 495 # number of demand (read+write) misses 2010system.cpu1.l2cache.demand_misses::cpu1.itb.walker 146 # number of demand (read+write) misses 2011system.cpu1.l2cache.demand_misses::cpu1.inst 85592 # number of demand (read+write) misses 2012system.cpu1.l2cache.demand_misses::total 86233 # number of demand (read+write) misses 2013system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 495 # number of overall misses 2014system.cpu1.l2cache.overall_misses::cpu1.itb.walker 146 # number of overall misses 2015system.cpu1.l2cache.overall_misses::cpu1.inst 85592 # number of overall misses 2016system.cpu1.l2cache.overall_misses::total 86233 # number of overall misses 2017system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11596750 # number of ReadReq miss cycles 2018system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3042000 # number of ReadReq miss cycles 2019system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1525132928 # number of ReadReq miss cycles 2020system.cpu1.l2cache.ReadReq_miss_latency::total 1539771678 # number of ReadReq miss cycles 2021system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 312251712 # number of UpgradeReq miss cycles 2022system.cpu1.l2cache.UpgradeReq_miss_latency::total 312251712 # number of UpgradeReq miss cycles 2023system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 251269185 # number of SCUpgradeReq miss cycles 2024system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 251269185 # number of SCUpgradeReq miss cycles 2025system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 836500 # number of SCUpgradeFailReq miss cycles 2026system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 836500 # number of SCUpgradeFailReq miss cycles 2027system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1004785618 # number of ReadExReq miss cycles 2028system.cpu1.l2cache.ReadExReq_miss_latency::total 1004785618 # number of ReadExReq miss cycles 2029system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11596750 # number of demand (read+write) miss cycles 2030system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3042000 # number of demand (read+write) miss cycles 2031system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2529918546 # number of demand (read+write) miss cycles 2032system.cpu1.l2cache.demand_miss_latency::total 2544557296 # number of demand (read+write) miss cycles 2033system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11596750 # number of overall miss cycles 2034system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3042000 # number of overall miss cycles 2035system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2529918546 # number of overall miss cycles 2036system.cpu1.l2cache.overall_miss_latency::total 2544557296 # number of overall miss cycles 2037system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29788 # number of ReadReq accesses(hits+misses) 2038system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7604 # number of ReadReq accesses(hits+misses) 2039system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 987949 # number of ReadReq accesses(hits+misses) 2040system.cpu1.l2cache.ReadReq_accesses::total 1025341 # number of ReadReq accesses(hits+misses) 2041system.cpu1.l2cache.Writeback_accesses::writebacks 242084 # number of Writeback accesses(hits+misses) 2042system.cpu1.l2cache.Writeback_accesses::total 242084 # number of Writeback accesses(hits+misses) 2043system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20604 # number of UpgradeReq accesses(hits+misses) 2044system.cpu1.l2cache.UpgradeReq_accesses::total 20604 # number of UpgradeReq accesses(hits+misses) 2045system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13688 # number of SCUpgradeReq accesses(hits+misses) 2046system.cpu1.l2cache.SCUpgradeReq_accesses::total 13688 # number of SCUpgradeReq accesses(hits+misses) 2047system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 3 # number of SCUpgradeFailReq accesses(hits+misses) 2048system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 2049system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136335 # number of ReadExReq accesses(hits+misses) 2050system.cpu1.l2cache.ReadExReq_accesses::total 136335 # number of ReadExReq accesses(hits+misses) 2051system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29788 # number of demand (read+write) accesses 2052system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7604 # number of demand (read+write) accesses 2053system.cpu1.l2cache.demand_accesses::cpu1.inst 1124284 # number of demand (read+write) accesses 2054system.cpu1.l2cache.demand_accesses::total 1161676 # number of demand (read+write) accesses 2055system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29788 # number of overall (read+write) accesses 2056system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7604 # number of overall (read+write) accesses 2057system.cpu1.l2cache.overall_accesses::cpu1.inst 1124284 # number of overall (read+write) accesses 2058system.cpu1.l2cache.overall_accesses::total 1161676 # number of overall (read+write) accesses 2059system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for ReadReq accesses 2060system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019200 # miss rate for ReadReq accesses 2061system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.062346 # miss rate for ReadReq accesses 2062system.cpu1.l2cache.ReadReq_miss_rate::total 0.060698 # miss rate for ReadReq accesses 2063system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.905455 # miss rate for UpgradeReq accesses 2064system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.905455 # miss rate for UpgradeReq accesses 2065system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.915400 # miss rate for SCUpgradeReq accesses 2066system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.915400 # miss rate for SCUpgradeReq accesses 2067system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses 2068system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2069system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.176015 # miss rate for ReadExReq accesses 2070system.cpu1.l2cache.ReadExReq_miss_rate::total 0.176015 # miss rate for ReadExReq accesses 2071system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for demand accesses 2072system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019200 # miss rate for demand accesses 2073system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076130 # miss rate for demand accesses 2074system.cpu1.l2cache.demand_miss_rate::total 0.074232 # miss rate for demand accesses 2075system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.016617 # miss rate for overall accesses 2076system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019200 # miss rate for overall accesses 2077system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076130 # miss rate for overall accesses 2078system.cpu1.l2cache.overall_miss_rate::total 0.074232 # miss rate for overall accesses 2079system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average ReadReq miss latency 2080system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20835.616438 # average ReadReq miss latency 2081system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 24760.661223 # average ReadReq miss latency 2082system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24740.852208 # average ReadReq miss latency 2083system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 16737.334477 # average UpgradeReq miss latency 2084system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16737.334477 # average UpgradeReq miss latency 2085system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20053.406624 # average SCUpgradeReq miss latency 2086system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20053.406624 # average SCUpgradeReq miss latency 2087system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 278833.333333 # average SCUpgradeFailReq miss latency 2088system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 278833.333333 # average SCUpgradeFailReq miss latency 2089system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41871.301329 # average ReadExReq miss latency 2090system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41871.301329 # average ReadExReq miss latency 2091system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average overall miss latency 2092system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20835.616438 # average overall miss latency 2093system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29557.885620 # average overall miss latency 2094system.cpu1.l2cache.demand_avg_miss_latency::total 29507.929633 # average overall miss latency 2095system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23427.777778 # average overall miss latency 2096system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20835.616438 # average overall miss latency 2097system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29557.885620 # average overall miss latency 2098system.cpu1.l2cache.overall_avg_miss_latency::total 29507.929633 # average overall miss latency 2099system.cpu1.l2cache.blocked_cycles::no_mshrs 1374 # number of cycles access was blocked | 1967system.cpu1.l2cache.tags.replacements 85101 # number of replacements 1968system.cpu1.l2cache.tags.tagsinuse 15525.587179 # Cycle average of tags in use 1969system.cpu1.l2cache.tags.total_refs 1172424 # Total number of references to valid blocks. 1970system.cpu1.l2cache.tags.sampled_refs 100275 # Sample count of references to valid blocks. 1971system.cpu1.l2cache.tags.avg_refs 11.692087 # Average number of references to valid blocks. 1972system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1973system.cpu1.l2cache.tags.occ_blocks::writebacks 5967.757550 # Average occupied blocks per requestor 1974system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.503310 # Average occupied blocks per requestor 1975system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.105046 # Average occupied blocks per requestor 1976system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2342.307731 # Average occupied blocks per requestor 1977system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7188.913541 # Average occupied blocks per requestor 1978system.cpu1.l2cache.tags.occ_percent::writebacks 0.364243 # Average percentage of cache occupancy 1979system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001618 # Average percentage of cache occupancy 1980system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy 1981system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142963 # Average percentage of cache occupancy 1982system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.438776 # Average percentage of cache occupancy 1983system.cpu1.l2cache.tags.occ_percent::total 0.947607 # Average percentage of cache occupancy 1984system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10134 # Occupied blocks per task id 1985system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id 1986system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5006 # Occupied blocks per task id 1987system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 136 # Occupied blocks per task id 1988system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6712 # Occupied blocks per task id 1989system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3286 # Occupied blocks per task id 1990system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 1991system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 1992system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 1993system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id 1994system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2980 # Occupied blocks per task id 1995system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1783 # Occupied blocks per task id 1996system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.618530 # Percentage of cache occupancy per task id 1997system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id 1998system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.305542 # Percentage of cache occupancy per task id 1999system.cpu1.l2cache.tags.tag_accesses 22015192 # Number of tag accesses 2000system.cpu1.l2cache.tags.data_accesses 22015192 # Number of data accesses 2001system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24492 # number of ReadReq hits 2002system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2447 # number of ReadReq hits 2003system.cpu1.l2cache.ReadReq_hits::cpu1.inst 1023306 # number of ReadReq hits 2004system.cpu1.l2cache.ReadReq_hits::total 1050245 # number of ReadReq hits 2005system.cpu1.l2cache.Writeback_hits::writebacks 119069 # number of Writeback hits 2006system.cpu1.l2cache.Writeback_hits::total 119069 # number of Writeback hits 2007system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1895 # number of UpgradeReq hits 2008system.cpu1.l2cache.UpgradeReq_hits::total 1895 # number of UpgradeReq hits 2009system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 736 # number of SCUpgradeReq hits 2010system.cpu1.l2cache.SCUpgradeReq_hits::total 736 # number of SCUpgradeReq hits 2011system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 30109 # number of ReadExReq hits 2012system.cpu1.l2cache.ReadExReq_hits::total 30109 # number of ReadExReq hits 2013system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24492 # number of demand (read+write) hits 2014system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2447 # number of demand (read+write) hits 2015system.cpu1.l2cache.demand_hits::cpu1.inst 1053415 # number of demand (read+write) hits 2016system.cpu1.l2cache.demand_hits::total 1080354 # number of demand (read+write) hits 2017system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24492 # number of overall hits 2018system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2447 # number of overall hits 2019system.cpu1.l2cache.overall_hits::cpu1.inst 1053415 # number of overall hits 2020system.cpu1.l2cache.overall_hits::total 1080354 # number of overall hits 2021system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 608 # number of ReadReq misses 2022system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 244 # number of ReadReq misses 2023system.cpu1.l2cache.ReadReq_misses::cpu1.inst 73509 # number of ReadReq misses 2024system.cpu1.l2cache.ReadReq_misses::total 74361 # number of ReadReq misses 2025system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28314 # number of UpgradeReq misses 2026system.cpu1.l2cache.UpgradeReq_misses::total 28314 # number of UpgradeReq misses 2027system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22589 # number of SCUpgradeReq misses 2028system.cpu1.l2cache.SCUpgradeReq_misses::total 22589 # number of SCUpgradeReq misses 2029system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32639 # number of ReadExReq misses 2030system.cpu1.l2cache.ReadExReq_misses::total 32639 # number of ReadExReq misses 2031system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 608 # number of demand (read+write) misses 2032system.cpu1.l2cache.demand_misses::cpu1.itb.walker 244 # number of demand (read+write) misses 2033system.cpu1.l2cache.demand_misses::cpu1.inst 106148 # number of demand (read+write) misses 2034system.cpu1.l2cache.demand_misses::total 107000 # number of demand (read+write) misses 2035system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 608 # number of overall misses 2036system.cpu1.l2cache.overall_misses::cpu1.itb.walker 244 # number of overall misses 2037system.cpu1.l2cache.overall_misses::cpu1.inst 106148 # number of overall misses 2038system.cpu1.l2cache.overall_misses::total 107000 # number of overall misses 2039system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13309748 # number of ReadReq miss cycles 2040system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4879000 # number of ReadReq miss cycles 2041system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1671503870 # number of ReadReq miss cycles 2042system.cpu1.l2cache.ReadReq_miss_latency::total 1689692618 # number of ReadReq miss cycles 2043system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 534018919 # number of UpgradeReq miss cycles 2044system.cpu1.l2cache.UpgradeReq_miss_latency::total 534018919 # number of UpgradeReq miss cycles 2045system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 443647551 # number of SCUpgradeReq miss cycles 2046system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443647551 # number of SCUpgradeReq miss cycles 2047system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 303500 # number of SCUpgradeFailReq miss cycles 2048system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 303500 # number of SCUpgradeFailReq miss cycles 2049system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1129954380 # number of ReadExReq miss cycles 2050system.cpu1.l2cache.ReadExReq_miss_latency::total 1129954380 # number of ReadExReq miss cycles 2051system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13309748 # number of demand (read+write) miss cycles 2052system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4879000 # number of demand (read+write) miss cycles 2053system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2801458250 # number of demand (read+write) miss cycles 2054system.cpu1.l2cache.demand_miss_latency::total 2819646998 # number of demand (read+write) miss cycles 2055system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13309748 # number of overall miss cycles 2056system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4879000 # number of overall miss cycles 2057system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2801458250 # number of overall miss cycles 2058system.cpu1.l2cache.overall_miss_latency::total 2819646998 # number of overall miss cycles 2059system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 25100 # number of ReadReq accesses(hits+misses) 2060system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2691 # number of ReadReq accesses(hits+misses) 2061system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1096815 # number of ReadReq accesses(hits+misses) 2062system.cpu1.l2cache.ReadReq_accesses::total 1124606 # number of ReadReq accesses(hits+misses) 2063system.cpu1.l2cache.Writeback_accesses::writebacks 119069 # number of Writeback accesses(hits+misses) 2064system.cpu1.l2cache.Writeback_accesses::total 119069 # number of Writeback accesses(hits+misses) 2065system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 30209 # number of UpgradeReq accesses(hits+misses) 2066system.cpu1.l2cache.UpgradeReq_accesses::total 30209 # number of UpgradeReq accesses(hits+misses) 2067system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23325 # number of SCUpgradeReq accesses(hits+misses) 2068system.cpu1.l2cache.SCUpgradeReq_accesses::total 23325 # number of SCUpgradeReq accesses(hits+misses) 2069system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 62748 # number of ReadExReq accesses(hits+misses) 2070system.cpu1.l2cache.ReadExReq_accesses::total 62748 # number of ReadExReq accesses(hits+misses) 2071system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 25100 # number of demand (read+write) accesses 2072system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2691 # number of demand (read+write) accesses 2073system.cpu1.l2cache.demand_accesses::cpu1.inst 1159563 # number of demand (read+write) accesses 2074system.cpu1.l2cache.demand_accesses::total 1187354 # number of demand (read+write) accesses 2075system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 25100 # number of overall (read+write) accesses 2076system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2691 # number of overall (read+write) accesses 2077system.cpu1.l2cache.overall_accesses::cpu1.inst 1159563 # number of overall (read+write) accesses 2078system.cpu1.l2cache.overall_accesses::total 1187354 # number of overall (read+write) accesses 2079system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for ReadReq accesses 2080system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090673 # miss rate for ReadReq accesses 2081system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067020 # miss rate for ReadReq accesses 2082system.cpu1.l2cache.ReadReq_miss_rate::total 0.066122 # miss rate for ReadReq accesses 2083system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.937270 # miss rate for UpgradeReq accesses 2084system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937270 # miss rate for UpgradeReq accesses 2085system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968446 # miss rate for SCUpgradeReq accesses 2086system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968446 # miss rate for SCUpgradeReq accesses 2087system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.520160 # miss rate for ReadExReq accesses 2088system.cpu1.l2cache.ReadExReq_miss_rate::total 0.520160 # miss rate for ReadExReq accesses 2089system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for demand accesses 2090system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090673 # miss rate for demand accesses 2091system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091541 # miss rate for demand accesses 2092system.cpu1.l2cache.demand_miss_rate::total 0.090116 # miss rate for demand accesses 2093system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for overall accesses 2094system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090673 # miss rate for overall accesses 2095system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091541 # miss rate for overall accesses 2096system.cpu1.l2cache.overall_miss_rate::total 0.090116 # miss rate for overall accesses 2097system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average ReadReq miss latency 2098system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19995.901639 # average ReadReq miss latency 2099system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22738.764913 # average ReadReq miss latency 2100system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22722.833448 # average ReadReq miss latency 2101system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18860.596136 # average UpgradeReq miss latency 2102system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18860.596136 # average UpgradeReq miss latency 2103system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19639.981894 # average SCUpgradeReq miss latency 2104system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19639.981894 # average SCUpgradeReq miss latency 2105system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency 2106system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 2107system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34619.761022 # average ReadExReq miss latency 2108system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34619.761022 # average ReadExReq miss latency 2109system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average overall miss latency 2110system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19995.901639 # average overall miss latency 2111system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26392.002204 # average overall miss latency 2112system.cpu1.l2cache.demand_avg_miss_latency::total 26351.841103 # average overall miss latency 2113system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21891.032895 # average overall miss latency 2114system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19995.901639 # average overall miss latency 2115system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26392.002204 # average overall miss latency 2116system.cpu1.l2cache.overall_avg_miss_latency::total 26351.841103 # average overall miss latency 2117system.cpu1.l2cache.blocked_cycles::no_mshrs 5254 # number of cycles access was blocked |
| 2100system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2118system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2101system.cpu1.l2cache.blocked::no_mshrs 55 # number of cycles access was blocked | 2119system.cpu1.l2cache.blocked::no_mshrs 187 # number of cycles access was blocked |
| 2102system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2120system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2103system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24.981818 # average number of cycles each access was blocked | 2121system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.096257 # average number of cycles each access was blocked |
| 2104system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2105system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2106system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2122system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2123system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2124system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2107system.cpu1.l2cache.writebacks::writebacks 100561 # number of writebacks 2108system.cpu1.l2cache.writebacks::total 100561 # number of writebacks 2109system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3711 # number of ReadReq MSHR hits 2110system.cpu1.l2cache.ReadReq_mshr_hits::total 3711 # number of ReadReq MSHR hits 2111system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 1353 # number of ReadExReq MSHR hits 2112system.cpu1.l2cache.ReadExReq_mshr_hits::total 1353 # number of ReadExReq MSHR hits 2113system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5064 # number of demand (read+write) MSHR hits 2114system.cpu1.l2cache.demand_mshr_hits::total 5064 # number of demand (read+write) MSHR hits 2115system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5064 # number of overall MSHR hits 2116system.cpu1.l2cache.overall_mshr_hits::total 5064 # number of overall MSHR hits 2117system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 495 # number of ReadReq MSHR misses 2118system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 146 # number of ReadReq MSHR misses 2119system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 57884 # number of ReadReq MSHR misses 2120system.cpu1.l2cache.ReadReq_mshr_misses::total 58525 # number of ReadReq MSHR misses 2121system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 195430 # number of HardPFReq MSHR misses 2122system.cpu1.l2cache.HardPFReq_mshr_misses::total 195430 # number of HardPFReq MSHR misses 2123system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 18656 # number of UpgradeReq MSHR misses 2124system.cpu1.l2cache.UpgradeReq_mshr_misses::total 18656 # number of UpgradeReq MSHR misses 2125system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 12530 # number of SCUpgradeReq MSHR misses 2126system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12530 # number of SCUpgradeReq MSHR misses 2127system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 3 # number of SCUpgradeFailReq MSHR misses 2128system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2129system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 22644 # number of ReadExReq MSHR misses 2130system.cpu1.l2cache.ReadExReq_mshr_misses::total 22644 # number of ReadExReq MSHR misses 2131system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 495 # number of demand (read+write) MSHR misses 2132system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 146 # number of demand (read+write) MSHR misses 2133system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 80528 # number of demand (read+write) MSHR misses 2134system.cpu1.l2cache.demand_mshr_misses::total 81169 # number of demand (read+write) MSHR misses 2135system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 495 # number of overall MSHR misses 2136system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 146 # number of overall MSHR misses 2137system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 80528 # number of overall MSHR misses 2138system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 195430 # number of overall MSHR misses 2139system.cpu1.l2cache.overall_mshr_misses::total 276599 # number of overall MSHR misses 2140system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of ReadReq MSHR miss cycles 2141system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2020000 # number of ReadReq MSHR miss cycles 2142system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1052949978 # number of ReadReq MSHR miss cycles 2143system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1063101228 # number of ReadReq MSHR miss cycles 2144system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10102217802 # number of HardPFReq MSHR miss cycles 2145system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10102217802 # number of HardPFReq MSHR miss cycles 2146system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 306954055 # number of UpgradeReq MSHR miss cycles 2147system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 306954055 # number of UpgradeReq MSHR miss cycles 2148system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 178539396 # number of SCUpgradeReq MSHR miss cycles 2149system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 178539396 # number of SCUpgradeReq MSHR miss cycles 2150system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 654500 # number of SCUpgradeFailReq MSHR miss cycles 2151system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 654500 # number of SCUpgradeFailReq MSHR miss cycles 2152system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 627825362 # number of ReadExReq MSHR miss cycles 2153system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 627825362 # number of ReadExReq MSHR miss cycles 2154system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of demand (read+write) MSHR miss cycles 2155system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2020000 # number of demand (read+write) MSHR miss cycles 2156system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1680775340 # number of demand (read+write) MSHR miss cycles 2157system.cpu1.l2cache.demand_mshr_miss_latency::total 1690926590 # number of demand (read+write) MSHR miss cycles 2158system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8131250 # number of overall MSHR miss cycles 2159system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2020000 # number of overall MSHR miss cycles 2160system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1680775340 # number of overall MSHR miss cycles 2161system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10102217802 # number of overall MSHR miss cycles 2162system.cpu1.l2cache.overall_mshr_miss_latency::total 11793144392 # number of overall MSHR miss cycles 2163system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 174927425750 # number of ReadReq MSHR uncacheable cycles 2164system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174927425750 # number of ReadReq MSHR uncacheable cycles 2165system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 28797119642 # number of WriteReq MSHR uncacheable cycles 2166system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28797119642 # number of WriteReq MSHR uncacheable cycles 2167system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 203724545392 # number of overall MSHR uncacheable cycles 2168system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 203724545392 # number of overall MSHR uncacheable cycles 2169system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for ReadReq accesses 2170system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for ReadReq accesses 2171system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.058590 # mshr miss rate for ReadReq accesses 2172system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.057079 # mshr miss rate for ReadReq accesses | 2125system.cpu1.l2cache.writebacks::writebacks 39442 # number of writebacks 2126system.cpu1.l2cache.writebacks::total 39442 # number of writebacks 2127system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1735 # number of ReadReq MSHR hits 2128system.cpu1.l2cache.ReadReq_mshr_hits::total 1735 # number of ReadReq MSHR hits 2129system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 340 # number of ReadExReq MSHR hits 2130system.cpu1.l2cache.ReadExReq_mshr_hits::total 340 # number of ReadExReq MSHR hits 2131system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2075 # number of demand (read+write) MSHR hits 2132system.cpu1.l2cache.demand_mshr_hits::total 2075 # number of demand (read+write) MSHR hits 2133system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2075 # number of overall MSHR hits 2134system.cpu1.l2cache.overall_mshr_hits::total 2075 # number of overall MSHR hits 2135system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 608 # number of ReadReq MSHR misses 2136system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 244 # number of ReadReq MSHR misses 2137system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 71774 # number of ReadReq MSHR misses 2138system.cpu1.l2cache.ReadReq_mshr_misses::total 72626 # number of ReadReq MSHR misses 2139system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 112390 # number of HardPFReq MSHR misses 2140system.cpu1.l2cache.HardPFReq_mshr_misses::total 112390 # number of HardPFReq MSHR misses 2141system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28314 # number of UpgradeReq MSHR misses 2142system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28314 # number of UpgradeReq MSHR misses 2143system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22589 # number of SCUpgradeReq MSHR misses 2144system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22589 # number of SCUpgradeReq MSHR misses 2145system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 32299 # number of ReadExReq MSHR misses 2146system.cpu1.l2cache.ReadExReq_mshr_misses::total 32299 # number of ReadExReq MSHR misses 2147system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 608 # number of demand (read+write) MSHR misses 2148system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 244 # number of demand (read+write) MSHR misses 2149system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 104073 # number of demand (read+write) MSHR misses 2150system.cpu1.l2cache.demand_mshr_misses::total 104925 # number of demand (read+write) MSHR misses 2151system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 608 # number of overall MSHR misses 2152system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 244 # number of overall MSHR misses 2153system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 104073 # number of overall MSHR misses 2154system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 112390 # number of overall MSHR misses 2155system.cpu1.l2cache.overall_mshr_misses::total 217315 # number of overall MSHR misses 2156system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of ReadReq MSHR miss cycles 2157system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3171000 # number of ReadReq MSHR miss cycles 2158system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1134657222 # number of ReadReq MSHR miss cycles 2159system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1146878474 # number of ReadReq MSHR miss cycles 2160system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3172675528 # number of HardPFReq MSHR miss cycles 2161system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3172675528 # number of HardPFReq MSHR miss cycles 2162system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 408265220 # number of UpgradeReq MSHR miss cycles 2163system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 408265220 # number of UpgradeReq MSHR miss cycles 2164system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 310198725 # number of SCUpgradeReq MSHR miss cycles 2165system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 310198725 # number of SCUpgradeReq MSHR miss cycles 2166system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 254500 # number of SCUpgradeFailReq MSHR miss cycles 2167system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 254500 # number of SCUpgradeFailReq MSHR miss cycles 2168system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 858509328 # number of ReadExReq MSHR miss cycles 2169system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 858509328 # number of ReadExReq MSHR miss cycles 2170system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of demand (read+write) MSHR miss cycles 2171system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3171000 # number of demand (read+write) MSHR miss cycles 2172system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1993166550 # number of demand (read+write) MSHR miss cycles 2173system.cpu1.l2cache.demand_mshr_miss_latency::total 2005387802 # number of demand (read+write) MSHR miss cycles 2174system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9050252 # number of overall MSHR miss cycles 2175system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3171000 # number of overall MSHR miss cycles 2176system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1993166550 # number of overall MSHR miss cycles 2177system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3172675528 # number of overall MSHR miss cycles 2178system.cpu1.l2cache.overall_mshr_miss_latency::total 5178063330 # number of overall MSHR miss cycles 2179system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 388960005 # number of ReadReq MSHR uncacheable cycles 2180system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 388960005 # number of ReadReq MSHR uncacheable cycles 2181system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 260468006 # number of WriteReq MSHR uncacheable cycles 2182system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 260468006 # number of WriteReq MSHR uncacheable cycles 2183system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 649428011 # number of overall MSHR uncacheable cycles 2184system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 649428011 # number of overall MSHR uncacheable cycles 2185system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for ReadReq accesses 2186system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for ReadReq accesses 2187system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.065439 # mshr miss rate for ReadReq accesses 2188system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.064579 # mshr miss rate for ReadReq accesses |
| 2173system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2174system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2189system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2190system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2175system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.905455 # mshr miss rate for UpgradeReq accesses 2176system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.905455 # mshr miss rate for UpgradeReq accesses 2177system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.915400 # mshr miss rate for SCUpgradeReq accesses 2178system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915400 # mshr miss rate for SCUpgradeReq accesses 2179system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 2180system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2181system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.166091 # mshr miss rate for ReadExReq accesses 2182system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.166091 # mshr miss rate for ReadExReq accesses 2183system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for demand accesses 2184system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for demand accesses 2185system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.071626 # mshr miss rate for demand accesses 2186system.cpu1.l2cache.demand_mshr_miss_rate::total 0.069872 # mshr miss rate for demand accesses 2187system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.016617 # mshr miss rate for overall accesses 2188system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019200 # mshr miss rate for overall accesses 2189system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.071626 # mshr miss rate for overall accesses | 2191system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.937270 # mshr miss rate for UpgradeReq accesses 2192system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937270 # mshr miss rate for UpgradeReq accesses 2193system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968446 # mshr miss rate for SCUpgradeReq accesses 2194system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968446 # mshr miss rate for SCUpgradeReq accesses 2195system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.514742 # mshr miss rate for ReadExReq accesses 2196system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.514742 # mshr miss rate for ReadExReq accesses 2197system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for demand accesses 2198system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for demand accesses 2199system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.089752 # mshr miss rate for demand accesses 2200system.cpu1.l2cache.demand_mshr_miss_rate::total 0.088369 # mshr miss rate for demand accesses 2201system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024223 # mshr miss rate for overall accesses 2202system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090673 # mshr miss rate for overall accesses 2203system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.089752 # mshr miss rate for overall accesses |
| 2190system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2204system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2191system.cpu1.l2cache.overall_mshr_miss_rate::total 0.238103 # mshr miss rate for overall accesses 2192system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average ReadReq mshr miss latency 2193system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average ReadReq mshr miss latency 2194system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18190.691348 # average ReadReq mshr miss latency 2195system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18164.907783 # average ReadReq mshr miss latency 2196system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51692.257084 # average HardPFReq mshr miss latency 2197system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51692.257084 # average HardPFReq mshr miss latency 2198system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16453.369157 # average UpgradeReq mshr miss latency 2199system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16453.369157 # average UpgradeReq mshr miss latency 2200system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14248.954190 # average SCUpgradeReq mshr miss latency 2201system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14248.954190 # average SCUpgradeReq mshr miss latency 2202system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 218166.666667 # average SCUpgradeFailReq mshr miss latency 2203system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 218166.666667 # average SCUpgradeFailReq mshr miss latency 2204system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27725.903639 # average ReadExReq mshr miss latency 2205system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27725.903639 # average ReadExReq mshr miss latency 2206system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency 2207system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency 2208system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency 2209system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20832.172258 # average overall mshr miss latency 2210system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency 2211system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency 2212system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency 2213system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51692.257084 # average overall mshr miss latency 2214system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42636.251006 # average overall mshr miss latency | 2205system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183025 # mshr miss rate for overall accesses 2206system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average ReadReq mshr miss latency 2207system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average ReadReq mshr miss latency 2208system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15808.749993 # average ReadReq mshr miss latency 2209system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15791.568777 # average ReadReq mshr miss latency 2210system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096 # average HardPFReq mshr miss latency 2211system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28229.162096 # average HardPFReq mshr miss latency 2212system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14419.199689 # average UpgradeReq mshr miss latency 2213system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14419.199689 # average UpgradeReq mshr miss latency 2214system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13732.291159 # average SCUpgradeReq mshr miss latency 2215system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13732.291159 # average SCUpgradeReq mshr miss latency 2216system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency 2217system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2218system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 26580.059073 # average ReadExReq mshr miss latency 2219system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26580.059073 # average ReadExReq mshr miss latency 2220system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average overall mshr miss latency 2221system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average overall mshr miss latency 2222system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19151.620017 # average overall mshr miss latency 2223system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19112.583293 # average overall mshr miss latency 2224system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14885.282895 # average overall mshr miss latency 2225system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12995.901639 # average overall mshr miss latency 2226system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19151.620017 # average overall mshr miss latency 2227system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28229.162096 # average overall mshr miss latency 2228system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23827.454755 # average overall mshr miss latency |
| 2215system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2216system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2217system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2218system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2219system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2220system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2221system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2229system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2230system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2231system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2232system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2233system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2234system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2235system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2222system.cpu1.dcache.tags.replacements 322748 # number of replacements 2223system.cpu1.dcache.tags.tagsinuse 491.331318 # Cycle average of tags in use 2224system.cpu1.dcache.tags.total_refs 11400815 # Total number of references to valid blocks. 2225system.cpu1.dcache.tags.sampled_refs 323107 # Sample count of references to valid blocks. 2226system.cpu1.dcache.tags.avg_refs 35.284952 # Average number of references to valid blocks. 2227system.cpu1.dcache.tags.warmup_cycle 72473667000 # Cycle when the warmup percentage was hit. 2228system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.331318 # Average occupied blocks per requestor 2229system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959631 # Average percentage of cache occupancy 2230system.cpu1.dcache.tags.occ_percent::total 0.959631 # Average percentage of cache occupancy 2231system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id 2232system.cpu1.dcache.tags.age_task_id_blocks_1024::2 359 # Occupied blocks per task id 2233system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id 2234system.cpu1.dcache.tags.tag_accesses 24164293 # Number of tag accesses 2235system.cpu1.dcache.tags.data_accesses 24164293 # Number of data accesses 2236system.cpu1.dcache.ReadReq_hits::cpu1.inst 6375660 # number of ReadReq hits 2237system.cpu1.dcache.ReadReq_hits::total 6375660 # number of ReadReq hits 2238system.cpu1.dcache.WriteReq_hits::cpu1.inst 4821255 # number of WriteReq hits 2239system.cpu1.dcache.WriteReq_hits::total 4821255 # number of WriteReq hits 2240system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 83384 # number of LoadLockedReq hits 2241system.cpu1.dcache.LoadLockedReq_hits::total 83384 # number of LoadLockedReq hits 2242system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 81522 # number of StoreCondReq hits 2243system.cpu1.dcache.StoreCondReq_hits::total 81522 # number of StoreCondReq hits 2244system.cpu1.dcache.demand_hits::cpu1.inst 11196915 # number of demand (read+write) hits 2245system.cpu1.dcache.demand_hits::total 11196915 # number of demand (read+write) hits 2246system.cpu1.dcache.overall_hits::cpu1.inst 11196915 # number of overall hits 2247system.cpu1.dcache.overall_hits::total 11196915 # number of overall hits 2248system.cpu1.dcache.ReadReq_misses::cpu1.inst 235192 # number of ReadReq misses 2249system.cpu1.dcache.ReadReq_misses::total 235192 # number of ReadReq misses 2250system.cpu1.dcache.WriteReq_misses::cpu1.inst 286280 # number of WriteReq misses 2251system.cpu1.dcache.WriteReq_misses::total 286280 # number of WriteReq misses 2252system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 11913 # number of LoadLockedReq misses 2253system.cpu1.dcache.LoadLockedReq_misses::total 11913 # number of LoadLockedReq misses 2254system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 13691 # number of StoreCondReq misses 2255system.cpu1.dcache.StoreCondReq_misses::total 13691 # number of StoreCondReq misses 2256system.cpu1.dcache.demand_misses::cpu1.inst 521472 # number of demand (read+write) misses 2257system.cpu1.dcache.demand_misses::total 521472 # number of demand (read+write) misses 2258system.cpu1.dcache.overall_misses::cpu1.inst 521472 # number of overall misses 2259system.cpu1.dcache.overall_misses::total 521472 # number of overall misses 2260system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3078984138 # number of ReadReq miss cycles 2261system.cpu1.dcache.ReadReq_miss_latency::total 3078984138 # number of ReadReq miss cycles 2262system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 4572469338 # number of WriteReq miss cycles 2263system.cpu1.dcache.WriteReq_miss_latency::total 4572469338 # number of WriteReq miss cycles 2264system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 214431997 # number of LoadLockedReq miss cycles 2265system.cpu1.dcache.LoadLockedReq_miss_latency::total 214431997 # number of LoadLockedReq miss cycles 2266system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 314961410 # number of StoreCondReq miss cycles 2267system.cpu1.dcache.StoreCondReq_miss_latency::total 314961410 # number of StoreCondReq miss cycles 2268system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 915000 # number of StoreCondFailReq miss cycles 2269system.cpu1.dcache.StoreCondFailReq_miss_latency::total 915000 # number of StoreCondFailReq miss cycles 2270system.cpu1.dcache.demand_miss_latency::cpu1.inst 7651453476 # number of demand (read+write) miss cycles 2271system.cpu1.dcache.demand_miss_latency::total 7651453476 # number of demand (read+write) miss cycles 2272system.cpu1.dcache.overall_miss_latency::cpu1.inst 7651453476 # number of overall miss cycles 2273system.cpu1.dcache.overall_miss_latency::total 7651453476 # number of overall miss cycles 2274system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6610852 # number of ReadReq accesses(hits+misses) 2275system.cpu1.dcache.ReadReq_accesses::total 6610852 # number of ReadReq accesses(hits+misses) 2276system.cpu1.dcache.WriteReq_accesses::cpu1.inst 5107535 # number of WriteReq accesses(hits+misses) 2277system.cpu1.dcache.WriteReq_accesses::total 5107535 # number of WriteReq accesses(hits+misses) 2278system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 95297 # number of LoadLockedReq accesses(hits+misses) 2279system.cpu1.dcache.LoadLockedReq_accesses::total 95297 # number of LoadLockedReq accesses(hits+misses) 2280system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 95213 # number of StoreCondReq accesses(hits+misses) 2281system.cpu1.dcache.StoreCondReq_accesses::total 95213 # number of StoreCondReq accesses(hits+misses) 2282system.cpu1.dcache.demand_accesses::cpu1.inst 11718387 # number of demand (read+write) accesses 2283system.cpu1.dcache.demand_accesses::total 11718387 # number of demand (read+write) accesses 2284system.cpu1.dcache.overall_accesses::cpu1.inst 11718387 # number of overall (read+write) accesses 2285system.cpu1.dcache.overall_accesses::total 11718387 # number of overall (read+write) accesses 2286system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.035577 # miss rate for ReadReq accesses 2287system.cpu1.dcache.ReadReq_miss_rate::total 0.035577 # miss rate for ReadReq accesses 2288system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.056051 # miss rate for WriteReq accesses 2289system.cpu1.dcache.WriteReq_miss_rate::total 0.056051 # miss rate for WriteReq accesses 2290system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.125009 # miss rate for LoadLockedReq accesses 2291system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125009 # miss rate for LoadLockedReq accesses 2292system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.143793 # miss rate for StoreCondReq accesses 2293system.cpu1.dcache.StoreCondReq_miss_rate::total 0.143793 # miss rate for StoreCondReq accesses 2294system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044500 # miss rate for demand accesses 2295system.cpu1.dcache.demand_miss_rate::total 0.044500 # miss rate for demand accesses 2296system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044500 # miss rate for overall accesses 2297system.cpu1.dcache.overall_miss_rate::total 0.044500 # miss rate for overall accesses 2298system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 13091.364239 # average ReadReq miss latency 2299system.cpu1.dcache.ReadReq_avg_miss_latency::total 13091.364239 # average ReadReq miss latency 2300system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15972.018087 # average WriteReq miss latency 2301system.cpu1.dcache.WriteReq_avg_miss_latency::total 15972.018087 # average WriteReq miss latency 2302system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 17999.831864 # average LoadLockedReq miss latency 2303system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17999.831864 # average LoadLockedReq miss latency 2304system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23004.996713 # average StoreCondReq miss latency 2305system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23004.996713 # average StoreCondReq miss latency | 2236system.cpu1.dcache.tags.replacements 193696 # number of replacements 2237system.cpu1.dcache.tags.tagsinuse 469.979850 # Cycle average of tags in use 2238system.cpu1.dcache.tags.total_refs 7249545 # Total number of references to valid blocks. 2239system.cpu1.dcache.tags.sampled_refs 194043 # Sample count of references to valid blocks. 2240system.cpu1.dcache.tags.avg_refs 37.360508 # Average number of references to valid blocks. 2241system.cpu1.dcache.tags.warmup_cycle 107387908500 # Cycle when the warmup percentage was hit. 2242system.cpu1.dcache.tags.occ_blocks::cpu1.inst 469.979850 # Average occupied blocks per requestor 2243system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.917929 # Average percentage of cache occupancy 2244system.cpu1.dcache.tags.occ_percent::total 0.917929 # Average percentage of cache occupancy 2245system.cpu1.dcache.tags.occ_task_id_blocks::1024 347 # Occupied blocks per task id 2246system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 2247system.cpu1.dcache.tags.age_task_id_blocks_1024::3 67 # Occupied blocks per task id 2248system.cpu1.dcache.tags.occ_task_id_percent::1024 0.677734 # Percentage of cache occupancy per task id 2249system.cpu1.dcache.tags.tag_accesses 15373685 # Number of tag accesses 2250system.cpu1.dcache.tags.data_accesses 15373685 # Number of data accesses 2251system.cpu1.dcache.ReadReq_hits::cpu1.inst 3863317 # number of ReadReq hits 2252system.cpu1.dcache.ReadReq_hits::total 3863317 # number of ReadReq hits 2253system.cpu1.dcache.WriteReq_hits::cpu1.inst 3184030 # number of WriteReq hits 2254system.cpu1.dcache.WriteReq_hits::total 3184030 # number of WriteReq hits 2255system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 91016 # number of LoadLockedReq hits 2256system.cpu1.dcache.LoadLockedReq_hits::total 91016 # number of LoadLockedReq hits 2257system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 71184 # number of StoreCondReq hits 2258system.cpu1.dcache.StoreCondReq_hits::total 71184 # number of StoreCondReq hits 2259system.cpu1.dcache.demand_hits::cpu1.inst 7047347 # number of demand (read+write) hits 2260system.cpu1.dcache.demand_hits::total 7047347 # number of demand (read+write) hits 2261system.cpu1.dcache.overall_hits::cpu1.inst 7047347 # number of overall hits 2262system.cpu1.dcache.overall_hits::total 7047347 # number of overall hits 2263system.cpu1.dcache.ReadReq_misses::cpu1.inst 184713 # number of ReadReq misses 2264system.cpu1.dcache.ReadReq_misses::total 184713 # number of ReadReq misses 2265system.cpu1.dcache.WriteReq_misses::cpu1.inst 145139 # number of WriteReq misses 2266system.cpu1.dcache.WriteReq_misses::total 145139 # number of WriteReq misses 2267system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5273 # number of LoadLockedReq misses 2268system.cpu1.dcache.LoadLockedReq_misses::total 5273 # number of LoadLockedReq misses 2269system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23325 # number of StoreCondReq misses 2270system.cpu1.dcache.StoreCondReq_misses::total 23325 # number of StoreCondReq misses 2271system.cpu1.dcache.demand_misses::cpu1.inst 329852 # number of demand (read+write) misses 2272system.cpu1.dcache.demand_misses::total 329852 # number of demand (read+write) misses 2273system.cpu1.dcache.overall_misses::cpu1.inst 329852 # number of overall misses 2274system.cpu1.dcache.overall_misses::total 329852 # number of overall misses 2275system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2791622179 # number of ReadReq miss cycles 2276system.cpu1.dcache.ReadReq_miss_latency::total 2791622179 # number of ReadReq miss cycles 2277system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3393821873 # number of WriteReq miss cycles 2278system.cpu1.dcache.WriteReq_miss_latency::total 3393821873 # number of WriteReq miss cycles 2279system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 95816000 # number of LoadLockedReq miss cycles 2280system.cpu1.dcache.LoadLockedReq_miss_latency::total 95816000 # number of LoadLockedReq miss cycles 2281system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 543674761 # number of StoreCondReq miss cycles 2282system.cpu1.dcache.StoreCondReq_miss_latency::total 543674761 # number of StoreCondReq miss cycles 2283system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 324500 # number of StoreCondFailReq miss cycles 2284system.cpu1.dcache.StoreCondFailReq_miss_latency::total 324500 # number of StoreCondFailReq miss cycles 2285system.cpu1.dcache.demand_miss_latency::cpu1.inst 6185444052 # number of demand (read+write) miss cycles 2286system.cpu1.dcache.demand_miss_latency::total 6185444052 # number of demand (read+write) miss cycles 2287system.cpu1.dcache.overall_miss_latency::cpu1.inst 6185444052 # number of overall miss cycles 2288system.cpu1.dcache.overall_miss_latency::total 6185444052 # number of overall miss cycles 2289system.cpu1.dcache.ReadReq_accesses::cpu1.inst 4048030 # number of ReadReq accesses(hits+misses) 2290system.cpu1.dcache.ReadReq_accesses::total 4048030 # number of ReadReq accesses(hits+misses) 2291system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3329169 # number of WriteReq accesses(hits+misses) 2292system.cpu1.dcache.WriteReq_accesses::total 3329169 # number of WriteReq accesses(hits+misses) 2293system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 96289 # number of LoadLockedReq accesses(hits+misses) 2294system.cpu1.dcache.LoadLockedReq_accesses::total 96289 # number of LoadLockedReq accesses(hits+misses) 2295system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 94509 # number of StoreCondReq accesses(hits+misses) 2296system.cpu1.dcache.StoreCondReq_accesses::total 94509 # number of StoreCondReq accesses(hits+misses) 2297system.cpu1.dcache.demand_accesses::cpu1.inst 7377199 # number of demand (read+write) accesses 2298system.cpu1.dcache.demand_accesses::total 7377199 # number of demand (read+write) accesses 2299system.cpu1.dcache.overall_accesses::cpu1.inst 7377199 # number of overall (read+write) accesses 2300system.cpu1.dcache.overall_accesses::total 7377199 # number of overall (read+write) accesses 2301system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045630 # miss rate for ReadReq accesses 2302system.cpu1.dcache.ReadReq_miss_rate::total 0.045630 # miss rate for ReadReq accesses 2303system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043596 # miss rate for WriteReq accesses 2304system.cpu1.dcache.WriteReq_miss_rate::total 0.043596 # miss rate for WriteReq accesses 2305system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054762 # miss rate for LoadLockedReq accesses 2306system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054762 # miss rate for LoadLockedReq accesses 2307system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.246802 # miss rate for StoreCondReq accesses 2308system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246802 # miss rate for StoreCondReq accesses 2309system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044712 # miss rate for demand accesses 2310system.cpu1.dcache.demand_miss_rate::total 0.044712 # miss rate for demand accesses 2311system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044712 # miss rate for overall accesses 2312system.cpu1.dcache.overall_miss_rate::total 0.044712 # miss rate for overall accesses 2313system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15113.295648 # average ReadReq miss latency 2314system.cpu1.dcache.ReadReq_avg_miss_latency::total 15113.295648 # average ReadReq miss latency 2315system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23383.252420 # average WriteReq miss latency 2316system.cpu1.dcache.WriteReq_avg_miss_latency::total 23383.252420 # average WriteReq miss latency 2317system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18171.060118 # average LoadLockedReq miss latency 2318system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18171.060118 # average LoadLockedReq miss latency 2319system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23308.671426 # average StoreCondReq miss latency 2320system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23308.671426 # average StoreCondReq miss latency |
| 2306system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 2307system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 2321system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 2322system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2308system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency 2309system.cpu1.dcache.demand_avg_miss_latency::total 14672.798302 # average overall miss latency 2310system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency 2311system.cpu1.dcache.overall_avg_miss_latency::total 14672.798302 # average overall miss latency | 2323system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency 2324system.cpu1.dcache.demand_avg_miss_latency::total 18752.179923 # average overall miss latency 2325system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency 2326system.cpu1.dcache.overall_avg_miss_latency::total 18752.179923 # average overall miss latency |
| 2312system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2313system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2314system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2315system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2316system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2317system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2318system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2319system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 2327system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2328system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2329system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2330system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2331system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2332system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2333system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2334system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 2320system.cpu1.dcache.writebacks::writebacks 242084 # number of writebacks 2321system.cpu1.dcache.writebacks::total 242084 # number of writebacks 2322system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36921 # number of ReadReq MSHR hits 2323system.cpu1.dcache.ReadReq_mshr_hits::total 36921 # number of ReadReq MSHR hits 2324system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129344 # number of WriteReq MSHR hits 2325system.cpu1.dcache.WriteReq_mshr_hits::total 129344 # number of WriteReq MSHR hits 2326system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 46 # number of LoadLockedReq MSHR hits 2327system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46 # number of LoadLockedReq MSHR hits 2328system.cpu1.dcache.demand_mshr_hits::cpu1.inst 166265 # number of demand (read+write) MSHR hits 2329system.cpu1.dcache.demand_mshr_hits::total 166265 # number of demand (read+write) MSHR hits 2330system.cpu1.dcache.overall_mshr_hits::cpu1.inst 166265 # number of overall MSHR hits 2331system.cpu1.dcache.overall_mshr_hits::total 166265 # number of overall MSHR hits 2332system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 198271 # number of ReadReq MSHR misses 2333system.cpu1.dcache.ReadReq_mshr_misses::total 198271 # number of ReadReq MSHR misses 2334system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156936 # number of WriteReq MSHR misses 2335system.cpu1.dcache.WriteReq_mshr_misses::total 156936 # number of WriteReq MSHR misses 2336system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11867 # number of LoadLockedReq MSHR misses 2337system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11867 # number of LoadLockedReq MSHR misses 2338system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13691 # number of StoreCondReq MSHR misses 2339system.cpu1.dcache.StoreCondReq_mshr_misses::total 13691 # number of StoreCondReq MSHR misses 2340system.cpu1.dcache.demand_mshr_misses::cpu1.inst 355207 # number of demand (read+write) MSHR misses 2341system.cpu1.dcache.demand_mshr_misses::total 355207 # number of demand (read+write) MSHR misses 2342system.cpu1.dcache.overall_mshr_misses::cpu1.inst 355207 # number of overall MSHR misses 2343system.cpu1.dcache.overall_mshr_misses::total 355207 # number of overall MSHR misses 2344system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202163297 # number of ReadReq MSHR miss cycles 2345system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202163297 # number of ReadReq MSHR miss cycles 2346system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2284592028 # number of WriteReq MSHR miss cycles 2347system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2284592028 # number of WriteReq MSHR miss cycles 2348system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 190117000 # number of LoadLockedReq MSHR miss cycles 2349system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 190117000 # number of LoadLockedReq MSHR miss cycles 2350system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286543590 # number of StoreCondReq MSHR miss cycles 2351system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286543590 # number of StoreCondReq MSHR miss cycles 2352system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 863000 # number of StoreCondFailReq MSHR miss cycles 2353system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 863000 # number of StoreCondFailReq MSHR miss cycles 2354system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4486755325 # number of demand (read+write) MSHR miss cycles 2355system.cpu1.dcache.demand_mshr_miss_latency::total 4486755325 # number of demand (read+write) MSHR miss cycles 2356system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4486755325 # number of overall MSHR miss cycles 2357system.cpu1.dcache.overall_mshr_miss_latency::total 4486755325 # number of overall MSHR miss cycles 2358system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183747450747 # number of ReadReq MSHR uncacheable cycles 2359system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183747450747 # number of ReadReq MSHR uncacheable cycles 2360system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481854358 # number of WriteReq MSHR uncacheable cycles 2361system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481854358 # number of WriteReq MSHR uncacheable cycles 2362system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218229305105 # number of overall MSHR uncacheable cycles 2363system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218229305105 # number of overall MSHR uncacheable cycles 2364system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029992 # mshr miss rate for ReadReq accesses 2365system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029992 # mshr miss rate for ReadReq accesses 2366system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030726 # mshr miss rate for WriteReq accesses 2367system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030726 # mshr miss rate for WriteReq accesses 2368system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.124526 # mshr miss rate for LoadLockedReq accesses 2369system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124526 # mshr miss rate for LoadLockedReq accesses 2370system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143793 # mshr miss rate for StoreCondReq accesses 2371system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143793 # mshr miss rate for StoreCondReq accesses 2372system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for demand accesses 2373system.cpu1.dcache.demand_mshr_miss_rate::total 0.030312 # mshr miss rate for demand accesses 2374system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for overall accesses 2375system.cpu1.dcache.overall_mshr_miss_rate::total 0.030312 # mshr miss rate for overall accesses 2376system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11106.835074 # average ReadReq mshr miss latency 2377system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11106.835074 # average ReadReq mshr miss latency 2378system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14557.475837 # average WriteReq mshr miss latency 2379system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14557.475837 # average WriteReq mshr miss latency 2380system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16020.645487 # average LoadLockedReq mshr miss latency 2381system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16020.645487 # average LoadLockedReq mshr miss latency 2382system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20929.339712 # average StoreCondReq mshr miss latency 2383system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20929.339712 # average StoreCondReq mshr miss latency | 2335system.cpu1.dcache.writebacks::writebacks 119069 # number of writebacks 2336system.cpu1.dcache.writebacks::total 119069 # number of writebacks 2337system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15047 # number of ReadReq MSHR hits 2338system.cpu1.dcache.ReadReq_mshr_hits::total 15047 # number of ReadReq MSHR hits 2339system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 52186 # number of WriteReq MSHR hits 2340system.cpu1.dcache.WriteReq_mshr_hits::total 52186 # number of WriteReq MSHR hits 2341system.cpu1.dcache.demand_mshr_hits::cpu1.inst 67233 # number of demand (read+write) MSHR hits 2342system.cpu1.dcache.demand_mshr_hits::total 67233 # number of demand (read+write) MSHR hits 2343system.cpu1.dcache.overall_mshr_hits::cpu1.inst 67233 # number of overall MSHR hits 2344system.cpu1.dcache.overall_mshr_hits::total 67233 # number of overall MSHR hits 2345system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 169666 # number of ReadReq MSHR misses 2346system.cpu1.dcache.ReadReq_mshr_misses::total 169666 # number of ReadReq MSHR misses 2347system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 92953 # number of WriteReq MSHR misses 2348system.cpu1.dcache.WriteReq_mshr_misses::total 92953 # number of WriteReq MSHR misses 2349system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5273 # number of LoadLockedReq MSHR misses 2350system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5273 # number of LoadLockedReq MSHR misses 2351system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23325 # number of StoreCondReq MSHR misses 2352system.cpu1.dcache.StoreCondReq_mshr_misses::total 23325 # number of StoreCondReq MSHR misses 2353system.cpu1.dcache.demand_mshr_misses::cpu1.inst 262619 # number of demand (read+write) MSHR misses 2354system.cpu1.dcache.demand_mshr_misses::total 262619 # number of demand (read+write) MSHR misses 2355system.cpu1.dcache.overall_mshr_misses::cpu1.inst 262619 # number of overall MSHR misses 2356system.cpu1.dcache.overall_mshr_misses::total 262619 # number of overall MSHR misses 2357system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2247676267 # number of ReadReq MSHR miss cycles 2358system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247676267 # number of ReadReq MSHR miss cycles 2359system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2022089921 # number of WriteReq MSHR miss cycles 2360system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2022089921 # number of WriteReq MSHR miss cycles 2361system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 85260000 # number of LoadLockedReq MSHR miss cycles 2362system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85260000 # number of LoadLockedReq MSHR miss cycles 2363system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 495802239 # number of StoreCondReq MSHR miss cycles 2364system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495802239 # number of StoreCondReq MSHR miss cycles 2365system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 310500 # number of StoreCondFailReq MSHR miss cycles 2366system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 310500 # number of StoreCondFailReq MSHR miss cycles 2367system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4269766188 # number of demand (read+write) MSHR miss cycles 2368system.cpu1.dcache.demand_mshr_miss_latency::total 4269766188 # number of demand (read+write) MSHR miss cycles 2369system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4269766188 # number of overall MSHR miss cycles 2370system.cpu1.dcache.overall_mshr_miss_latency::total 4269766188 # number of overall MSHR miss cycles 2371system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 405245745 # number of ReadReq MSHR uncacheable cycles 2372system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 405245745 # number of ReadReq MSHR uncacheable cycles 2373system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 279561993 # number of WriteReq MSHR uncacheable cycles 2374system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279561993 # number of WriteReq MSHR uncacheable cycles 2375system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 684807738 # number of overall MSHR uncacheable cycles 2376system.cpu1.dcache.overall_mshr_uncacheable_latency::total 684807738 # number of overall MSHR uncacheable cycles 2377system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.041913 # mshr miss rate for ReadReq accesses 2378system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041913 # mshr miss rate for ReadReq accesses 2379system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027921 # mshr miss rate for WriteReq accesses 2380system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027921 # mshr miss rate for WriteReq accesses 2381system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054762 # mshr miss rate for LoadLockedReq accesses 2382system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054762 # mshr miss rate for LoadLockedReq accesses 2383system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.246802 # mshr miss rate for StoreCondReq accesses 2384system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246802 # mshr miss rate for StoreCondReq accesses 2385system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for demand accesses 2386system.cpu1.dcache.demand_mshr_miss_rate::total 0.035599 # mshr miss rate for demand accesses 2387system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for overall accesses 2388system.cpu1.dcache.overall_mshr_miss_rate::total 0.035599 # mshr miss rate for overall accesses 2389system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13247.652841 # average ReadReq mshr miss latency 2390system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13247.652841 # average ReadReq mshr miss latency 2391system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 21753.896281 # average WriteReq mshr miss latency 2392system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21753.896281 # average WriteReq mshr miss latency 2393system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16169.163664 # average LoadLockedReq mshr miss latency 2394system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16169.163664 # average LoadLockedReq mshr miss latency 2395system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21256.258907 # average StoreCondReq mshr miss latency 2396system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21256.258907 # average StoreCondReq mshr miss latency |
| 2384system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 2385system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2397system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 2398system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2386system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency 2387system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency 2388system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency 2389system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency | 2399system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency 2400system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency 2401system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency 2402system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency |
| 2390system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2391system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2392system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2393system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2394system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2395system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2396system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2403system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2404system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2405system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2406system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2407system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2408system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2409system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2397system.iocache.tags.replacements 0 # number of replacements 2398system.iocache.tags.tagsinuse 0 # Cycle average of tags in use | 2410system.iocache.tags.replacements 36445 # number of replacements 2411system.iocache.tags.tagsinuse 14.485749 # Cycle average of tags in use |
| 2399system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 2412system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 2400system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 2401system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 2402system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2403system.iocache.tags.tag_accesses 0 # Number of tag accesses 2404system.iocache.tags.data_accesses 0 # Number of data accesses | 2413system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2414system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2415system.iocache.tags.warmup_cycle 268964842000 # Cycle when the warmup percentage was hit. 2416system.iocache.tags.occ_blocks::realview.ide 14.485749 # Average occupied blocks per requestor 2417system.iocache.tags.occ_percent::realview.ide 0.905359 # Average percentage of cache occupancy 2418system.iocache.tags.occ_percent::total 0.905359 # Average percentage of cache occupancy 2419system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2420system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2421system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2422system.iocache.tags.tag_accesses 328575 # Number of tag accesses 2423system.iocache.tags.data_accesses 328575 # Number of data accesses 2424system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2425system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 2426system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2427system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2428system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses 2429system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses 2430system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2431system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2432system.iocache.overall_misses::realview.ide 255 # number of overall misses 2433system.iocache.overall_misses::total 255 # number of overall misses 2434system.iocache.ReadReq_miss_latency::realview.ide 31822377 # number of ReadReq miss cycles 2435system.iocache.ReadReq_miss_latency::total 31822377 # number of ReadReq miss cycles 2436system.iocache.demand_miss_latency::realview.ide 31822377 # number of demand (read+write) miss cycles 2437system.iocache.demand_miss_latency::total 31822377 # number of demand (read+write) miss cycles 2438system.iocache.overall_miss_latency::realview.ide 31822377 # number of overall miss cycles 2439system.iocache.overall_miss_latency::total 31822377 # number of overall miss cycles 2440system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2441system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2442system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) 2443system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) 2444system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2445system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2446system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2447system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses 2448system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2449system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2450system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses 2451system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses 2452system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2453system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2454system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2455system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2456system.iocache.ReadReq_avg_miss_latency::realview.ide 124793.635294 # average ReadReq miss latency 2457system.iocache.ReadReq_avg_miss_latency::total 124793.635294 # average ReadReq miss latency 2458system.iocache.demand_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency 2459system.iocache.demand_avg_miss_latency::total 124793.635294 # average overall miss latency 2460system.iocache.overall_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency 2461system.iocache.overall_avg_miss_latency::total 124793.635294 # average overall miss latency |
| 2405system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2406system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2407system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2408system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2409system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2410system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2462system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2463system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2464system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2465system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2466system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2467system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2411system.iocache.fast_writes 0 # number of fast writes performed | 2468system.iocache.fast_writes 36224 # number of fast writes performed |
| 2412system.iocache.cache_copies 0 # number of cache copies performed | 2469system.iocache.cache_copies 0 # number of cache copies performed |
| 2413system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of ReadReq MSHR uncacheable cycles 2414system.iocache.ReadReq_mshr_uncacheable_latency::total 1759755743315 # number of ReadReq MSHR uncacheable cycles 2415system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of overall MSHR uncacheable cycles 2416system.iocache.overall_mshr_uncacheable_latency::total 1759755743315 # number of overall MSHR uncacheable cycles 2417system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2418system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2419system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2420system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 2470system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2471system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2472system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2473system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2474system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2475system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses 2476system.iocache.ReadReq_mshr_miss_latency::realview.ide 18561377 # number of ReadReq MSHR miss cycles 2477system.iocache.ReadReq_mshr_miss_latency::total 18561377 # number of ReadReq MSHR miss cycles 2478system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2257984064 # number of WriteInvalidateReq MSHR miss cycles 2479system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2257984064 # number of WriteInvalidateReq MSHR miss cycles 2480system.iocache.demand_mshr_miss_latency::realview.ide 18561377 # number of demand (read+write) MSHR miss cycles 2481system.iocache.demand_mshr_miss_latency::total 18561377 # number of demand (read+write) MSHR miss cycles 2482system.iocache.overall_mshr_miss_latency::realview.ide 18561377 # number of overall MSHR miss cycles 2483system.iocache.overall_mshr_miss_latency::total 18561377 # number of overall MSHR miss cycles 2484system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2485system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2486system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2487system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2488system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2489system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2490system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72789.713725 # average ReadReq mshr miss latency 2491system.iocache.ReadReq_avg_mshr_miss_latency::total 72789.713725 # average ReadReq mshr miss latency 2492system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2493system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2494system.iocache.demand_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency 2495system.iocache.demand_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency 2496system.iocache.overall_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency 2497system.iocache.overall_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency |
| 2421system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2422 2423---------- End Simulation Statistics ---------- | 2498system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2499 2500---------- End Simulation Statistics ---------- |