1 2---------- Begin Simulation Statistics ----------
|
3sim_seconds 2.843665 # Number of seconds simulated
4sim_ticks 2843665155500 # Number of ticks simulated
5final_tick 2843665155500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
3sim_seconds 2.843655 # Number of seconds simulated 4sim_ticks 2843654861000 # Number of ticks simulated 5final_tick 2843654861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 158211 # Simulator instruction rate (inst/s)
8host_op_rate 191554 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3597700350 # Simulator tick rate (ticks/s)
10host_mem_usage 605956 # Number of bytes of host memory used
11host_seconds 790.41 # Real time elapsed on the host
12sim_insts 125052080 # Number of instructions simulated
13sim_ops 151406456 # Number of ops (including micro ops) simulated
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7host_inst_rate 157498 # Simulator instruction rate (inst/s) 8host_op_rate 190690 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3581426538 # Simulator tick rate (ticks/s) 10host_mem_usage 613612 # Number of bytes of host memory used 11host_seconds 794.00 # Real time elapsed on the host 12sim_insts 125053138 # Number of instructions simulated 13sim_ops 151407658 # Number of ops (including micro ops) simulated |
14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
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16system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory
17system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
18system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory
19system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory
20system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory
21system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory
22system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
23system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
24system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory
25system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s)
26system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s)
27system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s)
28system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s)
29system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s)
30system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s)
32system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s)
33system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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16system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
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37system.physmem.bytes_read::cpu0.inst 1364476 # Number of bytes read from this memory
38system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766720 # Number of bytes read from this memory
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18system.physmem.bytes_read::cpu0.inst 1363068 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.l2cache.prefetcher 10771008 # Number of bytes read from this memory |
20system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
|
40system.physmem.bytes_read::cpu1.inst 533600 # Number of bytes read from this memory
41system.physmem.bytes_read::cpu1.l2cache.prefetcher 1164672 # Number of bytes read from this memory
42system.physmem.bytes_read::total 13841116 # Number of bytes read from this memory
43system.physmem.bytes_inst_read::cpu0.inst 419072 # Number of instructions bytes read from this memory
44system.physmem.bytes_inst_read::cpu1.inst 26240 # Number of instructions bytes read from this memory
45system.physmem.bytes_inst_read::total 445312 # Number of instructions bytes read from this memory
46system.physmem.bytes_written::writebacks 7174080 # Number of bytes written to this memory
47system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
|
21system.physmem.bytes_read::cpu1.inst 534304 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.l2cache.prefetcher 1165248 # Number of bytes read from this memory 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 24system.physmem.bytes_read::total 13845276 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 418688 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 26560 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 445248 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 7176128 # Number of bytes written to this memory |
29system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory
|
50system.physmem.bytes_written::total 9510160 # Number of bytes written to this memory
51system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
31system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 32system.physmem.bytes_written::total 9512208 # Number of bytes written to this memory |
33system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
|
54system.physmem.num_reads::cpu0.inst 21845 # Number of read requests responded to by this memory
55system.physmem.num_reads::cpu0.l2cache.prefetcher 168230 # Number of read requests responded to by this memory
|
35system.physmem.num_reads::cpu0.inst 21823 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.l2cache.prefetcher 168297 # Number of read requests responded to by this memory |
37system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
|
57system.physmem.num_reads::cpu1.inst 8361 # Number of read requests responded to by this memory
58system.physmem.num_reads::cpu1.l2cache.prefetcher 18198 # Number of read requests responded to by this memory
59system.physmem.num_reads::total 216816 # Number of read requests responded to by this memory
60system.physmem.num_writes::writebacks 112095 # Number of write requests responded to by this memory
61system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
|
38system.physmem.num_reads::cpu1.inst 8372 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.l2cache.prefetcher 18207 # Number of read requests responded to by this memory 40system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 41system.physmem.num_reads::total 216881 # Number of read requests responded to by this memory 42system.physmem.num_writes::writebacks 112127 # Number of write requests responded to by this memory |
43system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory
|
64system.physmem.num_writes::total 152755 # Number of write requests responded to by this memory
65system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s)
|
45system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 152787 # Number of write requests responded to by this memory |
47system.physmem.bw_read::cpu0.dtb.walker 3398 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
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68system.physmem.bw_read::cpu0.inst 479830 # Total read bandwidth from this memory (bytes/s)
69system.physmem.bw_read::cpu0.l2cache.prefetcher 3786212 # Total read bandwidth from this memory (bytes/s)
|
49system.physmem.bw_read::cpu0.inst 479337 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.l2cache.prefetcher 3787734 # Total read bandwidth from this memory (bytes/s) |
51system.physmem.bw_read::cpu1.dtb.walker 338 # Total read bandwidth from this memory (bytes/s)
|
71system.physmem.bw_read::cpu1.inst 187645 # Total read bandwidth from this memory (bytes/s)
72system.physmem.bw_read::cpu1.l2cache.prefetcher 409567 # Total read bandwidth from this memory (bytes/s)
73system.physmem.bw_read::total 4867351 # Total read bandwidth from this memory (bytes/s)
74system.physmem.bw_inst_read::cpu0.inst 147370 # Instruction read bandwidth from this memory (bytes/s)
75system.physmem.bw_inst_read::cpu1.inst 9228 # Instruction read bandwidth from this memory (bytes/s)
76system.physmem.bw_inst_read::total 156598 # Instruction read bandwidth from this memory (bytes/s)
77system.physmem.bw_write::writebacks 2522829 # Write bandwidth from this memory (bytes/s)
78system.physmem.bw_write::realview.ide 815263 # Write bandwidth from this memory (bytes/s)
|
52system.physmem.bw_read::cpu1.inst 187893 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.l2cache.prefetcher 409771 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::total 4868831 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu0.inst 147236 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu1.inst 9340 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::total 156576 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_write::writebacks 2523558 # Write bandwidth from this memory (bytes/s) |
60system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s)
|
81system.physmem.bw_write::total 3344332 # Write bandwidth from this memory (bytes/s)
82system.physmem.bw_total::writebacks 2522829 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::realview.ide 815601 # Total bandwidth to/from this memory (bytes/s)
|
62system.physmem.bw_write::realview.ide 815266 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 3345064 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2523558 # Total bandwidth to/from this memory (bytes/s) |
65system.physmem.bw_total::cpu0.dtb.walker 3398 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
|
86system.physmem.bw_total::cpu0.inst 486056 # Total bandwidth to/from this memory (bytes/s)
87system.physmem.bw_total::cpu0.l2cache.prefetcher 3786212 # Total bandwidth to/from this memory (bytes/s)
|
67system.physmem.bw_total::cpu0.inst 485562 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.l2cache.prefetcher 3787734 # Total bandwidth to/from this memory (bytes/s) |
69system.physmem.bw_total::cpu1.dtb.walker 338 # Total bandwidth to/from this memory (bytes/s)
|
89system.physmem.bw_total::cpu1.inst 187659 # Total bandwidth to/from this memory (bytes/s)
90system.physmem.bw_total::cpu1.l2cache.prefetcher 409567 # Total bandwidth to/from this memory (bytes/s)
91system.physmem.bw_total::total 8211683 # Total bandwidth to/from this memory (bytes/s)
92system.physmem.readReqs 216816 # Number of read requests accepted
93system.physmem.writeReqs 152755 # Number of write requests accepted
94system.physmem.readBursts 216816 # Number of DRAM read bursts, including those serviced by the write queue
95system.physmem.writeBursts 152755 # Number of DRAM write bursts, including those merged in the write queue
96system.physmem.bytesReadDRAM 13860032 # Total number of bytes read from DRAM
97system.physmem.bytesReadWrQ 16192 # Total number of bytes read from write queue
98system.physmem.bytesWritten 9524672 # Total number of bytes written to DRAM
99system.physmem.bytesReadSys 13841116 # Total read bytes from the system interface side
100system.physmem.bytesWrittenSys 9510160 # Total written bytes from the system interface side
101system.physmem.servicedByWrQ 253 # Number of DRAM read bursts serviced by the write queue
|
70system.physmem.bw_total::cpu1.inst 187907 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.l2cache.prefetcher 409771 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::realview.ide 815604 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::total 8213896 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.readReqs 216881 # Number of read requests accepted 75system.physmem.writeReqs 152787 # Number of write requests accepted 76system.physmem.readBursts 216881 # Number of DRAM read bursts, including those serviced by the write queue 77system.physmem.writeBursts 152787 # Number of DRAM write bursts, including those merged in the write queue 78system.physmem.bytesReadDRAM 13864960 # Total number of bytes read from DRAM 79system.physmem.bytesReadWrQ 15424 # Total number of bytes read from write queue 80system.physmem.bytesWritten 9526912 # Total number of bytes written to DRAM 81system.physmem.bytesReadSys 13845276 # Total read bytes from the system interface side 82system.physmem.bytesWrittenSys 9512208 # Total written bytes from the system interface side 83system.physmem.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue |
84system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one
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103system.physmem.neitherReadNorWriteReqs 13536 # Number of requests that are neither read nor write
104system.physmem.perBankRdBursts::0 13436 # Per bank write bursts
105system.physmem.perBankRdBursts::1 13084 # Per bank write bursts
106system.physmem.perBankRdBursts::2 14401 # Per bank write bursts
107system.physmem.perBankRdBursts::3 13747 # Per bank write bursts
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85system.physmem.neitherReadNorWriteReqs 13516 # Number of requests that are neither read nor write 86system.physmem.perBankRdBursts::0 13445 # Per bank write bursts 87system.physmem.perBankRdBursts::1 13090 # Per bank write bursts 88system.physmem.perBankRdBursts::2 14400 # Per bank write bursts 89system.physmem.perBankRdBursts::3 13760 # Per bank write bursts |
90system.physmem.perBankRdBursts::4 15799 # Per bank write bursts
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109system.physmem.perBankRdBursts::5 12797 # Per bank write bursts
110system.physmem.perBankRdBursts::6 13572 # Per bank write bursts
111system.physmem.perBankRdBursts::7 13744 # Per bank write bursts
112system.physmem.perBankRdBursts::8 13565 # Per bank write bursts
113system.physmem.perBankRdBursts::9 13602 # Per bank write bursts
114system.physmem.perBankRdBursts::10 13295 # Per bank write bursts
115system.physmem.perBankRdBursts::11 11895 # Per bank write bursts
116system.physmem.perBankRdBursts::12 13378 # Per bank write bursts
117system.physmem.perBankRdBursts::13 13725 # Per bank write bursts
118system.physmem.perBankRdBursts::14 13486 # Per bank write bursts
119system.physmem.perBankRdBursts::15 13037 # Per bank write bursts
120system.physmem.perBankWrBursts::0 9315 # Per bank write bursts
121system.physmem.perBankWrBursts::1 9418 # Per bank write bursts
122system.physmem.perBankWrBursts::2 10151 # Per bank write bursts
123system.physmem.perBankWrBursts::3 9572 # Per bank write bursts
124system.physmem.perBankWrBursts::4 8971 # Per bank write bursts
125system.physmem.perBankWrBursts::5 8910 # Per bank write bursts
126system.physmem.perBankWrBursts::6 9379 # Per bank write bursts
127system.physmem.perBankWrBursts::7 9378 # Per bank write bursts
|
91system.physmem.perBankRdBursts::5 12812 # Per bank write bursts 92system.physmem.perBankRdBursts::6 13576 # Per bank write bursts 93system.physmem.perBankRdBursts::7 13750 # Per bank write bursts 94system.physmem.perBankRdBursts::8 13572 # Per bank write bursts 95system.physmem.perBankRdBursts::9 13600 # Per bank write bursts 96system.physmem.perBankRdBursts::10 13300 # Per bank write bursts 97system.physmem.perBankRdBursts::11 11904 # Per bank write bursts 98system.physmem.perBankRdBursts::12 13370 # Per bank write bursts 99system.physmem.perBankRdBursts::13 13720 # Per bank write bursts 100system.physmem.perBankRdBursts::14 13497 # Per bank write bursts 101system.physmem.perBankRdBursts::15 13045 # Per bank write bursts 102system.physmem.perBankWrBursts::0 9322 # Per bank write bursts 103system.physmem.perBankWrBursts::1 9428 # Per bank write bursts 104system.physmem.perBankWrBursts::2 10143 # Per bank write bursts 105system.physmem.perBankWrBursts::3 9576 # Per bank write bursts 106system.physmem.perBankWrBursts::4 8974 # Per bank write bursts 107system.physmem.perBankWrBursts::5 8900 # Per bank write bursts 108system.physmem.perBankWrBursts::6 9376 # Per bank write bursts 109system.physmem.perBankWrBursts::7 9386 # Per bank write bursts |
110system.physmem.perBankWrBursts::8 9384 # Per bank write bursts
|
129system.physmem.perBankWrBursts::9 9425 # Per bank write bursts
130system.physmem.perBankWrBursts::10 9360 # Per bank write bursts
131system.physmem.perBankWrBursts::11 8832 # Per bank write bursts
132system.physmem.perBankWrBursts::12 9377 # Per bank write bursts
133system.physmem.perBankWrBursts::13 9192 # Per bank write bursts
134system.physmem.perBankWrBursts::14 9288 # Per bank write bursts
135system.physmem.perBankWrBursts::15 8871 # Per bank write bursts
|
111system.physmem.perBankWrBursts::9 9431 # Per bank write bursts 112system.physmem.perBankWrBursts::10 9355 # Per bank write bursts 113system.physmem.perBankWrBursts::11 8834 # Per bank write bursts 114system.physmem.perBankWrBursts::12 9379 # Per bank write bursts 115system.physmem.perBankWrBursts::13 9206 # Per bank write bursts 116system.physmem.perBankWrBursts::14 9289 # Per bank write bursts 117system.physmem.perBankWrBursts::15 8875 # Per bank write bursts |
118system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
137system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
138system.physmem.totGap 2843662895000 # Total gap between requests
|
119system.physmem.numWrRetry 3 # Number of times write queue was full causing retry 120system.physmem.totGap 2843652584000 # Total gap between requests |
121system.physmem.readPktSize::0 0 # Read request sizes (log2) 122system.physmem.readPktSize::1 0 # Read request sizes (log2) 123system.physmem.readPktSize::2 559 # Read request sizes (log2) 124system.physmem.readPktSize::3 28 # Read request sizes (log2) 125system.physmem.readPktSize::4 0 # Read request sizes (log2) 126system.physmem.readPktSize::5 0 # Read request sizes (log2)
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145system.physmem.readPktSize::6 216229 # Read request sizes (log2)
|
127system.physmem.readPktSize::6 216294 # Read request sizes (log2) |
128system.physmem.writePktSize::0 0 # Write request sizes (log2) 129system.physmem.writePktSize::1 0 # Write request sizes (log2) 130system.physmem.writePktSize::2 4436 # Write request sizes (log2) 131system.physmem.writePktSize::3 0 # Write request sizes (log2) 132system.physmem.writePktSize::4 0 # Write request sizes (log2) 133system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
152system.physmem.writePktSize::6 148319 # Write request sizes (log2)
153system.physmem.rdQLenPdf::0 79263 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::1 62843 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::2 17911 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::3 12269 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::4 10663 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::5 9296 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::6 8295 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::7 7452 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::8 6012 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::9 1182 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::10 433 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::11 321 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::12 208 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::13 169 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
172system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
|
134system.physmem.writePktSize::6 148351 # Write request sizes (log2) 135system.physmem.rdQLenPdf::0 79253 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::1 62833 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::2 17902 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::3 12267 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::4 10637 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::5 9321 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::6 8351 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::7 7490 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::10 425 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::11 318 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::12 210 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::13 171 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see |
155system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 167system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
200system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::16 3556 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::17 4340 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::18 5395 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::19 6276 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::20 7496 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::21 8100 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::22 8979 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::23 9748 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::24 10867 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::25 10670 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::26 10519 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::27 10413 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::28 10861 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::29 9033 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::30 8788 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::31 8722 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::32 8168 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::33 580 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::34 377 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::35 321 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::36 240 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::39 178 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::42 144 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::46 144 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::51 61 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see
240system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see
241system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see
|
182system.physmem.wrQLenPdf::15 2952 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::17 4345 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::18 5357 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::19 6270 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::20 7461 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::21 8095 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::22 8963 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::23 9736 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::24 10858 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::25 10694 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::26 10594 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::27 10430 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::28 10909 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::29 9025 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::30 8830 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::31 8791 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::32 8216 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::33 582 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::34 381 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::35 300 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::36 204 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::46 132 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see |
224system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see
|
243system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see
244system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see
245system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see
246system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see
247system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see
248system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
249system.physmem.bytesPerActivate::samples 92579 # Bytes accessed per row activation
250system.physmem.bytesPerActivate::mean 252.591884 # Bytes accessed per row activation
251system.physmem.bytesPerActivate::gmean 143.134462 # Bytes accessed per row activation
252system.physmem.bytesPerActivate::stdev 307.650054 # Bytes accessed per row activation
253system.physmem.bytesPerActivate::0-127 46986 50.75% 50.75% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::128-255 18789 20.30% 71.05% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::256-383 6843 7.39% 78.44% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::384-511 3586 3.87% 82.31% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::512-639 3022 3.26% 85.58% # Bytes accessed per row activation
|
225system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see 231system.physmem.bytesPerActivate::samples 92618 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::mean 252.562223 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::gmean 143.207145 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::stdev 307.469960 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::0-127 46921 50.66% 50.66% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::128-255 18876 20.38% 71.04% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::256-383 6855 7.40% 78.44% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::384-511 3600 3.89% 82.33% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::512-639 3008 3.25% 85.58% # Bytes accessed per row activation |
240system.physmem.bytesPerActivate::640-767 2120 2.29% 87.87% # Bytes accessed per row activation
|
259system.physmem.bytesPerActivate::768-895 1307 1.41% 89.28% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::896-1023 1131 1.22% 90.50% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::1024-1151 8795 9.50% 100.00% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::total 92579 # Bytes accessed per row activation
263system.physmem.rdPerTurnAround::samples 7460 # Reads before turning the bus around for writes
264system.physmem.rdPerTurnAround::mean 29.029759 # Reads before turning the bus around for writes
265system.physmem.rdPerTurnAround::stdev 529.579779 # Reads before turning the bus around for writes
266system.physmem.rdPerTurnAround::0-2047 7459 99.99% 99.99% # Reads before turning the bus around for writes
|
241system.physmem.bytesPerActivate::768-895 1341 1.45% 89.31% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::896-1023 1115 1.20% 90.52% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::1024-1151 8782 9.48% 100.00% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::total 92618 # Bytes accessed per row activation 245system.physmem.rdPerTurnAround::samples 7463 # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::mean 29.028407 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::stdev 529.473600 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::0-2047 7462 99.99% 99.99% # Reads before turning the bus around for writes |
249system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
|
268system.physmem.rdPerTurnAround::total 7460 # Reads before turning the bus around for writes
269system.physmem.wrPerTurnAround::samples 7460 # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::mean 19.949464 # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::gmean 18.624141 # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::stdev 10.915893 # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::16-19 6155 82.51% 82.51% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::20-23 493 6.61% 89.12% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::24-27 89 1.19% 90.31% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::28-31 200 2.68% 92.99% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::32-35 188 2.52% 95.51% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::36-39 17 0.23% 95.74% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::40-43 27 0.36% 96.10% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::44-47 16 0.21% 96.31% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::48-51 36 0.48% 96.80% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::52-55 10 0.13% 96.93% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::56-59 5 0.07% 97.00% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::60-63 4 0.05% 97.05% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::64-67 168 2.25% 99.30% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::68-71 5 0.07% 99.37% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::72-75 3 0.04% 99.41% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::76-79 4 0.05% 99.46% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::80-83 10 0.13% 99.60% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::88-91 1 0.01% 99.62% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::92-95 1 0.01% 99.64% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::96-99 2 0.03% 99.66% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::112-115 5 0.07% 99.83% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::116-119 4 0.05% 99.88% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::120-123 1 0.01% 99.89% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::124-127 1 0.01% 99.91% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::128-131 3 0.04% 99.95% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::140-143 4 0.05% 100.00% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::total 7460 # Writes before turning the bus around for reads
304system.physmem.totQLat 7660076750 # Total ticks spent queuing
305system.physmem.totMemAccLat 11720633000 # Total ticks spent from burst creation until serviced by the DRAM
306system.physmem.totBusLat 1082815000 # Total ticks spent in databus transfers
307system.physmem.avgQLat 35371.12 # Average queueing delay per DRAM burst
|
250system.physmem.rdPerTurnAround::total 7463 # Reads before turning the bus around for writes 251system.physmem.wrPerTurnAround::samples 7463 # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::mean 19.946134 # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::gmean 18.603737 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::stdev 11.129560 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::16-19 6171 82.69% 82.69% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::20-23 489 6.55% 89.24% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::24-27 84 1.13% 90.37% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::28-31 205 2.75% 93.11% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::32-35 200 2.68% 95.79% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::36-39 17 0.23% 96.02% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::40-43 17 0.23% 96.25% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::44-47 12 0.16% 96.41% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::48-51 25 0.33% 96.74% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::52-55 6 0.08% 96.82% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::56-59 6 0.08% 96.90% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::60-63 3 0.04% 96.94% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::64-67 165 2.21% 99.16% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::68-71 7 0.09% 99.25% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::72-75 6 0.08% 99.33% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::80-83 18 0.24% 99.57% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::84-87 1 0.01% 99.58% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::96-99 7 0.09% 99.71% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::100-103 1 0.01% 99.72% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::112-115 3 0.04% 99.79% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::124-127 1 0.01% 99.81% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::128-131 8 0.11% 99.92% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::136-139 1 0.01% 99.95% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::140-143 3 0.04% 99.99% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::total 7463 # Writes before turning the bus around for reads 287system.physmem.totQLat 7683149500 # Total ticks spent queuing 288system.physmem.totMemAccLat 11745149500 # Total ticks spent from burst creation until serviced by the DRAM 289system.physmem.totBusLat 1083200000 # Total ticks spent in databus transfers 290system.physmem.avgQLat 35465.05 # Average queueing delay per DRAM burst |
291system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
309system.physmem.avgMemAccLat 54121.12 # Average memory access latency per DRAM burst
310system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s
|
292system.physmem.avgMemAccLat 54215.05 # Average memory access latency per DRAM burst 293system.physmem.avgRdBW 4.88 # Average DRAM read bandwidth in MiByte/s |
294system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s 295system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s
|
313system.physmem.avgWrBWSys 3.34 # Average system write bandwidth in MiByte/s
|
296system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s |
297system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 298system.physmem.busUtil 0.06 # Data bus utilization in percentage 299system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 300system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 301system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
|
319system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing
320system.physmem.readRowHits 183124 # Number of row buffer hits during reads
321system.physmem.writeRowHits 89683 # Number of row buffer hits during writes
|
302system.physmem.avgWrQLen 26.48 # Average write queue length when enqueuing 303system.physmem.readRowHits 183194 # Number of row buffer hits during reads 304system.physmem.writeRowHits 89685 # Number of row buffer hits during writes |
305system.physmem.readRowHitRate 84.56 # Row buffer hit rate for reads
|
323system.physmem.writeRowHitRate 60.25 # Row buffer hit rate for writes
324system.physmem.avgGap 7694496.85 # Average gap between requests
|
306system.physmem.writeRowHitRate 60.24 # Row buffer hit rate for writes 307system.physmem.avgGap 7692449.94 # Average gap between requests |
308system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined
|
326system.physmem.memoryStateTime::IDLE 2709761139750 # Time in different power states
327system.physmem.memoryStateTime::REF 94956160000 # Time in different power states
|
309system.physmem.memoryStateTime::IDLE 2709796310750 # Time in different power states 310system.physmem.memoryStateTime::REF 94955640000 # Time in different power states |
311system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
329system.physmem.memoryStateTime::ACT 38946040250 # Time in different power states
|
312system.physmem.memoryStateTime::ACT 38900516750 # Time in different power states |
313system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
331system.physmem.actEnergy::0 358880760 # Energy for activate commands per rank (pJ)
332system.physmem.actEnergy::1 341016480 # Energy for activate commands per rank (pJ)
333system.physmem.preEnergy::0 195817875 # Energy for precharge commands per rank (pJ)
334system.physmem.preEnergy::1 186070500 # Energy for precharge commands per rank (pJ)
335system.physmem.readEnergy::0 862524000 # Energy for read commands per rank (pJ)
336system.physmem.readEnergy::1 826667400 # Energy for read commands per rank (pJ)
337system.physmem.writeEnergy::0 486609120 # Energy for write commands per rank (pJ)
338system.physmem.writeEnergy::1 477763920 # Energy for write commands per rank (pJ)
339system.physmem.refreshEnergy::0 185734248960 # Energy for refresh commands per rank (pJ)
340system.physmem.refreshEnergy::1 185734248960 # Energy for refresh commands per rank (pJ)
341system.physmem.actBackEnergy::0 81966350835 # Energy for active background per rank (pJ)
342system.physmem.actBackEnergy::1 81438405435 # Energy for active background per rank (pJ)
343system.physmem.preBackEnergy::0 1634297688000 # Energy for precharge background per rank (pJ)
344system.physmem.preBackEnergy::1 1634760798000 # Energy for precharge background per rank (pJ)
345system.physmem.totalEnergy::0 1903902119550 # Total energy per rank (pJ)
346system.physmem.totalEnergy::1 1903764970695 # Total energy per rank (pJ)
347system.physmem.averagePower::0 669.524448 # Core power per rank (mW)
348system.physmem.averagePower::1 669.476219 # Core power per rank (mW)
349system.membus.trans_dist::ReadReq 238011 # Transaction distribution
350system.membus.trans_dist::ReadResp 238011 # Transaction distribution
351system.membus.trans_dist::WriteReq 30931 # Transaction distribution
352system.membus.trans_dist::WriteResp 30931 # Transaction distribution
353system.membus.trans_dist::Writeback 112095 # Transaction distribution
354system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
355system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
356system.membus.trans_dist::UpgradeReq 79719 # Transaction distribution
357system.membus.trans_dist::SCUpgradeReq 39980 # Transaction distribution
358system.membus.trans_dist::UpgradeResp 13536 # Transaction distribution
359system.membus.trans_dist::ReadExReq 30379 # Transaction distribution
360system.membus.trans_dist::ReadExResp 13328 # Transaction distribution
361system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes)
362system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
363system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes)
364system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704855 # Packet count per connected master and slave (bytes)
365system.membus.pkt_count_system.l2c.mem_side::total 826435 # Packet count per connected master and slave (bytes)
366system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes)
367system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes)
368system.membus.pkt_count::total 899141 # Packet count per connected master and slave (bytes)
369system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes)
370system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes)
371system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes)
372system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21031980 # Cumulative packet size per connected master and slave (bytes)
373system.membus.pkt_size_system.l2c.mem_side::total 21223190 # Cumulative packet size per connected master and slave (bytes)
374system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
375system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
376system.membus.pkt_size::total 23542486 # Cumulative packet size per connected master and slave (bytes)
377system.membus.snoops 123442 # Total snoops (count)
378system.membus.snoop_fanout::samples 498376 # Request fanout histogram
379system.membus.snoop_fanout::mean 1 # Request fanout histogram
380system.membus.snoop_fanout::stdev 0 # Request fanout histogram
381system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
382system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
383system.membus.snoop_fanout::1 498376 100.00% 100.00% # Request fanout histogram
384system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
385system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
386system.membus.snoop_fanout::min_value 1 # Request fanout histogram
387system.membus.snoop_fanout::max_value 1 # Request fanout histogram
388system.membus.snoop_fanout::total 498376 # Request fanout histogram
389system.membus.reqLayer0.occupancy 87914995 # Layer occupancy (ticks)
390system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
391system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks)
392system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
393system.membus.reqLayer2.occupancy 11673499 # Layer occupancy (ticks)
394system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
395system.membus.reqLayer5.occupancy 1620072999 # Layer occupancy (ticks)
396system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
397system.membus.respLayer2.occupancy 2120142312 # Layer occupancy (ticks)
398system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
399system.membus.respLayer3.occupancy 38549614 # Layer occupancy (ticks)
400system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
401system.cpu_clk_domain.clock 500 # Clock period in ticks
402system.l2c.tags.replacements 151709 # number of replacements
403system.l2c.tags.tagsinuse 64474.290498 # Cycle average of tags in use
404system.l2c.tags.total_refs 529875 # Total number of references to valid blocks.
405system.l2c.tags.sampled_refs 216478 # Sample count of references to valid blocks.
406system.l2c.tags.avg_refs 2.447708 # Average number of references to valid blocks.
407system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
408system.l2c.tags.occ_blocks::writebacks 12364.739343 # Average occupied blocks per requestor
409system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831819 # Average occupied blocks per requestor
410system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030523 # Average occupied blocks per requestor
411system.l2c.tags.occ_blocks::cpu0.inst 3875.049948 # Average occupied blocks per requestor
412system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42732.474457 # Average occupied blocks per requestor
413system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.614781 # Average occupied blocks per requestor
414system.l2c.tags.occ_blocks::cpu1.inst 756.297533 # Average occupied blocks per requestor
415system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4653.252093 # Average occupied blocks per requestor
416system.l2c.tags.occ_percent::writebacks 0.188671 # Average percentage of cache occupancy
417system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy
418system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
419system.l2c.tags.occ_percent::cpu0.inst 0.059129 # Average percentage of cache occupancy
420system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.652046 # Average percentage of cache occupancy
421system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy
422system.l2c.tags.occ_percent::cpu1.inst 0.011540 # Average percentage of cache occupancy
423system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071003 # Average percentage of cache occupancy
424system.l2c.tags.occ_percent::total 0.983800 # Average percentage of cache occupancy
425system.l2c.tags.occ_task_id_blocks::1022 46265 # Occupied blocks per task id
426system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id
427system.l2c.tags.occ_task_id_blocks::1024 18457 # Occupied blocks per task id
428system.l2c.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id
429system.l2c.tags.age_task_id_blocks_1022::3 6570 # Occupied blocks per task id
430system.l2c.tags.age_task_id_blocks_1022::4 39426 # Occupied blocks per task id
431system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id
432system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
433system.l2c.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id
434system.l2c.tags.age_task_id_blocks_1024::3 2643 # Occupied blocks per task id
435system.l2c.tags.age_task_id_blocks_1024::4 15559 # Occupied blocks per task id
436system.l2c.tags.occ_task_id_percent::1022 0.705948 # Percentage of cache occupancy per task id
437system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id
438system.l2c.tags.occ_task_id_percent::1024 0.281631 # Percentage of cache occupancy per task id
439system.l2c.tags.tag_accesses 6643854 # Number of tag accesses
440system.l2c.tags.data_accesses 6643854 # Number of data accesses
441system.l2c.ReadReq_hits::cpu0.dtb.walker 549 # number of ReadReq hits
442system.l2c.ReadReq_hits::cpu0.itb.walker 114 # number of ReadReq hits
443system.l2c.ReadReq_hits::cpu0.inst 36725 # number of ReadReq hits
444system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207902 # number of ReadReq hits
445system.l2c.ReadReq_hits::cpu1.dtb.walker 116 # number of ReadReq hits
446system.l2c.ReadReq_hits::cpu1.itb.walker 47 # number of ReadReq hits
447system.l2c.ReadReq_hits::cpu1.inst 11423 # number of ReadReq hits
448system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45111 # number of ReadReq hits
449system.l2c.ReadReq_hits::total 301987 # number of ReadReq hits
450system.l2c.Writeback_hits::writebacks 252491 # number of Writeback hits
451system.l2c.Writeback_hits::total 252491 # number of Writeback hits
452system.l2c.UpgradeReq_hits::cpu0.inst 11970 # number of UpgradeReq hits
453system.l2c.UpgradeReq_hits::cpu1.inst 853 # number of UpgradeReq hits
454system.l2c.UpgradeReq_hits::total 12823 # number of UpgradeReq hits
455system.l2c.SCUpgradeReq_hits::cpu0.inst 185 # number of SCUpgradeReq hits
456system.l2c.SCUpgradeReq_hits::cpu1.inst 180 # number of SCUpgradeReq hits
457system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits
458system.l2c.ReadExReq_hits::cpu0.inst 3516 # number of ReadExReq hits
459system.l2c.ReadExReq_hits::cpu1.inst 1122 # number of ReadExReq hits
460system.l2c.ReadExReq_hits::total 4638 # number of ReadExReq hits
461system.l2c.demand_hits::cpu0.dtb.walker 549 # number of demand (read+write) hits
462system.l2c.demand_hits::cpu0.itb.walker 114 # number of demand (read+write) hits
463system.l2c.demand_hits::cpu0.inst 40241 # number of demand (read+write) hits
464system.l2c.demand_hits::cpu0.l2cache.prefetcher 207902 # number of demand (read+write) hits
465system.l2c.demand_hits::cpu1.dtb.walker 116 # number of demand (read+write) hits
466system.l2c.demand_hits::cpu1.itb.walker 47 # number of demand (read+write) hits
467system.l2c.demand_hits::cpu1.inst 12545 # number of demand (read+write) hits
468system.l2c.demand_hits::cpu1.l2cache.prefetcher 45111 # number of demand (read+write) hits
469system.l2c.demand_hits::total 306625 # number of demand (read+write) hits
470system.l2c.overall_hits::cpu0.dtb.walker 549 # number of overall hits
471system.l2c.overall_hits::cpu0.itb.walker 114 # number of overall hits
472system.l2c.overall_hits::cpu0.inst 40241 # number of overall hits
473system.l2c.overall_hits::cpu0.l2cache.prefetcher 207902 # number of overall hits
474system.l2c.overall_hits::cpu1.dtb.walker 116 # number of overall hits
475system.l2c.overall_hits::cpu1.itb.walker 47 # number of overall hits
476system.l2c.overall_hits::cpu1.inst 12545 # number of overall hits
477system.l2c.overall_hits::cpu1.l2cache.prefetcher 45111 # number of overall hits
478system.l2c.overall_hits::total 306625 # number of overall hits
479system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses
480system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
481system.l2c.ReadReq_misses::cpu0.inst 11298 # number of ReadReq misses
482system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq misses
483system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses
484system.l2c.ReadReq_misses::cpu1.inst 1836 # number of ReadReq misses
485system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18199 # number of ReadReq misses
486system.l2c.ReadReq_misses::total 199730 # number of ReadReq misses
487system.l2c.UpgradeReq_misses::cpu0.inst 9030 # number of UpgradeReq misses
488system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses
489system.l2c.UpgradeReq_misses::total 11695 # number of UpgradeReq misses
490system.l2c.SCUpgradeReq_misses::cpu0.inst 470 # number of SCUpgradeReq misses
491system.l2c.SCUpgradeReq_misses::cpu1.inst 1259 # number of SCUpgradeReq misses
492system.l2c.SCUpgradeReq_misses::total 1729 # number of SCUpgradeReq misses
493system.l2c.ReadExReq_misses::cpu0.inst 7024 # number of ReadExReq misses
494system.l2c.ReadExReq_misses::cpu1.inst 6416 # number of ReadExReq misses
495system.l2c.ReadExReq_misses::total 13440 # number of ReadExReq misses
496system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses
497system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
498system.l2c.demand_misses::cpu0.inst 18322 # number of demand (read+write) misses
499system.l2c.demand_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) misses
500system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses
501system.l2c.demand_misses::cpu1.inst 8252 # number of demand (read+write) misses
502system.l2c.demand_misses::cpu1.l2cache.prefetcher 18199 # number of demand (read+write) misses
503system.l2c.demand_misses::total 213170 # number of demand (read+write) misses
504system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses
505system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
506system.l2c.overall_misses::cpu0.inst 18322 # number of overall misses
507system.l2c.overall_misses::cpu0.l2cache.prefetcher 168230 # number of overall misses
508system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses
509system.l2c.overall_misses::cpu1.inst 8252 # number of overall misses
510system.l2c.overall_misses::cpu1.l2cache.prefetcher 18199 # number of overall misses
511system.l2c.overall_misses::total 213170 # number of overall misses
512system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles
513system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles
514system.l2c.ReadReq_miss_latency::cpu0.inst 956701998 # number of ReadReq miss cycles
515system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of ReadReq miss cycles
516system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1343500 # number of ReadReq miss cycles
517system.l2c.ReadReq_miss_latency::cpu1.inst 150016000 # number of ReadReq miss cycles
518system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of ReadReq miss cycles
519system.l2c.ReadReq_miss_latency::total 21240863385 # number of ReadReq miss cycles
520system.l2c.UpgradeReq_miss_latency::cpu0.inst 10890561 # number of UpgradeReq miss cycles
521system.l2c.UpgradeReq_miss_latency::cpu1.inst 2732384 # number of UpgradeReq miss cycles
522system.l2c.UpgradeReq_miss_latency::total 13622945 # number of UpgradeReq miss cycles
523system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1227450 # number of SCUpgradeReq miss cycles
524system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 930960 # number of SCUpgradeReq miss cycles
525system.l2c.SCUpgradeReq_miss_latency::total 2158410 # number of SCUpgradeReq miss cycles
526system.l2c.ReadExReq_miss_latency::cpu0.inst 595061904 # number of ReadExReq miss cycles
527system.l2c.ReadExReq_miss_latency::cpu1.inst 477250480 # number of ReadExReq miss cycles
528system.l2c.ReadExReq_miss_latency::total 1072312384 # number of ReadExReq miss cycles
529system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles
530system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles
531system.l2c.demand_miss_latency::cpu0.inst 1551763902 # number of demand (read+write) miss cycles
532system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of demand (read+write) miss cycles
533system.l2c.demand_miss_latency::cpu1.dtb.walker 1343500 # number of demand (read+write) miss cycles
534system.l2c.demand_miss_latency::cpu1.inst 627266480 # number of demand (read+write) miss cycles
535system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of demand (read+write) miss cycles
536system.l2c.demand_miss_latency::total 22313175769 # number of demand (read+write) miss cycles
537system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles
538system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles
539system.l2c.overall_miss_latency::cpu0.inst 1551763902 # number of overall miss cycles
540system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of overall miss cycles
541system.l2c.overall_miss_latency::cpu1.dtb.walker 1343500 # number of overall miss cycles
542system.l2c.overall_miss_latency::cpu1.inst 627266480 # number of overall miss cycles
543system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of overall miss cycles
544system.l2c.overall_miss_latency::total 22313175769 # number of overall miss cycles
545system.l2c.ReadReq_accesses::cpu0.dtb.walker 700 # number of ReadReq accesses(hits+misses)
546system.l2c.ReadReq_accesses::cpu0.itb.walker 115 # number of ReadReq accesses(hits+misses)
547system.l2c.ReadReq_accesses::cpu0.inst 48023 # number of ReadReq accesses(hits+misses)
548system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 376132 # number of ReadReq accesses(hits+misses)
549system.l2c.ReadReq_accesses::cpu1.dtb.walker 131 # number of ReadReq accesses(hits+misses)
550system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses)
551system.l2c.ReadReq_accesses::cpu1.inst 13259 # number of ReadReq accesses(hits+misses)
552system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63310 # number of ReadReq accesses(hits+misses)
553system.l2c.ReadReq_accesses::total 501717 # number of ReadReq accesses(hits+misses)
554system.l2c.Writeback_accesses::writebacks 252491 # number of Writeback accesses(hits+misses)
555system.l2c.Writeback_accesses::total 252491 # number of Writeback accesses(hits+misses)
556system.l2c.UpgradeReq_accesses::cpu0.inst 21000 # number of UpgradeReq accesses(hits+misses)
557system.l2c.UpgradeReq_accesses::cpu1.inst 3518 # number of UpgradeReq accesses(hits+misses)
558system.l2c.UpgradeReq_accesses::total 24518 # number of UpgradeReq accesses(hits+misses)
559system.l2c.SCUpgradeReq_accesses::cpu0.inst 655 # number of SCUpgradeReq accesses(hits+misses)
560system.l2c.SCUpgradeReq_accesses::cpu1.inst 1439 # number of SCUpgradeReq accesses(hits+misses)
561system.l2c.SCUpgradeReq_accesses::total 2094 # number of SCUpgradeReq accesses(hits+misses)
562system.l2c.ReadExReq_accesses::cpu0.inst 10540 # number of ReadExReq accesses(hits+misses)
563system.l2c.ReadExReq_accesses::cpu1.inst 7538 # number of ReadExReq accesses(hits+misses)
564system.l2c.ReadExReq_accesses::total 18078 # number of ReadExReq accesses(hits+misses)
565system.l2c.demand_accesses::cpu0.dtb.walker 700 # number of demand (read+write) accesses
566system.l2c.demand_accesses::cpu0.itb.walker 115 # number of demand (read+write) accesses
567system.l2c.demand_accesses::cpu0.inst 58563 # number of demand (read+write) accesses
568system.l2c.demand_accesses::cpu0.l2cache.prefetcher 376132 # number of demand (read+write) accesses
569system.l2c.demand_accesses::cpu1.dtb.walker 131 # number of demand (read+write) accesses
570system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses
571system.l2c.demand_accesses::cpu1.inst 20797 # number of demand (read+write) accesses
572system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63310 # number of demand (read+write) accesses
573system.l2c.demand_accesses::total 519795 # number of demand (read+write) accesses
574system.l2c.overall_accesses::cpu0.dtb.walker 700 # number of overall (read+write) accesses
575system.l2c.overall_accesses::cpu0.itb.walker 115 # number of overall (read+write) accesses
576system.l2c.overall_accesses::cpu0.inst 58563 # number of overall (read+write) accesses
577system.l2c.overall_accesses::cpu0.l2cache.prefetcher 376132 # number of overall (read+write) accesses
578system.l2c.overall_accesses::cpu1.dtb.walker 131 # number of overall (read+write) accesses
579system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses
580system.l2c.overall_accesses::cpu1.inst 20797 # number of overall (read+write) accesses
581system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63310 # number of overall (read+write) accesses
582system.l2c.overall_accesses::total 519795 # number of overall (read+write) accesses
583system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for ReadReq accesses
584system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008696 # miss rate for ReadReq accesses
585system.l2c.ReadReq_miss_rate::cpu0.inst 0.235262 # miss rate for ReadReq accesses
586system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for ReadReq accesses
587system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for ReadReq accesses
588system.l2c.ReadReq_miss_rate::cpu1.inst 0.138472 # miss rate for ReadReq accesses
589system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for ReadReq accesses
590system.l2c.ReadReq_miss_rate::total 0.398093 # miss rate for ReadReq accesses
591system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430000 # miss rate for UpgradeReq accesses
592system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.757533 # miss rate for UpgradeReq accesses
593system.l2c.UpgradeReq_miss_rate::total 0.476996 # miss rate for UpgradeReq accesses
594system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.717557 # miss rate for SCUpgradeReq accesses
595system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.874913 # miss rate for SCUpgradeReq accesses
596system.l2c.SCUpgradeReq_miss_rate::total 0.825692 # miss rate for SCUpgradeReq accesses
597system.l2c.ReadExReq_miss_rate::cpu0.inst 0.666414 # miss rate for ReadExReq accesses
598system.l2c.ReadExReq_miss_rate::cpu1.inst 0.851154 # miss rate for ReadExReq accesses
599system.l2c.ReadExReq_miss_rate::total 0.743445 # miss rate for ReadExReq accesses
600system.l2c.demand_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for demand accesses
601system.l2c.demand_miss_rate::cpu0.itb.walker 0.008696 # miss rate for demand accesses
602system.l2c.demand_miss_rate::cpu0.inst 0.312860 # miss rate for demand accesses
603system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for demand accesses
604system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for demand accesses
605system.l2c.demand_miss_rate::cpu1.inst 0.396788 # miss rate for demand accesses
606system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for demand accesses
607system.l2c.demand_miss_rate::total 0.410104 # miss rate for demand accesses
608system.l2c.overall_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for overall accesses
609system.l2c.overall_miss_rate::cpu0.itb.walker 0.008696 # miss rate for overall accesses
610system.l2c.overall_miss_rate::cpu0.inst 0.312860 # miss rate for overall accesses
611system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for overall accesses
612system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for overall accesses
613system.l2c.overall_miss_rate::cpu1.inst 0.396788 # miss rate for overall accesses
614system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for overall accesses
615system.l2c.overall_miss_rate::total 0.410104 # miss rate for overall accesses
616system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency
617system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency
618system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84678.881041 # average ReadReq miss latency
619system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average ReadReq miss latency
620system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average ReadReq miss latency
621system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81708.061002 # average ReadReq miss latency
622system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average ReadReq miss latency
623system.l2c.ReadReq_avg_miss_latency::total 106347.886572 # average ReadReq miss latency
624system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1206.042193 # average UpgradeReq miss latency
625system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1025.284803 # average UpgradeReq miss latency
626system.l2c.UpgradeReq_avg_miss_latency::total 1164.852074 # average UpgradeReq miss latency
627system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2611.595745 # average SCUpgradeReq miss latency
628system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 739.444003 # average SCUpgradeReq miss latency
629system.l2c.SCUpgradeReq_avg_miss_latency::total 1248.357432 # average SCUpgradeReq miss latency
630system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84718.380410 # average ReadExReq miss latency
631system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74384.426434 # average ReadExReq miss latency
632system.l2c.ReadExReq_avg_miss_latency::total 79785.147619 # average ReadExReq miss latency
633system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency
634system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
635system.l2c.demand_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency
636system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency
637system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency
638system.l2c.demand_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency
639system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency
640system.l2c.demand_avg_miss_latency::total 104673.151799 # average overall miss latency
641system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency
642system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
643system.l2c.overall_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency
644system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency
645system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency
646system.l2c.overall_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency
647system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency
648system.l2c.overall_avg_miss_latency::total 104673.151799 # average overall miss latency
649system.l2c.blocked_cycles::no_mshrs 758 # number of cycles access was blocked
650system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
651system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked
652system.l2c.blocked::no_targets 0 # number of cycles access was blocked
653system.l2c.avg_blocked_cycles::no_mshrs 36.095238 # average number of cycles each access was blocked
654system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
655system.l2c.fast_writes 0 # number of fast writes performed
656system.l2c.cache_copies 0 # number of cache copies performed
657system.l2c.writebacks::writebacks 112095 # number of writebacks
658system.l2c.writebacks::total 112095 # number of writebacks
659system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits
660system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
661system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
662system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
663system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits
664system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
665system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses
666system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses
667system.l2c.ReadReq_mshr_misses::cpu0.inst 11298 # number of ReadReq MSHR misses
668system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq MSHR misses
669system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses
670system.l2c.ReadReq_mshr_misses::cpu1.inst 1836 # number of ReadReq MSHR misses
671system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of ReadReq MSHR misses
672system.l2c.ReadReq_mshr_misses::total 199729 # number of ReadReq MSHR misses
673system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9030 # number of UpgradeReq MSHR misses
674system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses
675system.l2c.UpgradeReq_mshr_misses::total 11695 # number of UpgradeReq MSHR misses
676system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 470 # number of SCUpgradeReq MSHR misses
677system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1259 # number of SCUpgradeReq MSHR misses
678system.l2c.SCUpgradeReq_mshr_misses::total 1729 # number of SCUpgradeReq MSHR misses
679system.l2c.ReadExReq_mshr_misses::cpu0.inst 7024 # number of ReadExReq MSHR misses
680system.l2c.ReadExReq_mshr_misses::cpu1.inst 6416 # number of ReadExReq MSHR misses
681system.l2c.ReadExReq_mshr_misses::total 13440 # number of ReadExReq MSHR misses
682system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses
683system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
684system.l2c.demand_mshr_misses::cpu0.inst 18322 # number of demand (read+write) MSHR misses
685system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) MSHR misses
686system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses
687system.l2c.demand_mshr_misses::cpu1.inst 8252 # number of demand (read+write) MSHR misses
688system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of demand (read+write) MSHR misses
689system.l2c.demand_mshr_misses::total 213169 # number of demand (read+write) MSHR misses
690system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses
691system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
692system.l2c.overall_mshr_misses::cpu0.inst 18322 # number of overall MSHR misses
693system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of overall MSHR misses
694system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses
695system.l2c.overall_mshr_misses::cpu1.inst 8252 # number of overall MSHR misses
696system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of overall MSHR misses
697system.l2c.overall_mshr_misses::total 213169 # number of overall MSHR misses
698system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of ReadReq MSHR miss cycles
699system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles
700system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 816212498 # number of ReadReq MSHR miss cycles
701system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of ReadReq MSHR miss cycles
702system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of ReadReq MSHR miss cycles
703system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 127225500 # number of ReadReq MSHR miss cycles
704system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of ReadReq MSHR miss cycles
705system.l2c.ReadReq_mshr_miss_latency::total 18781676635 # number of ReadReq MSHR miss cycles
706system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91207456 # number of UpgradeReq MSHR miss cycles
707system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26838142 # number of UpgradeReq MSHR miss cycles
708system.l2c.UpgradeReq_mshr_miss_latency::total 118045598 # number of UpgradeReq MSHR miss cycles
709system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4758966 # number of SCUpgradeReq MSHR miss cycles
710system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12646753 # number of SCUpgradeReq MSHR miss cycles
711system.l2c.SCUpgradeReq_mshr_miss_latency::total 17405719 # number of SCUpgradeReq MSHR miss cycles
712system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 507430588 # number of ReadExReq MSHR miss cycles
713system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 396239520 # number of ReadExReq MSHR miss cycles
714system.l2c.ReadExReq_mshr_miss_latency::total 903670108 # number of ReadExReq MSHR miss cycles
715system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles
716system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
717system.l2c.demand_mshr_miss_latency::cpu0.inst 1323643086 # number of demand (read+write) MSHR miss cycles
718system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of demand (read+write) MSHR miss cycles
719system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of demand (read+write) MSHR miss cycles
720system.l2c.demand_mshr_miss_latency::cpu1.inst 523465020 # number of demand (read+write) MSHR miss cycles
721system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of demand (read+write) MSHR miss cycles
722system.l2c.demand_mshr_miss_latency::total 19685346743 # number of demand (read+write) MSHR miss cycles
723system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles
724system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles
725system.l2c.overall_mshr_miss_latency::cpu0.inst 1323643086 # number of overall MSHR miss cycles
726system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of overall MSHR miss cycles
727system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of overall MSHR miss cycles
728system.l2c.overall_mshr_miss_latency::cpu1.inst 523465020 # number of overall MSHR miss cycles
729system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of overall MSHR miss cycles
730system.l2c.overall_mshr_miss_latency::total 19685346743 # number of overall MSHR miss cycles
731system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518668247 # number of ReadReq MSHR uncacheable cycles
732system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263087751 # number of ReadReq MSHR uncacheable cycles
733system.l2c.ReadReq_mshr_uncacheable_latency::total 5781755998 # number of ReadReq MSHR uncacheable cycles
734system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4095979500 # number of WriteReq MSHR uncacheable cycles
735system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150492500 # number of WriteReq MSHR uncacheable cycles
736system.l2c.WriteReq_mshr_uncacheable_latency::total 4246472000 # number of WriteReq MSHR uncacheable cycles
737system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614647747 # number of overall MSHR uncacheable cycles
738system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413580251 # number of overall MSHR uncacheable cycles
739system.l2c.overall_mshr_uncacheable_latency::total 10028227998 # number of overall MSHR uncacheable cycles
740system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for ReadReq accesses
741system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for ReadReq accesses
742system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235262 # mshr miss rate for ReadReq accesses
743system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for ReadReq accesses
744system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for ReadReq accesses
745system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138472 # mshr miss rate for ReadReq accesses
746system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for ReadReq accesses
747system.l2c.ReadReq_mshr_miss_rate::total 0.398091 # mshr miss rate for ReadReq accesses
748system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430000 # mshr miss rate for UpgradeReq accesses
749system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.757533 # mshr miss rate for UpgradeReq accesses
750system.l2c.UpgradeReq_mshr_miss_rate::total 0.476996 # mshr miss rate for UpgradeReq accesses
751system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.717557 # mshr miss rate for SCUpgradeReq accesses
752system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.874913 # mshr miss rate for SCUpgradeReq accesses
753system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.825692 # mshr miss rate for SCUpgradeReq accesses
754system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.666414 # mshr miss rate for ReadExReq accesses
755system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.851154 # mshr miss rate for ReadExReq accesses
756system.l2c.ReadExReq_mshr_miss_rate::total 0.743445 # mshr miss rate for ReadExReq accesses
757system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for demand accesses
758system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for demand accesses
759system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for demand accesses
760system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for demand accesses
761system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for demand accesses
762system.l2c.demand_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for demand accesses
763system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for demand accesses
764system.l2c.demand_mshr_miss_rate::total 0.410102 # mshr miss rate for demand accesses
765system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for overall accesses
766system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for overall accesses
767system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for overall accesses
768system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for overall accesses
769system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for overall accesses
770system.l2c.overall_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for overall accesses
771system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for overall accesses
772system.l2c.overall_mshr_miss_rate::total 0.410102 # mshr miss rate for overall accesses
773system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency
774system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
775system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72243.981059 # average ReadReq mshr miss latency
776system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average ReadReq mshr miss latency
777system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average ReadReq mshr miss latency
778system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69294.934641 # average ReadReq mshr miss latency
779system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average ReadReq mshr miss latency
780system.l2c.ReadReq_avg_mshr_miss_latency::total 94035.801686 # average ReadReq mshr miss latency
781system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10100.493466 # average UpgradeReq mshr miss latency
782system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.597373 # average UpgradeReq mshr miss latency
783system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.680889 # average UpgradeReq mshr miss latency
784system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10125.459574 # average SCUpgradeReq mshr miss latency
785system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10045.077840 # average SCUpgradeReq mshr miss latency
786system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10066.928282 # average SCUpgradeReq mshr miss latency
787system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72242.395786 # average ReadExReq mshr miss latency
788system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61758.029925 # average ReadExReq mshr miss latency
789system.l2c.ReadExReq_avg_mshr_miss_latency::total 67237.359226 # average ReadExReq mshr miss latency
790system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency
791system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
792system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency
793system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency
794system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency
795system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency
796system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency
797system.l2c.demand_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency
798system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency
799system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
800system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency
801system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency
802system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency
803system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency
804system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency
805system.l2c.overall_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency
806system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
807system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
808system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
809system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
810system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
811system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
812system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
813system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
814system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
815system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
816system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
817system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
818system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
819system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
820system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
821system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
822system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
823system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
824system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
825system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
826system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
827system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
828system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
829system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
830system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
831system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
832system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
833system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
834system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
835system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
836system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
837system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
838system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
839system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
840system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
841system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
842system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
843system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
844system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
845system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
846system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
314system.physmem.actEnergy::0 358956360 # Energy for activate commands per rank (pJ) 315system.physmem.actEnergy::1 341235720 # Energy for activate commands per rank (pJ) 316system.physmem.preEnergy::0 195859125 # Energy for precharge commands per rank (pJ) 317system.physmem.preEnergy::1 186190125 # Energy for precharge commands per rank (pJ) 318system.physmem.readEnergy::0 862929600 # Energy for read commands per rank (pJ) 319system.physmem.readEnergy::1 826854600 # Energy for read commands per rank (pJ) 320system.physmem.writeEnergy::0 486680400 # Energy for write commands per rank (pJ) 321system.physmem.writeEnergy::1 477919440 # Energy for write commands per rank (pJ) 322system.physmem.refreshEnergy::0 185733231840 # Energy for refresh commands per rank (pJ) 323system.physmem.refreshEnergy::1 185733231840 # Energy for refresh commands per rank (pJ) 324system.physmem.actBackEnergy::0 81937929780 # Energy for active background per rank (pJ) 325system.physmem.actBackEnergy::1 81435296655 # Energy for active background per rank (pJ) 326system.physmem.preBackEnergy::0 1634313275250 # Energy for precharge background per rank (pJ) 327system.physmem.preBackEnergy::1 1634754181500 # Energy for precharge background per rank (pJ) 328system.physmem.totalEnergy::0 1903888862355 # Total energy per rank (pJ) 329system.physmem.totalEnergy::1 1903754909880 # Total energy per rank (pJ) 330system.physmem.averagePower::0 669.523453 # Core power per rank (mW) 331system.physmem.averagePower::1 669.476347 # Core power per rank (mW) 332system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 333system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 334system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 335system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 336system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 337system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 338system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 339system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 340system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory 341system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) 345system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) 346system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) 347system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) 348system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 349system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) |
350system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 351system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 352system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 353system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 354system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 355system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
853system.toL2Bus.trans_dist::ReadReq 668242 # Transaction distribution
854system.toL2Bus.trans_dist::ReadResp 668227 # Transaction distribution
855system.toL2Bus.trans_dist::WriteReq 30931 # Transaction distribution
856system.toL2Bus.trans_dist::WriteResp 30931 # Transaction distribution
857system.toL2Bus.trans_dist::Writeback 252491 # Transaction distribution
858system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
859system.toL2Bus.trans_dist::UpgradeReq 92430 # Transaction distribution
860system.toL2Bus.trans_dist::SCUpgradeReq 40345 # Transaction distribution
861system.toL2Bus.trans_dist::UpgradeResp 132775 # Transaction distribution
862system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
863system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
864system.toL2Bus.trans_dist::ReadExReq 38935 # Transaction distribution
865system.toL2Bus.trans_dist::ReadExResp 38935 # Transaction distribution
866system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370727 # Packet count per connected master and slave (bytes)
867system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368021 # Packet count per connected master and slave (bytes)
868system.toL2Bus.pkt_count::total 1738748 # Packet count per connected master and slave (bytes)
869system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41983735 # Cumulative packet size per connected master and slave (bytes)
870system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7870623 # Cumulative packet size per connected master and slave (bytes)
871system.toL2Bus.pkt_size::total 49854358 # Cumulative packet size per connected master and slave (bytes)
872system.toL2Bus.snoops 291977 # Total snoops (count)
873system.toL2Bus.snoop_fanout::samples 1090667 # Request fanout histogram
874system.toL2Bus.snoop_fanout::mean 1.033442 # Request fanout histogram
875system.toL2Bus.snoop_fanout::stdev 0.179788 # Request fanout histogram
876system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
877system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
878system.toL2Bus.snoop_fanout::1 1054193 96.66% 96.66% # Request fanout histogram
879system.toL2Bus.snoop_fanout::2 36474 3.34% 100.00% # Request fanout histogram
880system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
881system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
882system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
883system.toL2Bus.snoop_fanout::total 1090667 # Request fanout histogram
884system.toL2Bus.reqLayer0.occupancy 1589069612 # Layer occupancy (ticks)
885system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
886system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks)
887system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
888system.toL2Bus.respLayer0.occupancy 2362873368 # Layer occupancy (ticks)
889system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
890system.toL2Bus.respLayer1.occupancy 802585372 # Layer occupancy (ticks)
891system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
892system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
893system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
894system.iobus.trans_dist::WriteReq 59405 # Transaction distribution
895system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
896system.iobus.trans_dist::WriteInvalidateReq 35 # Transaction distribution
897system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
898system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
899system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
900system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
901system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
902system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
903system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
904system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
905system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
906system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
907system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
908system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
909system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
910system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
911system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
912system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
913system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
914system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
915system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
916system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
917system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
918system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
919system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
920system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
921system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes)
922system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
923system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
924system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
925system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
926system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
927system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
928system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
929system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
930system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
931system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
932system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
933system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
934system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
935system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
936system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
937system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
938system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
939system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
940system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
941system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
942system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
943system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
944system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
945system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
946system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes)
947system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
948system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
949system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
950system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
951system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
952system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
953system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
954system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
955system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
956system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
957system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
958system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
959system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
960system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
961system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
962system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
963system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
964system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
965system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
966system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
967system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
968system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
969system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
970system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
971system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
972system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
973system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
974system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
975system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
976system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
977system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
978system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
979system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
980system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
981system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
982system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
983system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
984system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
985system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
986system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
987system.iobus.reqLayer27.occupancy 326655076 # Layer occupancy (ticks)
988system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
989system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
990system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
991system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
992system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
993system.iobus.respLayer3.occupancy 36825386 # Layer occupancy (ticks)
994system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
995system.cpu0.branchPred.lookups 34893743 # Number of BP lookups
996system.cpu0.branchPred.condPredicted 17129146 # Number of conditional branches predicted
997system.cpu0.branchPred.condIncorrect 1674704 # Number of conditional branches incorrect
998system.cpu0.branchPred.BTBLookups 20005904 # Number of BTB lookups
999system.cpu0.branchPred.BTBHits 14465623 # Number of BTB hits
|
356system.cpu0.branchPred.lookups 34892527 # Number of BP lookups 357system.cpu0.branchPred.condPredicted 17126488 # Number of conditional branches predicted 358system.cpu0.branchPred.condIncorrect 1674515 # Number of conditional branches incorrect 359system.cpu0.branchPred.BTBLookups 20008950 # Number of BTB lookups 360system.cpu0.branchPred.BTBHits 14462185 # Number of BTB hits |
361system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
1001system.cpu0.branchPred.BTBHitPct 72.306770 # BTB Hit Percentage
1002system.cpu0.branchPred.usedRAS 10813555 # Number of times the RAS was used to get a target.
1003system.cpu0.branchPred.RASInCorrect 822515 # Number of incorrect RAS predictions.
|
362system.cpu0.branchPred.BTBHitPct 72.278580 # BTB Hit Percentage 363system.cpu0.branchPred.usedRAS 10813099 # Number of times the RAS was used to get a target. 364system.cpu0.branchPred.RASInCorrect 822816 # Number of incorrect RAS predictions. 365system.cpu_clk_domain.clock 500 # Clock period in ticks |
366system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 367system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 368system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 369system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 370system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 371system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 372system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 373system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 374system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 375system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 376system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 377system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 378system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 379system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 380system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 381system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 382system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 383system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 384system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 385system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 386system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 387system.cpu0.dtb.inst_hits 0 # ITB inst hits 388system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
1027system.cpu0.dtb.read_hits 23970791 # DTB read hits
1028system.cpu0.dtb.read_misses 62431 # DTB read misses
1029system.cpu0.dtb.write_hits 17948475 # DTB write hits
1030system.cpu0.dtb.write_misses 6765 # DTB write misses
|
389system.cpu0.dtb.read_hits 23969265 # DTB read hits 390system.cpu0.dtb.read_misses 62663 # DTB read misses 391system.cpu0.dtb.write_hits 17948332 # DTB write hits 392system.cpu0.dtb.write_misses 6711 # DTB write misses |
393system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 394system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 395system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 396system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
1035system.cpu0.dtb.flush_entries 3473 # Number of entries that have been flushed from TLB
1036system.cpu0.dtb.align_faults 1381 # Number of TLB faults due to alignment restrictions
1037system.cpu0.dtb.prefetch_faults 1976 # Number of TLB faults due to prefetch
|
397system.cpu0.dtb.flush_entries 3475 # Number of entries that have been flushed from TLB 398system.cpu0.dtb.align_faults 1396 # Number of TLB faults due to alignment restrictions 399system.cpu0.dtb.prefetch_faults 1982 # Number of TLB faults due to prefetch |
400system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
1039system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
1040system.cpu0.dtb.read_accesses 24033222 # DTB read accesses
1041system.cpu0.dtb.write_accesses 17955240 # DTB write accesses
|
401system.cpu0.dtb.perms_faults 568 # Number of TLB faults due to permissions restrictions 402system.cpu0.dtb.read_accesses 24031928 # DTB read accesses 403system.cpu0.dtb.write_accesses 17955043 # DTB write accesses |
404system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
1043system.cpu0.dtb.hits 41919266 # DTB hits
1044system.cpu0.dtb.misses 69196 # DTB misses
1045system.cpu0.dtb.accesses 41988462 # DTB accesses
|
405system.cpu0.dtb.hits 41917597 # DTB hits 406system.cpu0.dtb.misses 69374 # DTB misses 407system.cpu0.dtb.accesses 41986971 # DTB accesses |
408system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 409system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 410system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 411system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 412system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 413system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 414system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 415system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 416system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 417system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 418system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 419system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 420system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 421system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 422system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 423system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 424system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 425system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 426system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 427system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 428system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
1067system.cpu0.itb.inst_hits 70366530 # ITB inst hits
1068system.cpu0.itb.inst_misses 3846 # ITB inst misses
|
429system.cpu0.itb.inst_hits 70358748 # ITB inst hits 430system.cpu0.itb.inst_misses 3854 # ITB inst misses |
431system.cpu0.itb.read_hits 0 # DTB read hits 432system.cpu0.itb.read_misses 0 # DTB read misses 433system.cpu0.itb.write_hits 0 # DTB write hits 434system.cpu0.itb.write_misses 0 # DTB write misses 435system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 436system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 437system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 438system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 439system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB 440system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 441system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 442system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
1081system.cpu0.itb.perms_faults 7369 # Number of TLB faults due to permissions restrictions
|
443system.cpu0.itb.perms_faults 7388 # Number of TLB faults due to permissions restrictions |
444system.cpu0.itb.read_accesses 0 # DTB read accesses 445system.cpu0.itb.write_accesses 0 # DTB write accesses
|
1084system.cpu0.itb.inst_accesses 70370376 # ITB inst accesses
1085system.cpu0.itb.hits 70366530 # DTB hits
1086system.cpu0.itb.misses 3846 # DTB misses
1087system.cpu0.itb.accesses 70370376 # DTB accesses
1088system.cpu0.numCycles 229133691 # number of cpu cycles simulated
|
446system.cpu0.itb.inst_accesses 70362602 # ITB inst accesses 447system.cpu0.itb.hits 70358748 # DTB hits 448system.cpu0.itb.misses 3854 # DTB misses 449system.cpu0.itb.accesses 70362602 # DTB accesses 450system.cpu0.numCycles 229119066 # number of cpu cycles simulated |
451system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 452system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
1091system.cpu0.committedInsts 109191897 # Number of instructions committed
1092system.cpu0.committedOps 132018821 # Number of ops (including micro ops) committed
1093system.cpu0.discardedOps 8795011 # Number of ops (including micro ops) which were discarded before commit
1094system.cpu0.numFetchSuspends 1826 # Number of times Execute suspended instruction fetching
1095system.cpu0.quiesceCycles 5458210303 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1096system.cpu0.cpi 2.098450 # CPI: cycles per instruction
1097system.cpu0.ipc 0.476542 # IPC: instructions per cycle
|
453system.cpu0.committedInsts 109189984 # Number of instructions committed 454system.cpu0.committedOps 132016369 # Number of ops (including micro ops) committed 455system.cpu0.discardedOps 8791665 # Number of ops (including micro ops) which were discarded before commit 456system.cpu0.numFetchSuspends 1828 # Number of times Execute suspended instruction fetching 457system.cpu0.quiesceCycles 5458204948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 458system.cpu0.cpi 2.098352 # CPI: cycles per instruction 459system.cpu0.ipc 0.476564 # IPC: instructions per cycle |
460system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
1099system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed
1100system.cpu0.tickCycles 193242697 # Number of cycles that the object actually ticked
1101system.cpu0.idleCycles 35890994 # Total number of cycles that the object has spent stopped
1102system.cpu0.icache.tags.replacements 1983122 # number of replacements
1103system.cpu0.icache.tags.tagsinuse 511.796419 # Cycle average of tags in use
1104system.cpu0.icache.tags.total_refs 68375163 # Total number of references to valid blocks.
1105system.cpu0.icache.tags.sampled_refs 1983634 # Sample count of references to valid blocks.
1106system.cpu0.icache.tags.avg_refs 34.469647 # Average number of references to valid blocks.
|
461system.cpu0.kern.inst.quiesce 1830 # number of quiesce instructions executed 462system.cpu0.tickCycles 193229301 # Number of cycles that the object actually ticked 463system.cpu0.idleCycles 35889765 # Total number of cycles that the object has spent stopped 464system.cpu0.dcache.tags.replacements 714801 # number of replacements 465system.cpu0.dcache.tags.tagsinuse 493.827802 # Cycle average of tags in use 466system.cpu0.dcache.tags.total_refs 40473769 # Total number of references to valid blocks. 467system.cpu0.dcache.tags.sampled_refs 715313 # Sample count of references to valid blocks. 468system.cpu0.dcache.tags.avg_refs 56.581901 # Average number of references to valid blocks. 469system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit. 470system.cpu0.dcache.tags.occ_blocks::cpu0.inst 493.827802 # Average occupied blocks per requestor 471system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.964507 # Average percentage of cache occupancy 472system.cpu0.dcache.tags.occ_percent::total 0.964507 # Average percentage of cache occupancy 473system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 474system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id 475system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 476system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 477system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 478system.cpu0.dcache.tags.tag_accesses 83782876 # Number of tag accesses 479system.cpu0.dcache.tags.data_accesses 83782876 # Number of data accesses 480system.cpu0.dcache.ReadReq_hits::cpu0.inst 22802755 # number of ReadReq hits 481system.cpu0.dcache.ReadReq_hits::total 22802755 # number of ReadReq hits 482system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862558 # number of WriteReq hits 483system.cpu0.dcache.WriteReq_hits::total 16862558 # number of WriteReq hits 484system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381551 # number of LoadLockedReq hits 485system.cpu0.dcache.LoadLockedReq_hits::total 381551 # number of LoadLockedReq hits 486system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362630 # number of StoreCondReq hits 487system.cpu0.dcache.StoreCondReq_hits::total 362630 # number of StoreCondReq hits 488system.cpu0.dcache.demand_hits::cpu0.inst 39665313 # number of demand (read+write) hits 489system.cpu0.dcache.demand_hits::total 39665313 # number of demand (read+write) hits 490system.cpu0.dcache.overall_hits::cpu0.inst 39665313 # number of overall hits 491system.cpu0.dcache.overall_hits::total 39665313 # number of overall hits 492system.cpu0.dcache.ReadReq_misses::cpu0.inst 537301 # number of ReadReq misses 493system.cpu0.dcache.ReadReq_misses::total 537301 # number of ReadReq misses 494system.cpu0.dcache.WriteReq_misses::cpu0.inst 532764 # number of WriteReq misses 495system.cpu0.dcache.WriteReq_misses::total 532764 # number of WriteReq misses 496system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6412 # number of LoadLockedReq misses 497system.cpu0.dcache.LoadLockedReq_misses::total 6412 # number of LoadLockedReq misses 498system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20204 # number of StoreCondReq misses 499system.cpu0.dcache.StoreCondReq_misses::total 20204 # number of StoreCondReq misses 500system.cpu0.dcache.demand_misses::cpu0.inst 1070065 # number of demand (read+write) misses 501system.cpu0.dcache.demand_misses::total 1070065 # number of demand (read+write) misses 502system.cpu0.dcache.overall_misses::cpu0.inst 1070065 # number of overall misses 503system.cpu0.dcache.overall_misses::total 1070065 # number of overall misses 504system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609674711 # number of ReadReq miss cycles 505system.cpu0.dcache.ReadReq_miss_latency::total 6609674711 # number of ReadReq miss cycles 506system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8019150247 # number of WriteReq miss cycles 507system.cpu0.dcache.WriteReq_miss_latency::total 8019150247 # number of WriteReq miss cycles 508system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 105707749 # number of LoadLockedReq miss cycles 509system.cpu0.dcache.LoadLockedReq_miss_latency::total 105707749 # number of LoadLockedReq miss cycles 510system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 437634051 # number of StoreCondReq miss cycles 511system.cpu0.dcache.StoreCondReq_miss_latency::total 437634051 # number of StoreCondReq miss cycles 512system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles 513system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles 514system.cpu0.dcache.demand_miss_latency::cpu0.inst 14628824958 # number of demand (read+write) miss cycles 515system.cpu0.dcache.demand_miss_latency::total 14628824958 # number of demand (read+write) miss cycles 516system.cpu0.dcache.overall_miss_latency::cpu0.inst 14628824958 # number of overall miss cycles 517system.cpu0.dcache.overall_miss_latency::total 14628824958 # number of overall miss cycles 518system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23340056 # number of ReadReq accesses(hits+misses) 519system.cpu0.dcache.ReadReq_accesses::total 23340056 # number of ReadReq accesses(hits+misses) 520system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395322 # number of WriteReq accesses(hits+misses) 521system.cpu0.dcache.WriteReq_accesses::total 17395322 # number of WriteReq accesses(hits+misses) 522system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387963 # number of LoadLockedReq accesses(hits+misses) 523system.cpu0.dcache.LoadLockedReq_accesses::total 387963 # number of LoadLockedReq accesses(hits+misses) 524system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382834 # number of StoreCondReq accesses(hits+misses) 525system.cpu0.dcache.StoreCondReq_accesses::total 382834 # number of StoreCondReq accesses(hits+misses) 526system.cpu0.dcache.demand_accesses::cpu0.inst 40735378 # number of demand (read+write) accesses 527system.cpu0.dcache.demand_accesses::total 40735378 # number of demand (read+write) accesses 528system.cpu0.dcache.overall_accesses::cpu0.inst 40735378 # number of overall (read+write) accesses 529system.cpu0.dcache.overall_accesses::total 40735378 # number of overall (read+write) accesses 530system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023021 # miss rate for ReadReq accesses 531system.cpu0.dcache.ReadReq_miss_rate::total 0.023021 # miss rate for ReadReq accesses 532system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030627 # miss rate for WriteReq accesses 533system.cpu0.dcache.WriteReq_miss_rate::total 0.030627 # miss rate for WriteReq accesses 534system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016527 # miss rate for LoadLockedReq accesses 535system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016527 # miss rate for LoadLockedReq accesses 536system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052775 # miss rate for StoreCondReq accesses 537system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052775 # miss rate for StoreCondReq accesses 538system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026269 # miss rate for demand accesses 539system.cpu0.dcache.demand_miss_rate::total 0.026269 # miss rate for demand accesses 540system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026269 # miss rate for overall accesses 541system.cpu0.dcache.overall_miss_rate::total 0.026269 # miss rate for overall accesses 542system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12301.623691 # average ReadReq miss latency 543system.cpu0.dcache.ReadReq_avg_miss_latency::total 12301.623691 # average ReadReq miss latency 544system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15051.974696 # average WriteReq miss latency 545system.cpu0.dcache.WriteReq_avg_miss_latency::total 15051.974696 # average WriteReq miss latency 546system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16485.924672 # average LoadLockedReq miss latency 547system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16485.924672 # average LoadLockedReq miss latency 548system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21660.762770 # average StoreCondReq miss latency 549system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21660.762770 # average StoreCondReq miss latency 550system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 551system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 552system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency 553system.cpu0.dcache.demand_avg_miss_latency::total 13670.968547 # average overall miss latency 554system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency 555system.cpu0.dcache.overall_avg_miss_latency::total 13670.968547 # average overall miss latency 556system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 557system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 558system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 559system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 560system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 561system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 562system.cpu0.dcache.fast_writes 0 # number of fast writes performed 563system.cpu0.dcache.cache_copies 0 # number of cache copies performed 564system.cpu0.dcache.writebacks::writebacks 517954 # number of writebacks 565system.cpu0.dcache.writebacks::total 517954 # number of writebacks 566system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42678 # number of ReadReq MSHR hits 567system.cpu0.dcache.ReadReq_mshr_hits::total 42678 # number of ReadReq MSHR hits 568system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230706 # number of WriteReq MSHR hits 569system.cpu0.dcache.WriteReq_mshr_hits::total 230706 # number of WriteReq MSHR hits 570system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits 571system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits 572system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273384 # number of demand (read+write) MSHR hits 573system.cpu0.dcache.demand_mshr_hits::total 273384 # number of demand (read+write) MSHR hits 574system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273384 # number of overall MSHR hits 575system.cpu0.dcache.overall_mshr_hits::total 273384 # number of overall MSHR hits 576system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494623 # number of ReadReq MSHR misses 577system.cpu0.dcache.ReadReq_mshr_misses::total 494623 # number of ReadReq MSHR misses 578system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302058 # number of WriteReq MSHR misses 579system.cpu0.dcache.WriteReq_mshr_misses::total 302058 # number of WriteReq MSHR misses 580system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6411 # number of LoadLockedReq MSHR misses 581system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6411 # number of LoadLockedReq MSHR misses 582system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20204 # number of StoreCondReq MSHR misses 583system.cpu0.dcache.StoreCondReq_mshr_misses::total 20204 # number of StoreCondReq MSHR misses 584system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796681 # number of demand (read+write) MSHR misses 585system.cpu0.dcache.demand_mshr_misses::total 796681 # number of demand (read+write) MSHR misses 586system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796681 # number of overall MSHR misses 587system.cpu0.dcache.overall_mshr_misses::total 796681 # number of overall MSHR misses 588system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5117531439 # number of ReadReq MSHR miss cycles 589system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5117531439 # number of ReadReq MSHR miss cycles 590system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4270825900 # number of WriteReq MSHR miss cycles 591system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4270825900 # number of WriteReq MSHR miss cycles 592system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 92832750 # number of LoadLockedReq MSHR miss cycles 593system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 92832750 # number of LoadLockedReq MSHR miss cycles 594system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 396783949 # number of StoreCondReq MSHR miss cycles 595system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 396783949 # number of StoreCondReq MSHR miss cycles 596system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles 597system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles 598system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9388357339 # number of demand (read+write) MSHR miss cycles 599system.cpu0.dcache.demand_mshr_miss_latency::total 9388357339 # number of demand (read+write) MSHR miss cycles 600system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9388357339 # number of overall MSHR miss cycles 601system.cpu0.dcache.overall_mshr_miss_latency::total 9388357339 # number of overall MSHR miss cycles 602system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191310497 # number of ReadReq MSHR uncacheable cycles 603system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191310497 # number of ReadReq MSHR uncacheable cycles 604system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803760492 # number of WriteReq MSHR uncacheable cycles 605system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803760492 # number of WriteReq MSHR uncacheable cycles 606system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995070989 # number of overall MSHR uncacheable cycles 607system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995070989 # number of overall MSHR uncacheable cycles 608system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021192 # mshr miss rate for ReadReq accesses 609system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021192 # mshr miss rate for ReadReq accesses 610system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017364 # mshr miss rate for WriteReq accesses 611system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017364 # mshr miss rate for WriteReq accesses 612system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016525 # mshr miss rate for LoadLockedReq accesses 613system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016525 # mshr miss rate for LoadLockedReq accesses 614system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052775 # mshr miss rate for StoreCondReq accesses 615system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052775 # mshr miss rate for StoreCondReq accesses 616system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for demand accesses 617system.cpu0.dcache.demand_mshr_miss_rate::total 0.019557 # mshr miss rate for demand accesses 618system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for overall accesses 619system.cpu0.dcache.overall_mshr_miss_rate::total 0.019557 # mshr miss rate for overall accesses 620system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10346.327282 # average ReadReq mshr miss latency 621system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10346.327282 # average ReadReq mshr miss latency 622system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14139.092161 # average WriteReq mshr miss latency 623system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14139.092161 # average WriteReq mshr miss latency 624system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14480.229293 # average LoadLockedReq mshr miss latency 625system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14480.229293 # average LoadLockedReq mshr miss latency 626system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19638.880865 # average StoreCondReq mshr miss latency 627system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19638.880865 # average StoreCondReq mshr miss latency 628system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 629system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 630system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency 631system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency 632system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency 633system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency 634system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 635system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 636system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 637system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 638system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 639system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 640system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 641system.cpu0.icache.tags.replacements 1983566 # number of replacements 642system.cpu0.icache.tags.tagsinuse 511.796833 # Cycle average of tags in use 643system.cpu0.icache.tags.total_refs 68366923 # Total number of references to valid blocks. 644system.cpu0.icache.tags.sampled_refs 1984078 # Sample count of references to valid blocks. 645system.cpu0.icache.tags.avg_refs 34.457780 # Average number of references to valid blocks. |
646system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit.
|
1108system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796419 # Average occupied blocks per requestor
1109system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999602 # Average percentage of cache occupancy
1110system.cpu0.icache.tags.occ_percent::total 0.999602 # Average percentage of cache occupancy
|
647system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796833 # Average occupied blocks per requestor 648system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy 649system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy |
650system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
1112system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
1113system.cpu0.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id
1114system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id
|
651system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 652system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id 653system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id |
654system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
1116system.cpu0.icache.tags.tag_accesses 142701293 # Number of tag accesses
1117system.cpu0.icache.tags.data_accesses 142701293 # Number of data accesses
1118system.cpu0.icache.ReadReq_hits::cpu0.inst 68375163 # number of ReadReq hits
1119system.cpu0.icache.ReadReq_hits::total 68375163 # number of ReadReq hits
1120system.cpu0.icache.demand_hits::cpu0.inst 68375163 # number of demand (read+write) hits
1121system.cpu0.icache.demand_hits::total 68375163 # number of demand (read+write) hits
1122system.cpu0.icache.overall_hits::cpu0.inst 68375163 # number of overall hits
1123system.cpu0.icache.overall_hits::total 68375163 # number of overall hits
1124system.cpu0.icache.ReadReq_misses::cpu0.inst 1983656 # number of ReadReq misses
1125system.cpu0.icache.ReadReq_misses::total 1983656 # number of ReadReq misses
1126system.cpu0.icache.demand_misses::cpu0.inst 1983656 # number of demand (read+write) misses
1127system.cpu0.icache.demand_misses::total 1983656 # number of demand (read+write) misses
1128system.cpu0.icache.overall_misses::cpu0.inst 1983656 # number of overall misses
1129system.cpu0.icache.overall_misses::total 1983656 # number of overall misses
1130system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16542962894 # number of ReadReq miss cycles
1131system.cpu0.icache.ReadReq_miss_latency::total 16542962894 # number of ReadReq miss cycles
1132system.cpu0.icache.demand_miss_latency::cpu0.inst 16542962894 # number of demand (read+write) miss cycles
1133system.cpu0.icache.demand_miss_latency::total 16542962894 # number of demand (read+write) miss cycles
1134system.cpu0.icache.overall_miss_latency::cpu0.inst 16542962894 # number of overall miss cycles
1135system.cpu0.icache.overall_miss_latency::total 16542962894 # number of overall miss cycles
1136system.cpu0.icache.ReadReq_accesses::cpu0.inst 70358819 # number of ReadReq accesses(hits+misses)
1137system.cpu0.icache.ReadReq_accesses::total 70358819 # number of ReadReq accesses(hits+misses)
1138system.cpu0.icache.demand_accesses::cpu0.inst 70358819 # number of demand (read+write) accesses
1139system.cpu0.icache.demand_accesses::total 70358819 # number of demand (read+write) accesses
1140system.cpu0.icache.overall_accesses::cpu0.inst 70358819 # number of overall (read+write) accesses
1141system.cpu0.icache.overall_accesses::total 70358819 # number of overall (read+write) accesses
1142system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028193 # miss rate for ReadReq accesses
1143system.cpu0.icache.ReadReq_miss_rate::total 0.028193 # miss rate for ReadReq accesses
1144system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028193 # miss rate for demand accesses
1145system.cpu0.icache.demand_miss_rate::total 0.028193 # miss rate for demand accesses
1146system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028193 # miss rate for overall accesses
1147system.cpu0.icache.overall_miss_rate::total 0.028193 # miss rate for overall accesses
1148system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.632927 # average ReadReq miss latency
1149system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.632927 # average ReadReq miss latency
1150system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency
1151system.cpu0.icache.demand_avg_miss_latency::total 8339.632927 # average overall miss latency
1152system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency
1153system.cpu0.icache.overall_avg_miss_latency::total 8339.632927 # average overall miss latency
|
655system.cpu0.icache.tags.tag_accesses 142686127 # Number of tag accesses 656system.cpu0.icache.tags.data_accesses 142686127 # Number of data accesses 657system.cpu0.icache.ReadReq_hits::cpu0.inst 68366923 # number of ReadReq hits 658system.cpu0.icache.ReadReq_hits::total 68366923 # number of ReadReq hits 659system.cpu0.icache.demand_hits::cpu0.inst 68366923 # number of demand (read+write) hits 660system.cpu0.icache.demand_hits::total 68366923 # number of demand (read+write) hits 661system.cpu0.icache.overall_hits::cpu0.inst 68366923 # number of overall hits 662system.cpu0.icache.overall_hits::total 68366923 # number of overall hits 663system.cpu0.icache.ReadReq_misses::cpu0.inst 1984094 # number of ReadReq misses 664system.cpu0.icache.ReadReq_misses::total 1984094 # number of ReadReq misses 665system.cpu0.icache.demand_misses::cpu0.inst 1984094 # number of demand (read+write) misses 666system.cpu0.icache.demand_misses::total 1984094 # number of demand (read+write) misses 667system.cpu0.icache.overall_misses::cpu0.inst 1984094 # number of overall misses 668system.cpu0.icache.overall_misses::total 1984094 # number of overall misses 669system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16546799645 # number of ReadReq miss cycles 670system.cpu0.icache.ReadReq_miss_latency::total 16546799645 # number of ReadReq miss cycles 671system.cpu0.icache.demand_miss_latency::cpu0.inst 16546799645 # number of demand (read+write) miss cycles 672system.cpu0.icache.demand_miss_latency::total 16546799645 # number of demand (read+write) miss cycles 673system.cpu0.icache.overall_miss_latency::cpu0.inst 16546799645 # number of overall miss cycles 674system.cpu0.icache.overall_miss_latency::total 16546799645 # number of overall miss cycles 675system.cpu0.icache.ReadReq_accesses::cpu0.inst 70351017 # number of ReadReq accesses(hits+misses) 676system.cpu0.icache.ReadReq_accesses::total 70351017 # number of ReadReq accesses(hits+misses) 677system.cpu0.icache.demand_accesses::cpu0.inst 70351017 # number of demand (read+write) accesses 678system.cpu0.icache.demand_accesses::total 70351017 # number of demand (read+write) accesses 679system.cpu0.icache.overall_accesses::cpu0.inst 70351017 # number of overall (read+write) accesses 680system.cpu0.icache.overall_accesses::total 70351017 # number of overall (read+write) accesses 681system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028203 # miss rate for ReadReq accesses 682system.cpu0.icache.ReadReq_miss_rate::total 0.028203 # miss rate for ReadReq accesses 683system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028203 # miss rate for demand accesses 684system.cpu0.icache.demand_miss_rate::total 0.028203 # miss rate for demand accesses 685system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028203 # miss rate for overall accesses 686system.cpu0.icache.overall_miss_rate::total 0.028203 # miss rate for overall accesses 687system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.725661 # average ReadReq miss latency 688system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.725661 # average ReadReq miss latency 689system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency 690system.cpu0.icache.demand_avg_miss_latency::total 8339.725661 # average overall miss latency 691system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency 692system.cpu0.icache.overall_avg_miss_latency::total 8339.725661 # average overall miss latency |
693system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 697system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 698system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 699system.cpu0.icache.fast_writes 0 # number of fast writes performed 700system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
1162system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1983656 # number of ReadReq MSHR misses
1163system.cpu0.icache.ReadReq_mshr_misses::total 1983656 # number of ReadReq MSHR misses
1164system.cpu0.icache.demand_mshr_misses::cpu0.inst 1983656 # number of demand (read+write) MSHR misses
1165system.cpu0.icache.demand_mshr_misses::total 1983656 # number of demand (read+write) MSHR misses
1166system.cpu0.icache.overall_mshr_misses::cpu0.inst 1983656 # number of overall MSHR misses
1167system.cpu0.icache.overall_mshr_misses::total 1983656 # number of overall MSHR misses
1168system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13565509604 # number of ReadReq MSHR miss cycles
1169system.cpu0.icache.ReadReq_mshr_miss_latency::total 13565509604 # number of ReadReq MSHR miss cycles
1170system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13565509604 # number of demand (read+write) MSHR miss cycles
1171system.cpu0.icache.demand_mshr_miss_latency::total 13565509604 # number of demand (read+write) MSHR miss cycles
1172system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13565509604 # number of overall MSHR miss cycles
1173system.cpu0.icache.overall_mshr_miss_latency::total 13565509604 # number of overall MSHR miss cycles
|
701system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1984094 # number of ReadReq MSHR misses 702system.cpu0.icache.ReadReq_mshr_misses::total 1984094 # number of ReadReq MSHR misses 703system.cpu0.icache.demand_mshr_misses::cpu0.inst 1984094 # number of demand (read+write) MSHR misses 704system.cpu0.icache.demand_mshr_misses::total 1984094 # number of demand (read+write) MSHR misses 705system.cpu0.icache.overall_mshr_misses::cpu0.inst 1984094 # number of overall MSHR misses 706system.cpu0.icache.overall_mshr_misses::total 1984094 # number of overall MSHR misses 707system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13568682853 # number of ReadReq MSHR miss cycles 708system.cpu0.icache.ReadReq_mshr_miss_latency::total 13568682853 # number of ReadReq MSHR miss cycles 709system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13568682853 # number of demand (read+write) MSHR miss cycles 710system.cpu0.icache.demand_mshr_miss_latency::total 13568682853 # number of demand (read+write) MSHR miss cycles 711system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13568682853 # number of overall MSHR miss cycles 712system.cpu0.icache.overall_mshr_miss_latency::total 13568682853 # number of overall MSHR miss cycles |
713system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276787500 # number of ReadReq MSHR uncacheable cycles 714system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276787500 # number of ReadReq MSHR uncacheable cycles 715system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276787500 # number of overall MSHR uncacheable cycles 716system.cpu0.icache.overall_mshr_uncacheable_latency::total 276787500 # number of overall MSHR uncacheable cycles
|
1178system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for ReadReq accesses
1179system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028193 # mshr miss rate for ReadReq accesses
1180system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for demand accesses
1181system.cpu0.icache.demand_mshr_miss_rate::total 0.028193 # mshr miss rate for demand accesses
1182system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for overall accesses
1183system.cpu0.icache.overall_mshr_miss_rate::total 0.028193 # mshr miss rate for overall accesses
1184system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average ReadReq mshr miss latency
1185system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.640169 # average ReadReq mshr miss latency
1186system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency
1187system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency
1188system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency
1189system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency
|
717system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for ReadReq accesses 718system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028203 # mshr miss rate for ReadReq accesses 719system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for demand accesses 720system.cpu0.icache.demand_mshr_miss_rate::total 0.028203 # mshr miss rate for demand accesses 721system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for overall accesses 722system.cpu0.icache.overall_mshr_miss_rate::total 0.028203 # mshr miss rate for overall accesses 723system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average ReadReq mshr miss latency 724system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.729845 # average ReadReq mshr miss latency 725system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency 726system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency 727system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency 728system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency |
729system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 730system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 731system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 732system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 733system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
1195system.cpu0.toL2Bus.trans_dist::ReadReq 2764616 # Transaction distribution
1196system.cpu0.toL2Bus.trans_dist::ReadResp 2669805 # Transaction distribution
1197system.cpu0.toL2Bus.trans_dist::WriteReq 28812 # Transaction distribution
1198system.cpu0.toL2Bus.trans_dist::WriteResp 28812 # Transaction distribution
1199system.cpu0.toL2Bus.trans_dist::Writeback 518092 # Transaction distribution
1200system.cpu0.toL2Bus.trans_dist::HardPFReq 696796 # Transaction distribution
1201system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
1202system.cpu0.toL2Bus.trans_dist::UpgradeReq 70569 # Transaction distribution
1203system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42644 # Transaction distribution
1204system.cpu0.toL2Bus.trans_dist::UpgradeResp 93797 # Transaction distribution
1205system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
1206system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
1207system.cpu0.toL2Bus.trans_dist::ReadExReq 291655 # Transaction distribution
1208system.cpu0.toL2Bus.trans_dist::ReadExResp 282058 # Transaction distribution
1209system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3973433 # Packet count per connected master and slave (bytes)
1210system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393866 # Packet count per connected master and slave (bytes)
1211system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11794 # Packet count per connected master and slave (bytes)
1212system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167556 # Packet count per connected master and slave (bytes)
1213system.cpu0.toL2Bus.pkt_count::total 6546649 # Packet count per connected master and slave (bytes)
1214system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127149824 # Cumulative packet size per connected master and slave (bytes)
1215system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86895095 # Cumulative packet size per connected master and slave (bytes)
1216system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17624 # Cumulative packet size per connected master and slave (bytes)
1217system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313964 # Cumulative packet size per connected master and slave (bytes)
1218system.cpu0.toL2Bus.pkt_size::total 214376507 # Cumulative packet size per connected master and slave (bytes)
1219system.cpu0.toL2Bus.snoops 1084116 # Total snoops (count)
1220system.cpu0.toL2Bus.snoop_fanout::samples 4385551 # Request fanout histogram
1221system.cpu0.toL2Bus.snoop_fanout::mean 5.219745 # Request fanout histogram
1222system.cpu0.toL2Bus.snoop_fanout::stdev 0.414074 # Request fanout histogram
1223system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1224system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1225system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1226system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1227system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1228system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1229system.cpu0.toL2Bus.snoop_fanout::5 3421847 78.03% 78.03% # Request fanout histogram
1230system.cpu0.toL2Bus.snoop_fanout::6 963704 21.97% 100.00% # Request fanout histogram
1231system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1232system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1233system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1234system.cpu0.toL2Bus.snoop_fanout::total 4385551 # Request fanout histogram
1235system.cpu0.toL2Bus.reqLayer0.occupancy 2275908733 # Layer occupancy (ticks)
1236system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1237system.cpu0.toL2Bus.snoopLayer0.occupancy 119359000 # Layer occupancy (ticks)
1238system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1239system.cpu0.toL2Bus.respLayer0.occupancy 2981732395 # Layer occupancy (ticks)
1240system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1241system.cpu0.toL2Bus.respLayer1.occupancy 1235696460 # Layer occupancy (ticks)
1242system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1243system.cpu0.toL2Bus.respLayer2.occupancy 7392491 # Layer occupancy (ticks)
1244system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1245system.cpu0.toL2Bus.respLayer3.occupancy 89085972 # Layer occupancy (ticks)
1246system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1247system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17333419 # number of hwpf identified
1248system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425629 # number of hwpf that were already in mshr
1249system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16380209 # number of hwpf that were already in the cache
1250system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9025 # number of hwpf that were already in the prefetch queue
|
734system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17337039 # number of hwpf identified 735system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425762 # number of hwpf that were already in mshr 736system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16383461 # number of hwpf that were already in the cache 737system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9078 # number of hwpf that were already in the prefetch queue |
738system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
1252system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6465 # number of hwpf removed because MSHR allocated
1253system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512088 # number of hwpf issued
1254system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329549 # number of hwpf spanning a virtual page
|
739system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6456 # number of hwpf removed because MSHR allocated 740system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512279 # number of hwpf issued 741system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329409 # number of hwpf spanning a virtual page |
742system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
1256system.cpu0.l2cache.tags.replacements 409658 # number of replacements
1257system.cpu0.l2cache.tags.tagsinuse 16201.472263 # Cycle average of tags in use
1258system.cpu0.l2cache.tags.total_refs 3013143 # Total number of references to valid blocks.
1259system.cpu0.l2cache.tags.sampled_refs 425913 # Sample count of references to valid blocks.
1260system.cpu0.l2cache.tags.avg_refs 7.074550 # Average number of references to valid blocks.
1261system.cpu0.l2cache.tags.warmup_cycle 2824446064500 # Cycle when the warmup percentage was hit.
1262system.cpu0.l2cache.tags.occ_blocks::writebacks 4208.967244 # Average occupied blocks per requestor
1263system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.817277 # Average occupied blocks per requestor
1264system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.069510 # Average occupied blocks per requestor
1265system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2196.768436 # Average occupied blocks per requestor
1266system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.849796 # Average occupied blocks per requestor
1267system.cpu0.l2cache.tags.occ_percent::writebacks 0.256895 # Average percentage of cache occupancy
1268system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002919 # Average percentage of cache occupancy
|
743system.cpu0.l2cache.tags.replacements 409357 # number of replacements 744system.cpu0.l2cache.tags.tagsinuse 16202.462840 # Cycle average of tags in use 745system.cpu0.l2cache.tags.total_refs 3013500 # Total number of references to valid blocks. 746system.cpu0.l2cache.tags.sampled_refs 425611 # Sample count of references to valid blocks. 747system.cpu0.l2cache.tags.avg_refs 7.080409 # Average number of references to valid blocks. 748system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 749system.cpu0.l2cache.tags.occ_blocks::writebacks 4205.324174 # Average occupied blocks per requestor 750system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 51.364575 # Average occupied blocks per requestor 751system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062072 # Average occupied blocks per requestor 752system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2198.474976 # Average occupied blocks per requestor 753system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.237044 # Average occupied blocks per requestor 754system.cpu0.l2cache.tags.occ_percent::writebacks 0.256673 # Average percentage of cache occupancy 755system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003135 # Average percentage of cache occupancy |
756system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
|
1270system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134080 # Average percentage of cache occupancy
1271system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594962 # Average percentage of cache occupancy
1272system.cpu0.l2cache.tags.occ_percent::total 0.988859 # Average percentage of cache occupancy
1273system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8953 # Occupied blocks per task id
1274system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
1275system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7296 # Occupied blocks per task id
1276system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id
1277system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id
1278system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2849 # Occupied blocks per task id
1279system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5159 # Occupied blocks per task id
1280system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 779 # Occupied blocks per task id
1281system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
|
757system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134184 # Average percentage of cache occupancy 758system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594924 # Average percentage of cache occupancy 759system.cpu0.l2cache.tags.occ_percent::total 0.988920 # Average percentage of cache occupancy 760system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8963 # Occupied blocks per task id 761system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 762system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7281 # Occupied blocks per task id 763system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 54 # Occupied blocks per task id 764system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id 765system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2805 # Occupied blocks per task id 766system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5150 # Occupied blocks per task id 767system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 820 # Occupied blocks per task id 768system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 769system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 770system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id |
771system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
|
1283system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
1284system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
1285system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
1286system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3166 # Occupied blocks per task id
1287system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id
1288system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 286 # Occupied blocks per task id
1289system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546448 # Percentage of cache occupancy per task id
1290system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
1291system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.445312 # Percentage of cache occupancy per task id
1292system.cpu0.l2cache.tags.tag_accesses 55304097 # Number of tag accesses
1293system.cpu0.l2cache.tags.data_accesses 55304097 # Number of data accesses
1294system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77521 # number of ReadReq hits
1295system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4240 # number of ReadReq hits
1296system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390628 # number of ReadReq hits
1297system.cpu0.l2cache.ReadReq_hits::total 2472389 # number of ReadReq hits
1298system.cpu0.l2cache.Writeback_hits::writebacks 518092 # number of Writeback hits
1299system.cpu0.l2cache.Writeback_hits::total 518092 # number of Writeback hits
1300system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4676 # number of UpgradeReq hits
1301system.cpu0.l2cache.UpgradeReq_hits::total 4676 # number of UpgradeReq hits
1302system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2297 # number of SCUpgradeReq hits
1303system.cpu0.l2cache.SCUpgradeReq_hits::total 2297 # number of SCUpgradeReq hits
1304system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223112 # number of ReadExReq hits
1305system.cpu0.l2cache.ReadExReq_hits::total 223112 # number of ReadExReq hits
1306system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77521 # number of demand (read+write) hits
1307system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4240 # number of demand (read+write) hits
1308system.cpu0.l2cache.demand_hits::cpu0.inst 2613740 # number of demand (read+write) hits
1309system.cpu0.l2cache.demand_hits::total 2695501 # number of demand (read+write) hits
1310system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77521 # number of overall hits
1311system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4240 # number of overall hits
1312system.cpu0.l2cache.overall_hits::cpu0.inst 2613740 # number of overall hits
1313system.cpu0.l2cache.overall_hits::total 2695501 # number of overall hits
1314system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 970 # number of ReadReq misses
1315system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 166 # number of ReadReq misses
1316system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94231 # number of ReadReq misses
1317system.cpu0.l2cache.ReadReq_misses::total 95367 # number of ReadReq misses
1318system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27951 # number of UpgradeReq misses
1319system.cpu0.l2cache.UpgradeReq_misses::total 27951 # number of UpgradeReq misses
1320system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17951 # number of SCUpgradeReq misses
1321system.cpu0.l2cache.SCUpgradeReq_misses::total 17951 # number of SCUpgradeReq misses
|
772system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 773system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 774system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id 775system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3125 # Occupied blocks per task id 776system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3482 # Occupied blocks per task id 777system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 341 # Occupied blocks per task id 778system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.547058 # Percentage of cache occupancy per task id 779system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 780system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444397 # Percentage of cache occupancy per task id 781system.cpu0.l2cache.tags.tag_accesses 55309059 # Number of tag accesses 782system.cpu0.l2cache.tags.data_accesses 55309059 # Number of data accesses 783system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77781 # number of ReadReq hits 784system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4268 # number of ReadReq hits 785system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390782 # number of ReadReq hits 786system.cpu0.l2cache.ReadReq_hits::total 2472831 # number of ReadReq hits 787system.cpu0.l2cache.Writeback_hits::writebacks 517951 # number of Writeback hits 788system.cpu0.l2cache.Writeback_hits::total 517951 # number of Writeback hits 789system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4630 # number of UpgradeReq hits 790system.cpu0.l2cache.UpgradeReq_hits::total 4630 # number of UpgradeReq hits 791system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2244 # number of SCUpgradeReq hits 792system.cpu0.l2cache.SCUpgradeReq_hits::total 2244 # number of SCUpgradeReq hits 793system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223140 # number of ReadExReq hits 794system.cpu0.l2cache.ReadExReq_hits::total 223140 # number of ReadExReq hits 795system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77781 # number of demand (read+write) hits 796system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4268 # number of demand (read+write) hits 797system.cpu0.l2cache.demand_hits::cpu0.inst 2613922 # number of demand (read+write) hits 798system.cpu0.l2cache.demand_hits::total 2695971 # number of demand (read+write) hits 799system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77781 # number of overall hits 800system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4268 # number of overall hits 801system.cpu0.l2cache.overall_hits::cpu0.inst 2613922 # number of overall hits 802system.cpu0.l2cache.overall_hits::total 2695971 # number of overall hits 803system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 986 # number of ReadReq misses 804system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses 805system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94341 # number of ReadReq misses 806system.cpu0.l2cache.ReadReq_misses::total 95500 # number of ReadReq misses 807system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27941 # number of UpgradeReq misses 808system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses 809system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17958 # number of SCUpgradeReq misses 810system.cpu0.l2cache.SCUpgradeReq_misses::total 17958 # number of SCUpgradeReq misses |
811system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 2 # number of SCUpgradeFailReq misses 812system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
|
1324system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46376 # number of ReadExReq misses
1325system.cpu0.l2cache.ReadExReq_misses::total 46376 # number of ReadExReq misses
1326system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 970 # number of demand (read+write) misses
1327system.cpu0.l2cache.demand_misses::cpu0.itb.walker 166 # number of demand (read+write) misses
1328system.cpu0.l2cache.demand_misses::cpu0.inst 140607 # number of demand (read+write) misses
1329system.cpu0.l2cache.demand_misses::total 141743 # number of demand (read+write) misses
1330system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 970 # number of overall misses
1331system.cpu0.l2cache.overall_misses::cpu0.itb.walker 166 # number of overall misses
1332system.cpu0.l2cache.overall_misses::cpu0.inst 140607 # number of overall misses
1333system.cpu0.l2cache.overall_misses::total 141743 # number of overall misses
1334system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31913749 # number of ReadReq miss cycles
1335system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3705999 # number of ReadReq miss cycles
1336system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2892277884 # number of ReadReq miss cycles
1337system.cpu0.l2cache.ReadReq_miss_latency::total 2927897632 # number of ReadReq miss cycles
1338system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 496957551 # number of UpgradeReq miss cycles
1339system.cpu0.l2cache.UpgradeReq_miss_latency::total 496957551 # number of UpgradeReq miss cycles
1340system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 355013747 # number of SCUpgradeReq miss cycles
1341system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 355013747 # number of SCUpgradeReq miss cycles
|
813system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46352 # number of ReadExReq misses 814system.cpu0.l2cache.ReadExReq_misses::total 46352 # number of ReadExReq misses 815system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 986 # number of demand (read+write) misses 816system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses 817system.cpu0.l2cache.demand_misses::cpu0.inst 140693 # number of demand (read+write) misses 818system.cpu0.l2cache.demand_misses::total 141852 # number of demand (read+write) misses 819system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 986 # number of overall misses 820system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses 821system.cpu0.l2cache.overall_misses::cpu0.inst 140693 # number of overall misses 822system.cpu0.l2cache.overall_misses::total 141852 # number of overall misses 823system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 32261749 # number of ReadReq miss cycles 824system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3849999 # number of ReadReq miss cycles 825system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2894443882 # number of ReadReq miss cycles 826system.cpu0.l2cache.ReadReq_miss_latency::total 2930555630 # number of ReadReq miss cycles 827system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 497270548 # number of UpgradeReq miss cycles 828system.cpu0.l2cache.UpgradeReq_miss_latency::total 497270548 # number of UpgradeReq miss cycles 829system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 354837739 # number of SCUpgradeReq miss cycles 830system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 354837739 # number of SCUpgradeReq miss cycles |
831system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 117000 # number of SCUpgradeFailReq miss cycles 832system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 117000 # number of SCUpgradeFailReq miss cycles
|
1344system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1927567955 # number of ReadExReq miss cycles
1345system.cpu0.l2cache.ReadExReq_miss_latency::total 1927567955 # number of ReadExReq miss cycles
1346system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31913749 # number of demand (read+write) miss cycles
1347system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3705999 # number of demand (read+write) miss cycles
1348system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4819845839 # number of demand (read+write) miss cycles
1349system.cpu0.l2cache.demand_miss_latency::total 4855465587 # number of demand (read+write) miss cycles
1350system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31913749 # number of overall miss cycles
1351system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3705999 # number of overall miss cycles
1352system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4819845839 # number of overall miss cycles
1353system.cpu0.l2cache.overall_miss_latency::total 4855465587 # number of overall miss cycles
1354system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78491 # number of ReadReq accesses(hits+misses)
1355system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4406 # number of ReadReq accesses(hits+misses)
1356system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2484859 # number of ReadReq accesses(hits+misses)
1357system.cpu0.l2cache.ReadReq_accesses::total 2567756 # number of ReadReq accesses(hits+misses)
1358system.cpu0.l2cache.Writeback_accesses::writebacks 518092 # number of Writeback accesses(hits+misses)
1359system.cpu0.l2cache.Writeback_accesses::total 518092 # number of Writeback accesses(hits+misses)
1360system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32627 # number of UpgradeReq accesses(hits+misses)
1361system.cpu0.l2cache.UpgradeReq_accesses::total 32627 # number of UpgradeReq accesses(hits+misses)
1362system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20248 # number of SCUpgradeReq accesses(hits+misses)
1363system.cpu0.l2cache.SCUpgradeReq_accesses::total 20248 # number of SCUpgradeReq accesses(hits+misses)
|
833system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1925679719 # number of ReadExReq miss cycles 834system.cpu0.l2cache.ReadExReq_miss_latency::total 1925679719 # number of ReadExReq miss cycles 835system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 32261749 # number of demand (read+write) miss cycles 836system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3849999 # number of demand (read+write) miss cycles 837system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4820123601 # number of demand (read+write) miss cycles 838system.cpu0.l2cache.demand_miss_latency::total 4856235349 # number of demand (read+write) miss cycles 839system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 32261749 # number of overall miss cycles 840system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3849999 # number of overall miss cycles 841system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4820123601 # number of overall miss cycles 842system.cpu0.l2cache.overall_miss_latency::total 4856235349 # number of overall miss cycles 843system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78767 # number of ReadReq accesses(hits+misses) 844system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4441 # number of ReadReq accesses(hits+misses) 845system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2485123 # number of ReadReq accesses(hits+misses) 846system.cpu0.l2cache.ReadReq_accesses::total 2568331 # number of ReadReq accesses(hits+misses) 847system.cpu0.l2cache.Writeback_accesses::writebacks 517951 # number of Writeback accesses(hits+misses) 848system.cpu0.l2cache.Writeback_accesses::total 517951 # number of Writeback accesses(hits+misses) 849system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32571 # number of UpgradeReq accesses(hits+misses) 850system.cpu0.l2cache.UpgradeReq_accesses::total 32571 # number of UpgradeReq accesses(hits+misses) 851system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20202 # number of SCUpgradeReq accesses(hits+misses) 852system.cpu0.l2cache.SCUpgradeReq_accesses::total 20202 # number of SCUpgradeReq accesses(hits+misses) |
853system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 2 # number of SCUpgradeFailReq accesses(hits+misses) 854system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
|
1366system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 269488 # number of ReadExReq accesses(hits+misses)
1367system.cpu0.l2cache.ReadExReq_accesses::total 269488 # number of ReadExReq accesses(hits+misses)
1368system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78491 # number of demand (read+write) accesses
1369system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4406 # number of demand (read+write) accesses
1370system.cpu0.l2cache.demand_accesses::cpu0.inst 2754347 # number of demand (read+write) accesses
1371system.cpu0.l2cache.demand_accesses::total 2837244 # number of demand (read+write) accesses
1372system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78491 # number of overall (read+write) accesses
1373system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4406 # number of overall (read+write) accesses
1374system.cpu0.l2cache.overall_accesses::cpu0.inst 2754347 # number of overall (read+write) accesses
1375system.cpu0.l2cache.overall_accesses::total 2837244 # number of overall (read+write) accesses
1376system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for ReadReq accesses
1377system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037676 # miss rate for ReadReq accesses
1378system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037922 # miss rate for ReadReq accesses
1379system.cpu0.l2cache.ReadReq_miss_rate::total 0.037140 # miss rate for ReadReq accesses
1380system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.856683 # miss rate for UpgradeReq accesses
1381system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.856683 # miss rate for UpgradeReq accesses
1382system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.886557 # miss rate for SCUpgradeReq accesses
1383system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.886557 # miss rate for SCUpgradeReq accesses
|
855system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 269492 # number of ReadExReq accesses(hits+misses) 856system.cpu0.l2cache.ReadExReq_accesses::total 269492 # number of ReadExReq accesses(hits+misses) 857system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78767 # number of demand (read+write) accesses 858system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4441 # number of demand (read+write) accesses 859system.cpu0.l2cache.demand_accesses::cpu0.inst 2754615 # number of demand (read+write) accesses 860system.cpu0.l2cache.demand_accesses::total 2837823 # number of demand (read+write) accesses 861system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78767 # number of overall (read+write) accesses 862system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4441 # number of overall (read+write) accesses 863system.cpu0.l2cache.overall_accesses::cpu0.inst 2754615 # number of overall (read+write) accesses 864system.cpu0.l2cache.overall_accesses::total 2837823 # number of overall (read+write) accesses 865system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for ReadReq accesses 866system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.038955 # miss rate for ReadReq accesses 867system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037962 # miss rate for ReadReq accesses 868system.cpu0.l2cache.ReadReq_miss_rate::total 0.037184 # miss rate for ReadReq accesses 869system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.857849 # miss rate for UpgradeReq accesses 870system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.857849 # miss rate for UpgradeReq accesses 871system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.888922 # miss rate for SCUpgradeReq accesses 872system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.888922 # miss rate for SCUpgradeReq accesses |
873system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses 874system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
|
1386system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.172089 # miss rate for ReadExReq accesses
1387system.cpu0.l2cache.ReadExReq_miss_rate::total 0.172089 # miss rate for ReadExReq accesses
1388system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for demand accesses
1389system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037676 # miss rate for demand accesses
1390system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051049 # miss rate for demand accesses
1391system.cpu0.l2cache.demand_miss_rate::total 0.049958 # miss rate for demand accesses
1392system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for overall accesses
1393system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037676 # miss rate for overall accesses
1394system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051049 # miss rate for overall accesses
1395system.cpu0.l2cache.overall_miss_rate::total 0.049958 # miss rate for overall accesses
1396system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average ReadReq miss latency
1397system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22325.295181 # average ReadReq miss latency
1398system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30693.486050 # average ReadReq miss latency
1399system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30701.370831 # average ReadReq miss latency
1400system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17779.598261 # average UpgradeReq miss latency
1401system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17779.598261 # average UpgradeReq miss latency
1402system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19776.822851 # average SCUpgradeReq miss latency
1403system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19776.822851 # average SCUpgradeReq miss latency
|
875system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.171998 # miss rate for ReadExReq accesses 876system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171998 # miss rate for ReadExReq accesses 877system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for demand accesses 878system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.038955 # miss rate for demand accesses 879system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051075 # miss rate for demand accesses 880system.cpu0.l2cache.demand_miss_rate::total 0.049986 # miss rate for demand accesses 881system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for overall accesses 882system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.038955 # miss rate for overall accesses 883system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051075 # miss rate for overall accesses 884system.cpu0.l2cache.overall_miss_rate::total 0.049986 # miss rate for overall accesses 885system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average ReadReq miss latency 886system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22254.329480 # average ReadReq miss latency 887system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30680.657212 # average ReadReq miss latency 888system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30686.446387 # average ReadReq miss latency 889system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17797.163595 # average UpgradeReq miss latency 890system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17797.163595 # average UpgradeReq miss latency 891system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19759.312785 # average SCUpgradeReq miss latency 892system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19759.312785 # average SCUpgradeReq miss latency |
893system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 58500 # average SCUpgradeFailReq miss latency 894system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 58500 # average SCUpgradeFailReq miss latency
|
1406system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41563.911398 # average ReadExReq miss latency
1407system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41563.911398 # average ReadExReq miss latency
1408system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average overall miss latency
1409system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22325.295181 # average overall miss latency
1410system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34278.846992 # average overall miss latency
1411system.cpu0.l2cache.demand_avg_miss_latency::total 34255.417107 # average overall miss latency
1412system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average overall miss latency
1413system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22325.295181 # average overall miss latency
1414system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34278.846992 # average overall miss latency
1415system.cpu0.l2cache.overall_avg_miss_latency::total 34255.417107 # average overall miss latency
1416system.cpu0.l2cache.blocked_cycles::no_mshrs 26197 # number of cycles access was blocked
|
895system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41544.695353 # average ReadExReq miss latency 896system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41544.695353 # average ReadExReq miss latency 897system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average overall miss latency 898system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22254.329480 # average overall miss latency 899system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34259.867947 # average overall miss latency 900system.cpu0.l2cache.demand_avg_miss_latency::total 34234.521537 # average overall miss latency 901system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average overall miss latency 902system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22254.329480 # average overall miss latency 903system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34259.867947 # average overall miss latency 904system.cpu0.l2cache.overall_avg_miss_latency::total 34234.521537 # average overall miss latency 905system.cpu0.l2cache.blocked_cycles::no_mshrs 25463 # number of cycles access was blocked |
906system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
1418system.cpu0.l2cache.blocked::no_mshrs 374 # number of cycles access was blocked
|
907system.cpu0.l2cache.blocked::no_mshrs 375 # number of cycles access was blocked |
908system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
1420system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 70.045455 # average number of cycles each access was blocked
|
909system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 67.901333 # average number of cycles each access was blocked |
910system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 911system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 912system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
1424system.cpu0.l2cache.writebacks::writebacks 214192 # number of writebacks
1425system.cpu0.l2cache.writebacks::total 214192 # number of writebacks
1426system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7707 # number of ReadReq MSHR hits
1427system.cpu0.l2cache.ReadReq_mshr_hits::total 7707 # number of ReadReq MSHR hits
1428system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3080 # number of ReadExReq MSHR hits
1429system.cpu0.l2cache.ReadExReq_mshr_hits::total 3080 # number of ReadExReq MSHR hits
1430system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10787 # number of demand (read+write) MSHR hits
1431system.cpu0.l2cache.demand_mshr_hits::total 10787 # number of demand (read+write) MSHR hits
1432system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10787 # number of overall MSHR hits
1433system.cpu0.l2cache.overall_mshr_hits::total 10787 # number of overall MSHR hits
1434system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 970 # number of ReadReq MSHR misses
1435system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 166 # number of ReadReq MSHR misses
1436system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86524 # number of ReadReq MSHR misses
1437system.cpu0.l2cache.ReadReq_mshr_misses::total 87660 # number of ReadReq MSHR misses
1438system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 512085 # number of HardPFReq MSHR misses
1439system.cpu0.l2cache.HardPFReq_mshr_misses::total 512085 # number of HardPFReq MSHR misses
1440system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27951 # number of UpgradeReq MSHR misses
1441system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27951 # number of UpgradeReq MSHR misses
1442system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17951 # number of SCUpgradeReq MSHR misses
1443system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17951 # number of SCUpgradeReq MSHR misses
|
913system.cpu0.l2cache.writebacks::writebacks 214094 # number of writebacks 914system.cpu0.l2cache.writebacks::total 214094 # number of writebacks 915system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7763 # number of ReadReq MSHR hits 916system.cpu0.l2cache.ReadReq_mshr_hits::total 7763 # number of ReadReq MSHR hits 917system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3115 # number of ReadExReq MSHR hits 918system.cpu0.l2cache.ReadExReq_mshr_hits::total 3115 # number of ReadExReq MSHR hits 919system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10878 # number of demand (read+write) MSHR hits 920system.cpu0.l2cache.demand_mshr_hits::total 10878 # number of demand (read+write) MSHR hits 921system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10878 # number of overall MSHR hits 922system.cpu0.l2cache.overall_mshr_hits::total 10878 # number of overall MSHR hits 923system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 986 # number of ReadReq MSHR misses 924system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses 925system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86578 # number of ReadReq MSHR misses 926system.cpu0.l2cache.ReadReq_mshr_misses::total 87737 # number of ReadReq MSHR misses 927system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 512278 # number of HardPFReq MSHR misses 928system.cpu0.l2cache.HardPFReq_mshr_misses::total 512278 # number of HardPFReq MSHR misses 929system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27941 # number of UpgradeReq MSHR misses 930system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27941 # number of UpgradeReq MSHR misses 931system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17958 # number of SCUpgradeReq MSHR misses 932system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17958 # number of SCUpgradeReq MSHR misses |
933system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 2 # number of SCUpgradeFailReq MSHR misses 934system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
|
1446system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43296 # number of ReadExReq MSHR misses
1447system.cpu0.l2cache.ReadExReq_mshr_misses::total 43296 # number of ReadExReq MSHR misses
1448system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 970 # number of demand (read+write) MSHR misses
1449system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 166 # number of demand (read+write) MSHR misses
1450system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 129820 # number of demand (read+write) MSHR misses
1451system.cpu0.l2cache.demand_mshr_misses::total 130956 # number of demand (read+write) MSHR misses
1452system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 970 # number of overall MSHR misses
1453system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 166 # number of overall MSHR misses
1454system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 129820 # number of overall MSHR misses
1455system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 512085 # number of overall MSHR misses
1456system.cpu0.l2cache.overall_mshr_misses::total 643041 # number of overall MSHR misses
1457system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of ReadReq MSHR miss cycles
1458system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2543999 # number of ReadReq MSHR miss cycles
1459system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2121731252 # number of ReadReq MSHR miss cycles
1460system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2149385000 # number of ReadReq MSHR miss cycles
1461system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21314968847 # number of HardPFReq MSHR miss cycles
1462system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21314968847 # number of HardPFReq MSHR miss cycles
1463system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 476593305 # number of UpgradeReq MSHR miss cycles
1464system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 476593305 # number of UpgradeReq MSHR miss cycles
1465system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 237494522 # number of SCUpgradeReq MSHR miss cycles
1466system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 237494522 # number of SCUpgradeReq MSHR miss cycles
|
935system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43237 # number of ReadExReq MSHR misses 936system.cpu0.l2cache.ReadExReq_mshr_misses::total 43237 # number of ReadExReq MSHR misses 937system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 986 # number of demand (read+write) MSHR misses 938system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses 939system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 129815 # number of demand (read+write) MSHR misses 940system.cpu0.l2cache.demand_mshr_misses::total 130974 # number of demand (read+write) MSHR misses 941system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 986 # number of overall MSHR misses 942system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses 943system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 129815 # number of overall MSHR misses 944system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 512278 # number of overall MSHR misses 945system.cpu0.l2cache.overall_mshr_misses::total 643252 # number of overall MSHR misses 946system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of ReadReq MSHR miss cycles 947system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2638999 # number of ReadReq MSHR miss cycles 948system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2121502252 # number of ReadReq MSHR miss cycles 949system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2149486002 # number of ReadReq MSHR miss cycles 950system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21334624793 # number of HardPFReq MSHR miss cycles 951system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21334624793 # number of HardPFReq MSHR miss cycles 952system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 476101816 # number of UpgradeReq MSHR miss cycles 953system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 476101816 # number of UpgradeReq MSHR miss cycles 954system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 237455029 # number of SCUpgradeReq MSHR miss cycles 955system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 237455029 # number of SCUpgradeReq MSHR miss cycles |
956system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 89000 # number of SCUpgradeFailReq MSHR miss cycles 957system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 89000 # number of SCUpgradeFailReq MSHR miss cycles
|
1469system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1192659250 # number of ReadExReq MSHR miss cycles
1470system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1192659250 # number of ReadExReq MSHR miss cycles
1471system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of demand (read+write) MSHR miss cycles
1472system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2543999 # number of demand (read+write) MSHR miss cycles
1473system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3314390502 # number of demand (read+write) MSHR miss cycles
1474system.cpu0.l2cache.demand_mshr_miss_latency::total 3342044250 # number of demand (read+write) MSHR miss cycles
1475system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of overall MSHR miss cycles
1476system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2543999 # number of overall MSHR miss cycles
1477system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3314390502 # number of overall MSHR miss cycles
1478system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21314968847 # number of overall MSHR miss cycles
1479system.cpu0.l2cache.overall_mshr_miss_latency::total 24657013097 # number of overall MSHR miss cycles
1480system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6176307748 # number of ReadReq MSHR uncacheable cycles
1481system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6176307748 # number of ReadReq MSHR uncacheable cycles
1482system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4587485503 # number of WriteReq MSHR uncacheable cycles
1483system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4587485503 # number of WriteReq MSHR uncacheable cycles
1484system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10763793251 # number of overall MSHR uncacheable cycles
1485system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10763793251 # number of overall MSHR uncacheable cycles
1486system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for ReadReq accesses
1487system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for ReadReq accesses
1488system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034820 # mshr miss rate for ReadReq accesses
1489system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034139 # mshr miss rate for ReadReq accesses
|
958system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1189409987 # number of ReadExReq MSHR miss cycles 959system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1189409987 # number of ReadExReq MSHR miss cycles 960system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of demand (read+write) MSHR miss cycles 961system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2638999 # number of demand (read+write) MSHR miss cycles 962system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3310912239 # number of demand (read+write) MSHR miss cycles 963system.cpu0.l2cache.demand_mshr_miss_latency::total 3338895989 # number of demand (read+write) MSHR miss cycles 964system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of overall MSHR miss cycles 965system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2638999 # number of overall MSHR miss cycles 966system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3310912239 # number of overall MSHR miss cycles 967system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21334624793 # number of overall MSHR miss cycles 968system.cpu0.l2cache.overall_mshr_miss_latency::total 24673520782 # number of overall MSHR miss cycles 969system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6176243748 # number of ReadReq MSHR uncacheable cycles 970system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6176243748 # number of ReadReq MSHR uncacheable cycles 971system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4587514507 # number of WriteReq MSHR uncacheable cycles 972system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4587514507 # number of WriteReq MSHR uncacheable cycles 973system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10763758255 # number of overall MSHR uncacheable cycles 974system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10763758255 # number of overall MSHR uncacheable cycles 975system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for ReadReq accesses 976system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for ReadReq accesses 977system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034839 # mshr miss rate for ReadReq accesses 978system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034161 # mshr miss rate for ReadReq accesses |
979system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 980system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
1492system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856683 # mshr miss rate for UpgradeReq accesses
1493system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856683 # mshr miss rate for UpgradeReq accesses
1494system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.886557 # mshr miss rate for SCUpgradeReq accesses
1495system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.886557 # mshr miss rate for SCUpgradeReq accesses
|
981system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.857849 # mshr miss rate for UpgradeReq accesses 982system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.857849 # mshr miss rate for UpgradeReq accesses 983system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888922 # mshr miss rate for SCUpgradeReq accesses 984system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888922 # mshr miss rate for SCUpgradeReq accesses |
985system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 986system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
|
1498system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160660 # mshr miss rate for ReadExReq accesses
1499system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160660 # mshr miss rate for ReadExReq accesses
1500system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for demand accesses
1501system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for demand accesses
1502system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for demand accesses
1503system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046156 # mshr miss rate for demand accesses
1504system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for overall accesses
1505system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for overall accesses
1506system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for overall accesses
|
987system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160439 # mshr miss rate for ReadExReq accesses 988system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160439 # mshr miss rate for ReadExReq accesses 989system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for demand accesses 990system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for demand accesses 991system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for demand accesses 992system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046153 # mshr miss rate for demand accesses 993system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for overall accesses 994system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for overall accesses 995system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for overall accesses |
996system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
1508system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226643 # mshr miss rate for overall accesses
1509system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average ReadReq mshr miss latency
1510system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average ReadReq mshr miss latency
1511system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24521.881235 # average ReadReq mshr miss latency
1512system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24519.564225 # average ReadReq mshr miss latency
1513system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average HardPFReq mshr miss latency
1514system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41623.888313 # average HardPFReq mshr miss latency
1515system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17051.028765 # average UpgradeReq mshr miss latency
1516system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17051.028765 # average UpgradeReq mshr miss latency
1517system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13230.155535 # average SCUpgradeReq mshr miss latency
1518system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13230.155535 # average SCUpgradeReq mshr miss latency
|
997system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226671 # mshr miss rate for overall accesses 998system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average ReadReq mshr miss latency 999system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average ReadReq mshr miss latency 1000system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24503.941556 # average ReadReq mshr miss latency 1001system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24499.196485 # average ReadReq mshr miss latency 1002system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average HardPFReq mshr miss latency 1003system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41646.576259 # average HardPFReq mshr miss latency 1004system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17039.541033 # average UpgradeReq mshr miss latency 1005system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17039.541033 # average UpgradeReq mshr miss latency 1006system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13222.799254 # average SCUpgradeReq mshr miss latency 1007system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13222.799254 # average SCUpgradeReq mshr miss latency |
1008system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 44500 # average SCUpgradeFailReq mshr miss latency 1009system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 44500 # average SCUpgradeFailReq mshr miss latency
|
1521system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27546.638258 # average ReadExReq mshr miss latency
1522system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27546.638258 # average ReadExReq mshr miss latency
1523system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency
1524system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency
1525system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency
1526system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25520.359892 # average overall mshr miss latency
1527system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency
1528system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency
1529system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency
1530system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average overall mshr miss latency
1531system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38344.387212 # average overall mshr miss latency
|
1010system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27509.077572 # average ReadExReq mshr miss latency 1011system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27509.077572 # average ReadExReq mshr miss latency 1012system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency 1013system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency 1014system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency 1015system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25492.815284 # average overall mshr miss latency 1016system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency 1017system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency 1018system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency 1019system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average overall mshr miss latency 1020system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38357.472316 # average overall mshr miss latency |
1021system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1022system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1023system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1024system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1025system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1026system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1027system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
1539system.cpu0.dcache.tags.replacements 714989 # number of replacements
1540system.cpu0.dcache.tags.tagsinuse 494.379861 # Cycle average of tags in use
1541system.cpu0.dcache.tags.total_refs 40475201 # Total number of references to valid blocks.
1542system.cpu0.dcache.tags.sampled_refs 715501 # Sample count of references to valid blocks.
1543system.cpu0.dcache.tags.avg_refs 56.569035 # Average number of references to valid blocks.
1544system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit.
1545system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.379861 # Average occupied blocks per requestor
1546system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965586 # Average percentage of cache occupancy
1547system.cpu0.dcache.tags.occ_percent::total 0.965586 # Average percentage of cache occupancy
1548system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1549system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
1550system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
1551system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1552system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1553system.cpu0.dcache.tags.tag_accesses 83786238 # Number of tag accesses
1554system.cpu0.dcache.tags.data_accesses 83786238 # Number of data accesses
1555system.cpu0.dcache.ReadReq_hits::cpu0.inst 22803865 # number of ReadReq hits
1556system.cpu0.dcache.ReadReq_hits::total 22803865 # number of ReadReq hits
1557system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862785 # number of WriteReq hits
1558system.cpu0.dcache.WriteReq_hits::total 16862785 # number of WriteReq hits
1559system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381543 # number of LoadLockedReq hits
1560system.cpu0.dcache.LoadLockedReq_hits::total 381543 # number of LoadLockedReq hits
1561system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362585 # number of StoreCondReq hits
1562system.cpu0.dcache.StoreCondReq_hits::total 362585 # number of StoreCondReq hits
1563system.cpu0.dcache.demand_hits::cpu0.inst 39666650 # number of demand (read+write) hits
1564system.cpu0.dcache.demand_hits::total 39666650 # number of demand (read+write) hits
1565system.cpu0.dcache.overall_hits::cpu0.inst 39666650 # number of overall hits
1566system.cpu0.dcache.overall_hits::total 39666650 # number of overall hits
1567system.cpu0.dcache.ReadReq_misses::cpu0.inst 537471 # number of ReadReq misses
1568system.cpu0.dcache.ReadReq_misses::total 537471 # number of ReadReq misses
1569system.cpu0.dcache.WriteReq_misses::cpu0.inst 532850 # number of WriteReq misses
1570system.cpu0.dcache.WriteReq_misses::total 532850 # number of WriteReq misses
1571system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6422 # number of LoadLockedReq misses
1572system.cpu0.dcache.LoadLockedReq_misses::total 6422 # number of LoadLockedReq misses
1573system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20250 # number of StoreCondReq misses
1574system.cpu0.dcache.StoreCondReq_misses::total 20250 # number of StoreCondReq misses
1575system.cpu0.dcache.demand_misses::cpu0.inst 1070321 # number of demand (read+write) misses
1576system.cpu0.dcache.demand_misses::total 1070321 # number of demand (read+write) misses
1577system.cpu0.dcache.overall_misses::cpu0.inst 1070321 # number of overall misses
1578system.cpu0.dcache.overall_misses::total 1070321 # number of overall misses
1579system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609205728 # number of ReadReq miss cycles
1580system.cpu0.dcache.ReadReq_miss_latency::total 6609205728 # number of ReadReq miss cycles
1581system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8024129751 # number of WriteReq miss cycles
1582system.cpu0.dcache.WriteReq_miss_latency::total 8024129751 # number of WriteReq miss cycles
1583system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 106247249 # number of LoadLockedReq miss cycles
1584system.cpu0.dcache.LoadLockedReq_miss_latency::total 106247249 # number of LoadLockedReq miss cycles
1585system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 438093543 # number of StoreCondReq miss cycles
1586system.cpu0.dcache.StoreCondReq_miss_latency::total 438093543 # number of StoreCondReq miss cycles
1587system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles
1588system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles
1589system.cpu0.dcache.demand_miss_latency::cpu0.inst 14633335479 # number of demand (read+write) miss cycles
1590system.cpu0.dcache.demand_miss_latency::total 14633335479 # number of demand (read+write) miss cycles
1591system.cpu0.dcache.overall_miss_latency::cpu0.inst 14633335479 # number of overall miss cycles
1592system.cpu0.dcache.overall_miss_latency::total 14633335479 # number of overall miss cycles
1593system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23341336 # number of ReadReq accesses(hits+misses)
1594system.cpu0.dcache.ReadReq_accesses::total 23341336 # number of ReadReq accesses(hits+misses)
1595system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395635 # number of WriteReq accesses(hits+misses)
1596system.cpu0.dcache.WriteReq_accesses::total 17395635 # number of WriteReq accesses(hits+misses)
1597system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387965 # number of LoadLockedReq accesses(hits+misses)
1598system.cpu0.dcache.LoadLockedReq_accesses::total 387965 # number of LoadLockedReq accesses(hits+misses)
1599system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382835 # number of StoreCondReq accesses(hits+misses)
1600system.cpu0.dcache.StoreCondReq_accesses::total 382835 # number of StoreCondReq accesses(hits+misses)
1601system.cpu0.dcache.demand_accesses::cpu0.inst 40736971 # number of demand (read+write) accesses
1602system.cpu0.dcache.demand_accesses::total 40736971 # number of demand (read+write) accesses
1603system.cpu0.dcache.overall_accesses::cpu0.inst 40736971 # number of overall (read+write) accesses
1604system.cpu0.dcache.overall_accesses::total 40736971 # number of overall (read+write) accesses
1605system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023027 # miss rate for ReadReq accesses
1606system.cpu0.dcache.ReadReq_miss_rate::total 0.023027 # miss rate for ReadReq accesses
1607system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030631 # miss rate for WriteReq accesses
1608system.cpu0.dcache.WriteReq_miss_rate::total 0.030631 # miss rate for WriteReq accesses
1609system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016553 # miss rate for LoadLockedReq accesses
1610system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016553 # miss rate for LoadLockedReq accesses
1611system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052895 # miss rate for StoreCondReq accesses
1612system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052895 # miss rate for StoreCondReq accesses
1613system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026274 # miss rate for demand accesses
1614system.cpu0.dcache.demand_miss_rate::total 0.026274 # miss rate for demand accesses
1615system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026274 # miss rate for overall accesses
1616system.cpu0.dcache.overall_miss_rate::total 0.026274 # miss rate for overall accesses
1617system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12296.860162 # average ReadReq miss latency
1618system.cpu0.dcache.ReadReq_avg_miss_latency::total 12296.860162 # average ReadReq miss latency
1619system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15058.890403 # average WriteReq miss latency
1620system.cpu0.dcache.WriteReq_avg_miss_latency::total 15058.890403 # average WriteReq miss latency
1621system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16544.261756 # average LoadLockedReq miss latency
1622system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16544.261756 # average LoadLockedReq miss latency
1623system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21634.249037 # average StoreCondReq miss latency
1624system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21634.249037 # average StoreCondReq miss latency
1625system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency
1626system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1627system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency
1628system.cpu0.dcache.demand_avg_miss_latency::total 13671.912892 # average overall miss latency
1629system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency
1630system.cpu0.dcache.overall_avg_miss_latency::total 13671.912892 # average overall miss latency
1631system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1632system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1633system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1634system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1635system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1636system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1637system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1638system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1639system.cpu0.dcache.writebacks::writebacks 518095 # number of writebacks
1640system.cpu0.dcache.writebacks::total 518095 # number of writebacks
1641system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42683 # number of ReadReq MSHR hits
1642system.cpu0.dcache.ReadReq_mshr_hits::total 42683 # number of ReadReq MSHR hits
1643system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230741 # number of WriteReq MSHR hits
1644system.cpu0.dcache.WriteReq_mshr_hits::total 230741 # number of WriteReq MSHR hits
1645system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits
1646system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits
1647system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273424 # number of demand (read+write) MSHR hits
1648system.cpu0.dcache.demand_mshr_hits::total 273424 # number of demand (read+write) MSHR hits
1649system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273424 # number of overall MSHR hits
1650system.cpu0.dcache.overall_mshr_hits::total 273424 # number of overall MSHR hits
1651system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494788 # number of ReadReq MSHR misses
1652system.cpu0.dcache.ReadReq_mshr_misses::total 494788 # number of ReadReq MSHR misses
1653system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302109 # number of WriteReq MSHR misses
1654system.cpu0.dcache.WriteReq_mshr_misses::total 302109 # number of WriteReq MSHR misses
1655system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6421 # number of LoadLockedReq MSHR misses
1656system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6421 # number of LoadLockedReq MSHR misses
1657system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20250 # number of StoreCondReq MSHR misses
1658system.cpu0.dcache.StoreCondReq_mshr_misses::total 20250 # number of StoreCondReq MSHR misses
1659system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796897 # number of demand (read+write) MSHR misses
1660system.cpu0.dcache.demand_mshr_misses::total 796897 # number of demand (read+write) MSHR misses
1661system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796897 # number of overall MSHR misses
1662system.cpu0.dcache.overall_mshr_misses::total 796897 # number of overall MSHR misses
1663system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5118044180 # number of ReadReq MSHR miss cycles
1664system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5118044180 # number of ReadReq MSHR miss cycles
1665system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4273159157 # number of WriteReq MSHR miss cycles
1666system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4273159157 # number of WriteReq MSHR miss cycles
1667system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 93352250 # number of LoadLockedReq MSHR miss cycles
1668system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93352250 # number of LoadLockedReq MSHR miss cycles
1669system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 397142457 # number of StoreCondReq MSHR miss cycles
1670system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397142457 # number of StoreCondReq MSHR miss cycles
1671system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles
1672system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles
1673system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9391203337 # number of demand (read+write) MSHR miss cycles
1674system.cpu0.dcache.demand_mshr_miss_latency::total 9391203337 # number of demand (read+write) MSHR miss cycles
1675system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9391203337 # number of overall MSHR miss cycles
1676system.cpu0.dcache.overall_mshr_miss_latency::total 9391203337 # number of overall MSHR miss cycles
1677system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191390497 # number of ReadReq MSHR uncacheable cycles
1678system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191390497 # number of ReadReq MSHR uncacheable cycles
1679system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803718496 # number of WriteReq MSHR uncacheable cycles
1680system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803718496 # number of WriteReq MSHR uncacheable cycles
1681system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995108993 # number of overall MSHR uncacheable cycles
1682system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995108993 # number of overall MSHR uncacheable cycles
1683system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021198 # mshr miss rate for ReadReq accesses
1684system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021198 # mshr miss rate for ReadReq accesses
1685system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017367 # mshr miss rate for WriteReq accesses
1686system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017367 # mshr miss rate for WriteReq accesses
1687system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016550 # mshr miss rate for LoadLockedReq accesses
1688system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016550 # mshr miss rate for LoadLockedReq accesses
1689system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052895 # mshr miss rate for StoreCondReq accesses
1690system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052895 # mshr miss rate for StoreCondReq accesses
1691system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for demand accesses
1692system.cpu0.dcache.demand_mshr_miss_rate::total 0.019562 # mshr miss rate for demand accesses
1693system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for overall accesses
1694system.cpu0.dcache.overall_mshr_miss_rate::total 0.019562 # mshr miss rate for overall accesses
1695system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10343.913312 # average ReadReq mshr miss latency
1696system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10343.913312 # average ReadReq mshr miss latency
1697system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14144.428524 # average WriteReq mshr miss latency
1698system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14144.428524 # average WriteReq mshr miss latency
1699system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14538.584333 # average LoadLockedReq mshr miss latency
1700system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14538.584333 # average LoadLockedReq mshr miss latency
1701system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19611.973185 # average StoreCondReq mshr miss latency
1702system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19611.973185 # average StoreCondReq mshr miss latency
1703system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency
1704system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1705system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency
1706system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency
1707system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency
1708system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency
1709system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1710system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1711system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
1712system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1713system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1714system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1715system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1716system.cpu1.branchPred.lookups 4041852 # Number of BP lookups
1717system.cpu1.branchPred.condPredicted 2340524 # Number of conditional branches predicted
1718system.cpu1.branchPred.condIncorrect 248983 # Number of conditional branches incorrect
1719system.cpu1.branchPred.BTBLookups 2647417 # Number of BTB lookups
1720system.cpu1.branchPred.BTBHits 1629039 # Number of BTB hits
|
1028system.cpu0.toL2Bus.trans_dist::ReadReq 2765429 # Transaction distribution 1029system.cpu0.toL2Bus.trans_dist::ReadResp 2670282 # Transaction distribution 1030system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution 1031system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution 1032system.cpu0.toL2Bus.trans_dist::Writeback 517951 # Transaction distribution 1033system.cpu0.toL2Bus.trans_dist::HardPFReq 696439 # Transaction distribution 1034system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 1035system.cpu0.toL2Bus.trans_dist::UpgradeReq 70465 # Transaction distribution 1036system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42615 # Transaction distribution 1037system.cpu0.toL2Bus.trans_dist::UpgradeResp 93717 # Transaction distribution 1038system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 1039system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution 1040system.cpu0.toL2Bus.trans_dist::ReadExReq 291656 # Transaction distribution 1041system.cpu0.toL2Bus.trans_dist::ReadExResp 282057 # Transaction distribution 1042system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3974309 # Packet count per connected master and slave (bytes) 1043system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393187 # Packet count per connected master and slave (bytes) 1044system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11845 # Packet count per connected master and slave (bytes) 1045system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168040 # Packet count per connected master and slave (bytes) 1046system.cpu0.toL2Bus.pkt_count::total 6547381 # Packet count per connected master and slave (bytes) 1047system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127177856 # Cumulative packet size per connected master and slave (bytes) 1048system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86874167 # Cumulative packet size per connected master and slave (bytes) 1049system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17764 # Cumulative packet size per connected master and slave (bytes) 1050system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 315068 # Cumulative packet size per connected master and slave (bytes) 1051system.cpu0.toL2Bus.pkt_size::total 214384855 # Cumulative packet size per connected master and slave (bytes) 1052system.cpu0.toL2Bus.snoops 1083965 # Total snoops (count) 1053system.cpu0.toL2Bus.snoop_fanout::samples 4385734 # Request fanout histogram 1054system.cpu0.toL2Bus.snoop_fanout::mean 5.219720 # Request fanout histogram 1055system.cpu0.toL2Bus.snoop_fanout::stdev 0.414057 # Request fanout histogram 1056system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1057system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1058system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1059system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1060system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1061system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1062system.cpu0.toL2Bus.snoop_fanout::5 3422100 78.03% 78.03% # Request fanout histogram 1063system.cpu0.toL2Bus.snoop_fanout::6 963634 21.97% 100.00% # Request fanout histogram 1064system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1065system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1066system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1067system.cpu0.toL2Bus.snoop_fanout::total 4385734 # Request fanout histogram 1068system.cpu0.toL2Bus.reqLayer0.occupancy 2275890990 # Layer occupancy (ticks) 1069system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1070system.cpu0.toL2Bus.snoopLayer0.occupancy 119346000 # Layer occupancy (ticks) 1071system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1072system.cpu0.toL2Bus.respLayer0.occupancy 2982392646 # Layer occupancy (ticks) 1073system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1074system.cpu0.toL2Bus.respLayer1.occupancy 1235371968 # Layer occupancy (ticks) 1075system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1076system.cpu0.toL2Bus.respLayer2.occupancy 7407493 # Layer occupancy (ticks) 1077system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1078system.cpu0.toL2Bus.respLayer3.occupancy 89292476 # Layer occupancy (ticks) 1079system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1080system.cpu1.branchPred.lookups 4040174 # Number of BP lookups 1081system.cpu1.branchPred.condPredicted 2339682 # Number of conditional branches predicted 1082system.cpu1.branchPred.condIncorrect 248924 # Number of conditional branches incorrect 1083system.cpu1.branchPred.BTBLookups 2652147 # Number of BTB lookups 1084system.cpu1.branchPred.BTBHits 1629183 # Number of BTB hits |
1085system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
1722system.cpu1.branchPred.BTBHitPct 61.533147 # BTB Hit Percentage
1723system.cpu1.branchPred.usedRAS 795039 # Number of times the RAS was used to get a target.
1724system.cpu1.branchPred.RASInCorrect 55831 # Number of incorrect RAS predictions.
|
1086system.cpu1.branchPred.BTBHitPct 61.428835 # BTB Hit Percentage 1087system.cpu1.branchPred.usedRAS 794888 # Number of times the RAS was used to get a target. 1088system.cpu1.branchPred.RASInCorrect 55483 # Number of incorrect RAS predictions. |
1089system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1090system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1091system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1092system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1093system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1094system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1095system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1096system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1097system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1098system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1099system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1100system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1101system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1102system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1103system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1104system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1105system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1106system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1107system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1108system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1109system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1110system.cpu1.dtb.inst_hits 0 # ITB inst hits 1111system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
1748system.cpu1.dtb.read_hits 4061119 # DTB read hits
1749system.cpu1.dtb.read_misses 20366 # DTB read misses
1750system.cpu1.dtb.write_hits 3327004 # DTB write hits
1751system.cpu1.dtb.write_misses 1507 # DTB write misses
|
1112system.cpu1.dtb.read_hits 4061400 # DTB read hits 1113system.cpu1.dtb.read_misses 20326 # DTB read misses 1114system.cpu1.dtb.write_hits 3327397 # DTB write hits 1115system.cpu1.dtb.write_misses 1493 # DTB write misses |
1116system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1117system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1118system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1119system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
1756system.cpu1.dtb.flush_entries 2038 # Number of entries that have been flushed from TLB
1757system.cpu1.dtb.align_faults 134 # Number of TLB faults due to alignment restrictions
1758system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch
|
1120system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB 1121system.cpu1.dtb.align_faults 130 # Number of TLB faults due to alignment restrictions 1122system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch |
1123system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1124system.cpu1.dtb.perms_faults 275 # Number of TLB faults due to permissions restrictions
|
1761system.cpu1.dtb.read_accesses 4081485 # DTB read accesses
1762system.cpu1.dtb.write_accesses 3328511 # DTB write accesses
|
1125system.cpu1.dtb.read_accesses 4081726 # DTB read accesses 1126system.cpu1.dtb.write_accesses 3328890 # DTB write accesses |
1127system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
1764system.cpu1.dtb.hits 7388123 # DTB hits
1765system.cpu1.dtb.misses 21873 # DTB misses
1766system.cpu1.dtb.accesses 7409996 # DTB accesses
|
1128system.cpu1.dtb.hits 7388797 # DTB hits 1129system.cpu1.dtb.misses 21819 # DTB misses 1130system.cpu1.dtb.accesses 7410616 # DTB accesses |
1131system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1132system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1133system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1134system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1135system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1136system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1137system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1138system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1139system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1140system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1141system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1142system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1143system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1144system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1145system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1146system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1147system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1148system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1149system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1150system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1151system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
1788system.cpu1.itb.inst_hits 7667797 # ITB inst hits
1789system.cpu1.itb.inst_misses 2228 # ITB inst misses
|
1152system.cpu1.itb.inst_hits 7665717 # ITB inst hits 1153system.cpu1.itb.inst_misses 2240 # ITB inst misses |
1154system.cpu1.itb.read_hits 0 # DTB read hits 1155system.cpu1.itb.read_misses 0 # DTB read misses 1156system.cpu1.itb.write_hits 0 # DTB write hits 1157system.cpu1.itb.write_misses 0 # DTB write misses 1158system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1159system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1160system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1161system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
1798system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB
|
1162system.cpu1.itb.flush_entries 1155 # Number of entries that have been flushed from TLB |
1163system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1164system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1165system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
1802system.cpu1.itb.perms_faults 1890 # Number of TLB faults due to permissions restrictions
|
1166system.cpu1.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions |
1167system.cpu1.itb.read_accesses 0 # DTB read accesses 1168system.cpu1.itb.write_accesses 0 # DTB write accesses
|
1805system.cpu1.itb.inst_accesses 7670025 # ITB inst accesses
1806system.cpu1.itb.hits 7667797 # DTB hits
1807system.cpu1.itb.misses 2228 # DTB misses
1808system.cpu1.itb.accesses 7670025 # DTB accesses
1809system.cpu1.numCycles 40526065 # number of cpu cycles simulated
|
1169system.cpu1.itb.inst_accesses 7667957 # ITB inst accesses 1170system.cpu1.itb.hits 7665717 # DTB hits 1171system.cpu1.itb.misses 2240 # DTB misses 1172system.cpu1.itb.accesses 7667957 # DTB accesses 1173system.cpu1.numCycles 40520229 # number of cpu cycles simulated |
1174system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1175system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
1812system.cpu1.committedInsts 15860183 # Number of instructions committed
1813system.cpu1.committedOps 19387635 # Number of ops (including micro ops) committed
1814system.cpu1.discardedOps 1556469 # Number of ops (including micro ops) which were discarded before commit
1815system.cpu1.numFetchSuspends 2802 # Number of times Execute suspended instruction fetching
1816system.cpu1.quiesceCycles 5646205885 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1817system.cpu1.cpi 2.555208 # CPI: cycles per instruction
1818system.cpu1.ipc 0.391358 # IPC: instructions per cycle
|
1176system.cpu1.committedInsts 15863154 # Number of instructions committed 1177system.cpu1.committedOps 19391289 # Number of ops (including micro ops) committed 1178system.cpu1.discardedOps 1555006 # Number of ops (including micro ops) which were discarded before commit 1179system.cpu1.numFetchSuspends 2808 # Number of times Execute suspended instruction fetching 1180system.cpu1.quiesceCycles 5646190749 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1181system.cpu1.cpi 2.554361 # CPI: cycles per instruction 1182system.cpu1.ipc 0.391487 # IPC: instructions per cycle |
1183system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
1820system.cpu1.kern.inst.quiesce 2803 # number of quiesce instructions executed
1821system.cpu1.tickCycles 29467033 # Number of cycles that the object actually ticked
1822system.cpu1.idleCycles 11059032 # Total number of cycles that the object has spent stopped
1823system.cpu1.icache.tags.replacements 893075 # number of replacements
1824system.cpu1.icache.tags.tagsinuse 499.459055 # Cycle average of tags in use
1825system.cpu1.icache.tags.total_refs 6772156 # Total number of references to valid blocks.
1826system.cpu1.icache.tags.sampled_refs 893587 # Sample count of references to valid blocks.
1827system.cpu1.icache.tags.avg_refs 7.578620 # Average number of references to valid blocks.
|
1184system.cpu1.kern.inst.quiesce 2810 # number of quiesce instructions executed 1185system.cpu1.tickCycles 29462484 # Number of cycles that the object actually ticked 1186system.cpu1.idleCycles 11057745 # Total number of cycles that the object has spent stopped 1187system.cpu1.dcache.tags.replacements 188500 # number of replacements 1188system.cpu1.dcache.tags.tagsinuse 474.724355 # Cycle average of tags in use 1189system.cpu1.dcache.tags.total_refs 6998456 # Total number of references to valid blocks. 1190system.cpu1.dcache.tags.sampled_refs 188865 # Sample count of references to valid blocks. 1191system.cpu1.dcache.tags.avg_refs 37.055336 # Average number of references to valid blocks. 1192system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit. 1193system.cpu1.dcache.tags.occ_blocks::cpu1.inst 474.724355 # Average occupied blocks per requestor 1194system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927196 # Average percentage of cache occupancy 1195system.cpu1.dcache.tags.occ_percent::total 0.927196 # Average percentage of cache occupancy 1196system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 1197system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id 1198system.cpu1.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id 1199system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id 1200system.cpu1.dcache.tags.tag_accesses 14854828 # Number of tag accesses 1201system.cpu1.dcache.tags.data_accesses 14854828 # Number of data accesses 1202system.cpu1.dcache.ReadReq_hits::cpu1.inst 3752021 # number of ReadReq hits 1203system.cpu1.dcache.ReadReq_hits::total 3752021 # number of ReadReq hits 1204system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051608 # number of WriteReq hits 1205system.cpu1.dcache.WriteReq_hits::total 3051608 # number of WriteReq hits 1206system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88860 # number of LoadLockedReq hits 1207system.cpu1.dcache.LoadLockedReq_hits::total 88860 # number of LoadLockedReq hits 1208system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69213 # number of StoreCondReq hits 1209system.cpu1.dcache.StoreCondReq_hits::total 69213 # number of StoreCondReq hits 1210system.cpu1.dcache.demand_hits::cpu1.inst 6803629 # number of demand (read+write) hits 1211system.cpu1.dcache.demand_hits::total 6803629 # number of demand (read+write) hits 1212system.cpu1.dcache.overall_hits::cpu1.inst 6803629 # number of overall hits 1213system.cpu1.dcache.overall_hits::total 6803629 # number of overall hits 1214system.cpu1.dcache.ReadReq_misses::cpu1.inst 182037 # number of ReadReq misses 1215system.cpu1.dcache.ReadReq_misses::total 182037 # number of ReadReq misses 1216system.cpu1.dcache.WriteReq_misses::cpu1.inst 139457 # number of WriteReq misses 1217system.cpu1.dcache.WriteReq_misses::total 139457 # number of WriteReq misses 1218system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5164 # number of LoadLockedReq misses 1219system.cpu1.dcache.LoadLockedReq_misses::total 5164 # number of LoadLockedReq misses 1220system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23160 # number of StoreCondReq misses 1221system.cpu1.dcache.StoreCondReq_misses::total 23160 # number of StoreCondReq misses 1222system.cpu1.dcache.demand_misses::cpu1.inst 321494 # number of demand (read+write) misses 1223system.cpu1.dcache.demand_misses::total 321494 # number of demand (read+write) misses 1224system.cpu1.dcache.overall_misses::cpu1.inst 321494 # number of overall misses 1225system.cpu1.dcache.overall_misses::total 321494 # number of overall misses 1226system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2747896424 # number of ReadReq miss cycles 1227system.cpu1.dcache.ReadReq_miss_latency::total 2747896424 # number of ReadReq miss cycles 1228system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3339347493 # number of WriteReq miss cycles 1229system.cpu1.dcache.WriteReq_miss_latency::total 3339347493 # number of WriteReq miss cycles 1230system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93721501 # number of LoadLockedReq miss cycles 1231system.cpu1.dcache.LoadLockedReq_miss_latency::total 93721501 # number of LoadLockedReq miss cycles 1232system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540094758 # number of StoreCondReq miss cycles 1233system.cpu1.dcache.StoreCondReq_miss_latency::total 540094758 # number of StoreCondReq miss cycles 1234system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 317500 # number of StoreCondFailReq miss cycles 1235system.cpu1.dcache.StoreCondFailReq_miss_latency::total 317500 # number of StoreCondFailReq miss cycles 1236system.cpu1.dcache.demand_miss_latency::cpu1.inst 6087243917 # number of demand (read+write) miss cycles 1237system.cpu1.dcache.demand_miss_latency::total 6087243917 # number of demand (read+write) miss cycles 1238system.cpu1.dcache.overall_miss_latency::cpu1.inst 6087243917 # number of overall miss cycles 1239system.cpu1.dcache.overall_miss_latency::total 6087243917 # number of overall miss cycles 1240system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3934058 # number of ReadReq accesses(hits+misses) 1241system.cpu1.dcache.ReadReq_accesses::total 3934058 # number of ReadReq accesses(hits+misses) 1242system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3191065 # number of WriteReq accesses(hits+misses) 1243system.cpu1.dcache.WriteReq_accesses::total 3191065 # number of WriteReq accesses(hits+misses) 1244system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94024 # number of LoadLockedReq accesses(hits+misses) 1245system.cpu1.dcache.LoadLockedReq_accesses::total 94024 # number of LoadLockedReq accesses(hits+misses) 1246system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92373 # number of StoreCondReq accesses(hits+misses) 1247system.cpu1.dcache.StoreCondReq_accesses::total 92373 # number of StoreCondReq accesses(hits+misses) 1248system.cpu1.dcache.demand_accesses::cpu1.inst 7125123 # number of demand (read+write) accesses 1249system.cpu1.dcache.demand_accesses::total 7125123 # number of demand (read+write) accesses 1250system.cpu1.dcache.overall_accesses::cpu1.inst 7125123 # number of overall (read+write) accesses 1251system.cpu1.dcache.overall_accesses::total 7125123 # number of overall (read+write) accesses 1252system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046272 # miss rate for ReadReq accesses 1253system.cpu1.dcache.ReadReq_miss_rate::total 0.046272 # miss rate for ReadReq accesses 1254system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043702 # miss rate for WriteReq accesses 1255system.cpu1.dcache.WriteReq_miss_rate::total 0.043702 # miss rate for WriteReq accesses 1256system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054922 # miss rate for LoadLockedReq accesses 1257system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054922 # miss rate for LoadLockedReq accesses 1258system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250723 # miss rate for StoreCondReq accesses 1259system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250723 # miss rate for StoreCondReq accesses 1260system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045121 # miss rate for demand accesses 1261system.cpu1.dcache.demand_miss_rate::total 0.045121 # miss rate for demand accesses 1262system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045121 # miss rate for overall accesses 1263system.cpu1.dcache.overall_miss_rate::total 0.045121 # miss rate for overall accesses 1264system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15095.263183 # average ReadReq miss latency 1265system.cpu1.dcache.ReadReq_avg_miss_latency::total 15095.263183 # average ReadReq miss latency 1266system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23945.355866 # average WriteReq miss latency 1267system.cpu1.dcache.WriteReq_avg_miss_latency::total 23945.355866 # average WriteReq miss latency 1268system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18149.012587 # average LoadLockedReq miss latency 1269system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18149.012587 # average LoadLockedReq miss latency 1270system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23320.153627 # average StoreCondReq miss latency 1271system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23320.153627 # average StoreCondReq miss latency 1272system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 1273system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1274system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency 1275system.cpu1.dcache.demand_avg_miss_latency::total 18934.238017 # average overall miss latency 1276system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency 1277system.cpu1.dcache.overall_avg_miss_latency::total 18934.238017 # average overall miss latency 1278system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1279system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1280system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1281system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1282system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1283system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1284system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1285system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1286system.cpu1.dcache.writebacks::writebacks 115754 # number of writebacks 1287system.cpu1.dcache.writebacks::total 115754 # number of writebacks 1288system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15456 # number of ReadReq MSHR hits 1289system.cpu1.dcache.ReadReq_mshr_hits::total 15456 # number of ReadReq MSHR hits 1290system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49471 # number of WriteReq MSHR hits 1291system.cpu1.dcache.WriteReq_mshr_hits::total 49471 # number of WriteReq MSHR hits 1292system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64927 # number of demand (read+write) MSHR hits 1293system.cpu1.dcache.demand_mshr_hits::total 64927 # number of demand (read+write) MSHR hits 1294system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64927 # number of overall MSHR hits 1295system.cpu1.dcache.overall_mshr_hits::total 64927 # number of overall MSHR hits 1296system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166581 # number of ReadReq MSHR misses 1297system.cpu1.dcache.ReadReq_mshr_misses::total 166581 # number of ReadReq MSHR misses 1298system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89986 # number of WriteReq MSHR misses 1299system.cpu1.dcache.WriteReq_mshr_misses::total 89986 # number of WriteReq MSHR misses 1300system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5164 # number of LoadLockedReq MSHR misses 1301system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5164 # number of LoadLockedReq MSHR misses 1302system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23160 # number of StoreCondReq MSHR misses 1303system.cpu1.dcache.StoreCondReq_mshr_misses::total 23160 # number of StoreCondReq MSHR misses 1304system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256567 # number of demand (read+write) MSHR misses 1305system.cpu1.dcache.demand_mshr_misses::total 256567 # number of demand (read+write) MSHR misses 1306system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256567 # number of overall MSHR misses 1307system.cpu1.dcache.overall_mshr_misses::total 256567 # number of overall MSHR misses 1308system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204876516 # number of ReadReq MSHR miss cycles 1309system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204876516 # number of ReadReq MSHR miss cycles 1310system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1996537354 # number of WriteReq MSHR miss cycles 1311system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1996537354 # number of WriteReq MSHR miss cycles 1312system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83385499 # number of LoadLockedReq MSHR miss cycles 1313system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83385499 # number of LoadLockedReq MSHR miss cycles 1314system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492548242 # number of StoreCondReq MSHR miss cycles 1315system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492548242 # number of StoreCondReq MSHR miss cycles 1316system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 303500 # number of StoreCondFailReq MSHR miss cycles 1317system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 303500 # number of StoreCondFailReq MSHR miss cycles 1318system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4201413870 # number of demand (read+write) MSHR miss cycles 1319system.cpu1.dcache.demand_mshr_miss_latency::total 4201413870 # number of demand (read+write) MSHR miss cycles 1320system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4201413870 # number of overall MSHR miss cycles 1321system.cpu1.dcache.overall_mshr_miss_latency::total 4201413870 # number of overall MSHR miss cycles 1322system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329634997 # number of ReadReq MSHR uncacheable cycles 1323system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329634997 # number of ReadReq MSHR uncacheable cycles 1324system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202961999 # number of WriteReq MSHR uncacheable cycles 1325system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202961999 # number of WriteReq MSHR uncacheable cycles 1326system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532596996 # number of overall MSHR uncacheable cycles 1327system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532596996 # number of overall MSHR uncacheable cycles 1328system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042343 # mshr miss rate for ReadReq accesses 1329system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042343 # mshr miss rate for ReadReq accesses 1330system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028199 # mshr miss rate for WriteReq accesses 1331system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028199 # mshr miss rate for WriteReq accesses 1332system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054922 # mshr miss rate for LoadLockedReq accesses 1333system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054922 # mshr miss rate for LoadLockedReq accesses 1334system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250723 # mshr miss rate for StoreCondReq accesses 1335system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250723 # mshr miss rate for StoreCondReq accesses 1336system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for demand accesses 1337system.cpu1.dcache.demand_mshr_miss_rate::total 0.036009 # mshr miss rate for demand accesses 1338system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for overall accesses 1339system.cpu1.dcache.overall_mshr_miss_rate::total 0.036009 # mshr miss rate for overall accesses 1340system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13236.062432 # average ReadReq mshr miss latency 1341system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13236.062432 # average ReadReq mshr miss latency 1342system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22187.199720 # average WriteReq mshr miss latency 1343system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22187.199720 # average WriteReq mshr miss latency 1344system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16147.463013 # average LoadLockedReq mshr miss latency 1345system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.463013 # average LoadLockedReq mshr miss latency 1346system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21267.195250 # average StoreCondReq mshr miss latency 1347system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21267.195250 # average StoreCondReq mshr miss latency 1348system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 1349system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1350system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency 1351system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency 1352system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency 1353system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency 1354system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1355system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1356system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1357system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1358system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1359system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1360system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1361system.cpu1.icache.tags.replacements 893030 # number of replacements 1362system.cpu1.icache.tags.tagsinuse 499.459009 # Cycle average of tags in use 1363system.cpu1.icache.tags.total_refs 6770083 # Total number of references to valid blocks. 1364system.cpu1.icache.tags.sampled_refs 893542 # Sample count of references to valid blocks. 1365system.cpu1.icache.tags.avg_refs 7.576681 # Average number of references to valid blocks. |
1366system.cpu1.icache.tags.warmup_cycle 71221486500 # Cycle when the warmup percentage was hit.
|
1829system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459055 # Average occupied blocks per requestor
|
1367system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459009 # Average occupied blocks per requestor |
1368system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy 1369system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy 1370system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
1833system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id
1834system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
|
1371system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id 1372system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id |
1373system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
1836system.cpu1.icache.tags.tag_accesses 16225073 # Number of tag accesses
1837system.cpu1.icache.tags.data_accesses 16225073 # Number of data accesses
1838system.cpu1.icache.ReadReq_hits::cpu1.inst 6772156 # number of ReadReq hits
1839system.cpu1.icache.ReadReq_hits::total 6772156 # number of ReadReq hits
1840system.cpu1.icache.demand_hits::cpu1.inst 6772156 # number of demand (read+write) hits
1841system.cpu1.icache.demand_hits::total 6772156 # number of demand (read+write) hits
1842system.cpu1.icache.overall_hits::cpu1.inst 6772156 # number of overall hits
1843system.cpu1.icache.overall_hits::total 6772156 # number of overall hits
1844system.cpu1.icache.ReadReq_misses::cpu1.inst 893587 # number of ReadReq misses
1845system.cpu1.icache.ReadReq_misses::total 893587 # number of ReadReq misses
1846system.cpu1.icache.demand_misses::cpu1.inst 893587 # number of demand (read+write) misses
1847system.cpu1.icache.demand_misses::total 893587 # number of demand (read+write) misses
1848system.cpu1.icache.overall_misses::cpu1.inst 893587 # number of overall misses
1849system.cpu1.icache.overall_misses::total 893587 # number of overall misses
1850system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7266352748 # number of ReadReq miss cycles
1851system.cpu1.icache.ReadReq_miss_latency::total 7266352748 # number of ReadReq miss cycles
1852system.cpu1.icache.demand_miss_latency::cpu1.inst 7266352748 # number of demand (read+write) miss cycles
1853system.cpu1.icache.demand_miss_latency::total 7266352748 # number of demand (read+write) miss cycles
1854system.cpu1.icache.overall_miss_latency::cpu1.inst 7266352748 # number of overall miss cycles
1855system.cpu1.icache.overall_miss_latency::total 7266352748 # number of overall miss cycles
1856system.cpu1.icache.ReadReq_accesses::cpu1.inst 7665743 # number of ReadReq accesses(hits+misses)
1857system.cpu1.icache.ReadReq_accesses::total 7665743 # number of ReadReq accesses(hits+misses)
1858system.cpu1.icache.demand_accesses::cpu1.inst 7665743 # number of demand (read+write) accesses
1859system.cpu1.icache.demand_accesses::total 7665743 # number of demand (read+write) accesses
1860system.cpu1.icache.overall_accesses::cpu1.inst 7665743 # number of overall (read+write) accesses
1861system.cpu1.icache.overall_accesses::total 7665743 # number of overall (read+write) accesses
1862system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116569 # miss rate for ReadReq accesses
1863system.cpu1.icache.ReadReq_miss_rate::total 0.116569 # miss rate for ReadReq accesses
1864system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116569 # miss rate for demand accesses
1865system.cpu1.icache.demand_miss_rate::total 0.116569 # miss rate for demand accesses
1866system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116569 # miss rate for overall accesses
1867system.cpu1.icache.overall_miss_rate::total 0.116569 # miss rate for overall accesses
1868system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8131.667927 # average ReadReq miss latency
1869system.cpu1.icache.ReadReq_avg_miss_latency::total 8131.667927 # average ReadReq miss latency
1870system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency
1871system.cpu1.icache.demand_avg_miss_latency::total 8131.667927 # average overall miss latency
1872system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency
1873system.cpu1.icache.overall_avg_miss_latency::total 8131.667927 # average overall miss latency
|
1374system.cpu1.icache.tags.tag_accesses 16220792 # Number of tag accesses 1375system.cpu1.icache.tags.data_accesses 16220792 # Number of data accesses 1376system.cpu1.icache.ReadReq_hits::cpu1.inst 6770083 # number of ReadReq hits 1377system.cpu1.icache.ReadReq_hits::total 6770083 # number of ReadReq hits 1378system.cpu1.icache.demand_hits::cpu1.inst 6770083 # number of demand (read+write) hits 1379system.cpu1.icache.demand_hits::total 6770083 # number of demand (read+write) hits 1380system.cpu1.icache.overall_hits::cpu1.inst 6770083 # number of overall hits 1381system.cpu1.icache.overall_hits::total 6770083 # number of overall hits 1382system.cpu1.icache.ReadReq_misses::cpu1.inst 893542 # number of ReadReq misses 1383system.cpu1.icache.ReadReq_misses::total 893542 # number of ReadReq misses 1384system.cpu1.icache.demand_misses::cpu1.inst 893542 # number of demand (read+write) misses 1385system.cpu1.icache.demand_misses::total 893542 # number of demand (read+write) misses 1386system.cpu1.icache.overall_misses::cpu1.inst 893542 # number of overall misses 1387system.cpu1.icache.overall_misses::total 893542 # number of overall misses 1388system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7266670468 # number of ReadReq miss cycles 1389system.cpu1.icache.ReadReq_miss_latency::total 7266670468 # number of ReadReq miss cycles 1390system.cpu1.icache.demand_miss_latency::cpu1.inst 7266670468 # number of demand (read+write) miss cycles 1391system.cpu1.icache.demand_miss_latency::total 7266670468 # number of demand (read+write) miss cycles 1392system.cpu1.icache.overall_miss_latency::cpu1.inst 7266670468 # number of overall miss cycles 1393system.cpu1.icache.overall_miss_latency::total 7266670468 # number of overall miss cycles 1394system.cpu1.icache.ReadReq_accesses::cpu1.inst 7663625 # number of ReadReq accesses(hits+misses) 1395system.cpu1.icache.ReadReq_accesses::total 7663625 # number of ReadReq accesses(hits+misses) 1396system.cpu1.icache.demand_accesses::cpu1.inst 7663625 # number of demand (read+write) accesses 1397system.cpu1.icache.demand_accesses::total 7663625 # number of demand (read+write) accesses 1398system.cpu1.icache.overall_accesses::cpu1.inst 7663625 # number of overall (read+write) accesses 1399system.cpu1.icache.overall_accesses::total 7663625 # number of overall (read+write) accesses 1400system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116595 # miss rate for ReadReq accesses 1401system.cpu1.icache.ReadReq_miss_rate::total 0.116595 # miss rate for ReadReq accesses 1402system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116595 # miss rate for demand accesses 1403system.cpu1.icache.demand_miss_rate::total 0.116595 # miss rate for demand accesses 1404system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116595 # miss rate for overall accesses 1405system.cpu1.icache.overall_miss_rate::total 0.116595 # miss rate for overall accesses 1406system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8132.433023 # average ReadReq miss latency 1407system.cpu1.icache.ReadReq_avg_miss_latency::total 8132.433023 # average ReadReq miss latency 1408system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency 1409system.cpu1.icache.demand_avg_miss_latency::total 8132.433023 # average overall miss latency 1410system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency 1411system.cpu1.icache.overall_avg_miss_latency::total 8132.433023 # average overall miss latency |
1412system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1413system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1414system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1415system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1416system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1417system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1418system.cpu1.icache.fast_writes 0 # number of fast writes performed 1419system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
1882system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893587 # number of ReadReq MSHR misses
1883system.cpu1.icache.ReadReq_mshr_misses::total 893587 # number of ReadReq MSHR misses
1884system.cpu1.icache.demand_mshr_misses::cpu1.inst 893587 # number of demand (read+write) MSHR misses
1885system.cpu1.icache.demand_mshr_misses::total 893587 # number of demand (read+write) MSHR misses
1886system.cpu1.icache.overall_mshr_misses::cpu1.inst 893587 # number of overall MSHR misses
1887system.cpu1.icache.overall_mshr_misses::total 893587 # number of overall MSHR misses
1888system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923590752 # number of ReadReq MSHR miss cycles
1889system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923590752 # number of ReadReq MSHR miss cycles
1890system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923590752 # number of demand (read+write) MSHR miss cycles
1891system.cpu1.icache.demand_mshr_miss_latency::total 5923590752 # number of demand (read+write) MSHR miss cycles
1892system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923590752 # number of overall MSHR miss cycles
1893system.cpu1.icache.overall_mshr_miss_latency::total 5923590752 # number of overall MSHR miss cycles
|
1420system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893542 # number of ReadReq MSHR misses 1421system.cpu1.icache.ReadReq_mshr_misses::total 893542 # number of ReadReq MSHR misses 1422system.cpu1.icache.demand_mshr_misses::cpu1.inst 893542 # number of demand (read+write) MSHR misses 1423system.cpu1.icache.demand_mshr_misses::total 893542 # number of demand (read+write) MSHR misses 1424system.cpu1.icache.overall_mshr_misses::cpu1.inst 893542 # number of overall MSHR misses 1425system.cpu1.icache.overall_mshr_misses::total 893542 # number of overall MSHR misses 1426system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923954530 # number of ReadReq MSHR miss cycles 1427system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923954530 # number of ReadReq MSHR miss cycles 1428system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923954530 # number of demand (read+write) MSHR miss cycles 1429system.cpu1.icache.demand_mshr_miss_latency::total 5923954530 # number of demand (read+write) MSHR miss cycles 1430system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923954530 # number of overall MSHR miss cycles 1431system.cpu1.icache.overall_mshr_miss_latency::total 5923954530 # number of overall MSHR miss cycles |
1432system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10589750 # number of ReadReq MSHR uncacheable cycles 1433system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10589750 # number of ReadReq MSHR uncacheable cycles 1434system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10589750 # number of overall MSHR uncacheable cycles 1435system.cpu1.icache.overall_mshr_uncacheable_latency::total 10589750 # number of overall MSHR uncacheable cycles
|
1898system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for ReadReq accesses
1899system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116569 # mshr miss rate for ReadReq accesses
1900system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for demand accesses
1901system.cpu1.icache.demand_mshr_miss_rate::total 0.116569 # mshr miss rate for demand accesses
1902system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for overall accesses
1903system.cpu1.icache.overall_mshr_miss_rate::total 0.116569 # mshr miss rate for overall accesses
1904system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average ReadReq mshr miss latency
1905system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.002830 # average ReadReq mshr miss latency
1906system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency
1907system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency
1908system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency
1909system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency
|
1436system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for ReadReq accesses 1437system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses 1438system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for demand accesses 1439system.cpu1.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses 1440system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for overall accesses 1441system.cpu1.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses 1442system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average ReadReq mshr miss latency 1443system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.743795 # average ReadReq mshr miss latency 1444system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency 1445system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency 1446system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency 1447system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency |
1448system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1449system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1450system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1451system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1452system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
1915system.cpu1.toL2Bus.trans_dist::ReadReq 1582924 # Transaction distribution
1916system.cpu1.toL2Bus.trans_dist::ReadResp 1137885 # Transaction distribution
1917system.cpu1.toL2Bus.trans_dist::WriteReq 2119 # Transaction distribution
1918system.cpu1.toL2Bus.trans_dist::WriteResp 2119 # Transaction distribution
1919system.cpu1.toL2Bus.trans_dist::Writeback 115746 # Transaction distribution
1920system.cpu1.toL2Bus.trans_dist::HardPFReq 150971 # Transaction distribution
1921system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
1922system.cpu1.toL2Bus.trans_dist::UpgradeReq 84405 # Transaction distribution
1923system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41125 # Transaction distribution
1924system.cpu1.toL2Bus.trans_dist::UpgradeResp 85149 # Transaction distribution
1925system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
1926system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
1927system.cpu1.toL2Bus.trans_dist::ReadExReq 76810 # Transaction distribution
1928system.cpu1.toL2Bus.trans_dist::ReadExResp 64398 # Transaction distribution
1929system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787404 # Packet count per connected master and slave (bytes)
1930system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 768912 # Packet count per connected master and slave (bytes)
1931system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6948 # Packet count per connected master and slave (bytes)
1932system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51790 # Packet count per connected master and slave (bytes)
1933system.cpu1.toL2Bus.pkt_count::total 2615054 # Packet count per connected master and slave (bytes)
1934system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57196928 # Cumulative packet size per connected master and slave (bytes)
1935system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24920351 # Cumulative packet size per connected master and slave (bytes)
1936system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10668 # Cumulative packet size per connected master and slave (bytes)
1937system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 94516 # Cumulative packet size per connected master and slave (bytes)
1938system.cpu1.toL2Bus.pkt_size::total 82222463 # Cumulative packet size per connected master and slave (bytes)
1939system.cpu1.toL2Bus.snoops 838516 # Total snoops (count)
1940system.cpu1.toL2Bus.snoop_fanout::samples 2085340 # Request fanout histogram
1941system.cpu1.toL2Bus.snoop_fanout::mean 5.363825 # Request fanout histogram
1942system.cpu1.toL2Bus.snoop_fanout::stdev 0.481099 # Request fanout histogram
1943system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1944system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1945system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1946system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1947system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1948system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1949system.cpu1.toL2Bus.snoop_fanout::5 1326642 63.62% 63.62% # Request fanout histogram
1950system.cpu1.toL2Bus.snoop_fanout::6 758698 36.38% 100.00% # Request fanout histogram
1951system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1952system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1953system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1954system.cpu1.toL2Bus.snoop_fanout::total 2085340 # Request fanout histogram
1955system.cpu1.toL2Bus.reqLayer0.occupancy 782793185 # Layer occupancy (ticks)
1956system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1957system.cpu1.toL2Bus.snoopLayer0.occupancy 78444000 # Layer occupancy (ticks)
1958system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1959system.cpu1.toL2Bus.respLayer0.occupancy 1341767498 # Layer occupancy (ticks)
1960system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1961system.cpu1.toL2Bus.respLayer1.occupancy 381370915 # Layer occupancy (ticks)
1962system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1963system.cpu1.toL2Bus.respLayer2.occupancy 4282497 # Layer occupancy (ticks)
1964system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1965system.cpu1.toL2Bus.respLayer3.occupancy 28163996 # Layer occupancy (ticks)
1966system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1967system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7065047 # number of hwpf identified
1968system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40428 # number of hwpf that were already in mshr
1969system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914930 # number of hwpf that were already in the cache
1970system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1457 # number of hwpf that were already in the prefetch queue
|
1453system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7064659 # number of hwpf identified 1454system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40510 # number of hwpf that were already in mshr 1455system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914419 # number of hwpf that were already in the cache 1456system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1409 # number of hwpf that were already in the prefetch queue |
1457system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
1972system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2607 # number of hwpf removed because MSHR allocated
1973system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105625 # number of hwpf issued
1974system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724673 # number of hwpf spanning a virtual page
|
1458system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2627 # number of hwpf removed because MSHR allocated 1459system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105694 # number of hwpf issued 1460system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724613 # number of hwpf spanning a virtual page |
1461system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
1976system.cpu1.l2cache.tags.replacements 79629 # number of replacements
1977system.cpu1.l2cache.tags.tagsinuse 15528.716598 # Cycle average of tags in use
1978system.cpu1.l2cache.tags.total_refs 1138081 # Total number of references to valid blocks.
1979system.cpu1.l2cache.tags.sampled_refs 94994 # Sample count of references to valid blocks.
1980system.cpu1.l2cache.tags.avg_refs 11.980557 # Average number of references to valid blocks.
|
1462system.cpu1.l2cache.tags.replacements 80002 # number of replacements 1463system.cpu1.l2cache.tags.tagsinuse 15534.005683 # Cycle average of tags in use 1464system.cpu1.l2cache.tags.total_refs 1138706 # Total number of references to valid blocks. 1465system.cpu1.l2cache.tags.sampled_refs 95380 # Sample count of references to valid blocks. 1466system.cpu1.l2cache.tags.avg_refs 11.938624 # Average number of references to valid blocks. |
1467system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
1982system.cpu1.l2cache.tags.occ_blocks::writebacks 6912.222509 # Average occupied blocks per requestor
1983system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 24.793124 # Average occupied blocks per requestor
1984system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.117245 # Average occupied blocks per requestor
1985system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2315.760796 # Average occupied blocks per requestor
1986system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6275.822923 # Average occupied blocks per requestor
1987system.cpu1.l2cache.tags.occ_percent::writebacks 0.421889 # Average percentage of cache occupancy
1988system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001513 # Average percentage of cache occupancy
1989system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy
1990system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.141343 # Average percentage of cache occupancy
1991system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383046 # Average percentage of cache occupancy
1992system.cpu1.l2cache.tags.occ_percent::total 0.947798 # Average percentage of cache occupancy
1993system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10144 # Occupied blocks per task id
1994system.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id
1995system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5192 # Occupied blocks per task id
1996system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id
1997system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6818 # Occupied blocks per task id
1998system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3193 # Occupied blocks per task id
|
1468system.cpu1.l2cache.tags.occ_blocks::writebacks 6881.050205 # Average occupied blocks per requestor 1469system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.485106 # Average occupied blocks per requestor 1470system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.098583 # Average occupied blocks per requestor 1471system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2338.762949 # Average occupied blocks per requestor 1472system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6287.608842 # Average occupied blocks per requestor 1473system.cpu1.l2cache.tags.occ_percent::writebacks 0.419986 # Average percentage of cache occupancy 1474system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001617 # Average percentage of cache occupancy 1475system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy 1476system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142747 # Average percentage of cache occupancy 1477system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383765 # Average percentage of cache occupancy 1478system.cpu1.l2cache.tags.occ_percent::total 0.948120 # Average percentage of cache occupancy 1479system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10071 # Occupied blocks per task id 1480system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id 1481system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id 1482system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id 1483system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6676 # Occupied blocks per task id 1484system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3263 # Occupied blocks per task id |
1485system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id
|
2000system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
|
1486system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id |
1487system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
|
2002system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id
2003system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3095 # Occupied blocks per task id
2004system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1854 # Occupied blocks per task id
2005system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.619141 # Percentage of cache occupancy per task id
2006system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001770 # Percentage of cache occupancy per task id
2007system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.316895 # Percentage of cache occupancy per task id
2008system.cpu1.l2cache.tags.tag_accesses 21374644 # Number of tag accesses
2009system.cpu1.l2cache.tags.data_accesses 21374644 # Number of data accesses
2010system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23037 # number of ReadReq hits
2011system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2415 # number of ReadReq hits
2012system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993214 # number of ReadReq hits
2013system.cpu1.l2cache.ReadReq_hits::total 1018666 # number of ReadReq hits
2014system.cpu1.l2cache.Writeback_hits::writebacks 115746 # number of Writeback hits
2015system.cpu1.l2cache.Writeback_hits::total 115746 # number of Writeback hits
2016system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1782 # number of UpgradeReq hits
2017system.cpu1.l2cache.UpgradeReq_hits::total 1782 # number of UpgradeReq hits
2018system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 772 # number of SCUpgradeReq hits
2019system.cpu1.l2cache.SCUpgradeReq_hits::total 772 # number of SCUpgradeReq hits
2020system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27747 # number of ReadExReq hits
2021system.cpu1.l2cache.ReadExReq_hits::total 27747 # number of ReadExReq hits
2022system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23037 # number of demand (read+write) hits
2023system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2415 # number of demand (read+write) hits
2024system.cpu1.l2cache.demand_hits::cpu1.inst 1020961 # number of demand (read+write) hits
2025system.cpu1.l2cache.demand_hits::total 1046413 # number of demand (read+write) hits
2026system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23037 # number of overall hits
2027system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2415 # number of overall hits
2028system.cpu1.l2cache.overall_hits::cpu1.inst 1020961 # number of overall hits
2029system.cpu1.l2cache.overall_hits::total 1046413 # number of overall hits
2030system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 592 # number of ReadReq misses
2031system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 252 # number of ReadReq misses
2032system.cpu1.l2cache.ReadReq_misses::cpu1.inst 72082 # number of ReadReq misses
2033system.cpu1.l2cache.ReadReq_misses::total 72926 # number of ReadReq misses
2034system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28135 # number of UpgradeReq misses
2035system.cpu1.l2cache.UpgradeReq_misses::total 28135 # number of UpgradeReq misses
2036system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22404 # number of SCUpgradeReq misses
2037system.cpu1.l2cache.SCUpgradeReq_misses::total 22404 # number of SCUpgradeReq misses
2038system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32295 # number of ReadExReq misses
2039system.cpu1.l2cache.ReadExReq_misses::total 32295 # number of ReadExReq misses
2040system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 592 # number of demand (read+write) misses
2041system.cpu1.l2cache.demand_misses::cpu1.itb.walker 252 # number of demand (read+write) misses
2042system.cpu1.l2cache.demand_misses::cpu1.inst 104377 # number of demand (read+write) misses
2043system.cpu1.l2cache.demand_misses::total 105221 # number of demand (read+write) misses
2044system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 592 # number of overall misses
2045system.cpu1.l2cache.overall_misses::cpu1.itb.walker 252 # number of overall misses
2046system.cpu1.l2cache.overall_misses::cpu1.inst 104377 # number of overall misses
2047system.cpu1.l2cache.overall_misses::total 105221 # number of overall misses
2048system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13156500 # number of ReadReq miss cycles
2049system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5072997 # number of ReadReq miss cycles
2050system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1619935379 # number of ReadReq miss cycles
2051system.cpu1.l2cache.ReadReq_miss_latency::total 1638164876 # number of ReadReq miss cycles
2052system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 531136882 # number of UpgradeReq miss cycles
2053system.cpu1.l2cache.UpgradeReq_miss_latency::total 531136882 # number of UpgradeReq miss cycles
2054system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440134565 # number of SCUpgradeReq miss cycles
2055system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440134565 # number of SCUpgradeReq miss cycles
2056system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 329000 # number of SCUpgradeFailReq miss cycles
2057system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 329000 # number of SCUpgradeFailReq miss cycles
2058system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1130691878 # number of ReadExReq miss cycles
2059system.cpu1.l2cache.ReadExReq_miss_latency::total 1130691878 # number of ReadExReq miss cycles
2060system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13156500 # number of demand (read+write) miss cycles
2061system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5072997 # number of demand (read+write) miss cycles
2062system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2750627257 # number of demand (read+write) miss cycles
2063system.cpu1.l2cache.demand_miss_latency::total 2768856754 # number of demand (read+write) miss cycles
2064system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13156500 # number of overall miss cycles
2065system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5072997 # number of overall miss cycles
2066system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2750627257 # number of overall miss cycles
2067system.cpu1.l2cache.overall_miss_latency::total 2768856754 # number of overall miss cycles
2068system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23629 # number of ReadReq accesses(hits+misses)
2069system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2667 # number of ReadReq accesses(hits+misses)
2070system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1065296 # number of ReadReq accesses(hits+misses)
2071system.cpu1.l2cache.ReadReq_accesses::total 1091592 # number of ReadReq accesses(hits+misses)
2072system.cpu1.l2cache.Writeback_accesses::writebacks 115746 # number of Writeback accesses(hits+misses)
2073system.cpu1.l2cache.Writeback_accesses::total 115746 # number of Writeback accesses(hits+misses)
2074system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29917 # number of UpgradeReq accesses(hits+misses)
2075system.cpu1.l2cache.UpgradeReq_accesses::total 29917 # number of UpgradeReq accesses(hits+misses)
2076system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23176 # number of SCUpgradeReq accesses(hits+misses)
2077system.cpu1.l2cache.SCUpgradeReq_accesses::total 23176 # number of SCUpgradeReq accesses(hits+misses)
2078system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60042 # number of ReadExReq accesses(hits+misses)
2079system.cpu1.l2cache.ReadExReq_accesses::total 60042 # number of ReadExReq accesses(hits+misses)
2080system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23629 # number of demand (read+write) accesses
2081system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2667 # number of demand (read+write) accesses
2082system.cpu1.l2cache.demand_accesses::cpu1.inst 1125338 # number of demand (read+write) accesses
2083system.cpu1.l2cache.demand_accesses::total 1151634 # number of demand (read+write) accesses
2084system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23629 # number of overall (read+write) accesses
2085system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2667 # number of overall (read+write) accesses
2086system.cpu1.l2cache.overall_accesses::cpu1.inst 1125338 # number of overall (read+write) accesses
2087system.cpu1.l2cache.overall_accesses::total 1151634 # number of overall (read+write) accesses
2088system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for ReadReq accesses
2089system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.094488 # miss rate for ReadReq accesses
2090system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067664 # miss rate for ReadReq accesses
2091system.cpu1.l2cache.ReadReq_miss_rate::total 0.066807 # miss rate for ReadReq accesses
2092system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.940435 # miss rate for UpgradeReq accesses
2093system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.940435 # miss rate for UpgradeReq accesses
2094system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.966690 # miss rate for SCUpgradeReq accesses
2095system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.966690 # miss rate for SCUpgradeReq accesses
2096system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.537873 # miss rate for ReadExReq accesses
2097system.cpu1.l2cache.ReadExReq_miss_rate::total 0.537873 # miss rate for ReadExReq accesses
2098system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for demand accesses
2099system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.094488 # miss rate for demand accesses
2100system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092752 # miss rate for demand accesses
2101system.cpu1.l2cache.demand_miss_rate::total 0.091367 # miss rate for demand accesses
2102system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for overall accesses
2103system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.094488 # miss rate for overall accesses
2104system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092752 # miss rate for overall accesses
2105system.cpu1.l2cache.overall_miss_rate::total 0.091367 # miss rate for overall accesses
2106system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average ReadReq miss latency
2107system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20130.940476 # average ReadReq miss latency
2108system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22473.507658 # average ReadReq miss latency
2109system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22463.385843 # average ReadReq miss latency
2110system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18878.154683 # average UpgradeReq miss latency
2111system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18878.154683 # average UpgradeReq miss latency
2112system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19645.356410 # average SCUpgradeReq miss latency
2113system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19645.356410 # average SCUpgradeReq miss latency
|
1488system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 237 # Occupied blocks per task id 1489system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id 1490system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1869 # Occupied blocks per task id 1491system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.614685 # Percentage of cache occupancy per task id 1492system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id 1493system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.321838 # Percentage of cache occupancy per task id 1494system.cpu1.l2cache.tags.tag_accesses 21370209 # Number of tag accesses 1495system.cpu1.l2cache.tags.data_accesses 21370209 # Number of data accesses 1496system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22701 # number of ReadReq hits 1497system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2439 # number of ReadReq hits 1498system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993088 # number of ReadReq hits 1499system.cpu1.l2cache.ReadReq_hits::total 1018228 # number of ReadReq hits 1500system.cpu1.l2cache.Writeback_hits::writebacks 115754 # number of Writeback hits 1501system.cpu1.l2cache.Writeback_hits::total 115754 # number of Writeback hits 1502system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits 1503system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits 1504system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 740 # number of SCUpgradeReq hits 1505system.cpu1.l2cache.SCUpgradeReq_hits::total 740 # number of SCUpgradeReq hits 1506system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27796 # number of ReadExReq hits 1507system.cpu1.l2cache.ReadExReq_hits::total 27796 # number of ReadExReq hits 1508system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22701 # number of demand (read+write) hits 1509system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2439 # number of demand (read+write) hits 1510system.cpu1.l2cache.demand_hits::cpu1.inst 1020884 # number of demand (read+write) hits 1511system.cpu1.l2cache.demand_hits::total 1046024 # number of demand (read+write) hits 1512system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22701 # number of overall hits 1513system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2439 # number of overall hits 1514system.cpu1.l2cache.overall_hits::cpu1.inst 1020884 # number of overall hits 1515system.cpu1.l2cache.overall_hits::total 1046024 # number of overall hits 1516system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 604 # number of ReadReq misses 1517system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses 1518system.cpu1.l2cache.ReadReq_misses::cpu1.inst 72199 # number of ReadReq misses 1519system.cpu1.l2cache.ReadReq_misses::total 73046 # number of ReadReq misses 1520system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28140 # number of UpgradeReq misses 1521system.cpu1.l2cache.UpgradeReq_misses::total 28140 # number of UpgradeReq misses 1522system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22420 # number of SCUpgradeReq misses 1523system.cpu1.l2cache.SCUpgradeReq_misses::total 22420 # number of SCUpgradeReq misses 1524system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32240 # number of ReadExReq misses 1525system.cpu1.l2cache.ReadExReq_misses::total 32240 # number of ReadExReq misses 1526system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 604 # number of demand (read+write) misses 1527system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses 1528system.cpu1.l2cache.demand_misses::cpu1.inst 104439 # number of demand (read+write) misses 1529system.cpu1.l2cache.demand_misses::total 105286 # number of demand (read+write) misses 1530system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 604 # number of overall misses 1531system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses 1532system.cpu1.l2cache.overall_misses::cpu1.inst 104439 # number of overall misses 1533system.cpu1.l2cache.overall_misses::total 105286 # number of overall misses 1534system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13239000 # number of ReadReq miss cycles 1535system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4899500 # number of ReadReq miss cycles 1536system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1623706138 # number of ReadReq miss cycles 1537system.cpu1.l2cache.ReadReq_miss_latency::total 1641844638 # number of ReadReq miss cycles 1538system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 531483393 # number of UpgradeReq miss cycles 1539system.cpu1.l2cache.UpgradeReq_miss_latency::total 531483393 # number of UpgradeReq miss cycles 1540system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440502566 # number of SCUpgradeReq miss cycles 1541system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440502566 # number of SCUpgradeReq miss cycles 1542system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 296000 # number of SCUpgradeFailReq miss cycles 1543system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 296000 # number of SCUpgradeFailReq miss cycles 1544system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1126750383 # number of ReadExReq miss cycles 1545system.cpu1.l2cache.ReadExReq_miss_latency::total 1126750383 # number of ReadExReq miss cycles 1546system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13239000 # number of demand (read+write) miss cycles 1547system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4899500 # number of demand (read+write) miss cycles 1548system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2750456521 # number of demand (read+write) miss cycles 1549system.cpu1.l2cache.demand_miss_latency::total 2768595021 # number of demand (read+write) miss cycles 1550system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13239000 # number of overall miss cycles 1551system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4899500 # number of overall miss cycles 1552system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2750456521 # number of overall miss cycles 1553system.cpu1.l2cache.overall_miss_latency::total 2768595021 # number of overall miss cycles 1554system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23305 # number of ReadReq accesses(hits+misses) 1555system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2682 # number of ReadReq accesses(hits+misses) 1556system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1065287 # number of ReadReq accesses(hits+misses) 1557system.cpu1.l2cache.ReadReq_accesses::total 1091274 # number of ReadReq accesses(hits+misses) 1558system.cpu1.l2cache.Writeback_accesses::writebacks 115754 # number of Writeback accesses(hits+misses) 1559system.cpu1.l2cache.Writeback_accesses::total 115754 # number of Writeback accesses(hits+misses) 1560system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29950 # number of UpgradeReq accesses(hits+misses) 1561system.cpu1.l2cache.UpgradeReq_accesses::total 29950 # number of UpgradeReq accesses(hits+misses) 1562system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23160 # number of SCUpgradeReq accesses(hits+misses) 1563system.cpu1.l2cache.SCUpgradeReq_accesses::total 23160 # number of SCUpgradeReq accesses(hits+misses) 1564system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60036 # number of ReadExReq accesses(hits+misses) 1565system.cpu1.l2cache.ReadExReq_accesses::total 60036 # number of ReadExReq accesses(hits+misses) 1566system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23305 # number of demand (read+write) accesses 1567system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2682 # number of demand (read+write) accesses 1568system.cpu1.l2cache.demand_accesses::cpu1.inst 1125323 # number of demand (read+write) accesses 1569system.cpu1.l2cache.demand_accesses::total 1151310 # number of demand (read+write) accesses 1570system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23305 # number of overall (read+write) accesses 1571system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2682 # number of overall (read+write) accesses 1572system.cpu1.l2cache.overall_accesses::cpu1.inst 1125323 # number of overall (read+write) accesses 1573system.cpu1.l2cache.overall_accesses::total 1151310 # number of overall (read+write) accesses 1574system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for ReadReq accesses 1575system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090604 # miss rate for ReadReq accesses 1576system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067774 # miss rate for ReadReq accesses 1577system.cpu1.l2cache.ReadReq_miss_rate::total 0.066936 # miss rate for ReadReq accesses 1578system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.939566 # miss rate for UpgradeReq accesses 1579system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.939566 # miss rate for UpgradeReq accesses 1580system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968048 # miss rate for SCUpgradeReq accesses 1581system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968048 # miss rate for SCUpgradeReq accesses 1582system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.537011 # miss rate for ReadExReq accesses 1583system.cpu1.l2cache.ReadExReq_miss_rate::total 0.537011 # miss rate for ReadExReq accesses 1584system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for demand accesses 1585system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090604 # miss rate for demand accesses 1586system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092808 # miss rate for demand accesses 1587system.cpu1.l2cache.demand_miss_rate::total 0.091449 # miss rate for demand accesses 1588system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for overall accesses 1589system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090604 # miss rate for overall accesses 1590system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092808 # miss rate for overall accesses 1591system.cpu1.l2cache.overall_miss_rate::total 0.091449 # miss rate for overall accesses 1592system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average ReadReq miss latency 1593system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20162.551440 # average ReadReq miss latency 1594system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22489.316168 # average ReadReq miss latency 1595system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22476.858938 # average ReadReq miss latency 1596system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18887.114179 # average UpgradeReq miss latency 1597system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18887.114179 # average UpgradeReq miss latency 1598system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19647.750491 # average SCUpgradeReq miss latency 1599system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19647.750491 # average SCUpgradeReq miss latency |
1600system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency 1601system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
|
2116system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35011.360211 # average ReadExReq miss latency
2117system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35011.360211 # average ReadExReq miss latency
2118system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average overall miss latency
2119system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20130.940476 # average overall miss latency
2120system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26352.810073 # average overall miss latency
2121system.cpu1.l2cache.demand_avg_miss_latency::total 26314.678192 # average overall miss latency
2122system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average overall miss latency
2123system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20130.940476 # average overall miss latency
2124system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26352.810073 # average overall miss latency
2125system.cpu1.l2cache.overall_avg_miss_latency::total 26314.678192 # average overall miss latency
2126system.cpu1.l2cache.blocked_cycles::no_mshrs 4757 # number of cycles access was blocked
|
1602system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34948.833220 # average ReadExReq miss latency 1603system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34948.833220 # average ReadExReq miss latency 1604system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average overall miss latency 1605system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20162.551440 # average overall miss latency 1606system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26335.530989 # average overall miss latency 1607system.cpu1.l2cache.demand_avg_miss_latency::total 26295.946479 # average overall miss latency 1608system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average overall miss latency 1609system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20162.551440 # average overall miss latency 1610system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26335.530989 # average overall miss latency 1611system.cpu1.l2cache.overall_avg_miss_latency::total 26295.946479 # average overall miss latency 1612system.cpu1.l2cache.blocked_cycles::no_mshrs 4629 # number of cycles access was blocked |
1613system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2128system.cpu1.l2cache.blocked::no_mshrs 158 # number of cycles access was blocked
|
1614system.cpu1.l2cache.blocked::no_mshrs 159 # number of cycles access was blocked |
1615system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2130system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.107595 # average number of cycles each access was blocked
|
1616system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29.113208 # average number of cycles each access was blocked |
1617system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1618system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1619system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
2134system.cpu1.l2cache.writebacks::writebacks 38299 # number of writebacks
2135system.cpu1.l2cache.writebacks::total 38299 # number of writebacks
2136system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1547 # number of ReadReq MSHR hits
2137system.cpu1.l2cache.ReadReq_mshr_hits::total 1547 # number of ReadReq MSHR hits
2138system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 321 # number of ReadExReq MSHR hits
2139system.cpu1.l2cache.ReadExReq_mshr_hits::total 321 # number of ReadExReq MSHR hits
2140system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1868 # number of demand (read+write) MSHR hits
2141system.cpu1.l2cache.demand_mshr_hits::total 1868 # number of demand (read+write) MSHR hits
2142system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1868 # number of overall MSHR hits
2143system.cpu1.l2cache.overall_mshr_hits::total 1868 # number of overall MSHR hits
2144system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 592 # number of ReadReq MSHR misses
2145system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 252 # number of ReadReq MSHR misses
2146system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 70535 # number of ReadReq MSHR misses
2147system.cpu1.l2cache.ReadReq_mshr_misses::total 71379 # number of ReadReq MSHR misses
2148system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 105624 # number of HardPFReq MSHR misses
2149system.cpu1.l2cache.HardPFReq_mshr_misses::total 105624 # number of HardPFReq MSHR misses
2150system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28135 # number of UpgradeReq MSHR misses
2151system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28135 # number of UpgradeReq MSHR misses
2152system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22404 # number of SCUpgradeReq MSHR misses
2153system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22404 # number of SCUpgradeReq MSHR misses
2154system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 31974 # number of ReadExReq MSHR misses
2155system.cpu1.l2cache.ReadExReq_mshr_misses::total 31974 # number of ReadExReq MSHR misses
2156system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 592 # number of demand (read+write) MSHR misses
2157system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 252 # number of demand (read+write) MSHR misses
2158system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 102509 # number of demand (read+write) MSHR misses
2159system.cpu1.l2cache.demand_mshr_misses::total 103353 # number of demand (read+write) MSHR misses
2160system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 592 # number of overall MSHR misses
2161system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 252 # number of overall MSHR misses
2162system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 102509 # number of overall MSHR misses
2163system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 105624 # number of overall MSHR misses
2164system.cpu1.l2cache.overall_mshr_misses::total 208977 # number of overall MSHR misses
2165system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of ReadReq MSHR miss cycles
2166system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3308997 # number of ReadReq MSHR miss cycles
2167system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1095971987 # number of ReadReq MSHR miss cycles
2168system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1108291484 # number of ReadReq MSHR miss cycles
2169system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2952900698 # number of HardPFReq MSHR miss cycles
2170system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2952900698 # number of HardPFReq MSHR miss cycles
2171system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 404207806 # number of UpgradeReq MSHR miss cycles
2172system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 404207806 # number of UpgradeReq MSHR miss cycles
2173system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 308121722 # number of SCUpgradeReq MSHR miss cycles
2174system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308121722 # number of SCUpgradeReq MSHR miss cycles
2175system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 273000 # number of SCUpgradeFailReq MSHR miss cycles
2176system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 273000 # number of SCUpgradeFailReq MSHR miss cycles
2177system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 864621339 # number of ReadExReq MSHR miss cycles
2178system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 864621339 # number of ReadExReq MSHR miss cycles
2179system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of demand (read+write) MSHR miss cycles
2180system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3308997 # number of demand (read+write) MSHR miss cycles
2181system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1960593326 # number of demand (read+write) MSHR miss cycles
2182system.cpu1.l2cache.demand_mshr_miss_latency::total 1972912823 # number of demand (read+write) MSHR miss cycles
2183system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of overall MSHR miss cycles
2184system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3308997 # number of overall MSHR miss cycles
2185system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1960593326 # number of overall MSHR miss cycles
2186system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2952900698 # number of overall MSHR miss cycles
2187system.cpu1.l2cache.overall_mshr_miss_latency::total 4925813521 # number of overall MSHR miss cycles
2188system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316590752 # number of ReadReq MSHR uncacheable cycles
2189system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316590752 # number of ReadReq MSHR uncacheable cycles
2190system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 186920002 # number of WriteReq MSHR uncacheable cycles
2191system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 186920002 # number of WriteReq MSHR uncacheable cycles
2192system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 503510754 # number of overall MSHR uncacheable cycles
2193system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 503510754 # number of overall MSHR uncacheable cycles
2194system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for ReadReq accesses
2195system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for ReadReq accesses
2196system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066212 # mshr miss rate for ReadReq accesses
2197system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065390 # mshr miss rate for ReadReq accesses
|
1620system.cpu1.l2cache.writebacks::writebacks 38442 # number of writebacks 1621system.cpu1.l2cache.writebacks::total 38442 # number of writebacks 1622system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1604 # number of ReadReq MSHR hits 1623system.cpu1.l2cache.ReadReq_mshr_hits::total 1604 # number of ReadReq MSHR hits 1624system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 322 # number of ReadExReq MSHR hits 1625system.cpu1.l2cache.ReadExReq_mshr_hits::total 322 # number of ReadExReq MSHR hits 1626system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1926 # number of demand (read+write) MSHR hits 1627system.cpu1.l2cache.demand_mshr_hits::total 1926 # number of demand (read+write) MSHR hits 1628system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1926 # number of overall MSHR hits 1629system.cpu1.l2cache.overall_mshr_hits::total 1926 # number of overall MSHR hits 1630system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 604 # number of ReadReq MSHR misses 1631system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 243 # number of ReadReq MSHR misses 1632system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 70595 # number of ReadReq MSHR misses 1633system.cpu1.l2cache.ReadReq_mshr_misses::total 71442 # number of ReadReq MSHR misses 1634system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 105694 # number of HardPFReq MSHR misses 1635system.cpu1.l2cache.HardPFReq_mshr_misses::total 105694 # number of HardPFReq MSHR misses 1636system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28140 # number of UpgradeReq MSHR misses 1637system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28140 # number of UpgradeReq MSHR misses 1638system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22420 # number of SCUpgradeReq MSHR misses 1639system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22420 # number of SCUpgradeReq MSHR misses 1640system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 31918 # number of ReadExReq MSHR misses 1641system.cpu1.l2cache.ReadExReq_mshr_misses::total 31918 # number of ReadExReq MSHR misses 1642system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 604 # number of demand (read+write) MSHR misses 1643system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 243 # number of demand (read+write) MSHR misses 1644system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 102513 # number of demand (read+write) MSHR misses 1645system.cpu1.l2cache.demand_mshr_misses::total 103360 # number of demand (read+write) MSHR misses 1646system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 604 # number of overall MSHR misses 1647system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 243 # number of overall MSHR misses 1648system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 102513 # number of overall MSHR misses 1649system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 105694 # number of overall MSHR misses 1650system.cpu1.l2cache.overall_mshr_misses::total 209054 # number of overall MSHR misses 1651system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of ReadReq MSHR miss cycles 1652system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3198500 # number of ReadReq MSHR miss cycles 1653system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1098179235 # number of ReadReq MSHR miss cycles 1654system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1110385737 # number of ReadReq MSHR miss cycles 1655system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2958247424 # number of HardPFReq MSHR miss cycles 1656system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2958247424 # number of HardPFReq MSHR miss cycles 1657system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 404415795 # number of UpgradeReq MSHR miss cycles 1658system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 404415795 # number of UpgradeReq MSHR miss cycles 1659system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 308218727 # number of SCUpgradeReq MSHR miss cycles 1660system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308218727 # number of SCUpgradeReq MSHR miss cycles 1661system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 247000 # number of SCUpgradeFailReq MSHR miss cycles 1662system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 247000 # number of SCUpgradeFailReq MSHR miss cycles 1663system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 862164082 # number of ReadExReq MSHR miss cycles 1664system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 862164082 # number of ReadExReq MSHR miss cycles 1665system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of demand (read+write) MSHR miss cycles 1666system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3198500 # number of demand (read+write) MSHR miss cycles 1667system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1960343317 # number of demand (read+write) MSHR miss cycles 1668system.cpu1.l2cache.demand_mshr_miss_latency::total 1972549819 # number of demand (read+write) MSHR miss cycles 1669system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of overall MSHR miss cycles 1670system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3198500 # number of overall MSHR miss cycles 1671system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1960343317 # number of overall MSHR miss cycles 1672system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2958247424 # number of overall MSHR miss cycles 1673system.cpu1.l2cache.overall_mshr_miss_latency::total 4930797243 # number of overall MSHR miss cycles 1674system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316625253 # number of ReadReq MSHR uncacheable cycles 1675system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316625253 # number of ReadReq MSHR uncacheable cycles 1676system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 186937501 # number of WriteReq MSHR uncacheable cycles 1677system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 186937501 # number of WriteReq MSHR uncacheable cycles 1678system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 503562754 # number of overall MSHR uncacheable cycles 1679system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 503562754 # number of overall MSHR uncacheable cycles 1680system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for ReadReq accesses 1681system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for ReadReq accesses 1682system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066269 # mshr miss rate for ReadReq accesses 1683system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065467 # mshr miss rate for ReadReq accesses |
1684system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1685system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
2200system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.940435 # mshr miss rate for UpgradeReq accesses
2201system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.940435 # mshr miss rate for UpgradeReq accesses
2202system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.966690 # mshr miss rate for SCUpgradeReq accesses
2203system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.966690 # mshr miss rate for SCUpgradeReq accesses
2204system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.532527 # mshr miss rate for ReadExReq accesses
2205system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.532527 # mshr miss rate for ReadExReq accesses
2206system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for demand accesses
2207system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for demand accesses
2208system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for demand accesses
2209system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089745 # mshr miss rate for demand accesses
2210system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for overall accesses
2211system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for overall accesses
2212system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for overall accesses
|
1686system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.939566 # mshr miss rate for UpgradeReq accesses 1687system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.939566 # mshr miss rate for UpgradeReq accesses 1688system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968048 # mshr miss rate for SCUpgradeReq accesses 1689system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968048 # mshr miss rate for SCUpgradeReq accesses 1690system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.531648 # mshr miss rate for ReadExReq accesses 1691system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.531648 # mshr miss rate for ReadExReq accesses 1692system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for demand accesses 1693system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for demand accesses 1694system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for demand accesses 1695system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089776 # mshr miss rate for demand accesses 1696system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for overall accesses 1697system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for overall accesses 1698system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for overall accesses |
1699system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
2214system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181461 # mshr miss rate for overall accesses
2215system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average ReadReq mshr miss latency
2216system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average ReadReq mshr miss latency
2217system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15537.988048 # average ReadReq mshr miss latency
2218system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15526.856414 # average ReadReq mshr miss latency
2219system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average HardPFReq mshr miss latency
2220system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27956.720991 # average HardPFReq mshr miss latency
2221system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14366.724933 # average UpgradeReq mshr miss latency
2222system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14366.724933 # average UpgradeReq mshr miss latency
2223system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13752.978129 # average SCUpgradeReq mshr miss latency
2224system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13752.978129 # average SCUpgradeReq mshr miss latency
|
1700system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181579 # mshr miss rate for overall accesses 1701system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average ReadReq mshr miss latency 1702system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average ReadReq mshr miss latency 1703system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15556.048375 # average ReadReq mshr miss latency 1704system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15542.478332 # average ReadReq mshr miss latency 1705system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average HardPFReq mshr miss latency 1706system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27988.792401 # average HardPFReq mshr miss latency 1707system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14371.563433 # average UpgradeReq mshr miss latency 1708system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14371.563433 # average UpgradeReq mshr miss latency 1709system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13747.490054 # average SCUpgradeReq mshr miss latency 1710system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13747.490054 # average SCUpgradeReq mshr miss latency |
1711system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency 1712system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
|
2227system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27041.387971 # average ReadExReq mshr miss latency
2228system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27041.387971 # average ReadExReq mshr miss latency
2229system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency
2230system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency
2231system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency
2232system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19089.071657 # average overall mshr miss latency
2233system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency
2234system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency
2235system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency
2236system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average overall mshr miss latency
2237system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23571.079693 # average overall mshr miss latency
|
1713system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27011.845416 # average ReadExReq mshr miss latency 1714system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27011.845416 # average ReadExReq mshr miss latency 1715system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency 1716system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency 1717system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency 1718system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19084.266825 # average overall mshr miss latency 1719system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency 1720system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency 1721system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency 1722system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average overall mshr miss latency 1723system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23586.237254 # average overall mshr miss latency |
1724system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1725system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1726system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1727system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1728system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1729system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1730system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2245system.cpu1.dcache.tags.replacements 188481 # number of replacements
2246system.cpu1.dcache.tags.tagsinuse 475.009191 # Cycle average of tags in use
2247system.cpu1.dcache.tags.total_refs 6997616 # Total number of references to valid blocks.
2248system.cpu1.dcache.tags.sampled_refs 188846 # Sample count of references to valid blocks.
2249system.cpu1.dcache.tags.avg_refs 37.054616 # Average number of references to valid blocks.
2250system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit.
2251system.cpu1.dcache.tags.occ_blocks::cpu1.inst 475.009191 # Average occupied blocks per requestor
2252system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927752 # Average percentage of cache occupancy
2253system.cpu1.dcache.tags.occ_percent::total 0.927752 # Average percentage of cache occupancy
2254system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
2255system.cpu1.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id
2256system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id
2257system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id
2258system.cpu1.dcache.tags.tag_accesses 14853075 # Number of tag accesses
2259system.cpu1.dcache.tags.data_accesses 14853075 # Number of data accesses
2260system.cpu1.dcache.ReadReq_hits::cpu1.inst 3751603 # number of ReadReq hits
2261system.cpu1.dcache.ReadReq_hits::total 3751603 # number of ReadReq hits
2262system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051213 # number of WriteReq hits
2263system.cpu1.dcache.WriteReq_hits::total 3051213 # number of WriteReq hits
2264system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88863 # number of LoadLockedReq hits
2265system.cpu1.dcache.LoadLockedReq_hits::total 88863 # number of LoadLockedReq hits
2266system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69198 # number of StoreCondReq hits
2267system.cpu1.dcache.StoreCondReq_hits::total 69198 # number of StoreCondReq hits
2268system.cpu1.dcache.demand_hits::cpu1.inst 6802816 # number of demand (read+write) hits
2269system.cpu1.dcache.demand_hits::total 6802816 # number of demand (read+write) hits
2270system.cpu1.dcache.overall_hits::cpu1.inst 6802816 # number of overall hits
2271system.cpu1.dcache.overall_hits::total 6802816 # number of overall hits
2272system.cpu1.dcache.ReadReq_misses::cpu1.inst 182008 # number of ReadReq misses
2273system.cpu1.dcache.ReadReq_misses::total 182008 # number of ReadReq misses
2274system.cpu1.dcache.WriteReq_misses::cpu1.inst 139434 # number of WriteReq misses
2275system.cpu1.dcache.WriteReq_misses::total 139434 # number of WriteReq misses
2276system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5163 # number of LoadLockedReq misses
2277system.cpu1.dcache.LoadLockedReq_misses::total 5163 # number of LoadLockedReq misses
2278system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23176 # number of StoreCondReq misses
2279system.cpu1.dcache.StoreCondReq_misses::total 23176 # number of StoreCondReq misses
2280system.cpu1.dcache.demand_misses::cpu1.inst 321442 # number of demand (read+write) misses
2281system.cpu1.dcache.demand_misses::total 321442 # number of demand (read+write) misses
2282system.cpu1.dcache.overall_misses::cpu1.inst 321442 # number of overall misses
2283system.cpu1.dcache.overall_misses::total 321442 # number of overall misses
2284system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2744686684 # number of ReadReq miss cycles
2285system.cpu1.dcache.ReadReq_miss_latency::total 2744686684 # number of ReadReq miss cycles
2286system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3345931004 # number of WriteReq miss cycles
2287system.cpu1.dcache.WriteReq_miss_latency::total 3345931004 # number of WriteReq miss cycles
2288system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93833250 # number of LoadLockedReq miss cycles
2289system.cpu1.dcache.LoadLockedReq_miss_latency::total 93833250 # number of LoadLockedReq miss cycles
2290system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540125753 # number of StoreCondReq miss cycles
2291system.cpu1.dcache.StoreCondReq_miss_latency::total 540125753 # number of StoreCondReq miss cycles
2292system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 353500 # number of StoreCondFailReq miss cycles
2293system.cpu1.dcache.StoreCondFailReq_miss_latency::total 353500 # number of StoreCondFailReq miss cycles
2294system.cpu1.dcache.demand_miss_latency::cpu1.inst 6090617688 # number of demand (read+write) miss cycles
2295system.cpu1.dcache.demand_miss_latency::total 6090617688 # number of demand (read+write) miss cycles
2296system.cpu1.dcache.overall_miss_latency::cpu1.inst 6090617688 # number of overall miss cycles
2297system.cpu1.dcache.overall_miss_latency::total 6090617688 # number of overall miss cycles
2298system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3933611 # number of ReadReq accesses(hits+misses)
2299system.cpu1.dcache.ReadReq_accesses::total 3933611 # number of ReadReq accesses(hits+misses)
2300system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3190647 # number of WriteReq accesses(hits+misses)
2301system.cpu1.dcache.WriteReq_accesses::total 3190647 # number of WriteReq accesses(hits+misses)
2302system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94026 # number of LoadLockedReq accesses(hits+misses)
2303system.cpu1.dcache.LoadLockedReq_accesses::total 94026 # number of LoadLockedReq accesses(hits+misses)
2304system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92374 # number of StoreCondReq accesses(hits+misses)
2305system.cpu1.dcache.StoreCondReq_accesses::total 92374 # number of StoreCondReq accesses(hits+misses)
2306system.cpu1.dcache.demand_accesses::cpu1.inst 7124258 # number of demand (read+write) accesses
2307system.cpu1.dcache.demand_accesses::total 7124258 # number of demand (read+write) accesses
2308system.cpu1.dcache.overall_accesses::cpu1.inst 7124258 # number of overall (read+write) accesses
2309system.cpu1.dcache.overall_accesses::total 7124258 # number of overall (read+write) accesses
2310system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046270 # miss rate for ReadReq accesses
2311system.cpu1.dcache.ReadReq_miss_rate::total 0.046270 # miss rate for ReadReq accesses
2312system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043701 # miss rate for WriteReq accesses
2313system.cpu1.dcache.WriteReq_miss_rate::total 0.043701 # miss rate for WriteReq accesses
2314system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054910 # miss rate for LoadLockedReq accesses
2315system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054910 # miss rate for LoadLockedReq accesses
2316system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250893 # miss rate for StoreCondReq accesses
2317system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250893 # miss rate for StoreCondReq accesses
2318system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045119 # miss rate for demand accesses
2319system.cpu1.dcache.demand_miss_rate::total 0.045119 # miss rate for demand accesses
2320system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045119 # miss rate for overall accesses
2321system.cpu1.dcache.overall_miss_rate::total 0.045119 # miss rate for overall accesses
2322system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15080.033207 # average ReadReq miss latency
2323system.cpu1.dcache.ReadReq_avg_miss_latency::total 15080.033207 # average ReadReq miss latency
2324system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23996.521681 # average WriteReq miss latency
2325system.cpu1.dcache.WriteReq_avg_miss_latency::total 23996.521681 # average WriteReq miss latency
2326system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18174.171993 # average LoadLockedReq miss latency
2327system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18174.171993 # average LoadLockedReq miss latency
2328system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23305.391483 # average StoreCondReq miss latency
2329system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23305.391483 # average StoreCondReq miss latency
2330system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency
2331system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2332system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency
2333system.cpu1.dcache.demand_avg_miss_latency::total 18947.796766 # average overall miss latency
2334system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency
2335system.cpu1.dcache.overall_avg_miss_latency::total 18947.796766 # average overall miss latency
2336system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2337system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2338system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2339system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
2340system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2341system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2342system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2343system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2344system.cpu1.dcache.writebacks::writebacks 115746 # number of writebacks
2345system.cpu1.dcache.writebacks::total 115746 # number of writebacks
2346system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15462 # number of ReadReq MSHR hits
2347system.cpu1.dcache.ReadReq_mshr_hits::total 15462 # number of ReadReq MSHR hits
2348system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49475 # number of WriteReq MSHR hits
2349system.cpu1.dcache.WriteReq_mshr_hits::total 49475 # number of WriteReq MSHR hits
2350system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64937 # number of demand (read+write) MSHR hits
2351system.cpu1.dcache.demand_mshr_hits::total 64937 # number of demand (read+write) MSHR hits
2352system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64937 # number of overall MSHR hits
2353system.cpu1.dcache.overall_mshr_hits::total 64937 # number of overall MSHR hits
2354system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166546 # number of ReadReq MSHR misses
2355system.cpu1.dcache.ReadReq_mshr_misses::total 166546 # number of ReadReq MSHR misses
2356system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89959 # number of WriteReq MSHR misses
2357system.cpu1.dcache.WriteReq_mshr_misses::total 89959 # number of WriteReq MSHR misses
2358system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5163 # number of LoadLockedReq MSHR misses
2359system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5163 # number of LoadLockedReq MSHR misses
2360system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23176 # number of StoreCondReq MSHR misses
2361system.cpu1.dcache.StoreCondReq_mshr_misses::total 23176 # number of StoreCondReq MSHR misses
2362system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256505 # number of demand (read+write) MSHR misses
2363system.cpu1.dcache.demand_mshr_misses::total 256505 # number of demand (read+write) MSHR misses
2364system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256505 # number of overall MSHR misses
2365system.cpu1.dcache.overall_mshr_misses::total 256505 # number of overall MSHR misses
2366system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202025254 # number of ReadReq MSHR miss cycles
2367system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202025254 # number of ReadReq MSHR miss cycles
2368system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2000006836 # number of WriteReq MSHR miss cycles
2369system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2000006836 # number of WriteReq MSHR miss cycles
2370system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83498750 # number of LoadLockedReq MSHR miss cycles
2371system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83498750 # number of LoadLockedReq MSHR miss cycles
2372system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492542247 # number of StoreCondReq MSHR miss cycles
2373system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492542247 # number of StoreCondReq MSHR miss cycles
2374system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 337500 # number of StoreCondFailReq MSHR miss cycles
2375system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 337500 # number of StoreCondFailReq MSHR miss cycles
2376system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4202032090 # number of demand (read+write) MSHR miss cycles
2377system.cpu1.dcache.demand_mshr_miss_latency::total 4202032090 # number of demand (read+write) MSHR miss cycles
2378system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4202032090 # number of overall MSHR miss cycles
2379system.cpu1.dcache.overall_mshr_miss_latency::total 4202032090 # number of overall MSHR miss cycles
2380system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329591498 # number of ReadReq MSHR uncacheable cycles
2381system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329591498 # number of ReadReq MSHR uncacheable cycles
2382system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202938498 # number of WriteReq MSHR uncacheable cycles
2383system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202938498 # number of WriteReq MSHR uncacheable cycles
2384system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532529996 # number of overall MSHR uncacheable cycles
2385system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532529996 # number of overall MSHR uncacheable cycles
2386system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042339 # mshr miss rate for ReadReq accesses
2387system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042339 # mshr miss rate for ReadReq accesses
2388system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028195 # mshr miss rate for WriteReq accesses
2389system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028195 # mshr miss rate for WriteReq accesses
2390system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054910 # mshr miss rate for LoadLockedReq accesses
2391system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054910 # mshr miss rate for LoadLockedReq accesses
2392system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250893 # mshr miss rate for StoreCondReq accesses
2393system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250893 # mshr miss rate for StoreCondReq accesses
2394system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for demand accesses
2395system.cpu1.dcache.demand_mshr_miss_rate::total 0.036004 # mshr miss rate for demand accesses
2396system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for overall accesses
2397system.cpu1.dcache.overall_mshr_miss_rate::total 0.036004 # mshr miss rate for overall accesses
2398system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13221.724052 # average ReadReq mshr miss latency
2399system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13221.724052 # average ReadReq mshr miss latency
2400system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22232.426283 # average WriteReq mshr miss latency
2401system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22232.426283 # average WriteReq mshr miss latency
2402system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16172.525663 # average LoadLockedReq mshr miss latency
2403system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16172.525663 # average LoadLockedReq mshr miss latency
2404system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21252.254358 # average StoreCondReq mshr miss latency
2405system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21252.254358 # average StoreCondReq mshr miss latency
2406system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
2407system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2408system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency
2409system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency
2410system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency
2411system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency
2412system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2413system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2414system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
2415system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2416system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2417system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2418system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
1731system.cpu1.toL2Bus.trans_dist::ReadReq 1582615 # Transaction distribution 1732system.cpu1.toL2Bus.trans_dist::ReadResp 1137834 # Transaction distribution 1733system.cpu1.toL2Bus.trans_dist::WriteReq 2120 # Transaction distribution 1734system.cpu1.toL2Bus.trans_dist::WriteResp 2120 # Transaction distribution 1735system.cpu1.toL2Bus.trans_dist::Writeback 115754 # Transaction distribution 1736system.cpu1.toL2Bus.trans_dist::HardPFReq 151048 # Transaction distribution 1737system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 1738system.cpu1.toL2Bus.trans_dist::UpgradeReq 84372 # Transaction distribution 1739system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41116 # Transaction distribution 1740system.cpu1.toL2Bus.trans_dist::UpgradeResp 85179 # Transaction distribution 1741system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 1742system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution 1743system.cpu1.toL2Bus.trans_dist::ReadExReq 76804 # Transaction distribution 1744system.cpu1.toL2Bus.trans_dist::ReadExResp 64396 # Transaction distribution 1745system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787314 # Packet count per connected master and slave (bytes) 1746system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 769072 # Packet count per connected master and slave (bytes) 1747system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6988 # Packet count per connected master and slave (bytes) 1748system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51360 # Packet count per connected master and slave (bytes) 1749system.cpu1.toL2Bus.pkt_count::total 2614734 # Packet count per connected master and slave (bytes) 1750system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57194048 # Cumulative packet size per connected master and slave (bytes) 1751system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24925415 # Cumulative packet size per connected master and slave (bytes) 1752system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10728 # Cumulative packet size per connected master and slave (bytes) 1753system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93220 # Cumulative packet size per connected master and slave (bytes) 1754system.cpu1.toL2Bus.pkt_size::total 82223411 # Cumulative packet size per connected master and slave (bytes) 1755system.cpu1.toL2Bus.snoops 838592 # Total snoops (count) 1756system.cpu1.toL2Bus.snoop_fanout::samples 2085067 # Request fanout histogram 1757system.cpu1.toL2Bus.snoop_fanout::mean 5.363773 # Request fanout histogram 1758system.cpu1.toL2Bus.snoop_fanout::stdev 0.481085 # Request fanout histogram 1759system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1760system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1761system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1762system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1763system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1764system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1765system.cpu1.toL2Bus.snoop_fanout::5 1326575 63.62% 63.62% # Request fanout histogram 1766system.cpu1.toL2Bus.snoop_fanout::6 758492 36.38% 100.00% # Request fanout histogram 1767system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1768system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1769system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1770system.cpu1.toL2Bus.snoop_fanout::total 2085067 # Request fanout histogram 1771system.cpu1.toL2Bus.reqLayer0.occupancy 782771935 # Layer occupancy (ticks) 1772system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1773system.cpu1.toL2Bus.snoopLayer0.occupancy 78513000 # Layer occupancy (ticks) 1774system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1775system.cpu1.toL2Bus.respLayer0.occupancy 1341710719 # Layer occupancy (ticks) 1776system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1777system.cpu1.toL2Bus.respLayer1.occupancy 381436893 # Layer occupancy (ticks) 1778system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1779system.cpu1.toL2Bus.respLayer2.occupancy 4307996 # Layer occupancy (ticks) 1780system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1781system.cpu1.toL2Bus.respLayer3.occupancy 28057498 # Layer occupancy (ticks) 1782system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1783system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 1784system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 1785system.iobus.trans_dist::WriteReq 59407 # Transaction distribution 1786system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 1787system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution 1788system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 1789system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1790system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1791system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1792system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1793system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1794system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1795system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1796system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1797system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1798system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1799system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1800system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1801system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1802system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1803system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1804system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1805system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1806system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1807system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1808system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1809system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) 1810system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 1811system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 1812system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) 1813system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 1814system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1815system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1816system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1817system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1818system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1819system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1820system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1821system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1822system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1823system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1824system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1825system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1826system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1827system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1828system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1829system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1830system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1831system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1832system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1833system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1834system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) 1835system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 1836system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 1837system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) 1838system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) 1839system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1840system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 1841system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1842system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1843system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1844system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1845system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1846system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1847system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1848system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1849system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1850system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1851system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1852system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1853system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1854system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1855system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1856system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1857system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1858system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1859system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1860system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1861system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1862system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1863system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1864system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1865system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1866system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1867system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1868system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1869system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1870system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1871system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1872system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1873system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1874system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1875system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1876system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1877system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1878system.iobus.reqLayer27.occupancy 326658321 # Layer occupancy (ticks) 1879system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1880system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1881system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1882system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) 1883system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1884system.iobus.respLayer3.occupancy 36824131 # Layer occupancy (ticks) 1885system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
1886system.iocache.tags.replacements 36417 # number of replacements
|
2420system.iocache.tags.tagsinuse 0.992209 # Cycle average of tags in use
|
1887system.iocache.tags.tagsinuse 0.992159 # Cycle average of tags in use |
1888system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1889system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. 1890system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1891system.iocache.tags.warmup_cycle 268855800000 # Cycle when the warmup percentage was hit.
|
2425system.iocache.tags.occ_blocks::realview.ide 0.992209 # Average occupied blocks per requestor
2426system.iocache.tags.occ_percent::realview.ide 0.062013 # Average percentage of cache occupancy
2427system.iocache.tags.occ_percent::total 0.062013 # Average percentage of cache occupancy
|
1892system.iocache.tags.occ_blocks::realview.ide 0.992159 # Average occupied blocks per requestor 1893system.iocache.tags.occ_percent::realview.ide 0.062010 # Average percentage of cache occupancy 1894system.iocache.tags.occ_percent::total 0.062010 # Average percentage of cache occupancy |
1895system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1896system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1897system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
2431system.iocache.tags.tag_accesses 328483 # Number of tag accesses
2432system.iocache.tags.data_accesses 328483 # Number of data accesses
|
1898system.iocache.tags.tag_accesses 328467 # Number of tag accesses 1899system.iocache.tags.data_accesses 328467 # Number of data accesses |
1900system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1901system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1902system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 1903system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
|
2437system.iocache.WriteInvalidateReq_misses::realview.ide 35 # number of WriteInvalidateReq misses
2438system.iocache.WriteInvalidateReq_misses::total 35 # number of WriteInvalidateReq misses
|
1904system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses 1905system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses |
1906system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 1907system.iocache.demand_misses::total 243 # number of demand (read+write) misses 1908system.iocache.overall_misses::realview.ide 243 # number of overall misses 1909system.iocache.overall_misses::total 243 # number of overall misses
|
2443system.iocache.ReadReq_miss_latency::realview.ide 31692627 # number of ReadReq miss cycles
2444system.iocache.ReadReq_miss_latency::total 31692627 # number of ReadReq miss cycles
2445system.iocache.demand_miss_latency::realview.ide 31692627 # number of demand (read+write) miss cycles
2446system.iocache.demand_miss_latency::total 31692627 # number of demand (read+write) miss cycles
2447system.iocache.overall_miss_latency::realview.ide 31692627 # number of overall miss cycles
2448system.iocache.overall_miss_latency::total 31692627 # number of overall miss cycles
|
1910system.iocache.ReadReq_miss_latency::realview.ide 31254127 # number of ReadReq miss cycles 1911system.iocache.ReadReq_miss_latency::total 31254127 # number of ReadReq miss cycles 1912system.iocache.demand_miss_latency::realview.ide 31254127 # number of demand (read+write) miss cycles 1913system.iocache.demand_miss_latency::total 31254127 # number of demand (read+write) miss cycles 1914system.iocache.overall_miss_latency::realview.ide 31254127 # number of overall miss cycles 1915system.iocache.overall_miss_latency::total 31254127 # number of overall miss cycles |
1916system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 1917system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
|
2451system.iocache.WriteInvalidateReq_accesses::realview.ide 36259 # number of WriteInvalidateReq accesses(hits+misses)
2452system.iocache.WriteInvalidateReq_accesses::total 36259 # number of WriteInvalidateReq accesses(hits+misses)
|
1918system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) 1919system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) |
1920system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 1921system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 1922system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 1923system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 1924system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1925system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
2459system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000965 # miss rate for WriteInvalidateReq accesses
2460system.iocache.WriteInvalidateReq_miss_rate::total 0.000965 # miss rate for WriteInvalidateReq accesses
|
1926system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses 1927system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses |
1928system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1929system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1930system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1931system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
2465system.iocache.ReadReq_avg_miss_latency::realview.ide 130422.333333 # average ReadReq miss latency
2466system.iocache.ReadReq_avg_miss_latency::total 130422.333333 # average ReadReq miss latency
2467system.iocache.demand_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency
2468system.iocache.demand_avg_miss_latency::total 130422.333333 # average overall miss latency
2469system.iocache.overall_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency
2470system.iocache.overall_avg_miss_latency::total 130422.333333 # average overall miss latency
|
1932system.iocache.ReadReq_avg_miss_latency::realview.ide 128617.806584 # average ReadReq miss latency 1933system.iocache.ReadReq_avg_miss_latency::total 128617.806584 # average ReadReq miss latency 1934system.iocache.demand_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency 1935system.iocache.demand_avg_miss_latency::total 128617.806584 # average overall miss latency 1936system.iocache.overall_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency 1937system.iocache.overall_avg_miss_latency::total 128617.806584 # average overall miss latency |
1938system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1939system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1940system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1941system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1942system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1943system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1944system.iocache.fast_writes 36224 # number of fast writes performed 1945system.iocache.cache_copies 0 # number of cache copies performed 1946system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 1947system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 1948system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 1949system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 1950system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 1951system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
|
2485system.iocache.ReadReq_mshr_miss_latency::realview.ide 19056127 # number of ReadReq MSHR miss cycles
2486system.iocache.ReadReq_mshr_miss_latency::total 19056127 # number of ReadReq MSHR miss cycles
2487system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2259252335 # number of WriteInvalidateReq MSHR miss cycles
2488system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2259252335 # number of WriteInvalidateReq MSHR miss cycles
2489system.iocache.demand_mshr_miss_latency::realview.ide 19056127 # number of demand (read+write) MSHR miss cycles
2490system.iocache.demand_mshr_miss_latency::total 19056127 # number of demand (read+write) MSHR miss cycles
2491system.iocache.overall_mshr_miss_latency::realview.ide 19056127 # number of overall MSHR miss cycles
2492system.iocache.overall_mshr_miss_latency::total 19056127 # number of overall MSHR miss cycles
|
1952system.iocache.ReadReq_mshr_miss_latency::realview.ide 18617627 # number of ReadReq MSHR miss cycles 1953system.iocache.ReadReq_mshr_miss_latency::total 18617627 # number of ReadReq MSHR miss cycles 1954system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2261621825 # number of WriteInvalidateReq MSHR miss cycles 1955system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2261621825 # number of WriteInvalidateReq MSHR miss cycles 1956system.iocache.demand_mshr_miss_latency::realview.ide 18617627 # number of demand (read+write) MSHR miss cycles 1957system.iocache.demand_mshr_miss_latency::total 18617627 # number of demand (read+write) MSHR miss cycles 1958system.iocache.overall_mshr_miss_latency::realview.ide 18617627 # number of overall MSHR miss cycles 1959system.iocache.overall_mshr_miss_latency::total 18617627 # number of overall MSHR miss cycles |
1960system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1961system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1962system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1963system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1964system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1965system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
2499system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78420.275720 # average ReadReq mshr miss latency
2500system.iocache.ReadReq_avg_mshr_miss_latency::total 78420.275720 # average ReadReq mshr miss latency
|
1966system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76615.748971 # average ReadReq mshr miss latency 1967system.iocache.ReadReq_avg_mshr_miss_latency::total 76615.748971 # average ReadReq mshr miss latency |
1968system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1969system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
2503system.iocache.demand_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency
2504system.iocache.demand_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency
2505system.iocache.overall_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency
2506system.iocache.overall_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency
|
1970system.iocache.demand_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency 1971system.iocache.demand_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency 1972system.iocache.overall_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency 1973system.iocache.overall_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency |
1974system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
1975system.l2c.tags.replacements 151810 # number of replacements 1976system.l2c.tags.tagsinuse 64480.586594 # Cycle average of tags in use 1977system.l2c.tags.total_refs 529933 # Total number of references to valid blocks. 1978system.l2c.tags.sampled_refs 216565 # Sample count of references to valid blocks. 1979system.l2c.tags.avg_refs 2.446993 # Average number of references to valid blocks. 1980system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1981system.l2c.tags.occ_blocks::writebacks 12374.174406 # Average occupied blocks per requestor 1982system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831156 # Average occupied blocks per requestor 1983system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030524 # Average occupied blocks per requestor 1984system.l2c.tags.occ_blocks::cpu0.inst 3874.361594 # Average occupied blocks per requestor 1985system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42727.383721 # Average occupied blocks per requestor 1986system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.891665 # Average occupied blocks per requestor 1987system.l2c.tags.occ_blocks::cpu1.inst 757.615436 # Average occupied blocks per requestor 1988system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4654.298093 # Average occupied blocks per requestor 1989system.l2c.tags.occ_percent::writebacks 0.188815 # Average percentage of cache occupancy 1990system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy 1991system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1992system.l2c.tags.occ_percent::cpu0.inst 0.059118 # Average percentage of cache occupancy 1993system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.651968 # Average percentage of cache occupancy 1994system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy 1995system.l2c.tags.occ_percent::cpu1.inst 0.011560 # Average percentage of cache occupancy 1996system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071019 # Average percentage of cache occupancy 1997system.l2c.tags.occ_percent::total 0.983896 # Average percentage of cache occupancy 1998system.l2c.tags.occ_task_id_blocks::1022 46322 # Occupied blocks per task id 1999system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id 2000system.l2c.tags.occ_task_id_blocks::1024 18386 # Occupied blocks per task id 2001system.l2c.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id 2002system.l2c.tags.age_task_id_blocks_1022::3 6596 # Occupied blocks per task id 2003system.l2c.tags.age_task_id_blocks_1022::4 39440 # Occupied blocks per task id 2004system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id 2005system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 2006system.l2c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 2007system.l2c.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id 2008system.l2c.tags.age_task_id_blocks_1024::3 2604 # Occupied blocks per task id 2009system.l2c.tags.age_task_id_blocks_1024::4 15495 # Occupied blocks per task id 2010system.l2c.tags.occ_task_id_percent::1022 0.706818 # Percentage of cache occupancy per task id 2011system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id 2012system.l2c.tags.occ_task_id_percent::1024 0.280548 # Percentage of cache occupancy per task id 2013system.l2c.tags.tag_accesses 6644341 # Number of tag accesses 2014system.l2c.tags.data_accesses 6644341 # Number of data accesses 2015system.l2c.ReadReq_hits::cpu0.dtb.walker 563 # number of ReadReq hits 2016system.l2c.ReadReq_hits::cpu0.itb.walker 116 # number of ReadReq hits 2017system.l2c.ReadReq_hits::cpu0.inst 36701 # number of ReadReq hits 2018system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207577 # number of ReadReq hits 2019system.l2c.ReadReq_hits::cpu1.dtb.walker 129 # number of ReadReq hits 2020system.l2c.ReadReq_hits::cpu1.itb.walker 56 # number of ReadReq hits 2021system.l2c.ReadReq_hits::cpu1.inst 11433 # number of ReadReq hits 2022system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45418 # number of ReadReq hits 2023system.l2c.ReadReq_hits::total 301993 # number of ReadReq hits 2024system.l2c.Writeback_hits::writebacks 252536 # number of Writeback hits 2025system.l2c.Writeback_hits::total 252536 # number of Writeback hits 2026system.l2c.UpgradeReq_hits::cpu0.inst 11942 # number of UpgradeReq hits 2027system.l2c.UpgradeReq_hits::cpu1.inst 830 # number of UpgradeReq hits 2028system.l2c.UpgradeReq_hits::total 12772 # number of UpgradeReq hits 2029system.l2c.SCUpgradeReq_hits::cpu0.inst 205 # number of SCUpgradeReq hits 2030system.l2c.SCUpgradeReq_hits::cpu1.inst 179 # number of SCUpgradeReq hits 2031system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits 2032system.l2c.ReadExReq_hits::cpu0.inst 3525 # number of ReadExReq hits 2033system.l2c.ReadExReq_hits::cpu1.inst 1107 # number of ReadExReq hits 2034system.l2c.ReadExReq_hits::total 4632 # number of ReadExReq hits 2035system.l2c.demand_hits::cpu0.dtb.walker 563 # number of demand (read+write) hits 2036system.l2c.demand_hits::cpu0.itb.walker 116 # number of demand (read+write) hits 2037system.l2c.demand_hits::cpu0.inst 40226 # number of demand (read+write) hits 2038system.l2c.demand_hits::cpu0.l2cache.prefetcher 207577 # number of demand (read+write) hits 2039system.l2c.demand_hits::cpu1.dtb.walker 129 # number of demand (read+write) hits 2040system.l2c.demand_hits::cpu1.itb.walker 56 # number of demand (read+write) hits 2041system.l2c.demand_hits::cpu1.inst 12540 # number of demand (read+write) hits 2042system.l2c.demand_hits::cpu1.l2cache.prefetcher 45418 # number of demand (read+write) hits 2043system.l2c.demand_hits::total 306625 # number of demand (read+write) hits 2044system.l2c.overall_hits::cpu0.dtb.walker 563 # number of overall hits 2045system.l2c.overall_hits::cpu0.itb.walker 116 # number of overall hits 2046system.l2c.overall_hits::cpu0.inst 40226 # number of overall hits 2047system.l2c.overall_hits::cpu0.l2cache.prefetcher 207577 # number of overall hits 2048system.l2c.overall_hits::cpu1.dtb.walker 129 # number of overall hits 2049system.l2c.overall_hits::cpu1.itb.walker 56 # number of overall hits 2050system.l2c.overall_hits::cpu1.inst 12540 # number of overall hits 2051system.l2c.overall_hits::cpu1.l2cache.prefetcher 45418 # number of overall hits 2052system.l2c.overall_hits::total 306625 # number of overall hits 2053system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses 2054system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses 2055system.l2c.ReadReq_misses::cpu0.inst 11286 # number of ReadReq misses 2056system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq misses 2057system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses 2058system.l2c.ReadReq_misses::cpu1.inst 1852 # number of ReadReq misses 2059system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18208 # number of ReadReq misses 2060system.l2c.ReadReq_misses::total 199810 # number of ReadReq misses 2061system.l2c.UpgradeReq_misses::cpu0.inst 9028 # number of UpgradeReq misses 2062system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses 2063system.l2c.UpgradeReq_misses::total 11693 # number of UpgradeReq misses 2064system.l2c.SCUpgradeReq_misses::cpu0.inst 461 # number of SCUpgradeReq misses 2065system.l2c.SCUpgradeReq_misses::cpu1.inst 1254 # number of SCUpgradeReq misses 2066system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses 2067system.l2c.ReadExReq_misses::cpu0.inst 7011 # number of ReadExReq misses 2068system.l2c.ReadExReq_misses::cpu1.inst 6410 # number of ReadExReq misses 2069system.l2c.ReadExReq_misses::total 13421 # number of ReadExReq misses 2070system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses 2071system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2072system.l2c.demand_misses::cpu0.inst 18297 # number of demand (read+write) misses 2073system.l2c.demand_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) misses 2074system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses 2075system.l2c.demand_misses::cpu1.inst 8262 # number of demand (read+write) misses 2076system.l2c.demand_misses::cpu1.l2cache.prefetcher 18208 # number of demand (read+write) misses 2077system.l2c.demand_misses::total 213231 # number of demand (read+write) misses 2078system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses 2079system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2080system.l2c.overall_misses::cpu0.inst 18297 # number of overall misses 2081system.l2c.overall_misses::cpu0.l2cache.prefetcher 168297 # number of overall misses 2082system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses 2083system.l2c.overall_misses::cpu1.inst 8262 # number of overall misses 2084system.l2c.overall_misses::cpu1.l2cache.prefetcher 18208 # number of overall misses 2085system.l2c.overall_misses::total 213231 # number of overall misses 2086system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles 2087system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles 2088system.l2c.ReadReq_miss_latency::cpu0.inst 955847998 # number of ReadReq miss cycles 2089system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of ReadReq miss cycles 2090system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1150500 # number of ReadReq miss cycles 2091system.l2c.ReadReq_miss_latency::cpu1.inst 151717498 # number of ReadReq miss cycles 2092system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of ReadReq miss cycles 2093system.l2c.ReadReq_miss_latency::total 21276600608 # number of ReadReq miss cycles 2094system.l2c.UpgradeReq_miss_latency::cpu0.inst 10528075 # number of UpgradeReq miss cycles 2095system.l2c.UpgradeReq_miss_latency::cpu1.inst 2736385 # number of UpgradeReq miss cycles 2096system.l2c.UpgradeReq_miss_latency::total 13264460 # number of UpgradeReq miss cycles 2097system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1131453 # number of SCUpgradeReq miss cycles 2098system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1006958 # number of SCUpgradeReq miss cycles 2099system.l2c.SCUpgradeReq_miss_latency::total 2138411 # number of SCUpgradeReq miss cycles 2100system.l2c.ReadExReq_miss_latency::cpu0.inst 592519659 # number of ReadExReq miss cycles 2101system.l2c.ReadExReq_miss_latency::cpu1.inst 475914481 # number of ReadExReq miss cycles 2102system.l2c.ReadExReq_miss_latency::total 1068434140 # number of ReadExReq miss cycles 2103system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles 2104system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles 2105system.l2c.demand_miss_latency::cpu0.inst 1548367657 # number of demand (read+write) miss cycles 2106system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of demand (read+write) miss cycles 2107system.l2c.demand_miss_latency::cpu1.dtb.walker 1150500 # number of demand (read+write) miss cycles 2108system.l2c.demand_miss_latency::cpu1.inst 627631979 # number of demand (read+write) miss cycles 2109system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of demand (read+write) miss cycles 2110system.l2c.demand_miss_latency::total 22345034748 # number of demand (read+write) miss cycles 2111system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles 2112system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles 2113system.l2c.overall_miss_latency::cpu0.inst 1548367657 # number of overall miss cycles 2114system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of overall miss cycles 2115system.l2c.overall_miss_latency::cpu1.dtb.walker 1150500 # number of overall miss cycles 2116system.l2c.overall_miss_latency::cpu1.inst 627631979 # number of overall miss cycles 2117system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of overall miss cycles 2118system.l2c.overall_miss_latency::total 22345034748 # number of overall miss cycles 2119system.l2c.ReadReq_accesses::cpu0.dtb.walker 714 # number of ReadReq accesses(hits+misses) 2120system.l2c.ReadReq_accesses::cpu0.itb.walker 117 # number of ReadReq accesses(hits+misses) 2121system.l2c.ReadReq_accesses::cpu0.inst 47987 # number of ReadReq accesses(hits+misses) 2122system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 375874 # number of ReadReq accesses(hits+misses) 2123system.l2c.ReadReq_accesses::cpu1.dtb.walker 144 # number of ReadReq accesses(hits+misses) 2124system.l2c.ReadReq_accesses::cpu1.itb.walker 56 # number of ReadReq accesses(hits+misses) 2125system.l2c.ReadReq_accesses::cpu1.inst 13285 # number of ReadReq accesses(hits+misses) 2126system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63626 # number of ReadReq accesses(hits+misses) 2127system.l2c.ReadReq_accesses::total 501803 # number of ReadReq accesses(hits+misses) 2128system.l2c.Writeback_accesses::writebacks 252536 # number of Writeback accesses(hits+misses) 2129system.l2c.Writeback_accesses::total 252536 # number of Writeback accesses(hits+misses) 2130system.l2c.UpgradeReq_accesses::cpu0.inst 20970 # number of UpgradeReq accesses(hits+misses) 2131system.l2c.UpgradeReq_accesses::cpu1.inst 3495 # number of UpgradeReq accesses(hits+misses) 2132system.l2c.UpgradeReq_accesses::total 24465 # number of UpgradeReq accesses(hits+misses) 2133system.l2c.SCUpgradeReq_accesses::cpu0.inst 666 # number of SCUpgradeReq accesses(hits+misses) 2134system.l2c.SCUpgradeReq_accesses::cpu1.inst 1433 # number of SCUpgradeReq accesses(hits+misses) 2135system.l2c.SCUpgradeReq_accesses::total 2099 # number of SCUpgradeReq accesses(hits+misses) 2136system.l2c.ReadExReq_accesses::cpu0.inst 10536 # number of ReadExReq accesses(hits+misses) 2137system.l2c.ReadExReq_accesses::cpu1.inst 7517 # number of ReadExReq accesses(hits+misses) 2138system.l2c.ReadExReq_accesses::total 18053 # number of ReadExReq accesses(hits+misses) 2139system.l2c.demand_accesses::cpu0.dtb.walker 714 # number of demand (read+write) accesses 2140system.l2c.demand_accesses::cpu0.itb.walker 117 # number of demand (read+write) accesses 2141system.l2c.demand_accesses::cpu0.inst 58523 # number of demand (read+write) accesses 2142system.l2c.demand_accesses::cpu0.l2cache.prefetcher 375874 # number of demand (read+write) accesses 2143system.l2c.demand_accesses::cpu1.dtb.walker 144 # number of demand (read+write) accesses 2144system.l2c.demand_accesses::cpu1.itb.walker 56 # number of demand (read+write) accesses 2145system.l2c.demand_accesses::cpu1.inst 20802 # number of demand (read+write) accesses 2146system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63626 # number of demand (read+write) accesses 2147system.l2c.demand_accesses::total 519856 # number of demand (read+write) accesses 2148system.l2c.overall_accesses::cpu0.dtb.walker 714 # number of overall (read+write) accesses 2149system.l2c.overall_accesses::cpu0.itb.walker 117 # number of overall (read+write) accesses 2150system.l2c.overall_accesses::cpu0.inst 58523 # number of overall (read+write) accesses 2151system.l2c.overall_accesses::cpu0.l2cache.prefetcher 375874 # number of overall (read+write) accesses 2152system.l2c.overall_accesses::cpu1.dtb.walker 144 # number of overall (read+write) accesses 2153system.l2c.overall_accesses::cpu1.itb.walker 56 # number of overall (read+write) accesses 2154system.l2c.overall_accesses::cpu1.inst 20802 # number of overall (read+write) accesses 2155system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63626 # number of overall (read+write) accesses 2156system.l2c.overall_accesses::total 519856 # number of overall (read+write) accesses 2157system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for ReadReq accesses 2158system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008547 # miss rate for ReadReq accesses 2159system.l2c.ReadReq_miss_rate::cpu0.inst 0.235189 # miss rate for ReadReq accesses 2160system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for ReadReq accesses 2161system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for ReadReq accesses 2162system.l2c.ReadReq_miss_rate::cpu1.inst 0.139405 # miss rate for ReadReq accesses 2163system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for ReadReq accesses 2164system.l2c.ReadReq_miss_rate::total 0.398184 # miss rate for ReadReq accesses 2165system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430520 # miss rate for UpgradeReq accesses 2166system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.762518 # miss rate for UpgradeReq accesses 2167system.l2c.UpgradeReq_miss_rate::total 0.477948 # miss rate for UpgradeReq accesses 2168system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.692192 # miss rate for SCUpgradeReq accesses 2169system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.875087 # miss rate for SCUpgradeReq accesses 2170system.l2c.SCUpgradeReq_miss_rate::total 0.817056 # miss rate for SCUpgradeReq accesses 2171system.l2c.ReadExReq_miss_rate::cpu0.inst 0.665433 # miss rate for ReadExReq accesses 2172system.l2c.ReadExReq_miss_rate::cpu1.inst 0.852734 # miss rate for ReadExReq accesses 2173system.l2c.ReadExReq_miss_rate::total 0.743422 # miss rate for ReadExReq accesses 2174system.l2c.demand_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for demand accesses 2175system.l2c.demand_miss_rate::cpu0.itb.walker 0.008547 # miss rate for demand accesses 2176system.l2c.demand_miss_rate::cpu0.inst 0.312646 # miss rate for demand accesses 2177system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for demand accesses 2178system.l2c.demand_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for demand accesses 2179system.l2c.demand_miss_rate::cpu1.inst 0.397173 # miss rate for demand accesses 2180system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for demand accesses 2181system.l2c.demand_miss_rate::total 0.410173 # miss rate for demand accesses 2182system.l2c.overall_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for overall accesses 2183system.l2c.overall_miss_rate::cpu0.itb.walker 0.008547 # miss rate for overall accesses 2184system.l2c.overall_miss_rate::cpu0.inst 0.312646 # miss rate for overall accesses 2185system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for overall accesses 2186system.l2c.overall_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for overall accesses 2187system.l2c.overall_miss_rate::cpu1.inst 0.397173 # miss rate for overall accesses 2188system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for overall accesses 2189system.l2c.overall_miss_rate::total 0.410173 # miss rate for overall accesses 2190system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency 2191system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency 2192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84693.248095 # average ReadReq miss latency 2193system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average ReadReq miss latency 2194system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76700 # average ReadReq miss latency 2195system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81920.895248 # average ReadReq miss latency 2196system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average ReadReq miss latency 2197system.l2c.ReadReq_avg_miss_latency::total 106484.162995 # average ReadReq miss latency 2198system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1166.158064 # average UpgradeReq miss latency 2199system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1026.786116 # average UpgradeReq miss latency 2200system.l2c.UpgradeReq_avg_miss_latency::total 1134.393227 # average UpgradeReq miss latency 2201system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2454.344902 # average SCUpgradeReq miss latency 2202system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 802.996810 # average SCUpgradeReq miss latency 2203system.l2c.SCUpgradeReq_avg_miss_latency::total 1246.886880 # average SCUpgradeReq miss latency 2204system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84512.859649 # average ReadExReq miss latency 2205system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74245.628861 # average ReadExReq miss latency 2206system.l2c.ReadExReq_avg_miss_latency::total 79609.130467 # average ReadExReq miss latency 2207system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency 2208system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 2209system.l2c.demand_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency 2210system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency 2211system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency 2212system.l2c.demand_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency 2213system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency 2214system.l2c.demand_avg_miss_latency::total 104792.618090 # average overall miss latency 2215system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency 2216system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 2217system.l2c.overall_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency 2218system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency 2219system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency 2220system.l2c.overall_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency 2221system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency 2222system.l2c.overall_avg_miss_latency::total 104792.618090 # average overall miss latency 2223system.l2c.blocked_cycles::no_mshrs 845 # number of cycles access was blocked 2224system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2225system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked 2226system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2227system.l2c.avg_blocked_cycles::no_mshrs 32.500000 # average number of cycles each access was blocked 2228system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2229system.l2c.fast_writes 0 # number of fast writes performed 2230system.l2c.cache_copies 0 # number of cache copies performed 2231system.l2c.writebacks::writebacks 112127 # number of writebacks 2232system.l2c.writebacks::total 112127 # number of writebacks 2233system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits 2234system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2235system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 2236system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 2237system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits 2238system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 2239system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses 2240system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses 2241system.l2c.ReadReq_mshr_misses::cpu0.inst 11286 # number of ReadReq MSHR misses 2242system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq MSHR misses 2243system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses 2244system.l2c.ReadReq_mshr_misses::cpu1.inst 1852 # number of ReadReq MSHR misses 2245system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of ReadReq MSHR misses 2246system.l2c.ReadReq_mshr_misses::total 199809 # number of ReadReq MSHR misses 2247system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9028 # number of UpgradeReq MSHR misses 2248system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses 2249system.l2c.UpgradeReq_mshr_misses::total 11693 # number of UpgradeReq MSHR misses 2250system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 461 # number of SCUpgradeReq MSHR misses 2251system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1254 # number of SCUpgradeReq MSHR misses 2252system.l2c.SCUpgradeReq_mshr_misses::total 1715 # number of SCUpgradeReq MSHR misses 2253system.l2c.ReadExReq_mshr_misses::cpu0.inst 7011 # number of ReadExReq MSHR misses 2254system.l2c.ReadExReq_mshr_misses::cpu1.inst 6410 # number of ReadExReq MSHR misses 2255system.l2c.ReadExReq_mshr_misses::total 13421 # number of ReadExReq MSHR misses 2256system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses 2257system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2258system.l2c.demand_mshr_misses::cpu0.inst 18297 # number of demand (read+write) MSHR misses 2259system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) MSHR misses 2260system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses 2261system.l2c.demand_mshr_misses::cpu1.inst 8262 # number of demand (read+write) MSHR misses 2262system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of demand (read+write) MSHR misses 2263system.l2c.demand_mshr_misses::total 213230 # number of demand (read+write) MSHR misses 2264system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses 2265system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2266system.l2c.overall_mshr_misses::cpu0.inst 18297 # number of overall MSHR misses 2267system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of overall MSHR misses 2268system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses 2269system.l2c.overall_mshr_misses::cpu1.inst 8262 # number of overall MSHR misses 2270system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of overall MSHR misses 2271system.l2c.overall_mshr_misses::total 213230 # number of overall MSHR misses 2272system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of ReadReq MSHR miss cycles 2273system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles 2274system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 815475498 # number of ReadReq MSHR miss cycles 2275system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of ReadReq MSHR miss cycles 2276system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 965000 # number of ReadReq MSHR miss cycles 2277system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 128728998 # number of ReadReq MSHR miss cycles 2278system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of ReadReq MSHR miss cycles 2279system.l2c.ReadReq_mshr_miss_latency::total 18816537858 # number of ReadReq MSHR miss cycles 2280system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91196953 # number of UpgradeReq MSHR miss cycles 2281system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26828647 # number of UpgradeReq MSHR miss cycles 2282system.l2c.UpgradeReq_mshr_miss_latency::total 118025600 # number of UpgradeReq MSHR miss cycles 2283system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4664957 # number of SCUpgradeReq MSHR miss cycles 2284system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12607247 # number of SCUpgradeReq MSHR miss cycles 2285system.l2c.SCUpgradeReq_mshr_miss_latency::total 17272204 # number of SCUpgradeReq MSHR miss cycles 2286system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 505062337 # number of ReadExReq MSHR miss cycles 2287system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 394979019 # number of ReadExReq MSHR miss cycles 2288system.l2c.ReadExReq_mshr_miss_latency::total 900041356 # number of ReadExReq MSHR miss cycles 2289system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles 2290system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 2291system.l2c.demand_mshr_miss_latency::cpu0.inst 1320537835 # number of demand (read+write) MSHR miss cycles 2292system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of demand (read+write) MSHR miss cycles 2293system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 965000 # number of demand (read+write) MSHR miss cycles 2294system.l2c.demand_mshr_miss_latency::cpu1.inst 523708017 # number of demand (read+write) MSHR miss cycles 2295system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of demand (read+write) MSHR miss cycles 2296system.l2c.demand_mshr_miss_latency::total 19716579214 # number of demand (read+write) MSHR miss cycles 2297system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles 2298system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles 2299system.l2c.overall_mshr_miss_latency::cpu0.inst 1320537835 # number of overall MSHR miss cycles 2300system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of overall MSHR miss cycles 2301system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 965000 # number of overall MSHR miss cycles 2302system.l2c.overall_mshr_miss_latency::cpu1.inst 523708017 # number of overall MSHR miss cycles 2303system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of overall MSHR miss cycles 2304system.l2c.overall_mshr_miss_latency::total 19716579214 # number of overall MSHR miss cycles 2305system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518590247 # number of ReadReq MSHR uncacheable cycles 2306system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263108750 # number of ReadReq MSHR uncacheable cycles 2307system.l2c.ReadReq_mshr_uncacheable_latency::total 5781698997 # number of ReadReq MSHR uncacheable cycles 2308system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4096001500 # number of WriteReq MSHR uncacheable cycles 2309system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150494000 # number of WriteReq MSHR uncacheable cycles 2310system.l2c.WriteReq_mshr_uncacheable_latency::total 4246495500 # number of WriteReq MSHR uncacheable cycles 2311system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614591747 # number of overall MSHR uncacheable cycles 2312system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413602750 # number of overall MSHR uncacheable cycles 2313system.l2c.overall_mshr_uncacheable_latency::total 10028194497 # number of overall MSHR uncacheable cycles 2314system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for ReadReq accesses 2315system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for ReadReq accesses 2316system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235189 # mshr miss rate for ReadReq accesses 2317system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for ReadReq accesses 2318system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for ReadReq accesses 2319system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.139405 # mshr miss rate for ReadReq accesses 2320system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for ReadReq accesses 2321system.l2c.ReadReq_mshr_miss_rate::total 0.398182 # mshr miss rate for ReadReq accesses 2322system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430520 # mshr miss rate for UpgradeReq accesses 2323system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.762518 # mshr miss rate for UpgradeReq accesses 2324system.l2c.UpgradeReq_mshr_miss_rate::total 0.477948 # mshr miss rate for UpgradeReq accesses 2325system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.692192 # mshr miss rate for SCUpgradeReq accesses 2326system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.875087 # mshr miss rate for SCUpgradeReq accesses 2327system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817056 # mshr miss rate for SCUpgradeReq accesses 2328system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.665433 # mshr miss rate for ReadExReq accesses 2329system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.852734 # mshr miss rate for ReadExReq accesses 2330system.l2c.ReadExReq_mshr_miss_rate::total 0.743422 # mshr miss rate for ReadExReq accesses 2331system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for demand accesses 2332system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for demand accesses 2333system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for demand accesses 2334system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for demand accesses 2335system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for demand accesses 2336system.l2c.demand_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for demand accesses 2337system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for demand accesses 2338system.l2c.demand_mshr_miss_rate::total 0.410171 # mshr miss rate for demand accesses 2339system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for overall accesses 2340system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for overall accesses 2341system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for overall accesses 2342system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for overall accesses 2343system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for overall accesses 2344system.l2c.overall_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for overall accesses 2345system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for overall accesses 2346system.l2c.overall_mshr_miss_rate::total 0.410171 # mshr miss rate for overall accesses 2347system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency 2348system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 2349system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72255.493355 # average ReadReq mshr miss latency 2350system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average ReadReq mshr miss latency 2351system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average ReadReq mshr miss latency 2352system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69508.098272 # average ReadReq mshr miss latency 2353system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average ReadReq mshr miss latency 2354system.l2c.ReadReq_avg_mshr_miss_latency::total 94172.624146 # average ReadReq mshr miss latency 2355system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10101.567678 # average UpgradeReq mshr miss latency 2356system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10067.034522 # average UpgradeReq mshr miss latency 2357system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.697084 # average UpgradeReq mshr miss latency 2358system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10119.212581 # average SCUpgradeReq mshr miss latency 2359system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10053.625997 # average SCUpgradeReq mshr miss latency 2360system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.255977 # average SCUpgradeReq mshr miss latency 2361system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72038.558979 # average ReadExReq mshr miss latency 2362system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61619.191732 # average ReadExReq mshr miss latency 2363system.l2c.ReadExReq_avg_mshr_miss_latency::total 67062.167946 # average ReadExReq mshr miss latency 2364system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency 2365system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2366system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency 2367system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency 2368system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency 2369system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency 2370system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency 2371system.l2c.demand_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency 2372system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency 2373system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2374system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency 2375system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency 2376system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency 2377system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency 2378system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency 2379system.l2c.overall_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency 2380system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2381system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2382system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2383system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 2384system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2385system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2386system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2387system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2388system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2389system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2390system.membus.trans_dist::ReadReq 238091 # Transaction distribution 2391system.membus.trans_dist::ReadResp 238091 # Transaction distribution 2392system.membus.trans_dist::WriteReq 30933 # Transaction distribution 2393system.membus.trans_dist::WriteResp 30933 # Transaction distribution 2394system.membus.trans_dist::Writeback 112127 # Transaction distribution 2395system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2396system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2397system.membus.trans_dist::UpgradeReq 79652 # Transaction distribution 2398system.membus.trans_dist::SCUpgradeReq 39985 # Transaction distribution 2399system.membus.trans_dist::UpgradeResp 13516 # Transaction distribution 2400system.membus.trans_dist::ReadExReq 30363 # Transaction distribution 2401system.membus.trans_dist::ReadExResp 13313 # Transaction distribution 2402system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) 2403system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) 2404system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13576 # Packet count per connected master and slave (bytes) 2405system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704934 # Packet count per connected master and slave (bytes) 2406system.membus.pkt_count_system.l2c.mem_side::total 826518 # Packet count per connected master and slave (bytes) 2407system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes) 2408system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes) 2409system.membus.pkt_count::total 899224 # Packet count per connected master and slave (bytes) 2410system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) 2411system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) 2412system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27152 # Cumulative packet size per connected master and slave (bytes) 2413system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21038188 # Cumulative packet size per connected master and slave (bytes) 2414system.membus.pkt_size_system.l2c.mem_side::total 21229406 # Cumulative packet size per connected master and slave (bytes) 2415system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 2416system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 2417system.membus.pkt_size::total 23548702 # Cumulative packet size per connected master and slave (bytes) 2418system.membus.snoops 123399 # Total snoops (count) 2419system.membus.snoop_fanout::samples 498406 # Request fanout histogram 2420system.membus.snoop_fanout::mean 1 # Request fanout histogram 2421system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2422system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2423system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2424system.membus.snoop_fanout::1 498406 100.00% 100.00% # Request fanout histogram 2425system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2426system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2427system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2428system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2429system.membus.snoop_fanout::total 498406 # Request fanout histogram 2430system.membus.reqLayer0.occupancy 87864494 # Layer occupancy (ticks) 2431system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2432system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) 2433system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2434system.membus.reqLayer2.occupancy 11666999 # Layer occupancy (ticks) 2435system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2436system.membus.reqLayer5.occupancy 1620379248 # Layer occupancy (ticks) 2437system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 2438system.membus.respLayer2.occupancy 2120601580 # Layer occupancy (ticks) 2439system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 2440system.membus.respLayer3.occupancy 38542869 # Layer occupancy (ticks) 2441system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2442system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2443system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2444system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2445system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2446system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2447system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2448system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2449system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2450system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2451system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2452system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2453system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2454system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2455system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2456system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2457system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2458system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2459system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2460system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2461system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2462system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2463system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2464system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2465system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2466system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2467system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2468system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2469system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2470system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2471system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2472system.realview.ethernet.droppedPackets 0 # number of packets dropped 2473system.toL2Bus.trans_dist::ReadReq 668340 # Transaction distribution 2474system.toL2Bus.trans_dist::ReadResp 668325 # Transaction distribution 2475system.toL2Bus.trans_dist::WriteReq 30933 # Transaction distribution 2476system.toL2Bus.trans_dist::WriteResp 30933 # Transaction distribution 2477system.toL2Bus.trans_dist::Writeback 252536 # Transaction distribution 2478system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 2479system.toL2Bus.trans_dist::UpgradeReq 92316 # Transaction distribution 2480system.toL2Bus.trans_dist::SCUpgradeReq 40369 # Transaction distribution 2481system.toL2Bus.trans_dist::UpgradeResp 132685 # Transaction distribution 2482system.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution 2483system.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution 2484system.toL2Bus.trans_dist::ReadExReq 38932 # Transaction distribution 2485system.toL2Bus.trans_dist::ReadExResp 38932 # Transaction distribution 2486system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370044 # Packet count per connected master and slave (bytes) 2487system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368770 # Packet count per connected master and slave (bytes) 2488system.toL2Bus.pkt_count::total 1738814 # Packet count per connected master and slave (bytes) 2489system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41959415 # Cumulative packet size per connected master and slave (bytes) 2490system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7901735 # Cumulative packet size per connected master and slave (bytes) 2491system.toL2Bus.pkt_size::total 49861150 # Cumulative packet size per connected master and slave (bytes) 2492system.toL2Bus.snoops 291964 # Total snoops (count) 2493system.toL2Bus.snoop_fanout::samples 1090717 # Request fanout histogram 2494system.toL2Bus.snoop_fanout::mean 1.033437 # Request fanout histogram 2495system.toL2Bus.snoop_fanout::stdev 0.179774 # Request fanout histogram 2496system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2497system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2498system.toL2Bus.snoop_fanout::1 1054247 96.66% 96.66% # Request fanout histogram 2499system.toL2Bus.snoop_fanout::2 36470 3.34% 100.00% # Request fanout histogram 2500system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2501system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2502system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2503system.toL2Bus.snoop_fanout::total 1090717 # Request fanout histogram 2504system.toL2Bus.reqLayer0.occupancy 1589301055 # Layer occupancy (ticks) 2505system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2506system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) 2507system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2508system.toL2Bus.respLayer0.occupancy 2361799867 # Layer occupancy (ticks) 2509system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2510system.toL2Bus.respLayer1.occupancy 804005619 # Layer occupancy (ticks) 2511system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
2512 2513---------- End Simulation Statistics ----------
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