7,11c7,11
< host_inst_rate 194660 # Simulator instruction rate (inst/s)
< host_op_rate 235713 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4372273286 # Simulator tick rate (ticks/s)
< host_mem_usage 620428 # Number of bytes of host memory used
< host_seconds 651.58 # Real time elapsed on the host
---
> host_inst_rate 186843 # Simulator instruction rate (inst/s)
> host_op_rate 226247 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4196685224 # Simulator tick rate (ticks/s)
> host_mem_usage 620168 # Number of bytes of host memory used
> host_seconds 678.84 # Real time elapsed on the host
697,698d696
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
749,752c747,748
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5444959500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5444959500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12147316500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12147316500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6702357000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6702357000 # number of overall MSHR uncacheable cycles
785,789c781,782
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199903.177764 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110297.814567 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110297.814567 # average overall mshr uncacheable latency
848,849d840
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
888d878
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1083,1084d1072
< system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1165,1166d1152
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5229022000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5229022000 # number of WriteReq MSHR uncacheable cycles
1168,1169c1154,1155
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11674912500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12200932500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6445890500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6971910500 # number of overall MSHR uncacheable cycles
1227,1228d1212
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872 # average WriteReq mshr uncacheable latency
1230,1232c1214,1215
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124 # average overall mshr uncacheable latency
< system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 106077.255373 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 107785.824714 # average overall mshr uncacheable latency
1625,1626d1607
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1677,1680c1658,1659
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251809500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251809500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641276500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641276500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 389467000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 389467000 # number of overall MSHR uncacheable cycles
1713,1717c1692,1693
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 73706.850871 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 73706.850871 # average overall mshr uncacheable latency
1776,1777d1751
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1816d1789
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013,2014d1985
< system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2097,2098d2067
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 234344500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 234344500 # number of WriteReq MSHR uncacheable cycles
2100,2101c2069,2070
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 599978000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614553500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 365633500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 380209000 # number of overall MSHR uncacheable cycles
2161,2162d2129
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689 # average WriteReq mshr uncacheable latency
2164,2166c2131,2132
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087 # average overall mshr uncacheable latency
< system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69196.347464 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70461.267606 # average overall mshr uncacheable latency
2337,2340c2303,2306
< system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
< system.iocache.demand_misses::total 243 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 243 # number of overall misses
< system.iocache.overall_misses::total 243 # number of overall misses
---
> system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36467 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36467 # number of overall misses
> system.iocache.overall_misses::total 36467 # number of overall misses
2345,2348c2311,2314
< system.iocache.demand_miss_latency::realview.ide 31660877 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 31660877 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 31660877 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 31660877 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 4609920234 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4609920234 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4609920234 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4609920234 # number of overall miss cycles
2353,2356c2319,2322
< system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses
2369,2372c2335,2338
< system.iocache.demand_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 130291.674897 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 130291.674897 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126413.476129 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126413.476129 # average overall miss latency
2379,2380d2344
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
2387,2390c2351,2354
< system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses
2395,2398c2359,2362
< system.iocache.demand_mshr_miss_latency::realview.ide 19510877 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 19510877 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 19510877 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 19510877 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 2784909291 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2784909291 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2784909291 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2784909291 # number of overall MSHR miss cycles
2411,2415c2375,2378
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
2710,2711d2672
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
2821,2823d2781
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4740559503 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 195045002 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4935604505 # number of WriteReq MSHR uncacheable cycles
2825c2783
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10609656010 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5869096507 # number of overall MSHR uncacheable cycles
2827,2828c2785,2786
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 507159005 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 11572801015 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 312114003 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 6637196510 # number of overall MSHR uncacheable cycles
2914,2916d2871
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603 # average WriteReq mshr uncacheable latency
2918c2873
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96585.204012 # average overall mshr uncacheable latency
2920,2922c2875,2876
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 59101.307139 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 94714.260374 # average overall mshr uncacheable latency
< host_inst_rate 194660 # Simulator instruction rate (inst/s)
< host_op_rate 235713 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4372273286 # Simulator tick rate (ticks/s)
< host_mem_usage 620428 # Number of bytes of host memory used
< host_seconds 651.58 # Real time elapsed on the host
---
> host_inst_rate 186843 # Simulator instruction rate (inst/s)
> host_op_rate 226247 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4196685224 # Simulator tick rate (ticks/s)
> host_mem_usage 620168 # Number of bytes of host memory used
> host_seconds 678.84 # Real time elapsed on the host
697,698d696
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
749,752c747,748
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5444959500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5444959500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12147316500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12147316500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6702357000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6702357000 # number of overall MSHR uncacheable cycles
785,789c781,782
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199903.177764 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110297.814567 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110297.814567 # average overall mshr uncacheable latency
848,849d840
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
888d878
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1083,1084d1072
< system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1165,1166d1152
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5229022000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5229022000 # number of WriteReq MSHR uncacheable cycles
1168,1169c1154,1155
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11674912500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12200932500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6445890500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6971910500 # number of overall MSHR uncacheable cycles
1227,1228d1212
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872 # average WriteReq mshr uncacheable latency
1230,1232c1214,1215
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124 # average overall mshr uncacheable latency
< system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 106077.255373 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 107785.824714 # average overall mshr uncacheable latency
1625,1626d1607
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1677,1680c1658,1659
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251809500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251809500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641276500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641276500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 389467000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 389467000 # number of overall MSHR uncacheable cycles
1713,1717c1692,1693
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 73706.850871 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 73706.850871 # average overall mshr uncacheable latency
1776,1777d1751
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1816d1789
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013,2014d1985
< system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2097,2098d2067
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 234344500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 234344500 # number of WriteReq MSHR uncacheable cycles
2100,2101c2069,2070
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 599978000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614553500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 365633500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 380209000 # number of overall MSHR uncacheable cycles
2161,2162d2129
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689 # average WriteReq mshr uncacheable latency
2164,2166c2131,2132
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087 # average overall mshr uncacheable latency
< system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69196.347464 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70461.267606 # average overall mshr uncacheable latency
2337,2340c2303,2306
< system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
< system.iocache.demand_misses::total 243 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 243 # number of overall misses
< system.iocache.overall_misses::total 243 # number of overall misses
---
> system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36467 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36467 # number of overall misses
> system.iocache.overall_misses::total 36467 # number of overall misses
2345,2348c2311,2314
< system.iocache.demand_miss_latency::realview.ide 31660877 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 31660877 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 31660877 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 31660877 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 4609920234 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4609920234 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4609920234 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4609920234 # number of overall miss cycles
2353,2356c2319,2322
< system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses
2369,2372c2335,2338
< system.iocache.demand_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 130291.674897 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 130291.674897 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126413.476129 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126413.476129 # average overall miss latency
2379,2380d2344
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
2387,2390c2351,2354
< system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses
2395,2398c2359,2362
< system.iocache.demand_mshr_miss_latency::realview.ide 19510877 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 19510877 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 19510877 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 19510877 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 2784909291 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2784909291 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2784909291 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2784909291 # number of overall MSHR miss cycles
2411,2415c2375,2378
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
2710,2711d2672
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
2821,2823d2781
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4740559503 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 195045002 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4935604505 # number of WriteReq MSHR uncacheable cycles
2825c2783
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10609656010 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5869096507 # number of overall MSHR uncacheable cycles
2827,2828c2785,2786
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 507159005 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 11572801015 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 312114003 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 6637196510 # number of overall MSHR uncacheable cycles
2914,2916d2871
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603 # average WriteReq mshr uncacheable latency
2918c2873
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96585.204012 # average overall mshr uncacheable latency
2920,2922c2875,2876
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 59101.307139 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 94714.260374 # average overall mshr uncacheable latency