3,5c3,5
< sim_seconds 2.846117 # Number of seconds simulated
< sim_ticks 2846117015000 # Number of ticks simulated
< final_tick 2846117015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.848053 # Number of seconds simulated
> sim_ticks 2848053071500 # Number of ticks simulated
> final_tick 2848053071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 113156 # Simulator instruction rate (inst/s)
< host_op_rate 137057 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2513496102 # Simulator tick rate (ticks/s)
< host_mem_usage 647580 # Number of bytes of host memory used
< host_seconds 1132.33 # Real time elapsed on the host
< sim_insts 128130877 # Number of instructions simulated
< sim_ops 155193960 # Number of ops (including micro ops) simulated
---
> host_inst_rate 153295 # Simulator instruction rate (inst/s)
> host_op_rate 185627 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3443122383 # Simulator tick rate (ticks/s)
> host_mem_usage 659004 # Number of bytes of host memory used
> host_seconds 827.17 # Real time elapsed on the host
> sim_insts 126801159 # Number of instructions simulated
> sim_ops 153545030 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu0.dtb.walker 7296 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 8768 # Number of bytes read from this memory
18,25c18,24
< system.physmem.bytes_read::cpu0.inst 1474816 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1242668 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8247680 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 2432 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 378112 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 721620 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 564672 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1683840 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1312624 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8530944 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 199296 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 609360 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 366080 # Number of bytes read from this memory
27,31c26,30
< system.physmem.bytes_read::total 12640384 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1474816 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 378112 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1852928 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8933696 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 12712960 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1683840 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 199296 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1883136 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8845504 # Number of bytes written to this memory
34,35c33,34
< system.physmem.bytes_written::total 8951260 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 114 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8863068 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 137 # Number of read requests responded to by this memory
37,44c36,42
< system.physmem.num_reads::cpu0.inst 23044 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 19938 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 128870 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 38 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 5908 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 11296 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 8823 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 26310 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 21032 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 133296 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 3114 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 9541 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 5720 # Number of read requests responded to by this memory
46,47c44,45
< system.physmem.num_reads::total 198048 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 139589 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 199182 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 138211 # Number of write requests responded to by this memory
50,51c48,49
< system.physmem.num_writes::total 143980 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 2563 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 142602 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 3079 # Total read bandwidth from this memory (bytes/s)
53,60c51,57
< system.physmem.bw_read::cpu0.inst 518185 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 436619 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 2897871 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 854 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 132852 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 253545 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 198401 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 591225 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 460885 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 2995360 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 360 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 69976 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 213957 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 128537 # Total read bandwidth from this memory (bytes/s)
62,67c59,64
< system.physmem.bw_read::total 4441273 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 518185 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 132852 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 651037 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3138907 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4463737 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 591225 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 69976 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 661201 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3105807 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 6153 # Write bandwidth from this memory (bytes/s)
69,71c66,68
< system.physmem.bw_write::total 3145078 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3138907 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 2563 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3111974 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3105807 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 3079 # Total bandwidth to/from this memory (bytes/s)
73,80c70,76
< system.physmem.bw_total::cpu0.inst 518185 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 442776 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 2897871 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 854 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 132852 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 253559 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 198401 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 591225 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 467038 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 2995360 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 360 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 69976 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 213971 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 128537 # Total bandwidth to/from this memory (bytes/s)
82,126c78,122
< system.physmem.bw_total::total 7586351 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 198048 # Number of read requests accepted
< system.physmem.writeReqs 143980 # Number of write requests accepted
< system.physmem.readBursts 198048 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 143980 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12666176 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8963584 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12640384 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8951260 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 51245 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 12439 # Per bank write bursts
< system.physmem.perBankRdBursts::1 12567 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12508 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12584 # Per bank write bursts
< system.physmem.perBankRdBursts::4 14823 # Per bank write bursts
< system.physmem.perBankRdBursts::5 11920 # Per bank write bursts
< system.physmem.perBankRdBursts::6 13135 # Per bank write bursts
< system.physmem.perBankRdBursts::7 13383 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12319 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12338 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11698 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11134 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11462 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11917 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11661 # Per bank write bursts
< system.physmem.perBankRdBursts::15 12021 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8771 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9038 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9230 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8945 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8307 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8620 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9591 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9703 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8875 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8727 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8430 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8199 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8380 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8472 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8531 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8237 # Per bank write bursts
---
> system.physmem.bw_total::total 7575711 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 199182 # Number of read requests accepted
> system.physmem.writeReqs 142602 # Number of write requests accepted
> system.physmem.readBursts 199182 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 142602 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12737472 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8875904 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12712960 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8863068 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 49648 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 12703 # Per bank write bursts
> system.physmem.perBankRdBursts::1 12645 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12416 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12383 # Per bank write bursts
> system.physmem.perBankRdBursts::4 15579 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12155 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12470 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12693 # Per bank write bursts
> system.physmem.perBankRdBursts::8 11969 # Per bank write bursts
> system.physmem.perBankRdBursts::9 11857 # Per bank write bursts
> system.physmem.perBankRdBursts::10 12504 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11838 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11708 # Per bank write bursts
> system.physmem.perBankRdBursts::13 12391 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11950 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11762 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9214 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9232 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9104 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8883 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8269 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8437 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8818 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8777 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8437 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8418 # Per bank write bursts
> system.physmem.perBankWrBursts::10 9013 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8780 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8383 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8480 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8424 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8017 # Per bank write bursts
128,129c124,125
< system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
< system.physmem.totGap 2846116455500 # Total gap between requests
---
> system.physmem.numWrRetry 17 # Number of times write queue was full causing retry
> system.physmem.totGap 2848052462500 # Total gap between requests
136c132
< system.physmem.readPktSize::6 197468 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 198602 # Read request sizes (log2)
143,158c139,154
< system.physmem.writePktSize::6 139589 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 85140 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 62378 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 11568 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 9695 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 7750 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 6201 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 5246 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 4552 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3838 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 742 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 263 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 234 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 161 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 138211 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 87578 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 61104 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 11612 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 9452 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7822 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 6360 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 5253 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 4675 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3805 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 696 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 208 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 143 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
160,163c156,159
< system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
191,294c187,292
< system.physmem.wrQLenPdf::15 2706 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3163 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4888 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5603 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6092 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6675 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7058 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8476 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9015 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 10231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9841 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9581 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8847 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9302 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 10565 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 8547 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7994 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7600 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 353 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 278 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 95 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 88 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 68 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 40 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 33 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 91138 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 237.329061 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 134.886171 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 298.768529 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 49038 53.81% 53.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17709 19.43% 73.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6298 6.91% 80.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3704 4.06% 84.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2913 3.20% 87.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1386 1.52% 88.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 897 0.98% 89.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1023 1.12% 91.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8170 8.96% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 91138 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6991 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.308683 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 556.324450 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6990 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6991 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6991 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.033758 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.625060 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.557866 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5837 83.49% 83.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 357 5.11% 88.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 222 3.18% 91.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 60 0.86% 92.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 64 0.92% 93.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 166 2.37% 95.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 20 0.29% 96.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 6 0.09% 96.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 14 0.20% 96.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 10 0.14% 96.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 5 0.07% 96.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 9 0.13% 96.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 167 2.39% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 8 0.11% 99.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 8 0.11% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 7 0.10% 99.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 3 0.04% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 3 0.04% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 3 0.04% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.01% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.01% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 14 0.20% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 2 0.03% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 2 0.03% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6991 # Writes before turning the bus around for reads
< system.physmem.totQLat 5451252873 # Total ticks spent queuing
< system.physmem.totMemAccLat 9162046623 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 989545000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 27544.24 # Average queueing delay per DRAM burst
---
> system.physmem.wrQLenPdf::15 2725 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3230 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4408 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4909 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5831 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6431 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7731 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7825 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8951 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 9319 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9452 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 10926 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 9238 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 9075 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 10229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 8920 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7997 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7566 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 505 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 96 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 99 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 65 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 58 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 89100 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 242.573648 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 137.731983 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 302.151175 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 46893 52.63% 52.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17637 19.79% 72.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6363 7.14% 79.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3624 4.07% 83.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2948 3.31% 86.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1436 1.61% 88.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 938 1.05% 89.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 975 1.09% 90.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8286 9.30% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 89100 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6864 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.995047 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 543.916897 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6863 99.99% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6864 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6864 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.204837 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.711823 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 11.958888 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5637 82.12% 82.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 489 7.12% 89.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 82 1.19% 90.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 154 2.24% 92.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 37 0.54% 93.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 124 1.81% 95.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 47 0.68% 95.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 16 0.23% 95.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 21 0.31% 96.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 19 0.28% 96.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 6 0.09% 96.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 10 0.15% 96.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 153 2.23% 98.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 1 0.01% 99.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 5 0.07% 99.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 30 0.44% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 4 0.06% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.03% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 2 0.03% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.01% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 11 0.16% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.01% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 3 0.04% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 1 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6864 # Writes before turning the bus around for reads
> system.physmem.totQLat 5502163905 # Total ticks spent queuing
> system.physmem.totMemAccLat 9233845155 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 995115000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 27645.87 # Average queueing delay per DRAM burst
296,300c294,298
< system.physmem.avgMemAccLat 46294.24 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.15 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.15 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 46395.87 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.47 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 4.46 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s
305,323c303,321
< system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing
< system.physmem.readRowHits 164305 # Number of row buffer hits during reads
< system.physmem.writeRowHits 82521 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 83.02 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 58.91 # Row buffer hit rate for writes
< system.physmem.avgGap 8321296.66 # Average gap between requests
< system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 359440200 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 196123125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 806200200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 467888400 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 185894445360 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 83210904225 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1634677575750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1905612577260 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.548459 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2719308511052 # Time in different power states
< system.physmem_0.memoryStateTime::REF 95038060000 # Time in different power states
---
> system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing
> system.physmem.readRowHits 165564 # Number of row buffer hits during reads
> system.physmem.writeRowHits 83044 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.19 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 59.87 # Row buffer hit rate for writes
> system.physmem.avgGap 8332901.66 # Average gap between requests
> system.physmem.pageHitRate 73.61 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 347056920 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 189366375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 803743200 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 458356320 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 186020568240 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 84074155830 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1635078931500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1906972178385 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.571882 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2719967809945 # Time in different power states
> system.physmem_0.memoryStateTime::REF 95102540000 # Time in different power states
325c323
< system.physmem_0.memoryStateTime::ACT 31769437698 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 32976648805 # Time in different power states
327,337c325,335
< system.physmem_1.actEnergy 329563080 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 179821125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 737482200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 439674480 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 185894445360 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 82251132525 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1635519480750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1905351599520 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.456762 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2720714979061 # Time in different power states
< system.physmem_1.memoryStateTime::REF 95038060000 # Time in different power states
---
> system.physmem_1.actEnergy 326539080 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 178171125 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 748628400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 440328960 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 186020568240 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 83156024340 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1635884310000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1906754570145 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.495475 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2721316836638 # Time in different power states
> system.physmem_1.memoryStateTime::REF 95102540000 # Time in different power states
339c337
< system.physmem_1.memoryStateTime::ACT 30363879439 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 31633548862 # Time in different power states
365,369c363,367
< system.cpu0.branchPred.lookups 34784409 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 16478031 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 1480168 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 19725615 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 14342133 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 36422708 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 17757542 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 1699668 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 20591819 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 15078708 # Number of BTB hits
371,373c369,371
< system.cpu0.branchPred.BTBHitPct 72.708167 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 11162624 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 702720 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 73.226693 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 11344544 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 821497 # Number of incorrect RAS predictions.
404,428c402,424
< system.cpu0.dtb.walker.walks 65972 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 65972 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 43486 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22486 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walkWaitTime::samples 65972 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 65972 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 65972 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 6612 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 10372.504537 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 9312.931281 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 6218.139441 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-16383 6425 97.17% 97.17% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::16384-32767 170 2.57% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-49151 7 0.11% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.08% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.06% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 6612 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 327753000 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0 327753000 100.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 327753000 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 5105 77.21% 77.21% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1507 22.79% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 6612 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65972 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walks 72997 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 72997 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47155 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25842 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walkWaitTime::samples 72997 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 72997 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 72997 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 7509 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 10509.122386 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 9271.690184 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 8241.046102 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-32767 7465 99.41% 99.41% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::32768-65535 36 0.48% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 7509 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 581566000 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0 581566000 100.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 581566000 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 5843 77.81% 77.81% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1666 22.19% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 7509 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72997 # Table walker requests started/completed, data/inst
430,431c426,427
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65972 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6612 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72997 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7509 # Table walker requests started/completed, data/inst
433,434c429,430
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6612 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 72584 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7509 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 80506 # Table walker requests started/completed, data/inst
437,440c433,436
< system.cpu0.dtb.read_hits 23562231 # DTB read hits
< system.cpu0.dtb.read_misses 59962 # DTB read misses
< system.cpu0.dtb.write_hits 17431474 # DTB write hits
< system.cpu0.dtb.write_misses 6010 # DTB write misses
---
> system.cpu0.dtb.read_hits 24918355 # DTB read hits
> system.cpu0.dtb.read_misses 66392 # DTB read misses
> system.cpu0.dtb.write_hits 18544526 # DTB write hits
> system.cpu0.dtb.write_misses 6605 # DTB write misses
445,447c441,443
< system.cpu0.dtb.flush_entries 3494 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 1076 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 1600 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 3803 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 1293 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 2019 # Number of TLB faults due to prefetch
449,451c445,447
< system.cpu0.dtb.perms_faults 577 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 23622193 # DTB read accesses
< system.cpu0.dtb.write_accesses 17437484 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 24984747 # DTB read accesses
> system.cpu0.dtb.write_accesses 18551131 # DTB write accesses
453,455c449,451
< system.cpu0.dtb.hits 40993705 # DTB hits
< system.cpu0.dtb.misses 65972 # DTB misses
< system.cpu0.dtb.accesses 41059677 # DTB accesses
---
> system.cpu0.dtb.hits 43462881 # DTB hits
> system.cpu0.dtb.misses 72997 # DTB misses
> system.cpu0.dtb.accesses 43535878 # DTB accesses
485,505c481,502
< system.cpu0.itb.walker.walks 3855 # Table walker walks requested
< system.cpu0.itb.walker.walksShort 3855 # Table walker walks initiated with short descriptors
< system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3550 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 3855 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 3855 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 3855 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 2424 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 10979.785479 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 9797.993767 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 8035.967164 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-32767 2422 99.92% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 2424 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 327059500 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 327059500 100.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 327059500 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 2124 87.62% 87.62% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::1M 300 12.38% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 2424 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walks 4165 # Table walker walks requested
> system.cpu0.itb.walker.walksShort 4165 # Table walker walks initiated with short descriptors
> system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3841 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 4165 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 4165 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 4165 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 2676 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 10991.778774 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 9686.198014 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 6109.891448 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-16383 2598 97.09% 97.09% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::16384-32767 50 1.87% 98.95% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-49151 27 1.01% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 2676 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 580856500 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 580856500 100.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 580856500 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 2357 88.08% 88.08% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::1M 319 11.92% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 2676 # Table walker page sizes translated
507,508c504,505
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3855 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3855 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4165 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4165 # Table walker requests started/completed, data/inst
510,514c507,511
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2424 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2424 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 6279 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 68397916 # ITB inst hits
< system.cpu0.itb.inst_misses 3855 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2676 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2676 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 6841 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 71531107 # ITB inst hits
> system.cpu0.itb.inst_misses 4165 # ITB inst misses
523c520
< system.cpu0.itb.flush_entries 2226 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2451 # Number of entries that have been flushed from TLB
527c524
< system.cpu0.itb.perms_faults 7522 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 8112 # Number of TLB faults due to permissions restrictions
530,534c527,531
< system.cpu0.itb.inst_accesses 68401771 # ITB inst accesses
< system.cpu0.itb.hits 68397916 # DTB hits
< system.cpu0.itb.misses 3855 # DTB misses
< system.cpu0.itb.accesses 68401771 # DTB accesses
< system.cpu0.numCycles 225406925 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 71535272 # ITB inst accesses
> system.cpu0.itb.hits 71531107 # DTB hits
> system.cpu0.itb.misses 4165 # DTB misses
> system.cpu0.itb.accesses 71535272 # DTB accesses
> system.cpu0.numCycles 246249018 # number of cpu cycles simulated
537,543c534,540
< system.cpu0.committedInsts 107236402 # Number of instructions committed
< system.cpu0.committedOps 129680129 # Number of ops (including micro ops) committed
< system.cpu0.discardedOps 8567834 # Number of ops (including micro ops) which were discarded before commit
< system.cpu0.numFetchSuspends 2087 # Number of times Execute suspended instruction fetching
< system.cpu0.quiesceCycles 5466862375 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.cpi 2.101963 # CPI: cycles per instruction
< system.cpu0.ipc 0.475746 # IPC: instructions per cycle
---
> system.cpu0.committedInsts 113090684 # Number of instructions committed
> system.cpu0.committedOps 136745700 # Number of ops (including micro ops) committed
> system.cpu0.discardedOps 8942808 # Number of ops (including micro ops) which were discarded before commit
> system.cpu0.numFetchSuspends 1853 # Number of times Execute suspended instruction fetching
> system.cpu0.quiesceCycles 5449882320 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.cpi 2.177447 # CPI: cycles per instruction
> system.cpu0.ipc 0.459253 # IPC: instructions per cycle
545,556c542,553
< system.cpu0.kern.inst.quiesce 2088 # number of quiesce instructions executed
< system.cpu0.tickCycles 187552407 # Number of cycles that the object actually ticked
< system.cpu0.idleCycles 37854518 # Total number of cycles that the object has spent stopped
< system.cpu0.dcache.tags.replacements 678280 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 485.010035 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 39540240 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 678792 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 58.250893 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 345600000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.010035 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947285 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.947285 # Average percentage of cache occupancy
---
> system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed
> system.cpu0.tickCycles 199226503 # Number of cycles that the object actually ticked
> system.cpu0.idleCycles 47022515 # Total number of cycles that the object has spent stopped
> system.cpu0.dcache.tags.replacements 754267 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 495.799422 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 41868735 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 754779 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 55.471516 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 600230000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.799422 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968358 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.968358 # Average percentage of cache occupancy
558,560c555,557
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
562,641c559,638
< system.cpu0.dcache.tags.tag_accesses 81933612 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 81933612 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 22071197 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 22071197 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 16340314 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 16340314 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307086 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 307086 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357744 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 357744 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352756 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 352756 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 38411511 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 38411511 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 38718597 # number of overall hits
< system.cpu0.dcache.overall_hits::total 38718597 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 442022 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 442022 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 555005 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 555005 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131972 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 131972 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20768 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 20768 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21303 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 21303 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 997027 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 997027 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 1128999 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1128999 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5846536500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5846536500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8888918500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 8888918500 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 319234500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 319234500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481221000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 481221000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 684000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 684000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 14735455000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 14735455000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 14735455000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 14735455000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 22513219 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 22513219 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 16895319 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 16895319 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 439058 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 439058 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378512 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 378512 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 374059 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 374059 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 39408538 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 39408538 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 39847596 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 39847596 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019634 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.019634 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032850 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.032850 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300580 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300580 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054867 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054867 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056951 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056951 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025300 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.025300 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028333 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.028333 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13226.799797 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13226.799797 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16015.925082 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 16015.925082 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15371.460901 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15371.460901 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22589.353612 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22589.353612 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 86874809 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 86874809 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 23308542 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 23308542 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 17374131 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 17374131 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329905 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 329905 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374910 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 374910 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371257 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 371257 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 40682673 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 40682673 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 41012578 # number of overall hits
> system.cpu0.dcache.overall_hits::total 41012578 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 490349 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 490349 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 600389 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 600389 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141605 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 141605 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21484 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 21484 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20155 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 20155 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 1090738 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1090738 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1232343 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1232343 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6919620500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 6919620500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11358969500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 11358969500 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328836500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 328836500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472700000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 472700000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 403000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 403000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 18278590000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 18278590000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 18278590000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 18278590000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 23798891 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 23798891 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 17974520 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 17974520 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471510 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 471510 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396394 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 396394 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391412 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 391412 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 41773411 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 41773411 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 42244921 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 42244921 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020604 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.020604 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033402 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.033402 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300322 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300322 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054199 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054199 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051493 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051493 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026111 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.026111 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029171 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.029171 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14111.623558 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 14111.623558 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18919.349788 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 18919.349788 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15306.111525 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15306.111525 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23453.237410 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23453.237410 # average StoreCondReq miss latency
644,647c641,644
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14779.394139 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 14779.394139 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.787468 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 13051.787468 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16758.002380 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 16758.002380 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14832.388385 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 14832.388385 # average overall miss latency
656,733c653,730
< system.cpu0.dcache.writebacks::writebacks 490245 # number of writebacks
< system.cpu0.dcache.writebacks::total 490245 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69954 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 69954 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243081 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 243081 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14749 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14749 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 313035 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 313035 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 313035 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 313035 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372068 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 372068 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 311924 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 311924 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99410 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 99410 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6019 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6019 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21303 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 21303 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 683992 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 683992 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 783402 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 783402 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29426 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29426 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26162 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26162 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55588 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55588 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4399139000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4399139000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4959161000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4959161000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1608557500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1608557500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 92509500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 92509500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459936000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459936000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 666000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 666000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9358300000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9358300000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10966857500 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 10966857500 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5696567000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5696567000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4315116500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4315116500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10011683500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10011683500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016527 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016527 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018462 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018462 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226417 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226417 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015902 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015902 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056951 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056951 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017356 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.017356 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019660 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.019660 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11823.481192 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11823.481192 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15898.619536 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15898.619536 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16181.043155 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16181.043155 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15369.579664 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15369.579664 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21590.198564 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21590.198564 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 540480 # number of writebacks
> system.cpu0.dcache.writebacks::total 540480 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 76076 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 76076 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 264589 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 264589 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14754 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14754 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 340665 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 340665 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 340665 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 340665 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 414273 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 414273 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 335800 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 335800 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107967 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 107967 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6730 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6730 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20155 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 20155 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 750073 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 750073 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 858040 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 858040 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32040 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32040 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60762 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60762 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5238286000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5238286000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6456534000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6456534000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1810830000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1810830000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104761500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104761500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452552000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452552000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 396000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 396000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11694820000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 11694820000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13505650000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 13505650000 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6348331500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6348331500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5156547500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5156547500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11504879000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11504879000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017407 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017407 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018682 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018682 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228981 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228981 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016978 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016978 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051493 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051493 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017956 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.017956 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020311 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.020311 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12644.526677 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12644.526677 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19227.319833 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19227.319833 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16772.069243 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16772.069243 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15566.344725 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15566.344725 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.584718 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.584718 # average StoreCondReq mshr miss latency
736,745c733,742
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13681.885168 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13681.885168 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13999.016469 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13999.016469 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193589.580643 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193589.580643 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164938.326581 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 164938.326581 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180105.121609 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 180105.121609 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15591.575753 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15591.575753 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15740.117011 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15740.117011 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198137.687266 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198137.687266 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179533.023466 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179533.023466 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189343.323130 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189343.323130 # average overall mshr uncacheable latency
747,755c744,752
< system.cpu0.icache.tags.replacements 1886353 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.780174 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 66503170 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1886865 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 35.245325 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 6541312000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780174 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.replacements 2044285 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.729271 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 69477789 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 2044797 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 33.977842 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 6924011000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.729271 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999471 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999471 # Average percentage of cache occupancy
757,759c754,756
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
761,798c758,795
< system.cpu0.icache.tags.tag_accesses 138666991 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 138666991 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 66503170 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 66503170 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 66503170 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 66503170 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 66503170 # number of overall hits
< system.cpu0.icache.overall_hits::total 66503170 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1886884 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1886884 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1886884 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1886884 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1886884 # number of overall misses
< system.cpu0.icache.overall_misses::total 1886884 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17552107500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 17552107500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 17552107500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 17552107500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 17552107500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 17552107500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 68390054 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 68390054 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 68390054 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 68390054 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 68390054 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 68390054 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027590 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.027590 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027590 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.027590 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027590 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.027590 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9302.165634 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 9302.165634 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9302.165634 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 9302.165634 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9302.165634 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 9302.165634 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 145090031 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 145090031 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 69477789 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 69477789 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 69477789 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 69477789 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 69477789 # number of overall hits
> system.cpu0.icache.overall_hits::total 69477789 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 2044818 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 2044818 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 2044818 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 2044818 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 2044818 # number of overall misses
> system.cpu0.icache.overall_misses::total 2044818 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20517256500 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 20517256500 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 20517256500 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 20517256500 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 20517256500 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 20517256500 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 71522607 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 71522607 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 71522607 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 71522607 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 71522607 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 71522607 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028590 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.028590 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028590 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.028590 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028590 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.028590 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10033.781246 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10033.781246 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10033.781246 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10033.781246 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10033.781246 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10033.781246 # average overall miss latency
807,842c804,839
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1886884 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1886884 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1886884 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1886884 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1886884 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1886884 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
< system.cpu0.icache.ReadReq_mshr_uncacheable::total 3426 # number of ReadReq MSHR uncacheable
< system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
< system.cpu0.icache.overall_mshr_uncacheable_misses::total 3426 # number of overall MSHR uncacheable misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16608666000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 16608666000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16608666000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 16608666000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16608666000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 16608666000 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 314279000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 314279000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 314279000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 314279000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027590 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.027590 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027590 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.027590 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8802.165899 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 8802.165899 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8802.165899 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 8802.165899 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465 # average overall mshr uncacheable latency
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2044818 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 2044818 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 2044818 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 2044818 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 2044818 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 2044818 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3915 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.ReadReq_mshr_uncacheable::total 3915 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3915 # number of overall MSHR uncacheable misses
> system.cpu0.icache.overall_mshr_uncacheable_misses::total 3915 # number of overall MSHR uncacheable misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19494848000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 19494848000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19494848000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 19494848000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19494848000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 19494848000 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557217500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557217500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557217500 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 557217500 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028590 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028590 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028590 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.028590 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028590 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.028590 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9533.781491 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9533.781491 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9533.781491 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 9533.781491 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9533.781491 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 9533.781491 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142328.863346 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142328.863346 # average overall mshr uncacheable latency
844,846c841,843
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1753692 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1753724 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1923323 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1923513 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 165 # number of redundant prefetches already in prefetch queue
849,876c846,873
< system.cpu0.l2cache.prefetcher.pfSpanPage 222140 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 284631 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16080.562269 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 4811395 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 300867 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 15.991767 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 8557.843574 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.688699 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065125 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4677.760567 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1660.845415 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1126.358889 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.522329 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003521 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285508 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.101370 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068747 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.981480 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1014 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15208 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 351 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 393 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 243791 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 310417 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16162.197478 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 5245257 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 326630 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 16.058712 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 2827807181000 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 6560.031691 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 62.859334 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.055204 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5926.735945 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1926.535864 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1685.979439 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.400393 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003837 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.361739 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.117586 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.102904 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.986462 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 984 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15223 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 330 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 428 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 218 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
878,997c875,994
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4117 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7919 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2851 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061890 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928223 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 85529410 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 85529410 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77804 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4292 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 82096 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 490243 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 490243 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28207 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 28207 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1765 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 1765 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212310 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 212310 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1823174 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 1823174 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376441 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 376441 # number of ReadSharedReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77804 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4292 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1823174 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 588751 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 2494021 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77804 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4292 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1823174 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 588751 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 2494021 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 777 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 131 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 908 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27955 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 27955 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19533 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19533 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43457 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 43457 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 63710 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 63710 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101052 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 101052 # number of ReadSharedReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 777 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 131 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 63710 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 144509 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 209127 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 777 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 131 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 63710 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 144509 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 209127 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 26295000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3189000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 29484000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 514165000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 514165000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396282000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396282000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 637497 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 637497 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2195149500 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2195149500 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2860433500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2860433500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2915473994 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2915473994 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 26295000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3189000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2860433500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 5110623494 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 8000540994 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 26295000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3189000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2860433500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 5110623494 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 8000540994 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78581 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4423 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 83004 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 490243 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 490243 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56162 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 56162 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21298 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 21298 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 255767 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 255767 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1886884 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 1886884 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477493 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 477493 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78581 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4423 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1886884 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 733260 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 2703148 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78581 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4423 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1886884 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 733260 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 2703148 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009888 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029618 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.010939 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.497756 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.497756 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.917128 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.917128 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4188 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8533 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2180 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.060059 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.929138 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 93116780 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 93116780 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 86201 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4393 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 90594 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 540479 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 540479 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28758 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 28758 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2008 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 2008 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 233257 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 233257 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1970223 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 1970223 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 427246 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 427246 # number of ReadSharedReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 86201 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4393 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1970223 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 660503 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 2721320 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 86201 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4393 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1970223 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 660503 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 2721320 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 779 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 93 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 872 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26665 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 26665 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18145 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 18145 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47128 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 47128 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 74595 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 74595 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101717 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 101717 # number of ReadSharedReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 779 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 93 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 74595 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 148845 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 224312 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 779 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 93 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 74595 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 148845 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 224312 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 36149500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2302000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 38451500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 622250500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 622250500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 390027000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 390027000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 384498 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 384498 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3148896999 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 3148896999 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4603637500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4603637500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3550040997 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3550040997 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 36149500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2302000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4603637500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 6698937996 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 11341026996 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 36149500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2302000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4603637500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 6698937996 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 11341026996 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 86980 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4486 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 91466 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 540479 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 540479 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55423 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 55423 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20153 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 20153 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280385 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 280385 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2044818 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 2044818 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 528963 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 528963 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 86980 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4486 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 2044818 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 809348 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 2945632 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 86980 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4486 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 2044818 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 809348 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 2945632 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008956 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.020731 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.009534 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.481118 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.481118 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.900362 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.900362 # miss rate for SCUpgradeReq accesses
1000,1041c997,1038
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169909 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169909 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.033765 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.033765 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211630 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211630 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009888 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029618 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.033765 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197077 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.077364 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009888 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029618 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.033765 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197077 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.077364 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33841.698842 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24343.511450 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32471.365639 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18392.595242 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18392.595242 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20287.820611 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20287.820611 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 127499.400000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 127499.400000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50513.139425 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50513.139425 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44897.716214 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44897.716214 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28851.225052 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28851.225052 # average ReadSharedReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33841.698842 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24343.511450 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44897.716214 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35365.433945 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 38256.853462 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33841.698842 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24343.511450 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44897.716214 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35365.433945 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 38256.853462 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 59 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.168083 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.168083 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.036480 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.036480 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.192295 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.192295 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008956 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.020731 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036480 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183907 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.076151 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008956 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.020731 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036480 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183907 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.076151 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 46405.006418 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24752.688172 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44095.756881 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 23335.852241 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 23335.852241 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21495.012400 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21495.012400 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 192249 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 192249 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66815.841941 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66815.841941 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 61715.094845 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 61715.094845 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34901.157103 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34901.157103 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 46405.006418 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24752.688172 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 61715.094845 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45006.133871 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 50559.163112 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 46405.006418 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24752.688172 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 61715.094845 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45006.133871 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 50559.163112 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked
1043c1040
< system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
1045c1042
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 29.500000 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1049,1139c1046,1136
< system.cpu0.l2cache.writebacks::writebacks 195819 # number of writebacks
< system.cpu0.l2cache.writebacks::total 195819 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2770 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 2770 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 71 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 71 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 354 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 354 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 71 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3124 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 3195 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 71 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3124 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 3195 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 777 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 131 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 9247 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::total 9247 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232905 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 232905 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27955 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27955 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19533 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19533 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40687 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 40687 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 63639 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 63639 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100698 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100698 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 777 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 131 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 63639 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 141385 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 205932 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 777 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 131 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 63639 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 141385 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232905 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 438837 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29426 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 32852 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26162 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26162 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55588 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 59014 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 21633000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2403000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 24036000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13888716397 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13888716397 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 558509999 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 558509999 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 298853000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 298853000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 529497 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 529497 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1645934000 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1645934000 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2476915500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2476915500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2292009994 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2292009994 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 21633000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2403000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2476915500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3937943994 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 6438895494 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 21633000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2403000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2476915500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3937943994 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13888716397 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 20327611891 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 286870500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5461072000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5747942500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4118636500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4118636500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 286870500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9579708500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9866579000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009888 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029618 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010939 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.writebacks::writebacks 205168 # number of writebacks
> system.cpu0.l2cache.writebacks::total 205168 # number of writebacks
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5239 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 5239 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 89 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 89 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 602 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 602 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 89 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5841 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 5930 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 89 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5841 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 5930 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 779 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 93 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 872 # number of ReadReq MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 10393 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::total 10393 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 251914 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 251914 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26665 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26665 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18145 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18145 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41889 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 41889 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 74506 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 74506 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101115 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101115 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 779 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 93 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 74506 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143004 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 218382 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 779 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 93 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 74506 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143004 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 251914 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 470296 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3915 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32040 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35955 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3915 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60762 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 64677 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 31475500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1744000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33219500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21126531245 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21126531245 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 933301999 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 933301999 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 299858500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 299858500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 342498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 342498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2392710000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2392710000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4153675000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4153675000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2908093997 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2908093997 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 31475500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1744000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4153675000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5300803997 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 9487698497 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 31475500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1744000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4153675000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5300803997 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21126531245 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 30614229742 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 525897000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6091912000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6617809000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4940592000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4940592000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 525897000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11032504000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11558401000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008956 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.020731 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009534 # mshr miss rate for ReadReq accesses
1144,1147c1141,1144
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.497756 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.497756 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.917128 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.917128 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.481118 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.481118 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.900362 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.900362 # mshr miss rate for SCUpgradeReq accesses
1150,1164c1147,1161
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159078 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159078 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.033727 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033727 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.210889 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.210889 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009888 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029618 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.033727 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076182 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009888 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029618 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.033727 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.149398 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149398 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.036436 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036436 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.191157 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.191157 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008956 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.020731 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036436 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.176690 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.074138 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008956 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.020731 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036436 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.176690 # mshr miss rate for overall accesses
1166,1202c1163,1199
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162343 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26471.365639 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59632.538576 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19978.894616 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19978.894616 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15299.902729 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15299.902729 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 105899.400000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 105899.400000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40453.560105 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40453.560105 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38921.345401 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22761.226578 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22761.226578 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27852.629303 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31267.095420 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27841.698842 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18343.511450 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38921.345401 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27852.629303 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59632.538576 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46321.554224 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185586.624074 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174964.766224 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157428.197386 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157428.197386 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172334.109880 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167190.480225 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.159659 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38095.756881 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83864.061723 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35001.012526 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35001.012526 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16525.682006 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16525.682006 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 171249 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 171249 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57120.246365 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57120.246365 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 55749.536950 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28760.263037 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28760.263037 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37067.522566 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43445.423602 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37067.522566 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 65095.662608 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190134.581773 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 184058.100403 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172014.205139 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172014.205139 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181569.138606 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 178709.603105 # average overall mshr uncacheable latency
1204,1234c1201,1237
< system.cpu0.toL2Bus.trans_dist::ReadReq 134550 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 2542059 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 26162 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 862676 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 2186135 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 279695 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 92964 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43745 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 114531 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 284097 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 270085 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1886884 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603437 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5633887 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2503276 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11828 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167039 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 8316030 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120979776 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82538715 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17692 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314324 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 203850507 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 1178802 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 6482684 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 1.179159 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.383485 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 5752448 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2898331 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 171817 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 171638 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 179 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 142841 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 2765458 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28722 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28722 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 746343 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 2333999 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 319529 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 85747 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42548 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 112824 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 299375 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 296092 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2044818 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 602268 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 3078 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6106044 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739032 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12492 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185819 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 9043387 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 131118848 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90716354 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17944 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 347920 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 222201066 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 910866 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 6693455 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.042507 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.201876 # Request fanout histogram
1236,1238c1239,1241
< system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 5321256 82.08% 82.08% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 1161428 17.92% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 6409112 95.75% 95.75% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 284164 4.25% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 179 0.00% 100.00% # Request fanout histogram
1240c1243
< system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1242,1243c1245,1246
< system.cpu0.toL2Bus.snoop_fanout::total 6482684 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 3211889987 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 6693455 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 3504755489 # Layer occupancy (ticks)
1245c1248
< system.cpu0.toL2Bus.snoopLayer0.occupancy 113481999 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 115583734 # Layer occupancy (ticks)
1247c1250
< system.cpu0.toL2Bus.respLayer0.occupancy 2835744437 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 3073459276 # Layer occupancy (ticks)
1249c1252
< system.cpu0.toL2Bus.respLayer1.occupancy 1181675942 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1298870694 # Layer occupancy (ticks)
1251c1254
< system.cpu0.toL2Bus.respLayer2.occupancy 7408493 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 8011489 # Layer occupancy (ticks)
1253c1256
< system.cpu0.toL2Bus.respLayer3.occupancy 88460994 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 98861455 # Layer occupancy (ticks)
1255,1259c1258,1262
< system.cpu1.branchPred.lookups 5445699 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 3358034 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 328537 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 3334781 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 2260975 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 3534290 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 1990183 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 201553 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 2067319 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 1417438 # Number of BTB hits
1261,1263c1264,1266
< system.cpu1.branchPred.BTBHitPct 67.799805 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 969415 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 68088 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 68.564068 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 735878 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 53173 # Number of incorrect RAS predictions.
1293,1318c1296,1321
< system.cpu1.dtb.walker.walks 29420 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 29420 # Table walker walks initiated with short descriptors
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 21788 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7632 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walkWaitTime::samples 29420 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 29420 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 29420 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 10739.844904 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 9761.358244 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 6619.660152 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-16383 2565 94.72% 94.72% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-32767 128 4.73% 99.45% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-49151 8 0.30% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.04% 99.78% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::81920-98303 4 0.15% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::98304-114687 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 1720699264 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 1720699264 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 1720699264 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 2021 74.63% 74.63% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 687 25.37% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 29420 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walks 21952 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 21952 # Table walker walks initiated with short descriptors
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 17656 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4296 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walkWaitTime::samples 21952 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 21952 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 21952 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 1858 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 11787.944026 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 10957.170839 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 8000.267562 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-16383 1715 92.30% 92.30% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::16384-32767 133 7.16% 99.46% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-49151 6 0.32% 99.78% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.84% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::212992-229375 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 1858 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples -2099073032 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 -2099073032 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total -2099073032 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 1319 70.99% 70.99% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 539 29.01% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 1858 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21952 # Table walker requests started/completed, data/inst
1320,1321c1323,1324
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 29420 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21952 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1858 # Table walker requests started/completed, data/inst
1323,1324c1326,1327
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 32128 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1858 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 23810 # Table walker requests started/completed, data/inst
1327,1330c1330,1333
< system.cpu1.dtb.read_hits 5163963 # DTB read hits
< system.cpu1.dtb.read_misses 27269 # DTB read misses
< system.cpu1.dtb.write_hits 4235498 # DTB write hits
< system.cpu1.dtb.write_misses 2151 # DTB write misses
---
> system.cpu1.dtb.read_hits 3504265 # DTB read hits
> system.cpu1.dtb.read_misses 20273 # DTB read misses
> system.cpu1.dtb.write_hits 2919622 # DTB write hits
> system.cpu1.dtb.write_misses 1679 # DTB write misses
1335,1337c1338,1340
< system.cpu1.dtb.flush_entries 2054 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 296 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 518 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 1723 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 86 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch
1339,1341c1342,1344
< system.cpu1.dtb.perms_faults 294 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 5191232 # DTB read accesses
< system.cpu1.dtb.write_accesses 4237649 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 3524538 # DTB read accesses
> system.cpu1.dtb.write_accesses 2921301 # DTB write accesses
1343,1345c1346,1348
< system.cpu1.dtb.hits 9399461 # DTB hits
< system.cpu1.dtb.misses 29420 # DTB misses
< system.cpu1.dtb.accesses 9428881 # DTB accesses
---
> system.cpu1.dtb.hits 6423887 # DTB hits
> system.cpu1.dtb.misses 21952 # DTB misses
> system.cpu1.dtb.accesses 6445839 # DTB accesses
1375,1398c1378,1404
< system.cpu1.itb.walker.walks 2244 # Table walker walks requested
< system.cpu1.itb.walker.walksShort 2244 # Table walker walks initiated with short descriptors
< system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2063 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walkWaitTime::samples 2244 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 2244 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 2244 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 10959.928762 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 10069.580655 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 5627.290327 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-8191 289 25.73% 25.73% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-16383 792 70.53% 96.26% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-24575 4 0.36% 96.62% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::24576-32767 34 3.03% 99.64% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 1720133764 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 1720133764 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 1720133764 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 954 84.95% 84.95% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::1M 169 15.05% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walks 1951 # Table walker walks requested
> system.cpu1.itb.walker.walksShort 1951 # Table walker walks initiated with short descriptors
> system.cpu1.itb.walker.walksShortTerminationLevel::Level1 155 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1796 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walkWaitTime::samples 1951 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 1951 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 1951 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 11383.431953 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 10916.753394 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 4130.106784 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::4096-8191 149 17.63% 17.63% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-12287 569 67.34% 84.97% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::12288-16383 107 12.66% 97.63% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 97.75% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.82% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::28672-32767 4 0.47% 99.29% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.47% 99.76% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples -2099960532 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 -2099960532 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total -2099960532 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 705 83.43% 83.43% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::1M 140 16.57% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated
1400,1401c1406,1407
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2244 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2244 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1951 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1951 # Table walker requests started/completed, data/inst
1403,1407c1409,1413
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 3367 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 10150571 # ITB inst hits
< system.cpu1.itb.inst_misses 2244 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 2796 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 6761340 # ITB inst hits
> system.cpu1.itb.inst_misses 1951 # ITB inst misses
1416c1422
< system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 909 # Number of entries that have been flushed from TLB
1420c1426
< system.cpu1.itb.perms_faults 1947 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions
1423,1427c1429,1433
< system.cpu1.itb.inst_accesses 10152815 # ITB inst accesses
< system.cpu1.itb.hits 10150571 # DTB hits
< system.cpu1.itb.misses 2244 # DTB misses
< system.cpu1.itb.accesses 10152815 # DTB accesses
< system.cpu1.numCycles 54273174 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 6763291 # ITB inst accesses
> system.cpu1.itb.hits 6761340 # DTB hits
> system.cpu1.itb.misses 1951 # DTB misses
> system.cpu1.itb.accesses 6763291 # DTB accesses
> system.cpu1.numCycles 39381699 # number of cpu cycles simulated
1430,1436c1436,1442
< system.cpu1.committedInsts 20894475 # Number of instructions committed
< system.cpu1.committedOps 25513831 # Number of ops (including micro ops) committed
< system.cpu1.discardedOps 1850967 # Number of ops (including micro ops) which were discarded before commit
< system.cpu1.numFetchSuspends 2736 # Number of times Execute suspended instruction fetching
< system.cpu1.quiesceCycles 5637336830 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.cpi 2.597489 # CPI: cycles per instruction
< system.cpu1.ipc 0.384987 # IPC: instructions per cycle
---
> system.cpu1.committedInsts 13710475 # Number of instructions committed
> system.cpu1.committedOps 16799330 # Number of ops (including micro ops) committed
> system.cpu1.discardedOps 1340837 # Number of ops (including micro ops) which were discarded before commit
> system.cpu1.numFetchSuspends 2719 # Number of times Execute suspended instruction fetching
> system.cpu1.quiesceCycles 5656091241 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.cpi 2.872380 # CPI: cycles per instruction
> system.cpu1.ipc 0.348143 # IPC: instructions per cycle
1438,1533c1444,1539
< system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed
< system.cpu1.tickCycles 38589177 # Number of cycles that the object actually ticked
< system.cpu1.idleCycles 15683997 # Total number of cycles that the object has spent stopped
< system.cpu1.dcache.tags.replacements 232297 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 482.192292 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 8906174 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 232671 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 38.277972 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 90623150500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.192292 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941782 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.941782 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 18859700 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 18859700 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 4719301 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 4719301 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3908024 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3908024 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65371 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 65371 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88156 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 88156 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80067 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 80067 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 8627325 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 8627325 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 8692696 # number of overall hits
< system.cpu1.dcache.overall_hits::total 8692696 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 183894 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 183894 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 168264 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 168264 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35705 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 35705 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17716 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 17716 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23526 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23526 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 352158 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 352158 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 387863 # number of overall misses
< system.cpu1.dcache.overall_misses::total 387863 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2718275000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2718275000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4151672000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 4151672000 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326404500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 326404500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549519500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 549519500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 392000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 392000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 6869947000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 6869947000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 6869947000 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 6869947000 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 4903195 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 4903195 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 4076288 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 4076288 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101076 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 101076 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105872 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 105872 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103593 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 103593 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 8979483 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 8979483 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 9080559 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 9080559 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037505 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.037505 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041279 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.041279 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.353249 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.353249 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.167334 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.167334 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227100 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227100 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039218 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.039218 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042714 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.042714 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14781.749269 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14781.749269 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24673.560595 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 24673.560595 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18424.277489 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18424.277489 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23357.965655 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23357.965655 # average StoreCondReq miss latency
---
> system.cpu1.kern.inst.quiesce 2719 # number of quiesce instructions executed
> system.cpu1.tickCycles 26653258 # Number of cycles that the object actually ticked
> system.cpu1.idleCycles 12728441 # Total number of cycles that the object has spent stopped
> system.cpu1.dcache.tags.replacements 152894 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 470.093140 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 6072239 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 153243 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 39.624903 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 110033723500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.093140 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.918151 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.918151 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 286 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 12903758 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 12903758 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 3189039 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 3189039 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 2677291 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 2677291 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41980 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 41980 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69267 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 69267 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 60867 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 60867 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 5866330 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 5866330 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 5908310 # number of overall hits
> system.cpu1.dcache.overall_hits::total 5908310 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 130563 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 130563 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 120040 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 120040 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24252 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 24252 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16672 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 16672 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23310 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23310 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 250603 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 250603 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 274855 # number of overall misses
> system.cpu1.dcache.overall_misses::total 274855 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2128187500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2128187500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4337924000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 4337924000 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321753000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 321753000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 615942500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 615942500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1442500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1442500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 6466111500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 6466111500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 6466111500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 6466111500 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 3319602 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 3319602 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 2797331 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 2797331 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66232 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 66232 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 85939 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 85939 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84177 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 84177 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 6116933 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 6116933 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 6183165 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 6183165 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039331 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.039331 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042912 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.042912 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.366167 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.366167 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.193998 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.193998 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.276916 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.276916 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040969 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.040969 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044452 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.044452 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16300.081187 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 16300.081187 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36137.320893 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 36137.320893 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19299.004319 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19299.004319 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26423.959674 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26423.959674 # average StoreCondReq miss latency
1536,1539c1542,1545
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19508.138392 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 19508.138392 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17712.303055 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 17712.303055 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25802.211067 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 25802.211067 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23525.537101 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 23525.537101 # average overall miss latency
1548,1625c1554,1631
< system.cpu1.dcache.writebacks::writebacks 139329 # number of writebacks
< system.cpu1.dcache.writebacks::total 139329 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18066 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 18066 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62670 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 62670 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12262 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12262 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 80736 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 80736 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 80736 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 80736 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165828 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 165828 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105594 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 105594 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 34258 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 34258 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5454 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5454 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23526 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23526 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 271422 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 271422 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 305680 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 305680 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5722 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5722 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5009 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5009 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10731 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10731 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2294657000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2294657000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2511298500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2511298500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 559951000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 559951000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93173500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93173500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 526001500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 526001500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 384000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 384000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4805955500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4805955500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5365906500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 5365906500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 990469500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 990469500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 857774500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 857774500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1848244000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1848244000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033820 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033820 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025904 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025904 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.338933 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.338933 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051515 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051515 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227100 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227100 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030227 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.030227 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033663 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.033663 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13837.572666 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13837.572666 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23782.587079 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23782.587079 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16345.116469 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16345.116469 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17083.516685 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17083.516685 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22358.305704 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22358.305704 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 95329 # number of writebacks
> system.cpu1.dcache.writebacks::total 95329 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12149 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 12149 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 41106 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 41106 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11576 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11576 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 53255 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 53255 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 53255 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 53255 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118414 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 118414 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78934 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 78934 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23724 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 23724 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5096 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5096 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23310 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23310 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 197348 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 197348 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 221072 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 221072 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2845 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2845 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2191 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2191 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5036 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5036 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1811744000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1811744000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2651572500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2651572500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 432946000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 432946000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 92138000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 92138000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 592646500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 592646500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1428500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1428500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4463316500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4463316500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4896262500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4896262500 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 356276500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 356276500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224816500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224816500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 581093000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 581093000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035671 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035671 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028218 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028218 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.358195 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.358195 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059298 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059298 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.276916 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.276916 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032263 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.032263 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035754 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035754 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15300.082760 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15300.082760 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33592.273292 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33592.273292 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18249.283426 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18249.283426 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18080.455259 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18080.455259 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25424.560275 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25424.560275 # average StoreCondReq mshr miss latency
1628,1637c1634,1643
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17706.580528 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17706.580528 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17553.999280 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17553.999280 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173098.479553 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173098.479553 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171246.656019 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171246.656019 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172234.088156 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 172234.088156 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22616.476985 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22616.476985 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22147.818358 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22147.818358 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125228.998243 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125228.998243 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102609.082611 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 102609.082611 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 115387.807784 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 115387.807784 # average overall mshr uncacheable latency
1639,1647c1645,1653
< system.cpu1.icache.tags.replacements 1036067 # number of replacements
< system.cpu1.icache.tags.tagsinuse 499.306675 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 9111880 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 1036579 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 8.790338 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 72226761500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.306675 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975208 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.975208 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 837637 # number of replacements
> system.cpu1.icache.tags.tagsinuse 499.228366 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 5922018 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 838149 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 7.065591 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 72771979500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.228366 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975055 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.975055 # Average percentage of cache occupancy
1649,1650c1655,1657
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 457 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
1652,1689c1659,1696
< system.cpu1.icache.tags.tag_accesses 21333497 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 21333497 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 9111880 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 9111880 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 9111880 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 9111880 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 9111880 # number of overall hits
< system.cpu1.icache.overall_hits::total 9111880 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 1036579 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 1036579 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 1036579 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 1036579 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 1036579 # number of overall misses
< system.cpu1.icache.overall_misses::total 1036579 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9180202500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 9180202500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 9180202500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 9180202500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 9180202500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 9180202500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 10148459 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 10148459 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 10148459 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 10148459 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 10148459 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 10148459 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.102142 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.102142 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.102142 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.102142 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.102142 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.102142 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8856.249741 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 8856.249741 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8856.249741 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 8856.249741 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8856.249741 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 8856.249741 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 14358483 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 14358483 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 5922018 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 5922018 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 5922018 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 5922018 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 5922018 # number of overall hits
> system.cpu1.icache.overall_hits::total 5922018 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 838149 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 838149 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 838149 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 838149 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 838149 # number of overall misses
> system.cpu1.icache.overall_misses::total 838149 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7371671000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 7371671000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 7371671000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 7371671000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 7371671000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 7371671000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 6760167 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 6760167 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 6760167 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 6760167 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 6760167 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 6760167 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.123983 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.123983 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.123983 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.123983 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.123983 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.123983 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8795.179616 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 8795.179616 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8795.179616 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 8795.179616 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8795.179616 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 8795.179616 # average overall miss latency
1698,1733c1705,1740
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1036579 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 1036579 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 1036579 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 1036579 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 1036579 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 1036579 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable
< system.cpu1.icache.ReadReq_mshr_uncacheable::total 113 # number of ReadReq MSHR uncacheable
< system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses
< system.cpu1.icache.overall_mshr_uncacheable_misses::total 113 # number of overall MSHR uncacheable misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8661913000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 8661913000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8661913000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 8661913000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8661913000 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 8661913000 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10059500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10059500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10059500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 10059500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.102142 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.102142 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.102142 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.102142 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.102142 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.102142 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8356.249741 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8356.249741 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8356.249741 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8356.249741 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8356.249741 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8356.249741 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89022.123894 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89022.123894 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89022.123894 # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 838149 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 838149 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 838149 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 838149 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 838149 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 838149 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
> system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6952596500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 6952596500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6952596500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 6952596500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6952596500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 6952596500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15127000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15127000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15127000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 15127000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.123983 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.123983 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.123983 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.123983 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.123983 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.123983 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8295.179616 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8295.179616 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8295.179616 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8295.179616 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8295.179616 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8295.179616 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135062.500000 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135062.500000 # average overall mshr uncacheable latency
1735,1737c1742,1744
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 272165 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 272190 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 119402 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 119476 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue
1740,1745c1747,1752
< system.cpu1.l2cache.prefetcher.pfSpanPage 68922 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 69326 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15661.573061 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 2410564 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 84006 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 28.695141 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 48156 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 37250 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15275.676235 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 1897057 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 52360 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 36.231035 # Average number of references to valid blocks.
1747,1929c1754,1930
< system.cpu1.l2cache.tags.occ_blocks::writebacks 6188.157881 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.165341 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100614 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5579.436781 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2277.975966 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1563.736478 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.377695 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003184 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.340542 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.139037 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.095443 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.955907 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1195 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13435 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 666 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 525 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5728 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7406 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072937 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.820007 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 42699170 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 42699170 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 32497 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2653 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 35150 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 139329 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 139329 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2011 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 2011 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1071 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 1071 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38166 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 38166 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1009291 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 1009291 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 131481 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 131481 # number of ReadSharedReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 32497 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2653 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 1009291 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 169647 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 1214088 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 32497 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2653 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 1009291 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 169647 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 1214088 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 719 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 229 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29485 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29485 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22454 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22454 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35935 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 35935 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 27288 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 27288 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 74058 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 74058 # number of ReadSharedReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 719 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 229 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 27288 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 109993 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 138229 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 719 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 229 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 27288 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 109993 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 138229 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17830000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4703000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 22533000 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 557854000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 557854000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449261000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449261000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 372000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 372000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1407590499 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1407590499 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1060250500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1060250500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1775396994 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1775396994 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17830000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4703000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1060250500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 3182987493 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 4265770993 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17830000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4703000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1060250500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 3182987493 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 4265770993 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33216 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2882 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 36098 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 139329 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 139329 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31496 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 31496 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23525 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23525 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74101 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 74101 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1036579 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 1036579 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 205539 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 205539 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33216 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2882 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 1036579 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 279640 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 1352317 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33216 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2882 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 1036579 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 279640 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 1352317 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021646 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079459 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.026262 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936151 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936151 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.954474 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.954474 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
< system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484946 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484946 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026325 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026325 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.360311 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.360311 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021646 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.079459 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026325 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.393338 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.102216 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021646 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.079459 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026325 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.393338 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.102216 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 24798.331015 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20537.117904 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23768.987342 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18919.925386 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18919.925386 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20008.060925 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20008.060925 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 372000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 372000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39170.460526 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39170.460526 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38854.093374 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38854.093374 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23973.061573 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23973.061573 # average ReadSharedReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 24798.331015 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20537.117904 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38854.093374 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28938.091451 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 30860.174008 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 24798.331015 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20537.117904 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38854.093374 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28938.091451 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 30860.174008 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 7998.087446 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 32.292792 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.074638 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4213.861593 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2174.488490 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 856.871276 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.488165 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001971 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.257194 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132720 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052299 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.932353 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1099 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13920 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 56 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1042 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1993 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11603 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.067078 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 33573934 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 33573934 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23345 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2401 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 25746 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 95329 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 95329 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1276 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 1276 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 784 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 784 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 17759 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 17759 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 825014 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 825014 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 81245 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 81245 # number of ReadSharedReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23345 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2401 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 825014 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 99004 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 949764 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23345 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2401 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 825014 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 99004 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 949764 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 724 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 240 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 964 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27711 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 27711 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22526 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22526 # number of SCUpgradeReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32189 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 32189 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13135 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 13135 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 65988 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 65988 # number of ReadSharedReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 724 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 240 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 13135 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 98177 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 112276 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 724 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 240 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 13135 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 98177 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 112276 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 16832000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4807500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 21639500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 545169500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 545169500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 480035000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 480035000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1407500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1407500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1686123500 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1686123500 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 733172000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 733172000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1579312997 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1579312997 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 16832000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4807500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 733172000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 3265436497 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 4020247997 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 16832000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4807500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 733172000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 3265436497 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 4020247997 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24069 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2641 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 26710 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 95329 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 95329 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28987 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 28987 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23310 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23310 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 49948 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 49948 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 838149 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 838149 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 147233 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 147233 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24069 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2641 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 838149 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 197181 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 1062040 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24069 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2641 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 838149 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 197181 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 1062040 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.030080 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090875 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.036091 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.955980 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.955980 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.966366 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.966366 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.644450 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.644450 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.015671 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.015671 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.448188 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.448188 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.030080 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090875 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.015671 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.497903 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.105717 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.030080 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090875 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.015671 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.497903 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.105717 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23248.618785 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20031.250000 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22447.614108 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19673.396846 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19673.396846 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21310.263695 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21310.263695 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52381.978316 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52381.978316 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 55818.195660 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 55818.195660 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23933.336319 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23933.336319 # average ReadSharedReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23248.618785 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20031.250000 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 55818.195660 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33260.707671 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 35806.833134 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23248.618785 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20031.250000 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 55818.195660 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33260.707671 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 35806.833134 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 54 # number of cycles access was blocked
1933c1934
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 27 # average number of cycles each access was blocked
1937,2027c1938,2026
< system.cpu1.l2cache.writebacks::writebacks 37014 # number of writebacks
< system.cpu1.l2cache.writebacks::total 37014 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 288 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 288 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 20 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 127 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 127 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 20 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 415 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 435 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 20 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 415 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 435 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 719 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 229 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 948 # number of ReadReq MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3215 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::total 3215 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35422 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 35422 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29485 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29485 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22454 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22454 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35647 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 35647 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 27268 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 27268 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73931 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73931 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 719 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 229 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27268 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109578 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 137794 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 719 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 229 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27268 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109578 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35422 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 173216 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5722 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5835 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5009 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5009 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10731 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10844 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13516000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3329000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 16845000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1189902692 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1189902692 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 503727499 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 503727499 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348590500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348590500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 324000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 324000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1162178500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1162178500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 895970500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 895970500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1327142494 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1327142494 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13516000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3329000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 895970500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2489320994 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 3402136494 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13516000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3329000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 895970500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2489320994 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1189902692 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 4592039186 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9155500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 944653500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 953809000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 820084500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 820084500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9155500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1764738000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1773893500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021646 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.079459 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026262 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.writebacks::writebacks 25088 # number of writebacks
> system.cpu1.l2cache.writebacks::total 25088 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 258 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 258 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 13 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 45 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 45 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 13 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 303 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 13 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 303 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 316 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 724 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 240 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 964 # number of ReadReq MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 1571 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::total 1571 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 18681 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 18681 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27711 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27711 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22526 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22526 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31931 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 31931 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13122 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13122 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 65943 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 65943 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 724 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 240 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13122 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 97874 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 111960 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 724 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 240 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13122 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 97874 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 18681 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 130641 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2845 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 2957 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2191 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2191 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5036 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5148 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 12488000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3367500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 15855500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1045426686 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1045426686 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 554064000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 554064000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 417044500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 417044500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1323500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1323500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1465371000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1465371000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 653754000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 653754000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1181307497 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1181307497 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 12488000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3367500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 653754000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2646678497 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 3316287997 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 12488000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3367500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 653754000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2646678497 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1045426686 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 4361714683 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14231000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 333495000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 347726000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 208256000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 208256000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14231000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 541751000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 555982000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.036091 # mshr miss rate for ReadReq accesses
2032,2052c2031,2049
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936151 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936151 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954474 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.954474 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.481060 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.481060 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026306 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026306 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.359693 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.359693 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021646 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079459 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026306 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391854 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101895 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021646 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079459 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026306 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391854 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.955980 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.955980 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.966366 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.966366 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.639285 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.639285 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.015656 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.447882 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.447882 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.496366 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.105420 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.496366 # mshr miss rate for overall accesses
2054,2090c2051,2087
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.128088 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17768.987342 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33592.193891 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17084.195320 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17084.195320 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15524.650396 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15524.650396 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 324000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 324000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32602.420961 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32602.420961 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32857.947044 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17951.096211 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17951.096211 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22717.342843 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24690.019115 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18798.331015 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14537.117904 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32857.947044 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22717.342843 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33592.193891 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26510.479321 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165091.488990 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163463.410454 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163722.200040 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163722.200040 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81022.123894 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164452.334358 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163582.949096 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123009 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16447.614108 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55962.030191 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19994.370467 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19994.370467 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18513.917251 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18513.917251 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45891.797939 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45891.797939 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49821.216278 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.069681 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.069681 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27041.691328 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29620.292935 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27041.691328 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33387.027679 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117221.441125 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117594.183294 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95050.661798 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 95050.661798 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 107575.655282 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 107999.611500 # average overall mshr uncacheable latency
2092,2122c2089,2125
< system.cpu1.toL2Bus.trans_dist::ReadReq 80046 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 1329975 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 5009 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 511761 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 1258534 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 43565 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 76909 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43045 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 89356 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 97332 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 80052 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1036579 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 560078 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3090316 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1000986 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7189 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70268 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 4168759 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66348288 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29828599 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11528 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 132864 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 96321279 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 1191896 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 3797471 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 1.302048 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.459146 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 2085429 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1050114 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 105283 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 105064 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 32952 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 1055933 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 2191 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 2191 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 125445 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 933113 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 22957 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 71384 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41419 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 84915 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 57410 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 54585 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 838149 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 236592 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 39 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2498025 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 734861 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6388 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50317 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 3289591 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 53648704 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21442516 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10564 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 96276 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 75198060 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 344587 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 2379730 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.062577 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.242581 # Request fanout histogram
2124,2126c2127,2129
< system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 2650451 69.80% 69.80% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 1147020 30.20% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 2231032 93.75% 93.75% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 148479 6.24% 99.99% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 219 0.01% 100.00% # Request fanout histogram
2128c2131
< system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2130,2133c2133,2136
< system.cpu1.toL2Bus.snoop_fanout::total 3797471 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 1487742991 # Layer occupancy (ticks)
< system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
< system.cpu1.toL2Bus.snoopLayer0.occupancy 87115499 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 2379730 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 1153078495 # Layer occupancy (ticks)
> system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu1.toL2Bus.snoopLayer0.occupancy 79714518 # Layer occupancy (ticks)
2135,2137c2138,2140
< system.cpu1.toL2Bus.respLayer0.occupancy 1555110854 # Layer occupancy (ticks)
< system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
< system.cpu1.toL2Bus.respLayer1.occupancy 456039835 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 1257481819 # Layer occupancy (ticks)
> system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu1.toL2Bus.respLayer1.occupancy 326951344 # Layer occupancy (ticks)
2139c2142
< system.cpu1.toL2Bus.respLayer2.occupancy 4307000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 3747000 # Layer occupancy (ticks)
2141c2144
< system.cpu1.toL2Bus.respLayer3.occupancy 37064974 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 26275944 # Layer occupancy (ticks)
2143,2147c2146,2150
< system.iobus.trans_dist::ReadReq 30994 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30994 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
< system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 31009 # Transaction distribution
> system.iobus.trans_dist::ReadResp 31009 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
> system.iobus.trans_dist::WriteResp 59425 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes)
2152c2155
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2168,2172c2171,2175
< system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72920 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72920 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 180832 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes)
2177c2180
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2193,2197c2196,2200
< system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2483914 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 40103000 # Layer occupancy (ticks)
2207c2210
< system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
2237c2240
< system.iobus.reqLayer27.occupancy 187482956 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 186411762 # Layer occupancy (ticks)
2241c2244
< system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks)
2243c2246
< system.iobus.respLayer3.occupancy 36744000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks)
2245,2246c2248,2249
< system.iocache.tags.replacements 36426 # number of replacements
< system.iocache.tags.tagsinuse 1.010803 # Cycle average of tags in use
---
> system.iocache.tags.replacements 36433 # number of replacements
> system.iocache.tags.tagsinuse 14.472862 # Cycle average of tags in use
2248c2251
< system.iocache.tags.sampled_refs 36442 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks.
2250,2253c2253,2256
< system.iocache.tags.warmup_cycle 270452648000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.010803 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.063175 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.063175 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 271656669000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.472862 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.904554 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.904554 # Average percentage of cache occupancy
2257,2260c2260,2263
< system.iocache.tags.tag_accesses 328140 # Number of tag accesses
< system.iocache.tags.data_accesses 328140 # Number of data accesses
< system.iocache.ReadReq_misses::realview.ide 236 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 236 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 328203 # Number of tag accesses
> system.iocache.tags.data_accesses 328203 # Number of data accesses
> system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
2263,2276c2266,2279
< system.iocache.demand_misses::realview.ide 236 # number of demand (read+write) misses
< system.iocache.demand_misses::total 236 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 236 # number of overall misses
< system.iocache.overall_misses::total 236 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ide 30330877 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 30330877 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4273955079 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4273955079 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 30330877 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 30330877 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 30330877 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 30330877 # number of overall miss cycles
< system.iocache.ReadReq_accesses::realview.ide 236 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 236 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
> system.iocache.demand_misses::total 243 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 243 # number of overall misses
> system.iocache.overall_misses::total 243 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ide 31866877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 31866877 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4715834885 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4715834885 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 31866877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 31866877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 31866877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 31866877 # number of overall miss cycles
> system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
2279,2282c2282,2285
< system.iocache.demand_accesses::realview.ide 236 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 236 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 236 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 236 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
2291,2299c2294,2302
< system.iocache.ReadReq_avg_miss_latency::realview.ide 128520.665254 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 128520.665254 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117986.834116 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 117986.834116 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 128520.665254 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 128520.665254 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 128520.665254 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 128520.665254 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 131139.411523 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 131139.411523 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130185.371163 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 130185.371163 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 131139.411523 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 131139.411523 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 131139.411523 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 131139.411523 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked
2301c2304
< system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
2303c2306
< system.iocache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked
2309,2310c2312,2313
< system.iocache.ReadReq_mshr_misses::realview.ide 236 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 236 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
2313,2324c2316,2327
< system.iocache.demand_mshr_misses::realview.ide 236 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 236 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 236 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 236 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 18530877 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 18530877 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2462755079 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2462755079 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 18530877 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 18530877 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 18530877 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 18530877 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 19716877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 19716877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904634885 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2904634885 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 19716877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 19716877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 19716877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 19716877 # number of overall MSHR miss cycles
2333,2340c2336,2343
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78520.665254 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 78520.665254 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67986.834116 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67986.834116 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 78520.665254 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 78520.665254 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 78520.665254 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 78520.665254 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 81139.411523 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 81139.411523 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80185.371163 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80185.371163 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 81139.411523 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 81139.411523 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 81139.411523 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 81139.411523 # average overall mshr miss latency
2342,2346c2345,2349
< system.l2c.tags.replacements 135428 # number of replacements
< system.l2c.tags.tagsinuse 64138.208301 # Cycle average of tags in use
< system.l2c.tags.total_refs 442739 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 199807 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.215833 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 133318 # number of replacements
> system.l2c.tags.tagsinuse 64014.997062 # Cycle average of tags in use
> system.l2c.tags.total_refs 446453 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 198047 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.254278 # Average number of references to valid blocks.
2348,2360c2351,2362
< system.l2c.tags.occ_blocks::writebacks 12941.285088 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.276334 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.031468 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 7274.373268 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 2166.846690 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 31945.045858 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 24.318023 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851962 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 4022.114049 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 1496.265741 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4197.799819 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.197468 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001057 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_blocks::writebacks 12007.955719 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 82.059666 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029625 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 9722.429733 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 3069.037039 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34559.641433 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.516745 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1816.838650 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 555.114204 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2192.374249 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.183227 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001252 # Average percentage of cache occupancy
2362,2376c2364,2377
< system.l2c.tags.occ_percent::cpu0.inst 0.110998 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.033063 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.487443 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000371 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.061373 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.022831 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064053 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.978671 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 29250 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 35037 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 144 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 5264 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 23842 # Occupied blocks per task id
---
> system.l2c.tags.occ_percent::cpu0.inst 0.148353 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.046830 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.527338 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000145 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.027723 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.008470 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033453 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.976791 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 30866 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 33781 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 78 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 5648 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 25140 # Occupied blocks per task id
2378,2379c2379,2380
< system.l2c.tags.age_task_id_blocks_1023::4 91 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
---
> system.l2c.tags.age_task_id_blocks_1023::4 81 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
2381,2442c2382,2443
< system.l2c.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 3030 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 31679 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.446320 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.534622 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 5824693 # Number of tag accesses
< system.l2c.tags.data_accesses 5824693 # Number of data accesses
< system.l2c.Writeback_hits::writebacks 232832 # number of Writeback hits
< system.l2c.Writeback_hits::total 232832 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 3079 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 930 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 4009 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 233 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 92 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 325 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 4022 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 2114 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 6136 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 393 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 81 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 44006 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 47229 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46346 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 166 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 21446 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 11079 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8110 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 178893 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 393 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 81 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 44006 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 51251 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 46346 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 166 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 21446 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 13193 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 8110 # number of demand (read+write) hits
< system.l2c.demand_hits::total 185029 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 393 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 81 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 44006 # number of overall hits
< system.l2c.overall_hits::cpu0.data 51251 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 46346 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 166 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 21446 # number of overall hits
< system.l2c.overall_hits::cpu1.data 13193 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 8110 # number of overall hits
< system.l2c.overall_hits::total 185029 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 8747 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 4112 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 12859 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 835 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1227 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 2062 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 10918 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 8428 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 19346 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 114 # number of ReadSharedReq misses
---
> system.l2c.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 2821 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 30623 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.470978 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.001251 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.515457 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 5802831 # Number of tag accesses
> system.l2c.tags.data_accesses 5802831 # Number of data accesses
> system.l2c.Writeback_hits::writebacks 230256 # number of Writeback hits
> system.l2c.Writeback_hits::total 230256 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 3083 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 464 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 3547 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 148 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 197 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 345 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 4599 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 5978 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 467 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 52086 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 51828 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 50532 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 70 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 10095 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 4893 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3282 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 173352 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 467 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 52086 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 56427 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 50532 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 70 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 10095 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 6272 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 3282 # number of demand (read+write) hits
> system.l2c.demand_hits::total 179330 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 467 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 52086 # number of overall hits
> system.l2c.overall_hits::cpu0.data 56427 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 50532 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 70 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 10095 # number of overall hits
> system.l2c.overall_hits::cpu1.data 6272 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 3282 # number of overall hits
> system.l2c.overall_hits::total 179330 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 9481 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 2162 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 11643 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 497 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1197 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1694 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 11009 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 7938 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 18947 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 137 # number of ReadSharedReq misses
2444,2453c2445,2453
< system.l2c.ReadSharedReq_misses::cpu0.inst 19630 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 8718 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 129027 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 38 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 5812 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 2889 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8839 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 175069 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 114 # number of demand (read+write) misses
---
> system.l2c.ReadSharedReq_misses::cpu0.inst 22412 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 9738 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133466 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 16 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 3021 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 1593 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5720 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 176104 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 137 # number of demand (read+write) misses
2455,2464c2455,2463
< system.l2c.demand_misses::cpu0.inst 19630 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 19636 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 129027 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 38 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 5812 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 11317 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 8839 # number of demand (read+write) misses
< system.l2c.demand_misses::total 194415 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 114 # number of overall misses
---
> system.l2c.demand_misses::cpu0.inst 22412 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 20747 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 133466 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 3021 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 9531 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 5720 # number of demand (read+write) misses
> system.l2c.demand_misses::total 195051 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 137 # number of overall misses
2466,2645c2465,2634
< system.l2c.overall_misses::cpu0.inst 19630 # number of overall misses
< system.l2c.overall_misses::cpu0.data 19636 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 129027 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 38 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 5812 # number of overall misses
< system.l2c.overall_misses::cpu1.data 11317 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 8839 # number of overall misses
< system.l2c.overall_misses::total 194415 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 8346500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 5785000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 14131500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1392500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1414500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 2807000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 1077000000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 690485000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 1767485000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10253000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 303000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1569061500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 759147500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13107894109 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3343000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 83000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 479575000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 252543500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1024779080 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 17206982689 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 10253000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 303000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1569061500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 1836147500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13107894109 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 3343000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 83000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 479575000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 943028500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1024779080 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 18974467689 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 10253000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 303000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1569061500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 1836147500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13107894109 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 3343000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 83000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 479575000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 943028500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1024779080 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 18974467689 # number of overall miss cycles
< system.l2c.Writeback_accesses::writebacks 232832 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 232832 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 11826 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5042 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 16868 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 1068 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 1319 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2387 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 14940 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 10542 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 25482 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 507 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 82 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 63636 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 55947 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 175373 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 204 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 38 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 27258 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 13968 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 16949 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 353962 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 507 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 82 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 63636 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 70887 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 175373 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 204 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 27258 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 24510 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 16949 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 379444 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 507 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 82 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 63636 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 70887 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 175373 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 204 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 27258 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 24510 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 16949 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 379444 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.739641 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.815549 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.762331 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.781835 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.930250 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.863846 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.730790 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.799469 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.759203 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.224852 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.012195 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.308473 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.155826 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.735729 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.186275 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.026316 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.213222 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.206830 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.521506 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.494598 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.224852 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.012195 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.308473 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.277004 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735729 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.186275 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.026316 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.213222 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.461730 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.521506 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.512368 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.224852 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.012195 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.308473 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.277004 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735729 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.186275 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.026316 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.213222 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.461730 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.521506 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.512368 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 954.212873 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1406.857977 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1098.957928 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1667.664671 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1152.811736 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1361.299709 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 98644.440374 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81927.503560 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 91361.780213 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89938.596491 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 303000 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79931.813551 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87078.171599 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87973.684211 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 83000 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82514.624914 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 87415.541710 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 98286.862260 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89938.596491 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 79931.813551 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 93509.243227 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87973.684211 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 82514.624914 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 83328.488115 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 97597.755775 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89938.596491 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 79931.813551 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 93509.243227 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101590.319150 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87973.684211 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 82514.624914 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 83328.488115 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115938.350492 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 97597.755775 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.l2c.overall_misses::cpu0.inst 22412 # number of overall misses
> system.l2c.overall_misses::cpu0.data 20747 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 133466 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 3021 # number of overall misses
> system.l2c.overall_misses::cpu1.data 9531 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 5720 # number of overall misses
> system.l2c.overall_misses::total 195051 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 34581000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 5348500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 39929500 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3790500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2694500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 6485000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1642305000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 1048460500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 2690765500 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 19306500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 133000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2926929000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 1335340500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20225428758 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 2276000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 405795500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 223263000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 972266423 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 26110738681 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 19306500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 133000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 2926929000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 2977645500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20225428758 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 2276000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 405795500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1271723500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 972266423 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 28801504181 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 19306500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 133000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 2926929000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 2977645500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20225428758 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 2276000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 405795500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1271723500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 972266423 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 28801504181 # number of overall miss cycles
> system.l2c.Writeback_accesses::writebacks 230256 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 230256 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 12564 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 2626 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 15190 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 645 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 1394 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2039 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 15608 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 9317 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 24925 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 604 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 87 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 74498 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 61566 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183998 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 86 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 13 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 13116 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 6486 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 9002 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 349456 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 604 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 87 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 74498 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 77174 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183998 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 86 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 13 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 13116 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 15803 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 9002 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 374381 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 604 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 87 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 74498 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 77174 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183998 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 86 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 13 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 13116 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 15803 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 9002 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 374381 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754616 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.823305 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.766491 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.770543 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.858680 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.830799 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.705343 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.851991 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.760160 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.226821 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.011494 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.300840 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158172 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.725367 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.186047 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.230329 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.245606 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.635414 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.503938 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.226821 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.011494 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.300840 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.268834 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.725367 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.186047 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.230329 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.603113 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.635414 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.520996 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.226821 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.011494 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.300840 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.268834 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.725367 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.186047 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.230329 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.603113 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.635414 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.520996 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3647.400063 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2473.866790 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 3429.485528 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7626.760563 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2251.044277 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 3828.217237 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 149178.399491 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132081.191736 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 142015.385021 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140923.357664 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 133000 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 130596.510798 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137126.771411 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 142250 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134324.892420 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140152.542373 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 148268.856363 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140923.357664 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 130596.510798 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 143521.738083 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 142250 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 134324.892420 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 133430.227678 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 147661.402305 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140923.357664 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 130596.510798 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 143521.738083 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 142250 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 134324.892420 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 133430.227678 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 147661.402305 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 687 # number of cycles access was blocked
2647c2636
< system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked
2649c2638
< system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 229 # average number of cycles each access was blocked
2653,2675c2642,2667
< system.l2c.writebacks::writebacks 103399 # number of writebacks
< system.l2c.writebacks::total 103399 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 5 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 3802 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 3802 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 8747 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 4112 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 12859 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 835 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1227 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 2062 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 10918 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 8428 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 19346 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 114 # number of ReadSharedReq MSHR misses
---
> system.l2c.writebacks::writebacks 102021 # number of writebacks
> system.l2c.writebacks::total 102021 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 6 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 1 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 6 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 3105 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 3105 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 9481 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 2162 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 11643 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 497 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1197 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1694 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 11009 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 7938 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 18947 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 137 # number of ReadSharedReq MSHR misses
2677,2686c2669,2677
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19629 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8718 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 129027 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 38 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 5808 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2889 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 8839 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 175064 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 114 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22406 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9737 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133466 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3015 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1593 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5720 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 176091 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 137 # number of demand (read+write) MSHR misses
2688,2697c2679,2687
< system.l2c.demand_mshr_misses::cpu0.inst 19629 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 19636 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 129027 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 38 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 5808 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 11317 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8839 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 194410 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 114 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 22406 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 20746 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133466 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 3015 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 9531 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5720 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 195038 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 137 # number of overall MSHR misses
2699,2775c2689,2761
< system.l2c.overall_mshr_misses::cpu0.inst 19629 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 19636 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 129027 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 38 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 5808 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 11317 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 8839 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 194410 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29426 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5718 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 38683 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26162 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5009 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 31171 # number of WriteReq MSHR uncacheable
< system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55588 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10727 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 69854 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 181705001 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 86116001 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 267821002 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17444000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25472500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 42916500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 967820000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606205000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 1574025000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 9113000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 293000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1372734500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 671967500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11817624109 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 2963000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 73000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 421007000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 223653500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 936389080 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 15455817689 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9113000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1372734500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 1639787500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11817624109 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2963000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 421007000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 829858500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 936389080 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 17029842689 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9113000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 293000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1372734500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 1639787500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11817624109 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2963000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 421007000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 829858500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 936389080 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 17029842689 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 214924500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4931392500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6782000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 841666000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 5994765000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3673788500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 734928500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4408717000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 214924500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8605181000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6782000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1576594500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 10403482000 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_misses::cpu0.inst 22406 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 20746 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133466 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 3015 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 9531 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5720 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 195038 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3915 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32040 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2841 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 38908 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2191 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable
> system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3915 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60762 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5032 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 69821 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 714754501 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 161986000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 876740501 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 38415000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 91799500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 130214500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1532215000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 969080500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 2501295500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 17936500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2702366000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1237877500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18890768758 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 2116000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 375139500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 207333000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 915066423 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 24348726681 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 17936500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 2702366000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2770092500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18890768758 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2116000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 375139500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 1176413500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 915066423 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 26850022181 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 17936500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 2702366000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2770092500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18890768758 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2116000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 375139500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 1176413500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 915066423 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 26850022181 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443682000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5515186000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11878500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 282299000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6253045500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4452219000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 171006500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4623225500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443682000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9967405000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11878500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 453305500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10876271000 # number of overall MSHR uncacheable cycles
2778,2874c2764,2854
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.739641 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.815549 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.762331 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.781835 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.930250 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.863846 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.730790 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.799469 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.759203 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.224852 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.012195 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.308457 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.155826 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735729 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.186275 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.026316 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.213075 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.206830 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521506 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.494584 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.224852 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012195 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.308457 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.277004 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735729 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186275 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.026316 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.213075 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.461730 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521506 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.512355 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.224852 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012195 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.308457 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.277004 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735729 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186275 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.026316 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.213075 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.461730 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521506 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.512355 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.408140 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20942.607247 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20827.513959 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20891.017964 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20759.983700 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20813.045587 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 88644.440374 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71927.503560 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 81361.780213 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69934.000713 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77078.171599 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73000 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72487.431129 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 77415.541710 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88286.670526 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69934.000713 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83509.243227 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72487.431129 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73328.488115 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 87597.565398 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79938.596491 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69934.000713 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83509.243227 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91590.319150 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77973.684211 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72487.431129 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73328.488115 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105938.350492 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 87597.565398 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167586.233263 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147195.872683 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154971.563736 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140424.604388 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146721.601118 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141436.495461 # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154802.853134 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60017.699115 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146974.410366 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 148931.800613 # average overall mshr uncacheable latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754616 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.823305 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.766491 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.770543 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.858680 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.830799 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.705343 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851991 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.760160 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.226821 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.300760 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158155 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.725367 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.186047 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.229872 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245606 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.635414 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.503900 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.226821 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.300760 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.268821 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.725367 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186047 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.229872 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.603113 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.635414 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.520961 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.226821 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.300760 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.268821 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.725367 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186047 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.229872 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.603113 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.635414 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.520961 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75388.092079 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 74924.144311 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75301.941166 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77293.762575 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76691.311612 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76868.063754 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139178.399491 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122081.191736 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 132015.385021 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127131.303276 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130152.542373 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 138273.544253 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133524.173335 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123430.227678 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 137665.594300 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133524.173335 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123430.227678 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 137665.594300 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172134.394507 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99366.068286 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160713.619307 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155010.758304 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 78049.520767 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149556.028208 # average WriteReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164040.107304 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90084.558824 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 155773.635439 # average overall mshr uncacheable latency
2876,2888c2856,2868
< system.membus.trans_dist::ReadReq 38683 # Transaction distribution
< system.membus.trans_dist::ReadResp 213983 # Transaction distribution
< system.membus.trans_dist::WriteReq 31171 # Transaction distribution
< system.membus.trans_dist::WriteResp 31171 # Transaction distribution
< system.membus.trans_dist::Writeback 139589 # Transaction distribution
< system.membus.trans_dist::CleanEvict 18226 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 78324 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 41642 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 15039 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
< system.membus.trans_dist::ReadExReq 39751 # Transaction distribution
< system.membus.trans_dist::ReadExResp 19228 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 175300 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 38908 # Transaction distribution
> system.membus.trans_dist::ReadResp 215242 # Transaction distribution
> system.membus.trans_dist::WriteReq 30913 # Transaction distribution
> system.membus.trans_dist::WriteResp 30913 # Transaction distribution
> system.membus.trans_dist::Writeback 138211 # Transaction distribution
> system.membus.trans_dist::CleanEvict 17281 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 73717 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 40307 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 13440 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
> system.membus.trans_dist::ReadExReq 39445 # Transaction distribution
> system.membus.trans_dist::ReadExResp 18844 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 176334 # Transaction distribution
2891c2871
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes)
2893,2899c2873,2879
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14776 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 682330 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 805060 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108902 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 108902 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 913962 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13712 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 674810 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 796498 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 905407 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes)
2901,2903c2881,2883
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29552 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19274524 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 19468214 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27424 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19258908 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 19450490 # Cumulative packet size per connected master and slave (bytes)
2906,2908c2886,2888
< system.membus.pkt_size::total 21785334 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 126049 # Total snoops (count)
< system.membus.snoop_fanout::samples 599148 # Request fanout histogram
---
> system.membus.pkt_size::total 21767610 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 121785 # Total snoops (count)
> system.membus.snoop_fanout::samples 591590 # Request fanout histogram
2913c2893
< system.membus.snoop_fanout::1 599148 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 591590 100.00% 100.00% # Request fanout histogram
2918,2919c2898,2899
< system.membus.snoop_fanout::total 599148 # Request fanout histogram
< system.membus.reqLayer0.occupancy 91414000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 591590 # Request fanout histogram
> system.membus.reqLayer0.occupancy 91392000 # Layer occupancy (ticks)
2923c2903
< system.membus.reqLayer2.occupancy 12977999 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11844500 # Layer occupancy (ticks)
2925c2905
< system.membus.reqLayer5.occupancy 1005422091 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1004304747 # Layer occupancy (ticks)
2927c2907
< system.membus.respLayer2.occupancy 1166590180 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1168943229 # Layer occupancy (ticks)
2929c2909
< system.membus.respLayer3.occupancy 64371509 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 64602498 # Layer occupancy (ticks)
2972,2985c2952,2971
< system.toL2Bus.trans_dist::ReadReq 38687 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 518927 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 31171 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 372432 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 99547 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 82215 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 41967 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 124182 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 51561 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 51561 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 480255 # Transaction distribution
---
> system.toL2Bus.snoop_filter.tot_requests 982687 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 493902 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 158313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 22110 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 21385 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 725 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 38912 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 507516 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 368484 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 106099 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 77161 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 40652 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 117813 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 51062 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 51062 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 468619 # Transaction distribution
2987,2996c2973,2982
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1133004 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 361504 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1494508 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32818575 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6820071 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 39638646 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 465665 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 1285667 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.162057 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.368503 # Request fanout histogram
---
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1216476 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 257070 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1473546 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35115318 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4064004 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 39179322 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 452154 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 1258731 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.293892 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.456806 # Request fanout histogram
2998,3000c2984,2986
< system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 1077316 83.79% 83.79% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 208351 16.21% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 889525 70.67% 70.67% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 368481 29.27% 99.94% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 725 0.06% 100.00% # Request fanout histogram
3002c2988
< system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3004,3005c2990,2991
< system.toL2Bus.snoop_fanout::total 1285667 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 860205550 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 1258731 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 836264644 # Layer occupancy (ticks)
3007c2993
< system.toL2Bus.snoopLayer0.occupancy 331500 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks)
3009c2995
< system.toL2Bus.respLayer0.occupancy 646726661 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 685711951 # Layer occupancy (ticks)
3011c2997
< system.toL2Bus.respLayer1.occupancy 269148617 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 211221475 # Layer occupancy (ticks)