3,5c3,5
< sim_seconds 2.846047 # Number of seconds simulated
< sim_ticks 2846047385500 # Number of ticks simulated
< final_tick 2846047385500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.846057 # Number of seconds simulated
> sim_ticks 2846057099000 # Number of ticks simulated
> final_tick 2846057099000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 159625 # Simulator instruction rate (inst/s)
< host_op_rate 193311 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 3563510303 # Simulator tick rate (ticks/s)
< host_mem_usage 654020 # Number of bytes of host memory used
< host_seconds 798.66 # Real time elapsed on the host
< sim_insts 127487011 # Number of instructions simulated
< sim_ops 154390534 # Number of ops (including micro ops) simulated
---
> host_inst_rate 155095 # Simulator instruction rate (inst/s)
> host_op_rate 187821 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3461671389 # Simulator tick rate (ticks/s)
> host_mem_usage 654788 # Number of bytes of host memory used
> host_seconds 822.16 # Real time elapsed on the host
> sim_insts 127513349 # Number of instructions simulated
> sim_ops 154419501 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu0.dtb.walker 7424 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory
18,25c18,24
< system.physmem.bytes_read::cpu0.inst 1468992 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1221616 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8255360 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 381888 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 706136 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 588160 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1469184 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1233972 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8227712 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 2752 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 383104 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 711064 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 574528 # Number of bytes read from this memory
27,31c26,30
< system.physmem.bytes_read::total 12633224 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1468992 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 381888 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1850880 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8928128 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 12611084 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1469184 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 383104 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1852288 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8917568 # Number of bytes written to this memory
34,35c33,34
< system.physmem.bytes_written::total 8945692 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 116 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8935132 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory
37,44c36,42
< system.physmem.num_reads::cpu0.inst 22953 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 19610 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 128990 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 5967 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 11055 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 9190 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 22956 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 19804 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 128558 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 43 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 5986 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 11132 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 8977 # Number of read requests responded to by this memory
46,47c44,45
< system.physmem.num_reads::total 197938 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 139502 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 197593 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 139337 # Number of write requests responded to by this memory
50,51c48,49
< system.physmem.num_writes::total 143893 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 2609 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 143728 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 2721 # Total read bandwidth from this memory (bytes/s)
53,60c51,57
< system.physmem.bw_read::cpu0.inst 516152 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 429232 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 2900640 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 134182 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 248111 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 206659 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 516217 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 433572 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 2890916 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 967 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 134609 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 249842 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 201868 # Total read bandwidth from this memory (bytes/s)
62,66c59,63
< system.physmem.bw_read::total 4438866 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 516152 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 134182 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 650334 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3137027 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4431072 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 516217 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 134609 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 650826 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3133306 # Write bandwidth from this memory (bytes/s)
69,71c66,68
< system.physmem.bw_write::total 3143199 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3137027 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 2609 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3139477 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3133306 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 2721 # Total bandwidth to/from this memory (bytes/s)
73,80c70,76
< system.physmem.bw_total::cpu0.inst 516152 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 435390 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 2900640 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 134182 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 248125 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 206659 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 516217 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 439730 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 2890916 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 967 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 134609 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 249856 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 201868 # Total bandwidth to/from this memory (bytes/s)
82,126c78,122
< system.physmem.bw_total::total 7582065 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 197938 # Number of read requests accepted
< system.physmem.writeReqs 143893 # Number of write requests accepted
< system.physmem.readBursts 197938 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 143893 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12658432 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8958080 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12633224 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8945692 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 51249 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 12124 # Per bank write bursts
< system.physmem.perBankRdBursts::1 12298 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12956 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12344 # Per bank write bursts
< system.physmem.perBankRdBursts::4 15465 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12573 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12691 # Per bank write bursts
< system.physmem.perBankRdBursts::7 13082 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12243 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12357 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11723 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11147 # Per bank write bursts
< system.physmem.perBankRdBursts::12 12049 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11871 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11344 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11521 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8574 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8801 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9504 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8801 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8786 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8838 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9085 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9267 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8941 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8908 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8524 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8283 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8972 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8287 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8306 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8093 # Per bank write bursts
---
> system.physmem.bw_total::total 7570549 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 197593 # Number of read requests accepted
> system.physmem.writeReqs 143728 # Number of write requests accepted
> system.physmem.readBursts 197593 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 143728 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12635520 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 10432 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8947648 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12611084 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8935132 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 163 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 51189 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 12157 # Per bank write bursts
> system.physmem.perBankRdBursts::1 12292 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12950 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12405 # Per bank write bursts
> system.physmem.perBankRdBursts::4 15321 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12434 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12677 # Per bank write bursts
> system.physmem.perBankRdBursts::7 13084 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12267 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12426 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11655 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11073 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11997 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11769 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11320 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11603 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8631 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8804 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9518 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8865 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8658 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8780 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9135 # Per bank write bursts
> system.physmem.perBankWrBursts::7 9275 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8996 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8951 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8409 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8136 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8895 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8304 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8310 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8140 # Per bank write bursts
128,129c124,125
< system.physmem.numWrRetry 26 # Number of times write queue was full causing retry
< system.physmem.totGap 2846046899000 # Total gap between requests
---
> system.physmem.numWrRetry 40 # Number of times write queue was full causing retry
> system.physmem.totGap 2846056522500 # Total gap between requests
132c128
< system.physmem.readPktSize::2 554 # Read request sizes (log2)
---
> system.physmem.readPktSize::2 555 # Read request sizes (log2)
136c132
< system.physmem.readPktSize::6 197356 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 197010 # Read request sizes (log2)
143,154c139,150
< system.physmem.writePktSize::6 139502 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 97008 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 48975 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 12438 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 9719 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 7811 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 6380 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 5314 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 4715 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3822 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 751 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 280 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 139337 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 84527 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 62953 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 11439 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 9638 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7653 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 5113 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 4583 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3751 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 746 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see
156,158c152,154
< system.physmem.rdQLenPdf::12 162 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::12 175 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
160,163c156,159
< system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
191,296c187,294
< system.physmem.wrQLenPdf::15 2733 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3162 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4836 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5514 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6014 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6576 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8463 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8832 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 10148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9569 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9515 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8822 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9294 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 10498 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 8607 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 8058 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7671 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 489 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 332 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 297 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 100 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 92 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 117 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 117 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 50 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 53 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 90544 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 238.739707 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 135.462322 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 300.134416 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 48559 53.63% 53.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17642 19.48% 73.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6276 6.93% 80.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3581 3.95% 84.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2857 3.16% 87.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1437 1.59% 88.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 927 1.02% 89.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1107 1.22% 90.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8158 9.01% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 90544 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6994 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.279525 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 555.958801 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6993 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6994 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6994 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.012868 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.560049 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 12.293161 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5872 83.96% 83.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 361 5.16% 89.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 205 2.93% 92.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 59 0.84% 92.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 60 0.86% 93.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 157 2.24% 96.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 22 0.31% 96.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 8 0.11% 96.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 14 0.20% 96.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 7 0.10% 96.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 6 0.09% 96.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 8 0.11% 96.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 162 2.32% 99.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 3 0.04% 99.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 7 0.10% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 9 0.13% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 3 0.04% 99.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.01% 99.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 1 0.01% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.01% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.01% 99.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.01% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 12 0.17% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 2 0.03% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 3 0.04% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 6 0.09% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 2 0.03% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-203 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6994 # Writes before turning the bus around for reads
< system.physmem.totQLat 5635724944 # Total ticks spent queuing
< system.physmem.totMemAccLat 9344249944 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 988940000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 28493.77 # Average queueing delay per DRAM burst
---
> system.physmem.wrQLenPdf::15 2731 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4878 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5520 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6053 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6627 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7062 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8465 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8859 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 10175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9630 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8882 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 9201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 10384 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 8548 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7940 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7665 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 412 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 283 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 342 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 221 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 188 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 200 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 157 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 100 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 44 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 90385 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 238.790065 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 135.540737 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 300.321787 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 48391 53.54% 53.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17645 19.52% 73.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6369 7.05% 80.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3664 4.05% 84.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2743 3.03% 87.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1397 1.55% 88.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 884 0.98% 89.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1036 1.15% 90.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8256 9.13% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 90385 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.264567 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 537.756673 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6984 99.99% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.015319 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.579154 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 12.029266 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5867 83.99% 83.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 359 5.14% 89.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 198 2.83% 91.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 50 0.72% 92.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 72 1.03% 93.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 159 2.28% 95.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 19 0.27% 96.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 12 0.17% 96.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 11 0.16% 96.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 8 0.11% 96.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 6 0.09% 96.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 5 0.07% 96.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 162 2.32% 99.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 6 0.09% 99.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 6 0.09% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 10 0.14% 99.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 1 0.01% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 2 0.03% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.03% 99.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 2 0.03% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.01% 99.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.01% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 14 0.20% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.01% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 4 0.06% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads
> system.physmem.totQLat 5478181174 # Total ticks spent queuing
> system.physmem.totMemAccLat 9179993674 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 987150000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 27747.46 # Average queueing delay per DRAM burst
298,301c296,299
< system.physmem.avgMemAccLat 47243.77 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.15 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 46497.46 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.14 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 4.43 # Average system read bandwidth in MiByte/s
307,313c305,311
< system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing
< system.physmem.readRowHits 164502 # Number of row buffer hits during reads
< system.physmem.writeRowHits 82711 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes
< system.physmem.avgGap 8325888.81 # Average gap between requests
---
> system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 23.99 # Average write queue length when enqueuing
> system.physmem.readRowHits 164056 # Number of row buffer hits during reads
> system.physmem.writeRowHits 82794 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.10 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 59.21 # Row buffer hit rate for writes
> system.physmem.avgGap 8338357.51 # Average gap between requests
315,325c313,323
< system.physmem_0.actEnergy 356257440 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 194386500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 807557400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 464330880 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 185889868320 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 83150566875 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1634688457500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1905551424915 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.543458 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2719326804644 # Time in different power states
< system.physmem_0.memoryStateTime::REF 95035720000 # Time in different power states
---
> system.physmem_0.actEnergy 356771520 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 194667000 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 805888200 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 464395680 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 83219414895 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1634632736250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1905564250425 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.546132 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2719229075521 # Time in different power states
> system.physmem_0.memoryStateTime::REF 95035980000 # Time in different power states
327c325
< system.physmem_0.memoryStateTime::ACT 31683407856 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 31791929979 # Time in different power states
329,339c327,337
< system.physmem_1.actEnergy 328255200 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 179107500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 735181200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 442674720 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 185889868320 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 82066427730 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1635639456750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1905280971420 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.448430 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2720915660225 # Time in different power states
< system.physmem_1.memoryStateTime::REF 95035720000 # Time in different power states
---
> system.physmem_1.actEnergy 326539080 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 178171125 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 734050200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 441553680 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 82136174355 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1635582947250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1905289812570 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.449705 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2720812978493 # Time in different power states
> system.physmem_1.memoryStateTime::REF 95035980000 # Time in different power states
341c339
< system.physmem_1.memoryStateTime::ACT 30095909775 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30205644507 # Time in different power states
367,371c365,369
< system.cpu0.branchPred.lookups 19568417 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 12741959 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 982246 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 12413476 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 8819135 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 19599196 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 12768904 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 991514 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 12558764 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 8839837 # Number of BTB hits
373,375c371,373
< system.cpu0.branchPred.BTBHitPct 71.044847 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 3284365 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 198035 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 70.387795 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 3295346 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 199810 # Number of incorrect RAS predictions.
406,423c404,421
< system.cpu0.dtb.walker.walks 67683 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 67683 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45041 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22642 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walkWaitTime::samples 67683 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 67683 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 67683 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 6748 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 10568.612922 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 9555.209008 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 5781.304513 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-16383 6579 97.50% 97.50% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::16384-32767 156 2.31% 99.81% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 6748 # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walks 67395 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 67395 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44710 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22685 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walkWaitTime::samples 67395 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 67395 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 67395 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 6692 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 10409.593545 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 9352.624092 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 5969.180600 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-16383 6501 97.15% 97.15% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::16384-32767 173 2.59% 99.73% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::32768-49151 11 0.16% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 6692 # Table walker service (enqueue to completion) latency
427,430c425,428
< system.cpu0.dtb.walker.walkPageSizes::4K 5177 76.72% 76.72% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1571 23.28% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 6748 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67683 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkPageSizes::4K 5137 76.76% 76.76% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1555 23.24% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 6692 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67395 # Table walker requests started/completed, data/inst
432,433c430,431
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67683 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6748 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67395 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6692 # Table walker requests started/completed, data/inst
435,436c433,434
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6748 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 74431 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6692 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 74087 # Table walker requests started/completed, data/inst
439,442c437,440
< system.cpu0.dtb.read_hits 16473000 # DTB read hits
< system.cpu0.dtb.read_misses 62137 # DTB read misses
< system.cpu0.dtb.write_hits 13870452 # DTB write hits
< system.cpu0.dtb.write_misses 5546 # DTB write misses
---
> system.cpu0.dtb.read_hits 16492967 # DTB read hits
> system.cpu0.dtb.read_misses 61485 # DTB read misses
> system.cpu0.dtb.write_hits 13879033 # DTB write hits
> system.cpu0.dtb.write_misses 5910 # DTB write misses
447,449c445,447
< system.cpu0.dtb.flush_entries 3508 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 1130 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 1591 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 3512 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 1104 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 1584 # Number of TLB faults due to prefetch
451,453c449,451
< system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 16535137 # DTB read accesses
< system.cpu0.dtb.write_accesses 13875998 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 16554452 # DTB read accesses
> system.cpu0.dtb.write_accesses 13884943 # DTB write accesses
455,457c453,455
< system.cpu0.dtb.hits 30343452 # DTB hits
< system.cpu0.dtb.misses 67683 # DTB misses
< system.cpu0.dtb.accesses 30411135 # DTB accesses
---
> system.cpu0.dtb.hits 30372000 # DTB hits
> system.cpu0.dtb.misses 67395 # DTB misses
> system.cpu0.dtb.accesses 30439395 # DTB accesses
487,488c485,486
< system.cpu0.itb.walker.walks 3854 # Table walker walks requested
< system.cpu0.itb.walker.walksShort 3854 # Table walker walks initiated with short descriptors
---
> system.cpu0.itb.walker.walks 3867 # Table walker walks requested
> system.cpu0.itb.walker.walksShort 3867 # Table walker walks initiated with short descriptors
490,498c488,496
< system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3547 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 3854 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 3854 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 3854 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 2418 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 10984.077750 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 9918.433232 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 7783.469031 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-32767 2416 99.92% 99.92% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 3867 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 3867 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 3867 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 10756.092524 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 9615.276250 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 7885.681727 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-32767 2419 99.92% 99.92% # Table walker service (enqueue to completion) latency
501c499
< system.cpu0.itb.walker.walkCompletionTime::total 2418 # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency
505,507c503,505
< system.cpu0.itb.walker.walkPageSizes::4K 2118 87.59% 87.59% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::1M 300 12.41% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 2418 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::4K 2121 87.61% 87.61% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::1M 300 12.39% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated
509,510c507,508
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3854 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3854 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3867 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3867 # Table walker requests started/completed, data/inst
512,516c510,514
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2418 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2418 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 6272 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 36667532 # ITB inst hits
< system.cpu0.itb.inst_misses 3854 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 6288 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 36759532 # ITB inst hits
> system.cpu0.itb.inst_misses 3867 # ITB inst misses
525c523
< system.cpu0.itb.flush_entries 2221 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB
529c527
< system.cpu0.itb.perms_faults 7326 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 7295 # Number of TLB faults due to permissions restrictions
532,536c530,534
< system.cpu0.itb.inst_accesses 36671386 # ITB inst accesses
< system.cpu0.itb.hits 36667532 # DTB hits
< system.cpu0.itb.misses 3854 # DTB misses
< system.cpu0.itb.accesses 36671386 # DTB accesses
< system.cpu0.numCycles 154642199 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 36763399 # ITB inst accesses
> system.cpu0.itb.hits 36759532 # DTB hits
> system.cpu0.itb.misses 3867 # DTB misses
> system.cpu0.itb.accesses 36763399 # DTB accesses
> system.cpu0.numCycles 154883476 # number of cpu cycles simulated
539,545c537,543
< system.cpu0.committedInsts 75578579 # Number of instructions committed
< system.cpu0.committedOps 90977347 # Number of ops (including micro ops) committed
< system.cpu0.discardedOps 4937651 # Number of ops (including micro ops) which were discarded before commit
< system.cpu0.numFetchSuspends 2060 # Number of times Execute suspended instruction fetching
< system.cpu0.quiesceCycles 5537489017 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.cpi 2.046111 # CPI: cycles per instruction
< system.cpu0.ipc 0.488732 # IPC: instructions per cycle
---
> system.cpu0.committedInsts 75627253 # Number of instructions committed
> system.cpu0.committedOps 91033342 # Number of ops (including micro ops) committed
> system.cpu0.discardedOps 4957970 # Number of ops (including micro ops) which were discarded before commit
> system.cpu0.numFetchSuspends 2062 # Number of times Execute suspended instruction fetching
> system.cpu0.quiesceCycles 5537267530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.cpi 2.047985 # CPI: cycles per instruction
> system.cpu0.ipc 0.488285 # IPC: instructions per cycle
547,558c545,556
< system.cpu0.kern.inst.quiesce 2062 # number of quiesce instructions executed
< system.cpu0.tickCycles 120829876 # Number of cycles that the object actually ticked
< system.cpu0.idleCycles 33812323 # Total number of cycles that the object has spent stopped
< system.cpu0.dcache.tags.replacements 679563 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 486.133146 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 28909958 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 680075 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 42.509956 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 345411000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.133146 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949479 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.949479 # Average percentage of cache occupancy
---
> system.cpu0.kern.inst.quiesce 2064 # number of quiesce instructions executed
> system.cpu0.tickCycles 121009607 # Number of cycles that the object actually ticked
> system.cpu0.idleCycles 33873869 # Total number of cycles that the object has spent stopped
> system.cpu0.dcache.tags.replacements 680149 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 489.017964 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 28930962 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 680661 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 42.504216 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 345600000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.017964 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.955113 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.955113 # Average percentage of cache occupancy
561,562c559,560
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
564,631c562,629
< system.cpu0.dcache.tags.tag_accesses 60679422 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 60679422 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 14995018 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 14995018 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 12788335 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 12788335 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306891 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 306891 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356622 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 356622 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352102 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 352102 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 27783353 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 27783353 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 28090244 # number of overall hits
< system.cpu0.dcache.overall_hits::total 28090244 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 441719 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 441719 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 557349 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 557349 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131939 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 131939 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21205 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 21205 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21309 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 21309 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 999068 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 999068 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 1131007 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1131007 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5838844500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5838844500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8827018500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 8827018500 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 323291000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 323291000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480994000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 480994000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 412000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 412000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 14665863000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 14665863000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 14665863000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 14665863000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 15436737 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 15436737 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 13345684 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 13345684 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438830 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 438830 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377827 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 377827 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373411 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 373411 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 28782421 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 28782421 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 29221251 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 29221251 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028615 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.028615 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041762 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.041762 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300661 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300661 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056124 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056124 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057066 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057066 # miss rate for StoreCondReq accesses
---
> system.cpu0.dcache.tags.tag_accesses 60723709 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 60723709 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 15008806 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 15008806 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 12795540 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 12795540 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306691 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 306691 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356713 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 356713 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352309 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 352309 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 27804346 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 27804346 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 28111037 # number of overall hits
> system.cpu0.dcache.overall_hits::total 28111037 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 442745 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 442745 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 557072 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 557072 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131875 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 131875 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21262 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 21262 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21236 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 21236 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 999817 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 999817 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1131692 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1131692 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5845429500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5845429500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8925410000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 8925410000 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 323710500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 323710500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 479970000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 479970000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 445000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 445000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 14770839500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 14770839500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 14770839500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 14770839500 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 15451551 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 15451551 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 13352612 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 13352612 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438566 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 438566 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377975 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 377975 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373545 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 373545 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 28804163 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 28804163 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 29242729 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 29242729 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028654 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.028654 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041720 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.041720 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300696 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300696 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056252 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056252 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056850 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056850 # miss rate for StoreCondReq accesses
634,643c632,641
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038705 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.038705 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13218.459020 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13218.459020 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15837.506661 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 15837.506661 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15245.979722 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15245.979722 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22572.340326 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22572.340326 # average StoreCondReq miss latency
---
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038700 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.038700 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13202.700200 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13202.700200 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16022.004337 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 16022.004337 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15224.837739 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15224.837739 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22601.714070 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22601.714070 # average StoreCondReq miss latency
646,649c644,647
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14679.544335 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 14679.544335 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12967.084200 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 12967.084200 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14773.543058 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 14773.543058 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.996038 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 13051.996038 # average overall miss latency
658,735c656,733
< system.cpu0.dcache.writebacks::writebacks 493293 # number of writebacks
< system.cpu0.dcache.writebacks::total 493293 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69842 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 69842 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244235 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 244235 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15018 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15018 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 314077 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 314077 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 314077 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 314077 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371877 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 371877 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 313114 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 313114 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99356 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 99356 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6187 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6187 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21309 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 21309 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 684991 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 684991 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 784347 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 784347 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 18002 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18002 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16758 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16758 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34760 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34760 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4380232500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4380232500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4918203500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4918203500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1623471000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1623471000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94288500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94288500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459695000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459695000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 402000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 402000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9298436000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9298436000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10921907000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 10921907000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3751545500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3751545500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2725656000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725656000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6477201500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6477201500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024090 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024090 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023462 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023462 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226411 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226411 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016375 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016375 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057066 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057066 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023799 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.023799 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026842 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.026842 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11778.713123 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11778.713123 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15707.389321 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15707.389321 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16339.939209 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16339.939209 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15239.776952 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15239.776952 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21572.809611 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21572.809611 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 493052 # number of writebacks
> system.cpu0.dcache.writebacks::total 493052 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69962 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 69962 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244118 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 244118 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15072 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15072 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 314080 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 314080 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 314080 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 314080 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372783 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 372783 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312954 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 312954 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99314 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 99314 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6190 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6190 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21236 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 21236 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 685737 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 685737 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 785051 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 785051 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18001 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16756 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16756 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34757 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34757 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4391149500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4391149500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4970740000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4970740000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1612906500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1612906500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94756000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94756000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 458745000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458745000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 434000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 434000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9361889500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 9361889500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10974796000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 10974796000 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3751362500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3751362500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2725552500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725552500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6476915000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6476915000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024126 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024126 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023438 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023438 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226452 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226452 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016377 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016377 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056850 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056850 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023807 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.023807 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026846 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.026846 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11779.371645 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11779.371645 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15883.292752 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15883.292752 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16240.474656 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16240.474656 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15307.915994 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15307.915994 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21602.232059 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21602.232059 # average StoreCondReq mshr miss latency
738,747c736,745
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13574.537476 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13574.537476 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13924.840664 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13924.840664 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208396.039329 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208396.039329 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162648.048693 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162648.048693 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186340.664557 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186340.664557 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13652.303288 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13652.303288 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13979.723610 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13979.723610 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208397.450142 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208397.450142 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162661.285510 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162661.285510 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186348.505337 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186348.505337 # average overall mshr uncacheable latency
749,755c747,753
< system.cpu0.icache.tags.replacements 1878063 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.785549 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 34781277 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1878575 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 18.514713 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 6156628000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785549 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.replacements 1879741 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.785261 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 34871642 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1880253 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 18.546250 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 6165545000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785261 # Average occupied blocks per requestor
759,761c757,759
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
763,800c761,798
< system.cpu0.icache.tags.tag_accesses 75198332 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 75198332 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 34781277 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 34781277 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 34781277 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 34781277 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 34781277 # number of overall hits
< system.cpu0.icache.overall_hits::total 34781277 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1878593 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1878593 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1878593 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1878593 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1878593 # number of overall misses
< system.cpu0.icache.overall_misses::total 1878593 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17494191500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 17494191500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 17494191500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 17494191500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 17494191500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 17494191500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 36659870 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 36659870 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 36659870 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 36659870 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 36659870 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 36659870 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051244 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.051244 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051244 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.051244 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051244 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.051244 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9312.390443 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 9312.390443 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9312.390443 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 9312.390443 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9312.390443 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 9312.390443 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 75384087 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 75384087 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 34871642 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 34871642 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 34871642 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 34871642 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 34871642 # number of overall hits
> system.cpu0.icache.overall_hits::total 34871642 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1880268 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1880268 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1880268 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1880268 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1880268 # number of overall misses
> system.cpu0.icache.overall_misses::total 1880268 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17494991000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 17494991000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 17494991000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 17494991000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 17494991000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 17494991000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 36751910 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 36751910 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 36751910 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 36751910 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 36751910 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 36751910 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051161 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.051161 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051161 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.051161 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051161 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.051161 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9304.519888 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 9304.519888 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 9304.519888 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 9304.519888 # average overall miss latency
809,814c807,812
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1878593 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1878593 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1878593 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1878593 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1878593 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1878593 # number of overall MSHR misses
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1880268 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1880268 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1880268 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1880268 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1880268 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1880268 # number of overall MSHR misses
819,824c817,822
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16554895500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 16554895500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16554895500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 16554895500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16554895500 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 16554895500 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16554857500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 16554857500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16554857500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 16554857500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16554857500 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 16554857500 # number of overall MSHR miss cycles
829,840c827,838
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051244 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051244 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051244 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.051244 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051244 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.051244 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8812.390709 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8812.390709 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8812.390709 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 8812.390709 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8812.390709 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 8812.390709 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051161 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.051161 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.051161 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8804.520154 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 8804.520154 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 8804.520154 # average overall mshr miss latency
846,848c844,846
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1765882 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1765970 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 77 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1762988 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1763146 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 137 # number of redundant prefetches already in prefetch queue
851,856c849,854
< system.cpu0.l2cache.prefetcher.pfSpanPage 224118 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 286262 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16059.277635 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 4797112 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 302498 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 15.858326 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 223158 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 285163 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16064.441291 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 4801094 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 301400 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 15.929310 # Average number of references to valid blocks.
858,865c856,863
< system.cpu0.l2cache.tags.occ_blocks::writebacks 8723.236364 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 43.341002 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.066911 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4602.822845 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1559.466000 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1130.344513 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.532424 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002645 # Average percentage of cache occupancy
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 8613.892017 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 45.679204 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.072727 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4663.239886 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1620.721287 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1120.836170 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.525750 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002788 # Average percentage of cache occupancy
867,873c865,871
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.280934 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.095182 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068991 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.980181 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1044 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15177 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.284622 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.098921 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068410 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.980496 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15199 # Occupied blocks per task id
875,877c873,875
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 332 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 429 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 270 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 305 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 401 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 310 # Occupied blocks per task id
879,881c877,879
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
883,922c881,920
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4328 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7768 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2750 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063721 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.926331 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 85339399 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 85339399 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80048 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4433 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 84481 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 493290 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 493290 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28251 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 28251 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1773 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 1773 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213027 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 213027 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1814336 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 1814336 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376020 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 376020 # number of ReadSharedReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80048 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4433 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1814336 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 589047 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 2487864 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80048 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4433 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1814336 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 589047 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 2487864 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 723 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 114 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 837 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27851 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 27851 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19535 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19535 # number of SCUpgradeReq misses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4239 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7941 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2698 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927673 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 85389688 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 85389688 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78899 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4233 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 83132 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 493050 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 493050 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28200 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 28200 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1701 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 1701 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212815 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 212815 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1816263 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 1816263 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 377267 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 377267 # number of ReadSharedReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 78899 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4233 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1816263 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 590082 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 2489477 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 78899 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4233 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1816263 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 590082 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 2489477 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 767 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 105 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 872 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27843 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 27843 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19534 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 19534 # number of SCUpgradeReq misses
925,974c923,972
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43989 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 43989 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 64257 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 64257 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101397 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 101397 # number of ReadSharedReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 723 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 114 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 64257 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 145386 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 210480 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 723 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 114 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 64257 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 145386 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 210480 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 24794500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2781500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 27576000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 513504000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 513504000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 395434500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 395434500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 385999 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 385999 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2149567499 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2149567499 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2872366000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2872366000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2916301996 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2916301996 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 24794500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2781500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2872366000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 5065869495 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 7965811495 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 24794500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2781500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2872366000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 5065869495 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 7965811495 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 80771 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4547 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 85318 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 493290 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 493290 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56102 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 56102 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21308 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 21308 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44100 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 44100 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 64005 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 64005 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101018 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 101018 # number of ReadSharedReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 767 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 105 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 64005 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 145118 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 209995 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 767 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 105 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 64005 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 145118 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 209995 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 26175500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2558000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 28733500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 514961000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 514961000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 395123500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 395123500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 417500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 417500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2206381000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 2206381000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2858183000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2858183000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2907472497 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2907472497 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 26175500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2558000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2858183000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 5113853497 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 8000769997 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 26175500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2558000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2858183000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 5113853497 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 8000769997 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 79666 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4338 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 84004 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 493050 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 493050 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56043 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 56043 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21235 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 21235 # number of SCUpgradeReq accesses(hits+misses)
977,999c975,997
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257016 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 257016 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1878593 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 1878593 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477417 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 477417 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 80771 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4547 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1878593 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 734433 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 2698344 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 80771 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4547 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1878593 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 734433 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 2698344 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008951 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025071 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.009810 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.496435 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.496435 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.916792 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.916792 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256915 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 256915 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1880268 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 1880268 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 478285 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 478285 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 79666 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4338 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1880268 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 735200 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 2699472 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 79666 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4338 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1880268 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 735200 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 2699472 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009628 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.024205 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.010380 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.496815 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.496815 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.919896 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.919896 # miss rate for SCUpgradeReq accesses
1002,1043c1000,1041
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171153 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171153 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034205 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034205 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212387 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212387 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008951 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025071 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034205 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197957 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.078003 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008951 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025071 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034205 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197957 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.078003 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34293.914246 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24399.122807 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32946.236559 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18437.542638 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18437.542638 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20242.359867 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20242.359867 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 385999 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 385999 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48866.023301 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48866.023301 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44701.215432 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44701.215432 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28761.225638 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28761.225638 # average ReadSharedReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34293.914246 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24399.122807 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44701.215432 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34844.273142 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 37845.930706 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34293.914246 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24399.122807 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44701.215432 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34844.273142 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 37845.930706 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 68 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171652 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171652 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034040 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034040 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211209 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211209 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009628 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.024205 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034040 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197386 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.077791 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009628 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.024205 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034040 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197386 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.077791 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34127.118644 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24361.904762 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32951.261468 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18495.169342 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18495.169342 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20227.475171 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20227.475171 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 417500 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 417500 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50031.315193 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50031.315193 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44655.620655 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44655.620655 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28781.726989 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28781.726989 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34127.118644 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24361.904762 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44655.620655 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35239.277671 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 38099.811886 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34127.118644 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24361.904762 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44655.620655 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35239.277671 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 38099.811886 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 60 # number of cycles access was blocked
1047c1045
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
1051,1075c1049,1073
< system.cpu0.l2cache.writebacks::writebacks 196466 # number of writebacks
< system.cpu0.l2cache.writebacks::total 196466 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2877 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 2877 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 67 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 67 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 395 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 395 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 67 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3272 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 3339 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 67 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3272 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 3339 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 723 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 114 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 9399 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::total 9399 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 235023 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 235023 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27851 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27851 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19535 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19535 # number of SCUpgradeReq MSHR misses
---
> system.cpu0.l2cache.writebacks::writebacks 195910 # number of writebacks
> system.cpu0.l2cache.writebacks::total 195910 # number of writebacks
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2609 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 2609 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 70 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 70 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 363 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 363 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 70 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 2972 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 3042 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 70 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 2972 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 3042 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 767 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 105 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 872 # number of ReadReq MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 9288 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::total 9288 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 233934 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 233934 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27843 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27843 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19534 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19534 # number of SCUpgradeReq MSHR misses
1078,1094c1076,1092
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41112 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 41112 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 64190 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 64190 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101002 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101002 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 723 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 114 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 64190 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142114 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 207141 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 723 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 114 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 64190 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142114 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 235023 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 442164 # number of overall MSHR misses
---
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41491 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 41491 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 63935 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 63935 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100655 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100655 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 767 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 105 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 63935 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142146 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 206953 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 767 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 105 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 63935 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142146 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 233934 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 440887 # number of overall MSHR misses
1096,1099c1094,1097
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 18002 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 21428 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16758 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16758 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 21427 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16756 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16756 # number of WriteReq MSHR uncacheable
1101,1130c1099,1128
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34760 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 38186 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20456500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2097500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 22554000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14138051507 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14138051507 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 556929500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 556929500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 298503500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 298503500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 325999 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 325999 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1579585500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1579585500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2485678500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2485678500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2287922496 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2287922496 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 20456500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2097500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2485678500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3867507996 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 6375740496 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 20456500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2097500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2485678500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3867507996 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14138051507 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 20513792003 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34757 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 38183 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 21573500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1928000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 23501500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13851204796 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13851204796 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 554776500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 554776500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 298118500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 298118500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 351500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 351500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1669946000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1669946000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2472260000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2472260000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2283319997 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2283319997 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 21573500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1928000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2472260000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3953265997 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 6449027497 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 21573500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1928000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2472260000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3953265997 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13851204796 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 20300232293 # number of overall MSHR miss cycles
1132,1135c1130,1133
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3607450000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3894320500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2599707500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2599707500 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3607256500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3894127000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2599622000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2599622000 # number of WriteReq MSHR uncacheable cycles
1137,1141c1135,1139
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6207157500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6494028000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009810 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6206878500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6493749000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010380 # mshr miss rate for ReadReq accesses
1146,1149c1144,1147
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.496435 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.496435 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.916792 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916792 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.496815 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.496815 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.919896 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.919896 # mshr miss rate for SCUpgradeReq accesses
1152,1166c1150,1164
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159959 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159959 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034169 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211559 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211559 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193502 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076766 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193502 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.161497 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.161497 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034003 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.210450 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.210450 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193343 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076664 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193343 # mshr miss rate for overall accesses
1168,1196c1166,1194
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163865 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26946.236559 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60156.033695 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19996.750566 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19996.750566 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15280.445354 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15280.445354 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 325999 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 325999 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38421.519264 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38421.519264 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38723.765384 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22652.249421 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22652.249421 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27214.123844 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30779.712833 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27214.123844 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46394.080031 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163323 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26951.261468 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59209.883112 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19925.169702 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19925.169702 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15261.518378 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15261.518378 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 351500 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 351500 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40248.391217 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40248.391217 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38668.335028 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22684.615737 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22684.615737 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27811.306664 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31161.797592 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27811.306664 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46044.070914 # average overall mshr miss latency
1198,1201c1196,1199
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200391.623153 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.803061 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155132.324860 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155132.324860 # average WriteReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200392.006000 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.254212 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155145.738840 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155145.738840 # average WriteReq mshr uncacheable latency
1203,1204c1201,1202
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178571.849827 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170063.059760 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178579.235837 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170069.114527 # average overall mshr uncacheable latency
1206,1221c1204,1219
< system.cpu0.toL2Bus.trans_dist::ReadReq 136409 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 2524037 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 16758 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 866064 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 2177189 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 293784 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 92828 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43742 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 114509 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 285377 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 271332 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1878593 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603707 # Transaction distribution
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 136175 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 2526619 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 16756 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 865136 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 2178805 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 280675 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 92865 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43660 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 114593 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 285252 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 271172 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1880268 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604912 # Transaction distribution
1223,1236c1221,1234
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5608538 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2465365 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11948 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 171096 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 8256947 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120449152 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82718835 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18188 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 323084 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 203509259 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 1215113 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 6486372 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 1.185022 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.388316 # Request fanout histogram
---
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5613549 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2467613 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11765 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 169746 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 8262673 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120556352 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82765674 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17352 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 318664 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 203658042 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 1202366 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 6476462 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 1.183069 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.386723 # Request fanout histogram
1239,1240c1237,1238
< system.cpu0.toL2Bus.snoop_fanout::1 5286248 81.50% 81.50% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 1200124 18.50% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::1 5290820 81.69% 81.69% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 1185642 18.31% 100.00% # Request fanout histogram
1244,1245c1242,1243
< system.cpu0.toL2Bus.snoop_fanout::total 6486372 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 3193659992 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 6476462 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 3195593995 # Layer occupancy (ticks)
1247c1245
< system.cpu0.toL2Bus.snoopLayer0.occupancy 113350499 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 113765999 # Layer occupancy (ticks)
1249c1247
< system.cpu0.toL2Bus.respLayer0.occupancy 2823287977 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 2825774529 # Layer occupancy (ticks)
1251c1249
< system.cpu0.toL2Bus.respLayer1.occupancy 1167322846 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1168364927 # Layer occupancy (ticks)
1253c1251
< system.cpu0.toL2Bus.respLayer2.occupancy 7403495 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 7430992 # Layer occupancy (ticks)
1255c1253
< system.cpu0.toL2Bus.respLayer3.occupancy 90327994 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 90084491 # Layer occupancy (ticks)
1257,1261c1255,1259
< system.cpu1.branchPred.lookups 20515510 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 7101066 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 968769 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 10637682 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 7757881 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 20439224 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 7037667 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 906738 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 10483361 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 7695105 # Number of BTB hits
1263,1265c1261,1263
< system.cpu1.branchPred.BTBHitPct 72.928303 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 8827818 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 689615 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 73.403034 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 8822837 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 629691 # Number of incorrect RAS predictions.
1295,1321c1293,1317
< system.cpu1.dtb.walker.walks 30617 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 30617 # Table walker walks initiated with short descriptors
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22895 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7722 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walkWaitTime::samples 30617 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 30617 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 30617 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 2694 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 10773.014105 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 9833.978032 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 6170.794386 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-8191 858 31.85% 31.85% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1697 62.99% 94.84% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-24575 63 2.34% 97.18% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::24576-32767 63 2.34% 99.52% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::40960-49151 7 0.26% 99.78% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.81% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.15% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 2694 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 1565807264 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 1565807264 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 1565807264 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 2001 74.28% 74.28% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 693 25.72% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 2694 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30617 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walks 30282 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 30282 # Table walker walks initiated with short descriptors
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22625 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7657 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walkWaitTime::samples 30282 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 30282 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 30282 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 2657 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 10518.253670 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 9441.717442 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 7245.373074 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-16383 2512 94.54% 94.54% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 4.89% 99.44% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.26% 99.70% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::81920-98303 5 0.19% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::98304-114687 2 0.08% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 2657 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 1594102264 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 1594102264 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 1594102264 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 1972 74.22% 74.22% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 685 25.78% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 2657 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30282 # Table walker requests started/completed, data/inst
1323,1324c1319,1320
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30617 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2694 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30282 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2657 # Table walker requests started/completed, data/inst
1326,1327c1322,1323
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2694 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 33311 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2657 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 32939 # Table walker requests started/completed, data/inst
1330,1333c1326,1329
< system.cpu1.dtb.read_hits 12131046 # DTB read hits
< system.cpu1.dtb.read_misses 27925 # DTB read misses
< system.cpu1.dtb.write_hits 7724726 # DTB write hits
< system.cpu1.dtb.write_misses 2692 # DTB write misses
---
> system.cpu1.dtb.read_hits 12124185 # DTB read hits
> system.cpu1.dtb.read_misses 27903 # DTB read misses
> system.cpu1.dtb.write_hits 7716793 # DTB write hits
> system.cpu1.dtb.write_misses 2379 # DTB write misses
1338,1340c1334,1336
< system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 531 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 2053 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 374 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 549 # Number of TLB faults due to prefetch
1342,1344c1338,1340
< system.cpu1.dtb.perms_faults 287 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 12158971 # DTB read accesses
< system.cpu1.dtb.write_accesses 7727418 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 291 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 12152088 # DTB read accesses
> system.cpu1.dtb.write_accesses 7719172 # DTB write accesses
1346,1348c1342,1344
< system.cpu1.dtb.hits 19855772 # DTB hits
< system.cpu1.dtb.misses 30617 # DTB misses
< system.cpu1.dtb.accesses 19886389 # DTB accesses
---
> system.cpu1.dtb.hits 19840978 # DTB hits
> system.cpu1.dtb.misses 30282 # DTB misses
> system.cpu1.dtb.accesses 19871260 # DTB accesses
1378,1379c1374,1375
< system.cpu1.itb.walker.walks 2297 # Table walker walks requested
< system.cpu1.itb.walker.walksShort 2297 # Table walker walks initiated with short descriptors
---
> system.cpu1.itb.walker.walks 2290 # Table walker walks requested
> system.cpu1.itb.walker.walksShort 2290 # Table walker walks initiated with short descriptors
1381,1401c1377,1399
< system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2115 # Level at which table walker walks with short descriptors terminate
< system.cpu1.itb.walker.walkWaitTime::samples 2297 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 2297 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 2297 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 10860.516934 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 10080.267537 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 5206.907244 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-8191 274 24.42% 24.42% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-16383 814 72.55% 96.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-24575 4 0.36% 97.33% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.41% 99.73% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::40960-49151 2 0.18% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 1565238764 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 1565238764 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 1565238764 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 953 84.94% 84.94% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::1M 169 15.06% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2108 # Level at which table walker walks with short descriptors terminate
> system.cpu1.itb.walker.walkWaitTime::samples 2290 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 2290 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 2290 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 10627.337489 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 9754.511529 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 5025.096618 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::4096-8191 329 29.30% 29.30% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-12287 526 46.84% 76.14% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::12288-16383 229 20.39% 96.53% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.71% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::24576-28671 14 1.25% 97.95% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.87% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 1593536764 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 1593536764 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 1593536764 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 954 84.95% 84.95% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::1M 169 15.05% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated
1403,1404c1401,1402
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2297 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2297 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2290 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2290 # Table walker requests started/completed, data/inst
1406,1410c1404,1408
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 3419 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 41950603 # ITB inst hits
< system.cpu1.itb.inst_misses 2297 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 3413 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 41919801 # ITB inst hits
> system.cpu1.itb.inst_misses 2290 # ITB inst misses
1419c1417
< system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB
1423c1421
< system.cpu1.itb.perms_faults 1848 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 1868 # Number of TLB faults due to permissions restrictions
1426,1430c1424,1428
< system.cpu1.itb.inst_accesses 41952900 # ITB inst accesses
< system.cpu1.itb.hits 41950603 # DTB hits
< system.cpu1.itb.misses 2297 # DTB misses
< system.cpu1.itb.accesses 41952900 # DTB accesses
< system.cpu1.numCycles 125141481 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 41922091 # ITB inst accesses
> system.cpu1.itb.hits 41919801 # DTB hits
> system.cpu1.itb.misses 2290 # DTB misses
> system.cpu1.itb.accesses 41922091 # DTB accesses
> system.cpu1.numCycles 125017818 # number of cpu cycles simulated
1433,1439c1431,1437
< system.cpu1.committedInsts 51908432 # Number of instructions committed
< system.cpu1.committedOps 63413187 # Number of ops (including micro ops) committed
< system.cpu1.discardedOps 5363692 # Number of ops (including micro ops) which were discarded before commit
< system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching
< system.cpu1.quiesceCycles 5566331294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.cpi 2.410812 # CPI: cycles per instruction
< system.cpu1.ipc 0.414798 # IPC: instructions per cycle
---
> system.cpu1.committedInsts 51886096 # Number of instructions committed
> system.cpu1.committedOps 63386159 # Number of ops (including micro ops) committed
> system.cpu1.discardedOps 5353179 # Number of ops (including micro ops) which were discarded before commit
> system.cpu1.numFetchSuspends 2738 # Number of times Execute suspended instruction fetching
> system.cpu1.quiesceCycles 5566469050 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.cpi 2.409467 # CPI: cycles per instruction
> system.cpu1.ipc 0.415030 # IPC: instructions per cycle
1441,1536c1439,1534
< system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed
< system.cpu1.tickCycles 105428618 # Number of cycles that the object actually ticked
< system.cpu1.idleCycles 19712863 # Total number of cycles that the object has spent stopped
< system.cpu1.dcache.tags.replacements 231919 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 484.812111 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 19337078 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 232252 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 83.259038 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 90437090000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.812111 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.946899 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.946899 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 333 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 279 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 54 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.650391 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 39720944 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 39720944 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 11670097 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 11670097 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 7386354 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 7386354 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66295 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 66295 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88787 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 88787 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80732 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 80732 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 19056451 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 19056451 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 19122746 # number of overall hits
< system.cpu1.dcache.overall_hits::total 19122746 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 184750 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 184750 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 167503 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 167503 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35001 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 35001 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17741 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 17741 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23478 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23478 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 352253 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 352253 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 387254 # number of overall misses
< system.cpu1.dcache.overall_misses::total 387254 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2719987000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2719987000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4150031500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 4150031500 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326839500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 326839500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548823500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 548823500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 416500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 416500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 6870018500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 6870018500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 6870018500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 6870018500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 11854847 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 11854847 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 7553857 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 7553857 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101296 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 101296 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106528 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 106528 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104210 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 104210 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 19408704 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 19408704 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 19510000 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 19510000 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015584 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.015584 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022174 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.022174 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.345532 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.345532 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166538 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166538 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225295 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225295 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018149 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.018149 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019849 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.019849 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14722.527740 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14722.527740 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24775.863716 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 24775.863716 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18422.834113 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18422.834113 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23376.075475 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23376.075475 # average StoreCondReq miss latency
---
> system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
> system.cpu1.tickCycles 105304281 # Number of cycles that the object actually ticked
> system.cpu1.idleCycles 19713537 # Total number of cycles that the object has spent stopped
> system.cpu1.dcache.tags.replacements 231375 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 483.037999 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 19321104 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 231701 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 83.388091 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 90467560500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.037999 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943434 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.943434 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 253 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 39693132 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 39693132 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 11664966 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 11664966 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 7379255 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 7379255 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66113 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 66113 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88582 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 88582 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80498 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 80498 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 19044221 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 19044221 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 19110334 # number of overall hits
> system.cpu1.dcache.overall_hits::total 19110334 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 184342 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 184342 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 167268 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 167268 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34982 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 34982 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17676 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 17676 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23450 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23450 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 351610 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 351610 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 386592 # number of overall misses
> system.cpu1.dcache.overall_misses::total 386592 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2719374500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2719374500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4153510500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 4153510500 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325753000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 325753000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548137000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 548137000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 684500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 684500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 6872885000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 6872885000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 6872885000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 6872885000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 11849308 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 11849308 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 7546523 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 7546523 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101095 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 101095 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106258 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 106258 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103948 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 103948 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 19395831 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 19395831 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 19496926 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 19496926 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015557 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.015557 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022165 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.022165 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.346031 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.346031 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166350 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166350 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225594 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225594 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018128 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.018128 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019828 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.019828 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14751.790151 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 14751.790151 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24831.471052 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 24831.471052 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18429.112921 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18429.112921 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23374.712154 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23374.712154 # average StoreCondReq miss latency
1539,1542c1537,1540
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19503.080172 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 19503.080172 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17740.342256 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 17740.342256 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19546.898552 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 19546.898552 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17778.135605 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17778.135605 # average overall miss latency
1551,1628c1549,1626
< system.cpu1.dcache.writebacks::writebacks 138789 # number of writebacks
< system.cpu1.dcache.writebacks::total 138789 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18309 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 18309 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62144 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 62144 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12262 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12262 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 80453 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 80453 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 80453 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 80453 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166441 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 166441 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105359 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 105359 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33489 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 33489 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5479 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5479 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23478 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23478 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 271800 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 271800 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 305289 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 305289 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17142 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17142 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14413 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14413 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31555 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31555 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2292018500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2292018500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2517101000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2517101000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 540422500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 540422500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93861500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93861500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 525354500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 525354500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 407500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 407500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4809119500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4809119500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5349542000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 5349542000 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2935336500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2935336500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2447202500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2447202500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5382539000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5382539000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014040 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014040 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013948 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013948 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.330605 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.330605 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051432 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051432 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225295 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225295 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014004 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.014004 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015648 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.015648 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.756604 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.756604 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23890.707011 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23890.707011 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16137.313745 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16137.313745 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17131.137069 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17131.137069 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22376.458813 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22376.458813 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 138377 # number of writebacks
> system.cpu1.dcache.writebacks::total 138377 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18221 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 18221 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62038 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 62038 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12225 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12225 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 80259 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 80259 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 80259 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 80259 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166121 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 166121 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105230 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 105230 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33463 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 33463 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5451 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5451 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23450 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23450 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 271351 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 271351 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 304814 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 304814 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17128 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17128 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14405 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14405 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31533 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31533 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2295109000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2295109000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2517034000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2517034000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 544638000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 544638000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 92810500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 92810500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524700000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524700000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 671500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 671500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4812143000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4812143000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5356781000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 5356781000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2934873000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2934873000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2446602500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2446602500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5381475500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5381475500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014019 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014019 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013944 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013944 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331005 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331005 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051300 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051300 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225594 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225594 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013990 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.013990 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015634 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.015634 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13815.887215 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13815.887215 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23919.357598 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23919.357598 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16275.827033 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16275.827033 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17026.325445 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17026.325445 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22375.266525 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22375.266525 # average StoreCondReq mshr miss latency
1631,1640c1629,1638
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17693.596394 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17693.596394 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17522.878322 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17522.878322 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171236.524326 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171236.524326 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169791.334212 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169791.334212 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170576.422120 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170576.422120 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17734.016090 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17734.016090 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17573.933612 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17573.933612 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171349.427837 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171349.427837 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169843.977785 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169843.977785 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170661.703612 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170661.703612 # average overall mshr uncacheable latency
1642,1650c1640,1648
< system.cpu1.icache.tags.replacements 1046573 # number of replacements
< system.cpu1.icache.tags.tagsinuse 499.334165 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 40901496 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 1047085 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 39.062250 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 72079197500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.334165 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975262 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.975262 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 1042125 # number of replacements
> system.cpu1.icache.tags.tagsinuse 499.329120 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 40875126 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 1042637 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 39.203602 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 72106351500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.329120 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975252 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.975252 # Average percentage of cache occupancy
1655,1692c1653,1690
< system.cpu1.icache.tags.tag_accesses 84944247 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 84944247 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 40901496 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 40901496 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 40901496 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 40901496 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 40901496 # number of overall hits
< system.cpu1.icache.overall_hits::total 40901496 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 1047085 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 1047085 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 1047085 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 1047085 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 1047085 # number of overall misses
< system.cpu1.icache.overall_misses::total 1047085 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9273780500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 9273780500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 9273780500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 9273780500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 9273780500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 9273780500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 41948581 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 41948581 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 41948581 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 41948581 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 41948581 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 41948581 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024961 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024961 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024961 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8856.759957 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 8856.759957 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8856.759957 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 8856.759957 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8856.759957 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 8856.759957 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 84878163 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 84878163 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 40875126 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 40875126 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 40875126 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 40875126 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 40875126 # number of overall hits
> system.cpu1.icache.overall_hits::total 40875126 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 1042637 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 1042637 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 1042637 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 1042637 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 1042637 # number of overall misses
> system.cpu1.icache.overall_misses::total 1042637 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9237616500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 9237616500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 9237616500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 9237616500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 9237616500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 9237616500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 41917763 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 41917763 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 41917763 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 41917763 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 41917763 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 41917763 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024873 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.024873 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024873 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.024873 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024873 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.024873 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8859.858704 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 8859.858704 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8859.858704 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 8859.858704 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8859.858704 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 8859.858704 # average overall miss latency
1701,1706c1699,1704
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1047085 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 1047085 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 1047085 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 1047085 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 1047085 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 1047085 # number of overall MSHR misses
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1042637 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 1042637 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 1042637 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 1042637 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 1042637 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 1042637 # number of overall MSHR misses
1711,1736c1709,1734
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8750238000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 8750238000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8750238000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 8750238000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8750238000 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 8750238000 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10154500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10154500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10154500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 10154500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024961 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024961 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024961 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.024961 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024961 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.024961 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8356.759957 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8356.759957 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8356.759957 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8356.759957 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8356.759957 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8356.759957 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89862.831858 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89862.831858 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89862.831858 # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8716298000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 8716298000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8716298000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 8716298000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8716298000 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 8716298000 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10126000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10126000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10126000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 10126000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024873 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.024873 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.024873 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8359.858704 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8359.858704 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8359.858704 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89610.619469 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89610.619469 # average overall mshr uncacheable latency
1738,1740c1736,1738
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 270311 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 270335 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 270674 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 270706 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue
1743,1748c1741,1746
< system.cpu1.l2cache.prefetcher.pfSpanPage 70297 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 69395 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15632.228782 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 2434679 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 84293 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 28.883525 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 70190 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 69559 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15624.003278 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 2421583 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 84278 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 28.733276 # Average number of references to valid blocks.
1750,1768c1748,1766
< system.cpu1.l2cache.tags.occ_blocks::writebacks 6105.214353 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.591846 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.935526 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5648.623425 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2320.323151 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1496.540481 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.372633 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003698 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000057 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.344765 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.141621 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.091342 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.954116 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1218 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13618 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 684 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 526 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 6091.947681 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 59.671167 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.103493 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5612.930096 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2321.677903 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1537.672938 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.371823 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003642 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.342586 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.141704 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093852 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.953613 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1225 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13444 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 697 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 522 # Occupied blocks per task id
1770,1805c1768,1803
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 28 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6069 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7234 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074341 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.831177 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 43042452 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 43042452 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33942 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2703 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 36645 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 138788 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 138788 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2017 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 2017 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1035 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 1035 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37928 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 37928 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1019439 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 1019439 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 131721 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 131721 # number of ReadSharedReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 33942 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2703 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 1019439 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 169649 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 1225733 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 33942 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2703 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 1019439 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 169649 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 1225733 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 703 # number of ReadReq misses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5775 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7342 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074768 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.820557 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 42869923 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 42869923 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33040 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2583 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 35623 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 138377 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 138377 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2042 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 2042 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1012 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 1012 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37732 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 37732 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1015029 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 1015029 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 131048 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 131048 # number of ReadSharedReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 33040 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2583 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 1015029 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 168780 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 1219432 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 33040 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2583 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 1015029 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 168780 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 1219432 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 727 # number of ReadReq misses
1807,1818c1805,1818
< system.cpu1.l2cache.ReadReq_misses::total 924 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29293 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29293 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22443 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22443 # number of SCUpgradeReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36124 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 36124 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 27646 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 27646 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73685 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 73685 # number of ReadSharedReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 703 # number of demand (read+write) misses
---
> system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29373 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 29373 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22436 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22436 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36088 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 36088 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 27608 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 27608 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73984 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 73984 # number of ReadSharedReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 727 # number of demand (read+write) misses
1820,1823c1820,1823
< system.cpu1.l2cache.demand_misses::cpu1.inst 27646 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 109809 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 138379 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 703 # number of overall misses
---
> system.cpu1.l2cache.demand_misses::cpu1.inst 27608 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 110072 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 138628 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 727 # number of overall misses
1825,1926c1825,1930
< system.cpu1.l2cache.overall_misses::cpu1.inst 27646 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 109809 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 138379 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17833500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4520500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 22354000 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 553092500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 553092500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 450276000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 450276000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 393500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 393500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1418705500 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1418705500 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1071948000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1071948000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1752324498 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1752324498 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17833500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4520500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1071948000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 3171029998 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 4265331998 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17833500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4520500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1071948000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 3171029998 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 4265331998 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 34645 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2924 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 37569 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 138788 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 138788 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31310 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 31310 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23478 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23478 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74052 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 74052 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1047085 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 1047085 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 205406 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 205406 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 34645 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2924 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 1047085 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 279458 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 1364112 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 34645 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2924 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 1047085 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 279458 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 1364112 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020292 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.075581 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.024595 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.935580 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.935580 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955916 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955916 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.487819 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.487819 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026403 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026403 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.358729 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.358729 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020292 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.075581 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026403 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.392936 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.101443 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020292 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.075581 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026403 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.392936 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.101443 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25367.709815 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20454.751131 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24192.640693 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18881.388045 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18881.388045 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20063.093169 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20063.093169 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39273.211715 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39273.211715 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38774.072199 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38774.072199 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23781.291959 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23781.291959 # average ReadSharedReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25367.709815 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20454.751131 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38774.072199 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28877.687603 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 30823.549802 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25367.709815 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20454.751131 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38774.072199 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28877.687603 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 30823.549802 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
---
> system.cpu1.l2cache.overall_misses::cpu1.inst 27608 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 110072 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 138628 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 18603000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4457500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 23060500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 554124000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 554124000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449909000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449909000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 652000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 652000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1418232500 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1418232500 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1071283000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1071283000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1763586495 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1763586495 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 18603000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4457500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1071283000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 3181818995 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 4276162495 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 18603000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4457500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1071283000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 3181818995 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 4276162495 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33767 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2804 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 36571 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 138377 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 138377 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31415 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 31415 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23448 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23448 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73820 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 73820 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1042637 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 1042637 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 205032 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 205032 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33767 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2804 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 1042637 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 278852 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 1358060 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33767 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2804 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 1042637 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 278852 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 1358060 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021530 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.078816 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.025922 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.934999 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.934999 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.956841 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.956841 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.488865 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.488865 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026479 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026479 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.360841 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.360841 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021530 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.078816 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026479 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.394733 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.102078 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021530 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.078816 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026479 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.394733 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.102078 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25588.720770 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.683258 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24325.421941 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18865.080176 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18865.080176 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20052.995186 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20052.995186 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 326000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 326000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39299.282310 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39299.282310 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38803.354100 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38803.354100 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23837.403966 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23837.403966 # average ReadSharedReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25588.720770 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.683258 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38803.354100 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28906.706474 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 30846.311676 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25588.720770 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.683258 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38803.354100 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28906.706474 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 30846.311676 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1928c1932
< system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1930c1934
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1934,1948c1938,1952
< system.cpu1.l2cache.writebacks::writebacks 36782 # number of writebacks
< system.cpu1.l2cache.writebacks::total 36782 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 330 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 330 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 21 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 21 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 131 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 131 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 21 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 461 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 482 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 21 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 461 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 482 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 703 # number of ReadReq MSHR misses
---
> system.cpu1.l2cache.writebacks::writebacks 36799 # number of writebacks
> system.cpu1.l2cache.writebacks::total 36799 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 302 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 302 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 26 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 134 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 134 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 26 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 436 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 462 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 26 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 436 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 462 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 727 # number of ReadReq MSHR misses
1950,1965c1954,1971
< system.cpu1.l2cache.ReadReq_mshr_misses::total 924 # number of ReadReq MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3084 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::total 3084 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35155 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 35155 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29293 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29293 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22443 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22443 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35794 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 35794 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 27625 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 27625 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73554 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73554 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 703 # number of demand (read+write) MSHR misses
---
> system.cpu1.l2cache.ReadReq_mshr_misses::total 948 # number of ReadReq MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3205 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::total 3205 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35196 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 35196 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29373 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29373 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22436 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22436 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35786 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 35786 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 27582 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 27582 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73850 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73850 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 727 # number of demand (read+write) MSHR misses
1967,1970c1973,1976
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27625 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109348 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 137897 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 703 # number of overall MSHR misses
---
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27582 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109636 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 138166 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 727 # number of overall MSHR misses
1972,1975c1978,1981
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27625 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109348 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35155 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 173052 # number of overall MSHR misses
---
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27582 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109636 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35196 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 173362 # number of overall MSHR misses
1977,1980c1983,1986
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17142 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17255 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14413 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14413 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17128 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17241 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14405 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14405 # number of WriteReq MSHR uncacheable
1982,2022c1988,2028
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31555 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31668 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13615500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3194500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 16810000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1287870547 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1287870547 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 501412999 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 501412999 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348285500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348285500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 339500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 339500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1165172000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1165172000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 905573000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 905573000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1306537498 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1306537498 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13615500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3194500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 905573000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2471709498 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 3394092498 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13615500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3194500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 905573000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2471709498 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1287870547 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 4681963045 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9250500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2798164000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2807414500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2338978500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2338978500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9250500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5137142500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5146393000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.024595 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31533 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31646 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3131500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 17372500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1238467331 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1238467331 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 502709499 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 502709499 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348029000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348029000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 574000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 574000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1167759000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1167759000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 904893000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 904893000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1316095995 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1316095995 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3131500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 904893000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2483854995 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 3406120495 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3131500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 904893000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2483854995 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1238467331 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 4644587826 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9222000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2797805500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2807027500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2338455000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2338455000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9222000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5136260500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5145482500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025922 # mshr miss rate for ReadReq accesses
2027,2045c2033,2053
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.935580 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.935580 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955916 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955916 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.483363 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.483363 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026383 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.358091 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.358091 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391286 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101089 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391286 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.934999 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.934999 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.956841 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.956841 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.484774 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.484774 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026454 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.360188 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.360188 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393169 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101738 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393169 # mshr miss rate for overall accesses
2047,2083c2055,2091
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.126861 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18192.640693 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36634.064770 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17117.161062 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17117.161062 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15518.669518 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15518.669518 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32552.159580 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32552.159580 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32780.923077 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17762.970036 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17762.970036 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22604.066814 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24613.243928 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22604.066814 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27055.237992 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163234.395053 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162701.506810 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162282.557413 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162282.557413 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162799.635557 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162510.831123 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127654 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18325.421941 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35187.729600 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17114.680114 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17114.680114 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15512.078802 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15512.078802 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 287000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 287000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32631.727491 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32631.727491 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32807.374375 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17821.205078 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17821.205078 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22655.468961 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24652.378262 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22655.468961 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26791.268133 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163346.888136 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162811.176846 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162336.341548 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162336.341548 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162885.247201 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162595.035708 # average overall mshr uncacheable latency
2085,2100c2093,2108
< system.cpu1.toL2Bus.trans_dist::ReadReq 81434 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 1353329 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 14413 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 511562 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 1270278 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 44724 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 77037 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43004 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 89317 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 97290 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 79982 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1047085 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 561570 # Transaction distribution
---
> system.cpu1.toL2Bus.trans_dist::ReadReq 81005 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 1348099 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 14405 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 510462 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 1265020 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 43516 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 77320 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42972 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 89288 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 97251 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 79776 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1042637 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 559861 # Transaction distribution
2102,2115c2110,2123
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3121460 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1041902 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7336 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 72984 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 4243682 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67020672 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29874703 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11696 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 138580 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 97045651 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 1176077 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 3823827 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 1.296126 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.456547 # Request fanout histogram
---
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3108261 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1040223 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7202 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71706 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 4227392 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66736000 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29812791 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11216 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135068 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 96695075 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 1172897 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 3809713 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 1.296141 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.456554 # Request fanout histogram
2118,2119c2126,2127
< system.cpu1.toL2Bus.snoop_fanout::1 2691491 70.39% 70.39% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 1132336 29.61% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::1 2681500 70.39% 70.39% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 1128213 29.61% 100.00% # Request fanout histogram
2123,2124c2131,2132
< system.cpu1.toL2Bus.snoop_fanout::total 3823827 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 1513117496 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 3809713 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 1507501992 # Layer occupancy (ticks)
2126c2134
< system.cpu1.toL2Bus.snoopLayer0.occupancy 87426499 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 87443999 # Layer occupancy (ticks)
2128c2136
< system.cpu1.toL2Bus.respLayer0.occupancy 1570862868 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 1564193862 # Layer occupancy (ticks)
2130c2138
< system.cpu1.toL2Bus.respLayer1.occupancy 471839695 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 470956198 # Layer occupancy (ticks)
2132c2140
< system.cpu1.toL2Bus.respLayer2.occupancy 4412000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 4398499 # Layer occupancy (ticks)
2134c2142
< system.cpu1.toL2Bus.respLayer3.occupancy 38355467 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 37948980 # Layer occupancy (ticks)
2136,2137c2144,2145
< system.iobus.trans_dist::ReadReq 31014 # Transaction distribution
< system.iobus.trans_dist::ReadResp 31014 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 31013 # Transaction distribution
> system.iobus.trans_dist::ReadResp 31013 # Transaction distribution
2145c2153
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes)
2161c2169
< system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes)
2164c2172
< system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
2170c2178
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes)
2186c2194
< system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes)
2189c2197
< system.iobus.pkt_size::total 2484074 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size::total 2484073 # Cumulative packet size per connected master and slave (bytes)
2200c2208
< system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks)
2230c2238
< system.iobus.reqLayer27.occupancy 187550442 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 187545199 # Layer occupancy (ticks)
2234c2242
< system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks)
2238,2239c2246,2247
< system.iocache.tags.replacements 36446 # number of replacements
< system.iocache.tags.tagsinuse 14.479147 # Cycle average of tags in use
---
> system.iocache.tags.replacements 36462 # number of replacements
> system.iocache.tags.tagsinuse 14.479963 # Cycle average of tags in use
2241c2249
< system.iocache.tags.sampled_refs 36462 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks.
2243,2246c2251,2254
< system.iocache.tags.warmup_cycle 270355599000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.479147 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.904947 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.904947 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 270370198000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.479963 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.904998 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.904998 # Average percentage of cache occupancy
2260,2267c2268,2275
< system.iocache.ReadReq_miss_latency::realview.ide 32686877 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 32686877 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4278417565 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4278417565 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 32686877 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 32686877 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 32686877 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 32686877 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 32688877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 32688877 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4277206322 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4277206322 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 32688877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 32688877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 32688877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 32688877 # number of overall miss cycles
2284,2291c2292,2299
< system.iocache.ReadReq_avg_miss_latency::realview.ide 127683.113281 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 127683.113281 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118110.025536 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118110.025536 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 127683.113281 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 127683.113281 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 127683.113281 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 127683.113281 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 127690.925781 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 127690.925781 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118076.587953 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 118076.587953 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 127690.925781 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 127690.925781 # average overall miss latency
2294c2302
< system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
2296c2304
< system.iocache.avg_blocked_cycles::no_mshrs 5.250000 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked
2300,2301c2308,2309
< system.iocache.writebacks::writebacks 36190 # number of writebacks
< system.iocache.writebacks::total 36190 # number of writebacks
---
> system.iocache.writebacks::writebacks 36206 # number of writebacks
> system.iocache.writebacks::total 36206 # number of writebacks
2310,2317c2318,2325
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 19886877 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 19886877 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2467217565 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2467217565 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 19886877 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 19886877 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 19886877 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 19886877 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 19888877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 19888877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466006322 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2466006322 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 19888877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 19888877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 19888877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 19888877 # number of overall MSHR miss cycles
2326,2333c2334,2341
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77683.113281 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 77683.113281 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68110.025536 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68110.025536 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 77683.113281 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 77683.113281 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 77683.113281 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 77683.113281 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77690.925781 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 77690.925781 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68076.587953 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68076.587953 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency
2335,2339c2343,2347
< system.l2c.tags.replacements 135320 # number of replacements
< system.l2c.tags.tagsinuse 64080.552826 # Cycle average of tags in use
< system.l2c.tags.total_refs 445963 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 199765 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.232438 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 134724 # number of replacements
> system.l2c.tags.tagsinuse 64068.233504 # Cycle average of tags in use
> system.l2c.tags.total_refs 443602 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 199053 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.228562 # Average number of references to valid blocks.
2341,2434c2349,2441
< system.l2c.tags.occ_blocks::writebacks 12788.353662 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.367527 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034390 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 7205.553479 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 2096.784928 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32107.700654 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 26.808299 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851993 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 4024.713832 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 1527.951308 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4232.432754 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.195135 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001058 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.109948 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.031994 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.489925 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000409 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.061412 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.023315 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064582 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.977792 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 29238 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 35135 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 5585 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 23534 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 72 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 3030 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 31767 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.446136 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.536118 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 5845545 # Number of tag accesses
< system.l2c.tags.data_accesses 5845545 # Number of data accesses
< system.l2c.Writeback_hits::writebacks 233248 # number of Writeback hits
< system.l2c.Writeback_hits::total 233248 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 3007 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 942 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 3949 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 254 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 81 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 4095 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 2177 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 6272 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 343 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 65 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 44646 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 47683 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46675 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 154 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 31 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 21738 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 11221 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8044 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 180600 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 343 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 65 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 44646 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 51778 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 46675 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 154 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 31 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 21738 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 13398 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 8044 # number of demand (read+write) hits
< system.l2c.demand_hits::total 186872 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 343 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 65 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 44646 # number of overall hits
< system.l2c.overall_hits::cpu0.data 51778 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 46675 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 154 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 31 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 21738 # number of overall hits
< system.l2c.overall_hits::cpu1.data 13398 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 8044 # number of overall hits
< system.l2c.overall_hits::total 186872 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 8773 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 4095 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 12868 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 811 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1218 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 2029 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 10812 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 8416 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 19228 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 116 # number of ReadSharedReq misses
---
> system.l2c.tags.occ_blocks::writebacks 12835.902941 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.531822 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.025215 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 7257.127456 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 2101.817094 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32009.024605 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 30.126345 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 4045.876721 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 1535.093827 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4184.707478 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.195860 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001046 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.110735 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.032071 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.488419 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000460 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.061735 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.023424 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.063854 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.977604 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 29296 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 34966 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 113 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 5383 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 23800 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 313 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 2923 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 31711 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.447021 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.533539 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 5827626 # Number of tag accesses
> system.l2c.tags.data_accesses 5827626 # Number of data accesses
> system.l2c.Writeback_hits::writebacks 232709 # number of Writeback hits
> system.l2c.Writeback_hits::total 232709 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 3025 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 939 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 3964 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 83 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 340 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 4055 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 2183 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 6238 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 387 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 52 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 44381 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 47292 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46189 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 171 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 33 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 21681 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 11241 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8230 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 179657 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 387 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 52 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 44381 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 51347 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 46189 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 171 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 21681 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 13424 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 8230 # number of demand (read+write) hits
> system.l2c.demand_hits::total 185895 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 387 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 52 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 44381 # number of overall hits
> system.l2c.overall_hits::cpu0.data 51347 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 46189 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 171 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 21681 # number of overall hits
> system.l2c.overall_hits::cpu1.data 13424 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 8230 # number of overall hits
> system.l2c.overall_hits::total 185895 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 8753 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 4074 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 12827 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 797 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1213 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 2010 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 10969 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 8454 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 19423 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 121 # number of ReadSharedReq misses
2436,2445c2443,2451
< system.l2c.ReadSharedReq_misses::cpu0.inst 19540 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 8519 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 129160 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 40 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 5871 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 2660 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 9190 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 175098 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 116 # number of demand (read+write) misses
---
> system.l2c.ReadSharedReq_misses::cpu0.inst 19546 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 8542 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 128715 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 43 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 5890 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 2696 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8977 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 174531 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 121 # number of demand (read+write) misses
2447,2456c2453,2461
< system.l2c.demand_misses::cpu0.inst 19540 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 19331 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 129160 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 40 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 5871 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 11076 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 9190 # number of demand (read+write) misses
< system.l2c.demand_misses::total 194326 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 116 # number of overall misses
---
> system.l2c.demand_misses::cpu0.inst 19546 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 19511 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 128715 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 43 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 5890 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 11150 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 8977 # number of demand (read+write) misses
> system.l2c.demand_misses::total 193954 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 121 # number of overall misses
2458,2476c2463,2480
< system.l2c.overall_misses::cpu0.inst 19540 # number of overall misses
< system.l2c.overall_misses::cpu0.data 19331 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 129160 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 40 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 5871 # number of overall misses
< system.l2c.overall_misses::cpu1.data 11076 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 9190 # number of overall misses
< system.l2c.overall_misses::total 194326 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 9401500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 5084500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 14486000 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1177000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1665000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 2842000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 989600500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 687604500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 1677205000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10015500 # number of ReadSharedReq miss cycles
---
> system.l2c.overall_misses::cpu0.inst 19546 # number of overall misses
> system.l2c.overall_misses::cpu0.data 19511 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 128715 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 43 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 5890 # number of overall misses
> system.l2c.overall_misses::cpu1.data 11150 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 8977 # number of overall misses
> system.l2c.overall_misses::total 193954 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 9167000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 5104000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 14271000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1330000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1451500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 2781500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1087997000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 696148000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 1784145000 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10392000 # number of ReadSharedReq miss cycles
2478,2487c2482,2490
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1567254000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 747042500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13330410791 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3705500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 82500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 483609000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 234711500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1119629067 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 17496763358 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 10015500 # number of demand (read+write) miss cycles
---
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1558395000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 749223000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13067901493 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3962000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 483846500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 240245000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1069849511 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 17184117504 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 10392000 # number of demand (read+write) miss cycles
2489,2498c2492,2500
< system.l2c.demand_miss_latency::cpu0.inst 1567254000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 1736643000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13330410791 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 3705500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 82500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 483609000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 922316000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1119629067 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 19173968358 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 10015500 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 1558395000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 1837220000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13067901493 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 3962000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 483846500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 936393000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1069849511 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 18968262504 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 10392000 # number of overall miss cycles
2500,2604c2502,2602
< system.l2c.overall_miss_latency::cpu0.inst 1567254000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 1736643000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13330410791 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 3705500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 82500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 483609000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 922316000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1119629067 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 19173968358 # number of overall miss cycles
< system.l2c.Writeback_accesses::writebacks 233248 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 233248 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 11780 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5037 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 16817 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 1065 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 1299 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2364 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 14907 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 10593 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 25500 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 459 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 64186 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 56202 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 175835 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 194 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 32 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 27609 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 13881 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 17234 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 355698 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 459 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 64186 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 71109 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 175835 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 194 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 27609 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 24474 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 17234 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 381198 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 459 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 64186 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 71109 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 175835 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 194 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 27609 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 24474 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 17234 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 381198 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.744737 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.812984 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.765178 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.761502 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.937644 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.858291 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.725297 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.794487 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.754039 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.252723 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.015152 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.304428 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.151578 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.734552 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.206186 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.031250 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.212648 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.191629 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.533248 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.492266 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.252723 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.015152 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.304428 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.271850 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.734552 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.206186 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.031250 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.212648 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.452562 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.533248 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.509777 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.252723 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.015152 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.304428 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.271850 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.734552 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.206186 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.031250 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.212648 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.452562 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.533248 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.509777 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1071.640260 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1241.636142 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1125.738265 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1451.294698 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1366.995074 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1400.689995 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91527.978172 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81702.055608 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 87227.220720 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86340.517241 # average ReadSharedReq miss latency
---
> system.l2c.overall_miss_latency::cpu0.inst 1558395000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 1837220000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13067901493 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 3962000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 483846500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 936393000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1069849511 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 18968262504 # number of overall miss cycles
> system.l2c.Writeback_accesses::writebacks 232709 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 232709 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 11778 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 5013 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 16791 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 1054 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 1296 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2350 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 15024 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 10637 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 25661 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 508 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 53 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 63927 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 55834 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 174904 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 214 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 33 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 27571 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 13937 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 17207 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 354188 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 508 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 53 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 63927 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 70858 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 174904 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 214 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 27571 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 24574 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 17207 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 379849 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 508 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 53 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 63927 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 70858 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 174904 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 214 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 27571 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 24574 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 17207 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 379849 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.743165 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.812687 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.763921 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.756167 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.935957 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.855319 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.730099 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.794773 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.756907 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.238189 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.018868 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.305755 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.152989 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.735918 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.200935 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.213630 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.193442 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.521706 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.492764 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.238189 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.018868 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.305755 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.275354 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735918 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200935 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.213630 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.453732 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.521706 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.510608 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.238189 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.018868 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.305755 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.275354 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735918 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200935 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.213630 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.453732 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.521706 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.510608 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1047.298069 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1252.822779 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 1112.575037 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1668.757842 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1196.619951 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1383.830846 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99188.348983 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82345.398628 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 91857.334088 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 85884.297521 # average ReadSharedReq miss latency
2606,2615c2604,2612
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80207.471853 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87691.337011 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92637.500000 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 82500 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82372.508942 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88237.406015 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 99925.546597 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86340.517241 # average overall miss latency
---
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79729.612197 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87710.489347 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92139.534884 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82147.113752 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89111.646884 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 98458.826822 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85884.297521 # average overall miss latency
2617,2626c2614,2622
< system.l2c.demand_avg_miss_latency::cpu0.inst 80207.471853 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 89837.204490 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92637.500000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82500 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 82372.508942 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 83271.578187 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 98669.083694 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86340.517241 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 79729.612197 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 94163.292502 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92139.534884 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 82147.113752 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 83981.434978 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 97797.738144 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85884.297521 # average overall miss latency
2628,2637c2624,2632
< system.l2c.overall_avg_miss_latency::cpu0.inst 80207.471853 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 89837.204490 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103208.507208 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92637.500000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82500 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 82372.508942 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 83271.578187 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121831.236888 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 98669.083694 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 73 # number of cycles access was blocked
---
> system.l2c.overall_avg_miss_latency::cpu0.inst 79729.612197 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 94163.292502 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92139.534884 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 82147.113752 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 83981.434978 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 97797.738144 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 442 # number of cycles access was blocked
2639c2634
< system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked
2641c2636
< system.l2c.avg_blocked_cycles::no_mshrs 14.600000 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 221 # average number of cycles each access was blocked
2645,2647c2640,2642
< system.l2c.writebacks::writebacks 103312 # number of writebacks
< system.l2c.writebacks::total 103312 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits
---
> system.l2c.writebacks::writebacks 103131 # number of writebacks
> system.l2c.writebacks::total 103131 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
2649,2650c2644,2645
< system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
---
> system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
2652,2653c2647,2648
< system.l2c.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
---
> system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
2655,2667c2650,2662
< system.l2c.overall_mshr_hits::total 6 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 3718 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 3718 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 8773 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 4095 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 12868 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 811 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1218 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 2029 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 10812 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 8416 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 19228 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 116 # number of ReadSharedReq MSHR misses
---
> system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 3812 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 3812 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 8753 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 4074 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 12827 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 797 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1213 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 2010 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 10969 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 8454 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 19423 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 121 # number of ReadSharedReq MSHR misses
2669,2678c2664,2672
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19538 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8519 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 129160 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 40 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 5867 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2660 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 9190 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 175092 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 116 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19541 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8542 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 128715 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 43 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 5886 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2696 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 8977 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 174522 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 121 # number of demand (read+write) MSHR misses
2680,2689c2674,2682
< system.l2c.demand_mshr_misses::cpu0.inst 19538 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 19331 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 129160 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 40 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 5867 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 11076 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9190 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 194320 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 116 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 19541 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 19511 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128715 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 43 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 5886 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 11150 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8977 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 193945 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 121 # number of overall MSHR misses
2691,2699c2684,2691
< system.l2c.overall_mshr_misses::cpu0.inst 19538 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 19331 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 129160 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 40 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 5867 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 11076 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9190 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 194320 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.inst 19541 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 19511 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128715 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 43 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 5886 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 11150 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 8977 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 193945 # number of overall MSHR misses
2701c2693
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 18002 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable
2703,2707c2695,2699
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17138 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 38679 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16758 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14413 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 31171 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17124 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 38664 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16756 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14405 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 31161 # number of WriteReq MSHR uncacheable
2709c2701
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34760 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34757 # number of overall MSHR uncacheable misses
2711,2722c2703,2714
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31551 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 69850 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 182968000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 85020001 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 267988001 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16936500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25297000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 42233500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 881480500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 603444500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 1484925000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 8855500 # number of ReadSharedReq MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31529 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 69825 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 181795500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 84589501 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 266385001 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16646000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25174500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 41820500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 978307000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 611608000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 1589915000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 9182000 # number of ReadSharedReq MSHR miss cycles
2724,2728c2716,2719
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1371777500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 661852500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12038810791 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 3305500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 72500 # number of ReadSharedReq MSHR miss cycles
---
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1362728000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 663803000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11780751493 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 3532000 # number of ReadSharedReq MSHR miss cycles
2730,2733c2721,2724
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 208111500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1027729067 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 15745558358 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 8855500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 213285000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 980079511 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 15438404504 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9182000 # number of demand (read+write) MSHR miss cycles
2735,2739c2726,2729
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1371777500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 1543333000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12038810791 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3305500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 72500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1362728000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 1642110000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11780751493 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3532000 # number of demand (read+write) MSHR miss cycles
2741,2744c2731,2734
< system.l2c.demand_mshr_miss_latency::cpu1.data 811556000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1027729067 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 17230483358 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 8855500 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu1.data 824893000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 980079511 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 17028319504 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9182000 # number of overall MSHR miss cycles
2746,2750c2736,2739
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1371777500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 1543333000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12038810791 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3305500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 72500 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1362728000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 1642110000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11780751493 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3532000 # number of overall MSHR miss cycles
2752,2754c2741,2743
< system.l2c.overall_mshr_miss_latency::cpu1.data 811556000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1027729067 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 17230483358 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu1.data 824893000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 980079511 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 17028319504 # number of overall MSHR miss cycles
2756,2762c2745,2751
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3283407500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6877000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2489619500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 5994828500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2314728500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2093956000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4408684500 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3283233500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6848500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2489515500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 5994522000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2314676500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2093562500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4408239000 # number of WriteReq MSHR uncacheable cycles
2764,2767c2753,2756
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5598136000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6877000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4583575500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 10403513000 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5597910000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6848500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4583078000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10402761000 # number of overall MSHR uncacheable cycles
2770,2821c2759,2807
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.744737 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.812984 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.765178 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.761502 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.937644 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.858291 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725297 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.794487 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.754039 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.252723 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.015152 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.304397 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.151578 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.734552 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.206186 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.031250 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.212503 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.191629 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533248 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.492249 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.252723 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015152 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.304397 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.271850 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.734552 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.206186 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.031250 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.212503 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.452562 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533248 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.509761 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.252723 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015152 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.304397 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.271850 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.734552 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.206186 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.031250 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.212503 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.452562 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533248 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.509761 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20855.807591 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20761.905006 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20825.924852 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20883.477189 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20769.293924 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20814.933465 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81527.978172 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71702.055608 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 77227.220720 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average ReadSharedReq mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.743165 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.812687 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.763921 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.756167 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935957 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.855319 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.730099 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.794773 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.756907 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.152989 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.193442 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.492738 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.275354 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.453732 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.510584 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.275354 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.453732 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.510584 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20769.507597 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.255032 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20767.521712 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20885.821832 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20753.915911 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20806.218905 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89188.348983 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72345.398628 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 81857.334088 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average ReadSharedReq mshr miss latency
2823,2832c2809,2817
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77691.337011 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78237.406015 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89927.343100 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average overall mshr miss latency
---
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77710.489347 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79111.646884 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88461.079428 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average overall mshr miss latency
2834,2843c2819,2827
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79837.204490 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73271.578187 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 88670.663637 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84163.292502 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73981.434978 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 87799.734481 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average overall mshr miss latency
2845,2853c2829,2836
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79837.204490 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73271.578187 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 88670.663637 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84163.292502 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73981.434978 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 87799.734481 # average overall mshr miss latency
2855,2861c2838,2844
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.262082 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145268.963706 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154989.231883 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138126.775272 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145282.453341 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141435.452825 # average WriteReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.728237 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145381.657323 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 155041.433892 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138140.158749 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145335.820896 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141466.544719 # average WriteReq mshr uncacheable latency
2863,2866c2846,2849
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161051.093211 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145275.125986 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 148940.773085 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161058.491815 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145360.715532 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 148983.329753 # average overall mshr uncacheable latency
2868,2880c2851,2862
< system.membus.trans_dist::ReadReq 38679 # Transaction distribution
< system.membus.trans_dist::ReadResp 214027 # Transaction distribution
< system.membus.trans_dist::WriteReq 31171 # Transaction distribution
< system.membus.trans_dist::WriteResp 31171 # Transaction distribution
< system.membus.trans_dist::Writeback 139502 # Transaction distribution
< system.membus.trans_dist::CleanEvict 18408 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 78648 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 41625 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 15041 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
< system.membus.trans_dist::ReadExReq 39591 # Transaction distribution
< system.membus.trans_dist::ReadExResp 19084 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 175348 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 38664 # Transaction distribution
> system.membus.trans_dist::ReadResp 213442 # Transaction distribution
> system.membus.trans_dist::WriteReq 31161 # Transaction distribution
> system.membus.trans_dist::WriteResp 31161 # Transaction distribution
> system.membus.trans_dist::Writeback 139337 # Transaction distribution
> system.membus.trans_dist::CleanEvict 18210 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 78893 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 41609 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 14967 # Transaction distribution
> system.membus.trans_dist::ReadExReq 39746 # Transaction distribution
> system.membus.trans_dist::ReadExResp 19293 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 174778 # Transaction distribution
2883c2865
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes)
2885,2891c2867,2873
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14764 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 682494 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 805212 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 914134 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14714 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 681524 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 804190 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108938 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 108938 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 913128 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes)
2893,2900c2875,2882
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29528 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19261796 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 19455462 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 21772582 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 126350 # Total snoops (count)
< system.membus.snoop_fanout::samples 599467 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29428 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19228072 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 19421637 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 21739781 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 126569 # Total snoops (count)
> system.membus.snoop_fanout::samples 598906 # Request fanout histogram
2905c2887
< system.membus.snoop_fanout::1 599467 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 598906 100.00% 100.00% # Request fanout histogram
2910,2911c2892,2893
< system.membus.snoop_fanout::total 599467 # Request fanout histogram
< system.membus.reqLayer0.occupancy 91393000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 598906 # Request fanout histogram
> system.membus.reqLayer0.occupancy 91147500 # Layer occupancy (ticks)
2913c2895
< system.membus.reqLayer1.occupancy 24328 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks)
2915c2897
< system.membus.reqLayer2.occupancy 12942500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 12904500 # Layer occupancy (ticks)
2917c2899
< system.membus.reqLayer5.occupancy 1014707988 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1003618732 # Layer occupancy (ticks)
2919c2901
< system.membus.respLayer2.occupancy 1166663343 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1163956699 # Layer occupancy (ticks)
2921c2903
< system.membus.respLayer3.occupancy 64473559 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 64493538 # Layer occupancy (ticks)
2954,2967c2936,2949
< system.toL2Bus.trans_dist::ReadReq 38683 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 520875 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 31171 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 372774 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 100063 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 82453 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 41960 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 124413 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 51599 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 51599 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 482207 # Transaction distribution
---
> system.toL2Bus.trans_dist::ReadReq 38668 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 519865 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 31161 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 372085 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 99404 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 82727 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 124676 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 51768 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 51768 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 481212 # Transaction distribution
2969,2978c2951,2960
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1095171 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 404182 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1499353 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32852839 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6925951 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 39778790 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 466118 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 1289558 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.161505 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.367996 # Request fanout histogram
---
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1091980 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 404567 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1496547 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32727326 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6930535 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 39657861 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 466410 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 1287380 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.161360 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.367862 # Request fanout histogram
2981,2982c2963,2964
< system.toL2Bus.snoop_fanout::1 1081288 83.85% 83.85% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 208270 16.15% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::1 1079649 83.86% 83.86% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 207731 16.14% 100.00% # Request fanout histogram
2986,2987c2968,2969
< system.toL2Bus.snoop_fanout::total 1289558 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 856703495 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 1287380 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 861414818 # Layer occupancy (ticks)
2991c2973
< system.toL2Bus.respLayer0.occupancy 633166148 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 631551677 # Layer occupancy (ticks)
2993c2975
< system.toL2Bus.respLayer1.occupancy 285761511 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 286263459 # Layer occupancy (ticks)