3,5c3,5
< sim_seconds 2.843655 # Number of seconds simulated
< sim_ticks 2843654861000 # Number of ticks simulated
< final_tick 2843654861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.844427 # Number of seconds simulated
> sim_ticks 2844427140500 # Number of ticks simulated
> final_tick 2844427140500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 157498 # Simulator instruction rate (inst/s)
< host_op_rate 190690 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 3581426538 # Simulator tick rate (ticks/s)
< host_mem_usage 613612 # Number of bytes of host memory used
< host_seconds 794.00 # Real time elapsed on the host
< sim_insts 125053138 # Number of instructions simulated
< sim_ops 151407658 # Number of ops (including micro ops) simulated
---
> host_inst_rate 150296 # Simulator instruction rate (inst/s)
> host_op_rate 181972 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3416553864 # Simulator tick rate (ticks/s)
> host_mem_usage 612172 # Number of bytes of host memory used
> host_seconds 832.54 # Real time elapsed on the host
> sim_insts 125127935 # Number of instructions simulated
> sim_ops 151499394 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 10304 # Number of bytes read from this memory
18,22c18,22
< system.physmem.bytes_read::cpu0.inst 1363068 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 10771008 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 534304 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 1165248 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1349820 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 10836800 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 503456 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 1120064 # Number of bytes read from this memory
24,28c24,28
< system.physmem.bytes_read::total 13845276 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 418688 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 26560 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 445248 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7176128 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 13821980 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 416640 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 27264 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 443904 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9404288 # Number of bytes written to this memory
31,33c31,32
< system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9512208 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 9422032 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 161 # Number of read requests responded to by this memory
35,39c34,38
< system.physmem.num_reads::cpu0.inst 21823 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 168297 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 8372 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 18207 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 21616 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 169325 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 7890 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 17501 # Number of read requests responded to by this memory
41,42c40,41
< system.physmem.num_reads::total 216881 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 112127 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 216517 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 146942 # Number of write requests responded to by this memory
45,47c44,45
< system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 152787 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 3398 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 151378 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 3623 # Total read bandwidth from this memory (bytes/s)
49,53c47,51
< system.physmem.bw_read::cpu0.inst 479337 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 3787734 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 338 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 187893 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 409771 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 474549 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 3809836 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 176997 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 393775 # Total read bandwidth from this memory (bytes/s)
55,60c53,58
< system.physmem.bw_read::total 4868831 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 147236 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 9340 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 156576 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2523558 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4859319 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 146476 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 9585 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 156061 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3306215 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.inst 6224 # Write bandwidth from this memory (bytes/s)
62,65c60,62
< system.physmem.bw_write::realview.ide 815266 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3345064 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2523558 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 3398 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3312453 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3306215 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 3623 # Total bandwidth to/from this memory (bytes/s)
67,117c64,114
< system.physmem.bw_total::cpu0.inst 485562 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 3787734 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 338 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 187907 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 409771 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 815604 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 8213896 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 216881 # Number of read requests accepted
< system.physmem.writeReqs 152787 # Number of write requests accepted
< system.physmem.readBursts 216881 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 152787 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 13864960 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 15424 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9526912 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 13845276 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 9512208 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 13516 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 13445 # Per bank write bursts
< system.physmem.perBankRdBursts::1 13090 # Per bank write bursts
< system.physmem.perBankRdBursts::2 14400 # Per bank write bursts
< system.physmem.perBankRdBursts::3 13760 # Per bank write bursts
< system.physmem.perBankRdBursts::4 15799 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12812 # Per bank write bursts
< system.physmem.perBankRdBursts::6 13576 # Per bank write bursts
< system.physmem.perBankRdBursts::7 13750 # Per bank write bursts
< system.physmem.perBankRdBursts::8 13572 # Per bank write bursts
< system.physmem.perBankRdBursts::9 13600 # Per bank write bursts
< system.physmem.perBankRdBursts::10 13300 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11904 # Per bank write bursts
< system.physmem.perBankRdBursts::12 13370 # Per bank write bursts
< system.physmem.perBankRdBursts::13 13720 # Per bank write bursts
< system.physmem.perBankRdBursts::14 13497 # Per bank write bursts
< system.physmem.perBankRdBursts::15 13045 # Per bank write bursts
< system.physmem.perBankWrBursts::0 9322 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9428 # Per bank write bursts
< system.physmem.perBankWrBursts::2 10143 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9576 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8974 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8900 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9376 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9386 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9384 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9431 # Per bank write bursts
< system.physmem.perBankWrBursts::10 9355 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8834 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9379 # Per bank write bursts
< system.physmem.perBankWrBursts::13 9206 # Per bank write bursts
< system.physmem.perBankWrBursts::14 9289 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8875 # Per bank write bursts
---
> system.physmem.bw_total::cpu0.inst 480773 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 3809836 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 177011 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 393775 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 8171773 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 216517 # Number of read requests accepted
> system.physmem.writeReqs 187602 # Number of write requests accepted
> system.physmem.readBursts 216517 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 187602 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 13846784 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue
> system.physmem.bytesWritten 11642944 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 13821980 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 11740368 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 5664 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 13644 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 13513 # Per bank write bursts
> system.physmem.perBankRdBursts::1 13311 # Per bank write bursts
> system.physmem.perBankRdBursts::2 14548 # Per bank write bursts
> system.physmem.perBankRdBursts::3 14027 # Per bank write bursts
> system.physmem.perBankRdBursts::4 15548 # Per bank write bursts
> system.physmem.perBankRdBursts::5 13123 # Per bank write bursts
> system.physmem.perBankRdBursts::6 13508 # Per bank write bursts
> system.physmem.perBankRdBursts::7 14039 # Per bank write bursts
> system.physmem.perBankRdBursts::8 13183 # Per bank write bursts
> system.physmem.perBankRdBursts::9 13181 # Per bank write bursts
> system.physmem.perBankRdBursts::10 13142 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11743 # Per bank write bursts
> system.physmem.perBankRdBursts::12 13238 # Per bank write bursts
> system.physmem.perBankRdBursts::13 14181 # Per bank write bursts
> system.physmem.perBankRdBursts::14 13272 # Per bank write bursts
> system.physmem.perBankRdBursts::15 12799 # Per bank write bursts
> system.physmem.perBankWrBursts::0 11429 # Per bank write bursts
> system.physmem.perBankWrBursts::1 11725 # Per bank write bursts
> system.physmem.perBankWrBursts::2 12190 # Per bank write bursts
> system.physmem.perBankWrBursts::3 11854 # Per bank write bursts
> system.physmem.perBankWrBursts::4 10909 # Per bank write bursts
> system.physmem.perBankWrBursts::5 11199 # Per bank write bursts
> system.physmem.perBankWrBursts::6 11528 # Per bank write bursts
> system.physmem.perBankWrBursts::7 11643 # Per bank write bursts
> system.physmem.perBankWrBursts::8 11026 # Per bank write bursts
> system.physmem.perBankWrBursts::9 11436 # Per bank write bursts
> system.physmem.perBankWrBursts::10 11468 # Per bank write bursts
> system.physmem.perBankWrBursts::11 11022 # Per bank write bursts
> system.physmem.perBankWrBursts::12 11525 # Per bank write bursts
> system.physmem.perBankWrBursts::13 11398 # Per bank write bursts
> system.physmem.perBankWrBursts::14 10974 # Per bank write bursts
> system.physmem.perBankWrBursts::15 10595 # Per bank write bursts
119,120c116,117
< system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
< system.physmem.totGap 2843652584000 # Total gap between requests
---
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 2844424796500 # Total gap between requests
127c124
< system.physmem.readPktSize::6 216294 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 215930 # Read request sizes (log2)
134,151c131,148
< system.physmem.writePktSize::6 148351 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 79253 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 62833 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 17902 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 12267 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 10637 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 9321 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 8351 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 7490 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 425 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 318 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 210 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 171 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 183166 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 79055 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 63481 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 16932 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 12216 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 10702 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 9369 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 8301 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 7427 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 6415 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1133 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 442 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 303 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 206 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 92 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
153,154c150,151
< system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
182,220c179,217
< system.physmem.wrQLenPdf::15 2952 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4345 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5357 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6270 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7461 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 8095 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8963 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9736 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 10858 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10694 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10594 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 10430 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 10909 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 9025 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 8830 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 8791 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 8216 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 582 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 381 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 300 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 3120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5952 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 7602 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 8745 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 10117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 11015 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 12070 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 12267 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 13080 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 12741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 12428 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 11920 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 12228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 10042 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 9631 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 9531 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 8901 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 927 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 714 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 577 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 448 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 238 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see
222,248c219,245
< system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 92618 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 252.562223 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 143.207145 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 307.469960 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 46921 50.66% 50.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18876 20.38% 71.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6855 7.40% 78.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3600 3.89% 82.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3008 3.25% 85.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2120 2.29% 87.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1341 1.45% 89.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1115 1.20% 90.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8782 9.48% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 92618 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 7463 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 29.028407 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 529.473600 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 7462 99.99% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 93322 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 273.137395 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 151.655882 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 326.256113 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 45588 48.85% 48.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 18736 20.08% 68.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6915 7.41% 76.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3558 3.81% 80.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3108 3.33% 83.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2062 2.21% 85.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1352 1.45% 87.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1057 1.13% 88.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 10946 11.73% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 93322 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 7762 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 27.873744 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 521.384620 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 7761 99.99% 99.99% # Reads before turning the bus around for writes
250,290c247,304
< system.physmem.rdPerTurnAround::total 7463 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 7463 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.946134 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.603737 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.129560 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 6171 82.69% 82.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 489 6.55% 89.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 84 1.13% 90.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 205 2.75% 93.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 200 2.68% 95.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 17 0.23% 96.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 17 0.23% 96.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 12 0.16% 96.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 25 0.33% 96.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 6 0.08% 96.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 6 0.08% 96.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 3 0.04% 96.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 165 2.21% 99.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 7 0.09% 99.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 6 0.08% 99.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 18 0.24% 99.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.01% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 7 0.09% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.01% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 3 0.04% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.01% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 8 0.11% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.01% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 3 0.04% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 7463 # Writes before turning the bus around for reads
< system.physmem.totQLat 7683149500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11745149500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1083200000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 35465.05 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 7762 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 7762 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 23.437387 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 19.920909 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 21.626862 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 6141 79.12% 79.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 490 6.31% 85.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 77 0.99% 86.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 208 2.68% 89.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 144 1.86% 90.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 54 0.70% 91.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 53 0.68% 92.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 34 0.44% 92.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 115 1.48% 94.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 15 0.19% 94.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 16 0.21% 94.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 14 0.18% 94.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 31 0.40% 95.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 17 0.22% 95.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 9 0.12% 95.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 24 0.31% 95.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 61 0.79% 96.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 9 0.12% 96.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 4 0.05% 96.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 7 0.09% 96.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 74 0.95% 97.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.03% 97.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 12 0.15% 98.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 8 0.10% 98.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 21 0.27% 98.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 7 0.09% 98.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 12 0.15% 98.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 7 0.09% 98.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 28 0.36% 99.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 9 0.12% 99.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 3 0.04% 99.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 9 0.12% 99.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 8 0.10% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 3 0.04% 99.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 7 0.09% 99.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 3 0.04% 99.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-171 1 0.01% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 5 0.06% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 3 0.04% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-187 3 0.04% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 3 0.04% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::200-203 1 0.01% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-211 2 0.03% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::220-223 3 0.04% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 7762 # Writes before turning the bus around for reads
> system.physmem.totQLat 7644398000 # Total ticks spent queuing
> system.physmem.totMemAccLat 11701073000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1081780000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 35332.50 # Average queueing delay per DRAM burst
292,296c306,310
< system.physmem.avgMemAccLat 54215.05 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.88 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 54082.50 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 4.86 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 4.13 # Average system write bandwidth in MiByte/s
298c312
< system.physmem.busUtil 0.06 # Data bus utilization in percentage
---
> system.physmem.busUtil 0.07 # Data bus utilization in percentage
301,310c315,324
< system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.48 # Average write queue length when enqueuing
< system.physmem.readRowHits 183194 # Number of row buffer hits during reads
< system.physmem.writeRowHits 89685 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 84.56 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 60.24 # Row buffer hit rate for writes
< system.physmem.avgGap 7692449.94 # Average gap between requests
< system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 2709796310750 # Time in different power states
< system.physmem.memoryStateTime::REF 94955640000 # Time in different power states
---
> system.physmem.avgRdQLen 1.94 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 21.48 # Average write queue length when enqueuing
> system.physmem.readRowHits 183280 # Number of row buffer hits during reads
> system.physmem.writeRowHits 121675 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 84.71 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 66.88 # Row buffer hit rate for writes
> system.physmem.avgGap 7038582.19 # Average gap between requests
> system.physmem.pageHitRate 76.57 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2710525028500 # Time in different power states
> system.physmem.memoryStateTime::REF 94981640000 # Time in different power states
312c326
< system.physmem.memoryStateTime::ACT 38900516750 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 38919724000 # Time in different power states
314,331c328,345
< system.physmem.actEnergy::0 358956360 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 341235720 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 195859125 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 186190125 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 862929600 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 826854600 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 486680400 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 477919440 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 185733231840 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 185733231840 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 81937929780 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 81435296655 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1634313275250 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1634754181500 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1903888862355 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1903754909880 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.523453 # Core power per rank (mW)
< system.physmem.averagePower::1 669.476347 # Core power per rank (mW)
---
> system.physmem.actEnergy::0 365533560 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 339980760 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 199447875 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 185505375 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 870612600 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 816964200 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 599250960 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 579597120 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 185784087840 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 185784087840 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 82151193285 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 81119552850 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1634593377000 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1635498324750 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1904563503120 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1904324012895 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.577359 # Core power per rank (mW)
> system.physmem.averagePower::1 669.493163 # Core power per rank (mW)
356,360c370,374
< system.cpu0.branchPred.lookups 34892527 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 17126488 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 1674515 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 20008950 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 14462185 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 35736686 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 17706973 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 1707657 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 20554340 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 14845557 # Number of BTB hits
362,364c376,378
< system.cpu0.branchPred.BTBHitPct 72.278580 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 10813099 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 822816 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 72.225900 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 10924417 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 815226 # Number of incorrect RAS predictions.
389,392c403,406
< system.cpu0.dtb.read_hits 23969265 # DTB read hits
< system.cpu0.dtb.read_misses 62663 # DTB read misses
< system.cpu0.dtb.write_hits 17948332 # DTB write hits
< system.cpu0.dtb.write_misses 6711 # DTB write misses
---
> system.cpu0.dtb.read_hits 24607000 # DTB read hits
> system.cpu0.dtb.read_misses 66402 # DTB read misses
> system.cpu0.dtb.write_hits 18455953 # DTB write hits
> system.cpu0.dtb.write_misses 6655 # DTB write misses
397,399c411,413
< system.cpu0.dtb.flush_entries 3475 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 1396 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 1982 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 3808 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 1234 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 2108 # Number of TLB faults due to prefetch
401,403c415,417
< system.cpu0.dtb.perms_faults 568 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 24031928 # DTB read accesses
< system.cpu0.dtb.write_accesses 17955043 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 615 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 24673402 # DTB read accesses
> system.cpu0.dtb.write_accesses 18462608 # DTB write accesses
405,407c419,421
< system.cpu0.dtb.hits 41917597 # DTB hits
< system.cpu0.dtb.misses 69374 # DTB misses
< system.cpu0.dtb.accesses 41986971 # DTB accesses
---
> system.cpu0.dtb.hits 43062953 # DTB hits
> system.cpu0.dtb.misses 73057 # DTB misses
> system.cpu0.dtb.accesses 43136010 # DTB accesses
429,430c443,444
< system.cpu0.itb.inst_hits 70358748 # ITB inst hits
< system.cpu0.itb.inst_misses 3854 # ITB inst misses
---
> system.cpu0.itb.inst_hits 71661808 # ITB inst hits
> system.cpu0.itb.inst_misses 4142 # ITB inst misses
439c453
< system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2456 # Number of entries that have been flushed from TLB
443c457
< system.cpu0.itb.perms_faults 7388 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 8241 # Number of TLB faults due to permissions restrictions
446,450c460,464
< system.cpu0.itb.inst_accesses 70362602 # ITB inst accesses
< system.cpu0.itb.hits 70358748 # DTB hits
< system.cpu0.itb.misses 3854 # DTB misses
< system.cpu0.itb.accesses 70362602 # DTB accesses
< system.cpu0.numCycles 229119066 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 71665950 # ITB inst accesses
> system.cpu0.itb.hits 71661808 # DTB hits
> system.cpu0.itb.misses 4142 # DTB misses
> system.cpu0.itb.accesses 71665950 # DTB accesses
> system.cpu0.numCycles 235973632 # number of cpu cycles simulated
453,459c467,473
< system.cpu0.committedInsts 109189984 # Number of instructions committed
< system.cpu0.committedOps 132016369 # Number of ops (including micro ops) committed
< system.cpu0.discardedOps 8791665 # Number of ops (including micro ops) which were discarded before commit
< system.cpu0.numFetchSuspends 1828 # Number of times Execute suspended instruction fetching
< system.cpu0.quiesceCycles 5458204948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.cpi 2.098352 # CPI: cycles per instruction
< system.cpu0.ipc 0.476564 # IPC: instructions per cycle
---
> system.cpu0.committedInsts 111703770 # Number of instructions committed
> system.cpu0.committedOps 135097839 # Number of ops (including micro ops) committed
> system.cpu0.discardedOps 8562554 # Number of ops (including micro ops) which were discarded before commit
> system.cpu0.numFetchSuspends 1855 # Number of times Execute suspended instruction fetching
> system.cpu0.quiesceCycles 5452894525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.cpi 2.112495 # CPI: cycles per instruction
> system.cpu0.ipc 0.473374 # IPC: instructions per cycle
461,472c475,486
< system.cpu0.kern.inst.quiesce 1830 # number of quiesce instructions executed
< system.cpu0.tickCycles 193229301 # Number of cycles that the object actually ticked
< system.cpu0.idleCycles 35889765 # Total number of cycles that the object has spent stopped
< system.cpu0.dcache.tags.replacements 714801 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 493.827802 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 40473769 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 715313 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 56.581901 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.inst 493.827802 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.964507 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.964507 # Average percentage of cache occupancy
---
> system.cpu0.kern.inst.quiesce 1855 # number of quiesce instructions executed
> system.cpu0.tickCycles 199544848 # Number of cycles that the object actually ticked
> system.cpu0.idleCycles 36428784 # Total number of cycles that the object has spent stopped
> system.cpu0.dcache.tags.replacements 751860 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 494.262864 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 41566353 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 752372 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 55.247076 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 306713000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.262864 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965357 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.965357 # Average percentage of cache occupancy
475,476c489,490
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
478,549c492,563
< system.cpu0.dcache.tags.tag_accesses 83782876 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 83782876 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.inst 22802755 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 22802755 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862558 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 16862558 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381551 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 381551 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362630 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 362630 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.inst 39665313 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 39665313 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.inst 39665313 # number of overall hits
< system.cpu0.dcache.overall_hits::total 39665313 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.inst 537301 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 537301 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.inst 532764 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 532764 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6412 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 6412 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20204 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 20204 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.inst 1070065 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 1070065 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.inst 1070065 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1070065 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609674711 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 6609674711 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8019150247 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 8019150247 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 105707749 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 105707749 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 437634051 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 437634051 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.inst 14628824958 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 14628824958 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.inst 14628824958 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 14628824958 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23340056 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 23340056 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395322 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 17395322 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387963 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 387963 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382834 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 382834 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.inst 40735378 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 40735378 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.inst 40735378 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 40735378 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023021 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.023021 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030627 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.030627 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016527 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016527 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052775 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052775 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026269 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.026269 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026269 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.026269 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12301.623691 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 12301.623691 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15051.974696 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 15051.974696 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16485.924672 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16485.924672 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21660.762770 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21660.762770 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 86104149 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 86104149 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.inst 23403701 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 23403701 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.inst 17336391 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 17336391 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 390425 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 390425 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 371566 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 371566 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.inst 40740092 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 40740092 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.inst 40740092 # number of overall hits
> system.cpu0.dcache.overall_hits::total 40740092 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.inst 564897 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 564897 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.inst 554409 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 554409 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6644 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 6644 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20340 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 20340 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.inst 1119306 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1119306 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.inst 1119306 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1119306 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6887885459 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 6887885459 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8219762503 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 8219762503 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 108110000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 108110000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 440070983 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 440070983 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 121000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.inst 15107647962 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 15107647962 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.inst 15107647962 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 15107647962 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23968598 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 23968598 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17890800 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 17890800 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 397069 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 397069 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 391906 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 391906 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.inst 41859398 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 41859398 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.inst 41859398 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 41859398 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023568 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.023568 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030988 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.030988 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016733 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016733 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051900 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051900 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026740 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.026740 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026740 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.026740 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12193.170541 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 12193.170541 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 14826.170757 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 14826.170757 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16271.824202 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.824202 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21635.741544 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21635.741544 # average StoreCondReq miss latency
552,555c566,569
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 13670.968547 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 13670.968547 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 13497.334922 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 13497.334922 # average overall miss latency
564,627c578,639
< system.cpu0.dcache.writebacks::writebacks 517954 # number of writebacks
< system.cpu0.dcache.writebacks::total 517954 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42678 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 42678 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230706 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 230706 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273384 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 273384 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273384 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 273384 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494623 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 494623 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302058 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 302058 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6411 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6411 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20204 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 20204 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796681 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 796681 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796681 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 796681 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5117531439 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5117531439 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4270825900 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4270825900 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 92832750 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 92832750 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 396783949 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 396783949 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9388357339 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9388357339 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9388357339 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 9388357339 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191310497 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191310497 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803760492 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803760492 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995070989 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995070989 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021192 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021192 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017364 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017364 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016525 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016525 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052775 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052775 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.019557 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.019557 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10346.327282 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10346.327282 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14139.092161 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14139.092161 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14480.229293 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14480.229293 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19638.880865 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19638.880865 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 541643 # number of writebacks
> system.cpu0.dcache.writebacks::total 541643 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 45094 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 45094 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 240822 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 240822 # number of WriteReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.inst 285916 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 285916 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.inst 285916 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 285916 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 519803 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 519803 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 313587 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 313587 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6644 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6644 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20340 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 20340 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.inst 833390 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 833390 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.inst 833390 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 833390 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5323715430 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5323715430 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4366940170 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4366940170 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 94806000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94806000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 398879017 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 398879017 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 115000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 115000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9690655600 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 9690655600 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9690655600 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 9690655600 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6196262496 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6196262496 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4811489492 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4811489492 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11007751988 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11007751988 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021687 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021687 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017528 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017528 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016733 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016733 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051900 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051900 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.019909 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.019909 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10241.794353 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10241.794353 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13925.769149 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13925.769149 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14269.416014 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14269.416014 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19610.571141 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19610.571141 # average StoreCondReq mshr miss latency
630,633c642,645
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency
641,649c653,661
< system.cpu0.icache.tags.replacements 1983566 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.796833 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 68366923 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1984078 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 34.457780 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796833 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.replacements 2070442 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.797171 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 69582233 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 2070954 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 33.599121 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 6297775000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.797171 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999604 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy
651,653c663,665
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id
655,692c667,704
< system.cpu0.icache.tags.tag_accesses 142686127 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 142686127 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 68366923 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 68366923 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 68366923 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 68366923 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 68366923 # number of overall hits
< system.cpu0.icache.overall_hits::total 68366923 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1984094 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1984094 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1984094 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1984094 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1984094 # number of overall misses
< system.cpu0.icache.overall_misses::total 1984094 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16546799645 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 16546799645 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 16546799645 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 16546799645 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 16546799645 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 16546799645 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 70351017 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 70351017 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 70351017 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 70351017 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 70351017 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 70351017 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028203 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.028203 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028203 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.028203 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028203 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.028203 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.725661 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.725661 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 8339.725661 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 8339.725661 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 145377375 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 145377375 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 69582233 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 69582233 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 69582233 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 69582233 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 69582233 # number of overall hits
> system.cpu0.icache.overall_hits::total 69582233 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 2070970 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 2070970 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 2070970 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 2070970 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 2070970 # number of overall misses
> system.cpu0.icache.overall_misses::total 2070970 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17258012980 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 17258012980 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 17258012980 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 17258012980 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 17258012980 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 17258012980 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 71653203 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 71653203 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 71653203 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 71653203 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 71653203 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 71653203 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028903 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.028903 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028903 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.028903 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028903 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.028903 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8333.299362 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 8333.299362 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 8333.299362 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 8333.299362 # average overall miss latency
701,728c713,740
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1984094 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1984094 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1984094 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1984094 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1984094 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1984094 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13568682853 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 13568682853 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13568682853 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 13568682853 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13568682853 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 13568682853 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276787500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276787500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276787500 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 276787500 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028203 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.028203 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.028203 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.729845 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2070970 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 2070970 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 2070970 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 2070970 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 2070970 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 2070970 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 14149699520 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 14149699520 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 14149699520 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 14149699520 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 14149699520 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 14149699520 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276493750 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276493750 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276493750 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 276493750 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028903 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.028903 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.028903 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6832.401976 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency
734,737c746,749
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17337039 # number of hwpf identified
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425762 # number of hwpf that were already in mshr
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16383461 # number of hwpf that were already in the cache
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9078 # number of hwpf that were already in the prefetch queue
---
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 18115074 # number of hwpf identified
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 431506 # number of hwpf that were already in mshr
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 17132776 # number of hwpf that were already in the cache
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9283 # number of hwpf that were already in the prefetch queue
739,741c751,753
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6456 # number of hwpf removed because MSHR allocated
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512279 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329409 # number of hwpf spanning a virtual page
---
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6596 # number of hwpf removed because MSHR allocated
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 534910 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1383846 # number of hwpf spanning a virtual page
743,755c755,767
< system.cpu0.l2cache.tags.replacements 409357 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16202.462840 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 3013500 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 425611 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 7.080409 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 4205.324174 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 51.364575 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062072 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2198.474976 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.237044 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.256673 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003135 # Average percentage of cache occupancy
---
> system.cpu0.l2cache.tags.replacements 428439 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16212.256950 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 3152645 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 444682 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 7.089662 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 2824980212500 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 4226.197620 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.775812 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065487 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2187.555983 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.662049 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.257947 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003099 # Average percentage of cache occupancy
757,905c769,908
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134184 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594924 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.988920 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8963 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7281 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 54 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2805 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5150 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 820 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3125 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3482 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 341 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.547058 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444397 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 55309059 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 55309059 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77781 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4268 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390782 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 2472831 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 517951 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 517951 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4630 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 4630 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2244 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 2244 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223140 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 223140 # number of ReadExReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77781 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4268 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 2613922 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 2695971 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77781 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4268 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 2613922 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 2695971 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 986 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94341 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 95500 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27941 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17958 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 17958 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 2 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46352 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 46352 # number of ReadExReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 986 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 140693 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 141852 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 986 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 140693 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 141852 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 32261749 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3849999 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2894443882 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 2930555630 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 497270548 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 497270548 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 354837739 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 354837739 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 117000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 117000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1925679719 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 1925679719 # number of ReadExReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 32261749 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3849999 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4820123601 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 4856235349 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 32261749 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3849999 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4820123601 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 4856235349 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78767 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4441 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2485123 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 2568331 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 517951 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 517951 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32571 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 32571 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20202 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 20202 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 2 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 269492 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 269492 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78767 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4441 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 2754615 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 2837823 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78767 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4441 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 2754615 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 2837823 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.038955 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037962 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.037184 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.857849 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.857849 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.888922 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.888922 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses
< system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.171998 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171998 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.038955 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051075 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.049986 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.038955 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051075 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.049986 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22254.329480 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30680.657212 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30686.446387 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17797.163595 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17797.163595 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19759.312785 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19759.312785 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 58500 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 58500 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41544.695353 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41544.695353 # average ReadExReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22254.329480 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34259.867947 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 34234.521537 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22254.329480 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34259.867947 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 34234.521537 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 25463 # number of cycles access was blocked
---
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.133518 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594950 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.989518 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8981 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7254 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 61 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 111 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2870 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5529 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 410 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3049 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3651 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 230 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.548157 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.442749 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 57799798 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 57799798 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 84149 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4243 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2500411 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 2588803 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 541643 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 541643 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4674 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 4674 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2411 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 2411 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 234433 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 234433 # number of ReadExReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 84149 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4243 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 2734844 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 2823236 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 84149 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4243 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 2734844 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 2823236 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 906 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.inst 97001 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 98045 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27960 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 27960 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17929 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 17929 # number of SCUpgradeReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46525 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 46525 # number of ReadExReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 906 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 143526 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 144570 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 906 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 143526 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 144570 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31530500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3231999 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2954004148 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 2988766647 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 497244183 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 497244183 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 356127296 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356127296 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 112000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 112000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1936152477 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 1936152477 # number of ReadExReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31530500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3231999 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4890156625 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 4924919124 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31530500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3231999 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4890156625 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 4924919124 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 85055 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4381 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2597412 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 2686848 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 541643 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 541643 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32634 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 32634 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20340 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 20340 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 280958 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 280958 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 85055 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4381 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 2878370 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 2967806 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 85055 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4381 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 2878370 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 2967806 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031500 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037345 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.036491 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.856775 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.856775 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.881465 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.881465 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.165594 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.165594 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031500 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.049864 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.048713 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031500 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.049864 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.048713 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23420.282609 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30453.337058 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30483.621266 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17784.126717 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17784.126717 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19863.199063 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19863.199063 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41615.313853 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41615.313853 # average ReadExReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23420.282609 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34071.573269 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 34065.982735 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23420.282609 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34071.573269 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 34065.982735 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 25119 # number of cycles access was blocked
907c910
< system.cpu0.l2cache.blocked::no_mshrs 375 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 346 # number of cycles access was blocked
909c912
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 67.901333 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 72.598266 # average number of cycles each access was blocked
913,978c916,979
< system.cpu0.l2cache.writebacks::writebacks 214094 # number of writebacks
< system.cpu0.l2cache.writebacks::total 214094 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7763 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 7763 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3115 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 3115 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10878 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 10878 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10878 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 10878 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 986 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86578 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 87737 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 512278 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 512278 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27941 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27941 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17958 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17958 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 2 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43237 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 43237 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 986 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 129815 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 130974 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 986 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 129815 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 512278 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 643252 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2638999 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2121502252 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2149486002 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21334624793 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21334624793 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 476101816 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 476101816 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 237455029 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 237455029 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 89000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 89000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1189409987 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1189409987 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2638999 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3310912239 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 3338895989 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2638999 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3310912239 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21334624793 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 24673520782 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6176243748 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6176243748 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4587514507 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4587514507 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10763758255 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10763758255 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034839 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034161 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.writebacks::writebacks 220063 # number of writebacks
> system.cpu0.l2cache.writebacks::total 220063 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 8315 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 8315 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3034 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 3034 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11349 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 11349 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11349 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 11349 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 906 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 138 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 88686 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 89730 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 534906 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 534906 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27960 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27960 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17929 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17929 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43491 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 43491 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 906 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 138 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 132177 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 133221 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 906 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 138 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 132177 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 534906 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 668127 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2265999 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2160848492 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2188282991 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21648732719 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21648732719 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 481473058 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481473058 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 238593946 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 238593946 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 91000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 91000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1198815233 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1198815233 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2265999 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3359663725 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 3387098224 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2265999 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3359663725 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21648732719 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 25035830943 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6180670251 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6180670251 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4594924508 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4594924508 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10775594759 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10775594759 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034144 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.033396 # mshr miss rate for ReadReq accesses
981,995c982,994
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.857849 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.857849 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888922 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888922 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160439 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160439 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046153 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856775 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856775 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.881465 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.881465 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.154795 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154795 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.044889 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for overall accesses
997,1020c996,1019
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226671 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24503.941556 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24499.196485 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41646.576259 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17039.541033 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17039.541033 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13222.799254 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13222.799254 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 44500 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 44500 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27509.077572 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27509.077572 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25492.815284 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38357.472316 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225125 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24365.159010 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24387.417709 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40472.031944 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17220.066452 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17220.066452 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13307.710748 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13307.710748 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27564.673910 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27564.673910 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25424.656953 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37471.664733 # average overall mshr miss latency
1028,1055c1027,1054
< system.cpu0.toL2Bus.trans_dist::ReadReq 2765429 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 2670282 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 517951 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 696439 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 70465 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42615 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 93717 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 291656 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 282057 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3974309 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393187 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11845 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168040 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 6547381 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127177856 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86874167 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17764 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 315068 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 214384855 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 1083965 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 4385734 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 5.219720 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.414057 # Request fanout histogram
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 2861093 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 2792980 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28855 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28855 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 541643 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 731101 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 68486 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42622 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 93982 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 302729 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 293421 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 4148051 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2491359 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12339 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 183942 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 6835691 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 132737600 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90757533 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17524 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 340220 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 223852877 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 1093341 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 4548807 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 5.213001 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.409428 # Request fanout histogram
1062,1063c1061,1062
< system.cpu0.toL2Bus.snoop_fanout::5 3422100 78.03% 78.03% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::6 963634 21.97% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::5 3579907 78.70% 78.70% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::6 968900 21.30% 100.00% # Request fanout histogram
1067,1068c1066,1067
< system.cpu0.toL2Bus.snoop_fanout::total 4385734 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 2275890990 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 4548807 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 2378574445 # Layer occupancy (ticks)
1070c1069
< system.cpu0.toL2Bus.snoopLayer0.occupancy 119346000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 119537998 # Layer occupancy (ticks)
1072c1071
< system.cpu0.toL2Bus.respLayer0.occupancy 2982392646 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 3112636730 # Layer occupancy (ticks)
1074c1073
< system.cpu0.toL2Bus.respLayer1.occupancy 1235371968 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1291088389 # Layer occupancy (ticks)
1076c1075
< system.cpu0.toL2Bus.respLayer2.occupancy 7407493 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 7963988 # Layer occupancy (ticks)
1078c1077
< system.cpu0.toL2Bus.respLayer3.occupancy 89292476 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 98908477 # Layer occupancy (ticks)
1080,1084c1079,1083
< system.cpu1.branchPred.lookups 4040174 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 2339682 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 248924 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 2652147 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 1629183 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 3448752 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 1941981 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 196391 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 2221819 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 1396869 # Number of BTB hits
1086,1088c1085,1087
< system.cpu1.branchPred.BTBHitPct 61.428835 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 794888 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 55483 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 62.870513 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 715789 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 52420 # Number of incorrect RAS predictions.
1112,1115c1111,1114
< system.cpu1.dtb.read_hits 4061400 # DTB read hits
< system.cpu1.dtb.read_misses 20326 # DTB read misses
< system.cpu1.dtb.write_hits 3327397 # DTB write hits
< system.cpu1.dtb.write_misses 1493 # DTB write misses
---
> system.cpu1.dtb.read_hits 3432223 # DTB read hits
> system.cpu1.dtb.read_misses 19764 # DTB read misses
> system.cpu1.dtb.write_hits 2826731 # DTB write hits
> system.cpu1.dtb.write_misses 1392 # DTB write misses
1120,1122c1119,1121
< system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 130 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 1674 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch
1124,1126c1123,1125
< system.cpu1.dtb.perms_faults 275 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 4081726 # DTB read accesses
< system.cpu1.dtb.write_accesses 3328890 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 3451987 # DTB read accesses
> system.cpu1.dtb.write_accesses 2828123 # DTB write accesses
1128,1130c1127,1129
< system.cpu1.dtb.hits 7388797 # DTB hits
< system.cpu1.dtb.misses 21819 # DTB misses
< system.cpu1.dtb.accesses 7410616 # DTB accesses
---
> system.cpu1.dtb.hits 6258954 # DTB hits
> system.cpu1.dtb.misses 21156 # DTB misses
> system.cpu1.dtb.accesses 6280110 # DTB accesses
1152,1153c1151,1152
< system.cpu1.itb.inst_hits 7665717 # ITB inst hits
< system.cpu1.itb.inst_misses 2240 # ITB inst misses
---
> system.cpu1.itb.inst_hits 6653879 # ITB inst hits
> system.cpu1.itb.inst_misses 1856 # ITB inst misses
1162c1161
< system.cpu1.itb.flush_entries 1155 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 882 # Number of entries that have been flushed from TLB
1166c1165
< system.cpu1.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 1128 # Number of TLB faults due to permissions restrictions
1169,1173c1168,1172
< system.cpu1.itb.inst_accesses 7667957 # ITB inst accesses
< system.cpu1.itb.hits 7665717 # DTB hits
< system.cpu1.itb.misses 2240 # DTB misses
< system.cpu1.itb.accesses 7667957 # DTB accesses
< system.cpu1.numCycles 40520229 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 6655735 # ITB inst accesses
> system.cpu1.itb.hits 6653879 # DTB hits
> system.cpu1.itb.misses 1856 # DTB misses
> system.cpu1.itb.accesses 6655735 # DTB accesses
> system.cpu1.numCycles 36145472 # number of cpu cycles simulated
1176,1182c1175,1181
< system.cpu1.committedInsts 15863154 # Number of instructions committed
< system.cpu1.committedOps 19391289 # Number of ops (including micro ops) committed
< system.cpu1.discardedOps 1555006 # Number of ops (including micro ops) which were discarded before commit
< system.cpu1.numFetchSuspends 2808 # Number of times Execute suspended instruction fetching
< system.cpu1.quiesceCycles 5646190749 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.cpi 2.554361 # CPI: cycles per instruction
< system.cpu1.ipc 0.391487 # IPC: instructions per cycle
---
> system.cpu1.committedInsts 13424165 # Number of instructions committed
> system.cpu1.committedOps 16401555 # Number of ops (including micro ops) committed
> system.cpu1.discardedOps 1287407 # Number of ops (including micro ops) which were discarded before commit
> system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching
> system.cpu1.quiesceCycles 5652095397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.cpi 2.692568 # CPI: cycles per instruction
> system.cpu1.ipc 0.371393 # IPC: instructions per cycle
1184,1271c1183,1270
< system.cpu1.kern.inst.quiesce 2810 # number of quiesce instructions executed
< system.cpu1.tickCycles 29462484 # Number of cycles that the object actually ticked
< system.cpu1.idleCycles 11057745 # Total number of cycles that the object has spent stopped
< system.cpu1.dcache.tags.replacements 188500 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 474.724355 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 6998456 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 188865 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 37.055336 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.inst 474.724355 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927196 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.927196 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 14854828 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 14854828 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.inst 3752021 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 3752021 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051608 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3051608 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88860 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 88860 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69213 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 69213 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.inst 6803629 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 6803629 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.inst 6803629 # number of overall hits
< system.cpu1.dcache.overall_hits::total 6803629 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.inst 182037 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 182037 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.inst 139457 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 139457 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5164 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 5164 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23160 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23160 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.inst 321494 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 321494 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.inst 321494 # number of overall misses
< system.cpu1.dcache.overall_misses::total 321494 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2747896424 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2747896424 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3339347493 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 3339347493 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93721501 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 93721501 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540094758 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 540094758 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 317500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 317500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.inst 6087243917 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 6087243917 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.inst 6087243917 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 6087243917 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3934058 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 3934058 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3191065 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 3191065 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94024 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 94024 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92373 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 92373 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.inst 7125123 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 7125123 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.inst 7125123 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 7125123 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046272 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.046272 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043702 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.043702 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054922 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054922 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250723 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250723 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045121 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.045121 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045121 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.045121 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15095.263183 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15095.263183 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23945.355866 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 23945.355866 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18149.012587 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18149.012587 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23320.153627 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23320.153627 # average StoreCondReq miss latency
---
> system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed
> system.cpu1.tickCycles 26236459 # Number of cycles that the object actually ticked
> system.cpu1.idleCycles 9909013 # Total number of cycles that the object has spent stopped
> system.cpu1.dcache.tags.replacements 149765 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 476.829408 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 5935391 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 150124 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 39.536590 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 107725830000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.inst 476.829408 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.931307 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.931307 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 12574886 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 12574886 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.inst 3167382 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 3167382 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.inst 2587127 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 2587127 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 79870 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 79870 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 60510 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 60510 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.inst 5754509 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 5754509 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.inst 5754509 # number of overall hits
> system.cpu1.dcache.overall_hits::total 5754509 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.inst 151161 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 151161 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.inst 116953 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 116953 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5079 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 5079 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 22818 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 22818 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.inst 268114 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 268114 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.inst 268114 # number of overall misses
> system.cpu1.dcache.overall_misses::total 268114 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2359046468 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2359046468 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3063915205 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 3063915205 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93260000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 93260000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 534664798 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 534664798 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 106500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 106500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.inst 5422961673 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 5422961673 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.inst 5422961673 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 5422961673 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3318543 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 3318543 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.inst 2704080 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 2704080 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 84949 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 84949 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 83328 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 83328 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.inst 6022623 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 6022623 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.inst 6022623 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 6022623 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045550 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.045550 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043251 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.043251 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.059789 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.059789 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.273834 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273834 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044518 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.044518 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044518 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.044518 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15606.184585 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.184585 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26197.833360 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 26197.833360 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18361.882260 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18361.882260 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23431.711719 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.711719 # average StoreCondReq miss latency
1274,1277c1273,1276
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 18934.238017 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 18934.238017 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20226.327879 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 20226.327879 # average overall miss latency
1286,1347c1285,1346
< system.cpu1.dcache.writebacks::writebacks 115754 # number of writebacks
< system.cpu1.dcache.writebacks::total 115754 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15456 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 15456 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49471 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 49471 # number of WriteReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64927 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 64927 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64927 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 64927 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166581 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 166581 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89986 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 89986 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5164 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5164 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23160 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23160 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256567 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 256567 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256567 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 256567 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204876516 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204876516 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1996537354 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1996537354 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83385499 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83385499 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492548242 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492548242 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 303500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 303500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4201413870 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4201413870 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4201413870 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4201413870 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329634997 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329634997 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202961999 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202961999 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532596996 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532596996 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042343 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042343 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028199 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028199 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054922 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054922 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250723 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250723 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.036009 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.036009 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13236.062432 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13236.062432 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22187.199720 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22187.199720 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16147.463013 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.463013 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21267.195250 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21267.195250 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 93707 # number of writebacks
> system.cpu1.dcache.writebacks::total 93707 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 11593 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 11593 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 39187 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 39187 # number of WriteReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.inst 50780 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 50780 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.inst 50780 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 50780 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 139568 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 139568 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 77766 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 77766 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5079 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5079 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 22818 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 22818 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.inst 217334 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 217334 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.inst 217334 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 217334 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 1914681986 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914681986 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1867013423 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1867013423 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83091000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83091000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 487833202 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 487833202 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 100500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 100500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 3781695409 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3781695409 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 3781695409 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 3781695409 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 327471996 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 327471996 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 198424999 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 198424999 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 525896995 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 525896995 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042057 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042057 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028759 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028759 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.059789 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059789 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.273834 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273834 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.036086 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.036086 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13718.631678 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13718.631678 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24008.093807 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24008.093807 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16359.716480 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16359.716480 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21379.314664 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21379.314664 # average StoreCondReq mshr miss latency
1350,1353c1349,1352
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency
1361,1369c1360,1368
< system.cpu1.icache.tags.replacements 893030 # number of replacements
< system.cpu1.icache.tags.tagsinuse 499.459009 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 6770083 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 893542 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 7.576681 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 71221486500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459009 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 827152 # number of replacements
> system.cpu1.icache.tags.tagsinuse 499.447245 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 5824947 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 827664 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 7.037816 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 71343314500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.447245 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975483 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.975483 # Average percentage of cache occupancy
1371,1372c1370,1372
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 469 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
1374,1411c1374,1411
< system.cpu1.icache.tags.tag_accesses 16220792 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 16220792 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 6770083 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 6770083 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 6770083 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 6770083 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 6770083 # number of overall hits
< system.cpu1.icache.overall_hits::total 6770083 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 893542 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 893542 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 893542 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 893542 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 893542 # number of overall misses
< system.cpu1.icache.overall_misses::total 893542 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7266670468 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7266670468 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7266670468 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7266670468 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7266670468 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7266670468 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 7663625 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 7663625 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 7663625 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 7663625 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 7663625 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 7663625 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116595 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.116595 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116595 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.116595 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116595 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.116595 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8132.433023 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 8132.433023 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 8132.433023 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 8132.433023 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 14132886 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 14132886 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 5824947 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 5824947 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 5824947 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 5824947 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 5824947 # number of overall hits
> system.cpu1.icache.overall_hits::total 5824947 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 827664 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 827664 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 827664 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 827664 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 827664 # number of overall misses
> system.cpu1.icache.overall_misses::total 827664 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6712177482 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 6712177482 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 6712177482 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 6712177482 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 6712177482 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 6712177482 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 6652611 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 6652611 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 6652611 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 6652611 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 6652611 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 6652611 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124412 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.124412 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124412 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.124412 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124412 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.124412 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8109.785471 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 8109.785471 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 8109.785471 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 8109.785471 # average overall miss latency
1420,1447c1420,1447
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893542 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 893542 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 893542 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 893542 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 893542 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 893542 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923954530 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923954530 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923954530 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 5923954530 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923954530 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 5923954530 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10589750 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10589750 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10589750 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 10589750 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.743795 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 827664 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 827664 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 827664 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 827664 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 827664 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 827664 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5467532518 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5467532518 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5467532518 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5467532518 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5467532518 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5467532518 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10038000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10038000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10038000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 10038000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124412 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.124412 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.124412 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6605.980830 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency
1453,1456c1453,1456
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7064659 # number of hwpf identified
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40510 # number of hwpf that were already in mshr
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914419 # number of hwpf that were already in the cache
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1409 # number of hwpf that were already in the prefetch queue
---
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6453687 # number of hwpf identified
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 29592 # number of hwpf that were already in mshr
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6340817 # number of hwpf that were already in the cache
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 898 # number of hwpf that were already in the prefetch queue
1458,1460c1458,1460
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2627 # number of hwpf removed because MSHR allocated
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105694 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724613 # number of hwpf spanning a virtual page
---
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2376 # number of hwpf removed because MSHR allocated
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 80004 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 668025 # number of hwpf spanning a virtual page
1462,1466c1462,1466
< system.cpu1.l2cache.tags.replacements 80002 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15534.005683 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 1138706 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 95380 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 11.938624 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.tags.replacements 52740 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15520.178150 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 1029232 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 68128 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 15.107327 # Average number of references to valid blocks.
1468,1599c1468,1599
< system.cpu1.l2cache.tags.occ_blocks::writebacks 6881.050205 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.485106 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.098583 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2338.762949 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6287.608842 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.419986 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001617 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142747 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383765 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.948120 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10071 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6676 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3263 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 237 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1869 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.614685 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.321838 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 21370209 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 21370209 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22701 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2439 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993088 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 1018228 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 115754 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 115754 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 740 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 740 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27796 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 27796 # number of ReadExReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22701 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2439 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 1020884 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 1046024 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22701 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2439 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 1020884 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 1046024 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 604 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.inst 72199 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 73046 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28140 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 28140 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22420 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22420 # number of SCUpgradeReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32240 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 32240 # number of ReadExReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 604 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 104439 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 105286 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 604 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 104439 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 105286 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13239000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4899500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1623706138 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 1641844638 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 531483393 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 531483393 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440502566 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440502566 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 296000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 296000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1126750383 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1126750383 # number of ReadExReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13239000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4899500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2750456521 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 2768595021 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13239000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4899500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2750456521 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 2768595021 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23305 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2682 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1065287 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 1091274 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 115754 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 115754 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29950 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 29950 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23160 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23160 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60036 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 60036 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23305 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2682 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 1125323 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 1151310 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23305 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2682 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 1125323 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 1151310 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090604 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067774 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.066936 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.939566 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.939566 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968048 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968048 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.537011 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.537011 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090604 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092808 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.091449 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090604 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092808 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.091449 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20162.551440 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22489.316168 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22476.858938 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18887.114179 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18887.114179 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19647.750491 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19647.750491 # average SCUpgradeReq miss latency
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 6901.586978 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.255538 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.084140 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2337.993929 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6253.257565 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.421239 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001664 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142700 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.381669 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.947276 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8859 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 87 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6442 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 153 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1624 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 7082 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 51 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 256 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1161 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5025 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.540710 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005310 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.393188 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 19285639 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 19285639 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22569 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2289 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.inst 905837 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 930695 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 93707 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 93707 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1549 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 1549 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 533 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 533 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 18299 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 18299 # number of ReadExReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22569 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2289 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 924136 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 948994 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22569 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2289 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 924136 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 948994 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 704 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 245 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.inst 66474 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 67423 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 27781 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 27781 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22285 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22285 # number of SCUpgradeReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 30137 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 30137 # number of ReadExReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 704 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 245 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 96611 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 97560 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 704 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 245 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 96611 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 97560 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14471499 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4810998 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1464118881 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 1483401378 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 523592810 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 523592810 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 437167020 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 437167020 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 97500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 97500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1078871611 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1078871611 # number of ReadExReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14471499 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4810998 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2542990492 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 2562272989 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14471499 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4810998 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2542990492 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 2562272989 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23273 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2534 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 972311 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 998118 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 93707 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 93707 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29330 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 29330 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 22818 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 22818 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 48436 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 48436 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23273 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2534 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 1020747 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 1046554 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23273 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2534 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 1020747 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 1046554 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.096685 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.068367 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.067550 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.947187 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947187 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.976641 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.976641 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.622202 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.622202 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.096685 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094647 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.093220 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.096685 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094647 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.093220 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19636.726531 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22025.436727 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22001.414621 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18847.154890 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18847.154890 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19617.097599 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.097599 # average SCUpgradeReq miss latency
1602,1612c1602,1612
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34948.833220 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34948.833220 # average ReadExReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20162.551440 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26335.530989 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 26295.946479 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20162.551440 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26335.530989 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 26295.946479 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 4629 # number of cycles access was blocked
---
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35798.905365 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35798.905365 # average ReadExReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19636.726531 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26321.956009 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 26263.560773 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19636.726531 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26321.956009 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 26263.560773 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 2801 # number of cycles access was blocked
1614c1614
< system.cpu1.l2cache.blocked::no_mshrs 159 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 79 # number of cycles access was blocked
1616c1616
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29.113208 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 35.455696 # average number of cycles each access was blocked
1620,1683c1620,1683
< system.cpu1.l2cache.writebacks::writebacks 38442 # number of writebacks
< system.cpu1.l2cache.writebacks::total 38442 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1604 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 1604 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 322 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 322 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1926 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 1926 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1926 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 1926 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 604 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 243 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 70595 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 71442 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 105694 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 105694 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28140 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28140 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22420 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22420 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 31918 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 31918 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 604 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 243 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 102513 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 103360 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 604 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 243 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 102513 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 105694 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 209054 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3198500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1098179235 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1110385737 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2958247424 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2958247424 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 404415795 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 404415795 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 308218727 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308218727 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 247000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 247000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 862164082 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 862164082 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3198500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1960343317 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 1972549819 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3198500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1960343317 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2958247424 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 4930797243 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316625253 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316625253 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 186937501 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 186937501 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 503562754 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 503562754 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066269 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065467 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.writebacks::writebacks 30368 # number of writebacks
> system.cpu1.l2cache.writebacks::total 30368 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 950 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 950 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 295 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 295 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1245 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1245 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 1245 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 704 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 245 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 65524 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 66473 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 80004 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 27781 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27781 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22285 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22285 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 29842 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 29842 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 704 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 245 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 95366 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 96315 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 704 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 245 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 95366 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 176319 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3095998 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 981688737 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 994327236 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2522312930 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 396174942 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 396174942 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 306073762 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306073762 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 76500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 76500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 831450098 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 831450098 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3095998 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1813138835 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 1825777334 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3095998 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1813138835 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 4348090264 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 313994504 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 313994504 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 182561501 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 182561501 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 496556005 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 496556005 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.067390 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.066598 # mshr miss rate for ReadReq accesses
1686,1698c1686,1698
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.939566 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.939566 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968048 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968048 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.531648 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.531648 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089776 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.947187 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947187 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.976641 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.976641 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.616112 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.616112 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.092031 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for overall accesses
1700,1710c1700,1710
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181579 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15556.048375 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15542.478332 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27988.792401 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14371.563433 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14371.563433 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13747.490054 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13747.490054 # average SCUpgradeReq mshr miss latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168476 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14982.124672 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14958.362583 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31527.335258 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14260.643677 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14260.643677 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13734.519273 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13734.519273 # average SCUpgradeReq mshr miss latency
1713,1723c1713,1723
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27011.845416 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27011.845416 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19084.266825 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23586.237254 # average overall mshr miss latency
---
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27861.741773 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27861.741773 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18956.313492 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24660.361413 # average overall mshr miss latency
1731,1758c1731,1758
< system.cpu1.toL2Bus.trans_dist::ReadReq 1582615 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 1137834 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 2120 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 2120 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 115754 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 151048 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 84372 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41116 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 85179 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 76804 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 64396 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787314 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 769072 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6988 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51360 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2614734 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57194048 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24925415 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10728 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93220 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 82223411 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 838592 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 2085067 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 5.363773 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.481085 # Request fanout histogram
---
> system.cpu1.toL2Bus.trans_dist::ReadReq 1502965 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 1041469 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 2098 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 2098 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 93707 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 114724 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 83933 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40744 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 84523 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 65298 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 52790 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1655558 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 667978 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6105 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48641 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2378282 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 52977856 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21039827 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10136 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93092 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 74120911 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 816365 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 1934720 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 5.382054 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.485890 # Request fanout histogram
1765,1766c1765,1766
< system.cpu1.toL2Bus.snoop_fanout::5 1326575 63.62% 63.62% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::6 758492 36.38% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::5 1195552 61.79% 61.79% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::6 739168 38.21% 100.00% # Request fanout histogram
1770,1771c1770,1771
< system.cpu1.toL2Bus.snoop_fanout::total 2085067 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 782771935 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 1934720 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 695166718 # Layer occupancy (ticks)
1773c1773
< system.cpu1.toL2Bus.snoopLayer0.occupancy 78513000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 78719500 # Layer occupancy (ticks)
1775c1775
< system.cpu1.toL2Bus.respLayer0.occupancy 1341710719 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 1243267482 # Layer occupancy (ticks)
1777c1777
< system.cpu1.toL2Bus.respLayer1.occupancy 381436893 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 322631890 # Layer occupancy (ticks)
1779c1779
< system.cpu1.toL2Bus.respLayer2.occupancy 4307996 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 3571998 # Layer occupancy (ticks)
1781c1781
< system.cpu1.toL2Bus.respLayer3.occupancy 28057498 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 25370995 # Layer occupancy (ticks)
1783,1788c1783,1788
< system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
< system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59407 # Transaction distribution
< system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
< system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 31020 # Transaction distribution
> system.iobus.trans_dist::ReadResp 31020 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59447 # Transaction distribution
> system.iobus.trans_dist::WriteResp 23223 # Transaction distribution
> system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56686 # Packet count per connected master and slave (bytes)
1809c1809
< system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 108000 # Packet count per connected master and slave (bytes)
1812,1813c1812,1813
< system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 180934 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71630 # Cumulative packet size per connected master and slave (bytes)
1834c1834
< system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 162880 # Cumulative packet size per connected master and slave (bytes)
1837,1838c1837,1838
< system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 40158000 # Layer occupancy (ticks)
1878c1878
< system.iobus.reqLayer27.occupancy 326658321 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 347075142 # Layer occupancy (ticks)
1882c1882
< system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 84777000 # Layer occupancy (ticks)
1884c1884
< system.iobus.respLayer3.occupancy 36824131 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36822606 # Layer occupancy (ticks)
1886,1887c1886,1887
< system.iocache.tags.replacements 36417 # number of replacements
< system.iocache.tags.tagsinuse 0.992159 # Cycle average of tags in use
---
> system.iocache.tags.replacements 36433 # number of replacements
> system.iocache.tags.tagsinuse 0.995239 # Cycle average of tags in use
1889c1889
< system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks.
1891,1894c1891,1894
< system.iocache.tags.warmup_cycle 268855800000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 0.992159 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.062010 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.062010 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 269184120000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 0.995239 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.062202 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.062202 # Average percentage of cache occupancy
1898,1901c1898,1899
< system.iocache.tags.tag_accesses 328467 # Number of tag accesses
< system.iocache.tags.data_accesses 328467 # Number of data accesses
< system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
< system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
---
> system.iocache.tags.tag_accesses 328203 # Number of tag accesses
> system.iocache.tags.data_accesses 328203 # Number of data accesses
1904,1905c1902,1903
< system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses
< system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses
---
> system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
1910,1915c1908,1915
< system.iocache.ReadReq_miss_latency::realview.ide 31254127 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 31254127 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 31254127 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 31254127 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 31254127 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 31254127 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 30315377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 30315377 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9644186159 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 9644186159 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 30315377 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 30315377 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 30315377 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 30315377 # number of overall miss cycles
1918,1919c1918,1919
< system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses)
---
> system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
1926,1927c1926,1927
< system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses
---
> system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1932,1938c1932,1940
< system.iocache.ReadReq_avg_miss_latency::realview.ide 128617.806584 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 128617.806584 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 128617.806584 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 128617.806584 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 124754.637860 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 124754.637860 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266237.471262 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 266237.471262 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 124754.637860 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 124754.637860 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 57278 # number of cycles access was blocked
1940c1942
< system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 7269 # number of cycles access was blocked
1942c1944
< system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 7.879763 # average number of cycles each access was blocked
1944c1946
< system.iocache.fast_writes 36224 # number of fast writes performed
---
> system.iocache.fast_writes 0 # number of fast writes performed
1945a1948,1949
> system.iocache.writebacks::writebacks 36190 # number of writebacks
> system.iocache.writebacks::total 36190 # number of writebacks
1947a1952,1953
> system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
> system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
1952,1959c1958,1965
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 18617627 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 18617627 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2261621825 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2261621825 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 18617627 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 18617627 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 18617627 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 18617627 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 17678377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 17678377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7760326371 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7760326371 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 17678377 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 17678377 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 17678377 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 17678377 # number of overall MSHR miss cycles
1961a1968,1969
> system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1966,1973c1974,1981
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76615.748971 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 76615.748971 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72750.522634 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72750.522634 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214231.624641 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214231.624641 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency
1975,1979c1983,1987
< system.l2c.tags.replacements 151810 # number of replacements
< system.l2c.tags.tagsinuse 64480.586594 # Cycle average of tags in use
< system.l2c.tags.total_refs 529933 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 216565 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.446993 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 150396 # number of replacements
> system.l2c.tags.tagsinuse 64479.883220 # Cycle average of tags in use
> system.l2c.tags.total_refs 522727 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 215317 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.427709 # Average number of references to valid blocks.
1981,2053c1989,2062
< system.l2c.tags.occ_blocks::writebacks 12374.174406 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831156 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030524 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 3874.361594 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42727.383721 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.891665 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 757.615436 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4654.298093 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.188815 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.059118 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.651968 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.011560 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071019 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.983896 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 46322 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 18386 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 6596 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 39440 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 2604 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 15495 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.706818 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.280548 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 6644341 # Number of tag accesses
< system.l2c.tags.data_accesses 6644341 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 563 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 116 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 36701 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207577 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 129 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 56 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 11433 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45418 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 301993 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 252536 # number of Writeback hits
< system.l2c.Writeback_hits::total 252536 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.inst 11942 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.inst 830 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 12772 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.inst 205 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.inst 179 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.inst 3525 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.inst 1107 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 4632 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 563 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 116 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 40226 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 207577 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 129 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 56 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 12540 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 45418 # number of demand (read+write) hits
< system.l2c.demand_hits::total 306625 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 563 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 116 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 40226 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 207577 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 129 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 56 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 12540 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 45418 # number of overall hits
< system.l2c.overall_hits::total 306625 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses
---
> system.l2c.tags.occ_blocks::writebacks 12469.492368 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 93.733463 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999899 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 3818.005633 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42810.602787 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.718540 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 732.215158 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4549.115372 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.190269 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001430 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.058258 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.653238 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.011173 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.069414 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.983885 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 47457 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 17396 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 475 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 6086 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 40896 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 67 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 270 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 2310 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 14797 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.724136 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.265442 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 6561930 # Number of tag accesses
> system.l2c.tags.data_accesses 6561930 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 576 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 131 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 39519 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 221242 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 94 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 19 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 6900 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 25945 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 294426 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 250431 # number of Writeback hits
> system.l2c.Writeback_hits::total 250431 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.inst 11782 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.inst 481 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 12263 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.inst 184 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.inst 192 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.inst 3646 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.inst 908 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 4554 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 576 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 131 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 43165 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 221242 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 94 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 19 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 7808 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 25945 # number of demand (read+write) hits
> system.l2c.demand_hits::total 298980 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 576 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 131 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 43165 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 221242 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 94 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 19 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 7808 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 25945 # number of overall hits
> system.l2c.overall_hits::total 298980 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 161 # number of ReadReq misses
2055,2070c2064,2079
< system.l2c.ReadReq_misses::cpu0.inst 11286 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 1852 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18208 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 199810 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.inst 9028 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 11693 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.inst 461 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.inst 1254 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.inst 7011 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.inst 6410 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 13421 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses
---
> system.l2c.ReadReq_misses::cpu0.inst 11256 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 169617 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 1341 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 17501 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 199885 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.inst 9580 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.inst 2241 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 11821 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.inst 527 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.inst 1214 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1741 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.inst 6969 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.inst 6429 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 13398 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 161 # number of demand (read+write) misses
2072,2078c2081,2087
< system.l2c.demand_misses::cpu0.inst 18297 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 8262 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 18208 # number of demand (read+write) misses
< system.l2c.demand_misses::total 213231 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses
---
> system.l2c.demand_misses::cpu0.inst 18225 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 169617 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 7770 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 17501 # number of demand (read+write) misses
> system.l2c.demand_misses::total 213283 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 161 # number of overall misses
2080,2086c2089,2095
< system.l2c.overall_misses::cpu0.inst 18297 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 168297 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 8262 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 18208 # number of overall misses
< system.l2c.overall_misses::total 213231 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles
---
> system.l2c.overall_misses::cpu0.inst 18225 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 169617 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 7770 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 17501 # number of overall misses
> system.l2c.overall_misses::total 213283 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 12824000 # number of ReadReq miss cycles
2088,2103c2097,2112
< system.l2c.ReadReq_miss_latency::cpu0.inst 955847998 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1150500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 151717498 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 21276600608 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.inst 10528075 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.inst 2736385 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 13264460 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1131453 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1006958 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 2138411 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.inst 592519659 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.inst 475914481 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 1068434140 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu0.inst 957656246 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 597000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 113197750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 21264707667 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.inst 10249624 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.inst 2389898 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 12639522 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1315451 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1074955 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 2390406 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.inst 593841904 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.inst 477642745 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 1071484649 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 12824000 # number of demand (read+write) miss cycles
2105,2111c2114,2120
< system.l2c.demand_miss_latency::cpu0.inst 1548367657 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 1150500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 627631979 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 22345034748 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 1551498150 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 597000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 590840495 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 22336192316 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 12824000 # number of overall miss cycles
2113,2190c2122,2199
< system.l2c.overall_miss_latency::cpu0.inst 1548367657 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 1150500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 627631979 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 22345034748 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 714 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 117 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 47987 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 375874 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 144 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 56 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 13285 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63626 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 501803 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 252536 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 252536 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.inst 20970 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.inst 3495 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 24465 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.inst 666 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.inst 1433 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2099 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.inst 10536 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.inst 7517 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 18053 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 714 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 117 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 58523 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 375874 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 144 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 56 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 20802 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63626 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 519856 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 714 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 117 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 58523 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 375874 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 144 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 56 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 20802 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63626 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 519856 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008547 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.235189 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.139405 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.398184 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430520 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.762518 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.477948 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.692192 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.875087 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.817056 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.inst 0.665433 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.inst 0.852734 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.743422 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.008547 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.312646 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.397173 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.410173 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.008547 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.312646 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.397173 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.410173 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency
---
> system.l2c.overall_miss_latency::cpu0.inst 1551498150 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 597000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 590840495 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 22336192316 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 737 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 132 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 50775 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 390859 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 102 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 19 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 8241 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 43446 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 494311 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 250431 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 250431 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.inst 21362 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.inst 2722 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 24084 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.inst 711 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.inst 1406 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2117 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.inst 10615 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.inst 7337 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 17952 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 737 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 132 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 61390 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 390859 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 102 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 19 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 15578 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 43446 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 512263 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 737 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 132 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 61390 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 390859 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 102 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 19 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 15578 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 43446 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 512263 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007576 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.221684 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.162723 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.404371 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.448460 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.823292 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.490824 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.741210 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.863442 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.822390 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.inst 0.656524 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.inst 0.876244 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.746324 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.007576 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.296872 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.498780 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.416354 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.007576 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.296872 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.498780 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.416354 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average ReadReq miss latency
2192,2207c2201,2216
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84693.248095 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76700 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81920.895248 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 106484.162995 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1166.158064 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1026.786116 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1134.393227 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2454.344902 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 802.996810 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1246.886880 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84512.859649 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74245.628861 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 79609.130467 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85079.623845 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74625 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84412.938106 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 106384.709543 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1069.898121 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1066.442660 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 1069.243042 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2496.111954 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 885.465404 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1373.007467 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 85211.924810 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74295.029554 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 79973.477310 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average overall miss latency
2209,2215c2218,2224
< system.l2c.demand_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 104792.618090 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 85130.213992 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74625 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 76041.247748 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 104725.610180 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average overall miss latency
2217,2223c2226,2232
< system.l2c.overall_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 104792.618090 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 845 # number of cycles access was blocked
---
> system.l2c.overall_avg_miss_latency::cpu0.inst 85130.213992 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74625 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 76041.247748 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 104725.610180 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2225c2234
< system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2227c2236
< system.l2c.avg_blocked_cycles::no_mshrs 32.500000 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2231,2233c2240,2242
< system.l2c.writebacks::writebacks 112127 # number of writebacks
< system.l2c.writebacks::total 112127 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits
---
> system.l2c.writebacks::writebacks 110752 # number of writebacks
> system.l2c.writebacks::total 110752 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits
2235c2244
< system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
---
> system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
2237c2246
< system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits
---
> system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits
2239c2248
< system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 161 # number of ReadReq MSHR misses
2241,2256c2250,2265
< system.l2c.ReadReq_mshr_misses::cpu0.inst 11286 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 1852 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 199809 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9028 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 11693 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 461 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1254 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1715 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.inst 7011 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.inst 6410 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 13421 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 11256 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 1341 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 199884 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9580 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2241 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 11821 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 527 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1214 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1741 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.inst 6969 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.inst 6429 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 13398 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 161 # number of demand (read+write) MSHR misses
2258,2264c2267,2273
< system.l2c.demand_mshr_misses::cpu0.inst 18297 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 8262 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 213230 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 18225 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 7770 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 213282 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 161 # number of overall MSHR misses
2266,2272c2275,2281
< system.l2c.overall_mshr_misses::cpu0.inst 18297 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 8262 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 213230 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of ReadReq MSHR miss cycles
---
> system.l2c.overall_mshr_misses::cpu0.inst 18225 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 7770 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 213282 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of ReadReq MSHR miss cycles
2274,2289c2283,2298
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 815475498 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 965000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 128728998 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 18816537858 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91196953 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26828647 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 118025600 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4664957 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12607247 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 17272204 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 505062337 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 394979019 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 900041356 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 817788246 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 500000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 96492250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 18800812917 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 97817994 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 22626723 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 120444717 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 5423023 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12163710 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 17586733 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 506879094 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 396754755 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 903633849 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of demand (read+write) MSHR miss cycles
2291,2297c2300,2306
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1320537835 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 965000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 523708017 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 19716579214 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1324667340 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 500000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 493247005 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 19704446766 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of overall MSHR miss cycles
2299,2347c2308,2356
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1320537835 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 965000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 523708017 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 19716579214 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518590247 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263108750 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 5781698997 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4096001500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150494000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4246495500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614591747 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413602750 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 10028194497 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235189 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.139405 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.398182 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430520 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.762518 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.477948 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.692192 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.875087 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817056 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.665433 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.852734 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.743422 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.410171 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.410171 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency
---
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1324667340 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 500000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 493247005 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 19704446766 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5522428749 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 260648000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 5783076749 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4102579499 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 146450000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4249029499 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9625008248 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 407098000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10032106248 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.221684 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.162723 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.404369 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.448460 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.823292 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.490824 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.741210 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.863442 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.822390 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.656524 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.876244 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.746324 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.416353 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.416353 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average ReadReq mshr miss latency
2349,2364c2358,2373
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72255.493355 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69508.098272 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 94172.624146 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10101.567678 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10067.034522 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.697084 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10119.212581 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10053.625997 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.255977 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72038.558979 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61619.191732 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 67062.167946 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72653.539979 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71955.443699 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 94058.618584 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.646555 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10096.708166 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10189.046358 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10290.366224 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10019.530478 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10101.512349 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72733.404219 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61713.292114 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 67445.428348 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency
2366,2372c2375,2381
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency
2374,2379c2383,2388
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency
2390,2394c2399,2403
< system.membus.trans_dist::ReadReq 238091 # Transaction distribution
< system.membus.trans_dist::ReadResp 238091 # Transaction distribution
< system.membus.trans_dist::WriteReq 30933 # Transaction distribution
< system.membus.trans_dist::WriteResp 30933 # Transaction distribution
< system.membus.trans_dist::Writeback 112127 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 238185 # Transaction distribution
> system.membus.trans_dist::ReadResp 238185 # Transaction distribution
> system.membus.trans_dist::WriteReq 30953 # Transaction distribution
> system.membus.trans_dist::WriteResp 30953 # Transaction distribution
> system.membus.trans_dist::Writeback 146942 # Transaction distribution
2397,2402c2406,2411
< system.membus.trans_dist::UpgradeReq 79652 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 39985 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 13516 # Transaction distribution
< system.membus.trans_dist::ReadExReq 30363 # Transaction distribution
< system.membus.trans_dist::ReadExResp 13313 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::UpgradeReq 78292 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 39832 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 13662 # Transaction distribution
> system.membus.trans_dist::ReadExReq 30241 # Transaction distribution
> system.membus.trans_dist::ReadExResp 13298 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 108000 # Packet count per connected master and slave (bytes)
2404,2410c2413,2419
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13576 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704934 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 826518 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 899224 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13634 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 701758 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 823430 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 932326 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162880 # Cumulative packet size per connected master and slave (bytes)
2412,2419c2421,2428
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27152 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21038188 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 21229406 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 23548702 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 123399 # Total snoops (count)
< system.membus.snoop_fanout::samples 498406 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27268 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 20926892 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 21118256 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 25753712 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 122070 # Total snoops (count)
> system.membus.snoop_fanout::samples 531658 # Request fanout histogram
2424c2433
< system.membus.snoop_fanout::1 498406 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 531658 100.00% 100.00% # Request fanout histogram
2429,2430c2438,2439
< system.membus.snoop_fanout::total 498406 # Request fanout histogram
< system.membus.reqLayer0.occupancy 87864494 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 531658 # Request fanout histogram
> system.membus.reqLayer0.occupancy 88755994 # Layer occupancy (ticks)
2434c2443
< system.membus.reqLayer2.occupancy 11666999 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11894500 # Layer occupancy (ticks)
2436c2445
< system.membus.reqLayer5.occupancy 1620379248 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1935574499 # Layer occupancy (ticks)
2438c2447
< system.membus.respLayer2.occupancy 2120601580 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 2123782192 # Layer occupancy (ticks)
2440c2449
< system.membus.respLayer3.occupancy 38542869 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 38517394 # Layer occupancy (ticks)
2473,2495c2482,2504
< system.toL2Bus.trans_dist::ReadReq 668340 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 668325 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30933 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30933 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 252536 # Transaction distribution
< system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 92316 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 40369 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 132685 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 38932 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 38932 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370044 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368770 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1738814 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41959415 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7901735 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 49861150 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 291964 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 1090717 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.033437 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.179774 # Request fanout histogram
---
> system.toL2Bus.trans_dist::ReadReq 658320 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 658305 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30953 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30953 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 250431 # Transaction distribution
> system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 90455 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 40208 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 130663 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 38633 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 38633 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1411505 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 304961 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1716466 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 43486557 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5753747 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 49240304 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 287552 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 1076220 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.033884 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.180932 # Request fanout histogram
2498,2499c2507,2508
< system.toL2Bus.snoop_fanout::1 1054247 96.66% 96.66% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 36470 3.34% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::1 1039753 96.61% 96.61% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 36467 3.39% 100.00% # Request fanout histogram
2503,2504c2512,2513
< system.toL2Bus.snoop_fanout::total 1090717 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 1589301055 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 1076220 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 1573537018 # Layer occupancy (ticks)
2508c2517
< system.toL2Bus.respLayer0.occupancy 2361799867 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 2438104006 # Layer occupancy (ticks)
2510c2519
< system.toL2Bus.respLayer1.occupancy 804005619 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 680349684 # Layer occupancy (ticks)