3,5c3,5
< sim_seconds 1.145505 # Number of seconds simulated
< sim_ticks 1145504982000 # Number of ticks simulated
< final_tick 1145504982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.658500 # Number of seconds simulated
> sim_ticks 2658500429500 # Number of ticks simulated
> final_tick 2658500429500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 113120 # Simulator instruction rate (inst/s)
< host_op_rate 136231 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2095202848 # Simulator tick rate (ticks/s)
< host_mem_usage 413760 # Number of bytes of host memory used
< host_seconds 546.73 # Real time elapsed on the host
< sim_insts 61845931 # Number of instructions simulated
< sim_ops 74481224 # Number of ops (including micro ops) simulated
---
> host_inst_rate 100914 # Simulator instruction rate (inst/s)
> host_op_rate 121517 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4256503307 # Simulator tick rate (ticks/s)
> host_mem_usage 437672 # Number of bytes of host memory used
> host_seconds 624.57 # Real time elapsed on the host
> sim_insts 63028509 # Number of instructions simulated
> sim_ops 75896503 # Number of ops (including micro ops) simulated
16,35c16,17
< system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 615 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 615 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 615 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
---
> system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
37,44c19,29
< system.physmem.bytes_read::cpu0.inst 7004988 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 3603320 # Number of bytes read from this memory
< system.physmem.bytes_read::total 60941044 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 751104 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 270784 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1021888 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4281152 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.inst 670652 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 5012160 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 503736 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 5163008 # Number of bytes read from this memory
> system.physmem.bytes_read::total 134034100 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 219584 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 61824 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 281408 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4338816 # Number of bytes written to this memory
46,49c31,34
< system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7308496 # Number of bytes written to this memory
< system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7367952 # Number of bytes written to this memory
> system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
51,55c36,43
< system.physmem.num_reads::cpu0.inst 109512 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 56320 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 6457305 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 66893 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 10538 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 78315 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 7889 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 80672 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15512856 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 67794 # Number of write requests responded to by this memory
57,124c45,118
< system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 823729 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 43938393 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.dtb.walker 335 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 6115196 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 3145617 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 53200156 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 655697 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 236388 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 892085 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3737349 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.inst 14841 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu1.inst 2627962 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 6380152 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3737349 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 43938393 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 335 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 6130037 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 5773579 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 59580308 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 6457305 # Number of read requests accepted
< system.physmem.writeReqs 823729 # Number of write requests accepted
< system.physmem.readBursts 6457305 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 823729 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 413239936 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7320448 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 60941044 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7308496 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 709326 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 12284 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 403300 # Per bank write bursts
< system.physmem.perBankRdBursts::1 403658 # Per bank write bursts
< system.physmem.perBankRdBursts::2 403038 # Per bank write bursts
< system.physmem.perBankRdBursts::3 403410 # Per bank write bursts
< system.physmem.perBankRdBursts::4 406147 # Per bank write bursts
< system.physmem.perBankRdBursts::5 403703 # Per bank write bursts
< system.physmem.perBankRdBursts::6 403511 # Per bank write bursts
< system.physmem.perBankRdBursts::7 403334 # Per bank write bursts
< system.physmem.perBankRdBursts::8 403656 # Per bank write bursts
< system.physmem.perBankRdBursts::9 404136 # Per bank write bursts
< system.physmem.perBankRdBursts::10 403079 # Per bank write bursts
< system.physmem.perBankRdBursts::11 402530 # Per bank write bursts
< system.physmem.perBankRdBursts::12 403635 # Per bank write bursts
< system.physmem.perBankRdBursts::13 403544 # Per bank write bursts
< system.physmem.perBankRdBursts::14 403293 # Per bank write bursts
< system.physmem.perBankRdBursts::15 402900 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6991 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7395 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6850 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7056 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7584 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7290 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7311 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7141 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7309 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7743 # Per bank write bursts
< system.physmem.perBankWrBursts::10 6877 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6465 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7382 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7153 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7067 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6768 # Per bank write bursts
---
> system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 825078 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 46147592 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.dtb.walker 120 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 252267 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 1885334 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 241 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 189481 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 1942075 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 50417182 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 82597 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 23255 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 105852 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1632054 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu1.inst 1133021 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2771469 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1632054 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 46147592 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 120 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 258662 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 1885334 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 241 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 1322502 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 1942075 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53188651 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15512856 # Number of read requests accepted
> system.physmem.writeReqs 825078 # Number of write requests accepted
> system.physmem.readBursts 15512856 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 825078 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 992706816 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 115968 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7383872 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 134034100 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7367952 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 1812 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 709689 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 15707 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 969471 # Per bank write bursts
> system.physmem.perBankRdBursts::1 969246 # Per bank write bursts
> system.physmem.perBankRdBursts::2 969043 # Per bank write bursts
> system.physmem.perBankRdBursts::3 969564 # Per bank write bursts
> system.physmem.perBankRdBursts::4 971813 # Per bank write bursts
> system.physmem.perBankRdBursts::5 969510 # Per bank write bursts
> system.physmem.perBankRdBursts::6 969103 # Per bank write bursts
> system.physmem.perBankRdBursts::7 968972 # Per bank write bursts
> system.physmem.perBankRdBursts::8 969597 # Per bank write bursts
> system.physmem.perBankRdBursts::9 969588 # Per bank write bursts
> system.physmem.perBankRdBursts::10 969467 # Per bank write bursts
> system.physmem.perBankRdBursts::11 968939 # Per bank write bursts
> system.physmem.perBankRdBursts::12 969138 # Per bank write bursts
> system.physmem.perBankRdBursts::13 969444 # Per bank write bursts
> system.physmem.perBankRdBursts::14 969295 # Per bank write bursts
> system.physmem.perBankRdBursts::15 968854 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7363 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7345 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6989 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7254 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7419 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7425 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7374 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7152 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7408 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7360 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7357 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7062 # Per bank write bursts
> system.physmem.perBankWrBursts::12 6947 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7077 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7057 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6784 # Per bank write bursts
127c121
< system.physmem.totGap 1145502120500 # Total gap between requests
---
> system.physmem.totGap 2658500409000 # Total gap between requests
131c125
< system.physmem.readPktSize::3 6291481 # Read request sizes (log2)
---
> system.physmem.readPktSize::3 15335449 # Read request sizes (log2)
134c128
< system.physmem.readPktSize::6 165765 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 177348 # Read request sizes (log2)
137c131
< system.physmem.writePktSize::2 756836 # Write request sizes (log2)
---
> system.physmem.writePktSize::2 757284 # Write request sizes (log2)
141,171c135,165
< system.physmem.writePktSize::6 66893 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 558286 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 398741 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 399967 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 444496 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 405001 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 431562 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1118263 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 1083915 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1408608 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 55788 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 45494 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 41962 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 40334 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 8421 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 7962 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 7851 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 218 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 67794 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1046196 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1019688 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 986842 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1094338 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 993106 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1055542 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2738032 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2641383 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3439999 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 128528 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 110050 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 101603 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 98027 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 19641 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 18942 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 18731 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 149 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 32 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 29 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 20 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 18 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::24 9 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::25 7 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::26 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::27 3 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see
189,213c183,207
< system.physmem.wrQLenPdf::15 3952 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3973 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6584 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6653 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6664 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6655 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6658 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6656 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6659 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6656 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6662 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 6658 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6669 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6657 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6657 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6660 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6652 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 4053 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 4092 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5210 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5835 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6634 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6762 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6877 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7053 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7199 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7335 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7285 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7275 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7348 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7039 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 28 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
238,275c232,277
< system.physmem.bytesPerActivate::samples 460787 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 912.700193 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 781.910252 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 290.668132 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 24338 5.28% 5.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 21658 4.70% 9.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5935 1.29% 11.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2553 0.55% 11.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2424 0.53% 12.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1615 0.35% 12.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 4021 0.87% 13.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 977 0.21% 13.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 397266 86.21% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 460787 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6652 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 970.665664 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 26177.869763 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-65535 6645 99.89% 99.89% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6652 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6652 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.195129 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.166489 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.984981 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 2678 40.26% 40.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 22 0.33% 40.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 3930 59.08% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 20 0.30% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6652 # Writes before turning the bus around for reads
< system.physmem.totQLat 165525335000 # Total ticks spent queuing
< system.physmem.totMemAccLat 286591722500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 32284370000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 25635.52 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1037696 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 963.760762 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 885.523874 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 219.463963 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 32040 3.09% 3.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 21332 2.06% 5.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 9404 0.91% 6.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2470 0.24% 6.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3075 0.30% 6.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2164 0.21% 6.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8825 0.85% 7.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1075 0.10% 7.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 957311 92.25% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1037696 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6640 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 2336.000602 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 97357.467769 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-262143 6632 99.88% 99.88% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.91% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::524288-786431 3 0.05% 99.95% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6640 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6640 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.375452 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.330517 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.281391 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 2518 37.92% 37.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 36 0.54% 38.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 3683 55.47% 93.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 190 2.86% 96.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 92 1.39% 98.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 40 0.60% 98.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 30 0.45% 99.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 20 0.30% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 15 0.23% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 13 0.20% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6640 # Writes before turning the bus around for reads
> system.physmem.totQLat 403478953250 # Total ticks spent queuing
> system.physmem.totMemAccLat 694311028250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 77555220000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 26012.37 # Average queueing delay per DRAM burst
277,281c279,283
< system.physmem.avgMemAccLat 44385.52 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 360.75 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 6.39 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 53.20 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 6.38 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 44762.37 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s
283,295c285,297
< system.physmem.busUtil 2.87 # Data bus utilization in percentage
< system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
< system.physmem.avgRdQLen 3.81 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing
< system.physmem.readRowHits 6016106 # Number of row buffer hits during reads
< system.physmem.writeRowHits 94363 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 82.48 # Row buffer hit rate for writes
< system.physmem.avgGap 157326.85 # Average gap between requests
< system.physmem.pageHitRate 92.99 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 907058635500 # Time in different power states
< system.physmem.memoryStateTime::REF 38250680000 # Time in different power states
---
> system.physmem.busUtil 2.94 # Data bus utilization in percentage
> system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 6.07 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 26.23 # Average write queue length when enqueuing
> system.physmem.readRowHits 14503444 # Number of row buffer hits during reads
> system.physmem.writeRowHits 85277 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 73.90 # Row buffer hit rate for writes
> system.physmem.avgGap 162719.50 # Average gap between requests
> system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2316371594000 # Time in different power states
> system.physmem.memoryStateTime::REF 88773100000 # Time in different power states
297c299
< system.physmem.memoryStateTime::ACT 200188472000 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 253353834750 # Time in different power states
299,310c301,329
< system.membus.throughput 61688542 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 7506218 # Transaction distribution
< system.membus.trans_dist::ReadResp 7506218 # Transaction distribution
< system.membus.trans_dist::WriteReq 767823 # Transaction distribution
< system.membus.trans_dist::WriteResp 767823 # Transaction distribution
< system.membus.trans_dist::Writeback 66893 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 33061 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 17229 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 12284 # Transaction distribution
< system.membus.trans_dist::ReadExReq 137868 # Transaction distribution
< system.membus.trans_dist::ReadExResp 137512 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382652 # Packet count per connected master and slave (bytes)
---
> system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s)
> system.membus.trans_dist::ReadReq 16692425 # Transaction distribution
> system.membus.trans_dist::ReadResp 16692425 # Transaction distribution
> system.membus.trans_dist::WriteReq 768873 # Transaction distribution
> system.membus.trans_dist::WriteResp 768873 # Transaction distribution
> system.membus.trans_dist::Writeback 67794 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 55379 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 22285 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 15707 # Transaction distribution
> system.membus.trans_dist::ReadExReq 15268 # Transaction distribution
> system.membus.trans_dist::ReadExResp 8420 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384472 # Packet count per connected master and slave (bytes)
312c331
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11272 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12568 # Packet count per connected master and slave (bytes)
314,334c333,363
< system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975193 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 4370017 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 16952929 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389988 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22544 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17917892 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::total 20332884 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 70664532 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 70664532 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 1775897999 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
< system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037445 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 4436601 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 35107449 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392888 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25136 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718660 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 21141576 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 143824968 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 68805 # Total snoops (count)
> system.membus.snoop_fanout::samples 327203 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 327203 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 327203 # Request fanout histogram
> system.membus.reqLayer0.occupancy 1769123496 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.membus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
336c365
< system.membus.reqLayer2.occupancy 10198500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 10983499 # Layer occupancy (ticks)
338c367
< system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
---
> system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
340c369
< system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1597500 # Layer occupancy (ticks)
342,346c371,375
< system.membus.reqLayer6.occupancy 8866177000 # Layer occupancy (ticks)
< system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 4931588399 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
< system.membus.respLayer2.occupancy 15569082998 # Layer occupancy (ticks)
---
> system.membus.reqLayer6.occupancy 17876588998 # Layer occupancy (ticks)
> system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
> system.membus.respLayer1.occupancy 5004631688 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
> system.membus.respLayer2.occupancy 37937018429 # Layer occupancy (ticks)
349,353c378,382
< system.l2c.tags.replacements 73238 # number of replacements
< system.l2c.tags.tagsinuse 53823.910561 # Cycle average of tags in use
< system.l2c.tags.total_refs 2398257 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 138408 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 17.327445 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 92212 # number of replacements
> system.l2c.tags.tagsinuse 55213.567741 # Cycle average of tags in use
> system.l2c.tags.total_refs 396364 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 156868 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.526736 # Average number of references to valid blocks.
355,412c384,460
< system.l2c.tags.occ_blocks::writebacks 38958.946929 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.880846 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001294 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 8788.881914 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.740937 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 6066.458640 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.594466 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.134108 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000118 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.092567 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.821288 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 8664 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 53947 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 23040420 # Number of tag accesses
< system.l2c.tags.data_accesses 23040420 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 22272 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 6564 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 949144 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 22723 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 5189 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 959680 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1965572 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 575172 # number of Writeback hits
< system.l2c.Writeback_hits::total 575172 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.inst 954 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.inst 1026 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 1980 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.inst 203 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.inst 94 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 297 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.inst 58656 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.inst 50708 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 109364 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 22272 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 6564 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 1007800 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 22723 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 5189 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 1010388 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2074936 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 22272 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 6564 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 1007800 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 22723 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 5189 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 1010388 # number of overall hits
< system.l2c.overall_hits::total 2074936 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses
---
> system.l2c.tags.occ_blocks::writebacks 8088.192516 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.706191 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029154 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 2502.443827 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29448.913538 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.609197 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 0.004438 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 2039.532288 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13124.136592 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.123416 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000057 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.038184 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.449355 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000086 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.031121 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200258 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.842492 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 53217 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 11430 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 151 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 4758 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 48307 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 1757 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 9394 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.812027 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.174408 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 5122526 # Number of tag accesses
> system.l2c.tags.data_accesses 5122526 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 183 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 37 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 15214 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88074 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 233 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 19471 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76181 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 199443 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 215065 # number of Writeback hits
> system.l2c.Writeback_hits::total 215065 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.inst 3153 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.inst 2020 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 5173 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.inst 94 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.inst 2198 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.inst 2398 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 4596 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 183 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 37 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 17412 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 88074 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 233 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 21869 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 76181 # number of demand (read+write) hits
> system.l2c.demand_hits::total 204039 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 183 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 37 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 17412 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 88074 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 233 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 21869 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 76181 # number of overall hits
> system.l2c.overall_hits::total 204039 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses
414,427c462,478
< system.l2c.ReadReq_misses::cpu0.inst 16107 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 9802 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 25926 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.inst 4879 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.inst 4062 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 8941 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.inst 695 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.inst 300 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 995 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.inst 92450 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.inst 47410 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 139860 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses
---
> system.l2c.ReadReq_misses::cpu0.inst 4198 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78315 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 3275 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80672 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 166478 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.inst 7866 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.inst 5570 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 13436 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.inst 1047 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.inst 1097 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 2144 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.inst 3980 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.inst 4567 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 8547 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses
429,433c480,487
< system.l2c.demand_misses::cpu0.inst 108557 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 57212 # number of demand (read+write) misses
< system.l2c.demand_misses::total 165786 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses
---
> system.l2c.demand_misses::cpu0.inst 8178 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 78315 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 7842 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 80672 # number of demand (read+write) misses
> system.l2c.demand_misses::total 175025 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses
435,552c489,642
< system.l2c.overall_misses::cpu0.inst 108557 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 57212 # number of overall misses
< system.l2c.overall_misses::total 165786 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 592000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.inst 1134045250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 716250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 732959500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1868462500 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.inst 8149146 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.inst 13619415 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 21768561 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 695470 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2181906 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 2877376 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.inst 6400503611 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.inst 3385304039 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 9785807650 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 592000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 7534548861 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 716250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 4118263539 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 11654270150 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 592000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 7534548861 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 716250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 4118263539 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 11654270150 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 22278 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 6566 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 965251 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 22732 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 5189 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 969482 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1991498 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 575172 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 575172 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.inst 5833 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.inst 5088 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 10921 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.inst 898 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.inst 394 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1292 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.inst 151106 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.inst 98118 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 249224 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 22278 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 6566 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 1116357 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 22732 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 5189 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 1067600 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2240722 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 22278 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 6566 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 1116357 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 22732 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 5189 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 1067600 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2240722 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000305 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.016687 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.010111 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.836448 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.798349 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.818698 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.773942 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.761421 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.770124 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.inst 0.611822 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.inst 0.483194 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.561182 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.000305 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.097242 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.053589 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.073988 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.000305 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.097242 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.053589 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.073988 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70406.981437 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74776.525199 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 72069.061946 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1670.249231 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 3352.884047 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2434.689744 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 1000.676259 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 7273.020000 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 2891.835176 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 69232.056366 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 71404.852120 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 69968.594666 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 70297.070621 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 70297.070621 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.l2c.overall_misses::cpu0.inst 8178 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 78315 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 7842 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 80672 # number of overall misses
> system.l2c.overall_misses::total 175025 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 332000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.inst 326103000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 790750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.itb.walker 142500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 265072000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 16470995078 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.inst 13809412 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.inst 6376729 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 20186141 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 656474 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 4281316 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 4937790 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.inst 283206167 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.inst 338006954 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 621213121 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 332000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 609309167 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 790750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 142500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 603078954 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 17092208199 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 332000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 609309167 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 790750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 142500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 603078954 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 17092208199 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 188 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 39 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 19412 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 166389 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 243 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 22746 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 156853 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 365921 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 215065 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 215065 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.inst 11019 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.inst 7590 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 18609 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.inst 1141 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.inst 1310 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2451 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.inst 6178 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.inst 6965 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 13143 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 188 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 39 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 25590 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 166389 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 243 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 29711 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 156853 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 379064 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 188 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 39 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 25590 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 166389 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 243 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 29711 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 156853 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 379064 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.051282 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.216258 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.143981 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.454956 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.713858 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.733860 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.722016 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.917616 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.837405 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.874745 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.inst 0.644221 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.inst 0.655707 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.650308 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.051282 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.319578 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.263943 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.461729 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.051282 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.319578 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.263943 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.461729 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66400 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77680.562172 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79075 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 142500 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80938.015267 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 98937.968248 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1755.582507 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1144.834650 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 1502.392155 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 627.004776 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 3902.749316 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 2303.073694 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 71157.328392 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74010.719072 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 72682.007839 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66400 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 74505.889826 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79075 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142500 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 76903.717674 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 97655.810307 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66400 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 74505.889826 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79075 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142500 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 76903.717674 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 97655.810307 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 174 # number of cycles access was blocked
554c644
< system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked
556c646
< system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 34.800000 # average number of cycles each access was blocked
560,571c650,658
< system.l2c.writebacks::writebacks 66893 # number of writebacks
< system.l2c.writebacks::total 66893 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu1.inst 22 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadReq MSHR misses
---
> system.l2c.writebacks::writebacks 67795 # number of writebacks
> system.l2c.writebacks::total 67795 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 5 # number of ReadReq MSHR misses
573,586c660,676
< system.l2c.ReadReq_mshr_misses::cpu0.inst 16058 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 9780 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 25855 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.inst 4879 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.inst 4062 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 8941 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 695 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 300 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 995 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.inst 92450 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.inst 47410 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 139860 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 4198 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 3274 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 166477 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.inst 7866 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.inst 5570 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 13436 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 1047 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1097 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 2144 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.inst 3980 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.inst 4567 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 8547 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 5 # number of demand (read+write) MSHR misses
588,592c678,685
< system.l2c.demand_mshr_misses::cpu0.inst 108508 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 57190 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 165715 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 8178 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 7841 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 175024 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 5 # number of overall MSHR misses
594,598c687,694
< system.l2c.overall_mshr_misses::cpu0.inst 108508 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 57190 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 165715 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 518500 # number of ReadReq MSHR miss cycles
---
> system.l2c.overall_mshr_misses::cpu0.inst 8178 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 7841 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 175024 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 270000 # number of ReadReq MSHR miss cycles
600,613c696,712
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 929504000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603750 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 609332000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 1540083250 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 48881350 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 40684546 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 89565896 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6993689 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 3002299 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 9995988 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5227989883 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 2775821957 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 8003811840 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 518500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 273844500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 666250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 130500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 224380000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 14413044080 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 79216804 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 56126525 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 135343329 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 10623534 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 10994091 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 21617625 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 233127823 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 280625546 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 513753369 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 270000 # number of demand (read+write) MSHR miss cycles
615,619c714,721
< system.l2c.demand_mshr_miss_latency::cpu0.inst 6157493883 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 603750 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 3385153957 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 9543895090 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 518500 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 506972323 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 666250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 130500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 505005546 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 14926797449 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 270000 # number of overall MSHR miss cycles
621,661c723,775
< system.l2c.overall_mshr_miss_latency::cpu0.inst 6157493883 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 603750 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 3385153957 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 9543895090 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156449029487 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10979297747 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 167428327234 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1364347483 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15414886347 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 16779233830 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157813376970 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26394184094 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 184207561064 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016636 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010088 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.012983 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.836448 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.798349 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.818698 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.773942 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.761421 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770124 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.611822 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.483194 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.561182 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.073956 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.073956 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average ReadReq mshr miss latency
---
> system.l2c.overall_mshr_miss_latency::cpu0.inst 506972323 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 666250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 130500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 505005546 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 14926797449 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12572348996 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155062093246 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 167634442242 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125655500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721437217 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 16847092717 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13698004496 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170783530463 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 184481534959 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.216258 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.143937 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.454953 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.713858 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.733860 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.722016 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.917616 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837405 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.874745 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.644221 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.655707 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.650308 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.461727 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.461727 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average ReadReq mshr miss latency
663,676c777,793
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57884.169884 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62303.885481 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 59566.167086 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10018.723099 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10015.890202 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.436081 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10062.861871 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10007.663333 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10046.219095 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 56549.376777 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58549.292491 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 57227.311883 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65232.134350 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68533.903482 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 86576.788866 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.786168 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.575404 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10073.186142 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10146.641834 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10021.960802 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10082.847481 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 58574.829899 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61446.364353 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 60109.204282 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency
678,682c795,802
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency
684,687c804,810
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency
704,759c827,868
< system.toL2Bus.throughput 163445997 # Throughput (bytes/s)
< system.toL2Bus.trans_dist::ReadReq 3265310 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 3265309 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 767823 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 767823 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 575172 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 32693 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 17526 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 50219 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 260531 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 260531 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1555911 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3285118 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16087 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52607 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1583939 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2567940 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13476 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 53641 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 9128719 # Packet count per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49766528 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43750900 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26264 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 89112 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 50661248 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38001760 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20756 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 90928 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size::total 182407496 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 182407496 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 4820708 # Total snoop data (bytes)
< system.toL2Bus.reqLayer0.occupancy 5144551012 # Layer occupancy (ticks)
< system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
< system.toL2Bus.respLayer0.occupancy 3505001405 # Layer occupancy (ticks)
< system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
< system.toL2Bus.respLayer1.occupancy 2792622052 # Layer occupancy (ticks)
< system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
< system.toL2Bus.respLayer2.occupancy 9525491 # Layer occupancy (ticks)
< system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
< system.toL2Bus.respLayer3.occupancy 30330496 # Layer occupancy (ticks)
< system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.toL2Bus.respLayer6.occupancy 3566573438 # Layer occupancy (ticks)
< system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%)
< system.toL2Bus.respLayer7.occupancy 1934335367 # Layer occupancy (ticks)
< system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
< system.toL2Bus.respLayer8.occupancy 8290992 # Layer occupancy (ticks)
< system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
< system.toL2Bus.respLayer9.occupancy 30912744 # Layer occupancy (ticks)
< system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
< system.iobus.throughput 46024799 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 7474816 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7474816 # Transaction distribution
< system.iobus.trans_dist::WriteReq 7966 # Transaction distribution
< system.iobus.trans_dist::WriteResp 7966 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8038 # Packet count per connected master and slave (bytes)
---
> system.toL2Bus.trans_dist::ReadReq 1655769 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 1655769 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 768873 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 768873 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 215065 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 60425 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 22592 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 83017 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 22828 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 22828 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 802487 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302639 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5105126 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20032432 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23601176 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 43633608 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 171019 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 786212 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 786212 100.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.toL2Bus.snoop_fanout::total 786212 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 2618569936 # Layer occupancy (ticks)
> system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.toL2Bus.respLayer0.occupancy 1234710374 # Layer occupancy (ticks)
> system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.toL2Bus.respLayer1.occupancy 2607103376 # Layer occupancy (ticks)
> system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
> system.iobus.trans_dist::ReadReq 16519576 # Transaction distribution
> system.iobus.trans_dist::ReadResp 16519576 # Transaction distribution
> system.iobus.trans_dist::WriteReq 8084 # Transaction distribution
> system.iobus.trans_dist::WriteResp 8084 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8928 # Packet count per connected master and slave (bytes)
761c870
< system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
764c873
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 498 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes)
781,813c890,921
< system.iobus.pkt_count_system.bridge.master::total 2382652 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 14965564 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16076 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 273 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::total 2389988 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 52721636 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 52721636 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks)
---
> system.iobus.pkt_count_system.bridge.master::total 2384472 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 33055320 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17856 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 2392888 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 125076280 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks)
815c923
< system.iobus.reqLayer1.occupancy 4025000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 4470000 # Layer occupancy (ticks)
819c927
< system.iobus.reqLayer3.occupancy 372000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
825c933
< system.iobus.reqLayer6.occupancy 299000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks)
828c936
< system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
---
> system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
859,869c967,977
< system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks)
< system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
< system.iobus.respLayer0.occupancy 2374686000 # Layer occupancy (ticks)
< system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
< system.iobus.respLayer1.occupancy 15862213002 # Layer occupancy (ticks)
< system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
< system.cpu0.branchPred.lookups 6670288 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 4756995 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 639495 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 4605007 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 3289427 # Number of BTB hits
---
> system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks)
> system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
> system.iobus.respLayer0.occupancy 2376388000 # Layer occupancy (ticks)
> system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
> system.iobus.respLayer1.occupancy 38667942571 # Layer occupancy (ticks)
> system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
> system.cpu0.branchPred.lookups 7247667 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 5145194 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 425040 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 4677323 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 3357189 # Number of BTB hits
871,873c979,981
< system.cpu0.branchPred.BTBHitPct 71.431531 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 870926 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 69312 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 71.775864 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 942424 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 64273 # Number of incorrect RAS predictions.
897,900c1005,1008
< system.cpu0.dtb.read_hits 7193152 # DTB read hits
< system.cpu0.dtb.read_misses 17493 # DTB read misses
< system.cpu0.dtb.write_hits 6058571 # DTB write hits
< system.cpu0.dtb.write_misses 1416 # DTB write misses
---
> system.cpu0.dtb.read_hits 6449421 # DTB read hits
> system.cpu0.dtb.read_misses 22629 # DTB read misses
> system.cpu0.dtb.write_hits 5803237 # DTB write hits
> system.cpu0.dtb.write_misses 1880 # DTB write misses
905,907c1013,1015
< system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 1486 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 207 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 1731 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 1649 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 155 # Number of TLB faults due to prefetch
909,911c1017,1019
< system.cpu0.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 7210645 # DTB read accesses
< system.cpu0.dtb.write_accesses 6059987 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 268 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 6472050 # DTB read accesses
> system.cpu0.dtb.write_accesses 5805117 # DTB write accesses
913,915c1021,1023
< system.cpu0.dtb.hits 13251723 # DTB hits
< system.cpu0.dtb.misses 18909 # DTB misses
< system.cpu0.dtb.accesses 13270632 # DTB accesses
---
> system.cpu0.dtb.hits 12252658 # DTB hits
> system.cpu0.dtb.misses 24509 # DTB misses
> system.cpu0.dtb.accesses 12277167 # DTB accesses
937,938c1045,1046
< system.cpu0.itb.inst_hits 12268451 # ITB inst hits
< system.cpu0.itb.inst_misses 4809 # ITB inst misses
---
> system.cpu0.itb.inst_hits 13306402 # ITB inst hits
> system.cpu0.itb.inst_misses 3981 # ITB inst misses
947c1055
< system.cpu0.itb.flush_entries 1294 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 1196 # Number of entries that have been flushed from TLB
951c1059
< system.cpu0.itb.perms_faults 2809 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 3606 # Number of TLB faults due to permissions restrictions
954,958c1062,1066
< system.cpu0.itb.inst_accesses 12273260 # ITB inst accesses
< system.cpu0.itb.hits 12268451 # DTB hits
< system.cpu0.itb.misses 4809 # DTB misses
< system.cpu0.itb.accesses 12273260 # DTB accesses
< system.cpu0.numCycles 431172708 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 13310383 # ITB inst accesses
> system.cpu0.itb.hits 13306402 # DTB hits
> system.cpu0.itb.misses 3981 # DTB misses
> system.cpu0.itb.accesses 13310383 # DTB accesses
> system.cpu0.numCycles 86779776 # number of cpu cycles simulated
961,967c1069,1075
< system.cpu0.committedInsts 29878954 # Number of instructions committed
< system.cpu0.committedOps 36403873 # Number of ops (including micro ops) committed
< system.cpu0.discardedOps 1704985 # Number of ops (including micro ops) which were discarded before commit
< system.cpu0.numFetchSuspends 39450 # Number of times Execute suspended instruction fetching
< system.cpu0.quiesceCycles 1859905219 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.cpi 14.430649 # CPI: cycles per instruction
< system.cpu0.ipc 0.069297 # IPC: instructions per cycle
---
> system.cpu0.committedInsts 29469177 # Number of instructions committed
> system.cpu0.committedOps 35692469 # Number of ops (including micro ops) committed
> system.cpu0.discardedOps 1968048 # Number of ops (including micro ops) which were discarded before commit
> system.cpu0.numFetchSuspends 41085 # Number of times Execute suspended instruction fetching
> system.cpu0.quiesceCycles 5234632408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.cpi 2.944764 # CPI: cycles per instruction
> system.cpu0.ipc 0.339586 # IPC: instructions per cycle
969,980c1077,1088
< system.cpu0.kern.inst.quiesce 50317 # number of quiesce instructions executed
< system.cpu0.tickCycles 351703818 # Number of cycles that the object actually ticked
< system.cpu0.idleCycles 79468890 # Total number of cycles that the object has spent stopped
< system.cpu0.icache.tags.replacements 775463 # number of replacements
< system.cpu0.icache.tags.tagsinuse 510.771777 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 11489502 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 775975 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 14.806536 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 10202297000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.771777 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997601 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.997601 # Average percentage of cache occupancy
---
> system.cpu0.kern.inst.quiesce 47499 # number of quiesce instructions executed
> system.cpu0.tickCycles 68210329 # Number of cycles that the object actually ticked
> system.cpu0.idleCycles 18569447 # Total number of cycles that the object has spent stopped
> system.cpu0.icache.tags.replacements 669895 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.780265 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 12632215 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 670407 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 18.842606 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 6077782000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780265 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy
982,983c1090,1092
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id
985,1022c1094,1131
< system.cpu0.icache.tags.tag_accesses 13041458 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 13041458 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 11489502 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 11489502 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 11489502 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 11489502 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 11489502 # number of overall hits
< system.cpu0.icache.overall_hits::total 11489502 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 775978 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 775978 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 775978 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 775978 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 775978 # number of overall misses
< system.cpu0.icache.overall_misses::total 775978 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10689826155 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 10689826155 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 10689826155 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 10689826155 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 10689826155 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 10689826155 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 12265480 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 12265480 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 12265480 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 12265480 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 12265480 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 12265480 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.063265 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.063265 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.063265 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.063265 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.063265 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.063265 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13775.939724 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 13775.939724 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 13775.939724 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 13775.939724 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 27275662 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 27275662 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 12632215 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 12632215 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 12632215 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 12632215 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 12632215 # number of overall hits
> system.cpu0.icache.overall_hits::total 12632215 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 670411 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 670411 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 670411 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 670411 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 670411 # number of overall misses
> system.cpu0.icache.overall_misses::total 670411 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5588337897 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 5588337897 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 5588337897 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 5588337897 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 5588337897 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 5588337897 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 13302626 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 13302626 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 13302626 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 13302626 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 13302626 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 13302626 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050397 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.050397 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050397 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.050397 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050397 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.050397 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8335.689446 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 8335.689446 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 8335.689446 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 8335.689446 # average overall miss latency
1031,1058c1140,1167
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 775978 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 775978 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 775978 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 775978 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 775978 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 775978 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9133730845 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 9133730845 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9133730845 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 9133730845 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9133730845 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 9133730845 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171407250 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171407250 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171407250 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 171407250 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.063265 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.063265 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.063265 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11770.605410 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 670411 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 670411 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 670411 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 670411 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 670411 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 670411 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4581839103 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 4581839103 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4581839103 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 4581839103 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4581839103 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 4581839103 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 215199250 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 215199250 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 215199250 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 215199250 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050397 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.050397 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.050397 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6834.373396 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency
1064,1149c1173,1598
< system.cpu0.dcache.tags.replacements 331184 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 495.308279 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 11419092 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 331547 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 34.441850 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 235572250 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.inst 495.308279 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.967399 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.967399 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 363 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 48281639 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 48281639 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.inst 5587990 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 5587990 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.inst 5501455 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 5501455 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152609 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 152609 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 153662 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 153662 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.inst 11089445 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 11089445 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.inst 11089445 # number of overall hits
< system.cpu0.dcache.overall_hits::total 11089445 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.inst 255115 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 255115 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.inst 311930 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 311930 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 8548 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 8548 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 7439 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 7439 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.inst 567045 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 567045 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.inst 567045 # number of overall misses
< system.cpu0.dcache.overall_misses::total 567045 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3832963977 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 3832963977 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15354005377 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 15354005377 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 89150250 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 89150250 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47371188 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 47371188 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.inst 19186969354 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 19186969354 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.inst 19186969354 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 19186969354 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.inst 5843105 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 5843105 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5813385 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 5813385 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 161157 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 161157 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 161101 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 161101 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.inst 11656490 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 11656490 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.inst 11656490 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 11656490 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.043661 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.043661 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.053657 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.053657 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.053041 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053041 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046176 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046176 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.048646 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.048646 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.048646 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.048646 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15024.455547 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.455547 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49222.599227 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 49222.599227 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10429.369443 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10429.369443 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6367.951069 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6367.951069 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 33836.766666 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 33836.766666 # average overall miss latency
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 1297449 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1098949 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 10915 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 10915 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 277394 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 309853 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 48681 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23393 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 54656 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 145161 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 136933 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1345495 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1384854 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13521 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 67392 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 2811262 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43053120 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45712112 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22348 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 121316 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 88908896 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 663093 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 2014813 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 5.294791 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.455949 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::5 1420865 70.52% 70.52% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::6 593948 29.48% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::total 2014813 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 1042501632 # Layer occupancy (ticks)
> system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu0.toL2Bus.snoopLayer0.occupancy 66915000 # Layer occupancy (ticks)
> system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu0.toL2Bus.respLayer0.occupancy 1010138647 # Layer occupancy (ticks)
> system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu0.toL2Bus.respLayer1.occupancy 706064108 # Layer occupancy (ticks)
> system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
> system.cpu0.toL2Bus.respLayer2.occupancy 7935497 # Layer occupancy (ticks)
> system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
> system.cpu0.toL2Bus.respLayer3.occupancy 37067990 # Layer occupancy (ticks)
> system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6505286 # number of hwpf identified
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 197873 # number of hwpf that were already in mshr
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6075585 # number of hwpf that were already in the cache
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2087 # number of hwpf that were already in the prefetch queue
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 227641 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 451994 # number of hwpf spanning a virtual page
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
> system.cpu0.l2cache.tags.replacements 185568 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16045.943959 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 1211197 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 201780 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 6.002562 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 5120960000 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 4785.288649 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 15.661304 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.175022 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2150.935803 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9093.883182 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.292071 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000956 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000011 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.131283 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.555047 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.979367 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8308 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7886 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 36 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 61 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 933 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5734 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1544 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1527 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5465 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 648 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.507080 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.481323 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 22965812 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 22965812 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29822 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5414 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.inst 885726 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 920962 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 277394 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 277394 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1852 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 1852 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 771 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 771 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107990 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 107990 # number of ReadExReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29822 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5414 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 993716 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1028952 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29822 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5414 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 993716 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1028952 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 507 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.inst 49350 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 50030 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 18889 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 18889 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 10120 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 10120 # number of SCUpgradeReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 23685 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 23685 # number of ReadExReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 507 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 73035 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 73715 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 507 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 73035 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 73715 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10873500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3613500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1326942681 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 1341429681 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312233020 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 312233020 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 200699599 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 200699599 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1269500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1269500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 847496588 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 847496588 # number of ReadExReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10873500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3613500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2174439269 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 2188926269 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10873500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3613500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2174439269 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 2188926269 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 30329 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5587 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 935076 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 970992 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 277394 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 277394 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 20741 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 20741 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 10891 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 10891 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 131675 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 131675 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 30329 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5587 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1066751 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1102667 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 30329 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5587 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1066751 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1102667 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030965 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052776 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.051525 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.910708 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.910708 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.929208 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.929208 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.179875 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179875 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030965 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.068465 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.066852 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030965 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.068465 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.066852 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 20887.283237 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26888.402857 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26812.506116 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16529.886177 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16529.886177 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19831.976186 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19831.976186 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 35781.996538 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35781.996538 # average ReadExReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 20887.283237 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29772.564784 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 29694.448470 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 20887.283237 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29772.564784 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 29694.448470 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 1346 # number of cycles access was blocked
> system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu0.l2cache.blocked::no_mshrs 34 # number of cycles access was blocked
> system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 39.588235 # average number of cycles each access was blocked
> system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu0.l2cache.writebacks::writebacks 114944 # number of writebacks
> system.cpu0.l2cache.writebacks::total 114944 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2945 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 2945 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 748 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 748 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3693 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 3693 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3693 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 3693 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 507 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 46405 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 47085 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 227640 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 227640 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 18889 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18889 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 10120 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10120 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 22937 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 22937 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 507 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69342 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 70022 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 507 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69342 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 227640 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 297662 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2402500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 949940475 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 959667475 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8587835748 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8587835748 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 341053600 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 341053600 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 145849953 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 145849953 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1059500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1059500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 592786901 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 592786901 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2402500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1542727376 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 1552454376 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2402500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1542727376 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8587835748 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 10140290124 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14160332496 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14160332496 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1312896000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1312896000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15473228496 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15473228496 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.049627 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.048492 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
> system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.910708 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.910708 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.929208 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.929208 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.174194 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.174194 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.065003 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.063502 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.065003 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.269947 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20470.649176 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20381.596581 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37725.512862 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18055.672614 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18055.672614 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14412.050692 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14412.050692 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 25844.133976 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25844.133976 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22170.951644 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34066.458345 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu0.dcache.tags.replacements 363620 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 473.092728 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 11412864 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 364132 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 31.342656 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.092728 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924009 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.924009 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 24359055 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 24359055 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.inst 5804369 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 5804369 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275244 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 5275244 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147463 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 147463 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146615 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 146615 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.inst 11079613 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 11079613 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.inst 11079613 # number of overall hits
> system.cpu0.dcache.overall_hits::total 11079613 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.inst 309599 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 309599 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.inst 276951 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 276951 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 10168 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 10168 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 10891 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 10891 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.inst 586550 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 586550 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.inst 586550 # number of overall misses
> system.cpu0.dcache.overall_misses::total 586550 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3701357617 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 3701357617 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 4193199790 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 4193199790 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 166675501 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 166675501 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 254636964 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 254636964 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1359500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1359500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.inst 7894557407 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 7894557407 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.inst 7894557407 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 7894557407 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113968 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 6113968 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5552195 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5552195 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157631 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 157631 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157506 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 157506 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.inst 11666163 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 11666163 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.inst 11666163 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 11666163 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050638 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.050638 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049881 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.049881 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064505 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064505 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069147 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069147 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050278 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.050278 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050278 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.050278 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11955.328076 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 11955.328076 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15140.583677 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 15140.583677 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16392.161782 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16392.161782 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23380.494353 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23380.494353 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 13459.308511 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 13459.308511 # average overall miss latency
1158,1223c1607,1676
< system.cpu0.dcache.writebacks::writebacks 307170 # number of writebacks
< system.cpu0.dcache.writebacks::total 307170 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 50178 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 50178 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 144238 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 144238 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 22 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.inst 194416 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 194416 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.inst 194416 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 194416 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 204937 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 204937 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167692 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 167692 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8526 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7439 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 7439 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.inst 372629 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 372629 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.inst 372629 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 372629 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2523643558 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2523643558 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7293302576 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7293302576 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71695750 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71695750 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32490812 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32490812 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9816946134 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9816946134 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9816946134 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 9816946134 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170796523752 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170796523752 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513122000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513122000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172309645752 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172309645752 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.035073 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035073 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028846 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028846 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.052905 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.052905 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046176 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046176 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.031968 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031968 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12314.240757 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12314.240757 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 43492.251127 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43492.251127 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8409.072250 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8409.072250 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4367.631671 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4367.631671 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 277395 # number of writebacks
> system.cpu0.dcache.writebacks::total 277395 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54934 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 54934 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124546 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 124546 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.inst 179480 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 179480 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.inst 179480 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 179480 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 254665 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 254665 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152405 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 152405 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10094 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10094 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10891 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 10891 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.inst 407070 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 407070 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.inst 407070 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 407070 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2527058296 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2527058296 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2131958823 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2131958823 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 145779499 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145779499 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231881036 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231881036 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1299500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1299500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4659017119 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 4659017119 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4659017119 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 4659017119 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14650509239 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14650509239 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394876998 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394876998 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16045386237 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16045386237 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041653 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041653 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027450 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027450 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064036 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064036 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069147 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069147 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.034893 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.034893 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9923.068722 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9923.068722 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13988.772173 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13988.772173 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14442.193283 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14442.193283 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21291.069323 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21291.069323 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency
1231,1235c1684,1688
< system.cpu1.branchPred.lookups 6159330 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 4534606 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 426160 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 3924244 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 3043762 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 7015971 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 5101339 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 682515 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 5021553 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 3808301 # Number of BTB hits
1237,1239c1690,1692
< system.cpu1.branchPred.BTBHitPct 77.563016 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 713205 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 64399 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 75.839108 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 855690 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 72942 # Number of incorrect RAS predictions.
1263,1266c1716,1719
< system.cpu1.dtb.read_hits 6763605 # DTB read hits
< system.cpu1.dtb.read_misses 17087 # DTB read misses
< system.cpu1.dtb.write_hits 5563764 # DTB write hits
< system.cpu1.dtb.write_misses 2456 # DTB write misses
---
> system.cpu1.dtb.read_hits 7897430 # DTB read hits
> system.cpu1.dtb.read_misses 21135 # DTB read misses
> system.cpu1.dtb.write_hits 6047519 # DTB write hits
> system.cpu1.dtb.write_misses 2176 # DTB write misses
1271,1273c1724,1726
< system.cpu1.dtb.flush_entries 1713 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 1918 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 3376 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch
1275,1277c1728,1730
< system.cpu1.dtb.perms_faults 260 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 6780692 # DTB read accesses
< system.cpu1.dtb.write_accesses 5566220 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 7918565 # DTB read accesses
> system.cpu1.dtb.write_accesses 6049695 # DTB write accesses
1279,1281c1732,1734
< system.cpu1.dtb.hits 12327369 # DTB hits
< system.cpu1.dtb.misses 19543 # DTB misses
< system.cpu1.dtb.accesses 12346912 # DTB accesses
---
> system.cpu1.dtb.hits 13944949 # DTB hits
> system.cpu1.dtb.misses 23311 # DTB misses
> system.cpu1.dtb.accesses 13968260 # DTB accesses
1303,1304c1756,1757
< system.cpu1.itb.inst_hits 11206823 # ITB inst hits
< system.cpu1.itb.inst_misses 4156 # ITB inst misses
---
> system.cpu1.itb.inst_hits 14225149 # ITB inst hits
> system.cpu1.itb.inst_misses 5020 # ITB inst misses
1313c1766
< system.cpu1.itb.flush_entries 1190 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1294 # Number of entries that have been flushed from TLB
1317c1770
< system.cpu1.itb.perms_faults 2956 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 3363 # Number of TLB faults due to permissions restrictions
1320,1324c1773,1777
< system.cpu1.itb.inst_accesses 11210979 # ITB inst accesses
< system.cpu1.itb.hits 11206823 # DTB hits
< system.cpu1.itb.misses 4156 # DTB misses
< system.cpu1.itb.accesses 11210979 # DTB accesses
< system.cpu1.numCycles 147611080 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 14230169 # ITB inst accesses
> system.cpu1.itb.hits 14225149 # DTB hits
> system.cpu1.itb.misses 5020 # DTB misses
> system.cpu1.itb.accesses 14230169 # DTB accesses
> system.cpu1.numCycles 502333604 # number of cpu cycles simulated
1327,1333c1780,1786
< system.cpu1.committedInsts 31966977 # Number of instructions committed
< system.cpu1.committedOps 38077351 # Number of ops (including micro ops) committed
< system.cpu1.discardedOps 1608279 # Number of ops (including micro ops) which were discarded before commit
< system.cpu1.numFetchSuspends 39953 # Number of times Execute suspended instruction fetching
< system.cpu1.quiesceCycles 2144312243 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.cpi 4.617611 # CPI: cycles per instruction
< system.cpu1.ipc 0.216562 # IPC: instructions per cycle
---
> system.cpu1.committedInsts 33559332 # Number of instructions committed
> system.cpu1.committedOps 40204034 # Number of ops (including micro ops) committed
> system.cpu1.discardedOps 2027525 # Number of ops (including micro ops) which were discarded before commit
> system.cpu1.numFetchSuspends 40422 # Number of times Execute suspended instruction fetching
> system.cpu1.quiesceCycles 4816582490 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.cpi 14.968522 # CPI: cycles per instruction
> system.cpu1.ipc 0.066807 # IPC: instructions per cycle
1335,1346c1788,1799
< system.cpu1.kern.inst.quiesce 40481 # number of quiesce instructions executed
< system.cpu1.tickCycles 117794272 # Number of cycles that the object actually ticked
< system.cpu1.idleCycles 29816808 # Total number of cycles that the object has spent stopped
< system.cpu1.icache.tags.replacements 791766 # number of replacements
< system.cpu1.icache.tags.tagsinuse 480.612166 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 10411414 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 792278 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 13.141112 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 82581306250 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.612166 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938696 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.938696 # Average percentage of cache occupancy
---
> system.cpu1.kern.inst.quiesce 45430 # number of quiesce instructions executed
> system.cpu1.tickCycles 438569606 # Number of cycles that the object actually ticked
> system.cpu1.idleCycles 63763998 # Total number of cycles that the object has spent stopped
> system.cpu1.icache.tags.replacements 776883 # number of replacements
> system.cpu1.icache.tags.tagsinuse 499.132911 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 13444222 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 777395 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 17.293939 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 68940011500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.132911 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974869 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.974869 # Average percentage of cache occupancy
1348,1351c1801
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
1353,1390c1803,1840
< system.cpu1.icache.tags.tag_accesses 11995971 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 11995971 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 10411414 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 10411414 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 10411414 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 10411414 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 10411414 # number of overall hits
< system.cpu1.icache.overall_hits::total 10411414 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 792279 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 792279 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 792279 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 792279 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 792279 # number of overall misses
< system.cpu1.icache.overall_misses::total 792279 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10606605688 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 10606605688 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 10606605688 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 10606605688 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 10606605688 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 10606605688 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 11203693 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 11203693 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 11203693 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 11203693 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 11203693 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 11203693 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070716 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.070716 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070716 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.070716 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070716 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.070716 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.462861 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.462861 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13387.462861 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13387.462861 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 29220629 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 29220629 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 13444222 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 13444222 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 13444222 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 13444222 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 13444222 # number of overall hits
> system.cpu1.icache.overall_hits::total 13444222 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 777395 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 777395 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 777395 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 777395 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 777395 # number of overall misses
> system.cpu1.icache.overall_misses::total 777395 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6473834509 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 6473834509 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 6473834509 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 6473834509 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 6473834509 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 6473834509 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 14221617 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 14221617 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 14221617 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 14221617 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 14221617 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 14221617 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054663 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.054663 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054663 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.054663 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054663 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.054663 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8327.599880 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 8327.599880 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 8327.599880 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 8327.599880 # average overall miss latency
1399,1426c1849,1876
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 792279 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 792279 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 792279 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 792279 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 792279 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 792279 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9020137312 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 9020137312 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9020137312 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 9020137312 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9020137312 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 9020137312 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5771250 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5771250 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5771250 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 5771250 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070716 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.070716 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.070716 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11385.051619 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 777395 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 777395 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 777395 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 777395 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 777395 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 777395 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5306001991 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5306001991 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5306001991 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5306001991 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5306001991 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5306001991 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7443500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7443500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7443500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 7443500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054663 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.054663 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.054663 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6825.361613 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency
1432,1520c1882,2310
< system.cpu1.dcache.tags.replacements 300206 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 447.094079 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 10899911 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 300718 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 36.246287 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 76416861250 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.inst 447.094079 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.873231 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.873231 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 45736548 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 45736548 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.inst 6288103 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 6288103 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.inst 4421998 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 4421998 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78443 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 78443 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79055 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 79055 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.inst 10710101 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 10710101 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.inst 10710101 # number of overall hits
< system.cpu1.dcache.overall_hits::total 10710101 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.inst 241320 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 241320 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.inst 223635 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 223635 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10750 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 10750 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10087 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 10087 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.inst 464955 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 464955 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.inst 464955 # number of overall misses
< system.cpu1.dcache.overall_misses::total 464955 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3586794993 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 3586794993 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8773828993 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 8773828993 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90116500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 90116500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50277799 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 50277799 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.inst 12360623986 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 12360623986 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.inst 12360623986 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 12360623986 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6529423 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 6529423 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4645633 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 4645633 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89193 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 89193 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89142 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 89142 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.inst 11175056 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 11175056 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.inst 11175056 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 11175056 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.036959 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.036959 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048139 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.048139 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120525 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120525 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.113157 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113157 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.041607 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.041607 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.041607 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.041607 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14863.231365 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14863.231365 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 39232.807892 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 39232.807892 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8382.930233 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8382.930233 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4984.415485 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4984.415485 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 26584.559766 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 26584.559766 # average overall miss latency
---
> system.cpu1.toL2Bus.trans_dist::ReadReq 2372884 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 2161619 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 757958 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 757958 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 242023 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 269237 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 52848 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23732 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 50462 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 145739 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 137938 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1554692 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4766762 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17488 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67601 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 6406543 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49741696 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44501144 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30140 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 121260 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 94394240 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 607829 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 2003123 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 5.277710 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.447870 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::5 1446836 72.23% 72.23% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::6 556287 27.77% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::total 2003123 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 2275243689 # Layer occupancy (ticks)
> system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.cpu1.toL2Bus.snoopLayer0.occupancy 46353997 # Layer occupancy (ticks)
> system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu1.toL2Bus.respLayer0.occupancy 1167104009 # Layer occupancy (ticks)
> system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu1.toL2Bus.respLayer1.occupancy 2025335762 # Layer occupancy (ticks)
> system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
> system.cpu1.toL2Bus.respLayer2.occupancy 9955994 # Layer occupancy (ticks)
> system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
> system.cpu1.toL2Bus.respLayer3.occupancy 37292239 # Layer occupancy (ticks)
> system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6843055 # number of hwpf identified
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163843 # number of hwpf that were already in mshr
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6478033 # number of hwpf that were already in the cache
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2741 # number of hwpf that were already in the prefetch queue
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2015 # number of hwpf removed because MSHR allocated
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 196423 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 563857 # number of hwpf spanning a virtual page
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
> system.cpu1.l2cache.tags.replacements 179577 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15624.309787 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 1195829 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 195022 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 6.131765 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 2581358397500 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 4477.438103 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.594175 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.081575 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2724.649779 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8398.546154 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.273281 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001379 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000066 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.166299 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.512607 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.953632 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9457 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5975 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2071 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1611 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5775 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2329 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 929 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2717 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.577209 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364685 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 23391503 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 23391503 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29831 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7391 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.inst 925413 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 962635 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 242023 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 242023 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1118 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 1118 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112181 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 112181 # number of ReadExReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29831 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7391 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 1037594 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 1074816 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29831 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7391 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 1037594 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 1074816 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 484 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 144 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61489 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 62117 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18553 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 18553 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12524 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 12524 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 24216 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 24216 # number of ReadExReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 484 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 144 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 85705 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 86333 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 484 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 144 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 85705 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 86333 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10993750 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3129500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1532483424 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 1546606674 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 310148223 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 310148223 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 250854673 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 250854673 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 743500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 743500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1014040211 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1014040211 # number of ReadExReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10993750 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3129500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2546523635 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 2560646885 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10993750 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3129500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2546523635 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 2560646885 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 30315 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7535 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 986902 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 1024752 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 242023 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 242023 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20363 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 20363 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13642 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 13642 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136397 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 136397 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 30315 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7535 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 1123299 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 1161149 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 30315 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7535 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 1123299 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 1161149 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019111 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.062305 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.060617 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.911113 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.911113 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.918047 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.918047 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.177541 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.177541 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019111 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076298 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.074351 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019111 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076298 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.074351 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21732.638889 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 24922.887411 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24898.283465 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 16716.877217 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16716.877217 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20029.916401 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20029.916401 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 743500 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 743500 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41874.802238 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41874.802238 # average ReadExReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21732.638889 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29712.661280 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 29660.117047 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21732.638889 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29712.661280 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 29660.117047 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 2162 # number of cycles access was blocked
> system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu1.l2cache.blocked::no_mshrs 53 # number of cycles access was blocked
> system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 40.792453 # average number of cycles each access was blocked
> system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu1.l2cache.writebacks::writebacks 100121 # number of writebacks
> system.cpu1.l2cache.writebacks::total 100121 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3717 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 3717 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 1346 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 1346 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5063 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 5063 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5063 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 5063 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 484 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 144 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 57772 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 58400 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 196422 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 196422 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 18553 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 18553 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 12524 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12524 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 1 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 22870 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 22870 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 484 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 144 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 80642 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 81270 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 484 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 144 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 80642 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 196422 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 277692 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2121500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1060116241 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1069841991 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10135528743 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10135528743 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 305752523 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 305752523 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 178428901 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 178428901 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 582500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 582500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 637234022 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 637234022 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2121500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1697350263 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 1707076013 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2121500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1697350263 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10135528743 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 11842604756 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 174928342748 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174928342748 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 28797063287 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28797063287 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 203725406035 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 203725406035 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.058539 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.056989 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
> system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.911113 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.911113 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.918047 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.918047 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.167672 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.167672 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.071790 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.069991 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.071790 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.239153 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18350.000710 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18319.212175 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51600.781700 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16479.950574 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16479.950574 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14246.957921 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14246.957921 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 582500 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 582500 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27863.315348 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27863.315348 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21047.968342 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21004.995853 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21047.968342 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42646.546375 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu1.dcache.tags.replacements 322636 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 491.144142 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 11399665 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 322979 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 35.295375 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 72461169500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.144142 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959266 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.959266 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 24160845 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 24160845 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.inst 6375348 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 6375348 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.inst 4820943 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 4820943 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 83445 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 83445 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 81578 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 81578 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.inst 11196291 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 11196291 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.inst 11196291 # number of overall hits
> system.cpu1.dcache.overall_hits::total 11196291 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.inst 234523 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 234523 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.inst 286003 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 286003 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 11843 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 11843 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 13643 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 13643 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.inst 520526 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 520526 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.inst 520526 # number of overall misses
> system.cpu1.dcache.overall_misses::total 520526 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3079569141 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 3079569141 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 4582527620 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 4582527620 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 211610249 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 211610249 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 314496917 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 314496917 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 813000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 813000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.inst 7662096761 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 7662096761 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.inst 7662096761 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 7662096761 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6609871 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 6609871 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.inst 5106946 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 5106946 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 95288 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 95288 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 95221 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 95221 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.inst 11716817 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 11716817 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.inst 11716817 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 11716817 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.035481 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.035481 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.056003 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.056003 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.124286 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124286 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.143277 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.143277 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044426 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.044426 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044426 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.044426 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 13131.203085 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 13131.203085 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16022.655776 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 16022.655776 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 17867.959892 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17867.959892 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23051.888661 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23051.888661 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14719.911707 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 14719.911707 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14719.911707 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 14719.911707 # average overall miss latency
1529,1594c2319,2388
< system.cpu1.dcache.writebacks::writebacks 268002 # number of writebacks
< system.cpu1.dcache.writebacks::total 268002 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36395 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 36395 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98109 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 98109 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 34 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.inst 134504 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 134504 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.inst 134504 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 134504 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 204925 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 204925 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125526 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 125526 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10716 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10716 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10087 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 10087 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.inst 330451 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 330451 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.inst 330451 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 330451 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2412502275 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2412502275 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4153602004 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4153602004 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68123500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68123500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30103201 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30103201 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6566104279 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 6566104279 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6566104279 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 6566104279 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11993503000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11993503000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672579152 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672579152 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36666082152 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36666082152 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.031385 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.031385 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027020 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027020 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120144 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120144 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113157 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113157 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.029570 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.029570 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.610833 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11772.610833 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 33089.575100 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33089.575100 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6357.176185 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6357.176185 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2984.356201 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2984.356201 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 242023 # number of writebacks
> system.cpu1.dcache.writebacks::total 242023 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36547 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 36547 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129246 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 129246 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 45 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.inst 165793 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 165793 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.inst 165793 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 165793 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 197976 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 197976 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156757 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 156757 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11798 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11798 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13643 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 13643 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.inst 354733 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 354733 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.inst 354733 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 354733 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204262298 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204262298 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2289972148 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2289972148 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 187457749 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 187457749 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286173083 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286173083 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 767000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 767000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4494234446 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4494234446 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4494234446 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4494234446 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183748244745 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183748244745 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481816713 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481816713 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218230061458 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218230061458 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029952 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029952 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030695 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030695 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.123814 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123814 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143277 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143277 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.030276 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.030276 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11133.987443 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11133.987443 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14608.420345 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14608.420345 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 15888.942956 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15888.942956 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20975.817855 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20975.817855 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency
1618,1621c2412,2415
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722335941002 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 722335941002 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722335941002 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 722335941002 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1759208062571 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1759208062571 # number of overall MSHR uncacheable cycles