Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

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stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.847227 # Number of seconds simulated 4sim_ticks 2847227406000 # Number of ticks simulated 5final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.847227 # Number of seconds simulated 4sim_ticks 2847227406000 # Number of ticks simulated 5final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 262523 # Simulator instruction rate (inst/s) 8host_op_rate 317894 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5870765699 # Simulator tick rate (ticks/s) 10host_mem_usage 664268 # Number of bytes of host memory used 11host_seconds 484.98 # Real time elapsed on the host	7host_inst_rate 166460 # Simulator instruction rate (inst/s) 8host_op_rate 201569 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3722516357 # Simulator tick rate (ticks/s) 10host_mem_usage 624360 # Number of bytes of host memory used 11host_seconds 764.87 # Real time elapsed on the host
12sim_insts 127319545 # Number of instructions simulated 13sim_ops 154173476 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8353536 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 643604 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 446720 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12635780 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1647744 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1865024 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8874176 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8891740 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 117 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 25746 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 21109 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 130524 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.data 10077 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.l2cache.prefetcher 6980 # Number of read requests responded to by this memory 44system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 45system.physmem.num_reads::total 197977 # Number of read requests responded to by this memory 46system.physmem.num_writes::writebacks 138659 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 49system.physmem.num_writes::total 143050 # Number of write requests responded to by this memory 50system.physmem.bw_read::cpu0.dtb.walker 2630 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.inst 578719 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.data 462749 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.l2cache.prefetcher 2933919 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.dtb.walker 292 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.inst 76313 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.data 226046 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.l2cache.prefetcher 156896 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::total 4437924 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu0.inst 578719 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::cpu1.inst 76313 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::total 655032 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_write::writebacks 3116778 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu0.data 6155 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::total 3122947 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_total::writebacks 3116778 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.dtb.walker 2630 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.inst 578719 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.data 468904 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.l2cache.prefetcher 2933919 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.dtb.walker 292 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.inst 76313 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.data 226060 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.l2cache.prefetcher 156896 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::total 7560871 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.readReqs 197977 # Number of read requests accepted 81system.physmem.writeReqs 143050 # Number of write requests accepted 82system.physmem.readBursts 197977 # Number of DRAM read bursts, including those serviced by the write queue 83system.physmem.writeBursts 143050 # Number of DRAM write bursts, including those merged in the write queue 84system.physmem.bytesReadDRAM 12661056 # Total number of bytes read from DRAM 85system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue 86system.physmem.bytesWritten 8904256 # Total number of bytes written to DRAM 87system.physmem.bytesReadSys 12635780 # Total read bytes from the system interface side 88system.physmem.bytesWrittenSys 8891740 # Total written bytes from the system interface side 89system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue 90system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 91system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 92system.physmem.perBankRdBursts::0 11990 # Per bank write bursts 93system.physmem.perBankRdBursts::1 12090 # Per bank write bursts 94system.physmem.perBankRdBursts::2 12710 # Per bank write bursts 95system.physmem.perBankRdBursts::3 12556 # Per bank write bursts 96system.physmem.perBankRdBursts::4 14859 # Per bank write bursts 97system.physmem.perBankRdBursts::5 12263 # Per bank write bursts 98system.physmem.perBankRdBursts::6 12121 # Per bank write bursts 99system.physmem.perBankRdBursts::7 12401 # Per bank write bursts 100system.physmem.perBankRdBursts::8 11839 # Per bank write bursts 101system.physmem.perBankRdBursts::9 11973 # Per bank write bursts 102system.physmem.perBankRdBursts::10 12288 # Per bank write bursts 103system.physmem.perBankRdBursts::11 11633 # Per bank write bursts 104system.physmem.perBankRdBursts::12 12418 # Per bank write bursts 105system.physmem.perBankRdBursts::13 12730 # Per bank write bursts 106system.physmem.perBankRdBursts::14 11938 # Per bank write bursts 107system.physmem.perBankRdBursts::15 12020 # Per bank write bursts 108system.physmem.perBankWrBursts::0 8637 # Per bank write bursts 109system.physmem.perBankWrBursts::1 8726 # Per bank write bursts 110system.physmem.perBankWrBursts::2 9304 # Per bank write bursts 111system.physmem.perBankWrBursts::3 8986 # Per bank write bursts 112system.physmem.perBankWrBursts::4 8078 # Per bank write bursts 113system.physmem.perBankWrBursts::5 8592 # Per bank write bursts 114system.physmem.perBankWrBursts::6 8645 # Per bank write bursts 115system.physmem.perBankWrBursts::7 8770 # Per bank write bursts 116system.physmem.perBankWrBursts::8 8363 # Per bank write bursts 117system.physmem.perBankWrBursts::9 8478 # Per bank write bursts 118system.physmem.perBankWrBursts::10 8927 # Per bank write bursts 119system.physmem.perBankWrBursts::11 8795 # Per bank write bursts 120system.physmem.perBankWrBursts::12 9084 # Per bank write bursts 121system.physmem.perBankWrBursts::13 8813 # Per bank write bursts 122system.physmem.perBankWrBursts::14 8578 # Per bank write bursts 123system.physmem.perBankWrBursts::15 8353 # Per bank write bursts 124system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 125system.physmem.numWrRetry 38 # Number of times write queue was full causing retry 126system.physmem.totGap 2847226871000 # Total gap between requests 127system.physmem.readPktSize::0 0 # Read request sizes (log2) 128system.physmem.readPktSize::1 0 # Read request sizes (log2) 129system.physmem.readPktSize::2 553 # Read request sizes (log2) 130system.physmem.readPktSize::3 28 # Read request sizes (log2) 131system.physmem.readPktSize::4 0 # Read request sizes (log2) 132system.physmem.readPktSize::5 0 # Read request sizes (log2) 133system.physmem.readPktSize::6 197396 # Read request sizes (log2) 134system.physmem.writePktSize::0 0 # Write request sizes (log2) 135system.physmem.writePktSize::1 0 # Write request sizes (log2) 136system.physmem.writePktSize::2 4391 # Write request sizes (log2) 137system.physmem.writePktSize::3 0 # Write request sizes (log2) 138system.physmem.writePktSize::4 0 # Write request sizes (log2) 139system.physmem.writePktSize::5 0 # Write request sizes (log2) 140system.physmem.writePktSize::6 138659 # Write request sizes (log2) 141system.physmem.rdQLenPdf::0 85811 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::1 62349 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::2 11580 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::3 9476 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::4 7635 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::5 6090 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::6 5109 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::7 4527 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::8 3699 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::9 718 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::10 266 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::11 256 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 2854 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 3807 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 6069 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 6494 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 7293 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 7710 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 8609 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 8584 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 9885 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 10553 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 9022 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::28 8775 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::29 10298 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 8486 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 7932 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 7714 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::33 641 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::34 524 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::35 348 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::37 212 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::39 196 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::40 176 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::46 191 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::47 127 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::58 68 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::63 145 # What write queue length does an incoming req see 237system.physmem.bytesPerActivate::samples 92332 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::mean 233.562015 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::gmean 132.589518 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::stdev 297.350425 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::0-127 50532 54.73% 54.73% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::128-255 17809 19.29% 74.02% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::256-383 6200 6.71% 80.73% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::384-511 3503 3.79% 84.53% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::512-639 2794 3.03% 87.55% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::640-767 1407 1.52% 89.08% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::768-895 909 0.98% 90.06% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::896-1023 989 1.07% 91.13% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::1024-1151 8189 8.87% 100.00% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::total 92332 # Bytes accessed per row activation 251system.physmem.rdPerTurnAround::samples 6903 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::mean 28.657830 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::stdev 561.171003 # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::0-2047 6902 99.99% 99.99% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::total 6903 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 6903 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 20.154860 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 18.644326 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 12.603874 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16-19 5813 84.21% 84.21% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::20-23 373 5.40% 89.61% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::24-27 70 1.01% 90.63% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::28-31 58 0.84% 91.47% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::32-35 265 3.84% 95.31% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::36-39 25 0.36% 95.67% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::40-43 18 0.26% 95.93% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::44-47 26 0.38% 96.31% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::48-51 14 0.20% 96.51% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::52-55 9 0.13% 96.64% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-59 3 0.04% 96.68% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::60-63 8 0.12% 96.80% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::64-67 153 2.22% 99.01% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::68-71 6 0.09% 99.10% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::72-75 6 0.09% 99.19% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::76-79 5 0.07% 99.26% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::80-83 5 0.07% 99.33% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::84-87 3 0.04% 99.38% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::88-91 3 0.04% 99.42% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::92-95 3 0.04% 99.46% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::96-99 1 0.01% 99.48% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::104-107 1 0.01% 99.49% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::108-111 8 0.12% 99.61% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::112-115 2 0.03% 99.64% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::116-119 1 0.01% 99.65% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::124-127 1 0.01% 99.67% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::128-131 9 0.13% 99.80% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::132-135 2 0.03% 99.83% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::156-159 1 0.01% 99.87% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::160-163 6 0.09% 99.96% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::188-191 2 0.03% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::total 6903 # Writes before turning the bus around for reads 295system.physmem.totQLat 5250518808 # Total ticks spent queuing 296system.physmem.totMemAccLat 8959812558 # Total ticks spent from burst creation until serviced by the DRAM 297system.physmem.totBusLat 989145000 # Total ticks spent in databus transfers 298system.physmem.avgQLat 26540.69 # Average queueing delay per DRAM burst 299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 300system.physmem.avgMemAccLat 45290.69 # Average memory access latency per DRAM burst 301system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s 302system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s 303system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s 304system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 306system.physmem.busUtil 0.06 # Data bus utilization in percentage 307system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 308system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 309system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 310system.physmem.avgWrQLen 23.07 # Average write queue length when enqueuing 311system.physmem.readRowHits 164412 # Number of row buffer hits during reads 312system.physmem.writeRowHits 80213 # Number of row buffer hits during writes 313system.physmem.readRowHitRate 83.11 # Row buffer hit rate for reads 314system.physmem.writeRowHitRate 57.64 # Row buffer hit rate for writes 315system.physmem.avgGap 8348977.86 # Average gap between requests 316system.physmem.pageHitRate 72.59 # Row buffer hit rate, read and write combined 317system.physmem_0.actEnergy 354957120 # Energy for activate commands per rank (pJ) 318system.physmem_0.preEnergy 193677000 # Energy for precharge commands per rank (pJ) 319system.physmem_0.readEnergy 787722000 # Energy for read commands per rank (pJ) 320system.physmem_0.writeEnergy 451902240 # Energy for write commands per rank (pJ) 321system.physmem_0.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) 322system.physmem_0.actBackEnergy 83190012300 # Energy for active background per rank (pJ) 323system.physmem_0.preBackEnergy 1635359290500 # Energy for precharge background per rank (pJ) 324system.physmem_0.totalEnergy 1906304222040 # Total energy per rank (pJ) 325system.physmem_0.averagePower 669.531375 # Core power per rank (mW) 326system.physmem_0.memoryStateTime::IDLE 2720439936839 # Time in different power states 327system.physmem_0.memoryStateTime::REF 95074980000 # Time in different power states 328system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 329system.physmem_0.memoryStateTime::ACT 31706739411 # Time in different power states 330system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 331system.physmem_1.actEnergy 343072800 # Energy for activate commands per rank (pJ) 332system.physmem_1.preEnergy 187192500 # Energy for precharge commands per rank (pJ) 333system.physmem_1.readEnergy 755336400 # Energy for read commands per rank (pJ) 334system.physmem_1.writeEnergy 449653680 # Energy for write commands per rank (pJ) 335system.physmem_1.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) 336system.physmem_1.actBackEnergy 82901008620 # Energy for active background per rank (pJ) 337system.physmem_1.preBackEnergy 1635612802500 # Energy for precharge background per rank (pJ) 338system.physmem_1.totalEnergy 1906215727380 # Total energy per rank (pJ) 339system.physmem_1.averagePower 669.500294 # Core power per rank (mW) 340system.physmem_1.memoryStateTime::IDLE 2720864046511 # Time in different power states 341system.physmem_1.memoryStateTime::REF 95074980000 # Time in different power states 342system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 343system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states 344system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 345system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 346system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 355system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) 364system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 365system.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 366system.bridge.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 367system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 368system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 369system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 370system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 371system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 372system.cf0.dma_write_txs 631 # Number of DMA write transactions. 373system.cpu0.branchPred.lookups 20737076 # Number of BP lookups 374system.cpu0.branchPred.condPredicted 13605991 # Number of conditional branches predicted 375system.cpu0.branchPred.condIncorrect 1017313 # Number of conditional branches incorrect 376system.cpu0.branchPred.BTBLookups 13202297 # Number of BTB lookups 377system.cpu0.branchPred.BTBHits 8722072 # Number of BTB hits 378system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 379system.cpu0.branchPred.BTBHitPct 66.064807 # BTB Hit Percentage 380system.cpu0.branchPred.usedRAS 3399643 # Number of times the RAS was used to get a target. 381system.cpu0.branchPred.RASInCorrect 216094 # Number of incorrect RAS predictions. 382system.cpu0.branchPred.indirectLookups 760668 # Number of indirect predictor lookups. 383system.cpu0.branchPred.indirectHits 581758 # Number of indirect target hits. 384system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses. 385system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches. 386system.cpu_clk_domain.clock 500 # Clock period in ticks 387system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 397system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 398system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 399system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 400system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 401system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 402system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 403system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 404system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 406system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 407system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 409system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 410system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 412system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 413system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 414system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 415system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 416system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 417system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 418system.cpu0.dtb.walker.walks 68420 # Table walker walks requested 419system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors 420system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate 421system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22328 # Level at which table walker walks with short descriptors terminate 422system.cpu0.dtb.walker.walkWaitTime::samples 68420 # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::0 68420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::total 68420 # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkCompletionTime::samples 6777 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::mean 12395.971669 # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::gmean 11546.443771 # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::stdev 5803.014677 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::0-16383 6374 94.05% 94.05% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::16384-32767 345 5.09% 99.14% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.69% 99.84% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::49152-65535 6 0.09% 99.93% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.99% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::total 6777 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution 437system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution 438system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution 439system.cpu0.dtb.walker.walkPageSizes::4K 5225 77.10% 77.10% # Table walker page sizes translated 440system.cpu0.dtb.walker.walkPageSizes::1M 1552 22.90% 100.00% # Table walker page sizes translated 441system.cpu0.dtb.walker.walkPageSizes::total 6777 # Table walker page sizes translated 442system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68420 # Table walker requests started/completed, data/inst 443system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68420 # Table walker requests started/completed, data/inst 445system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6777 # Table walker requests started/completed, data/inst 446system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777 # Table walker requests started/completed, data/inst 448system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst 449system.cpu0.dtb.inst_hits 0 # ITB inst hits 450system.cpu0.dtb.inst_misses 0 # ITB inst misses 451system.cpu0.dtb.read_hits 17339981 # DTB read hits 452system.cpu0.dtb.read_misses 61941 # DTB read misses 453system.cpu0.dtb.write_hits 14540400 # DTB write hits 454system.cpu0.dtb.write_misses 6479 # DTB write misses 455system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 456system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 457system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	12sim_insts 127319545 # Number of instructions simulated 13sim_ops 154173476 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8353536 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 643604 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 446720 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12635780 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1647744 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1865024 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8874176 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8891740 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 117 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 25746 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 21109 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 130524 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.data 10077 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.l2cache.prefetcher 6980 # Number of read requests responded to by this memory 44system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 45system.physmem.num_reads::total 197977 # Number of read requests responded to by this memory 46system.physmem.num_writes::writebacks 138659 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 49system.physmem.num_writes::total 143050 # Number of write requests responded to by this memory 50system.physmem.bw_read::cpu0.dtb.walker 2630 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.inst 578719 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.data 462749 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.l2cache.prefetcher 2933919 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.dtb.walker 292 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.inst 76313 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.data 226046 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.l2cache.prefetcher 156896 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::total 4437924 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu0.inst 578719 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::cpu1.inst 76313 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::total 655032 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_write::writebacks 3116778 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu0.data 6155 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::total 3122947 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_total::writebacks 3116778 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.dtb.walker 2630 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.inst 578719 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.data 468904 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.l2cache.prefetcher 2933919 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.dtb.walker 292 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.inst 76313 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.data 226060 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.l2cache.prefetcher 156896 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::total 7560871 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.readReqs 197977 # Number of read requests accepted 81system.physmem.writeReqs 143050 # Number of write requests accepted 82system.physmem.readBursts 197977 # Number of DRAM read bursts, including those serviced by the write queue 83system.physmem.writeBursts 143050 # Number of DRAM write bursts, including those merged in the write queue 84system.physmem.bytesReadDRAM 12661056 # Total number of bytes read from DRAM 85system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue 86system.physmem.bytesWritten 8904256 # Total number of bytes written to DRAM 87system.physmem.bytesReadSys 12635780 # Total read bytes from the system interface side 88system.physmem.bytesWrittenSys 8891740 # Total written bytes from the system interface side 89system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue 90system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 91system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 92system.physmem.perBankRdBursts::0 11990 # Per bank write bursts 93system.physmem.perBankRdBursts::1 12090 # Per bank write bursts 94system.physmem.perBankRdBursts::2 12710 # Per bank write bursts 95system.physmem.perBankRdBursts::3 12556 # Per bank write bursts 96system.physmem.perBankRdBursts::4 14859 # Per bank write bursts 97system.physmem.perBankRdBursts::5 12263 # Per bank write bursts 98system.physmem.perBankRdBursts::6 12121 # Per bank write bursts 99system.physmem.perBankRdBursts::7 12401 # Per bank write bursts 100system.physmem.perBankRdBursts::8 11839 # Per bank write bursts 101system.physmem.perBankRdBursts::9 11973 # Per bank write bursts 102system.physmem.perBankRdBursts::10 12288 # Per bank write bursts 103system.physmem.perBankRdBursts::11 11633 # Per bank write bursts 104system.physmem.perBankRdBursts::12 12418 # Per bank write bursts 105system.physmem.perBankRdBursts::13 12730 # Per bank write bursts 106system.physmem.perBankRdBursts::14 11938 # Per bank write bursts 107system.physmem.perBankRdBursts::15 12020 # Per bank write bursts 108system.physmem.perBankWrBursts::0 8637 # Per bank write bursts 109system.physmem.perBankWrBursts::1 8726 # Per bank write bursts 110system.physmem.perBankWrBursts::2 9304 # Per bank write bursts 111system.physmem.perBankWrBursts::3 8986 # Per bank write bursts 112system.physmem.perBankWrBursts::4 8078 # Per bank write bursts 113system.physmem.perBankWrBursts::5 8592 # Per bank write bursts 114system.physmem.perBankWrBursts::6 8645 # Per bank write bursts 115system.physmem.perBankWrBursts::7 8770 # Per bank write bursts 116system.physmem.perBankWrBursts::8 8363 # Per bank write bursts 117system.physmem.perBankWrBursts::9 8478 # Per bank write bursts 118system.physmem.perBankWrBursts::10 8927 # Per bank write bursts 119system.physmem.perBankWrBursts::11 8795 # Per bank write bursts 120system.physmem.perBankWrBursts::12 9084 # Per bank write bursts 121system.physmem.perBankWrBursts::13 8813 # Per bank write bursts 122system.physmem.perBankWrBursts::14 8578 # Per bank write bursts 123system.physmem.perBankWrBursts::15 8353 # Per bank write bursts 124system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 125system.physmem.numWrRetry 38 # Number of times write queue was full causing retry 126system.physmem.totGap 2847226871000 # Total gap between requests 127system.physmem.readPktSize::0 0 # Read request sizes (log2) 128system.physmem.readPktSize::1 0 # Read request sizes (log2) 129system.physmem.readPktSize::2 553 # Read request sizes (log2) 130system.physmem.readPktSize::3 28 # Read request sizes (log2) 131system.physmem.readPktSize::4 0 # Read request sizes (log2) 132system.physmem.readPktSize::5 0 # Read request sizes (log2) 133system.physmem.readPktSize::6 197396 # Read request sizes (log2) 134system.physmem.writePktSize::0 0 # Write request sizes (log2) 135system.physmem.writePktSize::1 0 # Write request sizes (log2) 136system.physmem.writePktSize::2 4391 # Write request sizes (log2) 137system.physmem.writePktSize::3 0 # Write request sizes (log2) 138system.physmem.writePktSize::4 0 # Write request sizes (log2) 139system.physmem.writePktSize::5 0 # Write request sizes (log2) 140system.physmem.writePktSize::6 138659 # Write request sizes (log2) 141system.physmem.rdQLenPdf::0 85811 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::1 62349 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::2 11580 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::3 9476 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::4 7635 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::5 6090 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::6 5109 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::7 4527 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::8 3699 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::9 718 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::10 266 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::11 256 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 2854 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 3807 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 6069 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 6494 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 7293 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 7710 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 8609 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 8584 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 9885 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 10553 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 9022 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::28 8775 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::29 10298 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 8486 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 7932 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 7714 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::33 641 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::34 524 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::35 348 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::37 212 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::39 196 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::40 176 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::46 191 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::47 127 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::58 68 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::63 145 # What write queue length does an incoming req see 237system.physmem.bytesPerActivate::samples 92332 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::mean 233.562015 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::gmean 132.589518 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::stdev 297.350425 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::0-127 50532 54.73% 54.73% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::128-255 17809 19.29% 74.02% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::256-383 6200 6.71% 80.73% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::384-511 3503 3.79% 84.53% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::512-639 2794 3.03% 87.55% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::640-767 1407 1.52% 89.08% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::768-895 909 0.98% 90.06% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::896-1023 989 1.07% 91.13% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::1024-1151 8189 8.87% 100.00% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::total 92332 # Bytes accessed per row activation 251system.physmem.rdPerTurnAround::samples 6903 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::mean 28.657830 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::stdev 561.171003 # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::0-2047 6902 99.99% 99.99% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::total 6903 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 6903 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 20.154860 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 18.644326 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 12.603874 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16-19 5813 84.21% 84.21% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::20-23 373 5.40% 89.61% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::24-27 70 1.01% 90.63% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::28-31 58 0.84% 91.47% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::32-35 265 3.84% 95.31% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::36-39 25 0.36% 95.67% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::40-43 18 0.26% 95.93% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::44-47 26 0.38% 96.31% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::48-51 14 0.20% 96.51% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::52-55 9 0.13% 96.64% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-59 3 0.04% 96.68% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::60-63 8 0.12% 96.80% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::64-67 153 2.22% 99.01% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::68-71 6 0.09% 99.10% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::72-75 6 0.09% 99.19% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::76-79 5 0.07% 99.26% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::80-83 5 0.07% 99.33% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::84-87 3 0.04% 99.38% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::88-91 3 0.04% 99.42% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::92-95 3 0.04% 99.46% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::96-99 1 0.01% 99.48% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::104-107 1 0.01% 99.49% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::108-111 8 0.12% 99.61% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::112-115 2 0.03% 99.64% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::116-119 1 0.01% 99.65% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::124-127 1 0.01% 99.67% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::128-131 9 0.13% 99.80% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::132-135 2 0.03% 99.83% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::156-159 1 0.01% 99.87% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::160-163 6 0.09% 99.96% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::188-191 2 0.03% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::total 6903 # Writes before turning the bus around for reads 295system.physmem.totQLat 5250518808 # Total ticks spent queuing 296system.physmem.totMemAccLat 8959812558 # Total ticks spent from burst creation until serviced by the DRAM 297system.physmem.totBusLat 989145000 # Total ticks spent in databus transfers 298system.physmem.avgQLat 26540.69 # Average queueing delay per DRAM burst 299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 300system.physmem.avgMemAccLat 45290.69 # Average memory access latency per DRAM burst 301system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s 302system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s 303system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s 304system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 306system.physmem.busUtil 0.06 # Data bus utilization in percentage 307system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 308system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 309system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 310system.physmem.avgWrQLen 23.07 # Average write queue length when enqueuing 311system.physmem.readRowHits 164412 # Number of row buffer hits during reads 312system.physmem.writeRowHits 80213 # Number of row buffer hits during writes 313system.physmem.readRowHitRate 83.11 # Row buffer hit rate for reads 314system.physmem.writeRowHitRate 57.64 # Row buffer hit rate for writes 315system.physmem.avgGap 8348977.86 # Average gap between requests 316system.physmem.pageHitRate 72.59 # Row buffer hit rate, read and write combined 317system.physmem_0.actEnergy 354957120 # Energy for activate commands per rank (pJ) 318system.physmem_0.preEnergy 193677000 # Energy for precharge commands per rank (pJ) 319system.physmem_0.readEnergy 787722000 # Energy for read commands per rank (pJ) 320system.physmem_0.writeEnergy 451902240 # Energy for write commands per rank (pJ) 321system.physmem_0.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) 322system.physmem_0.actBackEnergy 83190012300 # Energy for active background per rank (pJ) 323system.physmem_0.preBackEnergy 1635359290500 # Energy for precharge background per rank (pJ) 324system.physmem_0.totalEnergy 1906304222040 # Total energy per rank (pJ) 325system.physmem_0.averagePower 669.531375 # Core power per rank (mW) 326system.physmem_0.memoryStateTime::IDLE 2720439936839 # Time in different power states 327system.physmem_0.memoryStateTime::REF 95074980000 # Time in different power states 328system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 329system.physmem_0.memoryStateTime::ACT 31706739411 # Time in different power states 330system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 331system.physmem_1.actEnergy 343072800 # Energy for activate commands per rank (pJ) 332system.physmem_1.preEnergy 187192500 # Energy for precharge commands per rank (pJ) 333system.physmem_1.readEnergy 755336400 # Energy for read commands per rank (pJ) 334system.physmem_1.writeEnergy 449653680 # Energy for write commands per rank (pJ) 335system.physmem_1.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) 336system.physmem_1.actBackEnergy 82901008620 # Energy for active background per rank (pJ) 337system.physmem_1.preBackEnergy 1635612802500 # Energy for precharge background per rank (pJ) 338system.physmem_1.totalEnergy 1906215727380 # Total energy per rank (pJ) 339system.physmem_1.averagePower 669.500294 # Core power per rank (mW) 340system.physmem_1.memoryStateTime::IDLE 2720864046511 # Time in different power states 341system.physmem_1.memoryStateTime::REF 95074980000 # Time in different power states 342system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 343system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states 344system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 345system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 346system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 355system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) 364system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 365system.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 366system.bridge.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 367system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 368system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 369system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 370system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 371system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 372system.cf0.dma_write_txs 631 # Number of DMA write transactions. 373system.cpu0.branchPred.lookups 20737076 # Number of BP lookups 374system.cpu0.branchPred.condPredicted 13605991 # Number of conditional branches predicted 375system.cpu0.branchPred.condIncorrect 1017313 # Number of conditional branches incorrect 376system.cpu0.branchPred.BTBLookups 13202297 # Number of BTB lookups 377system.cpu0.branchPred.BTBHits 8722072 # Number of BTB hits 378system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 379system.cpu0.branchPred.BTBHitPct 66.064807 # BTB Hit Percentage 380system.cpu0.branchPred.usedRAS 3399643 # Number of times the RAS was used to get a target. 381system.cpu0.branchPred.RASInCorrect 216094 # Number of incorrect RAS predictions. 382system.cpu0.branchPred.indirectLookups 760668 # Number of indirect predictor lookups. 383system.cpu0.branchPred.indirectHits 581758 # Number of indirect target hits. 384system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses. 385system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches. 386system.cpu_clk_domain.clock 500 # Clock period in ticks 387system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 397system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 398system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 399system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 400system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 401system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 402system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 403system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 404system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 406system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 407system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 409system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 410system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 412system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 413system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 414system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 415system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 416system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 417system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 418system.cpu0.dtb.walker.walks 68420 # Table walker walks requested 419system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors 420system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate 421system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22328 # Level at which table walker walks with short descriptors terminate 422system.cpu0.dtb.walker.walkWaitTime::samples 68420 # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::0 68420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::total 68420 # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkCompletionTime::samples 6777 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::mean 12395.971669 # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::gmean 11546.443771 # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::stdev 5803.014677 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::0-16383 6374 94.05% 94.05% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::16384-32767 345 5.09% 99.14% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.69% 99.84% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::49152-65535 6 0.09% 99.93% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.99% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::total 6777 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution 437system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution 438system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution 439system.cpu0.dtb.walker.walkPageSizes::4K 5225 77.10% 77.10% # Table walker page sizes translated 440system.cpu0.dtb.walker.walkPageSizes::1M 1552 22.90% 100.00% # Table walker page sizes translated 441system.cpu0.dtb.walker.walkPageSizes::total 6777 # Table walker page sizes translated 442system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68420 # Table walker requests started/completed, data/inst 443system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68420 # Table walker requests started/completed, data/inst 445system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6777 # Table walker requests started/completed, data/inst 446system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777 # Table walker requests started/completed, data/inst 448system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst 449system.cpu0.dtb.inst_hits 0 # ITB inst hits 450system.cpu0.dtb.inst_misses 0 # ITB inst misses 451system.cpu0.dtb.read_hits 17339981 # DTB read hits 452system.cpu0.dtb.read_misses 61941 # DTB read misses 453system.cpu0.dtb.write_hits 14540400 # DTB write hits 454system.cpu0.dtb.write_misses 6479 # DTB write misses 455system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 456system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 457system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
459system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB	459system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB
460system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions 461system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch 462system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions 464system.cpu0.dtb.read_accesses 17401922 # DTB read accesses 465system.cpu0.dtb.write_accesses 14546879 # DTB write accesses 466system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 467system.cpu0.dtb.hits 31880381 # DTB hits 468system.cpu0.dtb.misses 68420 # DTB misses 469system.cpu0.dtb.accesses 31948801 # DTB accesses 470system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 471system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 473system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 475system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 479system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 480system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 481system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 482system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 483system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 484system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 485system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 486system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 487system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 488system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 489system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 490system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 491system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 492system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 493system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 494system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 495system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 496system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 497system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 498system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 499system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 500system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 501system.cpu0.itb.walker.walks 3977 # Table walker walks requested 502system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors 503system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate 504system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3673 # Level at which table walker walks with short descriptors terminate 505system.cpu0.itb.walker.walkWaitTime::samples 3977 # Table walker wait (enqueue to first request) latency 506system.cpu0.itb.walker.walkWaitTime::0 3977 100.00% 100.00% # Table walker wait (enqueue to first request) latency 507system.cpu0.itb.walker.walkWaitTime::total 3977 # Table walker wait (enqueue to first request) latency 508system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency 509system.cpu0.itb.walker.walkCompletionTime::mean 12713.811696 # Table walker service (enqueue to completion) latency 510system.cpu0.itb.walker.walkCompletionTime::gmean 12041.525578 # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::stdev 4752.572139 # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::0-8191 358 14.85% 14.85% # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::8192-16383 1847 76.61% 91.46% # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::16384-24575 161 6.68% 98.13% # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::24576-32767 17 0.71% 98.84% # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.08% 99.92% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution 521system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution 522system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution 523system.cpu0.itb.walker.walkPageSizes::4K 2112 87.60% 87.60% # Table walker page sizes translated 524system.cpu0.itb.walker.walkPageSizes::1M 299 12.40% 100.00% # Table walker page sizes translated 525system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated 526system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 527system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3977 # Table walker requests started/completed, data/inst 528system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3977 # Table walker requests started/completed, data/inst 529system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 530system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst 531system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst 532system.cpu0.itb.walker.walkRequestOrigin::total 6388 # Table walker requests started/completed, data/inst 533system.cpu0.itb.inst_hits 38606266 # ITB inst hits 534system.cpu0.itb.inst_misses 3977 # ITB inst misses 535system.cpu0.itb.read_hits 0 # DTB read hits 536system.cpu0.itb.read_misses 0 # DTB read misses 537system.cpu0.itb.write_hits 0 # DTB write hits 538system.cpu0.itb.write_misses 0 # DTB write misses 539system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 540system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 541system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 542system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	460system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions 461system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch 462system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions 464system.cpu0.dtb.read_accesses 17401922 # DTB read accesses 465system.cpu0.dtb.write_accesses 14546879 # DTB write accesses 466system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 467system.cpu0.dtb.hits 31880381 # DTB hits 468system.cpu0.dtb.misses 68420 # DTB misses 469system.cpu0.dtb.accesses 31948801 # DTB accesses 470system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 471system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 473system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 475system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 479system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 480system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 481system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 482system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 483system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 484system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 485system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 486system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 487system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 488system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 489system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 490system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 491system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 492system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 493system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 494system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 495system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 496system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 497system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 498system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 499system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 500system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 501system.cpu0.itb.walker.walks 3977 # Table walker walks requested 502system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors 503system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate 504system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3673 # Level at which table walker walks with short descriptors terminate 505system.cpu0.itb.walker.walkWaitTime::samples 3977 # Table walker wait (enqueue to first request) latency 506system.cpu0.itb.walker.walkWaitTime::0 3977 100.00% 100.00% # Table walker wait (enqueue to first request) latency 507system.cpu0.itb.walker.walkWaitTime::total 3977 # Table walker wait (enqueue to first request) latency 508system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency 509system.cpu0.itb.walker.walkCompletionTime::mean 12713.811696 # Table walker service (enqueue to completion) latency 510system.cpu0.itb.walker.walkCompletionTime::gmean 12041.525578 # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::stdev 4752.572139 # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::0-8191 358 14.85% 14.85% # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::8192-16383 1847 76.61% 91.46% # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::16384-24575 161 6.68% 98.13% # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::24576-32767 17 0.71% 98.84% # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.08% 99.92% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution 521system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution 522system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution 523system.cpu0.itb.walker.walkPageSizes::4K 2112 87.60% 87.60% # Table walker page sizes translated 524system.cpu0.itb.walker.walkPageSizes::1M 299 12.40% 100.00% # Table walker page sizes translated 525system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated 526system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 527system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3977 # Table walker requests started/completed, data/inst 528system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3977 # Table walker requests started/completed, data/inst 529system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 530system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst 531system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst 532system.cpu0.itb.walker.walkRequestOrigin::total 6388 # Table walker requests started/completed, data/inst 533system.cpu0.itb.inst_hits 38606266 # ITB inst hits 534system.cpu0.itb.inst_misses 3977 # ITB inst misses 535system.cpu0.itb.read_hits 0 # DTB read hits 536system.cpu0.itb.read_misses 0 # DTB read misses 537system.cpu0.itb.write_hits 0 # DTB write hits 538system.cpu0.itb.write_misses 0 # DTB write misses 539system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 540system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 541system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 542system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
543system.cpu0.itb.flush_entries 2216 # Number of entries that have been flushed from TLB	543system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB
544system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 545system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 546system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 547system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions 548system.cpu0.itb.read_accesses 0 # DTB read accesses 549system.cpu0.itb.write_accesses 0 # DTB write accesses 550system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses 551system.cpu0.itb.hits 38606266 # DTB hits 552system.cpu0.itb.misses 3977 # DTB misses 553system.cpu0.itb.accesses 38610243 # DTB accesses 554system.cpu0.numPwrStateTransitions 3704 # Number of power state transitions 555system.cpu0.pwrStateClkGateDist::samples 1852 # Distribution of time spent in the clock gated state 556system.cpu0.pwrStateClkGateDist::mean 1492233091.644168 # Distribution of time spent in the clock gated state 557system.cpu0.pwrStateClkGateDist::stdev 23940880637.068275 # Distribution of time spent in the clock gated state 558system.cpu0.pwrStateClkGateDist::underflows 1073 57.94% 57.94% # Distribution of time spent in the clock gated state 559system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.68% 99.62% # Distribution of time spent in the clock gated state 560system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state 561system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state 562system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 563system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 564system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 565system.cpu0.pwrStateClkGateDist::max_value 499965331660 # Distribution of time spent in the clock gated state 566system.cpu0.pwrStateClkGateDist::total 1852 # Distribution of time spent in the clock gated state 567system.cpu0.pwrStateResidencyTicks::ON 83611720275 # Cumulative time (in ticks) in various power states 568system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763615685725 # Cumulative time (in ticks) in various power states 569system.cpu0.numCycles 167224982 # number of cpu cycles simulated 570system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 571system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 572system.cpu0.committedInsts 79715648 # Number of instructions committed 573system.cpu0.committedOps 95927461 # Number of ops (including micro ops) committed 574system.cpu0.discardedOps 5237247 # Number of ops (including micro ops) which were discarded before commit 575system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching 576system.cpu0.quiesceCycles 5527254348 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 577system.cpu0.cpi 2.097769 # CPI: cycles per instruction 578system.cpu0.ipc 0.476697 # IPC: instructions per cycle 579system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction 580system.cpu0.op_class_0::IntAlu 63730677 66.44% 66.44% # Class of committed instruction 581system.cpu0.op_class_0::IntMult 92076 0.10% 66.53% # Class of committed instruction 582system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction 583system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction 584system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction 585system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction 586system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction 587system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction 588system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction 589system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction 590system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction 591system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction 592system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction 593system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction 594system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction 595system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction 596system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction 597system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction 598system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction 599system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction 600system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction 601system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction 602system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction 603system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction 604system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction 605system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction 606system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction 607system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction 608system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction 609system.cpu0.op_class_0::MemRead 16811055 17.52% 84.07% # Class of committed instruction 610system.cpu0.op_class_0::MemWrite 15283265 15.93% 100.00% # Class of committed instruction 611system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 612system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 613system.cpu0.op_class_0::total 95927461 # Class of committed instruction 614system.cpu0.kern.inst.arm 0 # number of arm instructions executed 615system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed 616system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked 617system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped 618system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 619system.cpu0.dcache.tags.replacements 715130 # number of replacements 620system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use 621system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks. 622system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. 623system.cpu0.dcache.tags.avg_refs 42.471892 # Average number of references to valid blocks. 624system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. 625system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor 626system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy 627system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy 628system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 629system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 630system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id 631system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 632system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 633system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses 634system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses 635system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 636system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits 637system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits 638system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits 639system.cpu0.dcache.WriteReq_hits::total 13424812 # number of WriteReq hits 640system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits 641system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits 642system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits 643system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits 644system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080 # number of StoreCondReq hits 645system.cpu0.dcache.StoreCondReq_hits::total 361080 # number of StoreCondReq hits 646system.cpu0.dcache.demand_hits::cpu0.data 29235144 # number of demand (read+write) hits 647system.cpu0.dcache.demand_hits::total 29235144 # number of demand (read+write) hits 648system.cpu0.dcache.overall_hits::cpu0.data 29555584 # number of overall hits 649system.cpu0.dcache.overall_hits::total 29555584 # number of overall hits 650system.cpu0.dcache.ReadReq_misses::cpu0.data 463723 # number of ReadReq misses 651system.cpu0.dcache.ReadReq_misses::total 463723 # number of ReadReq misses 652system.cpu0.dcache.WriteReq_misses::cpu0.data 580901 # number of WriteReq misses 653system.cpu0.dcache.WriteReq_misses::total 580901 # number of WriteReq misses 654system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136483 # number of SoftPFReq misses 655system.cpu0.dcache.SoftPFReq_misses::total 136483 # number of SoftPFReq misses 656system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21307 # number of LoadLockedReq misses 657system.cpu0.dcache.LoadLockedReq_misses::total 21307 # number of LoadLockedReq misses 658system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20567 # number of StoreCondReq misses 659system.cpu0.dcache.StoreCondReq_misses::total 20567 # number of StoreCondReq misses 660system.cpu0.dcache.demand_misses::cpu0.data 1044624 # number of demand (read+write) misses 661system.cpu0.dcache.demand_misses::total 1044624 # number of demand (read+write) misses 662system.cpu0.dcache.overall_misses::cpu0.data 1181107 # number of overall misses 663system.cpu0.dcache.overall_misses::total 1181107 # number of overall misses 664system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6183627500 # number of ReadReq miss cycles 665system.cpu0.dcache.ReadReq_miss_latency::total 6183627500 # number of ReadReq miss cycles 666system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10315375000 # number of WriteReq miss cycles 667system.cpu0.dcache.WriteReq_miss_latency::total 10315375000 # number of WriteReq miss cycles 668system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 321766500 # number of LoadLockedReq miss cycles 669system.cpu0.dcache.LoadLockedReq_miss_latency::total 321766500 # number of LoadLockedReq miss cycles 670system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 497952500 # number of StoreCondReq miss cycles 671system.cpu0.dcache.StoreCondReq_miss_latency::total 497952500 # number of StoreCondReq miss cycles 672system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 229500 # number of StoreCondFailReq miss cycles 673system.cpu0.dcache.StoreCondFailReq_miss_latency::total 229500 # number of StoreCondFailReq miss cycles 674system.cpu0.dcache.demand_miss_latency::cpu0.data 16499002500 # number of demand (read+write) miss cycles 675system.cpu0.dcache.demand_miss_latency::total 16499002500 # number of demand (read+write) miss cycles 676system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500 # number of overall miss cycles 677system.cpu0.dcache.overall_miss_latency::total 16499002500 # number of overall miss cycles 678system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274055 # number of ReadReq accesses(hits+misses) 679system.cpu0.dcache.ReadReq_accesses::total 16274055 # number of ReadReq accesses(hits+misses) 680system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005713 # number of WriteReq accesses(hits+misses) 681system.cpu0.dcache.WriteReq_accesses::total 14005713 # number of WriteReq accesses(hits+misses) 682system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923 # number of SoftPFReq accesses(hits+misses) 683system.cpu0.dcache.SoftPFReq_accesses::total 456923 # number of SoftPFReq accesses(hits+misses) 684system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533 # number of LoadLockedReq accesses(hits+misses) 685system.cpu0.dcache.LoadLockedReq_accesses::total 386533 # number of LoadLockedReq accesses(hits+misses) 686system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647 # number of StoreCondReq accesses(hits+misses) 687system.cpu0.dcache.StoreCondReq_accesses::total 381647 # number of StoreCondReq accesses(hits+misses) 688system.cpu0.dcache.demand_accesses::cpu0.data 30279768 # number of demand (read+write) accesses 689system.cpu0.dcache.demand_accesses::total 30279768 # number of demand (read+write) accesses 690system.cpu0.dcache.overall_accesses::cpu0.data 30736691 # number of overall (read+write) accesses 691system.cpu0.dcache.overall_accesses::total 30736691 # number of overall (read+write) accesses 692system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses 693system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses 694system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses 695system.cpu0.dcache.WriteReq_miss_rate::total 0.041476 # miss rate for WriteReq accesses 696system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298700 # miss rate for SoftPFReq accesses 697system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298700 # miss rate for SoftPFReq accesses 698system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055123 # miss rate for LoadLockedReq accesses 699system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055123 # miss rate for LoadLockedReq accesses 700system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053890 # miss rate for StoreCondReq accesses 701system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053890 # miss rate for StoreCondReq accesses 702system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034499 # miss rate for demand accesses 703system.cpu0.dcache.demand_miss_rate::total 0.034499 # miss rate for demand accesses 704system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038427 # miss rate for overall accesses 705system.cpu0.dcache.overall_miss_rate::total 0.038427 # miss rate for overall accesses 706system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13334.744017 # average ReadReq miss latency 707system.cpu0.dcache.ReadReq_avg_miss_latency::total 13334.744017 # average ReadReq miss latency 708system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17757.543884 # average WriteReq miss latency 709system.cpu0.dcache.WriteReq_avg_miss_latency::total 17757.543884 # average WriteReq miss latency 710system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15101.445534 # average LoadLockedReq miss latency 711system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15101.445534 # average LoadLockedReq miss latency 712system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24211.236447 # average StoreCondReq miss latency 713system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24211.236447 # average StoreCondReq miss latency 714system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 715system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 716system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15794.202029 # average overall miss latency 717system.cpu0.dcache.demand_avg_miss_latency::total 15794.202029 # average overall miss latency 718system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13969.100598 # average overall miss latency 719system.cpu0.dcache.overall_avg_miss_latency::total 13969.100598 # average overall miss latency 720system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 721system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 722system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 723system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 724system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 725system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 726system.cpu0.dcache.writebacks::writebacks 715130 # number of writebacks 727system.cpu0.dcache.writebacks::total 715130 # number of writebacks 728system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 71798 # number of ReadReq MSHR hits 729system.cpu0.dcache.ReadReq_mshr_hits::total 71798 # number of ReadReq MSHR hits 730system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255281 # number of WriteReq MSHR hits 731system.cpu0.dcache.WriteReq_mshr_hits::total 255281 # number of WriteReq MSHR hits 732system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14780 # number of LoadLockedReq MSHR hits 733system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14780 # number of LoadLockedReq MSHR hits 734system.cpu0.dcache.demand_mshr_hits::cpu0.data 327079 # number of demand (read+write) MSHR hits 735system.cpu0.dcache.demand_mshr_hits::total 327079 # number of demand (read+write) MSHR hits 736system.cpu0.dcache.overall_mshr_hits::cpu0.data 327079 # number of overall MSHR hits 737system.cpu0.dcache.overall_mshr_hits::total 327079 # number of overall MSHR hits 738system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391925 # number of ReadReq MSHR misses 739system.cpu0.dcache.ReadReq_mshr_misses::total 391925 # number of ReadReq MSHR misses 740system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325620 # number of WriteReq MSHR misses 741system.cpu0.dcache.WriteReq_mshr_misses::total 325620 # number of WriteReq MSHR misses 742system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103078 # number of SoftPFReq MSHR misses 743system.cpu0.dcache.SoftPFReq_mshr_misses::total 103078 # number of SoftPFReq MSHR misses 744system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6527 # number of LoadLockedReq MSHR misses 745system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6527 # number of LoadLockedReq MSHR misses 746system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20567 # number of StoreCondReq MSHR misses 747system.cpu0.dcache.StoreCondReq_mshr_misses::total 20567 # number of StoreCondReq MSHR misses 748system.cpu0.dcache.demand_mshr_misses::cpu0.data 717545 # number of demand (read+write) MSHR misses 749system.cpu0.dcache.demand_mshr_misses::total 717545 # number of demand (read+write) MSHR misses 750system.cpu0.dcache.overall_mshr_misses::cpu0.data 820623 # number of overall MSHR misses 751system.cpu0.dcache.overall_mshr_misses::total 820623 # number of overall MSHR misses 752system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable 753system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20575 # number of ReadReq MSHR uncacheable 754system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable 755system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19271 # number of WriteReq MSHR uncacheable 756system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses 757system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses 758system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4674150000 # number of ReadReq MSHR miss cycles 759system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4674150000 # number of ReadReq MSHR miss cycles 760system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5703236000 # number of WriteReq MSHR miss cycles 761system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5703236000 # number of WriteReq MSHR miss cycles 762system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1673631500 # number of SoftPFReq MSHR miss cycles 763system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1673631500 # number of SoftPFReq MSHR miss cycles 764system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101407500 # number of LoadLockedReq MSHR miss cycles 765system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101407500 # number of LoadLockedReq MSHR miss cycles 766system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 477391500 # number of StoreCondReq MSHR miss cycles 767system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 477391500 # number of StoreCondReq MSHR miss cycles 768system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles 769system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles 770system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10377386000 # number of demand (read+write) MSHR miss cycles 771system.cpu0.dcache.demand_mshr_miss_latency::total 10377386000 # number of demand (read+write) MSHR miss cycles 772system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12051017500 # number of overall MSHR miss cycles 773system.cpu0.dcache.overall_mshr_miss_latency::total 12051017500 # number of overall MSHR miss cycles 774system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4615609000 # number of ReadReq MSHR uncacheable cycles 775system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4615609000 # number of ReadReq MSHR uncacheable cycles 776system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4615609000 # number of overall MSHR uncacheable cycles 777system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4615609000 # number of overall MSHR uncacheable cycles 778system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024083 # mshr miss rate for ReadReq accesses 779system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024083 # mshr miss rate for ReadReq accesses 780system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses 781system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses 782system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225592 # mshr miss rate for SoftPFReq accesses 783system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225592 # mshr miss rate for SoftPFReq accesses 784system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016886 # mshr miss rate for LoadLockedReq accesses 785system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016886 # mshr miss rate for LoadLockedReq accesses 786system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053890 # mshr miss rate for StoreCondReq accesses 787system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053890 # mshr miss rate for StoreCondReq accesses 788system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023697 # mshr miss rate for demand accesses 789system.cpu0.dcache.demand_mshr_miss_rate::total 0.023697 # mshr miss rate for demand accesses 790system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026698 # mshr miss rate for overall accesses 791system.cpu0.dcache.overall_mshr_miss_rate::total 0.026698 # mshr miss rate for overall accesses 792system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11926.133827 # average ReadReq mshr miss latency 793system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11926.133827 # average ReadReq mshr miss latency 794system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17515.005221 # average WriteReq mshr miss latency 795system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17515.005221 # average WriteReq mshr miss latency 796system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16236.553872 # average SoftPFReq mshr miss latency 797system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16236.553872 # average SoftPFReq mshr miss latency 798system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15536.617129 # average LoadLockedReq mshr miss latency 799system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15536.617129 # average LoadLockedReq mshr miss latency 800system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23211.528176 # average StoreCondReq mshr miss latency 801system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23211.528176 # average StoreCondReq mshr miss latency 802system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 803system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 804system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14462.348703 # average overall mshr miss latency 805system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14462.348703 # average overall mshr miss latency 806system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14685.205630 # average overall mshr miss latency 807system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14685.205630 # average overall mshr miss latency 808system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 224330.935601 # average ReadReq mshr uncacheable latency 809system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601 # average ReadReq mshr uncacheable latency 810system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348 # average overall mshr uncacheable latency 811system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348 # average overall mshr uncacheable latency 812system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 813system.cpu0.icache.tags.replacements 1962004 # number of replacements 814system.cpu0.icache.tags.tagsinuse 511.774944 # Cycle average of tags in use 815system.cpu0.icache.tags.total_refs 36636559 # Total number of references to valid blocks. 816system.cpu0.icache.tags.sampled_refs 1962516 # Sample count of references to valid blocks. 817system.cpu0.icache.tags.avg_refs 18.668158 # Average number of references to valid blocks. 818system.cpu0.icache.tags.warmup_cycle 6612168000 # Cycle when the warmup percentage was hit. 819system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774944 # Average occupied blocks per requestor 820system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy 821system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy 822system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 823system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 824system.cpu0.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 825system.cpu0.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id 826system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 827system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses 828system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses 829system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 830system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits 831system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits 832system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits 833system.cpu0.icache.demand_hits::total 36636559 # number of demand (read+write) hits 834system.cpu0.icache.overall_hits::cpu0.inst 36636559 # number of overall hits 835system.cpu0.icache.overall_hits::total 36636559 # number of overall hits 836system.cpu0.icache.ReadReq_misses::cpu0.inst 1962531 # number of ReadReq misses 837system.cpu0.icache.ReadReq_misses::total 1962531 # number of ReadReq misses 838system.cpu0.icache.demand_misses::cpu0.inst 1962531 # number of demand (read+write) misses 839system.cpu0.icache.demand_misses::total 1962531 # number of demand (read+write) misses 840system.cpu0.icache.overall_misses::cpu0.inst 1962531 # number of overall misses 841system.cpu0.icache.overall_misses::total 1962531 # number of overall misses 842system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18757498000 # number of ReadReq miss cycles 843system.cpu0.icache.ReadReq_miss_latency::total 18757498000 # number of ReadReq miss cycles 844system.cpu0.icache.demand_miss_latency::cpu0.inst 18757498000 # number of demand (read+write) miss cycles 845system.cpu0.icache.demand_miss_latency::total 18757498000 # number of demand (read+write) miss cycles 846system.cpu0.icache.overall_miss_latency::cpu0.inst 18757498000 # number of overall miss cycles 847system.cpu0.icache.overall_miss_latency::total 18757498000 # number of overall miss cycles 848system.cpu0.icache.ReadReq_accesses::cpu0.inst 38599090 # number of ReadReq accesses(hits+misses) 849system.cpu0.icache.ReadReq_accesses::total 38599090 # number of ReadReq accesses(hits+misses) 850system.cpu0.icache.demand_accesses::cpu0.inst 38599090 # number of demand (read+write) accesses 851system.cpu0.icache.demand_accesses::total 38599090 # number of demand (read+write) accesses 852system.cpu0.icache.overall_accesses::cpu0.inst 38599090 # number of overall (read+write) accesses 853system.cpu0.icache.overall_accesses::total 38599090 # number of overall (read+write) accesses 854system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050844 # miss rate for ReadReq accesses 855system.cpu0.icache.ReadReq_miss_rate::total 0.050844 # miss rate for ReadReq accesses 856system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050844 # miss rate for demand accesses 857system.cpu0.icache.demand_miss_rate::total 0.050844 # miss rate for demand accesses 858system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050844 # miss rate for overall accesses 859system.cpu0.icache.overall_miss_rate::total 0.050844 # miss rate for overall accesses 860system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9557.809787 # average ReadReq miss latency 861system.cpu0.icache.ReadReq_avg_miss_latency::total 9557.809787 # average ReadReq miss latency 862system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency 863system.cpu0.icache.demand_avg_miss_latency::total 9557.809787 # average overall miss latency 864system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency 865system.cpu0.icache.overall_avg_miss_latency::total 9557.809787 # average overall miss latency 866system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 867system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 868system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 869system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 870system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 871system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 872system.cpu0.icache.writebacks::writebacks 1962004 # number of writebacks 873system.cpu0.icache.writebacks::total 1962004 # number of writebacks 874system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1962531 # number of ReadReq MSHR misses 875system.cpu0.icache.ReadReq_mshr_misses::total 1962531 # number of ReadReq MSHR misses 876system.cpu0.icache.demand_mshr_misses::cpu0.inst 1962531 # number of demand (read+write) MSHR misses 877system.cpu0.icache.demand_mshr_misses::total 1962531 # number of demand (read+write) MSHR misses 878system.cpu0.icache.overall_mshr_misses::cpu0.inst 1962531 # number of overall MSHR misses 879system.cpu0.icache.overall_mshr_misses::total 1962531 # number of overall MSHR misses 880system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable 881system.cpu0.icache.ReadReq_mshr_uncacheable::total 3449 # number of ReadReq MSHR uncacheable 882system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses 883system.cpu0.icache.overall_mshr_uncacheable_misses::total 3449 # number of overall MSHR uncacheable misses 884system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17776233000 # number of ReadReq MSHR miss cycles 885system.cpu0.icache.ReadReq_mshr_miss_latency::total 17776233000 # number of ReadReq MSHR miss cycles 886system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17776233000 # number of demand (read+write) MSHR miss cycles 887system.cpu0.icache.demand_mshr_miss_latency::total 17776233000 # number of demand (read+write) MSHR miss cycles 888system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17776233000 # number of overall MSHR miss cycles 889system.cpu0.icache.overall_mshr_miss_latency::total 17776233000 # number of overall MSHR miss cycles 890system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319470000 # number of ReadReq MSHR uncacheable cycles 891system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319470000 # number of ReadReq MSHR uncacheable cycles 892system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319470000 # number of overall MSHR uncacheable cycles 893system.cpu0.icache.overall_mshr_uncacheable_latency::total 319470000 # number of overall MSHR uncacheable cycles 894system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for ReadReq accesses 895system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050844 # mshr miss rate for ReadReq accesses 896system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for demand accesses 897system.cpu0.icache.demand_mshr_miss_rate::total 0.050844 # mshr miss rate for demand accesses 898system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for overall accesses 899system.cpu0.icache.overall_mshr_miss_rate::total 0.050844 # mshr miss rate for overall accesses 900system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average ReadReq mshr miss latency 901system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9057.810042 # average ReadReq mshr miss latency 902system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency 903system.cpu0.icache.demand_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency 904system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency 905system.cpu0.icache.overall_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency 906system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average ReadReq mshr uncacheable latency 907system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency 908system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency 909system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency 910system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 911system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued 912system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified 913system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue 914system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 915system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 916system.cpu0.l2cache.prefetcher.pfSpanPage 233630 # number of prefetches not generated due to page crossing 917system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 918system.cpu0.l2cache.tags.replacements 298119 # number of replacements 919system.cpu0.l2cache.tags.tagsinuse 16125.660847 # Cycle average of tags in use 920system.cpu0.l2cache.tags.total_refs 4682482 # Total number of references to valid blocks. 921system.cpu0.l2cache.tags.sampled_refs 314209 # Sample count of references to valid blocks. 922system.cpu0.l2cache.tags.avg_refs 14.902444 # Average number of references to valid blocks. 923system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 924system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.008973 # Average occupied blocks per requestor 925system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.059574 # Average occupied blocks per requestor 926system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.057522 # Average occupied blocks per requestor 927system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1311.534778 # Average occupied blocks per requestor 928system.cpu0.l2cache.tags.occ_percent::writebacks 0.900635 # Average percentage of cache occupancy 929system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003544 # Average percentage of cache occupancy 930system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 931system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.080050 # Average percentage of cache occupancy 932system.cpu0.l2cache.tags.occ_percent::total 0.984232 # Average percentage of cache occupancy 933system.cpu0.l2cache.tags.occ_task_id_blocks::1022 965 # Occupied blocks per task id 934system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 935system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15115 # Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id 938system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 400 # Occupied blocks per task id 939system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 257 # Occupied blocks per task id 940system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 941system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 942system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 943system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 944system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 945system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4162 # Occupied blocks per task id 946system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7775 # Occupied blocks per task id 947system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2779 # Occupied blocks per task id 948system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058899 # Percentage of cache occupancy per task id 949system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 950system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id 951system.cpu0.l2cache.tags.tag_accesses 89320549 # Number of tag accesses 952system.cpu0.l2cache.tags.data_accesses 89320549 # Number of data accesses 953system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 954system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82730 # number of ReadReq hits 955system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5417 # number of ReadReq hits 956system.cpu0.l2cache.ReadReq_hits::total 88147 # number of ReadReq hits 957system.cpu0.l2cache.WritebackDirty_hits::writebacks 481961 # number of WritebackDirty hits 958system.cpu0.l2cache.WritebackDirty_hits::total 481961 # number of WritebackDirty hits 959system.cpu0.l2cache.WritebackClean_hits::writebacks 2152508 # number of WritebackClean hits 960system.cpu0.l2cache.WritebackClean_hits::total 2152508 # number of WritebackClean hits 961system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits 962system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 963system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222191 # number of ReadExReq hits 964system.cpu0.l2cache.ReadExReq_hits::total 222191 # number of ReadExReq hits 965system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1894118 # number of ReadCleanReq hits 966system.cpu0.l2cache.ReadCleanReq_hits::total 1894118 # number of ReadCleanReq hits 967system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 400891 # number of ReadSharedReq hits 968system.cpu0.l2cache.ReadSharedReq_hits::total 400891 # number of ReadSharedReq hits 969system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 82730 # number of demand (read+write) hits 970system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5417 # number of demand (read+write) hits 971system.cpu0.l2cache.demand_hits::cpu0.inst 1894118 # number of demand (read+write) hits 972system.cpu0.l2cache.demand_hits::cpu0.data 623082 # number of demand (read+write) hits 973system.cpu0.l2cache.demand_hits::total 2605347 # number of demand (read+write) hits 974system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 82730 # number of overall hits 975system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5417 # number of overall hits 976system.cpu0.l2cache.overall_hits::cpu0.inst 1894118 # number of overall hits 977system.cpu0.l2cache.overall_hits::cpu0.data 623082 # number of overall hits 978system.cpu0.l2cache.overall_hits::total 2605347 # number of overall hits 979system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 856 # number of ReadReq misses 980system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 128 # number of ReadReq misses 981system.cpu0.l2cache.ReadReq_misses::total 984 # number of ReadReq misses 982system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56746 # number of UpgradeReq misses 983system.cpu0.l2cache.UpgradeReq_misses::total 56746 # number of UpgradeReq misses 984system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20566 # number of SCUpgradeReq misses 985system.cpu0.l2cache.SCUpgradeReq_misses::total 20566 # number of SCUpgradeReq misses 986system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 987system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 988system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46690 # number of ReadExReq misses 989system.cpu0.l2cache.ReadExReq_misses::total 46690 # number of ReadExReq misses 990system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 68413 # number of ReadCleanReq misses 991system.cpu0.l2cache.ReadCleanReq_misses::total 68413 # number of ReadCleanReq misses 992system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100633 # number of ReadSharedReq misses 993system.cpu0.l2cache.ReadSharedReq_misses::total 100633 # number of ReadSharedReq misses 994system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 856 # number of demand (read+write) misses 995system.cpu0.l2cache.demand_misses::cpu0.itb.walker 128 # number of demand (read+write) misses 996system.cpu0.l2cache.demand_misses::cpu0.inst 68413 # number of demand (read+write) misses 997system.cpu0.l2cache.demand_misses::cpu0.data 147323 # number of demand (read+write) misses 998system.cpu0.l2cache.demand_misses::total 216720 # number of demand (read+write) misses 999system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 856 # number of overall misses 1000system.cpu0.l2cache.overall_misses::cpu0.itb.walker 128 # number of overall misses 1001system.cpu0.l2cache.overall_misses::cpu0.inst 68413 # number of overall misses 1002system.cpu0.l2cache.overall_misses::cpu0.data 147323 # number of overall misses 1003system.cpu0.l2cache.overall_misses::total 216720 # number of overall misses 1004system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 28767000 # number of ReadReq miss cycles 1005system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2997000 # number of ReadReq miss cycles 1006system.cpu0.l2cache.ReadReq_miss_latency::total 31764000 # number of ReadReq miss cycles 1007system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 121525500 # number of UpgradeReq miss cycles 1008system.cpu0.l2cache.UpgradeReq_miss_latency::total 121525500 # number of UpgradeReq miss cycles 1009system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 25214000 # number of SCUpgradeReq miss cycles 1010system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 25214000 # number of SCUpgradeReq miss cycles 1011system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 212499 # number of SCUpgradeFailReq miss cycles 1012system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 212499 # number of SCUpgradeFailReq miss cycles 1013system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2304231000 # number of ReadExReq miss cycles 1014system.cpu0.l2cache.ReadExReq_miss_latency::total 2304231000 # number of ReadExReq miss cycles 1015system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3342274500 # number of ReadCleanReq miss cycles 1016system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3342274500 # number of ReadCleanReq miss cycles 1017system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3044310495 # number of ReadSharedReq miss cycles 1018system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3044310495 # number of ReadSharedReq miss cycles 1019system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 28767000 # number of demand (read+write) miss cycles 1020system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2997000 # number of demand (read+write) miss cycles 1021system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3342274500 # number of demand (read+write) miss cycles 1022system.cpu0.l2cache.demand_miss_latency::cpu0.data 5348541495 # number of demand (read+write) miss cycles 1023system.cpu0.l2cache.demand_miss_latency::total 8722579995 # number of demand (read+write) miss cycles 1024system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 28767000 # number of overall miss cycles 1025system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2997000 # number of overall miss cycles 1026system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3342274500 # number of overall miss cycles 1027system.cpu0.l2cache.overall_miss_latency::cpu0.data 5348541495 # number of overall miss cycles 1028system.cpu0.l2cache.overall_miss_latency::total 8722579995 # number of overall miss cycles 1029system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 83586 # number of ReadReq accesses(hits+misses) 1030system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5545 # number of ReadReq accesses(hits+misses) 1031system.cpu0.l2cache.ReadReq_accesses::total 89131 # number of ReadReq accesses(hits+misses) 1032system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481961 # number of WritebackDirty accesses(hits+misses) 1033system.cpu0.l2cache.WritebackDirty_accesses::total 481961 # number of WritebackDirty accesses(hits+misses) 1034system.cpu0.l2cache.WritebackClean_accesses::writebacks 2152508 # number of WritebackClean accesses(hits+misses) 1035system.cpu0.l2cache.WritebackClean_accesses::total 2152508 # number of WritebackClean accesses(hits+misses) 1036system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56747 # number of UpgradeReq accesses(hits+misses) 1037system.cpu0.l2cache.UpgradeReq_accesses::total 56747 # number of UpgradeReq accesses(hits+misses) 1038system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20566 # number of SCUpgradeReq accesses(hits+misses) 1039system.cpu0.l2cache.SCUpgradeReq_accesses::total 20566 # number of SCUpgradeReq accesses(hits+misses) 1040system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1041system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1042system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268881 # number of ReadExReq accesses(hits+misses) 1043system.cpu0.l2cache.ReadExReq_accesses::total 268881 # number of ReadExReq accesses(hits+misses) 1044system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1962531 # number of ReadCleanReq accesses(hits+misses) 1045system.cpu0.l2cache.ReadCleanReq_accesses::total 1962531 # number of ReadCleanReq accesses(hits+misses) 1046system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 501524 # number of ReadSharedReq accesses(hits+misses) 1047system.cpu0.l2cache.ReadSharedReq_accesses::total 501524 # number of ReadSharedReq accesses(hits+misses) 1048system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 83586 # number of demand (read+write) accesses 1049system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5545 # number of demand (read+write) accesses 1050system.cpu0.l2cache.demand_accesses::cpu0.inst 1962531 # number of demand (read+write) accesses 1051system.cpu0.l2cache.demand_accesses::cpu0.data 770405 # number of demand (read+write) accesses 1052system.cpu0.l2cache.demand_accesses::total 2822067 # number of demand (read+write) accesses 1053system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 83586 # number of overall (read+write) accesses 1054system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5545 # number of overall (read+write) accesses 1055system.cpu0.l2cache.overall_accesses::cpu0.inst 1962531 # number of overall (read+write) accesses 1056system.cpu0.l2cache.overall_accesses::cpu0.data 770405 # number of overall (read+write) accesses 1057system.cpu0.l2cache.overall_accesses::total 2822067 # number of overall (read+write) accesses 1058system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010241 # miss rate for ReadReq accesses 1059system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.023084 # miss rate for ReadReq accesses 1060system.cpu0.l2cache.ReadReq_miss_rate::total 0.011040 # miss rate for ReadReq accesses 1061system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses 1062system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses 1063system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1064system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1065system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1066system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1067system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.173646 # miss rate for ReadExReq accesses 1068system.cpu0.l2cache.ReadExReq_miss_rate::total 0.173646 # miss rate for ReadExReq accesses 1069system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034860 # miss rate for ReadCleanReq accesses 1070system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034860 # miss rate for ReadCleanReq accesses 1071system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.200654 # miss rate for ReadSharedReq accesses 1072system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.200654 # miss rate for ReadSharedReq accesses 1073system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010241 # miss rate for demand accesses 1074system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.023084 # miss rate for demand accesses 1075system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034860 # miss rate for demand accesses 1076system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.191228 # miss rate for demand accesses 1077system.cpu0.l2cache.demand_miss_rate::total 0.076795 # miss rate for demand accesses 1078system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010241 # miss rate for overall accesses 1079system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.023084 # miss rate for overall accesses 1080system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034860 # miss rate for overall accesses 1081system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.191228 # miss rate for overall accesses 1082system.cpu0.l2cache.overall_miss_rate::total 0.076795 # miss rate for overall accesses 1083system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33606.308411 # average ReadReq miss latency 1084system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23414.062500 # average ReadReq miss latency 1085system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32280.487805 # average ReadReq miss latency 1086system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2141.569450 # average UpgradeReq miss latency 1087system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2141.569450 # average UpgradeReq miss latency 1088system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1226.004084 # average SCUpgradeReq miss latency 1089system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1226.004084 # average SCUpgradeReq miss latency 1090system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 212499 # average SCUpgradeFailReq miss latency 1091system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 212499 # average SCUpgradeFailReq miss latency 1092system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49351.702720 # average ReadExReq miss latency 1093system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49351.702720 # average ReadExReq miss latency 1094system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48854.377092 # average ReadCleanReq miss latency 1095system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48854.377092 # average ReadCleanReq miss latency 1096system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30251.612244 # average ReadSharedReq miss latency 1097system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30251.612244 # average ReadSharedReq miss latency 1098system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33606.308411 # average overall miss latency 1099system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23414.062500 # average overall miss latency 1100system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48854.377092 # average overall miss latency 1101system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36304.864108 # average overall miss latency 1102system.cpu0.l2cache.demand_avg_miss_latency::total 40248.154277 # average overall miss latency 1103system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33606.308411 # average overall miss latency 1104system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23414.062500 # average overall miss latency 1105system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48854.377092 # average overall miss latency 1106system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36304.864108 # average overall miss latency 1107system.cpu0.l2cache.overall_avg_miss_latency::total 40248.154277 # average overall miss latency 1108system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1109system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1110system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1111system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1112system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1113system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1114system.cpu0.l2cache.unused_prefetches 11097 # number of HardPF blocks evicted w/o reference 1115system.cpu0.l2cache.writebacks::writebacks 233923 # number of writebacks 1116system.cpu0.l2cache.writebacks::total 233923 # number of writebacks 1117system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2672 # number of ReadExReq MSHR hits 1118system.cpu0.l2cache.ReadExReq_mshr_hits::total 2672 # number of ReadExReq MSHR hits 1119system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 73 # number of ReadCleanReq MSHR hits 1120system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 73 # number of ReadCleanReq MSHR hits 1121system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 384 # number of ReadSharedReq MSHR hits 1122system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 384 # number of ReadSharedReq MSHR hits 1123system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 73 # number of demand (read+write) MSHR hits 1124system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3056 # number of demand (read+write) MSHR hits 1125system.cpu0.l2cache.demand_mshr_hits::total 3129 # number of demand (read+write) MSHR hits 1126system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 73 # number of overall MSHR hits 1127system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3056 # number of overall MSHR hits 1128system.cpu0.l2cache.overall_mshr_hits::total 3129 # number of overall MSHR hits 1129system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 856 # number of ReadReq MSHR misses 1130system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 128 # number of ReadReq MSHR misses 1131system.cpu0.l2cache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses 1132system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 258926 # number of HardPFReq MSHR misses 1133system.cpu0.l2cache.HardPFReq_mshr_misses::total 258926 # number of HardPFReq MSHR misses 1134system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56746 # number of UpgradeReq MSHR misses 1135system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56746 # number of UpgradeReq MSHR misses 1136system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20566 # number of SCUpgradeReq MSHR misses 1137system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20566 # number of SCUpgradeReq MSHR misses 1138system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1139system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1140system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 44018 # number of ReadExReq MSHR misses 1141system.cpu0.l2cache.ReadExReq_mshr_misses::total 44018 # number of ReadExReq MSHR misses 1142system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 68340 # number of ReadCleanReq MSHR misses 1143system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 68340 # number of ReadCleanReq MSHR misses 1144system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100249 # number of ReadSharedReq MSHR misses 1145system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100249 # number of ReadSharedReq MSHR misses 1146system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 856 # number of demand (read+write) MSHR misses 1147system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 128 # number of demand (read+write) MSHR misses 1148system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 68340 # number of demand (read+write) MSHR misses 1149system.cpu0.l2cache.demand_mshr_misses::cpu0.data 144267 # number of demand (read+write) MSHR misses 1150system.cpu0.l2cache.demand_mshr_misses::total 213591 # number of demand (read+write) MSHR misses 1151system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 856 # number of overall MSHR misses 1152system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 128 # number of overall MSHR misses 1153system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 68340 # number of overall MSHR misses 1154system.cpu0.l2cache.overall_mshr_misses::cpu0.data 144267 # number of overall MSHR misses 1155system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 258926 # number of overall MSHR misses 1156system.cpu0.l2cache.overall_mshr_misses::total 472517 # number of overall MSHR misses 1157system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable 1158system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable 1159system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 24024 # number of ReadReq MSHR uncacheable 1160system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable 1161system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19271 # number of WriteReq MSHR uncacheable 1162system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses 1163system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses 1164system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43295 # number of overall MSHR uncacheable misses 1165system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 23631000 # number of ReadReq MSHR miss cycles 1166system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2229000 # number of ReadReq MSHR miss cycles 1167system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 25860000 # number of ReadReq MSHR miss cycles 1168system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14017177372 # number of HardPFReq MSHR miss cycles 1169system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14017177372 # number of HardPFReq MSHR miss cycles 1170system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1114674000 # number of UpgradeReq MSHR miss cycles 1171system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1114674000 # number of UpgradeReq MSHR miss cycles 1172system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 322353500 # number of SCUpgradeReq MSHR miss cycles 1173system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 322353500 # number of SCUpgradeReq MSHR miss cycles 1174system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 176499 # number of SCUpgradeFailReq MSHR miss cycles 1175system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 176499 # number of SCUpgradeFailReq MSHR miss cycles 1176system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1755037000 # number of ReadExReq MSHR miss cycles 1177system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1755037000 # number of ReadExReq MSHR miss cycles 1178system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2929882500 # number of ReadCleanReq MSHR miss cycles 1179system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2929882500 # number of ReadCleanReq MSHR miss cycles 1180system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2420870995 # number of ReadSharedReq MSHR miss cycles 1181system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2420870995 # number of ReadSharedReq MSHR miss cycles 1182system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 23631000 # number of demand (read+write) MSHR miss cycles 1183system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2229000 # number of demand (read+write) MSHR miss cycles 1184system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2929882500 # number of demand (read+write) MSHR miss cycles 1185system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4175907995 # number of demand (read+write) MSHR miss cycles 1186system.cpu0.l2cache.demand_mshr_miss_latency::total 7131650495 # number of demand (read+write) MSHR miss cycles 1187system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 23631000 # number of overall MSHR miss cycles 1188system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2229000 # number of overall MSHR miss cycles 1189system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2929882500 # number of overall MSHR miss cycles 1190system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4175907995 # number of overall MSHR miss cycles 1191system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14017177372 # number of overall MSHR miss cycles 1192system.cpu0.l2cache.overall_mshr_miss_latency::total 21148827867 # number of overall MSHR miss cycles 1193system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 291877500 # number of ReadReq MSHR uncacheable cycles 1194system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4450889000 # number of ReadReq MSHR uncacheable cycles 1195system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4742766500 # number of ReadReq MSHR uncacheable cycles 1196system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 291877500 # number of overall MSHR uncacheable cycles 1197system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4450889000 # number of overall MSHR uncacheable cycles 1198system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4742766500 # number of overall MSHR uncacheable cycles 1199system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for ReadReq accesses 1200system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for ReadReq accesses 1201system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.011040 # mshr miss rate for ReadReq accesses 1202system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1203system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1204system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses 1205system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses 1206system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1207system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1208system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1209system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1210system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163708 # mshr miss rate for ReadExReq accesses 1211system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163708 # mshr miss rate for ReadExReq accesses 1212system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for ReadCleanReq accesses 1213system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034822 # mshr miss rate for ReadCleanReq accesses 1214system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.199889 # mshr miss rate for ReadSharedReq accesses 1215system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.199889 # mshr miss rate for ReadSharedReq accesses 1216system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for demand accesses 1217system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for demand accesses 1218system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for demand accesses 1219system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for demand accesses 1220system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075686 # mshr miss rate for demand accesses 1221system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for overall accesses 1222system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for overall accesses 1223system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for overall accesses 1224system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for overall accesses 1225system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1226system.cpu0.l2cache.overall_mshr_miss_rate::total 0.167436 # mshr miss rate for overall accesses 1227system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average ReadReq mshr miss latency 1228system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average ReadReq mshr miss latency 1229system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26280.487805 # average ReadReq mshr miss latency 1230system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average HardPFReq mshr miss latency 1231system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54135.843337 # average HardPFReq mshr miss latency 1232system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19643.217143 # average UpgradeReq mshr miss latency 1233system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19643.217143 # average UpgradeReq mshr miss latency 1234system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15674.098026 # average SCUpgradeReq mshr miss latency 1235system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15674.098026 # average SCUpgradeReq mshr miss latency 1236system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 176499 # average SCUpgradeFailReq mshr miss latency 1237system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 176499 # average SCUpgradeFailReq mshr miss latency 1238system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39870.893725 # average ReadExReq mshr miss latency 1239system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39870.893725 # average ReadExReq mshr miss latency 1240system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average ReadCleanReq mshr miss latency 1241system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42872.146620 # average ReadCleanReq mshr miss latency 1242system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24148.579986 # average ReadSharedReq mshr miss latency 1243system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24148.579986 # average ReadSharedReq mshr miss latency 1244system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency 1245system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency 1246system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency 1247system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency 1248system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33389.283701 # average overall mshr miss latency 1249system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency 1250system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency 1251system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency 1252system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency 1253system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average overall mshr miss latency 1254system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44757.813723 # average overall mshr miss latency 1255system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average ReadReq mshr uncacheable latency 1256system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 216325.103281 # average ReadReq mshr uncacheable latency 1257system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197417.852980 # average ReadReq mshr uncacheable latency 1258system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average overall mshr uncacheable latency 1259system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111702.278773 # average overall mshr uncacheable latency 1260system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109545.363206 # average overall mshr uncacheable latency 1261system.cpu0.toL2Bus.snoop_filter.tot_requests 5508026 # Total number of requests made to the snoop filter. 1262system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2775137 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1263system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42660 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1264system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter. 1265system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1266system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1267system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1268system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution 1269system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution 1270system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution 1271system.cpu0.toL2Bus.trans_dist::WriteResp 19271 # Transaction distribution 1272system.cpu0.toL2Bus.trans_dist::WritebackDirty 716131 # Transaction distribution 1273system.cpu0.toL2Bus.trans_dist::WritebackClean 2195168 # Transaction distribution 1274system.cpu0.toL2Bus.trans_dist::CleanEvict 240019 # Transaction distribution 1275system.cpu0.toL2Bus.trans_dist::HardPFReq 309687 # Transaction distribution 1276system.cpu0.toL2Bus.trans_dist::UpgradeReq 88590 # Transaction distribution 1277system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43220 # Transaction distribution 1278system.cpu0.toL2Bus.trans_dist::UpgradeResp 114518 # Transaction distribution 1279system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::ReadExReq 288089 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::ReadExResp 284462 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1962531 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586533 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::InvalidateReq 3131 # Transaction distribution 1286system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5893963 # Packet count per connected master and slave (bytes) 1287system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2592135 # Packet count per connected master and slave (bytes) 1288system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13195 # Packet count per connected master and slave (bytes) 1289system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174334 # Packet count per connected master and slave (bytes) 1290system.cpu0.toL2Bus.pkt_count::total 8673627 # Packet count per connected master and slave (bytes) 1291system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251390912 # Cumulative packet size per connected master and slave (bytes) 1292system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99322292 # Cumulative packet size per connected master and slave (bytes) 1293system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22180 # Cumulative packet size per connected master and slave (bytes) 1294system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 334344 # Cumulative packet size per connected master and slave (bytes) 1295system.cpu0.toL2Bus.pkt_size::total 351069728 # Cumulative packet size per connected master and slave (bytes) 1296system.cpu0.toL2Bus.snoops 1056913 # Total snoops (count) 1297system.cpu0.toL2Bus.snoop_fanout::samples 3897709 # Request fanout histogram 1298system.cpu0.toL2Bus.snoop_fanout::mean 0.106693 # Request fanout histogram 1299system.cpu0.toL2Bus.snoop_fanout::stdev 0.313582 # Request fanout histogram 1300system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1301system.cpu0.toL2Bus.snoop_fanout::0 3487742 89.48% 89.48% # Request fanout histogram 1302system.cpu0.toL2Bus.snoop_fanout::1 404074 10.37% 99.85% # Request fanout histogram 1303system.cpu0.toL2Bus.snoop_fanout::2 5893 0.15% 100.00% # Request fanout histogram 1304system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1305system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1306system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1307system.cpu0.toL2Bus.snoop_fanout::total 3897709 # Request fanout histogram 1308system.cpu0.toL2Bus.reqLayer0.occupancy 5501303494 # Layer occupancy (ticks) 1309system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1310system.cpu0.toL2Bus.snoopLayer0.occupancy 115667783 # Layer occupancy (ticks) 1311system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1312system.cpu0.toL2Bus.respLayer0.occupancy 2949460514 # Layer occupancy (ticks) 1313system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1314system.cpu0.toL2Bus.respLayer1.occupancy 1225261932 # Layer occupancy (ticks) 1315system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1316system.cpu0.toL2Bus.respLayer2.occupancy 7656487 # Layer occupancy (ticks) 1317system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1318system.cpu0.toL2Bus.respLayer3.occupancy 90771952 # Layer occupancy (ticks) 1319system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1320system.cpu1.branchPred.lookups 19337823 # Number of BP lookups 1321system.cpu1.branchPred.condPredicted 6215951 # Number of conditional branches predicted 1322system.cpu1.branchPred.condIncorrect 910078 # Number of conditional branches incorrect 1323system.cpu1.branchPred.BTBLookups 9913117 # Number of BTB lookups 1324system.cpu1.branchPred.BTBHits 3669706 # Number of BTB hits 1325system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1326system.cpu1.branchPred.BTBHitPct 37.018689 # BTB Hit Percentage 1327system.cpu1.branchPred.usedRAS 8699112 # Number of times the RAS was used to get a target. 1328system.cpu1.branchPred.RASInCorrect 707232 # Number of incorrect RAS predictions. 1329system.cpu1.branchPred.indirectLookups 3579063 # Number of indirect predictor lookups. 1330system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits. 1331system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses. 1332system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches. 1333system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1334system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1335system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1336system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1339system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1340system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1341system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1342system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1343system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1344system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1345system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1346system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1347system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1348system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1349system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1350system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1351system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1352system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1353system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1354system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1355system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1356system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1357system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1358system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1359system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1360system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1361system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1362system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1363system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1364system.cpu1.dtb.walker.walks 26974 # Table walker walks requested 1365system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors 1366system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate 1367system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6887 # Level at which table walker walks with short descriptors terminate 1368system.cpu1.dtb.walker.walkWaitTime::samples 26974 # Table walker wait (enqueue to first request) latency 1369system.cpu1.dtb.walker.walkWaitTime::0 26974 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1370system.cpu1.dtb.walker.walkWaitTime::total 26974 # Table walker wait (enqueue to first request) latency 1371system.cpu1.dtb.walker.walkCompletionTime::samples 2714 # Table walker service (enqueue to completion) latency 1372system.cpu1.dtb.walker.walkCompletionTime::mean 11914.148858 # Table walker service (enqueue to completion) latency 1373system.cpu1.dtb.walker.walkCompletionTime::gmean 11049.041659 # Table walker service (enqueue to completion) latency 1374system.cpu1.dtb.walker.walkCompletionTime::stdev 5760.245338 # Table walker service (enqueue to completion) latency 1375system.cpu1.dtb.walker.walkCompletionTime::0-8191 673 24.80% 24.80% # Table walker service (enqueue to completion) latency 1376system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1844 67.94% 92.74% # Table walker service (enqueue to completion) latency 1377system.cpu1.dtb.walker.walkCompletionTime::16384-24575 118 4.35% 97.09% # Table walker service (enqueue to completion) latency 1378system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.06% 99.15% # Table walker service (enqueue to completion) latency 1379system.cpu1.dtb.walker.walkCompletionTime::32768-40959 13 0.48% 99.63% # Table walker service (enqueue to completion) latency 1380system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency 1381system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency 1382system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walkCompletionTime::total 2714 # Table walker service (enqueue to completion) latency 1386system.cpu1.dtb.walker.walksPending::samples -2024068032 # Table walker pending requests distribution 1387system.cpu1.dtb.walker.walksPending::0 -2024068032 100.00% 100.00% # Table walker pending requests distribution 1388system.cpu1.dtb.walker.walksPending::total -2024068032 # Table walker pending requests distribution 1389system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.58% 73.58% # Table walker page sizes translated 1390system.cpu1.dtb.walker.walkPageSizes::1M 717 26.42% 100.00% # Table walker page sizes translated 1391system.cpu1.dtb.walker.walkPageSizes::total 2714 # Table walker page sizes translated 1392system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26974 # Table walker requests started/completed, data/inst 1393system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1394system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26974 # Table walker requests started/completed, data/inst 1395system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2714 # Table walker requests started/completed, data/inst 1396system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1397system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2714 # Table walker requests started/completed, data/inst 1398system.cpu1.dtb.walker.walkRequestOrigin::total 29688 # Table walker requests started/completed, data/inst 1399system.cpu1.dtb.inst_hits 0 # ITB inst hits 1400system.cpu1.dtb.inst_misses 0 # ITB inst misses 1401system.cpu1.dtb.read_hits 11185393 # DTB read hits 1402system.cpu1.dtb.read_misses 25019 # DTB read misses 1403system.cpu1.dtb.write_hits 6992115 # DTB write hits 1404system.cpu1.dtb.write_misses 1955 # DTB write misses 1405system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1406system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1407system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1408system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	544system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 545system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 546system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 547system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions 548system.cpu0.itb.read_accesses 0 # DTB read accesses 549system.cpu0.itb.write_accesses 0 # DTB write accesses 550system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses 551system.cpu0.itb.hits 38606266 # DTB hits 552system.cpu0.itb.misses 3977 # DTB misses 553system.cpu0.itb.accesses 38610243 # DTB accesses 554system.cpu0.numPwrStateTransitions 3704 # Number of power state transitions 555system.cpu0.pwrStateClkGateDist::samples 1852 # Distribution of time spent in the clock gated state 556system.cpu0.pwrStateClkGateDist::mean 1492233091.644168 # Distribution of time spent in the clock gated state 557system.cpu0.pwrStateClkGateDist::stdev 23940880637.068275 # Distribution of time spent in the clock gated state 558system.cpu0.pwrStateClkGateDist::underflows 1073 57.94% 57.94% # Distribution of time spent in the clock gated state 559system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.68% 99.62% # Distribution of time spent in the clock gated state 560system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state 561system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state 562system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 563system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 564system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 565system.cpu0.pwrStateClkGateDist::max_value 499965331660 # Distribution of time spent in the clock gated state 566system.cpu0.pwrStateClkGateDist::total 1852 # Distribution of time spent in the clock gated state 567system.cpu0.pwrStateResidencyTicks::ON 83611720275 # Cumulative time (in ticks) in various power states 568system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763615685725 # Cumulative time (in ticks) in various power states 569system.cpu0.numCycles 167224982 # number of cpu cycles simulated 570system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 571system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 572system.cpu0.committedInsts 79715648 # Number of instructions committed 573system.cpu0.committedOps 95927461 # Number of ops (including micro ops) committed 574system.cpu0.discardedOps 5237247 # Number of ops (including micro ops) which were discarded before commit 575system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching 576system.cpu0.quiesceCycles 5527254348 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 577system.cpu0.cpi 2.097769 # CPI: cycles per instruction 578system.cpu0.ipc 0.476697 # IPC: instructions per cycle 579system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction 580system.cpu0.op_class_0::IntAlu 63730677 66.44% 66.44% # Class of committed instruction 581system.cpu0.op_class_0::IntMult 92076 0.10% 66.53% # Class of committed instruction 582system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction 583system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction 584system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction 585system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction 586system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction 587system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction 588system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction 589system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction 590system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction 591system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction 592system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction 593system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction 594system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction 595system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction 596system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction 597system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction 598system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction 599system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction 600system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction 601system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction 602system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction 603system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction 604system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction 605system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction 606system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction 607system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction 608system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction 609system.cpu0.op_class_0::MemRead 16811055 17.52% 84.07% # Class of committed instruction 610system.cpu0.op_class_0::MemWrite 15283265 15.93% 100.00% # Class of committed instruction 611system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 612system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 613system.cpu0.op_class_0::total 95927461 # Class of committed instruction 614system.cpu0.kern.inst.arm 0 # number of arm instructions executed 615system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed 616system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked 617system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped 618system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 619system.cpu0.dcache.tags.replacements 715130 # number of replacements 620system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use 621system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks. 622system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. 623system.cpu0.dcache.tags.avg_refs 42.471892 # Average number of references to valid blocks. 624system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. 625system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor 626system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy 627system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy 628system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 629system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 630system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id 631system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 632system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 633system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses 634system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses 635system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 636system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits 637system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits 638system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits 639system.cpu0.dcache.WriteReq_hits::total 13424812 # number of WriteReq hits 640system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits 641system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits 642system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits 643system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits 644system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080 # number of StoreCondReq hits 645system.cpu0.dcache.StoreCondReq_hits::total 361080 # number of StoreCondReq hits 646system.cpu0.dcache.demand_hits::cpu0.data 29235144 # number of demand (read+write) hits 647system.cpu0.dcache.demand_hits::total 29235144 # number of demand (read+write) hits 648system.cpu0.dcache.overall_hits::cpu0.data 29555584 # number of overall hits 649system.cpu0.dcache.overall_hits::total 29555584 # number of overall hits 650system.cpu0.dcache.ReadReq_misses::cpu0.data 463723 # number of ReadReq misses 651system.cpu0.dcache.ReadReq_misses::total 463723 # number of ReadReq misses 652system.cpu0.dcache.WriteReq_misses::cpu0.data 580901 # number of WriteReq misses 653system.cpu0.dcache.WriteReq_misses::total 580901 # number of WriteReq misses 654system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136483 # number of SoftPFReq misses 655system.cpu0.dcache.SoftPFReq_misses::total 136483 # number of SoftPFReq misses 656system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21307 # number of LoadLockedReq misses 657system.cpu0.dcache.LoadLockedReq_misses::total 21307 # number of LoadLockedReq misses 658system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20567 # number of StoreCondReq misses 659system.cpu0.dcache.StoreCondReq_misses::total 20567 # number of StoreCondReq misses 660system.cpu0.dcache.demand_misses::cpu0.data 1044624 # number of demand (read+write) misses 661system.cpu0.dcache.demand_misses::total 1044624 # number of demand (read+write) misses 662system.cpu0.dcache.overall_misses::cpu0.data 1181107 # number of overall misses 663system.cpu0.dcache.overall_misses::total 1181107 # number of overall misses 664system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6183627500 # number of ReadReq miss cycles 665system.cpu0.dcache.ReadReq_miss_latency::total 6183627500 # number of ReadReq miss cycles 666system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10315375000 # number of WriteReq miss cycles 667system.cpu0.dcache.WriteReq_miss_latency::total 10315375000 # number of WriteReq miss cycles 668system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 321766500 # number of LoadLockedReq miss cycles 669system.cpu0.dcache.LoadLockedReq_miss_latency::total 321766500 # number of LoadLockedReq miss cycles 670system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 497952500 # number of StoreCondReq miss cycles 671system.cpu0.dcache.StoreCondReq_miss_latency::total 497952500 # number of StoreCondReq miss cycles 672system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 229500 # number of StoreCondFailReq miss cycles 673system.cpu0.dcache.StoreCondFailReq_miss_latency::total 229500 # number of StoreCondFailReq miss cycles 674system.cpu0.dcache.demand_miss_latency::cpu0.data 16499002500 # number of demand (read+write) miss cycles 675system.cpu0.dcache.demand_miss_latency::total 16499002500 # number of demand (read+write) miss cycles 676system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500 # number of overall miss cycles 677system.cpu0.dcache.overall_miss_latency::total 16499002500 # number of overall miss cycles 678system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274055 # number of ReadReq accesses(hits+misses) 679system.cpu0.dcache.ReadReq_accesses::total 16274055 # number of ReadReq accesses(hits+misses) 680system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005713 # number of WriteReq accesses(hits+misses) 681system.cpu0.dcache.WriteReq_accesses::total 14005713 # number of WriteReq accesses(hits+misses) 682system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923 # number of SoftPFReq accesses(hits+misses) 683system.cpu0.dcache.SoftPFReq_accesses::total 456923 # number of SoftPFReq accesses(hits+misses) 684system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533 # number of LoadLockedReq accesses(hits+misses) 685system.cpu0.dcache.LoadLockedReq_accesses::total 386533 # number of LoadLockedReq accesses(hits+misses) 686system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647 # number of StoreCondReq accesses(hits+misses) 687system.cpu0.dcache.StoreCondReq_accesses::total 381647 # number of StoreCondReq accesses(hits+misses) 688system.cpu0.dcache.demand_accesses::cpu0.data 30279768 # number of demand (read+write) accesses 689system.cpu0.dcache.demand_accesses::total 30279768 # number of demand (read+write) accesses 690system.cpu0.dcache.overall_accesses::cpu0.data 30736691 # number of overall (read+write) accesses 691system.cpu0.dcache.overall_accesses::total 30736691 # number of overall (read+write) accesses 692system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses 693system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses 694system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses 695system.cpu0.dcache.WriteReq_miss_rate::total 0.041476 # miss rate for WriteReq accesses 696system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298700 # miss rate for SoftPFReq accesses 697system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298700 # miss rate for SoftPFReq accesses 698system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055123 # miss rate for LoadLockedReq accesses 699system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055123 # miss rate for LoadLockedReq accesses 700system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053890 # miss rate for StoreCondReq accesses 701system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053890 # miss rate for StoreCondReq accesses 702system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034499 # miss rate for demand accesses 703system.cpu0.dcache.demand_miss_rate::total 0.034499 # miss rate for demand accesses 704system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038427 # miss rate for overall accesses 705system.cpu0.dcache.overall_miss_rate::total 0.038427 # miss rate for overall accesses 706system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13334.744017 # average ReadReq miss latency 707system.cpu0.dcache.ReadReq_avg_miss_latency::total 13334.744017 # average ReadReq miss latency 708system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17757.543884 # average WriteReq miss latency 709system.cpu0.dcache.WriteReq_avg_miss_latency::total 17757.543884 # average WriteReq miss latency 710system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15101.445534 # average LoadLockedReq miss latency 711system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15101.445534 # average LoadLockedReq miss latency 712system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24211.236447 # average StoreCondReq miss latency 713system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24211.236447 # average StoreCondReq miss latency 714system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 715system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 716system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15794.202029 # average overall miss latency 717system.cpu0.dcache.demand_avg_miss_latency::total 15794.202029 # average overall miss latency 718system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13969.100598 # average overall miss latency 719system.cpu0.dcache.overall_avg_miss_latency::total 13969.100598 # average overall miss latency 720system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 721system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 722system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 723system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 724system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 725system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 726system.cpu0.dcache.writebacks::writebacks 715130 # number of writebacks 727system.cpu0.dcache.writebacks::total 715130 # number of writebacks 728system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 71798 # number of ReadReq MSHR hits 729system.cpu0.dcache.ReadReq_mshr_hits::total 71798 # number of ReadReq MSHR hits 730system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255281 # number of WriteReq MSHR hits 731system.cpu0.dcache.WriteReq_mshr_hits::total 255281 # number of WriteReq MSHR hits 732system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14780 # number of LoadLockedReq MSHR hits 733system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14780 # number of LoadLockedReq MSHR hits 734system.cpu0.dcache.demand_mshr_hits::cpu0.data 327079 # number of demand (read+write) MSHR hits 735system.cpu0.dcache.demand_mshr_hits::total 327079 # number of demand (read+write) MSHR hits 736system.cpu0.dcache.overall_mshr_hits::cpu0.data 327079 # number of overall MSHR hits 737system.cpu0.dcache.overall_mshr_hits::total 327079 # number of overall MSHR hits 738system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391925 # number of ReadReq MSHR misses 739system.cpu0.dcache.ReadReq_mshr_misses::total 391925 # number of ReadReq MSHR misses 740system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325620 # number of WriteReq MSHR misses 741system.cpu0.dcache.WriteReq_mshr_misses::total 325620 # number of WriteReq MSHR misses 742system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103078 # number of SoftPFReq MSHR misses 743system.cpu0.dcache.SoftPFReq_mshr_misses::total 103078 # number of SoftPFReq MSHR misses 744system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6527 # number of LoadLockedReq MSHR misses 745system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6527 # number of LoadLockedReq MSHR misses 746system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20567 # number of StoreCondReq MSHR misses 747system.cpu0.dcache.StoreCondReq_mshr_misses::total 20567 # number of StoreCondReq MSHR misses 748system.cpu0.dcache.demand_mshr_misses::cpu0.data 717545 # number of demand (read+write) MSHR misses 749system.cpu0.dcache.demand_mshr_misses::total 717545 # number of demand (read+write) MSHR misses 750system.cpu0.dcache.overall_mshr_misses::cpu0.data 820623 # number of overall MSHR misses 751system.cpu0.dcache.overall_mshr_misses::total 820623 # number of overall MSHR misses 752system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable 753system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20575 # number of ReadReq MSHR uncacheable 754system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable 755system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19271 # number of WriteReq MSHR uncacheable 756system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses 757system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses 758system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4674150000 # number of ReadReq MSHR miss cycles 759system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4674150000 # number of ReadReq MSHR miss cycles 760system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5703236000 # number of WriteReq MSHR miss cycles 761system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5703236000 # number of WriteReq MSHR miss cycles 762system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1673631500 # number of SoftPFReq MSHR miss cycles 763system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1673631500 # number of SoftPFReq MSHR miss cycles 764system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101407500 # number of LoadLockedReq MSHR miss cycles 765system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101407500 # number of LoadLockedReq MSHR miss cycles 766system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 477391500 # number of StoreCondReq MSHR miss cycles 767system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 477391500 # number of StoreCondReq MSHR miss cycles 768system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles 769system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles 770system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10377386000 # number of demand (read+write) MSHR miss cycles 771system.cpu0.dcache.demand_mshr_miss_latency::total 10377386000 # number of demand (read+write) MSHR miss cycles 772system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12051017500 # number of overall MSHR miss cycles 773system.cpu0.dcache.overall_mshr_miss_latency::total 12051017500 # number of overall MSHR miss cycles 774system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4615609000 # number of ReadReq MSHR uncacheable cycles 775system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4615609000 # number of ReadReq MSHR uncacheable cycles 776system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4615609000 # number of overall MSHR uncacheable cycles 777system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4615609000 # number of overall MSHR uncacheable cycles 778system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024083 # mshr miss rate for ReadReq accesses 779system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024083 # mshr miss rate for ReadReq accesses 780system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses 781system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses 782system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225592 # mshr miss rate for SoftPFReq accesses 783system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225592 # mshr miss rate for SoftPFReq accesses 784system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016886 # mshr miss rate for LoadLockedReq accesses 785system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016886 # mshr miss rate for LoadLockedReq accesses 786system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053890 # mshr miss rate for StoreCondReq accesses 787system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053890 # mshr miss rate for StoreCondReq accesses 788system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023697 # mshr miss rate for demand accesses 789system.cpu0.dcache.demand_mshr_miss_rate::total 0.023697 # mshr miss rate for demand accesses 790system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026698 # mshr miss rate for overall accesses 791system.cpu0.dcache.overall_mshr_miss_rate::total 0.026698 # mshr miss rate for overall accesses 792system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11926.133827 # average ReadReq mshr miss latency 793system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11926.133827 # average ReadReq mshr miss latency 794system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17515.005221 # average WriteReq mshr miss latency 795system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17515.005221 # average WriteReq mshr miss latency 796system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16236.553872 # average SoftPFReq mshr miss latency 797system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16236.553872 # average SoftPFReq mshr miss latency 798system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15536.617129 # average LoadLockedReq mshr miss latency 799system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15536.617129 # average LoadLockedReq mshr miss latency 800system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23211.528176 # average StoreCondReq mshr miss latency 801system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23211.528176 # average StoreCondReq mshr miss latency 802system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 803system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 804system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14462.348703 # average overall mshr miss latency 805system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14462.348703 # average overall mshr miss latency 806system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14685.205630 # average overall mshr miss latency 807system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14685.205630 # average overall mshr miss latency 808system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 224330.935601 # average ReadReq mshr uncacheable latency 809system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601 # average ReadReq mshr uncacheable latency 810system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348 # average overall mshr uncacheable latency 811system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348 # average overall mshr uncacheable latency 812system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 813system.cpu0.icache.tags.replacements 1962004 # number of replacements 814system.cpu0.icache.tags.tagsinuse 511.774944 # Cycle average of tags in use 815system.cpu0.icache.tags.total_refs 36636559 # Total number of references to valid blocks. 816system.cpu0.icache.tags.sampled_refs 1962516 # Sample count of references to valid blocks. 817system.cpu0.icache.tags.avg_refs 18.668158 # Average number of references to valid blocks. 818system.cpu0.icache.tags.warmup_cycle 6612168000 # Cycle when the warmup percentage was hit. 819system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774944 # Average occupied blocks per requestor 820system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy 821system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy 822system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 823system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 824system.cpu0.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 825system.cpu0.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id 826system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 827system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses 828system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses 829system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 830system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits 831system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits 832system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits 833system.cpu0.icache.demand_hits::total 36636559 # number of demand (read+write) hits 834system.cpu0.icache.overall_hits::cpu0.inst 36636559 # number of overall hits 835system.cpu0.icache.overall_hits::total 36636559 # number of overall hits 836system.cpu0.icache.ReadReq_misses::cpu0.inst 1962531 # number of ReadReq misses 837system.cpu0.icache.ReadReq_misses::total 1962531 # number of ReadReq misses 838system.cpu0.icache.demand_misses::cpu0.inst 1962531 # number of demand (read+write) misses 839system.cpu0.icache.demand_misses::total 1962531 # number of demand (read+write) misses 840system.cpu0.icache.overall_misses::cpu0.inst 1962531 # number of overall misses 841system.cpu0.icache.overall_misses::total 1962531 # number of overall misses 842system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18757498000 # number of ReadReq miss cycles 843system.cpu0.icache.ReadReq_miss_latency::total 18757498000 # number of ReadReq miss cycles 844system.cpu0.icache.demand_miss_latency::cpu0.inst 18757498000 # number of demand (read+write) miss cycles 845system.cpu0.icache.demand_miss_latency::total 18757498000 # number of demand (read+write) miss cycles 846system.cpu0.icache.overall_miss_latency::cpu0.inst 18757498000 # number of overall miss cycles 847system.cpu0.icache.overall_miss_latency::total 18757498000 # number of overall miss cycles 848system.cpu0.icache.ReadReq_accesses::cpu0.inst 38599090 # number of ReadReq accesses(hits+misses) 849system.cpu0.icache.ReadReq_accesses::total 38599090 # number of ReadReq accesses(hits+misses) 850system.cpu0.icache.demand_accesses::cpu0.inst 38599090 # number of demand (read+write) accesses 851system.cpu0.icache.demand_accesses::total 38599090 # number of demand (read+write) accesses 852system.cpu0.icache.overall_accesses::cpu0.inst 38599090 # number of overall (read+write) accesses 853system.cpu0.icache.overall_accesses::total 38599090 # number of overall (read+write) accesses 854system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050844 # miss rate for ReadReq accesses 855system.cpu0.icache.ReadReq_miss_rate::total 0.050844 # miss rate for ReadReq accesses 856system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050844 # miss rate for demand accesses 857system.cpu0.icache.demand_miss_rate::total 0.050844 # miss rate for demand accesses 858system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050844 # miss rate for overall accesses 859system.cpu0.icache.overall_miss_rate::total 0.050844 # miss rate for overall accesses 860system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9557.809787 # average ReadReq miss latency 861system.cpu0.icache.ReadReq_avg_miss_latency::total 9557.809787 # average ReadReq miss latency 862system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency 863system.cpu0.icache.demand_avg_miss_latency::total 9557.809787 # average overall miss latency 864system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency 865system.cpu0.icache.overall_avg_miss_latency::total 9557.809787 # average overall miss latency 866system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 867system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 868system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 869system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 870system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 871system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 872system.cpu0.icache.writebacks::writebacks 1962004 # number of writebacks 873system.cpu0.icache.writebacks::total 1962004 # number of writebacks 874system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1962531 # number of ReadReq MSHR misses 875system.cpu0.icache.ReadReq_mshr_misses::total 1962531 # number of ReadReq MSHR misses 876system.cpu0.icache.demand_mshr_misses::cpu0.inst 1962531 # number of demand (read+write) MSHR misses 877system.cpu0.icache.demand_mshr_misses::total 1962531 # number of demand (read+write) MSHR misses 878system.cpu0.icache.overall_mshr_misses::cpu0.inst 1962531 # number of overall MSHR misses 879system.cpu0.icache.overall_mshr_misses::total 1962531 # number of overall MSHR misses 880system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable 881system.cpu0.icache.ReadReq_mshr_uncacheable::total 3449 # number of ReadReq MSHR uncacheable 882system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses 883system.cpu0.icache.overall_mshr_uncacheable_misses::total 3449 # number of overall MSHR uncacheable misses 884system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17776233000 # number of ReadReq MSHR miss cycles 885system.cpu0.icache.ReadReq_mshr_miss_latency::total 17776233000 # number of ReadReq MSHR miss cycles 886system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17776233000 # number of demand (read+write) MSHR miss cycles 887system.cpu0.icache.demand_mshr_miss_latency::total 17776233000 # number of demand (read+write) MSHR miss cycles 888system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17776233000 # number of overall MSHR miss cycles 889system.cpu0.icache.overall_mshr_miss_latency::total 17776233000 # number of overall MSHR miss cycles 890system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319470000 # number of ReadReq MSHR uncacheable cycles 891system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319470000 # number of ReadReq MSHR uncacheable cycles 892system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319470000 # number of overall MSHR uncacheable cycles 893system.cpu0.icache.overall_mshr_uncacheable_latency::total 319470000 # number of overall MSHR uncacheable cycles 894system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for ReadReq accesses 895system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050844 # mshr miss rate for ReadReq accesses 896system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for demand accesses 897system.cpu0.icache.demand_mshr_miss_rate::total 0.050844 # mshr miss rate for demand accesses 898system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for overall accesses 899system.cpu0.icache.overall_mshr_miss_rate::total 0.050844 # mshr miss rate for overall accesses 900system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average ReadReq mshr miss latency 901system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9057.810042 # average ReadReq mshr miss latency 902system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency 903system.cpu0.icache.demand_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency 904system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency 905system.cpu0.icache.overall_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency 906system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average ReadReq mshr uncacheable latency 907system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency 908system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency 909system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency 910system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 911system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued 912system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified 913system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue 914system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 915system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 916system.cpu0.l2cache.prefetcher.pfSpanPage 233630 # number of prefetches not generated due to page crossing 917system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 918system.cpu0.l2cache.tags.replacements 298119 # number of replacements 919system.cpu0.l2cache.tags.tagsinuse 16125.660847 # Cycle average of tags in use 920system.cpu0.l2cache.tags.total_refs 4682482 # Total number of references to valid blocks. 921system.cpu0.l2cache.tags.sampled_refs 314209 # Sample count of references to valid blocks. 922system.cpu0.l2cache.tags.avg_refs 14.902444 # Average number of references to valid blocks. 923system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 924system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.008973 # Average occupied blocks per requestor 925system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.059574 # Average occupied blocks per requestor 926system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.057522 # Average occupied blocks per requestor 927system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1311.534778 # Average occupied blocks per requestor 928system.cpu0.l2cache.tags.occ_percent::writebacks 0.900635 # Average percentage of cache occupancy 929system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003544 # Average percentage of cache occupancy 930system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 931system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.080050 # Average percentage of cache occupancy 932system.cpu0.l2cache.tags.occ_percent::total 0.984232 # Average percentage of cache occupancy 933system.cpu0.l2cache.tags.occ_task_id_blocks::1022 965 # Occupied blocks per task id 934system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 935system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15115 # Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id 938system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 400 # Occupied blocks per task id 939system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 257 # Occupied blocks per task id 940system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 941system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 942system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 943system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 944system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 945system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4162 # Occupied blocks per task id 946system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7775 # Occupied blocks per task id 947system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2779 # Occupied blocks per task id 948system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058899 # Percentage of cache occupancy per task id 949system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 950system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id 951system.cpu0.l2cache.tags.tag_accesses 89320549 # Number of tag accesses 952system.cpu0.l2cache.tags.data_accesses 89320549 # Number of data accesses 953system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 954system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82730 # number of ReadReq hits 955system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5417 # number of ReadReq hits 956system.cpu0.l2cache.ReadReq_hits::total 88147 # number of ReadReq hits 957system.cpu0.l2cache.WritebackDirty_hits::writebacks 481961 # number of WritebackDirty hits 958system.cpu0.l2cache.WritebackDirty_hits::total 481961 # number of WritebackDirty hits 959system.cpu0.l2cache.WritebackClean_hits::writebacks 2152508 # number of WritebackClean hits 960system.cpu0.l2cache.WritebackClean_hits::total 2152508 # number of WritebackClean hits 961system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits 962system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 963system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222191 # number of ReadExReq hits 964system.cpu0.l2cache.ReadExReq_hits::total 222191 # number of ReadExReq hits 965system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1894118 # number of ReadCleanReq hits 966system.cpu0.l2cache.ReadCleanReq_hits::total 1894118 # number of ReadCleanReq hits 967system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 400891 # number of ReadSharedReq hits 968system.cpu0.l2cache.ReadSharedReq_hits::total 400891 # number of ReadSharedReq hits 969system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 82730 # number of demand (read+write) hits 970system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5417 # number of demand (read+write) hits 971system.cpu0.l2cache.demand_hits::cpu0.inst 1894118 # number of demand (read+write) hits 972system.cpu0.l2cache.demand_hits::cpu0.data 623082 # number of demand (read+write) hits 973system.cpu0.l2cache.demand_hits::total 2605347 # number of demand (read+write) hits 974system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 82730 # number of overall hits 975system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5417 # number of overall hits 976system.cpu0.l2cache.overall_hits::cpu0.inst 1894118 # number of overall hits 977system.cpu0.l2cache.overall_hits::cpu0.data 623082 # number of overall hits 978system.cpu0.l2cache.overall_hits::total 2605347 # number of overall hits 979system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 856 # number of ReadReq misses 980system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 128 # number of ReadReq misses 981system.cpu0.l2cache.ReadReq_misses::total 984 # number of ReadReq misses 982system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56746 # number of UpgradeReq misses 983system.cpu0.l2cache.UpgradeReq_misses::total 56746 # number of UpgradeReq misses 984system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20566 # number of SCUpgradeReq misses 985system.cpu0.l2cache.SCUpgradeReq_misses::total 20566 # number of SCUpgradeReq misses 986system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 987system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 988system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46690 # number of ReadExReq misses 989system.cpu0.l2cache.ReadExReq_misses::total 46690 # number of ReadExReq misses 990system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 68413 # number of ReadCleanReq misses 991system.cpu0.l2cache.ReadCleanReq_misses::total 68413 # number of ReadCleanReq misses 992system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100633 # number of ReadSharedReq misses 993system.cpu0.l2cache.ReadSharedReq_misses::total 100633 # number of ReadSharedReq misses 994system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 856 # number of demand (read+write) misses 995system.cpu0.l2cache.demand_misses::cpu0.itb.walker 128 # number of demand (read+write) misses 996system.cpu0.l2cache.demand_misses::cpu0.inst 68413 # number of demand (read+write) misses 997system.cpu0.l2cache.demand_misses::cpu0.data 147323 # number of demand (read+write) misses 998system.cpu0.l2cache.demand_misses::total 216720 # number of demand (read+write) misses 999system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 856 # number of overall misses 1000system.cpu0.l2cache.overall_misses::cpu0.itb.walker 128 # number of overall misses 1001system.cpu0.l2cache.overall_misses::cpu0.inst 68413 # number of overall misses 1002system.cpu0.l2cache.overall_misses::cpu0.data 147323 # number of overall misses 1003system.cpu0.l2cache.overall_misses::total 216720 # number of overall misses 1004system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 28767000 # number of ReadReq miss cycles 1005system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2997000 # number of ReadReq miss cycles 1006system.cpu0.l2cache.ReadReq_miss_latency::total 31764000 # number of ReadReq miss cycles 1007system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 121525500 # number of UpgradeReq miss cycles 1008system.cpu0.l2cache.UpgradeReq_miss_latency::total 121525500 # number of UpgradeReq miss cycles 1009system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 25214000 # number of SCUpgradeReq miss cycles 1010system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 25214000 # number of SCUpgradeReq miss cycles 1011system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 212499 # number of SCUpgradeFailReq miss cycles 1012system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 212499 # number of SCUpgradeFailReq miss cycles 1013system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2304231000 # number of ReadExReq miss cycles 1014system.cpu0.l2cache.ReadExReq_miss_latency::total 2304231000 # number of ReadExReq miss cycles 1015system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3342274500 # number of ReadCleanReq miss cycles 1016system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3342274500 # number of ReadCleanReq miss cycles 1017system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3044310495 # number of ReadSharedReq miss cycles 1018system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3044310495 # number of ReadSharedReq miss cycles 1019system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 28767000 # number of demand (read+write) miss cycles 1020system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2997000 # number of demand (read+write) miss cycles 1021system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3342274500 # number of demand (read+write) miss cycles 1022system.cpu0.l2cache.demand_miss_latency::cpu0.data 5348541495 # number of demand (read+write) miss cycles 1023system.cpu0.l2cache.demand_miss_latency::total 8722579995 # number of demand (read+write) miss cycles 1024system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 28767000 # number of overall miss cycles 1025system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2997000 # number of overall miss cycles 1026system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3342274500 # number of overall miss cycles 1027system.cpu0.l2cache.overall_miss_latency::cpu0.data 5348541495 # number of overall miss cycles 1028system.cpu0.l2cache.overall_miss_latency::total 8722579995 # number of overall miss cycles 1029system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 83586 # number of ReadReq accesses(hits+misses) 1030system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5545 # number of ReadReq accesses(hits+misses) 1031system.cpu0.l2cache.ReadReq_accesses::total 89131 # number of ReadReq accesses(hits+misses) 1032system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481961 # number of WritebackDirty accesses(hits+misses) 1033system.cpu0.l2cache.WritebackDirty_accesses::total 481961 # number of WritebackDirty accesses(hits+misses) 1034system.cpu0.l2cache.WritebackClean_accesses::writebacks 2152508 # number of WritebackClean accesses(hits+misses) 1035system.cpu0.l2cache.WritebackClean_accesses::total 2152508 # number of WritebackClean accesses(hits+misses) 1036system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56747 # number of UpgradeReq accesses(hits+misses) 1037system.cpu0.l2cache.UpgradeReq_accesses::total 56747 # number of UpgradeReq accesses(hits+misses) 1038system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20566 # number of SCUpgradeReq accesses(hits+misses) 1039system.cpu0.l2cache.SCUpgradeReq_accesses::total 20566 # number of SCUpgradeReq accesses(hits+misses) 1040system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1041system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1042system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268881 # number of ReadExReq accesses(hits+misses) 1043system.cpu0.l2cache.ReadExReq_accesses::total 268881 # number of ReadExReq accesses(hits+misses) 1044system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1962531 # number of ReadCleanReq accesses(hits+misses) 1045system.cpu0.l2cache.ReadCleanReq_accesses::total 1962531 # number of ReadCleanReq accesses(hits+misses) 1046system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 501524 # number of ReadSharedReq accesses(hits+misses) 1047system.cpu0.l2cache.ReadSharedReq_accesses::total 501524 # number of ReadSharedReq accesses(hits+misses) 1048system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 83586 # number of demand (read+write) accesses 1049system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5545 # number of demand (read+write) accesses 1050system.cpu0.l2cache.demand_accesses::cpu0.inst 1962531 # number of demand (read+write) accesses 1051system.cpu0.l2cache.demand_accesses::cpu0.data 770405 # number of demand (read+write) accesses 1052system.cpu0.l2cache.demand_accesses::total 2822067 # number of demand (read+write) accesses 1053system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 83586 # number of overall (read+write) accesses 1054system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5545 # number of overall (read+write) accesses 1055system.cpu0.l2cache.overall_accesses::cpu0.inst 1962531 # number of overall (read+write) accesses 1056system.cpu0.l2cache.overall_accesses::cpu0.data 770405 # number of overall (read+write) accesses 1057system.cpu0.l2cache.overall_accesses::total 2822067 # number of overall (read+write) accesses 1058system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010241 # miss rate for ReadReq accesses 1059system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.023084 # miss rate for ReadReq accesses 1060system.cpu0.l2cache.ReadReq_miss_rate::total 0.011040 # miss rate for ReadReq accesses 1061system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses 1062system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses 1063system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1064system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1065system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1066system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1067system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.173646 # miss rate for ReadExReq accesses 1068system.cpu0.l2cache.ReadExReq_miss_rate::total 0.173646 # miss rate for ReadExReq accesses 1069system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034860 # miss rate for ReadCleanReq accesses 1070system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034860 # miss rate for ReadCleanReq accesses 1071system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.200654 # miss rate for ReadSharedReq accesses 1072system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.200654 # miss rate for ReadSharedReq accesses 1073system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010241 # miss rate for demand accesses 1074system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.023084 # miss rate for demand accesses 1075system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034860 # miss rate for demand accesses 1076system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.191228 # miss rate for demand accesses 1077system.cpu0.l2cache.demand_miss_rate::total 0.076795 # miss rate for demand accesses 1078system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010241 # miss rate for overall accesses 1079system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.023084 # miss rate for overall accesses 1080system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034860 # miss rate for overall accesses 1081system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.191228 # miss rate for overall accesses 1082system.cpu0.l2cache.overall_miss_rate::total 0.076795 # miss rate for overall accesses 1083system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33606.308411 # average ReadReq miss latency 1084system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23414.062500 # average ReadReq miss latency 1085system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32280.487805 # average ReadReq miss latency 1086system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2141.569450 # average UpgradeReq miss latency 1087system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2141.569450 # average UpgradeReq miss latency 1088system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1226.004084 # average SCUpgradeReq miss latency 1089system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1226.004084 # average SCUpgradeReq miss latency 1090system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 212499 # average SCUpgradeFailReq miss latency 1091system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 212499 # average SCUpgradeFailReq miss latency 1092system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49351.702720 # average ReadExReq miss latency 1093system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49351.702720 # average ReadExReq miss latency 1094system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48854.377092 # average ReadCleanReq miss latency 1095system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48854.377092 # average ReadCleanReq miss latency 1096system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30251.612244 # average ReadSharedReq miss latency 1097system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30251.612244 # average ReadSharedReq miss latency 1098system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33606.308411 # average overall miss latency 1099system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23414.062500 # average overall miss latency 1100system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48854.377092 # average overall miss latency 1101system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36304.864108 # average overall miss latency 1102system.cpu0.l2cache.demand_avg_miss_latency::total 40248.154277 # average overall miss latency 1103system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33606.308411 # average overall miss latency 1104system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23414.062500 # average overall miss latency 1105system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48854.377092 # average overall miss latency 1106system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36304.864108 # average overall miss latency 1107system.cpu0.l2cache.overall_avg_miss_latency::total 40248.154277 # average overall miss latency 1108system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1109system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1110system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1111system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1112system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1113system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1114system.cpu0.l2cache.unused_prefetches 11097 # number of HardPF blocks evicted w/o reference 1115system.cpu0.l2cache.writebacks::writebacks 233923 # number of writebacks 1116system.cpu0.l2cache.writebacks::total 233923 # number of writebacks 1117system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2672 # number of ReadExReq MSHR hits 1118system.cpu0.l2cache.ReadExReq_mshr_hits::total 2672 # number of ReadExReq MSHR hits 1119system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 73 # number of ReadCleanReq MSHR hits 1120system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 73 # number of ReadCleanReq MSHR hits 1121system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 384 # number of ReadSharedReq MSHR hits 1122system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 384 # number of ReadSharedReq MSHR hits 1123system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 73 # number of demand (read+write) MSHR hits 1124system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3056 # number of demand (read+write) MSHR hits 1125system.cpu0.l2cache.demand_mshr_hits::total 3129 # number of demand (read+write) MSHR hits 1126system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 73 # number of overall MSHR hits 1127system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3056 # number of overall MSHR hits 1128system.cpu0.l2cache.overall_mshr_hits::total 3129 # number of overall MSHR hits 1129system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 856 # number of ReadReq MSHR misses 1130system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 128 # number of ReadReq MSHR misses 1131system.cpu0.l2cache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses 1132system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 258926 # number of HardPFReq MSHR misses 1133system.cpu0.l2cache.HardPFReq_mshr_misses::total 258926 # number of HardPFReq MSHR misses 1134system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56746 # number of UpgradeReq MSHR misses 1135system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56746 # number of UpgradeReq MSHR misses 1136system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20566 # number of SCUpgradeReq MSHR misses 1137system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20566 # number of SCUpgradeReq MSHR misses 1138system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1139system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1140system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 44018 # number of ReadExReq MSHR misses 1141system.cpu0.l2cache.ReadExReq_mshr_misses::total 44018 # number of ReadExReq MSHR misses 1142system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 68340 # number of ReadCleanReq MSHR misses 1143system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 68340 # number of ReadCleanReq MSHR misses 1144system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100249 # number of ReadSharedReq MSHR misses 1145system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100249 # number of ReadSharedReq MSHR misses 1146system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 856 # number of demand (read+write) MSHR misses 1147system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 128 # number of demand (read+write) MSHR misses 1148system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 68340 # number of demand (read+write) MSHR misses 1149system.cpu0.l2cache.demand_mshr_misses::cpu0.data 144267 # number of demand (read+write) MSHR misses 1150system.cpu0.l2cache.demand_mshr_misses::total 213591 # number of demand (read+write) MSHR misses 1151system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 856 # number of overall MSHR misses 1152system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 128 # number of overall MSHR misses 1153system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 68340 # number of overall MSHR misses 1154system.cpu0.l2cache.overall_mshr_misses::cpu0.data 144267 # number of overall MSHR misses 1155system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 258926 # number of overall MSHR misses 1156system.cpu0.l2cache.overall_mshr_misses::total 472517 # number of overall MSHR misses 1157system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable 1158system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable 1159system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 24024 # number of ReadReq MSHR uncacheable 1160system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable 1161system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19271 # number of WriteReq MSHR uncacheable 1162system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses 1163system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses 1164system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43295 # number of overall MSHR uncacheable misses 1165system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 23631000 # number of ReadReq MSHR miss cycles 1166system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2229000 # number of ReadReq MSHR miss cycles 1167system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 25860000 # number of ReadReq MSHR miss cycles 1168system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14017177372 # number of HardPFReq MSHR miss cycles 1169system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14017177372 # number of HardPFReq MSHR miss cycles 1170system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1114674000 # number of UpgradeReq MSHR miss cycles 1171system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1114674000 # number of UpgradeReq MSHR miss cycles 1172system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 322353500 # number of SCUpgradeReq MSHR miss cycles 1173system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 322353500 # number of SCUpgradeReq MSHR miss cycles 1174system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 176499 # number of SCUpgradeFailReq MSHR miss cycles 1175system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 176499 # number of SCUpgradeFailReq MSHR miss cycles 1176system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1755037000 # number of ReadExReq MSHR miss cycles 1177system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1755037000 # number of ReadExReq MSHR miss cycles 1178system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2929882500 # number of ReadCleanReq MSHR miss cycles 1179system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2929882500 # number of ReadCleanReq MSHR miss cycles 1180system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2420870995 # number of ReadSharedReq MSHR miss cycles 1181system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2420870995 # number of ReadSharedReq MSHR miss cycles 1182system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 23631000 # number of demand (read+write) MSHR miss cycles 1183system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2229000 # number of demand (read+write) MSHR miss cycles 1184system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2929882500 # number of demand (read+write) MSHR miss cycles 1185system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4175907995 # number of demand (read+write) MSHR miss cycles 1186system.cpu0.l2cache.demand_mshr_miss_latency::total 7131650495 # number of demand (read+write) MSHR miss cycles 1187system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 23631000 # number of overall MSHR miss cycles 1188system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2229000 # number of overall MSHR miss cycles 1189system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2929882500 # number of overall MSHR miss cycles 1190system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4175907995 # number of overall MSHR miss cycles 1191system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14017177372 # number of overall MSHR miss cycles 1192system.cpu0.l2cache.overall_mshr_miss_latency::total 21148827867 # number of overall MSHR miss cycles 1193system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 291877500 # number of ReadReq MSHR uncacheable cycles 1194system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4450889000 # number of ReadReq MSHR uncacheable cycles 1195system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4742766500 # number of ReadReq MSHR uncacheable cycles 1196system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 291877500 # number of overall MSHR uncacheable cycles 1197system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4450889000 # number of overall MSHR uncacheable cycles 1198system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4742766500 # number of overall MSHR uncacheable cycles 1199system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for ReadReq accesses 1200system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for ReadReq accesses 1201system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.011040 # mshr miss rate for ReadReq accesses 1202system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1203system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1204system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses 1205system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses 1206system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1207system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1208system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1209system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1210system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163708 # mshr miss rate for ReadExReq accesses 1211system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163708 # mshr miss rate for ReadExReq accesses 1212system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for ReadCleanReq accesses 1213system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034822 # mshr miss rate for ReadCleanReq accesses 1214system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.199889 # mshr miss rate for ReadSharedReq accesses 1215system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.199889 # mshr miss rate for ReadSharedReq accesses 1216system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for demand accesses 1217system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for demand accesses 1218system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for demand accesses 1219system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for demand accesses 1220system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075686 # mshr miss rate for demand accesses 1221system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for overall accesses 1222system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for overall accesses 1223system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for overall accesses 1224system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for overall accesses 1225system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1226system.cpu0.l2cache.overall_mshr_miss_rate::total 0.167436 # mshr miss rate for overall accesses 1227system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average ReadReq mshr miss latency 1228system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average ReadReq mshr miss latency 1229system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26280.487805 # average ReadReq mshr miss latency 1230system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average HardPFReq mshr miss latency 1231system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54135.843337 # average HardPFReq mshr miss latency 1232system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19643.217143 # average UpgradeReq mshr miss latency 1233system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19643.217143 # average UpgradeReq mshr miss latency 1234system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15674.098026 # average SCUpgradeReq mshr miss latency 1235system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15674.098026 # average SCUpgradeReq mshr miss latency 1236system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 176499 # average SCUpgradeFailReq mshr miss latency 1237system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 176499 # average SCUpgradeFailReq mshr miss latency 1238system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39870.893725 # average ReadExReq mshr miss latency 1239system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39870.893725 # average ReadExReq mshr miss latency 1240system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average ReadCleanReq mshr miss latency 1241system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42872.146620 # average ReadCleanReq mshr miss latency 1242system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24148.579986 # average ReadSharedReq mshr miss latency 1243system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24148.579986 # average ReadSharedReq mshr miss latency 1244system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency 1245system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency 1246system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency 1247system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency 1248system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33389.283701 # average overall mshr miss latency 1249system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency 1250system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency 1251system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency 1252system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency 1253system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average overall mshr miss latency 1254system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44757.813723 # average overall mshr miss latency 1255system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average ReadReq mshr uncacheable latency 1256system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 216325.103281 # average ReadReq mshr uncacheable latency 1257system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197417.852980 # average ReadReq mshr uncacheable latency 1258system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average overall mshr uncacheable latency 1259system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111702.278773 # average overall mshr uncacheable latency 1260system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109545.363206 # average overall mshr uncacheable latency 1261system.cpu0.toL2Bus.snoop_filter.tot_requests 5508026 # Total number of requests made to the snoop filter. 1262system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2775137 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1263system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42660 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1264system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter. 1265system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1266system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1267system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1268system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution 1269system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution 1270system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution 1271system.cpu0.toL2Bus.trans_dist::WriteResp 19271 # Transaction distribution 1272system.cpu0.toL2Bus.trans_dist::WritebackDirty 716131 # Transaction distribution 1273system.cpu0.toL2Bus.trans_dist::WritebackClean 2195168 # Transaction distribution 1274system.cpu0.toL2Bus.trans_dist::CleanEvict 240019 # Transaction distribution 1275system.cpu0.toL2Bus.trans_dist::HardPFReq 309687 # Transaction distribution 1276system.cpu0.toL2Bus.trans_dist::UpgradeReq 88590 # Transaction distribution 1277system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43220 # Transaction distribution 1278system.cpu0.toL2Bus.trans_dist::UpgradeResp 114518 # Transaction distribution 1279system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::ReadExReq 288089 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::ReadExResp 284462 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1962531 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586533 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::InvalidateReq 3131 # Transaction distribution 1286system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5893963 # Packet count per connected master and slave (bytes) 1287system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2592135 # Packet count per connected master and slave (bytes) 1288system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13195 # Packet count per connected master and slave (bytes) 1289system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174334 # Packet count per connected master and slave (bytes) 1290system.cpu0.toL2Bus.pkt_count::total 8673627 # Packet count per connected master and slave (bytes) 1291system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251390912 # Cumulative packet size per connected master and slave (bytes) 1292system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99322292 # Cumulative packet size per connected master and slave (bytes) 1293system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22180 # Cumulative packet size per connected master and slave (bytes) 1294system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 334344 # Cumulative packet size per connected master and slave (bytes) 1295system.cpu0.toL2Bus.pkt_size::total 351069728 # Cumulative packet size per connected master and slave (bytes) 1296system.cpu0.toL2Bus.snoops 1056913 # Total snoops (count) 1297system.cpu0.toL2Bus.snoop_fanout::samples 3897709 # Request fanout histogram 1298system.cpu0.toL2Bus.snoop_fanout::mean 0.106693 # Request fanout histogram 1299system.cpu0.toL2Bus.snoop_fanout::stdev 0.313582 # Request fanout histogram 1300system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1301system.cpu0.toL2Bus.snoop_fanout::0 3487742 89.48% 89.48% # Request fanout histogram 1302system.cpu0.toL2Bus.snoop_fanout::1 404074 10.37% 99.85% # Request fanout histogram 1303system.cpu0.toL2Bus.snoop_fanout::2 5893 0.15% 100.00% # Request fanout histogram 1304system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1305system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1306system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1307system.cpu0.toL2Bus.snoop_fanout::total 3897709 # Request fanout histogram 1308system.cpu0.toL2Bus.reqLayer0.occupancy 5501303494 # Layer occupancy (ticks) 1309system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1310system.cpu0.toL2Bus.snoopLayer0.occupancy 115667783 # Layer occupancy (ticks) 1311system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1312system.cpu0.toL2Bus.respLayer0.occupancy 2949460514 # Layer occupancy (ticks) 1313system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1314system.cpu0.toL2Bus.respLayer1.occupancy 1225261932 # Layer occupancy (ticks) 1315system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1316system.cpu0.toL2Bus.respLayer2.occupancy 7656487 # Layer occupancy (ticks) 1317system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1318system.cpu0.toL2Bus.respLayer3.occupancy 90771952 # Layer occupancy (ticks) 1319system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1320system.cpu1.branchPred.lookups 19337823 # Number of BP lookups 1321system.cpu1.branchPred.condPredicted 6215951 # Number of conditional branches predicted 1322system.cpu1.branchPred.condIncorrect 910078 # Number of conditional branches incorrect 1323system.cpu1.branchPred.BTBLookups 9913117 # Number of BTB lookups 1324system.cpu1.branchPred.BTBHits 3669706 # Number of BTB hits 1325system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1326system.cpu1.branchPred.BTBHitPct 37.018689 # BTB Hit Percentage 1327system.cpu1.branchPred.usedRAS 8699112 # Number of times the RAS was used to get a target. 1328system.cpu1.branchPred.RASInCorrect 707232 # Number of incorrect RAS predictions. 1329system.cpu1.branchPred.indirectLookups 3579063 # Number of indirect predictor lookups. 1330system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits. 1331system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses. 1332system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches. 1333system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1334system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1335system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1336system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1339system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1340system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1341system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1342system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1343system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1344system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1345system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1346system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1347system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1348system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1349system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1350system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1351system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1352system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1353system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1354system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1355system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1356system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1357system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1358system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1359system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1360system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1361system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1362system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1363system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1364system.cpu1.dtb.walker.walks 26974 # Table walker walks requested 1365system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors 1366system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate 1367system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6887 # Level at which table walker walks with short descriptors terminate 1368system.cpu1.dtb.walker.walkWaitTime::samples 26974 # Table walker wait (enqueue to first request) latency 1369system.cpu1.dtb.walker.walkWaitTime::0 26974 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1370system.cpu1.dtb.walker.walkWaitTime::total 26974 # Table walker wait (enqueue to first request) latency 1371system.cpu1.dtb.walker.walkCompletionTime::samples 2714 # Table walker service (enqueue to completion) latency 1372system.cpu1.dtb.walker.walkCompletionTime::mean 11914.148858 # Table walker service (enqueue to completion) latency 1373system.cpu1.dtb.walker.walkCompletionTime::gmean 11049.041659 # Table walker service (enqueue to completion) latency 1374system.cpu1.dtb.walker.walkCompletionTime::stdev 5760.245338 # Table walker service (enqueue to completion) latency 1375system.cpu1.dtb.walker.walkCompletionTime::0-8191 673 24.80% 24.80% # Table walker service (enqueue to completion) latency 1376system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1844 67.94% 92.74% # Table walker service (enqueue to completion) latency 1377system.cpu1.dtb.walker.walkCompletionTime::16384-24575 118 4.35% 97.09% # Table walker service (enqueue to completion) latency 1378system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.06% 99.15% # Table walker service (enqueue to completion) latency 1379system.cpu1.dtb.walker.walkCompletionTime::32768-40959 13 0.48% 99.63% # Table walker service (enqueue to completion) latency 1380system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency 1381system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency 1382system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walkCompletionTime::total 2714 # Table walker service (enqueue to completion) latency 1386system.cpu1.dtb.walker.walksPending::samples -2024068032 # Table walker pending requests distribution 1387system.cpu1.dtb.walker.walksPending::0 -2024068032 100.00% 100.00% # Table walker pending requests distribution 1388system.cpu1.dtb.walker.walksPending::total -2024068032 # Table walker pending requests distribution 1389system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.58% 73.58% # Table walker page sizes translated 1390system.cpu1.dtb.walker.walkPageSizes::1M 717 26.42% 100.00% # Table walker page sizes translated 1391system.cpu1.dtb.walker.walkPageSizes::total 2714 # Table walker page sizes translated 1392system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26974 # Table walker requests started/completed, data/inst 1393system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1394system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26974 # Table walker requests started/completed, data/inst 1395system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2714 # Table walker requests started/completed, data/inst 1396system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1397system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2714 # Table walker requests started/completed, data/inst 1398system.cpu1.dtb.walker.walkRequestOrigin::total 29688 # Table walker requests started/completed, data/inst 1399system.cpu1.dtb.inst_hits 0 # ITB inst hits 1400system.cpu1.dtb.inst_misses 0 # ITB inst misses 1401system.cpu1.dtb.read_hits 11185393 # DTB read hits 1402system.cpu1.dtb.read_misses 25019 # DTB read misses 1403system.cpu1.dtb.write_hits 6992115 # DTB write hits 1404system.cpu1.dtb.write_misses 1955 # DTB write misses 1405system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1406system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1407system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1408system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1409system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB	1409system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB
1410system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions 1411system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch 1412system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1413system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions 1414system.cpu1.dtb.read_accesses 11210412 # DTB read accesses 1415system.cpu1.dtb.write_accesses 6994070 # DTB write accesses 1416system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1417system.cpu1.dtb.hits 18177508 # DTB hits 1418system.cpu1.dtb.misses 26974 # DTB misses 1419system.cpu1.dtb.accesses 18204482 # DTB accesses 1420system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1421system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1422system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1427system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1428system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1429system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1430system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1431system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1432system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1433system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1434system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1435system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1436system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1437system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1438system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1439system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1440system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1441system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1442system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1443system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1444system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1445system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1446system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1447system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1448system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1449system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1450system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1451system.cpu1.itb.walker.walks 2420 # Table walker walks requested 1452system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors 1453system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1454system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2239 # Level at which table walker walks with short descriptors terminate 1455system.cpu1.itb.walker.walkWaitTime::samples 2420 # Table walker wait (enqueue to first request) latency 1456system.cpu1.itb.walker.walkWaitTime::0 2420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1457system.cpu1.itb.walker.walkWaitTime::total 2420 # Table walker wait (enqueue to first request) latency 1458system.cpu1.itb.walker.walkCompletionTime::samples 1133 # Table walker service (enqueue to completion) latency 1459system.cpu1.itb.walker.walkCompletionTime::mean 12165.931156 # Table walker service (enqueue to completion) latency 1460system.cpu1.itb.walker.walkCompletionTime::gmean 11504.985007 # Table walker service (enqueue to completion) latency 1461system.cpu1.itb.walker.walkCompletionTime::stdev 4742.932714 # Table walker service (enqueue to completion) latency 1462system.cpu1.itb.walker.walkCompletionTime::4096-8191 196 17.30% 17.30% # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::8192-12287 640 56.49% 73.79% # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::12288-16383 219 19.33% 93.12% # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::16384-20479 41 3.62% 96.73% # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.91% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.32% 98.23% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.71% 98.94% # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.26% 99.21% # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.44% 99.65% # Table walker service (enqueue to completion) latency 1471system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.82% # Table walker service (enqueue to completion) latency 1472system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1474system.cpu1.itb.walker.walkCompletionTime::total 1133 # Table walker service (enqueue to completion) latency 1475system.cpu1.itb.walker.walksPending::samples -2024645532 # Table walker pending requests distribution 1476system.cpu1.itb.walker.walksPending::0 -2024645532 100.00% 100.00% # Table walker pending requests distribution 1477system.cpu1.itb.walker.walksPending::total -2024645532 # Table walker pending requests distribution 1478system.cpu1.itb.walker.walkPageSizes::4K 964 85.08% 85.08% # Table walker page sizes translated 1479system.cpu1.itb.walker.walkPageSizes::1M 169 14.92% 100.00% # Table walker page sizes translated 1480system.cpu1.itb.walker.walkPageSizes::total 1133 # Table walker page sizes translated 1481system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1482system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2420 # Table walker requests started/completed, data/inst 1483system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2420 # Table walker requests started/completed, data/inst 1484system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1485system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1133 # Table walker requests started/completed, data/inst 1486system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1133 # Table walker requests started/completed, data/inst 1487system.cpu1.itb.walker.walkRequestOrigin::total 3553 # Table walker requests started/completed, data/inst 1488system.cpu1.itb.inst_hits 39602800 # ITB inst hits 1489system.cpu1.itb.inst_misses 2420 # ITB inst misses 1490system.cpu1.itb.read_hits 0 # DTB read hits 1491system.cpu1.itb.read_misses 0 # DTB read misses 1492system.cpu1.itb.write_hits 0 # DTB write hits 1493system.cpu1.itb.write_misses 0 # DTB write misses 1494system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1495system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1496system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1497system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	1410system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions 1411system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch 1412system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1413system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions 1414system.cpu1.dtb.read_accesses 11210412 # DTB read accesses 1415system.cpu1.dtb.write_accesses 6994070 # DTB write accesses 1416system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1417system.cpu1.dtb.hits 18177508 # DTB hits 1418system.cpu1.dtb.misses 26974 # DTB misses 1419system.cpu1.dtb.accesses 18204482 # DTB accesses 1420system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1421system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1422system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1427system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1428system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1429system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1430system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1431system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1432system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1433system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1434system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1435system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1436system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1437system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1438system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1439system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1440system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1441system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1442system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1443system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1444system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1445system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1446system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1447system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1448system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1449system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1450system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1451system.cpu1.itb.walker.walks 2420 # Table walker walks requested 1452system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors 1453system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1454system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2239 # Level at which table walker walks with short descriptors terminate 1455system.cpu1.itb.walker.walkWaitTime::samples 2420 # Table walker wait (enqueue to first request) latency 1456system.cpu1.itb.walker.walkWaitTime::0 2420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1457system.cpu1.itb.walker.walkWaitTime::total 2420 # Table walker wait (enqueue to first request) latency 1458system.cpu1.itb.walker.walkCompletionTime::samples 1133 # Table walker service (enqueue to completion) latency 1459system.cpu1.itb.walker.walkCompletionTime::mean 12165.931156 # Table walker service (enqueue to completion) latency 1460system.cpu1.itb.walker.walkCompletionTime::gmean 11504.985007 # Table walker service (enqueue to completion) latency 1461system.cpu1.itb.walker.walkCompletionTime::stdev 4742.932714 # Table walker service (enqueue to completion) latency 1462system.cpu1.itb.walker.walkCompletionTime::4096-8191 196 17.30% 17.30% # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::8192-12287 640 56.49% 73.79% # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::12288-16383 219 19.33% 93.12% # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::16384-20479 41 3.62% 96.73% # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.91% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.32% 98.23% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.71% 98.94% # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.26% 99.21% # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.44% 99.65% # Table walker service (enqueue to completion) latency 1471system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.82% # Table walker service (enqueue to completion) latency 1472system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1474system.cpu1.itb.walker.walkCompletionTime::total 1133 # Table walker service (enqueue to completion) latency 1475system.cpu1.itb.walker.walksPending::samples -2024645532 # Table walker pending requests distribution 1476system.cpu1.itb.walker.walksPending::0 -2024645532 100.00% 100.00% # Table walker pending requests distribution 1477system.cpu1.itb.walker.walksPending::total -2024645532 # Table walker pending requests distribution 1478system.cpu1.itb.walker.walkPageSizes::4K 964 85.08% 85.08% # Table walker page sizes translated 1479system.cpu1.itb.walker.walkPageSizes::1M 169 14.92% 100.00% # Table walker page sizes translated 1480system.cpu1.itb.walker.walkPageSizes::total 1133 # Table walker page sizes translated 1481system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1482system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2420 # Table walker requests started/completed, data/inst 1483system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2420 # Table walker requests started/completed, data/inst 1484system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1485system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1133 # Table walker requests started/completed, data/inst 1486system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1133 # Table walker requests started/completed, data/inst 1487system.cpu1.itb.walker.walkRequestOrigin::total 3553 # Table walker requests started/completed, data/inst 1488system.cpu1.itb.inst_hits 39602800 # ITB inst hits 1489system.cpu1.itb.inst_misses 2420 # ITB inst misses 1490system.cpu1.itb.read_hits 0 # DTB read hits 1491system.cpu1.itb.read_misses 0 # DTB read misses 1492system.cpu1.itb.write_hits 0 # DTB write hits 1493system.cpu1.itb.write_misses 0 # DTB write misses 1494system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1495system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1496system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1497system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1498system.cpu1.itb.flush_entries 1166 # Number of entries that have been flushed from TLB	1498system.cpu1.itb.flush_entries 1102 # Number of entries that have been flushed from TLB
1499system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1500system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1501system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1502system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions 1503system.cpu1.itb.read_accesses 0 # DTB read accesses 1504system.cpu1.itb.write_accesses 0 # DTB write accesses 1505system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses 1506system.cpu1.itb.hits 39602800 # DTB hits 1507system.cpu1.itb.misses 2420 # DTB misses 1508system.cpu1.itb.accesses 39605220 # DTB accesses 1509system.cpu1.numPwrStateTransitions 5553 # Number of power state transitions 1510system.cpu1.pwrStateClkGateDist::samples 2777 # Distribution of time spent in the clock gated state 1511system.cpu1.pwrStateClkGateDist::mean 1004505001.039251 # Distribution of time spent in the clock gated state 1512system.cpu1.pwrStateClkGateDist::stdev 25654466824.490025 # Distribution of time spent in the clock gated state 1513system.cpu1.pwrStateClkGateDist::underflows 1974 71.08% 71.08% # Distribution of time spent in the clock gated state 1514system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.77% 99.86% # Distribution of time spent in the clock gated state 1515system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1516system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1517system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1518system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1519system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1520system.cpu1.pwrStateClkGateDist::max_value 949981296504 # Distribution of time spent in the clock gated state 1521system.cpu1.pwrStateClkGateDist::total 2777 # Distribution of time spent in the clock gated state 1522system.cpu1.pwrStateResidencyTicks::ON 57717018114 # Cumulative time (in ticks) in various power states 1523system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789510387886 # Cumulative time (in ticks) in various power states 1524system.cpu1.numCycles 115435582 # number of cpu cycles simulated 1525system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1526system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1527system.cpu1.committedInsts 47603897 # Number of instructions committed 1528system.cpu1.committedOps 58246015 # Number of ops (including micro ops) committed 1529system.cpu1.discardedOps 5049538 # Number of ops (including micro ops) which were discarded before commit 1530system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching 1531system.cpu1.quiesceCycles 5578401245 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1532system.cpu1.cpi 2.424919 # CPI: cycles per instruction 1533system.cpu1.ipc 0.412385 # IPC: instructions per cycle 1534system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction 1535system.cpu1.op_class_0::IntAlu 40076529 68.81% 68.81% # Class of committed instruction 1536system.cpu1.op_class_0::IntMult 45752 0.08% 68.88% # Class of committed instruction 1537system.cpu1.op_class_0::IntDiv 0 0.00% 68.88% # Class of committed instruction 1538system.cpu1.op_class_0::FloatAdd 0 0.00% 68.88% # Class of committed instruction 1539system.cpu1.op_class_0::FloatCmp 0 0.00% 68.88% # Class of committed instruction 1540system.cpu1.op_class_0::FloatCvt 0 0.00% 68.88% # Class of committed instruction 1541system.cpu1.op_class_0::FloatMult 0 0.00% 68.88% # Class of committed instruction 1542system.cpu1.op_class_0::FloatDiv 0 0.00% 68.88% # Class of committed instruction 1543system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.88% # Class of committed instruction 1544system.cpu1.op_class_0::SimdAdd 0 0.00% 68.88% # Class of committed instruction 1545system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.88% # Class of committed instruction 1546system.cpu1.op_class_0::SimdAlu 0 0.00% 68.88% # Class of committed instruction 1547system.cpu1.op_class_0::SimdCmp 0 0.00% 68.88% # Class of committed instruction 1548system.cpu1.op_class_0::SimdCvt 0 0.00% 68.88% # Class of committed instruction 1549system.cpu1.op_class_0::SimdMisc 0 0.00% 68.88% # Class of committed instruction 1550system.cpu1.op_class_0::SimdMult 0 0.00% 68.88% # Class of committed instruction 1551system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.88% # Class of committed instruction 1552system.cpu1.op_class_0::SimdShift 0 0.00% 68.88% # Class of committed instruction 1553system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.88% # Class of committed instruction 1554system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.88% # Class of committed instruction 1555system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.88% # Class of committed instruction 1556system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.88% # Class of committed instruction 1557system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.88% # Class of committed instruction 1558system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.88% # Class of committed instruction 1559system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.88% # Class of committed instruction 1560system.cpu1.op_class_0::SimdFloatMisc 3347 0.01% 68.89% # Class of committed instruction 1561system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.89% # Class of committed instruction 1562system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.89% # Class of committed instruction 1563system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.89% # Class of committed instruction 1564system.cpu1.op_class_0::MemRead 11012402 18.91% 87.80% # Class of committed instruction 1565system.cpu1.op_class_0::MemWrite 7107919 12.20% 100.00% # Class of committed instruction 1566system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1567system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1568system.cpu1.op_class_0::total 58246015 # Class of committed instruction 1569system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1570system.cpu1.kern.inst.quiesce 2777 # number of quiesce instructions executed 1571system.cpu1.tickCycles 97896037 # Number of cycles that the object actually ticked 1572system.cpu1.idleCycles 17539545 # Total number of cycles that the object has spent stopped 1573system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1574system.cpu1.dcache.tags.replacements 196286 # number of replacements 1575system.cpu1.dcache.tags.tagsinuse 471.109798 # Cycle average of tags in use 1576system.cpu1.dcache.tags.total_refs 17737294 # Total number of references to valid blocks. 1577system.cpu1.dcache.tags.sampled_refs 196629 # Sample count of references to valid blocks. 1578system.cpu1.dcache.tags.avg_refs 90.206907 # Average number of references to valid blocks. 1579system.cpu1.dcache.tags.warmup_cycle 91177108000 # Cycle when the warmup percentage was hit. 1580system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.109798 # Average occupied blocks per requestor 1581system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920136 # Average percentage of cache occupancy 1582system.cpu1.dcache.tags.occ_percent::total 0.920136 # Average percentage of cache occupancy 1583system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id 1584system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 1585system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 1586system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id 1587system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses 1588system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses 1589system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1590system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits 1591system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits 1592system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits 1593system.cpu1.dcache.WriteReq_hits::total 6704752 # number of WriteReq hits 1594system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50350 # number of SoftPFReq hits 1595system.cpu1.dcache.SoftPFReq_hits::total 50350 # number of SoftPFReq hits 1596system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80171 # number of LoadLockedReq hits 1597system.cpu1.dcache.LoadLockedReq_hits::total 80171 # number of LoadLockedReq hits 1598system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71533 # number of StoreCondReq hits 1599system.cpu1.dcache.StoreCondReq_hits::total 71533 # number of StoreCondReq hits 1600system.cpu1.dcache.demand_hits::cpu1.data 17499828 # number of demand (read+write) hits 1601system.cpu1.dcache.demand_hits::total 17499828 # number of demand (read+write) hits 1602system.cpu1.dcache.overall_hits::cpu1.data 17550178 # number of overall hits 1603system.cpu1.dcache.overall_hits::total 17550178 # number of overall hits 1604system.cpu1.dcache.ReadReq_misses::cpu1.data 159722 # number of ReadReq misses 1605system.cpu1.dcache.ReadReq_misses::total 159722 # number of ReadReq misses 1606system.cpu1.dcache.WriteReq_misses::cpu1.data 145538 # number of WriteReq misses 1607system.cpu1.dcache.WriteReq_misses::total 145538 # number of WriteReq misses 1608system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31004 # number of SoftPFReq misses 1609system.cpu1.dcache.SoftPFReq_misses::total 31004 # number of SoftPFReq misses 1610system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses 1611system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses 1612system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23795 # number of StoreCondReq misses 1613system.cpu1.dcache.StoreCondReq_misses::total 23795 # number of StoreCondReq misses 1614system.cpu1.dcache.demand_misses::cpu1.data 305260 # number of demand (read+write) misses 1615system.cpu1.dcache.demand_misses::total 305260 # number of demand (read+write) misses 1616system.cpu1.dcache.overall_misses::cpu1.data 336264 # number of overall misses 1617system.cpu1.dcache.overall_misses::total 336264 # number of overall misses 1618system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2429598500 # number of ReadReq miss cycles 1619system.cpu1.dcache.ReadReq_miss_latency::total 2429598500 # number of ReadReq miss cycles 1620system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3913148500 # number of WriteReq miss cycles 1621system.cpu1.dcache.WriteReq_miss_latency::total 3913148500 # number of WriteReq miss cycles 1622system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317482500 # number of LoadLockedReq miss cycles 1623system.cpu1.dcache.LoadLockedReq_miss_latency::total 317482500 # number of LoadLockedReq miss cycles 1624system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 583924500 # number of StoreCondReq miss cycles 1625system.cpu1.dcache.StoreCondReq_miss_latency::total 583924500 # number of StoreCondReq miss cycles 1626system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 387500 # number of StoreCondFailReq miss cycles 1627system.cpu1.dcache.StoreCondFailReq_miss_latency::total 387500 # number of StoreCondFailReq miss cycles 1628system.cpu1.dcache.demand_miss_latency::cpu1.data 6342747000 # number of demand (read+write) miss cycles 1629system.cpu1.dcache.demand_miss_latency::total 6342747000 # number of demand (read+write) miss cycles 1630system.cpu1.dcache.overall_miss_latency::cpu1.data 6342747000 # number of overall miss cycles 1631system.cpu1.dcache.overall_miss_latency::total 6342747000 # number of overall miss cycles 1632system.cpu1.dcache.ReadReq_accesses::cpu1.data 10954798 # number of ReadReq accesses(hits+misses) 1633system.cpu1.dcache.ReadReq_accesses::total 10954798 # number of ReadReq accesses(hits+misses) 1634system.cpu1.dcache.WriteReq_accesses::cpu1.data 6850290 # number of WriteReq accesses(hits+misses) 1635system.cpu1.dcache.WriteReq_accesses::total 6850290 # number of WriteReq accesses(hits+misses) 1636system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81354 # number of SoftPFReq accesses(hits+misses) 1637system.cpu1.dcache.SoftPFReq_accesses::total 81354 # number of SoftPFReq accesses(hits+misses) 1638system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97131 # number of LoadLockedReq accesses(hits+misses) 1639system.cpu1.dcache.LoadLockedReq_accesses::total 97131 # number of LoadLockedReq accesses(hits+misses) 1640system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95328 # number of StoreCondReq accesses(hits+misses) 1641system.cpu1.dcache.StoreCondReq_accesses::total 95328 # number of StoreCondReq accesses(hits+misses) 1642system.cpu1.dcache.demand_accesses::cpu1.data 17805088 # number of demand (read+write) accesses 1643system.cpu1.dcache.demand_accesses::total 17805088 # number of demand (read+write) accesses 1644system.cpu1.dcache.overall_accesses::cpu1.data 17886442 # number of overall (read+write) accesses 1645system.cpu1.dcache.overall_accesses::total 17886442 # number of overall (read+write) accesses 1646system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014580 # miss rate for ReadReq accesses 1647system.cpu1.dcache.ReadReq_miss_rate::total 0.014580 # miss rate for ReadReq accesses 1648system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021246 # miss rate for WriteReq accesses 1649system.cpu1.dcache.WriteReq_miss_rate::total 0.021246 # miss rate for WriteReq accesses 1650system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381100 # miss rate for SoftPFReq accesses 1651system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381100 # miss rate for SoftPFReq accesses 1652system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174610 # miss rate for LoadLockedReq accesses 1653system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174610 # miss rate for LoadLockedReq accesses 1654system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249612 # miss rate for StoreCondReq accesses 1655system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249612 # miss rate for StoreCondReq accesses 1656system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017145 # miss rate for demand accesses 1657system.cpu1.dcache.demand_miss_rate::total 0.017145 # miss rate for demand accesses 1658system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018800 # miss rate for overall accesses 1659system.cpu1.dcache.overall_miss_rate::total 0.018800 # miss rate for overall accesses 1660system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15211.420468 # average ReadReq miss latency 1661system.cpu1.dcache.ReadReq_avg_miss_latency::total 15211.420468 # average ReadReq miss latency 1662system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26887.469252 # average WriteReq miss latency 1663system.cpu1.dcache.WriteReq_avg_miss_latency::total 26887.469252 # average WriteReq miss latency 1664system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18719.487028 # average LoadLockedReq miss latency 1665system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18719.487028 # average LoadLockedReq miss latency 1666system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24539.798277 # average StoreCondReq miss latency 1667system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24539.798277 # average StoreCondReq miss latency 1668system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1669system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1670system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20778.179257 # average overall miss latency 1671system.cpu1.dcache.demand_avg_miss_latency::total 20778.179257 # average overall miss latency 1672system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18862.402755 # average overall miss latency 1673system.cpu1.dcache.overall_avg_miss_latency::total 18862.402755 # average overall miss latency 1674system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1675system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1676system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1677system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1678system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1679system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1680system.cpu1.dcache.writebacks::writebacks 196286 # number of writebacks 1681system.cpu1.dcache.writebacks::total 196286 # number of writebacks 1682system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16292 # number of ReadReq MSHR hits 1683system.cpu1.dcache.ReadReq_mshr_hits::total 16292 # number of ReadReq MSHR hits 1684system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52982 # number of WriteReq MSHR hits 1685system.cpu1.dcache.WriteReq_mshr_hits::total 52982 # number of WriteReq MSHR hits 1686system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12069 # number of LoadLockedReq MSHR hits 1687system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12069 # number of LoadLockedReq MSHR hits 1688system.cpu1.dcache.demand_mshr_hits::cpu1.data 69274 # number of demand (read+write) MSHR hits 1689system.cpu1.dcache.demand_mshr_hits::total 69274 # number of demand (read+write) MSHR hits 1690system.cpu1.dcache.overall_mshr_hits::cpu1.data 69274 # number of overall MSHR hits 1691system.cpu1.dcache.overall_mshr_hits::total 69274 # number of overall MSHR hits 1692system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143430 # number of ReadReq MSHR misses 1693system.cpu1.dcache.ReadReq_mshr_misses::total 143430 # number of ReadReq MSHR misses 1694system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92556 # number of WriteReq MSHR misses 1695system.cpu1.dcache.WriteReq_mshr_misses::total 92556 # number of WriteReq MSHR misses 1696system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30096 # number of SoftPFReq MSHR misses 1697system.cpu1.dcache.SoftPFReq_mshr_misses::total 30096 # number of SoftPFReq MSHR misses 1698system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses 1699system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses 1700system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23795 # number of StoreCondReq MSHR misses 1701system.cpu1.dcache.StoreCondReq_mshr_misses::total 23795 # number of StoreCondReq MSHR misses 1702system.cpu1.dcache.demand_mshr_misses::cpu1.data 235986 # number of demand (read+write) MSHR misses 1703system.cpu1.dcache.demand_mshr_misses::total 235986 # number of demand (read+write) MSHR misses 1704system.cpu1.dcache.overall_mshr_misses::cpu1.data 266082 # number of overall MSHR misses 1705system.cpu1.dcache.overall_mshr_misses::total 266082 # number of overall MSHR misses 1706system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable 1707system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable 1708system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11758 # number of WriteReq MSHR uncacheable 1709system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11758 # number of WriteReq MSHR uncacheable 1710system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26182 # number of overall MSHR uncacheable misses 1711system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26182 # number of overall MSHR uncacheable misses 1712system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2041290000 # number of ReadReq MSHR miss cycles 1713system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2041290000 # number of ReadReq MSHR miss cycles 1714system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2380409500 # number of WriteReq MSHR miss cycles 1715system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2380409500 # number of WriteReq MSHR miss cycles 1716system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 535271500 # number of SoftPFReq MSHR miss cycles 1717system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 535271500 # number of SoftPFReq MSHR miss cycles 1718system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82814000 # number of LoadLockedReq MSHR miss cycles 1719system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82814000 # number of LoadLockedReq MSHR miss cycles 1720system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 560137500 # number of StoreCondReq MSHR miss cycles 1721system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 560137500 # number of StoreCondReq MSHR miss cycles 1722system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 379500 # number of StoreCondFailReq MSHR miss cycles 1723system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 379500 # number of StoreCondFailReq MSHR miss cycles 1724system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4421699500 # number of demand (read+write) MSHR miss cycles 1725system.cpu1.dcache.demand_mshr_miss_latency::total 4421699500 # number of demand (read+write) MSHR miss cycles 1726system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4956971000 # number of overall MSHR miss cycles 1727system.cpu1.dcache.overall_mshr_miss_latency::total 4956971000 # number of overall MSHR miss cycles 1728system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2479783500 # number of ReadReq MSHR uncacheable cycles 1729system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2479783500 # number of ReadReq MSHR uncacheable cycles 1730system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2479783500 # number of overall MSHR uncacheable cycles 1731system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2479783500 # number of overall MSHR uncacheable cycles 1732system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013093 # mshr miss rate for ReadReq accesses 1733system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013093 # mshr miss rate for ReadReq accesses 1734system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013511 # mshr miss rate for WriteReq accesses 1735system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013511 # mshr miss rate for WriteReq accesses 1736system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369939 # mshr miss rate for SoftPFReq accesses 1737system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369939 # mshr miss rate for SoftPFReq accesses 1738system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050355 # mshr miss rate for LoadLockedReq accesses 1739system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050355 # mshr miss rate for LoadLockedReq accesses 1740system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249612 # mshr miss rate for StoreCondReq accesses 1741system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249612 # mshr miss rate for StoreCondReq accesses 1742system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013254 # mshr miss rate for demand accesses 1743system.cpu1.dcache.demand_mshr_miss_rate::total 0.013254 # mshr miss rate for demand accesses 1744system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014876 # mshr miss rate for overall accesses 1745system.cpu1.dcache.overall_mshr_miss_rate::total 0.014876 # mshr miss rate for overall accesses 1746system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14231.959841 # average ReadReq mshr miss latency 1747system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14231.959841 # average ReadReq mshr miss latency 1748system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25718.586585 # average WriteReq mshr miss latency 1749system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25718.586585 # average WriteReq mshr miss latency 1750system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17785.469830 # average SoftPFReq mshr miss latency 1751system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17785.469830 # average SoftPFReq mshr miss latency 1752system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16931.915764 # average LoadLockedReq mshr miss latency 1753system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16931.915764 # average LoadLockedReq mshr miss latency 1754system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23540.134482 # average StoreCondReq mshr miss latency 1755system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23540.134482 # average StoreCondReq mshr miss latency 1756system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1757system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1758system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18737.126355 # average overall mshr miss latency 1759system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18737.126355 # average overall mshr miss latency 1760system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18629.486399 # average overall mshr miss latency 1761system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18629.486399 # average overall mshr miss latency 1762system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078 # average ReadReq mshr uncacheable latency 1763system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency 1764system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency 1765system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency 1766system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1767system.cpu1.icache.tags.replacements 946364 # number of replacements 1768system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use 1769system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks. 1770system.cpu1.icache.tags.sampled_refs 946876 # Sample count of references to valid blocks. 1771system.cpu1.icache.tags.avg_refs 40.822690 # Average number of references to valid blocks. 1772system.cpu1.icache.tags.warmup_cycle 72815756000 # Cycle when the warmup percentage was hit. 1773system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.210861 # Average occupied blocks per requestor 1774system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975021 # Average percentage of cache occupancy 1775system.cpu1.icache.tags.occ_percent::total 0.975021 # Average percentage of cache occupancy 1776system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1777system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id 1778system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id 1779system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1780system.cpu1.icache.tags.tag_accesses 80148678 # Number of tag accesses 1781system.cpu1.icache.tags.data_accesses 80148678 # Number of data accesses 1782system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1783system.cpu1.icache.ReadReq_hits::cpu1.inst 38654025 # number of ReadReq hits 1784system.cpu1.icache.ReadReq_hits::total 38654025 # number of ReadReq hits 1785system.cpu1.icache.demand_hits::cpu1.inst 38654025 # number of demand (read+write) hits 1786system.cpu1.icache.demand_hits::total 38654025 # number of demand (read+write) hits 1787system.cpu1.icache.overall_hits::cpu1.inst 38654025 # number of overall hits 1788system.cpu1.icache.overall_hits::total 38654025 # number of overall hits 1789system.cpu1.icache.ReadReq_misses::cpu1.inst 946876 # number of ReadReq misses 1790system.cpu1.icache.ReadReq_misses::total 946876 # number of ReadReq misses 1791system.cpu1.icache.demand_misses::cpu1.inst 946876 # number of demand (read+write) misses 1792system.cpu1.icache.demand_misses::total 946876 # number of demand (read+write) misses 1793system.cpu1.icache.overall_misses::cpu1.inst 946876 # number of overall misses 1794system.cpu1.icache.overall_misses::total 946876 # number of overall misses 1795system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8324695000 # number of ReadReq miss cycles 1796system.cpu1.icache.ReadReq_miss_latency::total 8324695000 # number of ReadReq miss cycles 1797system.cpu1.icache.demand_miss_latency::cpu1.inst 8324695000 # number of demand (read+write) miss cycles 1798system.cpu1.icache.demand_miss_latency::total 8324695000 # number of demand (read+write) miss cycles 1799system.cpu1.icache.overall_miss_latency::cpu1.inst 8324695000 # number of overall miss cycles 1800system.cpu1.icache.overall_miss_latency::total 8324695000 # number of overall miss cycles 1801system.cpu1.icache.ReadReq_accesses::cpu1.inst 39600901 # number of ReadReq accesses(hits+misses) 1802system.cpu1.icache.ReadReq_accesses::total 39600901 # number of ReadReq accesses(hits+misses) 1803system.cpu1.icache.demand_accesses::cpu1.inst 39600901 # number of demand (read+write) accesses 1804system.cpu1.icache.demand_accesses::total 39600901 # number of demand (read+write) accesses 1805system.cpu1.icache.overall_accesses::cpu1.inst 39600901 # number of overall (read+write) accesses 1806system.cpu1.icache.overall_accesses::total 39600901 # number of overall (read+write) accesses 1807system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023910 # miss rate for ReadReq accesses 1808system.cpu1.icache.ReadReq_miss_rate::total 0.023910 # miss rate for ReadReq accesses 1809system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023910 # miss rate for demand accesses 1810system.cpu1.icache.demand_miss_rate::total 0.023910 # miss rate for demand accesses 1811system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023910 # miss rate for overall accesses 1812system.cpu1.icache.overall_miss_rate::total 0.023910 # miss rate for overall accesses 1813system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8791.747811 # average ReadReq miss latency 1814system.cpu1.icache.ReadReq_avg_miss_latency::total 8791.747811 # average ReadReq miss latency 1815system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency 1816system.cpu1.icache.demand_avg_miss_latency::total 8791.747811 # average overall miss latency 1817system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency 1818system.cpu1.icache.overall_avg_miss_latency::total 8791.747811 # average overall miss latency 1819system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1820system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1821system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1822system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1823system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1824system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1825system.cpu1.icache.writebacks::writebacks 946364 # number of writebacks 1826system.cpu1.icache.writebacks::total 946364 # number of writebacks 1827system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 946876 # number of ReadReq MSHR misses 1828system.cpu1.icache.ReadReq_mshr_misses::total 946876 # number of ReadReq MSHR misses 1829system.cpu1.icache.demand_mshr_misses::cpu1.inst 946876 # number of demand (read+write) MSHR misses 1830system.cpu1.icache.demand_mshr_misses::total 946876 # number of demand (read+write) MSHR misses 1831system.cpu1.icache.overall_mshr_misses::cpu1.inst 946876 # number of overall MSHR misses 1832system.cpu1.icache.overall_mshr_misses::total 946876 # number of overall MSHR misses 1833system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1834system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1835system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1836system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses 1837system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7851257000 # number of ReadReq MSHR miss cycles 1838system.cpu1.icache.ReadReq_mshr_miss_latency::total 7851257000 # number of ReadReq MSHR miss cycles 1839system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7851257000 # number of demand (read+write) MSHR miss cycles 1840system.cpu1.icache.demand_mshr_miss_latency::total 7851257000 # number of demand (read+write) MSHR miss cycles 1841system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7851257000 # number of overall MSHR miss cycles 1842system.cpu1.icache.overall_mshr_miss_latency::total 7851257000 # number of overall MSHR miss cycles 1843system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10474500 # number of ReadReq MSHR uncacheable cycles 1844system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10474500 # number of ReadReq MSHR uncacheable cycles 1845system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10474500 # number of overall MSHR uncacheable cycles 1846system.cpu1.icache.overall_mshr_uncacheable_latency::total 10474500 # number of overall MSHR uncacheable cycles 1847system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for ReadReq accesses 1848system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023910 # mshr miss rate for ReadReq accesses 1849system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for demand accesses 1850system.cpu1.icache.demand_mshr_miss_rate::total 0.023910 # mshr miss rate for demand accesses 1851system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for overall accesses 1852system.cpu1.icache.overall_mshr_miss_rate::total 0.023910 # mshr miss rate for overall accesses 1853system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average ReadReq mshr miss latency 1854system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8291.747811 # average ReadReq mshr miss latency 1855system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency 1856system.cpu1.icache.demand_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency 1857system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency 1858system.cpu1.icache.overall_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency 1859system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average ReadReq mshr uncacheable latency 1860system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency 1861system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency 1862system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency 1863system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1864system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued 1865system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified 1866system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue 1867system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1868system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1869system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing 1870system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1871system.cpu1.l2cache.tags.replacements 53638 # number of replacements 1872system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use 1873system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks. 1874system.cpu1.l2cache.tags.sampled_refs 68366 # Sample count of references to valid blocks. 1875system.cpu1.l2cache.tags.avg_refs 30.105579 # Average number of references to valid blocks. 1876system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1877system.cpu1.l2cache.tags.occ_blocks::writebacks 14816.571197 # Average occupied blocks per requestor 1878system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 39.116539 # Average occupied blocks per requestor 1879system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.045474 # Average occupied blocks per requestor 1880system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 428.691662 # Average occupied blocks per requestor 1881system.cpu1.l2cache.tags.occ_percent::writebacks 0.904332 # Average percentage of cache occupancy 1882system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002387 # Average percentage of cache occupancy 1883system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy 1884system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026165 # Average percentage of cache occupancy 1885system.cpu1.l2cache.tags.occ_percent::total 0.933009 # Average percentage of cache occupancy 1886system.cpu1.l2cache.tags.occ_task_id_blocks::1022 907 # Occupied blocks per task id 1887system.cpu1.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id 1888system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13776 # Occupied blocks per task id 1889system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id 1890system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 323 # Occupied blocks per task id 1891system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 581 # Occupied blocks per task id 1892system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id 1893system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5681 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7813 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.055359 # Percentage of cache occupancy per task id 1899system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id 1900system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id 1901system.cpu1.l2cache.tags.tag_accesses 38543839 # Number of tag accesses 1902system.cpu1.l2cache.tags.data_accesses 38543839 # Number of data accesses 1903system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1904system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30076 # number of ReadReq hits 1905system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3135 # number of ReadReq hits 1906system.cpu1.l2cache.ReadReq_hits::total 33211 # number of ReadReq hits 1907system.cpu1.l2cache.WritebackDirty_hits::writebacks 117792 # number of WritebackDirty hits 1908system.cpu1.l2cache.WritebackDirty_hits::total 117792 # number of WritebackDirty hits 1909system.cpu1.l2cache.WritebackClean_hits::writebacks 1004693 # number of WritebackClean hits 1910system.cpu1.l2cache.WritebackClean_hits::total 1004693 # number of WritebackClean hits 1911system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28032 # number of ReadExReq hits 1912system.cpu1.l2cache.ReadExReq_hits::total 28032 # number of ReadExReq hits 1913system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 926813 # number of ReadCleanReq hits 1914system.cpu1.l2cache.ReadCleanReq_hits::total 926813 # number of ReadCleanReq hits 1915system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 106584 # number of ReadSharedReq hits 1916system.cpu1.l2cache.ReadSharedReq_hits::total 106584 # number of ReadSharedReq hits 1917system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 30076 # number of demand (read+write) hits 1918system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3135 # number of demand (read+write) hits 1919system.cpu1.l2cache.demand_hits::cpu1.inst 926813 # number of demand (read+write) hits 1920system.cpu1.l2cache.demand_hits::cpu1.data 134616 # number of demand (read+write) hits 1921system.cpu1.l2cache.demand_hits::total 1094640 # number of demand (read+write) hits 1922system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 30076 # number of overall hits 1923system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3135 # number of overall hits 1924system.cpu1.l2cache.overall_hits::cpu1.inst 926813 # number of overall hits 1925system.cpu1.l2cache.overall_hits::cpu1.data 134616 # number of overall hits 1926system.cpu1.l2cache.overall_hits::total 1094640 # number of overall hits 1927system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 622 # number of ReadReq misses 1928system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 230 # number of ReadReq misses 1929system.cpu1.l2cache.ReadReq_misses::total 852 # number of ReadReq misses 1930system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 30029 # number of UpgradeReq misses 1931system.cpu1.l2cache.UpgradeReq_misses::total 30029 # number of UpgradeReq misses 1932system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23795 # number of SCUpgradeReq misses 1933system.cpu1.l2cache.SCUpgradeReq_misses::total 23795 # number of SCUpgradeReq misses 1934system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34495 # number of ReadExReq misses 1935system.cpu1.l2cache.ReadExReq_misses::total 34495 # number of ReadExReq misses 1936system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 20063 # number of ReadCleanReq misses 1937system.cpu1.l2cache.ReadCleanReq_misses::total 20063 # number of ReadCleanReq misses 1938system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71833 # number of ReadSharedReq misses 1939system.cpu1.l2cache.ReadSharedReq_misses::total 71833 # number of ReadSharedReq misses 1940system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 622 # number of demand (read+write) misses 1941system.cpu1.l2cache.demand_misses::cpu1.itb.walker 230 # number of demand (read+write) misses 1942system.cpu1.l2cache.demand_misses::cpu1.inst 20063 # number of demand (read+write) misses 1943system.cpu1.l2cache.demand_misses::cpu1.data 106328 # number of demand (read+write) misses 1944system.cpu1.l2cache.demand_misses::total 127243 # number of demand (read+write) misses 1945system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 622 # number of overall misses 1946system.cpu1.l2cache.overall_misses::cpu1.itb.walker 230 # number of overall misses 1947system.cpu1.l2cache.overall_misses::cpu1.inst 20063 # number of overall misses 1948system.cpu1.l2cache.overall_misses::cpu1.data 106328 # number of overall misses 1949system.cpu1.l2cache.overall_misses::total 127243 # number of overall misses 1950system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14337000 # number of ReadReq miss cycles 1951system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4653500 # number of ReadReq miss cycles 1952system.cpu1.l2cache.ReadReq_miss_latency::total 18990500 # number of ReadReq miss cycles 1953system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 67215000 # number of UpgradeReq miss cycles 1954system.cpu1.l2cache.UpgradeReq_miss_latency::total 67215000 # number of UpgradeReq miss cycles 1955system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 37021000 # number of SCUpgradeReq miss cycles 1956system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 37021000 # number of SCUpgradeReq miss cycles 1957system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 366000 # number of SCUpgradeFailReq miss cycles 1958system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 366000 # number of SCUpgradeFailReq miss cycles 1959system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1366050498 # number of ReadExReq miss cycles 1960system.cpu1.l2cache.ReadExReq_miss_latency::total 1366050498 # number of ReadExReq miss cycles 1961system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 796902000 # number of ReadCleanReq miss cycles 1962system.cpu1.l2cache.ReadCleanReq_miss_latency::total 796902000 # number of ReadCleanReq miss cycles 1963system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1679934496 # number of ReadSharedReq miss cycles 1964system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1679934496 # number of ReadSharedReq miss cycles 1965system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14337000 # number of demand (read+write) miss cycles 1966system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4653500 # number of demand (read+write) miss cycles 1967system.cpu1.l2cache.demand_miss_latency::cpu1.inst 796902000 # number of demand (read+write) miss cycles 1968system.cpu1.l2cache.demand_miss_latency::cpu1.data 3045984994 # number of demand (read+write) miss cycles 1969system.cpu1.l2cache.demand_miss_latency::total 3861877494 # number of demand (read+write) miss cycles 1970system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14337000 # number of overall miss cycles 1971system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4653500 # number of overall miss cycles 1972system.cpu1.l2cache.overall_miss_latency::cpu1.inst 796902000 # number of overall miss cycles 1973system.cpu1.l2cache.overall_miss_latency::cpu1.data 3045984994 # number of overall miss cycles 1974system.cpu1.l2cache.overall_miss_latency::total 3861877494 # number of overall miss cycles 1975system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 30698 # number of ReadReq accesses(hits+misses) 1976system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3365 # number of ReadReq accesses(hits+misses) 1977system.cpu1.l2cache.ReadReq_accesses::total 34063 # number of ReadReq accesses(hits+misses) 1978system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117792 # number of WritebackDirty accesses(hits+misses) 1979system.cpu1.l2cache.WritebackDirty_accesses::total 117792 # number of WritebackDirty accesses(hits+misses) 1980system.cpu1.l2cache.WritebackClean_accesses::writebacks 1004693 # number of WritebackClean accesses(hits+misses) 1981system.cpu1.l2cache.WritebackClean_accesses::total 1004693 # number of WritebackClean accesses(hits+misses) 1982system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30029 # number of UpgradeReq accesses(hits+misses) 1983system.cpu1.l2cache.UpgradeReq_accesses::total 30029 # number of UpgradeReq accesses(hits+misses) 1984system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23795 # number of SCUpgradeReq accesses(hits+misses) 1985system.cpu1.l2cache.SCUpgradeReq_accesses::total 23795 # number of SCUpgradeReq accesses(hits+misses) 1986system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62527 # number of ReadExReq accesses(hits+misses) 1987system.cpu1.l2cache.ReadExReq_accesses::total 62527 # number of ReadExReq accesses(hits+misses) 1988system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 946876 # number of ReadCleanReq accesses(hits+misses) 1989system.cpu1.l2cache.ReadCleanReq_accesses::total 946876 # number of ReadCleanReq accesses(hits+misses) 1990system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 178417 # number of ReadSharedReq accesses(hits+misses) 1991system.cpu1.l2cache.ReadSharedReq_accesses::total 178417 # number of ReadSharedReq accesses(hits+misses) 1992system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 30698 # number of demand (read+write) accesses 1993system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3365 # number of demand (read+write) accesses 1994system.cpu1.l2cache.demand_accesses::cpu1.inst 946876 # number of demand (read+write) accesses 1995system.cpu1.l2cache.demand_accesses::cpu1.data 240944 # number of demand (read+write) accesses 1996system.cpu1.l2cache.demand_accesses::total 1221883 # number of demand (read+write) accesses 1997system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 30698 # number of overall (read+write) accesses 1998system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3365 # number of overall (read+write) accesses 1999system.cpu1.l2cache.overall_accesses::cpu1.inst 946876 # number of overall (read+write) accesses 2000system.cpu1.l2cache.overall_accesses::cpu1.data 240944 # number of overall (read+write) accesses 2001system.cpu1.l2cache.overall_accesses::total 1221883 # number of overall (read+write) accesses 2002system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020262 # miss rate for ReadReq accesses 2003system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068351 # miss rate for ReadReq accesses 2004system.cpu1.l2cache.ReadReq_miss_rate::total 0.025012 # miss rate for ReadReq accesses 2005system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2006system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2007system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2008system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2009system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.551682 # miss rate for ReadExReq accesses 2010system.cpu1.l2cache.ReadExReq_miss_rate::total 0.551682 # miss rate for ReadExReq accesses 2011system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.021189 # miss rate for ReadCleanReq accesses 2012system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.021189 # miss rate for ReadCleanReq accesses 2013system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.402613 # miss rate for ReadSharedReq accesses 2014system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.402613 # miss rate for ReadSharedReq accesses 2015system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020262 # miss rate for demand accesses 2016system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.068351 # miss rate for demand accesses 2017system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.021189 # miss rate for demand accesses 2018system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.441298 # miss rate for demand accesses 2019system.cpu1.l2cache.demand_miss_rate::total 0.104137 # miss rate for demand accesses 2020system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020262 # miss rate for overall accesses 2021system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.068351 # miss rate for overall accesses 2022system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.021189 # miss rate for overall accesses 2023system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.441298 # miss rate for overall accesses 2024system.cpu1.l2cache.overall_miss_rate::total 0.104137 # miss rate for overall accesses 2025system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23049.839228 # average ReadReq miss latency 2026system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20232.608696 # average ReadReq miss latency 2027system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22289.319249 # average ReadReq miss latency 2028system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2238.336275 # average UpgradeReq miss latency 2029system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2238.336275 # average UpgradeReq miss latency 2030system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1555.831057 # average SCUpgradeReq miss latency 2031system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1555.831057 # average SCUpgradeReq miss latency 2032system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 2033system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 2034system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39601.405943 # average ReadExReq miss latency 2035system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39601.405943 # average ReadExReq miss latency 2036system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39719.982057 # average ReadCleanReq miss latency 2037system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39719.982057 # average ReadCleanReq miss latency 2038system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23386.667632 # average ReadSharedReq miss latency 2039system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23386.667632 # average ReadSharedReq miss latency 2040system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23049.839228 # average overall miss latency 2041system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20232.608696 # average overall miss latency 2042system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39719.982057 # average overall miss latency 2043system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28647.063746 # average overall miss latency 2044system.cpu1.l2cache.demand_avg_miss_latency::total 30350.412156 # average overall miss latency 2045system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23049.839228 # average overall miss latency 2046system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20232.608696 # average overall miss latency 2047system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39719.982057 # average overall miss latency 2048system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28647.063746 # average overall miss latency 2049system.cpu1.l2cache.overall_avg_miss_latency::total 30350.412156 # average overall miss latency 2050system.cpu1.l2cache.blocked_cycles::no_mshrs 149 # number of cycles access was blocked 2051system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2052system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 2053system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2054system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 37.250000 # average number of cycles each access was blocked 2055system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2056system.cpu1.l2cache.unused_prefetches 841 # number of HardPF blocks evicted w/o reference 2057system.cpu1.l2cache.writebacks::writebacks 35327 # number of writebacks 2058system.cpu1.l2cache.writebacks::total 35327 # number of writebacks 2059system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 230 # number of ReadExReq MSHR hits 2060system.cpu1.l2cache.ReadExReq_mshr_hits::total 230 # number of ReadExReq MSHR hits 2061system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 22 # number of ReadCleanReq MSHR hits 2062system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 22 # number of ReadCleanReq MSHR hits 2063system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 84 # number of ReadSharedReq MSHR hits 2064system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 84 # number of ReadSharedReq MSHR hits 2065system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits 2066system.cpu1.l2cache.demand_mshr_hits::cpu1.data 314 # number of demand (read+write) MSHR hits 2067system.cpu1.l2cache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits 2068system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits 2069system.cpu1.l2cache.overall_mshr_hits::cpu1.data 314 # number of overall MSHR hits 2070system.cpu1.l2cache.overall_mshr_hits::total 336 # number of overall MSHR hits 2071system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 622 # number of ReadReq MSHR misses 2072system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 230 # number of ReadReq MSHR misses 2073system.cpu1.l2cache.ReadReq_mshr_misses::total 852 # number of ReadReq MSHR misses 2074system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26036 # number of HardPFReq MSHR misses 2075system.cpu1.l2cache.HardPFReq_mshr_misses::total 26036 # number of HardPFReq MSHR misses 2076system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 30029 # number of UpgradeReq MSHR misses 2077system.cpu1.l2cache.UpgradeReq_mshr_misses::total 30029 # number of UpgradeReq MSHR misses 2078system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23795 # number of SCUpgradeReq MSHR misses 2079system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23795 # number of SCUpgradeReq MSHR misses 2080system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34265 # number of ReadExReq MSHR misses 2081system.cpu1.l2cache.ReadExReq_mshr_misses::total 34265 # number of ReadExReq MSHR misses 2082system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 20041 # number of ReadCleanReq MSHR misses 2083system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 20041 # number of ReadCleanReq MSHR misses 2084system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71749 # number of ReadSharedReq MSHR misses 2085system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71749 # number of ReadSharedReq MSHR misses 2086system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 622 # number of demand (read+write) MSHR misses 2087system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 230 # number of demand (read+write) MSHR misses 2088system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20041 # number of demand (read+write) MSHR misses 2089system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106014 # number of demand (read+write) MSHR misses 2090system.cpu1.l2cache.demand_mshr_misses::total 126907 # number of demand (read+write) MSHR misses 2091system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 622 # number of overall MSHR misses 2092system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 230 # number of overall MSHR misses 2093system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20041 # number of overall MSHR misses 2094system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106014 # number of overall MSHR misses 2095system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26036 # number of overall MSHR misses 2096system.cpu1.l2cache.overall_mshr_misses::total 152943 # number of overall MSHR misses 2097system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2098system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable 2099system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14536 # number of ReadReq MSHR uncacheable 2100system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11758 # number of WriteReq MSHR uncacheable 2101system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11758 # number of WriteReq MSHR uncacheable 2102system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2103system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26182 # number of overall MSHR uncacheable misses 2104system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26294 # number of overall MSHR uncacheable misses 2105system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of ReadReq MSHR miss cycles 2106system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3273500 # number of ReadReq MSHR miss cycles 2107system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 13878500 # number of ReadReq MSHR miss cycles 2108system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1006636893 # number of HardPFReq MSHR miss cycles 2109system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1006636893 # number of HardPFReq MSHR miss cycles 2110system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 505691500 # number of UpgradeReq MSHR miss cycles 2111system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 505691500 # number of UpgradeReq MSHR miss cycles 2112system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 380458500 # number of SCUpgradeReq MSHR miss cycles 2113system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 380458500 # number of SCUpgradeReq MSHR miss cycles 2114system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 318000 # number of SCUpgradeFailReq MSHR miss cycles 2115system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 318000 # number of SCUpgradeFailReq MSHR miss cycles 2116system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1135025000 # number of ReadExReq MSHR miss cycles 2117system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1135025000 # number of ReadExReq MSHR miss cycles 2118system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 675844000 # number of ReadCleanReq MSHR miss cycles 2119system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 675844000 # number of ReadCleanReq MSHR miss cycles 2120system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1246810496 # number of ReadSharedReq MSHR miss cycles 2121system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1246810496 # number of ReadSharedReq MSHR miss cycles 2122system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of demand (read+write) MSHR miss cycles 2123system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3273500 # number of demand (read+write) MSHR miss cycles 2124system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 675844000 # number of demand (read+write) MSHR miss cycles 2125system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2381835496 # number of demand (read+write) MSHR miss cycles 2126system.cpu1.l2cache.demand_mshr_miss_latency::total 3071557996 # number of demand (read+write) MSHR miss cycles 2127system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of overall MSHR miss cycles 2128system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3273500 # number of overall MSHR miss cycles 2129system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 675844000 # number of overall MSHR miss cycles 2130system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2381835496 # number of overall MSHR miss cycles 2131system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1006636893 # number of overall MSHR miss cycles 2132system.cpu1.l2cache.overall_mshr_miss_latency::total 4078194889 # number of overall MSHR miss cycles 2133system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9578500 # number of ReadReq MSHR uncacheable cycles 2134system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2364337500 # number of ReadReq MSHR uncacheable cycles 2135system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2373916000 # number of ReadReq MSHR uncacheable cycles 2136system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9578500 # number of overall MSHR uncacheable cycles 2137system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2364337500 # number of overall MSHR uncacheable cycles 2138system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2373916000 # number of overall MSHR uncacheable cycles 2139system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for ReadReq accesses 2140system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for ReadReq accesses 2141system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025012 # mshr miss rate for ReadReq accesses 2142system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2143system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2144system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2145system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2146system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2147system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2148system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548003 # mshr miss rate for ReadExReq accesses 2149system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548003 # mshr miss rate for ReadExReq accesses 2150system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for ReadCleanReq accesses 2151system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.021165 # mshr miss rate for ReadCleanReq accesses 2152system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402142 # mshr miss rate for ReadSharedReq accesses 2153system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402142 # mshr miss rate for ReadSharedReq accesses 2154system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for demand accesses 2155system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for demand accesses 2156system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for demand accesses 2157system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for demand accesses 2158system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103862 # mshr miss rate for demand accesses 2159system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for overall accesses 2160system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for overall accesses 2161system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for overall accesses 2162system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for overall accesses 2163system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2164system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125170 # mshr miss rate for overall accesses 2165system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average ReadReq mshr miss latency 2166system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average ReadReq mshr miss latency 2167system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16289.319249 # average ReadReq mshr miss latency 2168system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average HardPFReq mshr miss latency 2169system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38663.269819 # average HardPFReq mshr miss latency 2170system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16840.104566 # average UpgradeReq mshr miss latency 2171system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16840.104566 # average UpgradeReq mshr miss latency 2172system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15989.010296 # average SCUpgradeReq mshr miss latency 2173system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15989.010296 # average SCUpgradeReq mshr miss latency 2174system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2175system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2176system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33124.908799 # average ReadExReq mshr miss latency 2177system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33124.908799 # average ReadExReq mshr miss latency 2178system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average ReadCleanReq mshr miss latency 2179system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33723.067711 # average ReadCleanReq mshr miss latency 2180system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17377.391964 # average ReadSharedReq mshr miss latency 2181system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17377.391964 # average ReadSharedReq mshr miss latency 2182system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency 2183system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency 2184system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency 2185system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency 2186system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24203.219649 # average overall mshr miss latency 2187system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency 2188system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency 2189system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency 2190system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency 2191system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average overall mshr miss latency 2192system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26664.802502 # average overall mshr miss latency 2193system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average ReadReq mshr uncacheable latency 2194system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163916.909318 # average ReadReq mshr uncacheable latency 2195system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163312.878371 # average ReadReq mshr uncacheable latency 2196system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average overall mshr uncacheable latency 2197system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90303.930181 # average overall mshr uncacheable latency 2198system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90283.562790 # average overall mshr uncacheable latency 2199system.cpu1.toL2Bus.snoop_filter.tot_requests 2394243 # Total number of requests made to the snoop filter. 2200system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1206431 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2201system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20164 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2202system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter. 2203system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2204system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2205system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2206system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution 2207system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution 2208system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution 2209system.cpu1.toL2Bus.trans_dist::WriteResp 11758 # Transaction distribution 2210system.cpu1.toL2Bus.trans_dist::WritebackDirty 154274 # Transaction distribution 2211system.cpu1.toL2Bus.trans_dist::WritebackClean 1024857 # Transaction distribution 2212system.cpu1.toL2Bus.trans_dist::CleanEvict 118852 # Transaction distribution 2213system.cpu1.toL2Bus.trans_dist::HardPFReq 31456 # Transaction distribution 2214system.cpu1.toL2Bus.trans_dist::UpgradeReq 74303 # Transaction distribution 2215system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42261 # Transaction distribution 2216system.cpu1.toL2Bus.trans_dist::UpgradeResp 86315 # Transaction distribution 2217system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 2218system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution 2219system.cpu1.toL2Bus.trans_dist::ReadExReq 69975 # Transaction distribution 2220system.cpu1.toL2Bus.trans_dist::ReadExResp 67112 # Transaction distribution 2221system.cpu1.toL2Bus.trans_dist::ReadCleanReq 946876 # Transaction distribution 2222system.cpu1.toL2Bus.trans_dist::ReadSharedReq 270105 # Transaction distribution 2223system.cpu1.toL2Bus.trans_dist::InvalidateReq 65 # Transaction distribution 2224system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2840340 # Packet count per connected master and slave (bytes) 2225system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 913098 # Packet count per connected master and slave (bytes) 2226system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8024 # Packet count per connected master and slave (bytes) 2227system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64559 # Packet count per connected master and slave (bytes) 2228system.cpu1.toL2Bus.pkt_count::total 3826021 # Packet count per connected master and slave (bytes) 2229system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121174528 # Cumulative packet size per connected master and slave (bytes) 2230system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30799564 # Cumulative packet size per connected master and slave (bytes) 2231system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13460 # Cumulative packet size per connected master and slave (bytes) 2232system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122792 # Cumulative packet size per connected master and slave (bytes) 2233system.cpu1.toL2Bus.pkt_size::total 152110344 # Cumulative packet size per connected master and slave (bytes) 2234system.cpu1.toL2Bus.snoops 428107 # Total snoops (count) 2235system.cpu1.toL2Bus.snoop_fanout::samples 1655199 # Request fanout histogram 2236system.cpu1.toL2Bus.snoop_fanout::mean 0.135380 # Request fanout histogram 2237system.cpu1.toL2Bus.snoop_fanout::stdev 0.345288 # Request fanout histogram 2238system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2239system.cpu1.toL2Bus.snoop_fanout::0 1432915 86.57% 86.57% # Request fanout histogram 2240system.cpu1.toL2Bus.snoop_fanout::1 220487 13.32% 99.89% # Request fanout histogram 2241system.cpu1.toL2Bus.snoop_fanout::2 1797 0.11% 100.00% # Request fanout histogram 2242system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2243system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2244system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2245system.cpu1.toL2Bus.snoop_fanout::total 1655199 # Request fanout histogram 2246system.cpu1.toL2Bus.reqLayer0.occupancy 2373087991 # Layer occupancy (ticks) 2247system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2248system.cpu1.toL2Bus.snoopLayer0.occupancy 79906669 # Layer occupancy (ticks) 2249system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2250system.cpu1.toL2Bus.respLayer0.occupancy 1420645672 # Layer occupancy (ticks) 2251system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2252system.cpu1.toL2Bus.respLayer1.occupancy 410383006 # Layer occupancy (ticks) 2253system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2254system.cpu1.toL2Bus.respLayer2.occupancy 4659998 # Layer occupancy (ticks) 2255system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2256system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks) 2257system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2258system.iobus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2259system.iobus.trans_dist::ReadReq 31003 # Transaction distribution 2260system.iobus.trans_dist::ReadResp 31003 # Transaction distribution 2261system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2262system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2263system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2264system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2265system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2266system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2267system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2268system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2269system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2270system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2271system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2272system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2273system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2274system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2275system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2276system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2277system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2278system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2279system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2280system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2281system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2282system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2283system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 2284system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 2285system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) 2286system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2287system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2288system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2289system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2290system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2291system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2292system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2293system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2294system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2295system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2296system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2297system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2298system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2299system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2300system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2301system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2302system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2303system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2304system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2305system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2306system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 2307system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 2308system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) 2309system.iobus.reqLayer0.occupancy 48463001 # Layer occupancy (ticks) 2310system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2311system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) 2312system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2313system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) 2314system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2315system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) 2316system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2317system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) 2318system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2319system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) 2320system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2321system.iobus.reqLayer8.occupancy 574000 # Layer occupancy (ticks) 2322system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2323system.iobus.reqLayer10.occupancy 18000 # Layer occupancy (ticks) 2324system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2325system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) 2326system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2327system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2328system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2329system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 2330system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2331system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) 2332system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2333system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2334system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2335system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 2336system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2337system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2338system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2339system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) 2340system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2341system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2342system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2343system.iobus.reqLayer23.occupancy 6138000 # Layer occupancy (ticks) 2344system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2345system.iobus.reqLayer24.occupancy 33143500 # Layer occupancy (ticks) 2346system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2347system.iobus.reqLayer25.occupancy 187679851 # Layer occupancy (ticks) 2348system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2349system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2350system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2351system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) 2352system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2353system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2354system.iocache.tags.replacements 36449 # number of replacements 2355system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use 2356system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2357system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. 2358system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2359system.iocache.tags.warmup_cycle 271175186000 # Cycle when the warmup percentage was hit. 2360system.iocache.tags.occ_blocks::realview.ide 14.476064 # Average occupied blocks per requestor 2361system.iocache.tags.occ_percent::realview.ide 0.904754 # Average percentage of cache occupancy 2362system.iocache.tags.occ_percent::total 0.904754 # Average percentage of cache occupancy 2363system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2364system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2365system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2366system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2367system.iocache.tags.data_accesses 328203 # Number of data accesses 2368system.iocache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2369system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2370system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2371system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2372system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2373system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses 2374system.iocache.demand_misses::total 36467 # number of demand (read+write) misses 2375system.iocache.overall_misses::realview.ide 36467 # number of overall misses 2376system.iocache.overall_misses::total 36467 # number of overall misses 2377system.iocache.ReadReq_miss_latency::realview.ide 31712877 # number of ReadReq miss cycles 2378system.iocache.ReadReq_miss_latency::total 31712877 # number of ReadReq miss cycles 2379system.iocache.WriteLineReq_miss_latency::realview.ide 4301380974 # number of WriteLineReq miss cycles 2380system.iocache.WriteLineReq_miss_latency::total 4301380974 # number of WriteLineReq miss cycles 2381system.iocache.demand_miss_latency::realview.ide 4333093851 # number of demand (read+write) miss cycles 2382system.iocache.demand_miss_latency::total 4333093851 # number of demand (read+write) miss cycles 2383system.iocache.overall_miss_latency::realview.ide 4333093851 # number of overall miss cycles 2384system.iocache.overall_miss_latency::total 4333093851 # number of overall miss cycles 2385system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2386system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2387system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2388system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2389system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses 2390system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses 2391system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses 2392system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses 2393system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2394system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2395system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2396system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2397system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2398system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2399system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2400system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2401system.iocache.ReadReq_avg_miss_latency::realview.ide 130505.666667 # average ReadReq miss latency 2402system.iocache.ReadReq_avg_miss_latency::total 130505.666667 # average ReadReq miss latency 2403system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118743.953567 # average WriteLineReq miss latency 2404system.iocache.WriteLineReq_avg_miss_latency::total 118743.953567 # average WriteLineReq miss latency 2405system.iocache.demand_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency 2406system.iocache.demand_avg_miss_latency::total 118822.328434 # average overall miss latency 2407system.iocache.overall_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency 2408system.iocache.overall_avg_miss_latency::total 118822.328434 # average overall miss latency 2409system.iocache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked 2410system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2411system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked 2412system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2413system.iocache.avg_blocked_cycles::no_mshrs 16.888889 # average number of cycles each access was blocked 2414system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2415system.iocache.writebacks::writebacks 36206 # number of writebacks 2416system.iocache.writebacks::total 36206 # number of writebacks 2417system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2418system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2419system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2420system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2421system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses 2422system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses 2423system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses 2424system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses 2425system.iocache.ReadReq_mshr_miss_latency::realview.ide 19562877 # number of ReadReq MSHR miss cycles 2426system.iocache.ReadReq_mshr_miss_latency::total 19562877 # number of ReadReq MSHR miss cycles 2427system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2487893822 # number of WriteLineReq MSHR miss cycles 2428system.iocache.WriteLineReq_mshr_miss_latency::total 2487893822 # number of WriteLineReq MSHR miss cycles 2429system.iocache.demand_mshr_miss_latency::realview.ide 2507456699 # number of demand (read+write) MSHR miss cycles 2430system.iocache.demand_mshr_miss_latency::total 2507456699 # number of demand (read+write) MSHR miss cycles 2431system.iocache.overall_mshr_miss_latency::realview.ide 2507456699 # number of overall MSHR miss cycles 2432system.iocache.overall_mshr_miss_latency::total 2507456699 # number of overall MSHR miss cycles 2433system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2434system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2435system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2436system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2437system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2438system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2439system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2440system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2441system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80505.666667 # average ReadReq mshr miss latency 2442system.iocache.ReadReq_avg_mshr_miss_latency::total 80505.666667 # average ReadReq mshr miss latency 2443system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68680.814432 # average WriteLineReq mshr miss latency 2444system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68680.814432 # average WriteLineReq mshr miss latency 2445system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency 2446system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency 2447system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency 2448system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency 2449system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2450system.l2c.tags.replacements 131721 # number of replacements 2451system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use 2452system.l2c.tags.total_refs 480965 # Total number of references to valid blocks. 2453system.l2c.tags.sampled_refs 195649 # Sample count of references to valid blocks. 2454system.l2c.tags.avg_refs 2.458305 # Average number of references to valid blocks. 2455system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2456system.l2c.tags.occ_blocks::writebacks 13508.912510 # Average occupied blocks per requestor 2457system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.990696 # Average occupied blocks per requestor 2458system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038635 # Average occupied blocks per requestor 2459system.l2c.tags.occ_blocks::cpu0.inst 9208.691215 # Average occupied blocks per requestor 2460system.l2c.tags.occ_blocks::cpu0.data 2842.970469 # Average occupied blocks per requestor 2461system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33089.520800 # Average occupied blocks per requestor 2462system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.769626 # Average occupied blocks per requestor 2463system.l2c.tags.occ_blocks::cpu1.inst 2121.922145 # Average occupied blocks per requestor 2464system.l2c.tags.occ_blocks::cpu1.data 593.095570 # Average occupied blocks per requestor 2465system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1670.405219 # Average occupied blocks per requestor 2466system.l2c.tags.occ_percent::writebacks 0.206130 # Average percentage of cache occupancy 2467system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001144 # Average percentage of cache occupancy 2468system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2469system.l2c.tags.occ_percent::cpu0.inst 0.140513 # Average percentage of cache occupancy 2470system.l2c.tags.occ_percent::cpu0.data 0.043380 # Average percentage of cache occupancy 2471system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.504906 # Average percentage of cache occupancy 2472system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy 2473system.l2c.tags.occ_percent::cpu1.inst 0.032378 # Average percentage of cache occupancy 2474system.l2c.tags.occ_percent::cpu1.data 0.009050 # Average percentage of cache occupancy 2475system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025488 # Average percentage of cache occupancy 2476system.l2c.tags.occ_percent::total 0.963124 # Average percentage of cache occupancy 2477system.l2c.tags.occ_task_id_blocks::1022 27523 # Occupied blocks per task id 2478system.l2c.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id 2479system.l2c.tags.occ_task_id_blocks::1024 36326 # Occupied blocks per task id 2480system.l2c.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 2481system.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id 2482system.l2c.tags.age_task_id_blocks_1022::3 4354 # Occupied blocks per task id 2483system.l2c.tags.age_task_id_blocks_1022::4 23032 # Occupied blocks per task id 2484system.l2c.tags.age_task_id_blocks_1023::4 79 # Occupied blocks per task id 2485system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 2486system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 2487system.l2c.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id 2488system.l2c.tags.age_task_id_blocks_1024::3 3689 # Occupied blocks per task id 2489system.l2c.tags.age_task_id_blocks_1024::4 32199 # Occupied blocks per task id 2490system.l2c.tags.occ_task_id_percent::1022 0.419968 # Percentage of cache occupancy per task id 2491system.l2c.tags.occ_task_id_percent::1023 0.001205 # Percentage of cache occupancy per task id 2492system.l2c.tags.occ_task_id_percent::1024 0.554291 # Percentage of cache occupancy per task id 2493system.l2c.tags.tag_accesses 6440622 # Number of tag accesses 2494system.l2c.tags.data_accesses 6440622 # Number of data accesses 2495system.l2c.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2496system.l2c.WritebackDirty_hits::writebacks 269250 # number of WritebackDirty hits 2497system.l2c.WritebackDirty_hits::total 269250 # number of WritebackDirty hits 2498system.l2c.UpgradeReq_hits::cpu0.data 33826 # number of UpgradeReq hits 2499system.l2c.UpgradeReq_hits::cpu1.data 2712 # number of UpgradeReq hits 2500system.l2c.UpgradeReq_hits::total 36538 # number of UpgradeReq hits 2501system.l2c.SCUpgradeReq_hits::cpu0.data 2202 # number of SCUpgradeReq hits 2502system.l2c.SCUpgradeReq_hits::cpu1.data 1074 # number of SCUpgradeReq hits 2503system.l2c.SCUpgradeReq_hits::total 3276 # number of SCUpgradeReq hits 2504system.l2c.ReadExReq_hits::cpu0.data 4226 # number of ReadExReq hits 2505system.l2c.ReadExReq_hits::cpu1.data 1659 # number of ReadExReq hits 2506system.l2c.ReadExReq_hits::total 5885 # number of ReadExReq hits 2507system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 466 # number of ReadSharedReq hits 2508system.l2c.ReadSharedReq_hits::cpu0.itb.walker 69 # number of ReadSharedReq hits 2509system.l2c.ReadSharedReq_hits::cpu0.inst 46028 # number of ReadSharedReq hits 2510system.l2c.ReadSharedReq_hits::cpu0.data 50195 # number of ReadSharedReq hits 2511system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48669 # number of ReadSharedReq hits 2512system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 136 # number of ReadSharedReq hits 2513system.l2c.ReadSharedReq_hits::cpu1.itb.walker 26 # number of ReadSharedReq hits 2514system.l2c.ReadSharedReq_hits::cpu1.inst 16745 # number of ReadSharedReq hits 2515system.l2c.ReadSharedReq_hits::cpu1.data 10025 # number of ReadSharedReq hits 2516system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5491 # number of ReadSharedReq hits 2517system.l2c.ReadSharedReq_hits::total 177850 # number of ReadSharedReq hits 2518system.l2c.demand_hits::cpu0.dtb.walker 466 # number of demand (read+write) hits 2519system.l2c.demand_hits::cpu0.itb.walker 69 # number of demand (read+write) hits 2520system.l2c.demand_hits::cpu0.inst 46028 # number of demand (read+write) hits 2521system.l2c.demand_hits::cpu0.data 54421 # number of demand (read+write) hits 2522system.l2c.demand_hits::cpu0.l2cache.prefetcher 48669 # number of demand (read+write) hits 2523system.l2c.demand_hits::cpu1.dtb.walker 136 # number of demand (read+write) hits 2524system.l2c.demand_hits::cpu1.itb.walker 26 # number of demand (read+write) hits 2525system.l2c.demand_hits::cpu1.inst 16745 # number of demand (read+write) hits 2526system.l2c.demand_hits::cpu1.data 11684 # number of demand (read+write) hits 2527system.l2c.demand_hits::cpu1.l2cache.prefetcher 5491 # number of demand (read+write) hits 2528system.l2c.demand_hits::total 183735 # number of demand (read+write) hits 2529system.l2c.overall_hits::cpu0.dtb.walker 466 # number of overall hits 2530system.l2c.overall_hits::cpu0.itb.walker 69 # number of overall hits 2531system.l2c.overall_hits::cpu0.inst 46028 # number of overall hits 2532system.l2c.overall_hits::cpu0.data 54421 # number of overall hits 2533system.l2c.overall_hits::cpu0.l2cache.prefetcher 48669 # number of overall hits 2534system.l2c.overall_hits::cpu1.dtb.walker 136 # number of overall hits 2535system.l2c.overall_hits::cpu1.itb.walker 26 # number of overall hits 2536system.l2c.overall_hits::cpu1.inst 16745 # number of overall hits 2537system.l2c.overall_hits::cpu1.data 11684 # number of overall hits 2538system.l2c.overall_hits::cpu1.l2cache.prefetcher 5491 # number of overall hits 2539system.l2c.overall_hits::total 183735 # number of overall hits 2540system.l2c.UpgradeReq_misses::cpu0.data 9873 # number of UpgradeReq misses 2541system.l2c.UpgradeReq_misses::cpu1.data 3017 # number of UpgradeReq misses 2542system.l2c.UpgradeReq_misses::total 12890 # number of UpgradeReq misses 2543system.l2c.SCUpgradeReq_misses::cpu0.data 747 # number of SCUpgradeReq misses 2544system.l2c.SCUpgradeReq_misses::cpu1.data 1385 # number of SCUpgradeReq misses 2545system.l2c.SCUpgradeReq_misses::total 2132 # number of SCUpgradeReq misses 2546system.l2c.ReadExReq_misses::cpu0.data 11157 # number of ReadExReq misses 2547system.l2c.ReadExReq_misses::cpu1.data 8253 # number of ReadExReq misses 2548system.l2c.ReadExReq_misses::total 19410 # number of ReadExReq misses 2549system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 117 # number of ReadSharedReq misses 2550system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses 2551system.l2c.ReadSharedReq_misses::cpu0.inst 22311 # number of ReadSharedReq misses 2552system.l2c.ReadSharedReq_misses::cpu0.data 9661 # number of ReadSharedReq misses 2553system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130681 # number of ReadSharedReq misses 2554system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 13 # number of ReadSharedReq misses 2555system.l2c.ReadSharedReq_misses::cpu1.inst 3296 # number of ReadSharedReq misses 2556system.l2c.ReadSharedReq_misses::cpu1.data 1822 # number of ReadSharedReq misses 2557system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6980 # number of ReadSharedReq misses 2558system.l2c.ReadSharedReq_misses::total 174882 # number of ReadSharedReq misses 2559system.l2c.demand_misses::cpu0.dtb.walker 117 # number of demand (read+write) misses 2560system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2561system.l2c.demand_misses::cpu0.inst 22311 # number of demand (read+write) misses 2562system.l2c.demand_misses::cpu0.data 20818 # number of demand (read+write) misses 2563system.l2c.demand_misses::cpu0.l2cache.prefetcher 130681 # number of demand (read+write) misses 2564system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses 2565system.l2c.demand_misses::cpu1.inst 3296 # number of demand (read+write) misses 2566system.l2c.demand_misses::cpu1.data 10075 # number of demand (read+write) misses 2567system.l2c.demand_misses::cpu1.l2cache.prefetcher 6980 # number of demand (read+write) misses 2568system.l2c.demand_misses::total 194292 # number of demand (read+write) misses 2569system.l2c.overall_misses::cpu0.dtb.walker 117 # number of overall misses 2570system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2571system.l2c.overall_misses::cpu0.inst 22311 # number of overall misses 2572system.l2c.overall_misses::cpu0.data 20818 # number of overall misses 2573system.l2c.overall_misses::cpu0.l2cache.prefetcher 130681 # number of overall misses 2574system.l2c.overall_misses::cpu1.dtb.walker 13 # number of overall misses 2575system.l2c.overall_misses::cpu1.inst 3296 # number of overall misses 2576system.l2c.overall_misses::cpu1.data 10075 # number of overall misses 2577system.l2c.overall_misses::cpu1.l2cache.prefetcher 6980 # number of overall misses 2578system.l2c.overall_misses::total 194292 # number of overall misses 2579system.l2c.UpgradeReq_miss_latency::cpu0.data 11941000 # number of UpgradeReq miss cycles 2580system.l2c.UpgradeReq_miss_latency::cpu1.data 3314000 # number of UpgradeReq miss cycles 2581system.l2c.UpgradeReq_miss_latency::total 15255000 # number of UpgradeReq miss cycles 2582system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1661000 # number of SCUpgradeReq miss cycles 2583system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2074000 # number of SCUpgradeReq miss cycles 2584system.l2c.SCUpgradeReq_miss_latency::total 3735000 # number of SCUpgradeReq miss cycles 2585system.l2c.ReadExReq_miss_latency::cpu0.data 1109421000 # number of ReadExReq miss cycles 2586system.l2c.ReadExReq_miss_latency::cpu1.data 686062500 # number of ReadExReq miss cycles 2587system.l2c.ReadExReq_miss_latency::total 1795483500 # number of ReadExReq miss cycles 2588system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10072500 # number of ReadSharedReq miss cycles 2589system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 84000 # number of ReadSharedReq miss cycles 2590system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1812545500 # number of ReadSharedReq miss cycles 2591system.l2c.ReadSharedReq_miss_latency::cpu0.data 856898000 # number of ReadSharedReq miss cycles 2592system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13156370360 # number of ReadSharedReq miss cycles 2593system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1285500 # number of ReadSharedReq miss cycles 2594system.l2c.ReadSharedReq_miss_latency::cpu1.inst 273248000 # number of ReadSharedReq miss cycles 2595system.l2c.ReadSharedReq_miss_latency::cpu1.data 169259000 # number of ReadSharedReq miss cycles 2596system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 891916725 # number of ReadSharedReq miss cycles 2597system.l2c.ReadSharedReq_miss_latency::total 17171679585 # number of ReadSharedReq miss cycles 2598system.l2c.demand_miss_latency::cpu0.dtb.walker 10072500 # number of demand (read+write) miss cycles 2599system.l2c.demand_miss_latency::cpu0.itb.walker 84000 # number of demand (read+write) miss cycles 2600system.l2c.demand_miss_latency::cpu0.inst 1812545500 # number of demand (read+write) miss cycles 2601system.l2c.demand_miss_latency::cpu0.data 1966319000 # number of demand (read+write) miss cycles 2602system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13156370360 # number of demand (read+write) miss cycles 2603system.l2c.demand_miss_latency::cpu1.dtb.walker 1285500 # number of demand (read+write) miss cycles 2604system.l2c.demand_miss_latency::cpu1.inst 273248000 # number of demand (read+write) miss cycles 2605system.l2c.demand_miss_latency::cpu1.data 855321500 # number of demand (read+write) miss cycles 2606system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 891916725 # number of demand (read+write) miss cycles 2607system.l2c.demand_miss_latency::total 18967163085 # number of demand (read+write) miss cycles 2608system.l2c.overall_miss_latency::cpu0.dtb.walker 10072500 # number of overall miss cycles 2609system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles 2610system.l2c.overall_miss_latency::cpu0.inst 1812545500 # number of overall miss cycles 2611system.l2c.overall_miss_latency::cpu0.data 1966319000 # number of overall miss cycles 2612system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13156370360 # number of overall miss cycles 2613system.l2c.overall_miss_latency::cpu1.dtb.walker 1285500 # number of overall miss cycles 2614system.l2c.overall_miss_latency::cpu1.inst 273248000 # number of overall miss cycles 2615system.l2c.overall_miss_latency::cpu1.data 855321500 # number of overall miss cycles 2616system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 891916725 # number of overall miss cycles 2617system.l2c.overall_miss_latency::total 18967163085 # number of overall miss cycles 2618system.l2c.WritebackDirty_accesses::writebacks 269250 # number of WritebackDirty accesses(hits+misses) 2619system.l2c.WritebackDirty_accesses::total 269250 # number of WritebackDirty accesses(hits+misses) 2620system.l2c.UpgradeReq_accesses::cpu0.data 43699 # number of UpgradeReq accesses(hits+misses) 2621system.l2c.UpgradeReq_accesses::cpu1.data 5729 # number of UpgradeReq accesses(hits+misses) 2622system.l2c.UpgradeReq_accesses::total 49428 # number of UpgradeReq accesses(hits+misses) 2623system.l2c.SCUpgradeReq_accesses::cpu0.data 2949 # number of SCUpgradeReq accesses(hits+misses) 2624system.l2c.SCUpgradeReq_accesses::cpu1.data 2459 # number of SCUpgradeReq accesses(hits+misses) 2625system.l2c.SCUpgradeReq_accesses::total 5408 # number of SCUpgradeReq accesses(hits+misses) 2626system.l2c.ReadExReq_accesses::cpu0.data 15383 # number of ReadExReq accesses(hits+misses) 2627system.l2c.ReadExReq_accesses::cpu1.data 9912 # number of ReadExReq accesses(hits+misses) 2628system.l2c.ReadExReq_accesses::total 25295 # number of ReadExReq accesses(hits+misses) 2629system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 583 # number of ReadSharedReq accesses(hits+misses) 2630system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) 2631system.l2c.ReadSharedReq_accesses::cpu0.inst 68339 # number of ReadSharedReq accesses(hits+misses) 2632system.l2c.ReadSharedReq_accesses::cpu0.data 59856 # number of ReadSharedReq accesses(hits+misses) 2633system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179350 # number of ReadSharedReq accesses(hits+misses) 2634system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 149 # number of ReadSharedReq accesses(hits+misses) 2635system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 26 # number of ReadSharedReq accesses(hits+misses) 2636system.l2c.ReadSharedReq_accesses::cpu1.inst 20041 # number of ReadSharedReq accesses(hits+misses) 2637system.l2c.ReadSharedReq_accesses::cpu1.data 11847 # number of ReadSharedReq accesses(hits+misses) 2638system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 12471 # number of ReadSharedReq accesses(hits+misses) 2639system.l2c.ReadSharedReq_accesses::total 352732 # number of ReadSharedReq accesses(hits+misses) 2640system.l2c.demand_accesses::cpu0.dtb.walker 583 # number of demand (read+write) accesses 2641system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses 2642system.l2c.demand_accesses::cpu0.inst 68339 # number of demand (read+write) accesses 2643system.l2c.demand_accesses::cpu0.data 75239 # number of demand (read+write) accesses 2644system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179350 # number of demand (read+write) accesses 2645system.l2c.demand_accesses::cpu1.dtb.walker 149 # number of demand (read+write) accesses 2646system.l2c.demand_accesses::cpu1.itb.walker 26 # number of demand (read+write) accesses 2647system.l2c.demand_accesses::cpu1.inst 20041 # number of demand (read+write) accesses 2648system.l2c.demand_accesses::cpu1.data 21759 # number of demand (read+write) accesses 2649system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12471 # number of demand (read+write) accesses 2650system.l2c.demand_accesses::total 378027 # number of demand (read+write) accesses 2651system.l2c.overall_accesses::cpu0.dtb.walker 583 # number of overall (read+write) accesses 2652system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses 2653system.l2c.overall_accesses::cpu0.inst 68339 # number of overall (read+write) accesses 2654system.l2c.overall_accesses::cpu0.data 75239 # number of overall (read+write) accesses 2655system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179350 # number of overall (read+write) accesses 2656system.l2c.overall_accesses::cpu1.dtb.walker 149 # number of overall (read+write) accesses 2657system.l2c.overall_accesses::cpu1.itb.walker 26 # number of overall (read+write) accesses 2658system.l2c.overall_accesses::cpu1.inst 20041 # number of overall (read+write) accesses 2659system.l2c.overall_accesses::cpu1.data 21759 # number of overall (read+write) accesses 2660system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12471 # number of overall (read+write) accesses 2661system.l2c.overall_accesses::total 378027 # number of overall (read+write) accesses 2662system.l2c.UpgradeReq_miss_rate::cpu0.data 0.225932 # miss rate for UpgradeReq accesses 2663system.l2c.UpgradeReq_miss_rate::cpu1.data 0.526619 # miss rate for UpgradeReq accesses 2664system.l2c.UpgradeReq_miss_rate::total 0.260783 # miss rate for UpgradeReq accesses 2665system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.253306 # miss rate for SCUpgradeReq accesses 2666system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.563237 # miss rate for SCUpgradeReq accesses 2667system.l2c.SCUpgradeReq_miss_rate::total 0.394231 # miss rate for SCUpgradeReq accesses 2668system.l2c.ReadExReq_miss_rate::cpu0.data 0.725281 # miss rate for ReadExReq accesses 2669system.l2c.ReadExReq_miss_rate::cpu1.data 0.832627 # miss rate for ReadExReq accesses 2670system.l2c.ReadExReq_miss_rate::total 0.767345 # miss rate for ReadExReq accesses 2671system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.200686 # miss rate for ReadSharedReq accesses 2672system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.014286 # miss rate for ReadSharedReq accesses 2673system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.326475 # miss rate for ReadSharedReq accesses 2674system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.161404 # miss rate for ReadSharedReq accesses 2675system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.728637 # miss rate for ReadSharedReq accesses 2676system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.087248 # miss rate for ReadSharedReq accesses 2677system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.164463 # miss rate for ReadSharedReq accesses 2678system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.153794 # miss rate for ReadSharedReq accesses 2679system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.559699 # miss rate for ReadSharedReq accesses 2680system.l2c.ReadSharedReq_miss_rate::total 0.495793 # miss rate for ReadSharedReq accesses 2681system.l2c.demand_miss_rate::cpu0.dtb.walker 0.200686 # miss rate for demand accesses 2682system.l2c.demand_miss_rate::cpu0.itb.walker 0.014286 # miss rate for demand accesses 2683system.l2c.demand_miss_rate::cpu0.inst 0.326475 # miss rate for demand accesses 2684system.l2c.demand_miss_rate::cpu0.data 0.276692 # miss rate for demand accesses 2685system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.728637 # miss rate for demand accesses 2686system.l2c.demand_miss_rate::cpu1.dtb.walker 0.087248 # miss rate for demand accesses 2687system.l2c.demand_miss_rate::cpu1.inst 0.164463 # miss rate for demand accesses 2688system.l2c.demand_miss_rate::cpu1.data 0.463027 # miss rate for demand accesses 2689system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.559699 # miss rate for demand accesses 2690system.l2c.demand_miss_rate::total 0.513963 # miss rate for demand accesses 2691system.l2c.overall_miss_rate::cpu0.dtb.walker 0.200686 # miss rate for overall accesses 2692system.l2c.overall_miss_rate::cpu0.itb.walker 0.014286 # miss rate for overall accesses 2693system.l2c.overall_miss_rate::cpu0.inst 0.326475 # miss rate for overall accesses 2694system.l2c.overall_miss_rate::cpu0.data 0.276692 # miss rate for overall accesses 2695system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.728637 # miss rate for overall accesses 2696system.l2c.overall_miss_rate::cpu1.dtb.walker 0.087248 # miss rate for overall accesses 2697system.l2c.overall_miss_rate::cpu1.inst 0.164463 # miss rate for overall accesses 2698system.l2c.overall_miss_rate::cpu1.data 0.463027 # miss rate for overall accesses 2699system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.559699 # miss rate for overall accesses 2700system.l2c.overall_miss_rate::total 0.513963 # miss rate for overall accesses 2701system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1209.460144 # average UpgradeReq miss latency 2702system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1098.442161 # average UpgradeReq miss latency 2703system.l2c.UpgradeReq_avg_miss_latency::total 1183.475562 # average UpgradeReq miss latency 2704system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2223.560910 # average SCUpgradeReq miss latency 2705system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1497.472924 # average SCUpgradeReq miss latency 2706system.l2c.SCUpgradeReq_avg_miss_latency::total 1751.876173 # average SCUpgradeReq miss latency 2707system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99437.214305 # average ReadExReq miss latency 2708system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83128.862232 # average ReadExReq miss latency 2709system.l2c.ReadExReq_avg_miss_latency::total 92503.013910 # average ReadExReq miss latency 2710system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86089.743590 # average ReadSharedReq miss latency 2711system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 84000 # average ReadSharedReq miss latency 2712system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81239.993725 # average ReadSharedReq miss latency 2713system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88696.615257 # average ReadSharedReq miss latency 2714system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 100675.464375 # average ReadSharedReq miss latency 2715system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 98884.615385 # average ReadSharedReq miss latency 2716system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82902.912621 # average ReadSharedReq miss latency 2717system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92897.365532 # average ReadSharedReq miss latency 2718system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 127781.765759 # average ReadSharedReq miss latency 2719system.l2c.ReadSharedReq_avg_miss_latency::total 98190.091519 # average ReadSharedReq miss latency 2720system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86089.743590 # average overall miss latency 2721system.l2c.demand_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency 2722system.l2c.demand_avg_miss_latency::cpu0.inst 81239.993725 # average overall miss latency 2723system.l2c.demand_avg_miss_latency::cpu0.data 94452.829282 # average overall miss latency 2724system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100675.464375 # average overall miss latency 2725system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 98884.615385 # average overall miss latency 2726system.l2c.demand_avg_miss_latency::cpu1.inst 82902.912621 # average overall miss latency 2727system.l2c.demand_avg_miss_latency::cpu1.data 84895.434243 # average overall miss latency 2728system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 127781.765759 # average overall miss latency 2729system.l2c.demand_avg_miss_latency::total 97621.945757 # average overall miss latency 2730system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86089.743590 # average overall miss latency 2731system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency 2732system.l2c.overall_avg_miss_latency::cpu0.inst 81239.993725 # average overall miss latency 2733system.l2c.overall_avg_miss_latency::cpu0.data 94452.829282 # average overall miss latency 2734system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100675.464375 # average overall miss latency 2735system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 98884.615385 # average overall miss latency 2736system.l2c.overall_avg_miss_latency::cpu1.inst 82902.912621 # average overall miss latency 2737system.l2c.overall_avg_miss_latency::cpu1.data 84895.434243 # average overall miss latency 2738system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 127781.765759 # average overall miss latency 2739system.l2c.overall_avg_miss_latency::total 97621.945757 # average overall miss latency 2740system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2741system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2742system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2743system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2744system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2745system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2746system.l2c.writebacks::writebacks 102453 # number of writebacks 2747system.l2c.writebacks::total 102453 # number of writebacks 2748system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits 2749system.l2c.ReadSharedReq_mshr_hits::total 3 # number of ReadSharedReq MSHR hits 2750system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 2751system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 2752system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 2753system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits 2754system.l2c.CleanEvict_mshr_misses::writebacks 4008 # number of CleanEvict MSHR misses 2755system.l2c.CleanEvict_mshr_misses::total 4008 # number of CleanEvict MSHR misses 2756system.l2c.UpgradeReq_mshr_misses::cpu0.data 9873 # number of UpgradeReq MSHR misses 2757system.l2c.UpgradeReq_mshr_misses::cpu1.data 3017 # number of UpgradeReq MSHR misses 2758system.l2c.UpgradeReq_mshr_misses::total 12890 # number of UpgradeReq MSHR misses 2759system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 747 # number of SCUpgradeReq MSHR misses 2760system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1385 # number of SCUpgradeReq MSHR misses 2761system.l2c.SCUpgradeReq_mshr_misses::total 2132 # number of SCUpgradeReq MSHR misses 2762system.l2c.ReadExReq_mshr_misses::cpu0.data 11157 # number of ReadExReq MSHR misses 2763system.l2c.ReadExReq_mshr_misses::cpu1.data 8253 # number of ReadExReq MSHR misses 2764system.l2c.ReadExReq_mshr_misses::total 19410 # number of ReadExReq MSHR misses 2765system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 117 # number of ReadSharedReq MSHR misses 2766system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses 2767system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22308 # number of ReadSharedReq MSHR misses 2768system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9661 # number of ReadSharedReq MSHR misses 2769system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130681 # number of ReadSharedReq MSHR misses 2770system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 13 # number of ReadSharedReq MSHR misses 2771system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3296 # number of ReadSharedReq MSHR misses 2772system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1822 # number of ReadSharedReq MSHR misses 2773system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6980 # number of ReadSharedReq MSHR misses 2774system.l2c.ReadSharedReq_mshr_misses::total 174879 # number of ReadSharedReq MSHR misses 2775system.l2c.demand_mshr_misses::cpu0.dtb.walker 117 # number of demand (read+write) MSHR misses 2776system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2777system.l2c.demand_mshr_misses::cpu0.inst 22308 # number of demand (read+write) MSHR misses 2778system.l2c.demand_mshr_misses::cpu0.data 20818 # number of demand (read+write) MSHR misses 2779system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130681 # number of demand (read+write) MSHR misses 2780system.l2c.demand_mshr_misses::cpu1.dtb.walker 13 # number of demand (read+write) MSHR misses 2781system.l2c.demand_mshr_misses::cpu1.inst 3296 # number of demand (read+write) MSHR misses 2782system.l2c.demand_mshr_misses::cpu1.data 10075 # number of demand (read+write) MSHR misses 2783system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6980 # number of demand (read+write) MSHR misses 2784system.l2c.demand_mshr_misses::total 194289 # number of demand (read+write) MSHR misses 2785system.l2c.overall_mshr_misses::cpu0.dtb.walker 117 # number of overall MSHR misses 2786system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2787system.l2c.overall_mshr_misses::cpu0.inst 22308 # number of overall MSHR misses 2788system.l2c.overall_mshr_misses::cpu0.data 20818 # number of overall MSHR misses 2789system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130681 # number of overall MSHR misses 2790system.l2c.overall_mshr_misses::cpu1.dtb.walker 13 # number of overall MSHR misses 2791system.l2c.overall_mshr_misses::cpu1.inst 3296 # number of overall MSHR misses 2792system.l2c.overall_mshr_misses::cpu1.data 10075 # number of overall MSHR misses 2793system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6980 # number of overall MSHR misses 2794system.l2c.overall_mshr_misses::total 194289 # number of overall MSHR misses 2795system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable 2796system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable 2797system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2798system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14421 # number of ReadReq MSHR uncacheable 2799system.l2c.ReadReq_mshr_uncacheable::total 38557 # number of ReadReq MSHR uncacheable 2800system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable 2801system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11758 # number of WriteReq MSHR uncacheable 2802system.l2c.WriteReq_mshr_uncacheable::total 31029 # number of WriteReq MSHR uncacheable 2803system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses 2804system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses 2805system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2806system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses 2807system.l2c.overall_mshr_uncacheable_misses::total 69586 # number of overall MSHR uncacheable misses 2808system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 236541500 # number of UpgradeReq MSHR miss cycles 2809system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 69602500 # number of UpgradeReq MSHR miss cycles 2810system.l2c.UpgradeReq_mshr_miss_latency::total 306144000 # number of UpgradeReq MSHR miss cycles 2811system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 19267000 # number of SCUpgradeReq MSHR miss cycles 2812system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 34208500 # number of SCUpgradeReq MSHR miss cycles 2813system.l2c.SCUpgradeReq_mshr_miss_latency::total 53475500 # number of SCUpgradeReq MSHR miss cycles 2814system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 997851000 # number of ReadExReq MSHR miss cycles 2815system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 603531502 # number of ReadExReq MSHR miss cycles 2816system.l2c.ReadExReq_mshr_miss_latency::total 1601382502 # number of ReadExReq MSHR miss cycles 2817system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 8902500 # number of ReadSharedReq MSHR miss cycles 2818system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 74000 # number of ReadSharedReq MSHR miss cycles 2819system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1589128504 # number of ReadSharedReq MSHR miss cycles 2820system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 760287501 # number of ReadSharedReq MSHR miss cycles 2821system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11849557367 # number of ReadSharedReq MSHR miss cycles 2822system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1155500 # number of ReadSharedReq MSHR miss cycles 2823system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 240287501 # number of ReadSharedReq MSHR miss cycles 2824system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 151039000 # number of ReadSharedReq MSHR miss cycles 2825system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 822114729 # number of ReadSharedReq MSHR miss cycles 2826system.l2c.ReadSharedReq_mshr_miss_latency::total 15422546602 # number of ReadSharedReq MSHR miss cycles 2827system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 8902500 # number of demand (read+write) MSHR miss cycles 2828system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 74000 # number of demand (read+write) MSHR miss cycles 2829system.l2c.demand_mshr_miss_latency::cpu0.inst 1589128504 # number of demand (read+write) MSHR miss cycles 2830system.l2c.demand_mshr_miss_latency::cpu0.data 1758138501 # number of demand (read+write) MSHR miss cycles 2831system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11849557367 # number of demand (read+write) MSHR miss cycles 2832system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1155500 # number of demand (read+write) MSHR miss cycles 2833system.l2c.demand_mshr_miss_latency::cpu1.inst 240287501 # number of demand (read+write) MSHR miss cycles 2834system.l2c.demand_mshr_miss_latency::cpu1.data 754570502 # number of demand (read+write) MSHR miss cycles 2835system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 822114729 # number of demand (read+write) MSHR miss cycles 2836system.l2c.demand_mshr_miss_latency::total 17023929104 # number of demand (read+write) MSHR miss cycles 2837system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 8902500 # number of overall MSHR miss cycles 2838system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles 2839system.l2c.overall_mshr_miss_latency::cpu0.inst 1589128504 # number of overall MSHR miss cycles 2840system.l2c.overall_mshr_miss_latency::cpu0.data 1758138501 # number of overall MSHR miss cycles 2841system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11849557367 # number of overall MSHR miss cycles 2842system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1155500 # number of overall MSHR miss cycles 2843system.l2c.overall_mshr_miss_latency::cpu1.inst 240287501 # number of overall MSHR miss cycles 2844system.l2c.overall_mshr_miss_latency::cpu1.data 754570502 # number of overall MSHR miss cycles 2845system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 822114729 # number of overall MSHR miss cycles 2846system.l2c.overall_mshr_miss_latency::total 17023929104 # number of overall MSHR miss cycles 2847system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 219448500 # number of ReadReq MSHR uncacheable cycles 2848system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4080498000 # number of ReadReq MSHR uncacheable cycles 2849system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7226000 # number of ReadReq MSHR uncacheable cycles 2850system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2104700001 # number of ReadReq MSHR uncacheable cycles 2851system.l2c.ReadReq_mshr_uncacheable_latency::total 6411872501 # number of ReadReq MSHR uncacheable cycles 2852system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 219448500 # number of overall MSHR uncacheable cycles 2853system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4080498000 # number of overall MSHR uncacheable cycles 2854system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7226000 # number of overall MSHR uncacheable cycles 2855system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2104700001 # number of overall MSHR uncacheable cycles 2856system.l2c.overall_mshr_uncacheable_latency::total 6411872501 # number of overall MSHR uncacheable cycles 2857system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2858system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2859system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225932 # mshr miss rate for UpgradeReq accesses 2860system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.526619 # mshr miss rate for UpgradeReq accesses 2861system.l2c.UpgradeReq_mshr_miss_rate::total 0.260783 # mshr miss rate for UpgradeReq accesses 2862system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.253306 # mshr miss rate for SCUpgradeReq accesses 2863system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563237 # mshr miss rate for SCUpgradeReq accesses 2864system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.394231 # mshr miss rate for SCUpgradeReq accesses 2865system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725281 # mshr miss rate for ReadExReq accesses 2866system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.832627 # mshr miss rate for ReadExReq accesses 2867system.l2c.ReadExReq_mshr_miss_rate::total 0.767345 # mshr miss rate for ReadExReq accesses 2868system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for ReadSharedReq accesses 2869system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for ReadSharedReq accesses 2870system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for ReadSharedReq accesses 2871system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161404 # mshr miss rate for ReadSharedReq accesses 2872system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for ReadSharedReq accesses 2873system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for ReadSharedReq accesses 2874system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for ReadSharedReq accesses 2875system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.153794 # mshr miss rate for ReadSharedReq accesses 2876system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for ReadSharedReq accesses 2877system.l2c.ReadSharedReq_mshr_miss_rate::total 0.495784 # mshr miss rate for ReadSharedReq accesses 2878system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for demand accesses 2879system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for demand accesses 2880system.l2c.demand_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for demand accesses 2881system.l2c.demand_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for demand accesses 2882system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for demand accesses 2883system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for demand accesses 2884system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for demand accesses 2885system.l2c.demand_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for demand accesses 2886system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for demand accesses 2887system.l2c.demand_mshr_miss_rate::total 0.513955 # mshr miss rate for demand accesses 2888system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for overall accesses 2889system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for overall accesses 2890system.l2c.overall_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for overall accesses 2891system.l2c.overall_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for overall accesses 2892system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for overall accesses 2893system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for overall accesses 2894system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for overall accesses 2895system.l2c.overall_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for overall accesses 2896system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for overall accesses 2897system.l2c.overall_mshr_miss_rate::total 0.513955 # mshr miss rate for overall accesses 2898system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23958.421959 # average UpgradeReq mshr miss latency 2899system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23070.102751 # average UpgradeReq mshr miss latency 2900system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23750.504267 # average UpgradeReq mshr miss latency 2901system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25792.503347 # average SCUpgradeReq mshr miss latency 2902system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24699.277978 # average SCUpgradeReq mshr miss latency 2903system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25082.317073 # average SCUpgradeReq mshr miss latency 2904system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89437.214305 # average ReadExReq mshr miss latency 2905system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73128.741306 # average ReadExReq mshr miss latency 2906system.l2c.ReadExReq_avg_mshr_miss_latency::total 82502.962494 # average ReadExReq mshr miss latency 2907system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average ReadSharedReq mshr miss latency 2908system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadSharedReq mshr miss latency 2909system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average ReadSharedReq mshr miss latency 2910system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78696.563606 # average ReadSharedReq mshr miss latency 2911system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average ReadSharedReq mshr miss latency 2912system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average ReadSharedReq mshr miss latency 2913system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average ReadSharedReq mshr miss latency 2914system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82897.365532 # average ReadSharedReq mshr miss latency 2915system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average ReadSharedReq mshr miss latency 2916system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88189.814683 # average ReadSharedReq mshr miss latency 2917system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency 2918system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency 2919system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency 2920system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency 2921system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency 2922system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency 2923system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency 2924system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency 2925system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency 2926system.l2c.demand_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency 2927system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency 2928system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency 2929system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency 2930system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency 2931system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency 2932system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency 2933system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency 2934system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency 2935system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency 2936system.l2c.overall_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency 2937system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average ReadReq mshr uncacheable latency 2938system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198323.110571 # average ReadReq mshr uncacheable latency 2939system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average ReadReq mshr uncacheable latency 2940system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145946.883087 # average ReadReq mshr uncacheable latency 2941system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166295.938507 # average ReadReq mshr uncacheable latency 2942system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average overall mshr uncacheable latency 2943system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102406.715856 # average overall mshr uncacheable latency 2944system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average overall mshr uncacheable latency 2945system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80396.501050 # average overall mshr uncacheable latency 2946system.l2c.overall_avg_mshr_uncacheable_latency::total 92143.139439 # average overall mshr uncacheable latency 2947system.membus.snoop_filter.tot_requests 526346 # Total number of requests made to the snoop filter. 2948system.membus.snoop_filter.hit_single_requests 301567 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2949system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2950system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2951system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2952system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2953system.membus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2954system.membus.trans_dist::ReadReq 38557 # Transaction distribution 2955system.membus.trans_dist::ReadResp 213679 # Transaction distribution 2956system.membus.trans_dist::WriteReq 31029 # Transaction distribution 2957system.membus.trans_dist::WriteResp 31029 # Transaction distribution 2958system.membus.trans_dist::WritebackDirty 138659 # Transaction distribution 2959system.membus.trans_dist::CleanEvict 18543 # Transaction distribution 2960system.membus.trans_dist::UpgradeReq 76988 # Transaction distribution 2961system.membus.trans_dist::SCUpgradeReq 41072 # Transaction distribution 2962system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 2963system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2964system.membus.trans_dist::ReadExReq 39665 # Transaction distribution 2965system.membus.trans_dist::ReadExResp 19299 # Transaction distribution 2966system.membus.trans_dist::ReadSharedReq 175122 # Transaction distribution 2967system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2968system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2969system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 2970system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14190 # Packet count per connected master and slave (bytes) 2971system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664223 # Packet count per connected master and slave (bytes) 2972system.membus.pkt_count_system.l2c.mem_side::total 786371 # Packet count per connected master and slave (bytes) 2973system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) 2974system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) 2975system.membus.pkt_count::total 859302 # Packet count per connected master and slave (bytes) 2976system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2977system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) 2978system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28380 # Cumulative packet size per connected master and slave (bytes) 2979system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19209376 # Cumulative packet size per connected master and slave (bytes) 2980system.membus.pkt_size_system.l2c.mem_side::total 19401896 # Cumulative packet size per connected master and slave (bytes) 2981system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 2982system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 2983system.membus.pkt_size::total 21720040 # Cumulative packet size per connected master and slave (bytes) 2984system.membus.snoops 123861 # Total snoops (count) 2985system.membus.snoop_fanout::samples 438659 # Request fanout histogram 2986system.membus.snoop_fanout::mean 0.011132 # Request fanout histogram 2987system.membus.snoop_fanout::stdev 0.104918 # Request fanout histogram 2988system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2989system.membus.snoop_fanout::0 433776 98.89% 98.89% # Request fanout histogram 2990system.membus.snoop_fanout::1 4883 1.11% 100.00% # Request fanout histogram 2991system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2992system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2993system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2994system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2995system.membus.snoop_fanout::total 438659 # Request fanout histogram 2996system.membus.reqLayer0.occupancy 89013499 # Layer occupancy (ticks) 2997system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2998system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) 2999system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3000system.membus.reqLayer2.occupancy 12314999 # Layer occupancy (ticks) 3001system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3002system.membus.reqLayer5.occupancy 1002605728 # Layer occupancy (ticks) 3003system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3004system.membus.respLayer2.occupancy 1133893717 # Layer occupancy (ticks) 3005system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3006system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks) 3007system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3008system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3009system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3010system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3011system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3012system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3013system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3014system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3015system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3016system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3017system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3018system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3019system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3020system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3021system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3022system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3023system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3024system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3025system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3026system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3027system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3028system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3029system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3030system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3031system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3032system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3033system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3034system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3035system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3036system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3037system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3038system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3039system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3040system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3041system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3042system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3043system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3044system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3045system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3046system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3047system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3048system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3049system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3050system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3051system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3052system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3053system.realview.ethernet.droppedPackets 0 # number of packets dropped 3054system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3055system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3056system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3057system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3058system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3059system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3060system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3061system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3062system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3063system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3064system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3065system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3066system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3067system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3068system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3069system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3070system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3071system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3072system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3073system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3074system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3075system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3076system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3077system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter. 3078system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3079system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3080system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter. 3081system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3082system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3083system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3084system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution 3085system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution 3086system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution 3087system.toL2Bus.trans_dist::WriteResp 31029 # Transaction distribution 3088system.toL2Bus.trans_dist::WritebackDirty 371703 # Transaction distribution 3089system.toL2Bus.trans_dist::CleanEvict 144260 # Transaction distribution 3090system.toL2Bus.trans_dist::UpgradeReq 113415 # Transaction distribution 3091system.toL2Bus.trans_dist::SCUpgradeReq 44348 # Transaction distribution 3092system.toL2Bus.trans_dist::UpgradeResp 157763 # Transaction distribution 3093system.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution 3094system.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution 3095system.toL2Bus.trans_dist::ReadExReq 51662 # Transaction distribution 3096system.toL2Bus.trans_dist::ReadExResp 51662 # Transaction distribution 3097system.toL2Bus.trans_dist::ReadSharedReq 474894 # Transaction distribution 3098system.toL2Bus.trans_dist::InvalidateReq 4314 # Transaction distribution 3099system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1271960 # Packet count per connected master and slave (bytes) 3100system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368625 # Packet count per connected master and slave (bytes) 3101system.toL2Bus.pkt_count::total 1640585 # Packet count per connected master and slave (bytes) 3102system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36024040 # Cumulative packet size per connected master and slave (bytes) 3103system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5855360 # Cumulative packet size per connected master and slave (bytes) 3104system.toL2Bus.pkt_size::total 41879400 # Cumulative packet size per connected master and slave (bytes) 3105system.toL2Bus.snoops 387762 # Total snoops (count) 3106system.toL2Bus.snoop_fanout::samples 889983 # Request fanout histogram 3107system.toL2Bus.snoop_fanout::mean 0.383411 # Request fanout histogram 3108system.toL2Bus.snoop_fanout::stdev 0.488617 # Request fanout histogram 3109system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3110system.toL2Bus.snoop_fanout::0 549795 61.78% 61.78% # Request fanout histogram 3111system.toL2Bus.snoop_fanout::1 339147 38.11% 99.88% # Request fanout histogram 3112system.toL2Bus.snoop_fanout::2 1041 0.12% 100.00% # Request fanout histogram 3113system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3114system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3115system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3116system.toL2Bus.snoop_fanout::total 889983 # Request fanout histogram 3117system.toL2Bus.reqLayer0.occupancy 926156147 # Layer occupancy (ticks) 3118system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3119system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks) 3120system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3121system.toL2Bus.respLayer0.occupancy 669727799 # Layer occupancy (ticks) 3122system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3123system.toL2Bus.respLayer1.occupancy 257138606 # Layer occupancy (ticks) 3124system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3125 3126---------- End Simulation Statistics ----------	1499system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1500system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1501system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1502system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions 1503system.cpu1.itb.read_accesses 0 # DTB read accesses 1504system.cpu1.itb.write_accesses 0 # DTB write accesses 1505system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses 1506system.cpu1.itb.hits 39602800 # DTB hits 1507system.cpu1.itb.misses 2420 # DTB misses 1508system.cpu1.itb.accesses 39605220 # DTB accesses 1509system.cpu1.numPwrStateTransitions 5553 # Number of power state transitions 1510system.cpu1.pwrStateClkGateDist::samples 2777 # Distribution of time spent in the clock gated state 1511system.cpu1.pwrStateClkGateDist::mean 1004505001.039251 # Distribution of time spent in the clock gated state 1512system.cpu1.pwrStateClkGateDist::stdev 25654466824.490025 # Distribution of time spent in the clock gated state 1513system.cpu1.pwrStateClkGateDist::underflows 1974 71.08% 71.08% # Distribution of time spent in the clock gated state 1514system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.77% 99.86% # Distribution of time spent in the clock gated state 1515system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1516system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1517system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1518system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1519system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1520system.cpu1.pwrStateClkGateDist::max_value 949981296504 # Distribution of time spent in the clock gated state 1521system.cpu1.pwrStateClkGateDist::total 2777 # Distribution of time spent in the clock gated state 1522system.cpu1.pwrStateResidencyTicks::ON 57717018114 # Cumulative time (in ticks) in various power states 1523system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789510387886 # Cumulative time (in ticks) in various power states 1524system.cpu1.numCycles 115435582 # number of cpu cycles simulated 1525system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1526system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1527system.cpu1.committedInsts 47603897 # Number of instructions committed 1528system.cpu1.committedOps 58246015 # Number of ops (including micro ops) committed 1529system.cpu1.discardedOps 5049538 # Number of ops (including micro ops) which were discarded before commit 1530system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching 1531system.cpu1.quiesceCycles 5578401245 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1532system.cpu1.cpi 2.424919 # CPI: cycles per instruction 1533system.cpu1.ipc 0.412385 # IPC: instructions per cycle 1534system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction 1535system.cpu1.op_class_0::IntAlu 40076529 68.81% 68.81% # Class of committed instruction 1536system.cpu1.op_class_0::IntMult 45752 0.08% 68.88% # Class of committed instruction 1537system.cpu1.op_class_0::IntDiv 0 0.00% 68.88% # Class of committed instruction 1538system.cpu1.op_class_0::FloatAdd 0 0.00% 68.88% # Class of committed instruction 1539system.cpu1.op_class_0::FloatCmp 0 0.00% 68.88% # Class of committed instruction 1540system.cpu1.op_class_0::FloatCvt 0 0.00% 68.88% # Class of committed instruction 1541system.cpu1.op_class_0::FloatMult 0 0.00% 68.88% # Class of committed instruction 1542system.cpu1.op_class_0::FloatDiv 0 0.00% 68.88% # Class of committed instruction 1543system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.88% # Class of committed instruction 1544system.cpu1.op_class_0::SimdAdd 0 0.00% 68.88% # Class of committed instruction 1545system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.88% # Class of committed instruction 1546system.cpu1.op_class_0::SimdAlu 0 0.00% 68.88% # Class of committed instruction 1547system.cpu1.op_class_0::SimdCmp 0 0.00% 68.88% # Class of committed instruction 1548system.cpu1.op_class_0::SimdCvt 0 0.00% 68.88% # Class of committed instruction 1549system.cpu1.op_class_0::SimdMisc 0 0.00% 68.88% # Class of committed instruction 1550system.cpu1.op_class_0::SimdMult 0 0.00% 68.88% # Class of committed instruction 1551system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.88% # Class of committed instruction 1552system.cpu1.op_class_0::SimdShift 0 0.00% 68.88% # Class of committed instruction 1553system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.88% # Class of committed instruction 1554system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.88% # Class of committed instruction 1555system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.88% # Class of committed instruction 1556system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.88% # Class of committed instruction 1557system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.88% # Class of committed instruction 1558system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.88% # Class of committed instruction 1559system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.88% # Class of committed instruction 1560system.cpu1.op_class_0::SimdFloatMisc 3347 0.01% 68.89% # Class of committed instruction 1561system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.89% # Class of committed instruction 1562system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.89% # Class of committed instruction 1563system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.89% # Class of committed instruction 1564system.cpu1.op_class_0::MemRead 11012402 18.91% 87.80% # Class of committed instruction 1565system.cpu1.op_class_0::MemWrite 7107919 12.20% 100.00% # Class of committed instruction 1566system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1567system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1568system.cpu1.op_class_0::total 58246015 # Class of committed instruction 1569system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1570system.cpu1.kern.inst.quiesce 2777 # number of quiesce instructions executed 1571system.cpu1.tickCycles 97896037 # Number of cycles that the object actually ticked 1572system.cpu1.idleCycles 17539545 # Total number of cycles that the object has spent stopped 1573system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1574system.cpu1.dcache.tags.replacements 196286 # number of replacements 1575system.cpu1.dcache.tags.tagsinuse 471.109798 # Cycle average of tags in use 1576system.cpu1.dcache.tags.total_refs 17737294 # Total number of references to valid blocks. 1577system.cpu1.dcache.tags.sampled_refs 196629 # Sample count of references to valid blocks. 1578system.cpu1.dcache.tags.avg_refs 90.206907 # Average number of references to valid blocks. 1579system.cpu1.dcache.tags.warmup_cycle 91177108000 # Cycle when the warmup percentage was hit. 1580system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.109798 # Average occupied blocks per requestor 1581system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920136 # Average percentage of cache occupancy 1582system.cpu1.dcache.tags.occ_percent::total 0.920136 # Average percentage of cache occupancy 1583system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id 1584system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 1585system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 1586system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id 1587system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses 1588system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses 1589system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1590system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits 1591system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits 1592system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits 1593system.cpu1.dcache.WriteReq_hits::total 6704752 # number of WriteReq hits 1594system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50350 # number of SoftPFReq hits 1595system.cpu1.dcache.SoftPFReq_hits::total 50350 # number of SoftPFReq hits 1596system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80171 # number of LoadLockedReq hits 1597system.cpu1.dcache.LoadLockedReq_hits::total 80171 # number of LoadLockedReq hits 1598system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71533 # number of StoreCondReq hits 1599system.cpu1.dcache.StoreCondReq_hits::total 71533 # number of StoreCondReq hits 1600system.cpu1.dcache.demand_hits::cpu1.data 17499828 # number of demand (read+write) hits 1601system.cpu1.dcache.demand_hits::total 17499828 # number of demand (read+write) hits 1602system.cpu1.dcache.overall_hits::cpu1.data 17550178 # number of overall hits 1603system.cpu1.dcache.overall_hits::total 17550178 # number of overall hits 1604system.cpu1.dcache.ReadReq_misses::cpu1.data 159722 # number of ReadReq misses 1605system.cpu1.dcache.ReadReq_misses::total 159722 # number of ReadReq misses 1606system.cpu1.dcache.WriteReq_misses::cpu1.data 145538 # number of WriteReq misses 1607system.cpu1.dcache.WriteReq_misses::total 145538 # number of WriteReq misses 1608system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31004 # number of SoftPFReq misses 1609system.cpu1.dcache.SoftPFReq_misses::total 31004 # number of SoftPFReq misses 1610system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses 1611system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses 1612system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23795 # number of StoreCondReq misses 1613system.cpu1.dcache.StoreCondReq_misses::total 23795 # number of StoreCondReq misses 1614system.cpu1.dcache.demand_misses::cpu1.data 305260 # number of demand (read+write) misses 1615system.cpu1.dcache.demand_misses::total 305260 # number of demand (read+write) misses 1616system.cpu1.dcache.overall_misses::cpu1.data 336264 # number of overall misses 1617system.cpu1.dcache.overall_misses::total 336264 # number of overall misses 1618system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2429598500 # number of ReadReq miss cycles 1619system.cpu1.dcache.ReadReq_miss_latency::total 2429598500 # number of ReadReq miss cycles 1620system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3913148500 # number of WriteReq miss cycles 1621system.cpu1.dcache.WriteReq_miss_latency::total 3913148500 # number of WriteReq miss cycles 1622system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317482500 # number of LoadLockedReq miss cycles 1623system.cpu1.dcache.LoadLockedReq_miss_latency::total 317482500 # number of LoadLockedReq miss cycles 1624system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 583924500 # number of StoreCondReq miss cycles 1625system.cpu1.dcache.StoreCondReq_miss_latency::total 583924500 # number of StoreCondReq miss cycles 1626system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 387500 # number of StoreCondFailReq miss cycles 1627system.cpu1.dcache.StoreCondFailReq_miss_latency::total 387500 # number of StoreCondFailReq miss cycles 1628system.cpu1.dcache.demand_miss_latency::cpu1.data 6342747000 # number of demand (read+write) miss cycles 1629system.cpu1.dcache.demand_miss_latency::total 6342747000 # number of demand (read+write) miss cycles 1630system.cpu1.dcache.overall_miss_latency::cpu1.data 6342747000 # number of overall miss cycles 1631system.cpu1.dcache.overall_miss_latency::total 6342747000 # number of overall miss cycles 1632system.cpu1.dcache.ReadReq_accesses::cpu1.data 10954798 # number of ReadReq accesses(hits+misses) 1633system.cpu1.dcache.ReadReq_accesses::total 10954798 # number of ReadReq accesses(hits+misses) 1634system.cpu1.dcache.WriteReq_accesses::cpu1.data 6850290 # number of WriteReq accesses(hits+misses) 1635system.cpu1.dcache.WriteReq_accesses::total 6850290 # number of WriteReq accesses(hits+misses) 1636system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81354 # number of SoftPFReq accesses(hits+misses) 1637system.cpu1.dcache.SoftPFReq_accesses::total 81354 # number of SoftPFReq accesses(hits+misses) 1638system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97131 # number of LoadLockedReq accesses(hits+misses) 1639system.cpu1.dcache.LoadLockedReq_accesses::total 97131 # number of LoadLockedReq accesses(hits+misses) 1640system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95328 # number of StoreCondReq accesses(hits+misses) 1641system.cpu1.dcache.StoreCondReq_accesses::total 95328 # number of StoreCondReq accesses(hits+misses) 1642system.cpu1.dcache.demand_accesses::cpu1.data 17805088 # number of demand (read+write) accesses 1643system.cpu1.dcache.demand_accesses::total 17805088 # number of demand (read+write) accesses 1644system.cpu1.dcache.overall_accesses::cpu1.data 17886442 # number of overall (read+write) accesses 1645system.cpu1.dcache.overall_accesses::total 17886442 # number of overall (read+write) accesses 1646system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014580 # miss rate for ReadReq accesses 1647system.cpu1.dcache.ReadReq_miss_rate::total 0.014580 # miss rate for ReadReq accesses 1648system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021246 # miss rate for WriteReq accesses 1649system.cpu1.dcache.WriteReq_miss_rate::total 0.021246 # miss rate for WriteReq accesses 1650system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381100 # miss rate for SoftPFReq accesses 1651system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381100 # miss rate for SoftPFReq accesses 1652system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174610 # miss rate for LoadLockedReq accesses 1653system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174610 # miss rate for LoadLockedReq accesses 1654system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249612 # miss rate for StoreCondReq accesses 1655system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249612 # miss rate for StoreCondReq accesses 1656system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017145 # miss rate for demand accesses 1657system.cpu1.dcache.demand_miss_rate::total 0.017145 # miss rate for demand accesses 1658system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018800 # miss rate for overall accesses 1659system.cpu1.dcache.overall_miss_rate::total 0.018800 # miss rate for overall accesses 1660system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15211.420468 # average ReadReq miss latency 1661system.cpu1.dcache.ReadReq_avg_miss_latency::total 15211.420468 # average ReadReq miss latency 1662system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26887.469252 # average WriteReq miss latency 1663system.cpu1.dcache.WriteReq_avg_miss_latency::total 26887.469252 # average WriteReq miss latency 1664system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18719.487028 # average LoadLockedReq miss latency 1665system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18719.487028 # average LoadLockedReq miss latency 1666system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24539.798277 # average StoreCondReq miss latency 1667system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24539.798277 # average StoreCondReq miss latency 1668system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1669system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1670system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20778.179257 # average overall miss latency 1671system.cpu1.dcache.demand_avg_miss_latency::total 20778.179257 # average overall miss latency 1672system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18862.402755 # average overall miss latency 1673system.cpu1.dcache.overall_avg_miss_latency::total 18862.402755 # average overall miss latency 1674system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1675system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1676system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1677system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1678system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1679system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1680system.cpu1.dcache.writebacks::writebacks 196286 # number of writebacks 1681system.cpu1.dcache.writebacks::total 196286 # number of writebacks 1682system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16292 # number of ReadReq MSHR hits 1683system.cpu1.dcache.ReadReq_mshr_hits::total 16292 # number of ReadReq MSHR hits 1684system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52982 # number of WriteReq MSHR hits 1685system.cpu1.dcache.WriteReq_mshr_hits::total 52982 # number of WriteReq MSHR hits 1686system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12069 # number of LoadLockedReq MSHR hits 1687system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12069 # number of LoadLockedReq MSHR hits 1688system.cpu1.dcache.demand_mshr_hits::cpu1.data 69274 # number of demand (read+write) MSHR hits 1689system.cpu1.dcache.demand_mshr_hits::total 69274 # number of demand (read+write) MSHR hits 1690system.cpu1.dcache.overall_mshr_hits::cpu1.data 69274 # number of overall MSHR hits 1691system.cpu1.dcache.overall_mshr_hits::total 69274 # number of overall MSHR hits 1692system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143430 # number of ReadReq MSHR misses 1693system.cpu1.dcache.ReadReq_mshr_misses::total 143430 # number of ReadReq MSHR misses 1694system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92556 # number of WriteReq MSHR misses 1695system.cpu1.dcache.WriteReq_mshr_misses::total 92556 # number of WriteReq MSHR misses 1696system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30096 # number of SoftPFReq MSHR misses 1697system.cpu1.dcache.SoftPFReq_mshr_misses::total 30096 # number of SoftPFReq MSHR misses 1698system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses 1699system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses 1700system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23795 # number of StoreCondReq MSHR misses 1701system.cpu1.dcache.StoreCondReq_mshr_misses::total 23795 # number of StoreCondReq MSHR misses 1702system.cpu1.dcache.demand_mshr_misses::cpu1.data 235986 # number of demand (read+write) MSHR misses 1703system.cpu1.dcache.demand_mshr_misses::total 235986 # number of demand (read+write) MSHR misses 1704system.cpu1.dcache.overall_mshr_misses::cpu1.data 266082 # number of overall MSHR misses 1705system.cpu1.dcache.overall_mshr_misses::total 266082 # number of overall MSHR misses 1706system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable 1707system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable 1708system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11758 # number of WriteReq MSHR uncacheable 1709system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11758 # number of WriteReq MSHR uncacheable 1710system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26182 # number of overall MSHR uncacheable misses 1711system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26182 # number of overall MSHR uncacheable misses 1712system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2041290000 # number of ReadReq MSHR miss cycles 1713system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2041290000 # number of ReadReq MSHR miss cycles 1714system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2380409500 # number of WriteReq MSHR miss cycles 1715system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2380409500 # number of WriteReq MSHR miss cycles 1716system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 535271500 # number of SoftPFReq MSHR miss cycles 1717system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 535271500 # number of SoftPFReq MSHR miss cycles 1718system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82814000 # number of LoadLockedReq MSHR miss cycles 1719system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82814000 # number of LoadLockedReq MSHR miss cycles 1720system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 560137500 # number of StoreCondReq MSHR miss cycles 1721system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 560137500 # number of StoreCondReq MSHR miss cycles 1722system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 379500 # number of StoreCondFailReq MSHR miss cycles 1723system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 379500 # number of StoreCondFailReq MSHR miss cycles 1724system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4421699500 # number of demand (read+write) MSHR miss cycles 1725system.cpu1.dcache.demand_mshr_miss_latency::total 4421699500 # number of demand (read+write) MSHR miss cycles 1726system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4956971000 # number of overall MSHR miss cycles 1727system.cpu1.dcache.overall_mshr_miss_latency::total 4956971000 # number of overall MSHR miss cycles 1728system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2479783500 # number of ReadReq MSHR uncacheable cycles 1729system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2479783500 # number of ReadReq MSHR uncacheable cycles 1730system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2479783500 # number of overall MSHR uncacheable cycles 1731system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2479783500 # number of overall MSHR uncacheable cycles 1732system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013093 # mshr miss rate for ReadReq accesses 1733system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013093 # mshr miss rate for ReadReq accesses 1734system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013511 # mshr miss rate for WriteReq accesses 1735system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013511 # mshr miss rate for WriteReq accesses 1736system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369939 # mshr miss rate for SoftPFReq accesses 1737system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369939 # mshr miss rate for SoftPFReq accesses 1738system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050355 # mshr miss rate for LoadLockedReq accesses 1739system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050355 # mshr miss rate for LoadLockedReq accesses 1740system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249612 # mshr miss rate for StoreCondReq accesses 1741system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249612 # mshr miss rate for StoreCondReq accesses 1742system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013254 # mshr miss rate for demand accesses 1743system.cpu1.dcache.demand_mshr_miss_rate::total 0.013254 # mshr miss rate for demand accesses 1744system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014876 # mshr miss rate for overall accesses 1745system.cpu1.dcache.overall_mshr_miss_rate::total 0.014876 # mshr miss rate for overall accesses 1746system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14231.959841 # average ReadReq mshr miss latency 1747system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14231.959841 # average ReadReq mshr miss latency 1748system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25718.586585 # average WriteReq mshr miss latency 1749system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25718.586585 # average WriteReq mshr miss latency 1750system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17785.469830 # average SoftPFReq mshr miss latency 1751system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17785.469830 # average SoftPFReq mshr miss latency 1752system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16931.915764 # average LoadLockedReq mshr miss latency 1753system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16931.915764 # average LoadLockedReq mshr miss latency 1754system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23540.134482 # average StoreCondReq mshr miss latency 1755system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23540.134482 # average StoreCondReq mshr miss latency 1756system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1757system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1758system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18737.126355 # average overall mshr miss latency 1759system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18737.126355 # average overall mshr miss latency 1760system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18629.486399 # average overall mshr miss latency 1761system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18629.486399 # average overall mshr miss latency 1762system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078 # average ReadReq mshr uncacheable latency 1763system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency 1764system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency 1765system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency 1766system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1767system.cpu1.icache.tags.replacements 946364 # number of replacements 1768system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use 1769system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks. 1770system.cpu1.icache.tags.sampled_refs 946876 # Sample count of references to valid blocks. 1771system.cpu1.icache.tags.avg_refs 40.822690 # Average number of references to valid blocks. 1772system.cpu1.icache.tags.warmup_cycle 72815756000 # Cycle when the warmup percentage was hit. 1773system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.210861 # Average occupied blocks per requestor 1774system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975021 # Average percentage of cache occupancy 1775system.cpu1.icache.tags.occ_percent::total 0.975021 # Average percentage of cache occupancy 1776system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1777system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id 1778system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id 1779system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1780system.cpu1.icache.tags.tag_accesses 80148678 # Number of tag accesses 1781system.cpu1.icache.tags.data_accesses 80148678 # Number of data accesses 1782system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1783system.cpu1.icache.ReadReq_hits::cpu1.inst 38654025 # number of ReadReq hits 1784system.cpu1.icache.ReadReq_hits::total 38654025 # number of ReadReq hits 1785system.cpu1.icache.demand_hits::cpu1.inst 38654025 # number of demand (read+write) hits 1786system.cpu1.icache.demand_hits::total 38654025 # number of demand (read+write) hits 1787system.cpu1.icache.overall_hits::cpu1.inst 38654025 # number of overall hits 1788system.cpu1.icache.overall_hits::total 38654025 # number of overall hits 1789system.cpu1.icache.ReadReq_misses::cpu1.inst 946876 # number of ReadReq misses 1790system.cpu1.icache.ReadReq_misses::total 946876 # number of ReadReq misses 1791system.cpu1.icache.demand_misses::cpu1.inst 946876 # number of demand (read+write) misses 1792system.cpu1.icache.demand_misses::total 946876 # number of demand (read+write) misses 1793system.cpu1.icache.overall_misses::cpu1.inst 946876 # number of overall misses 1794system.cpu1.icache.overall_misses::total 946876 # number of overall misses 1795system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8324695000 # number of ReadReq miss cycles 1796system.cpu1.icache.ReadReq_miss_latency::total 8324695000 # number of ReadReq miss cycles 1797system.cpu1.icache.demand_miss_latency::cpu1.inst 8324695000 # number of demand (read+write) miss cycles 1798system.cpu1.icache.demand_miss_latency::total 8324695000 # number of demand (read+write) miss cycles 1799system.cpu1.icache.overall_miss_latency::cpu1.inst 8324695000 # number of overall miss cycles 1800system.cpu1.icache.overall_miss_latency::total 8324695000 # number of overall miss cycles 1801system.cpu1.icache.ReadReq_accesses::cpu1.inst 39600901 # number of ReadReq accesses(hits+misses) 1802system.cpu1.icache.ReadReq_accesses::total 39600901 # number of ReadReq accesses(hits+misses) 1803system.cpu1.icache.demand_accesses::cpu1.inst 39600901 # number of demand (read+write) accesses 1804system.cpu1.icache.demand_accesses::total 39600901 # number of demand (read+write) accesses 1805system.cpu1.icache.overall_accesses::cpu1.inst 39600901 # number of overall (read+write) accesses 1806system.cpu1.icache.overall_accesses::total 39600901 # number of overall (read+write) accesses 1807system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023910 # miss rate for ReadReq accesses 1808system.cpu1.icache.ReadReq_miss_rate::total 0.023910 # miss rate for ReadReq accesses 1809system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023910 # miss rate for demand accesses 1810system.cpu1.icache.demand_miss_rate::total 0.023910 # miss rate for demand accesses 1811system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023910 # miss rate for overall accesses 1812system.cpu1.icache.overall_miss_rate::total 0.023910 # miss rate for overall accesses 1813system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8791.747811 # average ReadReq miss latency 1814system.cpu1.icache.ReadReq_avg_miss_latency::total 8791.747811 # average ReadReq miss latency 1815system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency 1816system.cpu1.icache.demand_avg_miss_latency::total 8791.747811 # average overall miss latency 1817system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency 1818system.cpu1.icache.overall_avg_miss_latency::total 8791.747811 # average overall miss latency 1819system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1820system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1821system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1822system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1823system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1824system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1825system.cpu1.icache.writebacks::writebacks 946364 # number of writebacks 1826system.cpu1.icache.writebacks::total 946364 # number of writebacks 1827system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 946876 # number of ReadReq MSHR misses 1828system.cpu1.icache.ReadReq_mshr_misses::total 946876 # number of ReadReq MSHR misses 1829system.cpu1.icache.demand_mshr_misses::cpu1.inst 946876 # number of demand (read+write) MSHR misses 1830system.cpu1.icache.demand_mshr_misses::total 946876 # number of demand (read+write) MSHR misses 1831system.cpu1.icache.overall_mshr_misses::cpu1.inst 946876 # number of overall MSHR misses 1832system.cpu1.icache.overall_mshr_misses::total 946876 # number of overall MSHR misses 1833system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1834system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1835system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1836system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses 1837system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7851257000 # number of ReadReq MSHR miss cycles 1838system.cpu1.icache.ReadReq_mshr_miss_latency::total 7851257000 # number of ReadReq MSHR miss cycles 1839system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7851257000 # number of demand (read+write) MSHR miss cycles 1840system.cpu1.icache.demand_mshr_miss_latency::total 7851257000 # number of demand (read+write) MSHR miss cycles 1841system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7851257000 # number of overall MSHR miss cycles 1842system.cpu1.icache.overall_mshr_miss_latency::total 7851257000 # number of overall MSHR miss cycles 1843system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10474500 # number of ReadReq MSHR uncacheable cycles 1844system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10474500 # number of ReadReq MSHR uncacheable cycles 1845system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10474500 # number of overall MSHR uncacheable cycles 1846system.cpu1.icache.overall_mshr_uncacheable_latency::total 10474500 # number of overall MSHR uncacheable cycles 1847system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for ReadReq accesses 1848system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023910 # mshr miss rate for ReadReq accesses 1849system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for demand accesses 1850system.cpu1.icache.demand_mshr_miss_rate::total 0.023910 # mshr miss rate for demand accesses 1851system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for overall accesses 1852system.cpu1.icache.overall_mshr_miss_rate::total 0.023910 # mshr miss rate for overall accesses 1853system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average ReadReq mshr miss latency 1854system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8291.747811 # average ReadReq mshr miss latency 1855system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency 1856system.cpu1.icache.demand_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency 1857system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency 1858system.cpu1.icache.overall_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency 1859system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average ReadReq mshr uncacheable latency 1860system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency 1861system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency 1862system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency 1863system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1864system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued 1865system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified 1866system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue 1867system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1868system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1869system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing 1870system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1871system.cpu1.l2cache.tags.replacements 53638 # number of replacements 1872system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use 1873system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks. 1874system.cpu1.l2cache.tags.sampled_refs 68366 # Sample count of references to valid blocks. 1875system.cpu1.l2cache.tags.avg_refs 30.105579 # Average number of references to valid blocks. 1876system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1877system.cpu1.l2cache.tags.occ_blocks::writebacks 14816.571197 # Average occupied blocks per requestor 1878system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 39.116539 # Average occupied blocks per requestor 1879system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.045474 # Average occupied blocks per requestor 1880system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 428.691662 # Average occupied blocks per requestor 1881system.cpu1.l2cache.tags.occ_percent::writebacks 0.904332 # Average percentage of cache occupancy 1882system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002387 # Average percentage of cache occupancy 1883system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy 1884system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026165 # Average percentage of cache occupancy 1885system.cpu1.l2cache.tags.occ_percent::total 0.933009 # Average percentage of cache occupancy 1886system.cpu1.l2cache.tags.occ_task_id_blocks::1022 907 # Occupied blocks per task id 1887system.cpu1.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id 1888system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13776 # Occupied blocks per task id 1889system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id 1890system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 323 # Occupied blocks per task id 1891system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 581 # Occupied blocks per task id 1892system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id 1893system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5681 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7813 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.055359 # Percentage of cache occupancy per task id 1899system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id 1900system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id 1901system.cpu1.l2cache.tags.tag_accesses 38543839 # Number of tag accesses 1902system.cpu1.l2cache.tags.data_accesses 38543839 # Number of data accesses 1903system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 1904system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30076 # number of ReadReq hits 1905system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3135 # number of ReadReq hits 1906system.cpu1.l2cache.ReadReq_hits::total 33211 # number of ReadReq hits 1907system.cpu1.l2cache.WritebackDirty_hits::writebacks 117792 # number of WritebackDirty hits 1908system.cpu1.l2cache.WritebackDirty_hits::total 117792 # number of WritebackDirty hits 1909system.cpu1.l2cache.WritebackClean_hits::writebacks 1004693 # number of WritebackClean hits 1910system.cpu1.l2cache.WritebackClean_hits::total 1004693 # number of WritebackClean hits 1911system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28032 # number of ReadExReq hits 1912system.cpu1.l2cache.ReadExReq_hits::total 28032 # number of ReadExReq hits 1913system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 926813 # number of ReadCleanReq hits 1914system.cpu1.l2cache.ReadCleanReq_hits::total 926813 # number of ReadCleanReq hits 1915system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 106584 # number of ReadSharedReq hits 1916system.cpu1.l2cache.ReadSharedReq_hits::total 106584 # number of ReadSharedReq hits 1917system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 30076 # number of demand (read+write) hits 1918system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3135 # number of demand (read+write) hits 1919system.cpu1.l2cache.demand_hits::cpu1.inst 926813 # number of demand (read+write) hits 1920system.cpu1.l2cache.demand_hits::cpu1.data 134616 # number of demand (read+write) hits 1921system.cpu1.l2cache.demand_hits::total 1094640 # number of demand (read+write) hits 1922system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 30076 # number of overall hits 1923system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3135 # number of overall hits 1924system.cpu1.l2cache.overall_hits::cpu1.inst 926813 # number of overall hits 1925system.cpu1.l2cache.overall_hits::cpu1.data 134616 # number of overall hits 1926system.cpu1.l2cache.overall_hits::total 1094640 # number of overall hits 1927system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 622 # number of ReadReq misses 1928system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 230 # number of ReadReq misses 1929system.cpu1.l2cache.ReadReq_misses::total 852 # number of ReadReq misses 1930system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 30029 # number of UpgradeReq misses 1931system.cpu1.l2cache.UpgradeReq_misses::total 30029 # number of UpgradeReq misses 1932system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23795 # number of SCUpgradeReq misses 1933system.cpu1.l2cache.SCUpgradeReq_misses::total 23795 # number of SCUpgradeReq misses 1934system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34495 # number of ReadExReq misses 1935system.cpu1.l2cache.ReadExReq_misses::total 34495 # number of ReadExReq misses 1936system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 20063 # number of ReadCleanReq misses 1937system.cpu1.l2cache.ReadCleanReq_misses::total 20063 # number of ReadCleanReq misses 1938system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71833 # number of ReadSharedReq misses 1939system.cpu1.l2cache.ReadSharedReq_misses::total 71833 # number of ReadSharedReq misses 1940system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 622 # number of demand (read+write) misses 1941system.cpu1.l2cache.demand_misses::cpu1.itb.walker 230 # number of demand (read+write) misses 1942system.cpu1.l2cache.demand_misses::cpu1.inst 20063 # number of demand (read+write) misses 1943system.cpu1.l2cache.demand_misses::cpu1.data 106328 # number of demand (read+write) misses 1944system.cpu1.l2cache.demand_misses::total 127243 # number of demand (read+write) misses 1945system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 622 # number of overall misses 1946system.cpu1.l2cache.overall_misses::cpu1.itb.walker 230 # number of overall misses 1947system.cpu1.l2cache.overall_misses::cpu1.inst 20063 # number of overall misses 1948system.cpu1.l2cache.overall_misses::cpu1.data 106328 # number of overall misses 1949system.cpu1.l2cache.overall_misses::total 127243 # number of overall misses 1950system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14337000 # number of ReadReq miss cycles 1951system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4653500 # number of ReadReq miss cycles 1952system.cpu1.l2cache.ReadReq_miss_latency::total 18990500 # number of ReadReq miss cycles 1953system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 67215000 # number of UpgradeReq miss cycles 1954system.cpu1.l2cache.UpgradeReq_miss_latency::total 67215000 # number of UpgradeReq miss cycles 1955system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 37021000 # number of SCUpgradeReq miss cycles 1956system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 37021000 # number of SCUpgradeReq miss cycles 1957system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 366000 # number of SCUpgradeFailReq miss cycles 1958system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 366000 # number of SCUpgradeFailReq miss cycles 1959system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1366050498 # number of ReadExReq miss cycles 1960system.cpu1.l2cache.ReadExReq_miss_latency::total 1366050498 # number of ReadExReq miss cycles 1961system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 796902000 # number of ReadCleanReq miss cycles 1962system.cpu1.l2cache.ReadCleanReq_miss_latency::total 796902000 # number of ReadCleanReq miss cycles 1963system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1679934496 # number of ReadSharedReq miss cycles 1964system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1679934496 # number of ReadSharedReq miss cycles 1965system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14337000 # number of demand (read+write) miss cycles 1966system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4653500 # number of demand (read+write) miss cycles 1967system.cpu1.l2cache.demand_miss_latency::cpu1.inst 796902000 # number of demand (read+write) miss cycles 1968system.cpu1.l2cache.demand_miss_latency::cpu1.data 3045984994 # number of demand (read+write) miss cycles 1969system.cpu1.l2cache.demand_miss_latency::total 3861877494 # number of demand (read+write) miss cycles 1970system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14337000 # number of overall miss cycles 1971system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4653500 # number of overall miss cycles 1972system.cpu1.l2cache.overall_miss_latency::cpu1.inst 796902000 # number of overall miss cycles 1973system.cpu1.l2cache.overall_miss_latency::cpu1.data 3045984994 # number of overall miss cycles 1974system.cpu1.l2cache.overall_miss_latency::total 3861877494 # number of overall miss cycles 1975system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 30698 # number of ReadReq accesses(hits+misses) 1976system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3365 # number of ReadReq accesses(hits+misses) 1977system.cpu1.l2cache.ReadReq_accesses::total 34063 # number of ReadReq accesses(hits+misses) 1978system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117792 # number of WritebackDirty accesses(hits+misses) 1979system.cpu1.l2cache.WritebackDirty_accesses::total 117792 # number of WritebackDirty accesses(hits+misses) 1980system.cpu1.l2cache.WritebackClean_accesses::writebacks 1004693 # number of WritebackClean accesses(hits+misses) 1981system.cpu1.l2cache.WritebackClean_accesses::total 1004693 # number of WritebackClean accesses(hits+misses) 1982system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30029 # number of UpgradeReq accesses(hits+misses) 1983system.cpu1.l2cache.UpgradeReq_accesses::total 30029 # number of UpgradeReq accesses(hits+misses) 1984system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23795 # number of SCUpgradeReq accesses(hits+misses) 1985system.cpu1.l2cache.SCUpgradeReq_accesses::total 23795 # number of SCUpgradeReq accesses(hits+misses) 1986system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62527 # number of ReadExReq accesses(hits+misses) 1987system.cpu1.l2cache.ReadExReq_accesses::total 62527 # number of ReadExReq accesses(hits+misses) 1988system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 946876 # number of ReadCleanReq accesses(hits+misses) 1989system.cpu1.l2cache.ReadCleanReq_accesses::total 946876 # number of ReadCleanReq accesses(hits+misses) 1990system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 178417 # number of ReadSharedReq accesses(hits+misses) 1991system.cpu1.l2cache.ReadSharedReq_accesses::total 178417 # number of ReadSharedReq accesses(hits+misses) 1992system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 30698 # number of demand (read+write) accesses 1993system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3365 # number of demand (read+write) accesses 1994system.cpu1.l2cache.demand_accesses::cpu1.inst 946876 # number of demand (read+write) accesses 1995system.cpu1.l2cache.demand_accesses::cpu1.data 240944 # number of demand (read+write) accesses 1996system.cpu1.l2cache.demand_accesses::total 1221883 # number of demand (read+write) accesses 1997system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 30698 # number of overall (read+write) accesses 1998system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3365 # number of overall (read+write) accesses 1999system.cpu1.l2cache.overall_accesses::cpu1.inst 946876 # number of overall (read+write) accesses 2000system.cpu1.l2cache.overall_accesses::cpu1.data 240944 # number of overall (read+write) accesses 2001system.cpu1.l2cache.overall_accesses::total 1221883 # number of overall (read+write) accesses 2002system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020262 # miss rate for ReadReq accesses 2003system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068351 # miss rate for ReadReq accesses 2004system.cpu1.l2cache.ReadReq_miss_rate::total 0.025012 # miss rate for ReadReq accesses 2005system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2006system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2007system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2008system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2009system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.551682 # miss rate for ReadExReq accesses 2010system.cpu1.l2cache.ReadExReq_miss_rate::total 0.551682 # miss rate for ReadExReq accesses 2011system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.021189 # miss rate for ReadCleanReq accesses 2012system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.021189 # miss rate for ReadCleanReq accesses 2013system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.402613 # miss rate for ReadSharedReq accesses 2014system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.402613 # miss rate for ReadSharedReq accesses 2015system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020262 # miss rate for demand accesses 2016system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.068351 # miss rate for demand accesses 2017system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.021189 # miss rate for demand accesses 2018system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.441298 # miss rate for demand accesses 2019system.cpu1.l2cache.demand_miss_rate::total 0.104137 # miss rate for demand accesses 2020system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020262 # miss rate for overall accesses 2021system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.068351 # miss rate for overall accesses 2022system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.021189 # miss rate for overall accesses 2023system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.441298 # miss rate for overall accesses 2024system.cpu1.l2cache.overall_miss_rate::total 0.104137 # miss rate for overall accesses 2025system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23049.839228 # average ReadReq miss latency 2026system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20232.608696 # average ReadReq miss latency 2027system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22289.319249 # average ReadReq miss latency 2028system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2238.336275 # average UpgradeReq miss latency 2029system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2238.336275 # average UpgradeReq miss latency 2030system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1555.831057 # average SCUpgradeReq miss latency 2031system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1555.831057 # average SCUpgradeReq miss latency 2032system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 2033system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 2034system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39601.405943 # average ReadExReq miss latency 2035system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39601.405943 # average ReadExReq miss latency 2036system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39719.982057 # average ReadCleanReq miss latency 2037system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39719.982057 # average ReadCleanReq miss latency 2038system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23386.667632 # average ReadSharedReq miss latency 2039system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23386.667632 # average ReadSharedReq miss latency 2040system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23049.839228 # average overall miss latency 2041system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20232.608696 # average overall miss latency 2042system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39719.982057 # average overall miss latency 2043system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28647.063746 # average overall miss latency 2044system.cpu1.l2cache.demand_avg_miss_latency::total 30350.412156 # average overall miss latency 2045system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23049.839228 # average overall miss latency 2046system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20232.608696 # average overall miss latency 2047system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39719.982057 # average overall miss latency 2048system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28647.063746 # average overall miss latency 2049system.cpu1.l2cache.overall_avg_miss_latency::total 30350.412156 # average overall miss latency 2050system.cpu1.l2cache.blocked_cycles::no_mshrs 149 # number of cycles access was blocked 2051system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2052system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 2053system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2054system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 37.250000 # average number of cycles each access was blocked 2055system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2056system.cpu1.l2cache.unused_prefetches 841 # number of HardPF blocks evicted w/o reference 2057system.cpu1.l2cache.writebacks::writebacks 35327 # number of writebacks 2058system.cpu1.l2cache.writebacks::total 35327 # number of writebacks 2059system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 230 # number of ReadExReq MSHR hits 2060system.cpu1.l2cache.ReadExReq_mshr_hits::total 230 # number of ReadExReq MSHR hits 2061system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 22 # number of ReadCleanReq MSHR hits 2062system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 22 # number of ReadCleanReq MSHR hits 2063system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 84 # number of ReadSharedReq MSHR hits 2064system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 84 # number of ReadSharedReq MSHR hits 2065system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits 2066system.cpu1.l2cache.demand_mshr_hits::cpu1.data 314 # number of demand (read+write) MSHR hits 2067system.cpu1.l2cache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits 2068system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits 2069system.cpu1.l2cache.overall_mshr_hits::cpu1.data 314 # number of overall MSHR hits 2070system.cpu1.l2cache.overall_mshr_hits::total 336 # number of overall MSHR hits 2071system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 622 # number of ReadReq MSHR misses 2072system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 230 # number of ReadReq MSHR misses 2073system.cpu1.l2cache.ReadReq_mshr_misses::total 852 # number of ReadReq MSHR misses 2074system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26036 # number of HardPFReq MSHR misses 2075system.cpu1.l2cache.HardPFReq_mshr_misses::total 26036 # number of HardPFReq MSHR misses 2076system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 30029 # number of UpgradeReq MSHR misses 2077system.cpu1.l2cache.UpgradeReq_mshr_misses::total 30029 # number of UpgradeReq MSHR misses 2078system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23795 # number of SCUpgradeReq MSHR misses 2079system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23795 # number of SCUpgradeReq MSHR misses 2080system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34265 # number of ReadExReq MSHR misses 2081system.cpu1.l2cache.ReadExReq_mshr_misses::total 34265 # number of ReadExReq MSHR misses 2082system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 20041 # number of ReadCleanReq MSHR misses 2083system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 20041 # number of ReadCleanReq MSHR misses 2084system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71749 # number of ReadSharedReq MSHR misses 2085system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71749 # number of ReadSharedReq MSHR misses 2086system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 622 # number of demand (read+write) MSHR misses 2087system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 230 # number of demand (read+write) MSHR misses 2088system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20041 # number of demand (read+write) MSHR misses 2089system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106014 # number of demand (read+write) MSHR misses 2090system.cpu1.l2cache.demand_mshr_misses::total 126907 # number of demand (read+write) MSHR misses 2091system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 622 # number of overall MSHR misses 2092system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 230 # number of overall MSHR misses 2093system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20041 # number of overall MSHR misses 2094system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106014 # number of overall MSHR misses 2095system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26036 # number of overall MSHR misses 2096system.cpu1.l2cache.overall_mshr_misses::total 152943 # number of overall MSHR misses 2097system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2098system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable 2099system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14536 # number of ReadReq MSHR uncacheable 2100system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11758 # number of WriteReq MSHR uncacheable 2101system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11758 # number of WriteReq MSHR uncacheable 2102system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2103system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26182 # number of overall MSHR uncacheable misses 2104system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26294 # number of overall MSHR uncacheable misses 2105system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of ReadReq MSHR miss cycles 2106system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3273500 # number of ReadReq MSHR miss cycles 2107system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 13878500 # number of ReadReq MSHR miss cycles 2108system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1006636893 # number of HardPFReq MSHR miss cycles 2109system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1006636893 # number of HardPFReq MSHR miss cycles 2110system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 505691500 # number of UpgradeReq MSHR miss cycles 2111system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 505691500 # number of UpgradeReq MSHR miss cycles 2112system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 380458500 # number of SCUpgradeReq MSHR miss cycles 2113system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 380458500 # number of SCUpgradeReq MSHR miss cycles 2114system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 318000 # number of SCUpgradeFailReq MSHR miss cycles 2115system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 318000 # number of SCUpgradeFailReq MSHR miss cycles 2116system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1135025000 # number of ReadExReq MSHR miss cycles 2117system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1135025000 # number of ReadExReq MSHR miss cycles 2118system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 675844000 # number of ReadCleanReq MSHR miss cycles 2119system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 675844000 # number of ReadCleanReq MSHR miss cycles 2120system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1246810496 # number of ReadSharedReq MSHR miss cycles 2121system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1246810496 # number of ReadSharedReq MSHR miss cycles 2122system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of demand (read+write) MSHR miss cycles 2123system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3273500 # number of demand (read+write) MSHR miss cycles 2124system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 675844000 # number of demand (read+write) MSHR miss cycles 2125system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2381835496 # number of demand (read+write) MSHR miss cycles 2126system.cpu1.l2cache.demand_mshr_miss_latency::total 3071557996 # number of demand (read+write) MSHR miss cycles 2127system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of overall MSHR miss cycles 2128system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3273500 # number of overall MSHR miss cycles 2129system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 675844000 # number of overall MSHR miss cycles 2130system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2381835496 # number of overall MSHR miss cycles 2131system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1006636893 # number of overall MSHR miss cycles 2132system.cpu1.l2cache.overall_mshr_miss_latency::total 4078194889 # number of overall MSHR miss cycles 2133system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9578500 # number of ReadReq MSHR uncacheable cycles 2134system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2364337500 # number of ReadReq MSHR uncacheable cycles 2135system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2373916000 # number of ReadReq MSHR uncacheable cycles 2136system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9578500 # number of overall MSHR uncacheable cycles 2137system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2364337500 # number of overall MSHR uncacheable cycles 2138system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2373916000 # number of overall MSHR uncacheable cycles 2139system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for ReadReq accesses 2140system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for ReadReq accesses 2141system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025012 # mshr miss rate for ReadReq accesses 2142system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2143system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2144system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2145system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2146system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2147system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2148system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548003 # mshr miss rate for ReadExReq accesses 2149system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548003 # mshr miss rate for ReadExReq accesses 2150system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for ReadCleanReq accesses 2151system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.021165 # mshr miss rate for ReadCleanReq accesses 2152system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402142 # mshr miss rate for ReadSharedReq accesses 2153system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402142 # mshr miss rate for ReadSharedReq accesses 2154system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for demand accesses 2155system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for demand accesses 2156system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for demand accesses 2157system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for demand accesses 2158system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103862 # mshr miss rate for demand accesses 2159system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for overall accesses 2160system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for overall accesses 2161system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for overall accesses 2162system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for overall accesses 2163system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2164system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125170 # mshr miss rate for overall accesses 2165system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average ReadReq mshr miss latency 2166system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average ReadReq mshr miss latency 2167system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16289.319249 # average ReadReq mshr miss latency 2168system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average HardPFReq mshr miss latency 2169system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38663.269819 # average HardPFReq mshr miss latency 2170system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16840.104566 # average UpgradeReq mshr miss latency 2171system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16840.104566 # average UpgradeReq mshr miss latency 2172system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15989.010296 # average SCUpgradeReq mshr miss latency 2173system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15989.010296 # average SCUpgradeReq mshr miss latency 2174system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2175system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2176system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33124.908799 # average ReadExReq mshr miss latency 2177system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33124.908799 # average ReadExReq mshr miss latency 2178system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average ReadCleanReq mshr miss latency 2179system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33723.067711 # average ReadCleanReq mshr miss latency 2180system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17377.391964 # average ReadSharedReq mshr miss latency 2181system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17377.391964 # average ReadSharedReq mshr miss latency 2182system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency 2183system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency 2184system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency 2185system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency 2186system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24203.219649 # average overall mshr miss latency 2187system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency 2188system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency 2189system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency 2190system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency 2191system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average overall mshr miss latency 2192system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26664.802502 # average overall mshr miss latency 2193system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average ReadReq mshr uncacheable latency 2194system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163916.909318 # average ReadReq mshr uncacheable latency 2195system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163312.878371 # average ReadReq mshr uncacheable latency 2196system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average overall mshr uncacheable latency 2197system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90303.930181 # average overall mshr uncacheable latency 2198system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90283.562790 # average overall mshr uncacheable latency 2199system.cpu1.toL2Bus.snoop_filter.tot_requests 2394243 # Total number of requests made to the snoop filter. 2200system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1206431 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2201system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20164 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2202system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter. 2203system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2204system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2205system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2206system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution 2207system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution 2208system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution 2209system.cpu1.toL2Bus.trans_dist::WriteResp 11758 # Transaction distribution 2210system.cpu1.toL2Bus.trans_dist::WritebackDirty 154274 # Transaction distribution 2211system.cpu1.toL2Bus.trans_dist::WritebackClean 1024857 # Transaction distribution 2212system.cpu1.toL2Bus.trans_dist::CleanEvict 118852 # Transaction distribution 2213system.cpu1.toL2Bus.trans_dist::HardPFReq 31456 # Transaction distribution 2214system.cpu1.toL2Bus.trans_dist::UpgradeReq 74303 # Transaction distribution 2215system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42261 # Transaction distribution 2216system.cpu1.toL2Bus.trans_dist::UpgradeResp 86315 # Transaction distribution 2217system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 2218system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution 2219system.cpu1.toL2Bus.trans_dist::ReadExReq 69975 # Transaction distribution 2220system.cpu1.toL2Bus.trans_dist::ReadExResp 67112 # Transaction distribution 2221system.cpu1.toL2Bus.trans_dist::ReadCleanReq 946876 # Transaction distribution 2222system.cpu1.toL2Bus.trans_dist::ReadSharedReq 270105 # Transaction distribution 2223system.cpu1.toL2Bus.trans_dist::InvalidateReq 65 # Transaction distribution 2224system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2840340 # Packet count per connected master and slave (bytes) 2225system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 913098 # Packet count per connected master and slave (bytes) 2226system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8024 # Packet count per connected master and slave (bytes) 2227system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64559 # Packet count per connected master and slave (bytes) 2228system.cpu1.toL2Bus.pkt_count::total 3826021 # Packet count per connected master and slave (bytes) 2229system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121174528 # Cumulative packet size per connected master and slave (bytes) 2230system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30799564 # Cumulative packet size per connected master and slave (bytes) 2231system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13460 # Cumulative packet size per connected master and slave (bytes) 2232system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122792 # Cumulative packet size per connected master and slave (bytes) 2233system.cpu1.toL2Bus.pkt_size::total 152110344 # Cumulative packet size per connected master and slave (bytes) 2234system.cpu1.toL2Bus.snoops 428107 # Total snoops (count) 2235system.cpu1.toL2Bus.snoop_fanout::samples 1655199 # Request fanout histogram 2236system.cpu1.toL2Bus.snoop_fanout::mean 0.135380 # Request fanout histogram 2237system.cpu1.toL2Bus.snoop_fanout::stdev 0.345288 # Request fanout histogram 2238system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2239system.cpu1.toL2Bus.snoop_fanout::0 1432915 86.57% 86.57% # Request fanout histogram 2240system.cpu1.toL2Bus.snoop_fanout::1 220487 13.32% 99.89% # Request fanout histogram 2241system.cpu1.toL2Bus.snoop_fanout::2 1797 0.11% 100.00% # Request fanout histogram 2242system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2243system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2244system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2245system.cpu1.toL2Bus.snoop_fanout::total 1655199 # Request fanout histogram 2246system.cpu1.toL2Bus.reqLayer0.occupancy 2373087991 # Layer occupancy (ticks) 2247system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2248system.cpu1.toL2Bus.snoopLayer0.occupancy 79906669 # Layer occupancy (ticks) 2249system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2250system.cpu1.toL2Bus.respLayer0.occupancy 1420645672 # Layer occupancy (ticks) 2251system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2252system.cpu1.toL2Bus.respLayer1.occupancy 410383006 # Layer occupancy (ticks) 2253system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2254system.cpu1.toL2Bus.respLayer2.occupancy 4659998 # Layer occupancy (ticks) 2255system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2256system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks) 2257system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2258system.iobus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2259system.iobus.trans_dist::ReadReq 31003 # Transaction distribution 2260system.iobus.trans_dist::ReadResp 31003 # Transaction distribution 2261system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2262system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2263system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2264system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2265system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2266system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2267system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2268system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2269system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2270system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2271system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2272system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2273system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2274system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2275system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2276system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2277system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2278system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2279system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2280system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2281system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2282system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2283system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 2284system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 2285system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) 2286system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2287system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2288system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2289system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2290system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2291system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2292system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2293system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2294system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2295system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2296system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2297system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2298system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2299system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2300system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2301system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2302system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2303system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2304system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2305system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2306system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 2307system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 2308system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) 2309system.iobus.reqLayer0.occupancy 48463001 # Layer occupancy (ticks) 2310system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2311system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) 2312system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2313system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) 2314system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2315system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) 2316system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2317system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) 2318system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2319system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) 2320system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2321system.iobus.reqLayer8.occupancy 574000 # Layer occupancy (ticks) 2322system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2323system.iobus.reqLayer10.occupancy 18000 # Layer occupancy (ticks) 2324system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2325system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) 2326system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2327system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2328system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2329system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 2330system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2331system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) 2332system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2333system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2334system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2335system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 2336system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2337system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2338system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2339system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) 2340system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2341system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2342system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2343system.iobus.reqLayer23.occupancy 6138000 # Layer occupancy (ticks) 2344system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2345system.iobus.reqLayer24.occupancy 33143500 # Layer occupancy (ticks) 2346system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2347system.iobus.reqLayer25.occupancy 187679851 # Layer occupancy (ticks) 2348system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2349system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2350system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2351system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) 2352system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2353system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2354system.iocache.tags.replacements 36449 # number of replacements 2355system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use 2356system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2357system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. 2358system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2359system.iocache.tags.warmup_cycle 271175186000 # Cycle when the warmup percentage was hit. 2360system.iocache.tags.occ_blocks::realview.ide 14.476064 # Average occupied blocks per requestor 2361system.iocache.tags.occ_percent::realview.ide 0.904754 # Average percentage of cache occupancy 2362system.iocache.tags.occ_percent::total 0.904754 # Average percentage of cache occupancy 2363system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2364system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2365system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2366system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2367system.iocache.tags.data_accesses 328203 # Number of data accesses 2368system.iocache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2369system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2370system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2371system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2372system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2373system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses 2374system.iocache.demand_misses::total 36467 # number of demand (read+write) misses 2375system.iocache.overall_misses::realview.ide 36467 # number of overall misses 2376system.iocache.overall_misses::total 36467 # number of overall misses 2377system.iocache.ReadReq_miss_latency::realview.ide 31712877 # number of ReadReq miss cycles 2378system.iocache.ReadReq_miss_latency::total 31712877 # number of ReadReq miss cycles 2379system.iocache.WriteLineReq_miss_latency::realview.ide 4301380974 # number of WriteLineReq miss cycles 2380system.iocache.WriteLineReq_miss_latency::total 4301380974 # number of WriteLineReq miss cycles 2381system.iocache.demand_miss_latency::realview.ide 4333093851 # number of demand (read+write) miss cycles 2382system.iocache.demand_miss_latency::total 4333093851 # number of demand (read+write) miss cycles 2383system.iocache.overall_miss_latency::realview.ide 4333093851 # number of overall miss cycles 2384system.iocache.overall_miss_latency::total 4333093851 # number of overall miss cycles 2385system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2386system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2387system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2388system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2389system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses 2390system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses 2391system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses 2392system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses 2393system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2394system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2395system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2396system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2397system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2398system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2399system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2400system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2401system.iocache.ReadReq_avg_miss_latency::realview.ide 130505.666667 # average ReadReq miss latency 2402system.iocache.ReadReq_avg_miss_latency::total 130505.666667 # average ReadReq miss latency 2403system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118743.953567 # average WriteLineReq miss latency 2404system.iocache.WriteLineReq_avg_miss_latency::total 118743.953567 # average WriteLineReq miss latency 2405system.iocache.demand_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency 2406system.iocache.demand_avg_miss_latency::total 118822.328434 # average overall miss latency 2407system.iocache.overall_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency 2408system.iocache.overall_avg_miss_latency::total 118822.328434 # average overall miss latency 2409system.iocache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked 2410system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2411system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked 2412system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2413system.iocache.avg_blocked_cycles::no_mshrs 16.888889 # average number of cycles each access was blocked 2414system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2415system.iocache.writebacks::writebacks 36206 # number of writebacks 2416system.iocache.writebacks::total 36206 # number of writebacks 2417system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2418system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2419system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2420system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2421system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses 2422system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses 2423system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses 2424system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses 2425system.iocache.ReadReq_mshr_miss_latency::realview.ide 19562877 # number of ReadReq MSHR miss cycles 2426system.iocache.ReadReq_mshr_miss_latency::total 19562877 # number of ReadReq MSHR miss cycles 2427system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2487893822 # number of WriteLineReq MSHR miss cycles 2428system.iocache.WriteLineReq_mshr_miss_latency::total 2487893822 # number of WriteLineReq MSHR miss cycles 2429system.iocache.demand_mshr_miss_latency::realview.ide 2507456699 # number of demand (read+write) MSHR miss cycles 2430system.iocache.demand_mshr_miss_latency::total 2507456699 # number of demand (read+write) MSHR miss cycles 2431system.iocache.overall_mshr_miss_latency::realview.ide 2507456699 # number of overall MSHR miss cycles 2432system.iocache.overall_mshr_miss_latency::total 2507456699 # number of overall MSHR miss cycles 2433system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2434system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2435system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2436system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2437system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2438system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2439system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2440system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2441system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80505.666667 # average ReadReq mshr miss latency 2442system.iocache.ReadReq_avg_mshr_miss_latency::total 80505.666667 # average ReadReq mshr miss latency 2443system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68680.814432 # average WriteLineReq mshr miss latency 2444system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68680.814432 # average WriteLineReq mshr miss latency 2445system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency 2446system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency 2447system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency 2448system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency 2449system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2450system.l2c.tags.replacements 131721 # number of replacements 2451system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use 2452system.l2c.tags.total_refs 480965 # Total number of references to valid blocks. 2453system.l2c.tags.sampled_refs 195649 # Sample count of references to valid blocks. 2454system.l2c.tags.avg_refs 2.458305 # Average number of references to valid blocks. 2455system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2456system.l2c.tags.occ_blocks::writebacks 13508.912510 # Average occupied blocks per requestor 2457system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.990696 # Average occupied blocks per requestor 2458system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038635 # Average occupied blocks per requestor 2459system.l2c.tags.occ_blocks::cpu0.inst 9208.691215 # Average occupied blocks per requestor 2460system.l2c.tags.occ_blocks::cpu0.data 2842.970469 # Average occupied blocks per requestor 2461system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33089.520800 # Average occupied blocks per requestor 2462system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.769626 # Average occupied blocks per requestor 2463system.l2c.tags.occ_blocks::cpu1.inst 2121.922145 # Average occupied blocks per requestor 2464system.l2c.tags.occ_blocks::cpu1.data 593.095570 # Average occupied blocks per requestor 2465system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1670.405219 # Average occupied blocks per requestor 2466system.l2c.tags.occ_percent::writebacks 0.206130 # Average percentage of cache occupancy 2467system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001144 # Average percentage of cache occupancy 2468system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2469system.l2c.tags.occ_percent::cpu0.inst 0.140513 # Average percentage of cache occupancy 2470system.l2c.tags.occ_percent::cpu0.data 0.043380 # Average percentage of cache occupancy 2471system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.504906 # Average percentage of cache occupancy 2472system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy 2473system.l2c.tags.occ_percent::cpu1.inst 0.032378 # Average percentage of cache occupancy 2474system.l2c.tags.occ_percent::cpu1.data 0.009050 # Average percentage of cache occupancy 2475system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025488 # Average percentage of cache occupancy 2476system.l2c.tags.occ_percent::total 0.963124 # Average percentage of cache occupancy 2477system.l2c.tags.occ_task_id_blocks::1022 27523 # Occupied blocks per task id 2478system.l2c.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id 2479system.l2c.tags.occ_task_id_blocks::1024 36326 # Occupied blocks per task id 2480system.l2c.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 2481system.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id 2482system.l2c.tags.age_task_id_blocks_1022::3 4354 # Occupied blocks per task id 2483system.l2c.tags.age_task_id_blocks_1022::4 23032 # Occupied blocks per task id 2484system.l2c.tags.age_task_id_blocks_1023::4 79 # Occupied blocks per task id 2485system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 2486system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 2487system.l2c.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id 2488system.l2c.tags.age_task_id_blocks_1024::3 3689 # Occupied blocks per task id 2489system.l2c.tags.age_task_id_blocks_1024::4 32199 # Occupied blocks per task id 2490system.l2c.tags.occ_task_id_percent::1022 0.419968 # Percentage of cache occupancy per task id 2491system.l2c.tags.occ_task_id_percent::1023 0.001205 # Percentage of cache occupancy per task id 2492system.l2c.tags.occ_task_id_percent::1024 0.554291 # Percentage of cache occupancy per task id 2493system.l2c.tags.tag_accesses 6440622 # Number of tag accesses 2494system.l2c.tags.data_accesses 6440622 # Number of data accesses 2495system.l2c.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2496system.l2c.WritebackDirty_hits::writebacks 269250 # number of WritebackDirty hits 2497system.l2c.WritebackDirty_hits::total 269250 # number of WritebackDirty hits 2498system.l2c.UpgradeReq_hits::cpu0.data 33826 # number of UpgradeReq hits 2499system.l2c.UpgradeReq_hits::cpu1.data 2712 # number of UpgradeReq hits 2500system.l2c.UpgradeReq_hits::total 36538 # number of UpgradeReq hits 2501system.l2c.SCUpgradeReq_hits::cpu0.data 2202 # number of SCUpgradeReq hits 2502system.l2c.SCUpgradeReq_hits::cpu1.data 1074 # number of SCUpgradeReq hits 2503system.l2c.SCUpgradeReq_hits::total 3276 # number of SCUpgradeReq hits 2504system.l2c.ReadExReq_hits::cpu0.data 4226 # number of ReadExReq hits 2505system.l2c.ReadExReq_hits::cpu1.data 1659 # number of ReadExReq hits 2506system.l2c.ReadExReq_hits::total 5885 # number of ReadExReq hits 2507system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 466 # number of ReadSharedReq hits 2508system.l2c.ReadSharedReq_hits::cpu0.itb.walker 69 # number of ReadSharedReq hits 2509system.l2c.ReadSharedReq_hits::cpu0.inst 46028 # number of ReadSharedReq hits 2510system.l2c.ReadSharedReq_hits::cpu0.data 50195 # number of ReadSharedReq hits 2511system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48669 # number of ReadSharedReq hits 2512system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 136 # number of ReadSharedReq hits 2513system.l2c.ReadSharedReq_hits::cpu1.itb.walker 26 # number of ReadSharedReq hits 2514system.l2c.ReadSharedReq_hits::cpu1.inst 16745 # number of ReadSharedReq hits 2515system.l2c.ReadSharedReq_hits::cpu1.data 10025 # number of ReadSharedReq hits 2516system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5491 # number of ReadSharedReq hits 2517system.l2c.ReadSharedReq_hits::total 177850 # number of ReadSharedReq hits 2518system.l2c.demand_hits::cpu0.dtb.walker 466 # number of demand (read+write) hits 2519system.l2c.demand_hits::cpu0.itb.walker 69 # number of demand (read+write) hits 2520system.l2c.demand_hits::cpu0.inst 46028 # number of demand (read+write) hits 2521system.l2c.demand_hits::cpu0.data 54421 # number of demand (read+write) hits 2522system.l2c.demand_hits::cpu0.l2cache.prefetcher 48669 # number of demand (read+write) hits 2523system.l2c.demand_hits::cpu1.dtb.walker 136 # number of demand (read+write) hits 2524system.l2c.demand_hits::cpu1.itb.walker 26 # number of demand (read+write) hits 2525system.l2c.demand_hits::cpu1.inst 16745 # number of demand (read+write) hits 2526system.l2c.demand_hits::cpu1.data 11684 # number of demand (read+write) hits 2527system.l2c.demand_hits::cpu1.l2cache.prefetcher 5491 # number of demand (read+write) hits 2528system.l2c.demand_hits::total 183735 # number of demand (read+write) hits 2529system.l2c.overall_hits::cpu0.dtb.walker 466 # number of overall hits 2530system.l2c.overall_hits::cpu0.itb.walker 69 # number of overall hits 2531system.l2c.overall_hits::cpu0.inst 46028 # number of overall hits 2532system.l2c.overall_hits::cpu0.data 54421 # number of overall hits 2533system.l2c.overall_hits::cpu0.l2cache.prefetcher 48669 # number of overall hits 2534system.l2c.overall_hits::cpu1.dtb.walker 136 # number of overall hits 2535system.l2c.overall_hits::cpu1.itb.walker 26 # number of overall hits 2536system.l2c.overall_hits::cpu1.inst 16745 # number of overall hits 2537system.l2c.overall_hits::cpu1.data 11684 # number of overall hits 2538system.l2c.overall_hits::cpu1.l2cache.prefetcher 5491 # number of overall hits 2539system.l2c.overall_hits::total 183735 # number of overall hits 2540system.l2c.UpgradeReq_misses::cpu0.data 9873 # number of UpgradeReq misses 2541system.l2c.UpgradeReq_misses::cpu1.data 3017 # number of UpgradeReq misses 2542system.l2c.UpgradeReq_misses::total 12890 # number of UpgradeReq misses 2543system.l2c.SCUpgradeReq_misses::cpu0.data 747 # number of SCUpgradeReq misses 2544system.l2c.SCUpgradeReq_misses::cpu1.data 1385 # number of SCUpgradeReq misses 2545system.l2c.SCUpgradeReq_misses::total 2132 # number of SCUpgradeReq misses 2546system.l2c.ReadExReq_misses::cpu0.data 11157 # number of ReadExReq misses 2547system.l2c.ReadExReq_misses::cpu1.data 8253 # number of ReadExReq misses 2548system.l2c.ReadExReq_misses::total 19410 # number of ReadExReq misses 2549system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 117 # number of ReadSharedReq misses 2550system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses 2551system.l2c.ReadSharedReq_misses::cpu0.inst 22311 # number of ReadSharedReq misses 2552system.l2c.ReadSharedReq_misses::cpu0.data 9661 # number of ReadSharedReq misses 2553system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130681 # number of ReadSharedReq misses 2554system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 13 # number of ReadSharedReq misses 2555system.l2c.ReadSharedReq_misses::cpu1.inst 3296 # number of ReadSharedReq misses 2556system.l2c.ReadSharedReq_misses::cpu1.data 1822 # number of ReadSharedReq misses 2557system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6980 # number of ReadSharedReq misses 2558system.l2c.ReadSharedReq_misses::total 174882 # number of ReadSharedReq misses 2559system.l2c.demand_misses::cpu0.dtb.walker 117 # number of demand (read+write) misses 2560system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2561system.l2c.demand_misses::cpu0.inst 22311 # number of demand (read+write) misses 2562system.l2c.demand_misses::cpu0.data 20818 # number of demand (read+write) misses 2563system.l2c.demand_misses::cpu0.l2cache.prefetcher 130681 # number of demand (read+write) misses 2564system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses 2565system.l2c.demand_misses::cpu1.inst 3296 # number of demand (read+write) misses 2566system.l2c.demand_misses::cpu1.data 10075 # number of demand (read+write) misses 2567system.l2c.demand_misses::cpu1.l2cache.prefetcher 6980 # number of demand (read+write) misses 2568system.l2c.demand_misses::total 194292 # number of demand (read+write) misses 2569system.l2c.overall_misses::cpu0.dtb.walker 117 # number of overall misses 2570system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2571system.l2c.overall_misses::cpu0.inst 22311 # number of overall misses 2572system.l2c.overall_misses::cpu0.data 20818 # number of overall misses 2573system.l2c.overall_misses::cpu0.l2cache.prefetcher 130681 # number of overall misses 2574system.l2c.overall_misses::cpu1.dtb.walker 13 # number of overall misses 2575system.l2c.overall_misses::cpu1.inst 3296 # number of overall misses 2576system.l2c.overall_misses::cpu1.data 10075 # number of overall misses 2577system.l2c.overall_misses::cpu1.l2cache.prefetcher 6980 # number of overall misses 2578system.l2c.overall_misses::total 194292 # number of overall misses 2579system.l2c.UpgradeReq_miss_latency::cpu0.data 11941000 # number of UpgradeReq miss cycles 2580system.l2c.UpgradeReq_miss_latency::cpu1.data 3314000 # number of UpgradeReq miss cycles 2581system.l2c.UpgradeReq_miss_latency::total 15255000 # number of UpgradeReq miss cycles 2582system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1661000 # number of SCUpgradeReq miss cycles 2583system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2074000 # number of SCUpgradeReq miss cycles 2584system.l2c.SCUpgradeReq_miss_latency::total 3735000 # number of SCUpgradeReq miss cycles 2585system.l2c.ReadExReq_miss_latency::cpu0.data 1109421000 # number of ReadExReq miss cycles 2586system.l2c.ReadExReq_miss_latency::cpu1.data 686062500 # number of ReadExReq miss cycles 2587system.l2c.ReadExReq_miss_latency::total 1795483500 # number of ReadExReq miss cycles 2588system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10072500 # number of ReadSharedReq miss cycles 2589system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 84000 # number of ReadSharedReq miss cycles 2590system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1812545500 # number of ReadSharedReq miss cycles 2591system.l2c.ReadSharedReq_miss_latency::cpu0.data 856898000 # number of ReadSharedReq miss cycles 2592system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13156370360 # number of ReadSharedReq miss cycles 2593system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1285500 # number of ReadSharedReq miss cycles 2594system.l2c.ReadSharedReq_miss_latency::cpu1.inst 273248000 # number of ReadSharedReq miss cycles 2595system.l2c.ReadSharedReq_miss_latency::cpu1.data 169259000 # number of ReadSharedReq miss cycles 2596system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 891916725 # number of ReadSharedReq miss cycles 2597system.l2c.ReadSharedReq_miss_latency::total 17171679585 # number of ReadSharedReq miss cycles 2598system.l2c.demand_miss_latency::cpu0.dtb.walker 10072500 # number of demand (read+write) miss cycles 2599system.l2c.demand_miss_latency::cpu0.itb.walker 84000 # number of demand (read+write) miss cycles 2600system.l2c.demand_miss_latency::cpu0.inst 1812545500 # number of demand (read+write) miss cycles 2601system.l2c.demand_miss_latency::cpu0.data 1966319000 # number of demand (read+write) miss cycles 2602system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13156370360 # number of demand (read+write) miss cycles 2603system.l2c.demand_miss_latency::cpu1.dtb.walker 1285500 # number of demand (read+write) miss cycles 2604system.l2c.demand_miss_latency::cpu1.inst 273248000 # number of demand (read+write) miss cycles 2605system.l2c.demand_miss_latency::cpu1.data 855321500 # number of demand (read+write) miss cycles 2606system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 891916725 # number of demand (read+write) miss cycles 2607system.l2c.demand_miss_latency::total 18967163085 # number of demand (read+write) miss cycles 2608system.l2c.overall_miss_latency::cpu0.dtb.walker 10072500 # number of overall miss cycles 2609system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles 2610system.l2c.overall_miss_latency::cpu0.inst 1812545500 # number of overall miss cycles 2611system.l2c.overall_miss_latency::cpu0.data 1966319000 # number of overall miss cycles 2612system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13156370360 # number of overall miss cycles 2613system.l2c.overall_miss_latency::cpu1.dtb.walker 1285500 # number of overall miss cycles 2614system.l2c.overall_miss_latency::cpu1.inst 273248000 # number of overall miss cycles 2615system.l2c.overall_miss_latency::cpu1.data 855321500 # number of overall miss cycles 2616system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 891916725 # number of overall miss cycles 2617system.l2c.overall_miss_latency::total 18967163085 # number of overall miss cycles 2618system.l2c.WritebackDirty_accesses::writebacks 269250 # number of WritebackDirty accesses(hits+misses) 2619system.l2c.WritebackDirty_accesses::total 269250 # number of WritebackDirty accesses(hits+misses) 2620system.l2c.UpgradeReq_accesses::cpu0.data 43699 # number of UpgradeReq accesses(hits+misses) 2621system.l2c.UpgradeReq_accesses::cpu1.data 5729 # number of UpgradeReq accesses(hits+misses) 2622system.l2c.UpgradeReq_accesses::total 49428 # number of UpgradeReq accesses(hits+misses) 2623system.l2c.SCUpgradeReq_accesses::cpu0.data 2949 # number of SCUpgradeReq accesses(hits+misses) 2624system.l2c.SCUpgradeReq_accesses::cpu1.data 2459 # number of SCUpgradeReq accesses(hits+misses) 2625system.l2c.SCUpgradeReq_accesses::total 5408 # number of SCUpgradeReq accesses(hits+misses) 2626system.l2c.ReadExReq_accesses::cpu0.data 15383 # number of ReadExReq accesses(hits+misses) 2627system.l2c.ReadExReq_accesses::cpu1.data 9912 # number of ReadExReq accesses(hits+misses) 2628system.l2c.ReadExReq_accesses::total 25295 # number of ReadExReq accesses(hits+misses) 2629system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 583 # number of ReadSharedReq accesses(hits+misses) 2630system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) 2631system.l2c.ReadSharedReq_accesses::cpu0.inst 68339 # number of ReadSharedReq accesses(hits+misses) 2632system.l2c.ReadSharedReq_accesses::cpu0.data 59856 # number of ReadSharedReq accesses(hits+misses) 2633system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179350 # number of ReadSharedReq accesses(hits+misses) 2634system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 149 # number of ReadSharedReq accesses(hits+misses) 2635system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 26 # number of ReadSharedReq accesses(hits+misses) 2636system.l2c.ReadSharedReq_accesses::cpu1.inst 20041 # number of ReadSharedReq accesses(hits+misses) 2637system.l2c.ReadSharedReq_accesses::cpu1.data 11847 # number of ReadSharedReq accesses(hits+misses) 2638system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 12471 # number of ReadSharedReq accesses(hits+misses) 2639system.l2c.ReadSharedReq_accesses::total 352732 # number of ReadSharedReq accesses(hits+misses) 2640system.l2c.demand_accesses::cpu0.dtb.walker 583 # number of demand (read+write) accesses 2641system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses 2642system.l2c.demand_accesses::cpu0.inst 68339 # number of demand (read+write) accesses 2643system.l2c.demand_accesses::cpu0.data 75239 # number of demand (read+write) accesses 2644system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179350 # number of demand (read+write) accesses 2645system.l2c.demand_accesses::cpu1.dtb.walker 149 # number of demand (read+write) accesses 2646system.l2c.demand_accesses::cpu1.itb.walker 26 # number of demand (read+write) accesses 2647system.l2c.demand_accesses::cpu1.inst 20041 # number of demand (read+write) accesses 2648system.l2c.demand_accesses::cpu1.data 21759 # number of demand (read+write) accesses 2649system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12471 # number of demand (read+write) accesses 2650system.l2c.demand_accesses::total 378027 # number of demand (read+write) accesses 2651system.l2c.overall_accesses::cpu0.dtb.walker 583 # number of overall (read+write) accesses 2652system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses 2653system.l2c.overall_accesses::cpu0.inst 68339 # number of overall (read+write) accesses 2654system.l2c.overall_accesses::cpu0.data 75239 # number of overall (read+write) accesses 2655system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179350 # number of overall (read+write) accesses 2656system.l2c.overall_accesses::cpu1.dtb.walker 149 # number of overall (read+write) accesses 2657system.l2c.overall_accesses::cpu1.itb.walker 26 # number of overall (read+write) accesses 2658system.l2c.overall_accesses::cpu1.inst 20041 # number of overall (read+write) accesses 2659system.l2c.overall_accesses::cpu1.data 21759 # number of overall (read+write) accesses 2660system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12471 # number of overall (read+write) accesses 2661system.l2c.overall_accesses::total 378027 # number of overall (read+write) accesses 2662system.l2c.UpgradeReq_miss_rate::cpu0.data 0.225932 # miss rate for UpgradeReq accesses 2663system.l2c.UpgradeReq_miss_rate::cpu1.data 0.526619 # miss rate for UpgradeReq accesses 2664system.l2c.UpgradeReq_miss_rate::total 0.260783 # miss rate for UpgradeReq accesses 2665system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.253306 # miss rate for SCUpgradeReq accesses 2666system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.563237 # miss rate for SCUpgradeReq accesses 2667system.l2c.SCUpgradeReq_miss_rate::total 0.394231 # miss rate for SCUpgradeReq accesses 2668system.l2c.ReadExReq_miss_rate::cpu0.data 0.725281 # miss rate for ReadExReq accesses 2669system.l2c.ReadExReq_miss_rate::cpu1.data 0.832627 # miss rate for ReadExReq accesses 2670system.l2c.ReadExReq_miss_rate::total 0.767345 # miss rate for ReadExReq accesses 2671system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.200686 # miss rate for ReadSharedReq accesses 2672system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.014286 # miss rate for ReadSharedReq accesses 2673system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.326475 # miss rate for ReadSharedReq accesses 2674system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.161404 # miss rate for ReadSharedReq accesses 2675system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.728637 # miss rate for ReadSharedReq accesses 2676system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.087248 # miss rate for ReadSharedReq accesses 2677system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.164463 # miss rate for ReadSharedReq accesses 2678system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.153794 # miss rate for ReadSharedReq accesses 2679system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.559699 # miss rate for ReadSharedReq accesses 2680system.l2c.ReadSharedReq_miss_rate::total 0.495793 # miss rate for ReadSharedReq accesses 2681system.l2c.demand_miss_rate::cpu0.dtb.walker 0.200686 # miss rate for demand accesses 2682system.l2c.demand_miss_rate::cpu0.itb.walker 0.014286 # miss rate for demand accesses 2683system.l2c.demand_miss_rate::cpu0.inst 0.326475 # miss rate for demand accesses 2684system.l2c.demand_miss_rate::cpu0.data 0.276692 # miss rate for demand accesses 2685system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.728637 # miss rate for demand accesses 2686system.l2c.demand_miss_rate::cpu1.dtb.walker 0.087248 # miss rate for demand accesses 2687system.l2c.demand_miss_rate::cpu1.inst 0.164463 # miss rate for demand accesses 2688system.l2c.demand_miss_rate::cpu1.data 0.463027 # miss rate for demand accesses 2689system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.559699 # miss rate for demand accesses 2690system.l2c.demand_miss_rate::total 0.513963 # miss rate for demand accesses 2691system.l2c.overall_miss_rate::cpu0.dtb.walker 0.200686 # miss rate for overall accesses 2692system.l2c.overall_miss_rate::cpu0.itb.walker 0.014286 # miss rate for overall accesses 2693system.l2c.overall_miss_rate::cpu0.inst 0.326475 # miss rate for overall accesses 2694system.l2c.overall_miss_rate::cpu0.data 0.276692 # miss rate for overall accesses 2695system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.728637 # miss rate for overall accesses 2696system.l2c.overall_miss_rate::cpu1.dtb.walker 0.087248 # miss rate for overall accesses 2697system.l2c.overall_miss_rate::cpu1.inst 0.164463 # miss rate for overall accesses 2698system.l2c.overall_miss_rate::cpu1.data 0.463027 # miss rate for overall accesses 2699system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.559699 # miss rate for overall accesses 2700system.l2c.overall_miss_rate::total 0.513963 # miss rate for overall accesses 2701system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1209.460144 # average UpgradeReq miss latency 2702system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1098.442161 # average UpgradeReq miss latency 2703system.l2c.UpgradeReq_avg_miss_latency::total 1183.475562 # average UpgradeReq miss latency 2704system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2223.560910 # average SCUpgradeReq miss latency 2705system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1497.472924 # average SCUpgradeReq miss latency 2706system.l2c.SCUpgradeReq_avg_miss_latency::total 1751.876173 # average SCUpgradeReq miss latency 2707system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99437.214305 # average ReadExReq miss latency 2708system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83128.862232 # average ReadExReq miss latency 2709system.l2c.ReadExReq_avg_miss_latency::total 92503.013910 # average ReadExReq miss latency 2710system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86089.743590 # average ReadSharedReq miss latency 2711system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 84000 # average ReadSharedReq miss latency 2712system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81239.993725 # average ReadSharedReq miss latency 2713system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88696.615257 # average ReadSharedReq miss latency 2714system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 100675.464375 # average ReadSharedReq miss latency 2715system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 98884.615385 # average ReadSharedReq miss latency 2716system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82902.912621 # average ReadSharedReq miss latency 2717system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92897.365532 # average ReadSharedReq miss latency 2718system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 127781.765759 # average ReadSharedReq miss latency 2719system.l2c.ReadSharedReq_avg_miss_latency::total 98190.091519 # average ReadSharedReq miss latency 2720system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86089.743590 # average overall miss latency 2721system.l2c.demand_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency 2722system.l2c.demand_avg_miss_latency::cpu0.inst 81239.993725 # average overall miss latency 2723system.l2c.demand_avg_miss_latency::cpu0.data 94452.829282 # average overall miss latency 2724system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100675.464375 # average overall miss latency 2725system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 98884.615385 # average overall miss latency 2726system.l2c.demand_avg_miss_latency::cpu1.inst 82902.912621 # average overall miss latency 2727system.l2c.demand_avg_miss_latency::cpu1.data 84895.434243 # average overall miss latency 2728system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 127781.765759 # average overall miss latency 2729system.l2c.demand_avg_miss_latency::total 97621.945757 # average overall miss latency 2730system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86089.743590 # average overall miss latency 2731system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency 2732system.l2c.overall_avg_miss_latency::cpu0.inst 81239.993725 # average overall miss latency 2733system.l2c.overall_avg_miss_latency::cpu0.data 94452.829282 # average overall miss latency 2734system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100675.464375 # average overall miss latency 2735system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 98884.615385 # average overall miss latency 2736system.l2c.overall_avg_miss_latency::cpu1.inst 82902.912621 # average overall miss latency 2737system.l2c.overall_avg_miss_latency::cpu1.data 84895.434243 # average overall miss latency 2738system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 127781.765759 # average overall miss latency 2739system.l2c.overall_avg_miss_latency::total 97621.945757 # average overall miss latency 2740system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2741system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2742system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2743system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2744system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2745system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2746system.l2c.writebacks::writebacks 102453 # number of writebacks 2747system.l2c.writebacks::total 102453 # number of writebacks 2748system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits 2749system.l2c.ReadSharedReq_mshr_hits::total 3 # number of ReadSharedReq MSHR hits 2750system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 2751system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 2752system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 2753system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits 2754system.l2c.CleanEvict_mshr_misses::writebacks 4008 # number of CleanEvict MSHR misses 2755system.l2c.CleanEvict_mshr_misses::total 4008 # number of CleanEvict MSHR misses 2756system.l2c.UpgradeReq_mshr_misses::cpu0.data 9873 # number of UpgradeReq MSHR misses 2757system.l2c.UpgradeReq_mshr_misses::cpu1.data 3017 # number of UpgradeReq MSHR misses 2758system.l2c.UpgradeReq_mshr_misses::total 12890 # number of UpgradeReq MSHR misses 2759system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 747 # number of SCUpgradeReq MSHR misses 2760system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1385 # number of SCUpgradeReq MSHR misses 2761system.l2c.SCUpgradeReq_mshr_misses::total 2132 # number of SCUpgradeReq MSHR misses 2762system.l2c.ReadExReq_mshr_misses::cpu0.data 11157 # number of ReadExReq MSHR misses 2763system.l2c.ReadExReq_mshr_misses::cpu1.data 8253 # number of ReadExReq MSHR misses 2764system.l2c.ReadExReq_mshr_misses::total 19410 # number of ReadExReq MSHR misses 2765system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 117 # number of ReadSharedReq MSHR misses 2766system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses 2767system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22308 # number of ReadSharedReq MSHR misses 2768system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9661 # number of ReadSharedReq MSHR misses 2769system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130681 # number of ReadSharedReq MSHR misses 2770system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 13 # number of ReadSharedReq MSHR misses 2771system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3296 # number of ReadSharedReq MSHR misses 2772system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1822 # number of ReadSharedReq MSHR misses 2773system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6980 # number of ReadSharedReq MSHR misses 2774system.l2c.ReadSharedReq_mshr_misses::total 174879 # number of ReadSharedReq MSHR misses 2775system.l2c.demand_mshr_misses::cpu0.dtb.walker 117 # number of demand (read+write) MSHR misses 2776system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2777system.l2c.demand_mshr_misses::cpu0.inst 22308 # number of demand (read+write) MSHR misses 2778system.l2c.demand_mshr_misses::cpu0.data 20818 # number of demand (read+write) MSHR misses 2779system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130681 # number of demand (read+write) MSHR misses 2780system.l2c.demand_mshr_misses::cpu1.dtb.walker 13 # number of demand (read+write) MSHR misses 2781system.l2c.demand_mshr_misses::cpu1.inst 3296 # number of demand (read+write) MSHR misses 2782system.l2c.demand_mshr_misses::cpu1.data 10075 # number of demand (read+write) MSHR misses 2783system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6980 # number of demand (read+write) MSHR misses 2784system.l2c.demand_mshr_misses::total 194289 # number of demand (read+write) MSHR misses 2785system.l2c.overall_mshr_misses::cpu0.dtb.walker 117 # number of overall MSHR misses 2786system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2787system.l2c.overall_mshr_misses::cpu0.inst 22308 # number of overall MSHR misses 2788system.l2c.overall_mshr_misses::cpu0.data 20818 # number of overall MSHR misses 2789system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130681 # number of overall MSHR misses 2790system.l2c.overall_mshr_misses::cpu1.dtb.walker 13 # number of overall MSHR misses 2791system.l2c.overall_mshr_misses::cpu1.inst 3296 # number of overall MSHR misses 2792system.l2c.overall_mshr_misses::cpu1.data 10075 # number of overall MSHR misses 2793system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6980 # number of overall MSHR misses 2794system.l2c.overall_mshr_misses::total 194289 # number of overall MSHR misses 2795system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable 2796system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable 2797system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2798system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14421 # number of ReadReq MSHR uncacheable 2799system.l2c.ReadReq_mshr_uncacheable::total 38557 # number of ReadReq MSHR uncacheable 2800system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable 2801system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11758 # number of WriteReq MSHR uncacheable 2802system.l2c.WriteReq_mshr_uncacheable::total 31029 # number of WriteReq MSHR uncacheable 2803system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses 2804system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses 2805system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2806system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses 2807system.l2c.overall_mshr_uncacheable_misses::total 69586 # number of overall MSHR uncacheable misses 2808system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 236541500 # number of UpgradeReq MSHR miss cycles 2809system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 69602500 # number of UpgradeReq MSHR miss cycles 2810system.l2c.UpgradeReq_mshr_miss_latency::total 306144000 # number of UpgradeReq MSHR miss cycles 2811system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 19267000 # number of SCUpgradeReq MSHR miss cycles 2812system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 34208500 # number of SCUpgradeReq MSHR miss cycles 2813system.l2c.SCUpgradeReq_mshr_miss_latency::total 53475500 # number of SCUpgradeReq MSHR miss cycles 2814system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 997851000 # number of ReadExReq MSHR miss cycles 2815system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 603531502 # number of ReadExReq MSHR miss cycles 2816system.l2c.ReadExReq_mshr_miss_latency::total 1601382502 # number of ReadExReq MSHR miss cycles 2817system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 8902500 # number of ReadSharedReq MSHR miss cycles 2818system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 74000 # number of ReadSharedReq MSHR miss cycles 2819system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1589128504 # number of ReadSharedReq MSHR miss cycles 2820system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 760287501 # number of ReadSharedReq MSHR miss cycles 2821system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11849557367 # number of ReadSharedReq MSHR miss cycles 2822system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1155500 # number of ReadSharedReq MSHR miss cycles 2823system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 240287501 # number of ReadSharedReq MSHR miss cycles 2824system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 151039000 # number of ReadSharedReq MSHR miss cycles 2825system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 822114729 # number of ReadSharedReq MSHR miss cycles 2826system.l2c.ReadSharedReq_mshr_miss_latency::total 15422546602 # number of ReadSharedReq MSHR miss cycles 2827system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 8902500 # number of demand (read+write) MSHR miss cycles 2828system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 74000 # number of demand (read+write) MSHR miss cycles 2829system.l2c.demand_mshr_miss_latency::cpu0.inst 1589128504 # number of demand (read+write) MSHR miss cycles 2830system.l2c.demand_mshr_miss_latency::cpu0.data 1758138501 # number of demand (read+write) MSHR miss cycles 2831system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11849557367 # number of demand (read+write) MSHR miss cycles 2832system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1155500 # number of demand (read+write) MSHR miss cycles 2833system.l2c.demand_mshr_miss_latency::cpu1.inst 240287501 # number of demand (read+write) MSHR miss cycles 2834system.l2c.demand_mshr_miss_latency::cpu1.data 754570502 # number of demand (read+write) MSHR miss cycles 2835system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 822114729 # number of demand (read+write) MSHR miss cycles 2836system.l2c.demand_mshr_miss_latency::total 17023929104 # number of demand (read+write) MSHR miss cycles 2837system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 8902500 # number of overall MSHR miss cycles 2838system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles 2839system.l2c.overall_mshr_miss_latency::cpu0.inst 1589128504 # number of overall MSHR miss cycles 2840system.l2c.overall_mshr_miss_latency::cpu0.data 1758138501 # number of overall MSHR miss cycles 2841system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11849557367 # number of overall MSHR miss cycles 2842system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1155500 # number of overall MSHR miss cycles 2843system.l2c.overall_mshr_miss_latency::cpu1.inst 240287501 # number of overall MSHR miss cycles 2844system.l2c.overall_mshr_miss_latency::cpu1.data 754570502 # number of overall MSHR miss cycles 2845system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 822114729 # number of overall MSHR miss cycles 2846system.l2c.overall_mshr_miss_latency::total 17023929104 # number of overall MSHR miss cycles 2847system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 219448500 # number of ReadReq MSHR uncacheable cycles 2848system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4080498000 # number of ReadReq MSHR uncacheable cycles 2849system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7226000 # number of ReadReq MSHR uncacheable cycles 2850system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2104700001 # number of ReadReq MSHR uncacheable cycles 2851system.l2c.ReadReq_mshr_uncacheable_latency::total 6411872501 # number of ReadReq MSHR uncacheable cycles 2852system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 219448500 # number of overall MSHR uncacheable cycles 2853system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4080498000 # number of overall MSHR uncacheable cycles 2854system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7226000 # number of overall MSHR uncacheable cycles 2855system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2104700001 # number of overall MSHR uncacheable cycles 2856system.l2c.overall_mshr_uncacheable_latency::total 6411872501 # number of overall MSHR uncacheable cycles 2857system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2858system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2859system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225932 # mshr miss rate for UpgradeReq accesses 2860system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.526619 # mshr miss rate for UpgradeReq accesses 2861system.l2c.UpgradeReq_mshr_miss_rate::total 0.260783 # mshr miss rate for UpgradeReq accesses 2862system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.253306 # mshr miss rate for SCUpgradeReq accesses 2863system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563237 # mshr miss rate for SCUpgradeReq accesses 2864system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.394231 # mshr miss rate for SCUpgradeReq accesses 2865system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725281 # mshr miss rate for ReadExReq accesses 2866system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.832627 # mshr miss rate for ReadExReq accesses 2867system.l2c.ReadExReq_mshr_miss_rate::total 0.767345 # mshr miss rate for ReadExReq accesses 2868system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for ReadSharedReq accesses 2869system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for ReadSharedReq accesses 2870system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for ReadSharedReq accesses 2871system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161404 # mshr miss rate for ReadSharedReq accesses 2872system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for ReadSharedReq accesses 2873system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for ReadSharedReq accesses 2874system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for ReadSharedReq accesses 2875system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.153794 # mshr miss rate for ReadSharedReq accesses 2876system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for ReadSharedReq accesses 2877system.l2c.ReadSharedReq_mshr_miss_rate::total 0.495784 # mshr miss rate for ReadSharedReq accesses 2878system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for demand accesses 2879system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for demand accesses 2880system.l2c.demand_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for demand accesses 2881system.l2c.demand_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for demand accesses 2882system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for demand accesses 2883system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for demand accesses 2884system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for demand accesses 2885system.l2c.demand_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for demand accesses 2886system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for demand accesses 2887system.l2c.demand_mshr_miss_rate::total 0.513955 # mshr miss rate for demand accesses 2888system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for overall accesses 2889system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for overall accesses 2890system.l2c.overall_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for overall accesses 2891system.l2c.overall_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for overall accesses 2892system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for overall accesses 2893system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for overall accesses 2894system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for overall accesses 2895system.l2c.overall_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for overall accesses 2896system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for overall accesses 2897system.l2c.overall_mshr_miss_rate::total 0.513955 # mshr miss rate for overall accesses 2898system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23958.421959 # average UpgradeReq mshr miss latency 2899system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23070.102751 # average UpgradeReq mshr miss latency 2900system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23750.504267 # average UpgradeReq mshr miss latency 2901system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25792.503347 # average SCUpgradeReq mshr miss latency 2902system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24699.277978 # average SCUpgradeReq mshr miss latency 2903system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25082.317073 # average SCUpgradeReq mshr miss latency 2904system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89437.214305 # average ReadExReq mshr miss latency 2905system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73128.741306 # average ReadExReq mshr miss latency 2906system.l2c.ReadExReq_avg_mshr_miss_latency::total 82502.962494 # average ReadExReq mshr miss latency 2907system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average ReadSharedReq mshr miss latency 2908system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadSharedReq mshr miss latency 2909system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average ReadSharedReq mshr miss latency 2910system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78696.563606 # average ReadSharedReq mshr miss latency 2911system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average ReadSharedReq mshr miss latency 2912system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average ReadSharedReq mshr miss latency 2913system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average ReadSharedReq mshr miss latency 2914system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82897.365532 # average ReadSharedReq mshr miss latency 2915system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average ReadSharedReq mshr miss latency 2916system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88189.814683 # average ReadSharedReq mshr miss latency 2917system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency 2918system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency 2919system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency 2920system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency 2921system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency 2922system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency 2923system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency 2924system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency 2925system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency 2926system.l2c.demand_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency 2927system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency 2928system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency 2929system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency 2930system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency 2931system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency 2932system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency 2933system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency 2934system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency 2935system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency 2936system.l2c.overall_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency 2937system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average ReadReq mshr uncacheable latency 2938system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198323.110571 # average ReadReq mshr uncacheable latency 2939system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average ReadReq mshr uncacheable latency 2940system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145946.883087 # average ReadReq mshr uncacheable latency 2941system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166295.938507 # average ReadReq mshr uncacheable latency 2942system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average overall mshr uncacheable latency 2943system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102406.715856 # average overall mshr uncacheable latency 2944system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average overall mshr uncacheable latency 2945system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80396.501050 # average overall mshr uncacheable latency 2946system.l2c.overall_avg_mshr_uncacheable_latency::total 92143.139439 # average overall mshr uncacheable latency 2947system.membus.snoop_filter.tot_requests 526346 # Total number of requests made to the snoop filter. 2948system.membus.snoop_filter.hit_single_requests 301567 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2949system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2950system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2951system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2952system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2953system.membus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 2954system.membus.trans_dist::ReadReq 38557 # Transaction distribution 2955system.membus.trans_dist::ReadResp 213679 # Transaction distribution 2956system.membus.trans_dist::WriteReq 31029 # Transaction distribution 2957system.membus.trans_dist::WriteResp 31029 # Transaction distribution 2958system.membus.trans_dist::WritebackDirty 138659 # Transaction distribution 2959system.membus.trans_dist::CleanEvict 18543 # Transaction distribution 2960system.membus.trans_dist::UpgradeReq 76988 # Transaction distribution 2961system.membus.trans_dist::SCUpgradeReq 41072 # Transaction distribution 2962system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 2963system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2964system.membus.trans_dist::ReadExReq 39665 # Transaction distribution 2965system.membus.trans_dist::ReadExResp 19299 # Transaction distribution 2966system.membus.trans_dist::ReadSharedReq 175122 # Transaction distribution 2967system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2968system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2969system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 2970system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14190 # Packet count per connected master and slave (bytes) 2971system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664223 # Packet count per connected master and slave (bytes) 2972system.membus.pkt_count_system.l2c.mem_side::total 786371 # Packet count per connected master and slave (bytes) 2973system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) 2974system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) 2975system.membus.pkt_count::total 859302 # Packet count per connected master and slave (bytes) 2976system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2977system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) 2978system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28380 # Cumulative packet size per connected master and slave (bytes) 2979system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19209376 # Cumulative packet size per connected master and slave (bytes) 2980system.membus.pkt_size_system.l2c.mem_side::total 19401896 # Cumulative packet size per connected master and slave (bytes) 2981system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 2982system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 2983system.membus.pkt_size::total 21720040 # Cumulative packet size per connected master and slave (bytes) 2984system.membus.snoops 123861 # Total snoops (count) 2985system.membus.snoop_fanout::samples 438659 # Request fanout histogram 2986system.membus.snoop_fanout::mean 0.011132 # Request fanout histogram 2987system.membus.snoop_fanout::stdev 0.104918 # Request fanout histogram 2988system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2989system.membus.snoop_fanout::0 433776 98.89% 98.89% # Request fanout histogram 2990system.membus.snoop_fanout::1 4883 1.11% 100.00% # Request fanout histogram 2991system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2992system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2993system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2994system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2995system.membus.snoop_fanout::total 438659 # Request fanout histogram 2996system.membus.reqLayer0.occupancy 89013499 # Layer occupancy (ticks) 2997system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2998system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) 2999system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3000system.membus.reqLayer2.occupancy 12314999 # Layer occupancy (ticks) 3001system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3002system.membus.reqLayer5.occupancy 1002605728 # Layer occupancy (ticks) 3003system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3004system.membus.respLayer2.occupancy 1133893717 # Layer occupancy (ticks) 3005system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3006system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks) 3007system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3008system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3009system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3010system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3011system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3012system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3013system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3014system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3015system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3016system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3017system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3018system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3019system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3020system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3021system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3022system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3023system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3024system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3025system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3026system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3027system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3028system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3029system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3030system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3031system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3032system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3033system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3034system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3035system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3036system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3037system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3038system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3039system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3040system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3041system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3042system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3043system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3044system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3045system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3046system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3047system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3048system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3049system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3050system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3051system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3052system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3053system.realview.ethernet.droppedPackets 0 # number of packets dropped 3054system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3055system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3056system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3057system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3058system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3059system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3060system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3061system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3062system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3063system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3064system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3065system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3066system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3067system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3068system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3069system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3070system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3071system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3072system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3073system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3074system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3075system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3076system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3077system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter. 3078system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3079system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3080system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter. 3081system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3082system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3083system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3084system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution 3085system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution 3086system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution 3087system.toL2Bus.trans_dist::WriteResp 31029 # Transaction distribution 3088system.toL2Bus.trans_dist::WritebackDirty 371703 # Transaction distribution 3089system.toL2Bus.trans_dist::CleanEvict 144260 # Transaction distribution 3090system.toL2Bus.trans_dist::UpgradeReq 113415 # Transaction distribution 3091system.toL2Bus.trans_dist::SCUpgradeReq 44348 # Transaction distribution 3092system.toL2Bus.trans_dist::UpgradeResp 157763 # Transaction distribution 3093system.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution 3094system.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution 3095system.toL2Bus.trans_dist::ReadExReq 51662 # Transaction distribution 3096system.toL2Bus.trans_dist::ReadExResp 51662 # Transaction distribution 3097system.toL2Bus.trans_dist::ReadSharedReq 474894 # Transaction distribution 3098system.toL2Bus.trans_dist::InvalidateReq 4314 # Transaction distribution 3099system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1271960 # Packet count per connected master and slave (bytes) 3100system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368625 # Packet count per connected master and slave (bytes) 3101system.toL2Bus.pkt_count::total 1640585 # Packet count per connected master and slave (bytes) 3102system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36024040 # Cumulative packet size per connected master and slave (bytes) 3103system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5855360 # Cumulative packet size per connected master and slave (bytes) 3104system.toL2Bus.pkt_size::total 41879400 # Cumulative packet size per connected master and slave (bytes) 3105system.toL2Bus.snoops 387762 # Total snoops (count) 3106system.toL2Bus.snoop_fanout::samples 889983 # Request fanout histogram 3107system.toL2Bus.snoop_fanout::mean 0.383411 # Request fanout histogram 3108system.toL2Bus.snoop_fanout::stdev 0.488617 # Request fanout histogram 3109system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3110system.toL2Bus.snoop_fanout::0 549795 61.78% 61.78% # Request fanout histogram 3111system.toL2Bus.snoop_fanout::1 339147 38.11% 99.88% # Request fanout histogram 3112system.toL2Bus.snoop_fanout::2 1041 0.12% 100.00% # Request fanout histogram 3113system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3114system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3115system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3116system.toL2Bus.snoop_fanout::total 889983 # Request fanout histogram 3117system.toL2Bus.reqLayer0.occupancy 926156147 # Layer occupancy (ticks) 3118system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3119system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks) 3120system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3121system.toL2Bus.respLayer0.occupancy 669727799 # Layer occupancy (ticks) 3122system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3123system.toL2Bus.respLayer1.occupancy 257138606 # Layer occupancy (ticks) 3124system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3125 3126---------- End Simulation Statistics ----------