Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.848878 # Number of seconds simulated
4sim_ticks 2848878048000 # Number of ticks simulated
5final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 194660 # Simulator instruction rate (inst/s)
8host_op_rate 235713 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4372273286 # Simulator tick rate (ticks/s)
10host_mem_usage 620428 # Number of bytes of host memory used
11host_seconds 651.58 # Real time elapsed on the host

7host_inst_rate 186843 # Simulator instruction rate (inst/s)
8host_op_rate 226247 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4196685224 # Simulator tick rate (ticks/s)
10host_mem_usage 620168 # Number of bytes of host memory used
11host_seconds 678.84 # Real time elapsed on the host

12sim_insts 126836472 # Number of instructions simulated
13sim_ops 153585571 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1701632 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1345580 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8578560 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 207872 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 624532 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.l2cache.prefetcher 336128 # Number of bytes read from this memory
25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
26system.physmem.bytes_read::total 12804992 # Number of bytes read from this memory
27system.physmem.bytes_inst_read::cpu0.inst 1701632 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu1.inst 207872 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 1909504 # Number of instructions bytes read from this memory
30system.physmem.bytes_written::writebacks 8865600 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
33system.physmem.bytes_written::total 8883164 # Number of bytes written to this memory
34system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.inst 26588 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.data 21546 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.l2cache.prefetcher 134040 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.inst 3248 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.data 9779 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.l2cache.prefetcher 5252 # Number of read requests responded to by this memory
43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
44system.physmem.num_reads::total 200620 # Number of read requests responded to by this memory
45system.physmem.num_writes::writebacks 138525 # Number of write requests responded to by this memory
46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
48system.physmem.num_writes::total 142916 # Number of write requests responded to by this memory
49system.physmem.bw_read::cpu0.dtb.walker 3145 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.inst 597299 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.data 472319 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.l2cache.prefetcher 3011206 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.dtb.walker 247 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.inst 72966 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.data 219220 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.l2cache.prefetcher 117986 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::total 4494749 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_inst_read::cpu0.inst 597299 # Instruction read bandwidth from this memory (bytes/s)
61system.physmem.bw_inst_read::cpu1.inst 72966 # Instruction read bandwidth from this memory (bytes/s)
62system.physmem.bw_inst_read::total 670265 # Instruction read bandwidth from this memory (bytes/s)
63system.physmem.bw_write::writebacks 3111962 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
66system.physmem.bw_write::total 3118127 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_total::writebacks 3111962 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.dtb.walker 3145 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu0.inst 597299 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.data 478470 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.l2cache.prefetcher 3011206 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu1.dtb.walker 247 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu1.inst 72966 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu1.data 219234 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.l2cache.prefetcher 117986 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::total 7612876 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.readReqs 200620 # Number of read requests accepted
80system.physmem.writeReqs 142916 # Number of write requests accepted
81system.physmem.readBursts 200620 # Number of DRAM read bursts, including those serviced by the write queue
82system.physmem.writeBursts 142916 # Number of DRAM write bursts, including those merged in the write queue
83system.physmem.bytesReadDRAM 12829952 # Total number of bytes read from DRAM
84system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue
85system.physmem.bytesWritten 8896256 # Total number of bytes written to DRAM
86system.physmem.bytesReadSys 12804992 # Total read bytes from the system interface side
87system.physmem.bytesWrittenSys 8883164 # Total written bytes from the system interface side
88system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue
89system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
90system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
91system.physmem.perBankRdBursts::0 12282 # Per bank write bursts
92system.physmem.perBankRdBursts::1 12615 # Per bank write bursts
93system.physmem.perBankRdBursts::2 13546 # Per bank write bursts
94system.physmem.perBankRdBursts::3 12896 # Per bank write bursts
95system.physmem.perBankRdBursts::4 15667 # Per bank write bursts
96system.physmem.perBankRdBursts::5 12734 # Per bank write bursts
97system.physmem.perBankRdBursts::6 12682 # Per bank write bursts
98system.physmem.perBankRdBursts::7 12950 # Per bank write bursts
99system.physmem.perBankRdBursts::8 12070 # Per bank write bursts
100system.physmem.perBankRdBursts::9 12307 # Per bank write bursts
101system.physmem.perBankRdBursts::10 11595 # Per bank write bursts
102system.physmem.perBankRdBursts::11 10656 # Per bank write bursts
103system.physmem.perBankRdBursts::12 11845 # Per bank write bursts
104system.physmem.perBankRdBursts::13 12839 # Per bank write bursts
105system.physmem.perBankRdBursts::14 12069 # Per bank write bursts
106system.physmem.perBankRdBursts::15 11715 # Per bank write bursts
107system.physmem.perBankWrBursts::0 8801 # Per bank write bursts
108system.physmem.perBankWrBursts::1 9221 # Per bank write bursts
109system.physmem.perBankWrBursts::2 9816 # Per bank write bursts
110system.physmem.perBankWrBursts::3 9124 # Per bank write bursts
111system.physmem.perBankWrBursts::4 8304 # Per bank write bursts
112system.physmem.perBankWrBursts::5 8866 # Per bank write bursts
113system.physmem.perBankWrBursts::6 8953 # Per bank write bursts
114system.physmem.perBankWrBursts::7 8983 # Per bank write bursts
115system.physmem.perBankWrBursts::8 8497 # Per bank write bursts
116system.physmem.perBankWrBursts::9 8715 # Per bank write bursts
117system.physmem.perBankWrBursts::10 8212 # Per bank write bursts
118system.physmem.perBankWrBursts::11 7775 # Per bank write bursts
119system.physmem.perBankWrBursts::12 8513 # Per bank write bursts
120system.physmem.perBankWrBursts::13 8820 # Per bank write bursts
121system.physmem.perBankWrBursts::14 8499 # Per bank write bursts
122system.physmem.perBankWrBursts::15 7905 # Per bank write bursts
123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
124system.physmem.numWrRetry 24 # Number of times write queue was full causing retry
125system.physmem.totGap 2848877502000 # Total gap between requests
126system.physmem.readPktSize::0 0 # Read request sizes (log2)
127system.physmem.readPktSize::1 0 # Read request sizes (log2)
128system.physmem.readPktSize::2 552 # Read request sizes (log2)
129system.physmem.readPktSize::3 28 # Read request sizes (log2)
130system.physmem.readPktSize::4 0 # Read request sizes (log2)
131system.physmem.readPktSize::5 0 # Read request sizes (log2)
132system.physmem.readPktSize::6 200040 # Read request sizes (log2)
133system.physmem.writePktSize::0 0 # Write request sizes (log2)
134system.physmem.writePktSize::1 0 # Write request sizes (log2)
135system.physmem.writePktSize::2 4391 # Write request sizes (log2)
136system.physmem.writePktSize::3 0 # Write request sizes (log2)
137system.physmem.writePktSize::4 0 # Write request sizes (log2)
138system.physmem.writePktSize::5 0 # Write request sizes (log2)
139system.physmem.writePktSize::6 138525 # Write request sizes (log2)
140system.physmem.rdQLenPdf::0 88667 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::1 61660 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::2 11649 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::3 9417 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::4 7800 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::5 6275 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::6 5209 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::7 4659 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::8 3795 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::9 680 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::10 205 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::12 147 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::15 2736 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::17 5382 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::18 5002 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::19 6318 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::20 6195 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::21 6700 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::22 7342 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::23 8071 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::24 8092 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::25 8883 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::26 9784 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::27 8806 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::28 9313 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::29 11631 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::30 9125 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::31 8320 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::32 7996 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::33 1289 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::34 454 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::35 316 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::36 294 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::37 246 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::38 189 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::39 164 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::46 100 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::49 169 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::50 150 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::54 156 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::58 89 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::63 83 # What write queue length does an incoming req see
236system.physmem.bytesPerActivate::samples 92501 # Bytes accessed per row activation
237system.physmem.bytesPerActivate::mean 234.874693 # Bytes accessed per row activation
238system.physmem.bytesPerActivate::gmean 133.252552 # Bytes accessed per row activation
239system.physmem.bytesPerActivate::stdev 298.003949 # Bytes accessed per row activation
240system.physmem.bytesPerActivate::0-127 50468 54.56% 54.56% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::128-255 17746 19.18% 73.74% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::256-383 6298 6.81% 80.55% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::384-511 3474 3.76% 84.31% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::512-639 2881 3.11% 87.42% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::640-767 1488 1.61% 89.03% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::768-895 938 1.01% 90.05% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::896-1023 959 1.04% 91.08% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::1024-1151 8249 8.92% 100.00% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::total 92501 # Bytes accessed per row activation
250system.physmem.rdPerTurnAround::samples 6731 # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::mean 29.782499 # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::stdev 569.000641 # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::0-2047 6729 99.97% 99.97% # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::total 6731 # Reads before turning the bus around for writes
257system.physmem.wrPerTurnAround::samples 6731 # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::mean 20.651315 # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::gmean 18.819444 # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::stdev 13.992190 # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::16-19 5609 83.33% 83.33% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::20-23 487 7.24% 90.57% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::24-27 91 1.35% 91.92% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::28-31 48 0.71% 92.63% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::32-35 35 0.52% 93.15% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::36-39 15 0.22% 93.37% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::40-43 45 0.67% 94.04% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::44-47 18 0.27% 94.31% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::48-51 127 1.89% 96.20% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::52-55 10 0.15% 96.35% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::56-59 8 0.12% 96.46% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::60-63 12 0.18% 96.64% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::64-67 75 1.11% 97.76% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::68-71 6 0.09% 97.85% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::72-75 3 0.04% 97.89% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::76-79 23 0.34% 98.23% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::80-83 82 1.22% 99.45% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::104-107 1 0.01% 99.49% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::108-111 2 0.03% 99.52% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::112-115 5 0.07% 99.60% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::124-127 2 0.03% 99.63% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::128-131 8 0.12% 99.75% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::136-139 1 0.01% 99.76% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::144-147 9 0.13% 99.90% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::156-159 1 0.01% 99.91% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::176-179 2 0.03% 99.97% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::total 6731 # Writes before turning the bus around for reads
292system.physmem.totQLat 5345988099 # Total ticks spent queuing
293system.physmem.totMemAccLat 9104763099 # Total ticks spent from burst creation until serviced by the DRAM
294system.physmem.totBusLat 1002340000 # Total ticks spent in databus transfers
295system.physmem.avgQLat 26667.54 # Average queueing delay per DRAM burst
296system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
297system.physmem.avgMemAccLat 45417.54 # Average memory access latency per DRAM burst
298system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s
299system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s
300system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s
301system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s
302system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
303system.physmem.busUtil 0.06 # Data bus utilization in percentage
304system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
305system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
306system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
307system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing
308system.physmem.readRowHits 166512 # Number of row buffer hits during reads
309system.physmem.writeRowHits 80458 # Number of row buffer hits during writes
310system.physmem.readRowHitRate 83.06 # Row buffer hit rate for reads
311system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes
312system.physmem.avgGap 8292806.29 # Average gap between requests
313system.physmem.pageHitRate 72.75 # Row buffer hit rate, read and write combined
314system.physmem_0.actEnergy 369525240 # Energy for activate commands per rank (pJ)
315system.physmem_0.preEnergy 201625875 # Energy for precharge commands per rank (pJ)
316system.physmem_0.readEnergy 821901600 # Energy for read commands per rank (pJ)
317system.physmem_0.writeEnergy 467000640 # Energy for write commands per rank (pJ)
318system.physmem_0.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ)
319system.physmem_0.actBackEnergy 85037796405 # Energy for active background per rank (pJ)
320system.physmem_0.preBackEnergy 1634728846500 # Energy for precharge background per rank (pJ)
321system.physmem_0.totalEnergy 1907701171860 # Total energy per rank (pJ)
322system.physmem_0.averagePower 669.633786 # Core power per rank (mW)
323system.physmem_0.memoryStateTime::IDLE 2719381991131 # Time in different power states
324system.physmem_0.memoryStateTime::REF 95130100000 # Time in different power states
325system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
326system.physmem_0.memoryStateTime::ACT 34360263869 # Time in different power states
327system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
328system.physmem_1.actEnergy 329782320 # Energy for activate commands per rank (pJ)
329system.physmem_1.preEnergy 179940750 # Energy for precharge commands per rank (pJ)
330system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ)
331system.physmem_1.writeEnergy 433745280 # Energy for write commands per rank (pJ)
332system.physmem_1.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ)
333system.physmem_1.actBackEnergy 83868136740 # Energy for active background per rank (pJ)
334system.physmem_1.preBackEnergy 1635754863750 # Energy for precharge background per rank (pJ)
335system.physmem_1.totalEnergy 1907382685440 # Total energy per rank (pJ)
336system.physmem_1.averagePower 669.521992 # Core power per rank (mW)
337system.physmem_1.memoryStateTime::IDLE 2721101495830 # Time in different power states
338system.physmem_1.memoryStateTime::REF 95130100000 # Time in different power states
339system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
340system.physmem_1.memoryStateTime::ACT 32646289170 # Time in different power states
341system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
342system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
343system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
344system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory
345system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory
346system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory
347system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
348system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
349system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
350system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
351system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s)
352system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s)
353system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s)
354system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s)
355system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s)
356system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s)
357system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
358system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
359system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
360system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
361system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
362system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
363system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
364system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
365system.cf0.dma_write_txs 631 # Number of DMA write transactions.
366system.cpu0.branchPred.lookups 36258885 # Number of BP lookups
367system.cpu0.branchPred.condPredicted 17779541 # Number of conditional branches predicted
368system.cpu0.branchPred.condIncorrect 1788671 # Number of conditional branches incorrect
369system.cpu0.branchPred.BTBLookups 20741460 # Number of BTB lookups
370system.cpu0.branchPred.BTBHits 11048316 # Number of BTB hits
371system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
372system.cpu0.branchPred.BTBHitPct 53.266819 # BTB Hit Percentage
373system.cpu0.branchPred.usedRAS 11219024 # Number of times the RAS was used to get a target.
374system.cpu0.branchPred.RASInCorrect 931479 # Number of incorrect RAS predictions.
375system.cpu0.branchPred.indirectLookups 4153759 # Number of indirect predictor lookups.
376system.cpu0.branchPred.indirectHits 3951203 # Number of indirect target hits.
377system.cpu0.branchPred.indirectMisses 202556 # Number of indirect misses.
378system.cpu0.branchPredindirectMispredicted 105471 # Number of mispredicted indirect branches.
379system.cpu_clk_domain.clock 500 # Clock period in ticks
380system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
388system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
389system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
390system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
391system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
392system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
393system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
394system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
395system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
396system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
398system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
399system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
400system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
401system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
402system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
403system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
404system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
405system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
406system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
407system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
408system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
409system.cpu0.dtb.walker.walks 71829 # Table walker walks requested
410system.cpu0.dtb.walker.walksShort 71829 # Table walker walks initiated with short descriptors
411system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46722 # Level at which table walker walks with short descriptors terminate
412system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25107 # Level at which table walker walks with short descriptors terminate
413system.cpu0.dtb.walker.walkWaitTime::samples 71829 # Table walker wait (enqueue to first request) latency
414system.cpu0.dtb.walker.walkWaitTime::0 71829 100.00% 100.00% # Table walker wait (enqueue to first request) latency
415system.cpu0.dtb.walker.walkWaitTime::total 71829 # Table walker wait (enqueue to first request) latency
416system.cpu0.dtb.walker.walkCompletionTime::samples 7556 # Table walker service (enqueue to completion) latency
417system.cpu0.dtb.walker.walkCompletionTime::mean 12351.641080 # Table walker service (enqueue to completion) latency
418system.cpu0.dtb.walker.walkCompletionTime::gmean 11368.840758 # Table walker service (enqueue to completion) latency
419system.cpu0.dtb.walker.walkCompletionTime::stdev 8528.588507 # Table walker service (enqueue to completion) latency
420system.cpu0.dtb.walker.walkCompletionTime::0-32767 7496 99.21% 99.21% # Table walker service (enqueue to completion) latency
421system.cpu0.dtb.walker.walkCompletionTime::32768-65535 51 0.67% 99.88% # Table walker service (enqueue to completion) latency
422system.cpu0.dtb.walker.walkCompletionTime::131072-163839 5 0.07% 99.95% # Table walker service (enqueue to completion) latency
423system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.96% # Table walker service (enqueue to completion) latency
424system.cpu0.dtb.walker.walkCompletionTime::196608-229375 1 0.01% 99.97% # Table walker service (enqueue to completion) latency
425system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
426system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
427system.cpu0.dtb.walker.walkCompletionTime::total 7556 # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution
429system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution
430system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution
431system.cpu0.dtb.walker.walkPageSizes::4K 5875 77.75% 77.75% # Table walker page sizes translated
432system.cpu0.dtb.walker.walkPageSizes::1M 1681 22.25% 100.00% # Table walker page sizes translated
433system.cpu0.dtb.walker.walkPageSizes::total 7556 # Table walker page sizes translated
434system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71829 # Table walker requests started/completed, data/inst
435system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
436system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71829 # Table walker requests started/completed, data/inst
437system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7556 # Table walker requests started/completed, data/inst
438system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
439system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7556 # Table walker requests started/completed, data/inst
440system.cpu0.dtb.walker.walkRequestOrigin::total 79385 # Table walker requests started/completed, data/inst
441system.cpu0.dtb.inst_hits 0 # ITB inst hits
442system.cpu0.dtb.inst_misses 0 # ITB inst misses
443system.cpu0.dtb.read_hits 24842790 # DTB read hits
444system.cpu0.dtb.read_misses 65179 # DTB read misses
445system.cpu0.dtb.write_hits 18502994 # DTB write hits
446system.cpu0.dtb.write_misses 6650 # DTB write misses
447system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
448system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
449system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
450system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
451system.cpu0.dtb.flush_entries 3814 # Number of entries that have been flushed from TLB
452system.cpu0.dtb.align_faults 1457 # Number of TLB faults due to alignment restrictions
453system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch
454system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
455system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions
456system.cpu0.dtb.read_accesses 24907969 # DTB read accesses
457system.cpu0.dtb.write_accesses 18509644 # DTB write accesses
458system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
459system.cpu0.dtb.hits 43345784 # DTB hits
460system.cpu0.dtb.misses 71829 # DTB misses
461system.cpu0.dtb.accesses 43417613 # DTB accesses
462system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
465system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
466system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
470system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
471system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
472system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
473system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
474system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
475system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
476system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
477system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
478system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
479system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
480system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
481system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
482system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
483system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
484system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
485system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
486system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
487system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
488system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
489system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
490system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
491system.cpu0.itb.walker.walks 4265 # Table walker walks requested
492system.cpu0.itb.walker.walksShort 4265 # Table walker walks initiated with short descriptors
493system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate
494system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3940 # Level at which table walker walks with short descriptors terminate
495system.cpu0.itb.walker.walkWaitTime::samples 4265 # Table walker wait (enqueue to first request) latency
496system.cpu0.itb.walker.walkWaitTime::0 4265 100.00% 100.00% # Table walker wait (enqueue to first request) latency
497system.cpu0.itb.walker.walkWaitTime::total 4265 # Table walker wait (enqueue to first request) latency
498system.cpu0.itb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency
499system.cpu0.itb.walker.walkCompletionTime::mean 12705.663189 # Table walker service (enqueue to completion) latency
500system.cpu0.itb.walker.walkCompletionTime::gmean 11959.550432 # Table walker service (enqueue to completion) latency
501system.cpu0.itb.walker.walkCompletionTime::stdev 5173.129128 # Table walker service (enqueue to completion) latency
502system.cpu0.itb.walker.walkCompletionTime::0-16383 2444 91.06% 91.06% # Table walker service (enqueue to completion) latency
503system.cpu0.itb.walker.walkCompletionTime::16384-32767 221 8.23% 99.29% # Table walker service (enqueue to completion) latency
504system.cpu0.itb.walker.walkCompletionTime::32768-49151 17 0.63% 99.93% # Table walker service (enqueue to completion) latency
505system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
506system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
507system.cpu0.itb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency
508system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution
509system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution
510system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution
511system.cpu0.itb.walker.walkPageSizes::4K 2364 88.08% 88.08% # Table walker page sizes translated
512system.cpu0.itb.walker.walkPageSizes::1M 320 11.92% 100.00% # Table walker page sizes translated
513system.cpu0.itb.walker.walkPageSizes::total 2684 # Table walker page sizes translated
514system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
515system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4265 # Table walker requests started/completed, data/inst
516system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4265 # Table walker requests started/completed, data/inst
517system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
518system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2684 # Table walker requests started/completed, data/inst
519system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst
520system.cpu0.itb.walker.walkRequestOrigin::total 6949 # Table walker requests started/completed, data/inst
521system.cpu0.itb.inst_hits 71322502 # ITB inst hits
522system.cpu0.itb.inst_misses 4265 # ITB inst misses
523system.cpu0.itb.read_hits 0 # DTB read hits
524system.cpu0.itb.read_misses 0 # DTB read misses
525system.cpu0.itb.write_hits 0 # DTB write hits
526system.cpu0.itb.write_misses 0 # DTB write misses
527system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
528system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
529system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
530system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
531system.cpu0.itb.flush_entries 2459 # Number of entries that have been flushed from TLB
532system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
533system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
534system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
535system.cpu0.itb.perms_faults 7664 # Number of TLB faults due to permissions restrictions
536system.cpu0.itb.read_accesses 0 # DTB read accesses
537system.cpu0.itb.write_accesses 0 # DTB write accesses
538system.cpu0.itb.inst_accesses 71326767 # ITB inst accesses
539system.cpu0.itb.hits 71322502 # DTB hits
540system.cpu0.itb.misses 4265 # DTB misses
541system.cpu0.itb.accesses 71326767 # DTB accesses
542system.cpu0.numCycles 248723849 # number of cpu cycles simulated
543system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
544system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
545system.cpu0.committedInsts 112829406 # Number of instructions committed
546system.cpu0.committedOps 136421013 # Number of ops (including micro ops) committed
547system.cpu0.discardedOps 8883957 # Number of ops (including micro ops) which were discarded before commit
548system.cpu0.numFetchSuspends 1865 # Number of times Execute suspended instruction fetching
549system.cpu0.quiesceCycles 5449058541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
550system.cpu0.cpi 2.204424 # CPI: cycles per instruction
551system.cpu0.ipc 0.453633 # IPC: instructions per cycle
552system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% # Class of committed instruction
553system.cpu0.op_class_0::IntAlu 92785256 68.01% 68.02% # Class of committed instruction
554system.cpu0.op_class_0::IntMult 112251 0.08% 68.10% # Class of committed instruction
555system.cpu0.op_class_0::IntDiv 0 0.00% 68.10% # Class of committed instruction
556system.cpu0.op_class_0::FloatAdd 0 0.00% 68.10% # Class of committed instruction
557system.cpu0.op_class_0::FloatCmp 0 0.00% 68.10% # Class of committed instruction
558system.cpu0.op_class_0::FloatCvt 0 0.00% 68.10% # Class of committed instruction
559system.cpu0.op_class_0::FloatMult 0 0.00% 68.10% # Class of committed instruction
560system.cpu0.op_class_0::FloatDiv 0 0.00% 68.10% # Class of committed instruction
561system.cpu0.op_class_0::FloatSqrt 0 0.00% 68.10% # Class of committed instruction
562system.cpu0.op_class_0::SimdAdd 0 0.00% 68.10% # Class of committed instruction
563system.cpu0.op_class_0::SimdAddAcc 0 0.00% 68.10% # Class of committed instruction
564system.cpu0.op_class_0::SimdAlu 0 0.00% 68.10% # Class of committed instruction
565system.cpu0.op_class_0::SimdCmp 0 0.00% 68.10% # Class of committed instruction
566system.cpu0.op_class_0::SimdCvt 0 0.00% 68.10% # Class of committed instruction
567system.cpu0.op_class_0::SimdMisc 0 0.00% 68.10% # Class of committed instruction
568system.cpu0.op_class_0::SimdMult 0 0.00% 68.10% # Class of committed instruction
569system.cpu0.op_class_0::SimdMultAcc 0 0.00% 68.10% # Class of committed instruction
570system.cpu0.op_class_0::SimdShift 0 0.00% 68.10% # Class of committed instruction
571system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 68.10% # Class of committed instruction
572system.cpu0.op_class_0::SimdSqrt 0 0.00% 68.10% # Class of committed instruction
573system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 68.10% # Class of committed instruction
574system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 68.10% # Class of committed instruction
575system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 68.10% # Class of committed instruction
576system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 68.10% # Class of committed instruction
577system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 68.10% # Class of committed instruction
578system.cpu0.op_class_0::SimdFloatMisc 8279 0.01% 68.10% # Class of committed instruction
579system.cpu0.op_class_0::SimdFloatMult 0 0.00% 68.10% # Class of committed instruction
580system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 68.10% # Class of committed instruction
581system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 68.10% # Class of committed instruction
582system.cpu0.op_class_0::MemRead 24255979 17.78% 85.88% # Class of committed instruction
583system.cpu0.op_class_0::MemWrite 19256933 14.12% 100.00% # Class of committed instruction
584system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
585system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
586system.cpu0.op_class_0::total 136421013 # Class of committed instruction
587system.cpu0.kern.inst.arm 0 # number of arm instructions executed
588system.cpu0.kern.inst.quiesce 1871 # number of quiesce instructions executed
589system.cpu0.tickCycles 199772172 # Number of cycles that the object actually ticked
590system.cpu0.idleCycles 48951677 # Total number of cycles that the object has spent stopped
591system.cpu0.dcache.tags.replacements 757698 # number of replacements
592system.cpu0.dcache.tags.tagsinuse 497.510170 # Cycle average of tags in use
593system.cpu0.dcache.tags.total_refs 41768211 # Total number of references to valid blocks.
594system.cpu0.dcache.tags.sampled_refs 758210 # Sample count of references to valid blocks.
595system.cpu0.dcache.tags.avg_refs 55.087919 # Average number of references to valid blocks.
596system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit.
597system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.510170 # Average occupied blocks per requestor
598system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971700 # Average percentage of cache occupancy
599system.cpu0.dcache.tags.occ_percent::total 0.971700 # Average percentage of cache occupancy
600system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
601system.cpu0.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
602system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id
603system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
604system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
605system.cpu0.dcache.tags.tag_accesses 86683357 # Number of tag accesses
606system.cpu0.dcache.tags.data_accesses 86683357 # Number of data accesses
607system.cpu0.dcache.ReadReq_hits::cpu0.data 23240588 # number of ReadReq hits
608system.cpu0.dcache.ReadReq_hits::total 23240588 # number of ReadReq hits
609system.cpu0.dcache.WriteReq_hits::cpu0.data 17340312 # number of WriteReq hits
610system.cpu0.dcache.WriteReq_hits::total 17340312 # number of WriteReq hits
611system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329150 # number of SoftPFReq hits
612system.cpu0.dcache.SoftPFReq_hits::total 329150 # number of SoftPFReq hits
613system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374937 # number of LoadLockedReq hits
614system.cpu0.dcache.LoadLockedReq_hits::total 374937 # number of LoadLockedReq hits
615system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370987 # number of StoreCondReq hits
616system.cpu0.dcache.StoreCondReq_hits::total 370987 # number of StoreCondReq hits
617system.cpu0.dcache.demand_hits::cpu0.data 40580900 # number of demand (read+write) hits
618system.cpu0.dcache.demand_hits::total 40580900 # number of demand (read+write) hits
619system.cpu0.dcache.overall_hits::cpu0.data 40910050 # number of overall hits
620system.cpu0.dcache.overall_hits::total 40910050 # number of overall hits
621system.cpu0.dcache.ReadReq_misses::cpu0.data 491866 # number of ReadReq misses
622system.cpu0.dcache.ReadReq_misses::total 491866 # number of ReadReq misses
623system.cpu0.dcache.WriteReq_misses::cpu0.data 603751 # number of WriteReq misses
624system.cpu0.dcache.WriteReq_misses::total 603751 # number of WriteReq misses
625system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141943 # number of SoftPFReq misses
626system.cpu0.dcache.SoftPFReq_misses::total 141943 # number of SoftPFReq misses
627system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21447 # number of LoadLockedReq misses
628system.cpu0.dcache.LoadLockedReq_misses::total 21447 # number of LoadLockedReq misses
629system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20439 # number of StoreCondReq misses
630system.cpu0.dcache.StoreCondReq_misses::total 20439 # number of StoreCondReq misses
631system.cpu0.dcache.demand_misses::cpu0.data 1095617 # number of demand (read+write) misses
632system.cpu0.dcache.demand_misses::total 1095617 # number of demand (read+write) misses
633system.cpu0.dcache.overall_misses::cpu0.data 1237560 # number of overall misses
634system.cpu0.dcache.overall_misses::total 1237560 # number of overall misses
635system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6971329500 # number of ReadReq miss cycles
636system.cpu0.dcache.ReadReq_miss_latency::total 6971329500 # number of ReadReq miss cycles
637system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12451928500 # number of WriteReq miss cycles
638system.cpu0.dcache.WriteReq_miss_latency::total 12451928500 # number of WriteReq miss cycles
639system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330609500 # number of LoadLockedReq miss cycles
640system.cpu0.dcache.LoadLockedReq_miss_latency::total 330609500 # number of LoadLockedReq miss cycles
641system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 530569000 # number of StoreCondReq miss cycles
642system.cpu0.dcache.StoreCondReq_miss_latency::total 530569000 # number of StoreCondReq miss cycles
643system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 651500 # number of StoreCondFailReq miss cycles
644system.cpu0.dcache.StoreCondFailReq_miss_latency::total 651500 # number of StoreCondFailReq miss cycles
645system.cpu0.dcache.demand_miss_latency::cpu0.data 19423258000 # number of demand (read+write) miss cycles
646system.cpu0.dcache.demand_miss_latency::total 19423258000 # number of demand (read+write) miss cycles
647system.cpu0.dcache.overall_miss_latency::cpu0.data 19423258000 # number of overall miss cycles
648system.cpu0.dcache.overall_miss_latency::total 19423258000 # number of overall miss cycles
649system.cpu0.dcache.ReadReq_accesses::cpu0.data 23732454 # number of ReadReq accesses(hits+misses)
650system.cpu0.dcache.ReadReq_accesses::total 23732454 # number of ReadReq accesses(hits+misses)
651system.cpu0.dcache.WriteReq_accesses::cpu0.data 17944063 # number of WriteReq accesses(hits+misses)
652system.cpu0.dcache.WriteReq_accesses::total 17944063 # number of WriteReq accesses(hits+misses)
653system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471093 # number of SoftPFReq accesses(hits+misses)
654system.cpu0.dcache.SoftPFReq_accesses::total 471093 # number of SoftPFReq accesses(hits+misses)
655system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396384 # number of LoadLockedReq accesses(hits+misses)
656system.cpu0.dcache.LoadLockedReq_accesses::total 396384 # number of LoadLockedReq accesses(hits+misses)
657system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391426 # number of StoreCondReq accesses(hits+misses)
658system.cpu0.dcache.StoreCondReq_accesses::total 391426 # number of StoreCondReq accesses(hits+misses)
659system.cpu0.dcache.demand_accesses::cpu0.data 41676517 # number of demand (read+write) accesses
660system.cpu0.dcache.demand_accesses::total 41676517 # number of demand (read+write) accesses
661system.cpu0.dcache.overall_accesses::cpu0.data 42147610 # number of overall (read+write) accesses
662system.cpu0.dcache.overall_accesses::total 42147610 # number of overall (read+write) accesses
663system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020725 # miss rate for ReadReq accesses
664system.cpu0.dcache.ReadReq_miss_rate::total 0.020725 # miss rate for ReadReq accesses
665system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033646 # miss rate for WriteReq accesses
666system.cpu0.dcache.WriteReq_miss_rate::total 0.033646 # miss rate for WriteReq accesses
667system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301306 # miss rate for SoftPFReq accesses
668system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301306 # miss rate for SoftPFReq accesses
669system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054107 # miss rate for LoadLockedReq accesses
670system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054107 # miss rate for LoadLockedReq accesses
671system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052217 # miss rate for StoreCondReq accesses
672system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052217 # miss rate for StoreCondReq accesses
673system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026289 # miss rate for demand accesses
674system.cpu0.dcache.demand_miss_rate::total 0.026289 # miss rate for demand accesses
675system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029363 # miss rate for overall accesses
676system.cpu0.dcache.overall_miss_rate::total 0.029363 # miss rate for overall accesses
677system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14173.229091 # average ReadReq miss latency
678system.cpu0.dcache.ReadReq_avg_miss_latency::total 14173.229091 # average ReadReq miss latency
679system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20624.278055 # average WriteReq miss latency
680system.cpu0.dcache.WriteReq_avg_miss_latency::total 20624.278055 # average WriteReq miss latency
681system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15415.186273 # average LoadLockedReq miss latency
682system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15415.186273 # average LoadLockedReq miss latency
683system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25958.657469 # average StoreCondReq miss latency
684system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25958.657469 # average StoreCondReq miss latency
685system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
686system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
687system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17728.145876 # average overall miss latency
688system.cpu0.dcache.demand_avg_miss_latency::total 17728.145876 # average overall miss latency
689system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15694.801060 # average overall miss latency
690system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060 # average overall miss latency
691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
696system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

697system.cpu0.dcache.fast_writes 0 # number of fast writes performed
698system.cpu0.dcache.cache_copies 0 # number of cache copies performed

699system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks
700system.cpu0.dcache.writebacks::total 757698 # number of writebacks
701system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits
702system.cpu0.dcache.ReadReq_mshr_hits::total 75572 # number of ReadReq MSHR hits
703system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266010 # number of WriteReq MSHR hits
704system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits
705system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14891 # number of LoadLockedReq MSHR hits
706system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits
707system.cpu0.dcache.demand_mshr_hits::cpu0.data 341582 # number of demand (read+write) MSHR hits
708system.cpu0.dcache.demand_mshr_hits::total 341582 # number of demand (read+write) MSHR hits
709system.cpu0.dcache.overall_mshr_hits::cpu0.data 341582 # number of overall MSHR hits
710system.cpu0.dcache.overall_mshr_hits::total 341582 # number of overall MSHR hits
711system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416294 # number of ReadReq MSHR misses
712system.cpu0.dcache.ReadReq_mshr_misses::total 416294 # number of ReadReq MSHR misses
713system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337741 # number of WriteReq MSHR misses
714system.cpu0.dcache.WriteReq_mshr_misses::total 337741 # number of WriteReq MSHR misses
715system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108342 # number of SoftPFReq MSHR misses
716system.cpu0.dcache.SoftPFReq_mshr_misses::total 108342 # number of SoftPFReq MSHR misses
717system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses
718system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses
719system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20439 # number of StoreCondReq MSHR misses
720system.cpu0.dcache.StoreCondReq_mshr_misses::total 20439 # number of StoreCondReq MSHR misses
721system.cpu0.dcache.demand_mshr_misses::cpu0.data 754035 # number of demand (read+write) MSHR misses
722system.cpu0.dcache.demand_mshr_misses::total 754035 # number of demand (read+write) MSHR misses
723system.cpu0.dcache.overall_mshr_misses::cpu0.data 862377 # number of overall MSHR misses
724system.cpu0.dcache.overall_mshr_misses::total 862377 # number of overall MSHR misses
725system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32042 # number of ReadReq MSHR uncacheable
726system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32042 # number of ReadReq MSHR uncacheable
727system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable
728system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable
729system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60766 # number of overall MSHR uncacheable misses
730system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60766 # number of overall MSHR uncacheable misses
731system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5289052500 # number of ReadReq MSHR miss cycles
732system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5289052500 # number of ReadReq MSHR miss cycles
733system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7033138500 # number of WriteReq MSHR miss cycles
734system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7033138500 # number of WriteReq MSHR miss cycles
735system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1803466000 # number of SoftPFReq MSHR miss cycles
736system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1803466000 # number of SoftPFReq MSHR miss cycles
737system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104788000 # number of LoadLockedReq MSHR miss cycles
738system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104788000 # number of LoadLockedReq MSHR miss cycles
739system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 510140000 # number of StoreCondReq MSHR miss cycles
740system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 510140000 # number of StoreCondReq MSHR miss cycles
741system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 641500 # number of StoreCondFailReq MSHR miss cycles
742system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles
743system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12322191000 # number of demand (read+write) MSHR miss cycles
744system.cpu0.dcache.demand_mshr_miss_latency::total 12322191000 # number of demand (read+write) MSHR miss cycles
745system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000 # number of overall MSHR miss cycles
746system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles
747system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles
748system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles

697system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks
698system.cpu0.dcache.writebacks::total 757698 # number of writebacks
699system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits
700system.cpu0.dcache.ReadReq_mshr_hits::total 75572 # number of ReadReq MSHR hits
701system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266010 # number of WriteReq MSHR hits
702system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits
703system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14891 # number of LoadLockedReq MSHR hits
704system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits
705system.cpu0.dcache.demand_mshr_hits::cpu0.data 341582 # number of demand (read+write) MSHR hits
706system.cpu0.dcache.demand_mshr_hits::total 341582 # number of demand (read+write) MSHR hits
707system.cpu0.dcache.overall_mshr_hits::cpu0.data 341582 # number of overall MSHR hits
708system.cpu0.dcache.overall_mshr_hits::total 341582 # number of overall MSHR hits
709system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416294 # number of ReadReq MSHR misses
710system.cpu0.dcache.ReadReq_mshr_misses::total 416294 # number of ReadReq MSHR misses
711system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337741 # number of WriteReq MSHR misses
712system.cpu0.dcache.WriteReq_mshr_misses::total 337741 # number of WriteReq MSHR misses
713system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108342 # number of SoftPFReq MSHR misses
714system.cpu0.dcache.SoftPFReq_mshr_misses::total 108342 # number of SoftPFReq MSHR misses
715system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses
716system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses
717system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20439 # number of StoreCondReq MSHR misses
718system.cpu0.dcache.StoreCondReq_mshr_misses::total 20439 # number of StoreCondReq MSHR misses
719system.cpu0.dcache.demand_mshr_misses::cpu0.data 754035 # number of demand (read+write) MSHR misses
720system.cpu0.dcache.demand_mshr_misses::total 754035 # number of demand (read+write) MSHR misses
721system.cpu0.dcache.overall_mshr_misses::cpu0.data 862377 # number of overall MSHR misses
722system.cpu0.dcache.overall_mshr_misses::total 862377 # number of overall MSHR misses
723system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32042 # number of ReadReq MSHR uncacheable
724system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32042 # number of ReadReq MSHR uncacheable
725system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable
726system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable
727system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60766 # number of overall MSHR uncacheable misses
728system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60766 # number of overall MSHR uncacheable misses
729system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5289052500 # number of ReadReq MSHR miss cycles
730system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5289052500 # number of ReadReq MSHR miss cycles
731system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7033138500 # number of WriteReq MSHR miss cycles
732system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7033138500 # number of WriteReq MSHR miss cycles
733system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1803466000 # number of SoftPFReq MSHR miss cycles
734system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1803466000 # number of SoftPFReq MSHR miss cycles
735system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104788000 # number of LoadLockedReq MSHR miss cycles
736system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104788000 # number of LoadLockedReq MSHR miss cycles
737system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 510140000 # number of StoreCondReq MSHR miss cycles
738system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 510140000 # number of StoreCondReq MSHR miss cycles
739system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 641500 # number of StoreCondFailReq MSHR miss cycles
740system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles
741system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12322191000 # number of demand (read+write) MSHR miss cycles
742system.cpu0.dcache.demand_mshr_miss_latency::total 12322191000 # number of demand (read+write) MSHR miss cycles
743system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000 # number of overall MSHR miss cycles
744system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles
745system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles
746system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles

749system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5444959500 # number of WriteReq MSHR uncacheable cycles
750system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5444959500 # number of WriteReq MSHR uncacheable cycles
751system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12147316500 # number of overall MSHR uncacheable cycles
752system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12147316500 # number of overall MSHR uncacheable cycles

747system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6702357000 # number of overall MSHR uncacheable cycles
748system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6702357000 # number of overall MSHR uncacheable cycles

753system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses
754system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
755system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses
756system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses
757system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses
758system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses
759system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses
760system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses
761system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052217 # mshr miss rate for StoreCondReq accesses
762system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052217 # mshr miss rate for StoreCondReq accesses
763system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for demand accesses
764system.cpu0.dcache.demand_mshr_miss_rate::total 0.018093 # mshr miss rate for demand accesses
765system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020461 # mshr miss rate for overall accesses
766system.cpu0.dcache.overall_mshr_miss_rate::total 0.020461 # mshr miss rate for overall accesses
767system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.089432 # average ReadReq mshr miss latency
768system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.089432 # average ReadReq mshr miss latency
769system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20824.058968 # average WriteReq mshr miss latency
770system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20824.058968 # average WriteReq mshr miss latency
771system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16646.046778 # average SoftPFReq mshr miss latency
772system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16646.046778 # average SoftPFReq mshr miss latency
773system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.526541 # average LoadLockedReq mshr miss latency
774system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.526541 # average LoadLockedReq mshr miss latency
775system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24959.146729 # average StoreCondReq mshr miss latency
776system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24959.146729 # average StoreCondReq mshr miss latency
777system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
778system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
779system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency
780system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816 # average overall mshr miss latency
781system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency
782system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency
783system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency
784system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency

749system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses
750system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
751system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses
752system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses
753system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses
754system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses
755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses
756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses
757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052217 # mshr miss rate for StoreCondReq accesses
758system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052217 # mshr miss rate for StoreCondReq accesses
759system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for demand accesses
760system.cpu0.dcache.demand_mshr_miss_rate::total 0.018093 # mshr miss rate for demand accesses
761system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020461 # mshr miss rate for overall accesses
762system.cpu0.dcache.overall_mshr_miss_rate::total 0.020461 # mshr miss rate for overall accesses
763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.089432 # average ReadReq mshr miss latency
764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.089432 # average ReadReq mshr miss latency
765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20824.058968 # average WriteReq mshr miss latency
766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20824.058968 # average WriteReq mshr miss latency
767system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16646.046778 # average SoftPFReq mshr miss latency
768system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16646.046778 # average SoftPFReq mshr miss latency
769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.526541 # average LoadLockedReq mshr miss latency
770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.526541 # average LoadLockedReq mshr miss latency
771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24959.146729 # average StoreCondReq mshr miss latency
772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24959.146729 # average StoreCondReq mshr miss latency
773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency
776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816 # average overall mshr miss latency
777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency
778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency
779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency
780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency

785system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024 # average WriteReq mshr uncacheable latency
786system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024 # average WriteReq mshr uncacheable latency
787system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199903.177764 # average overall mshr uncacheable latency
788system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764 # average overall mshr uncacheable latency
789system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110297.814567 # average overall mshr uncacheable latency
782system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110297.814567 # average overall mshr uncacheable latency

790system.cpu0.icache.tags.replacements 2042425 # number of replacements
791system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use
792system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks.
793system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks.
794system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks.
795system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit.
796system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor
797system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy
798system.cpu0.icache.tags.occ_percent::total 0.999464 # Average percentage of cache occupancy
799system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
800system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
801system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
802system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id
803system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
804system.cpu0.icache.tags.tag_accesses 144672089 # Number of tag accesses
805system.cpu0.icache.tags.data_accesses 144672089 # Number of data accesses
806system.cpu0.icache.ReadReq_hits::cpu0.inst 69271608 # number of ReadReq hits
807system.cpu0.icache.ReadReq_hits::total 69271608 # number of ReadReq hits
808system.cpu0.icache.demand_hits::cpu0.inst 69271608 # number of demand (read+write) hits
809system.cpu0.icache.demand_hits::total 69271608 # number of demand (read+write) hits
810system.cpu0.icache.overall_hits::cpu0.inst 69271608 # number of overall hits
811system.cpu0.icache.overall_hits::total 69271608 # number of overall hits
812system.cpu0.icache.ReadReq_misses::cpu0.inst 2042958 # number of ReadReq misses
813system.cpu0.icache.ReadReq_misses::total 2042958 # number of ReadReq misses
814system.cpu0.icache.demand_misses::cpu0.inst 2042958 # number of demand (read+write) misses
815system.cpu0.icache.demand_misses::total 2042958 # number of demand (read+write) misses
816system.cpu0.icache.overall_misses::cpu0.inst 2042958 # number of overall misses
817system.cpu0.icache.overall_misses::total 2042958 # number of overall misses
818system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20578821000 # number of ReadReq miss cycles
819system.cpu0.icache.ReadReq_miss_latency::total 20578821000 # number of ReadReq miss cycles
820system.cpu0.icache.demand_miss_latency::cpu0.inst 20578821000 # number of demand (read+write) miss cycles
821system.cpu0.icache.demand_miss_latency::total 20578821000 # number of demand (read+write) miss cycles
822system.cpu0.icache.overall_miss_latency::cpu0.inst 20578821000 # number of overall miss cycles
823system.cpu0.icache.overall_miss_latency::total 20578821000 # number of overall miss cycles
824system.cpu0.icache.ReadReq_accesses::cpu0.inst 71314566 # number of ReadReq accesses(hits+misses)
825system.cpu0.icache.ReadReq_accesses::total 71314566 # number of ReadReq accesses(hits+misses)
826system.cpu0.icache.demand_accesses::cpu0.inst 71314566 # number of demand (read+write) accesses
827system.cpu0.icache.demand_accesses::total 71314566 # number of demand (read+write) accesses
828system.cpu0.icache.overall_accesses::cpu0.inst 71314566 # number of overall (read+write) accesses
829system.cpu0.icache.overall_accesses::total 71314566 # number of overall (read+write) accesses
830system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028647 # miss rate for ReadReq accesses
831system.cpu0.icache.ReadReq_miss_rate::total 0.028647 # miss rate for ReadReq accesses
832system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028647 # miss rate for demand accesses
833system.cpu0.icache.demand_miss_rate::total 0.028647 # miss rate for demand accesses
834system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028647 # miss rate for overall accesses
835system.cpu0.icache.overall_miss_rate::total 0.028647 # miss rate for overall accesses
836system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10073.051428 # average ReadReq miss latency
837system.cpu0.icache.ReadReq_avg_miss_latency::total 10073.051428 # average ReadReq miss latency
838system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency
839system.cpu0.icache.demand_avg_miss_latency::total 10073.051428 # average overall miss latency
840system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency
841system.cpu0.icache.overall_avg_miss_latency::total 10073.051428 # average overall miss latency
842system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
843system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
844system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
845system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
846system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
847system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

783system.cpu0.icache.tags.replacements 2042425 # number of replacements
784system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use
785system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks.
786system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks.
787system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks.
788system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit.
789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor
790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy
791system.cpu0.icache.tags.occ_percent::total 0.999464 # Average percentage of cache occupancy
792system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
793system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
794system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
795system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id
796system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
797system.cpu0.icache.tags.tag_accesses 144672089 # Number of tag accesses
798system.cpu0.icache.tags.data_accesses 144672089 # Number of data accesses
799system.cpu0.icache.ReadReq_hits::cpu0.inst 69271608 # number of ReadReq hits
800system.cpu0.icache.ReadReq_hits::total 69271608 # number of ReadReq hits
801system.cpu0.icache.demand_hits::cpu0.inst 69271608 # number of demand (read+write) hits
802system.cpu0.icache.demand_hits::total 69271608 # number of demand (read+write) hits
803system.cpu0.icache.overall_hits::cpu0.inst 69271608 # number of overall hits
804system.cpu0.icache.overall_hits::total 69271608 # number of overall hits
805system.cpu0.icache.ReadReq_misses::cpu0.inst 2042958 # number of ReadReq misses
806system.cpu0.icache.ReadReq_misses::total 2042958 # number of ReadReq misses
807system.cpu0.icache.demand_misses::cpu0.inst 2042958 # number of demand (read+write) misses
808system.cpu0.icache.demand_misses::total 2042958 # number of demand (read+write) misses
809system.cpu0.icache.overall_misses::cpu0.inst 2042958 # number of overall misses
810system.cpu0.icache.overall_misses::total 2042958 # number of overall misses
811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20578821000 # number of ReadReq miss cycles
812system.cpu0.icache.ReadReq_miss_latency::total 20578821000 # number of ReadReq miss cycles
813system.cpu0.icache.demand_miss_latency::cpu0.inst 20578821000 # number of demand (read+write) miss cycles
814system.cpu0.icache.demand_miss_latency::total 20578821000 # number of demand (read+write) miss cycles
815system.cpu0.icache.overall_miss_latency::cpu0.inst 20578821000 # number of overall miss cycles
816system.cpu0.icache.overall_miss_latency::total 20578821000 # number of overall miss cycles
817system.cpu0.icache.ReadReq_accesses::cpu0.inst 71314566 # number of ReadReq accesses(hits+misses)
818system.cpu0.icache.ReadReq_accesses::total 71314566 # number of ReadReq accesses(hits+misses)
819system.cpu0.icache.demand_accesses::cpu0.inst 71314566 # number of demand (read+write) accesses
820system.cpu0.icache.demand_accesses::total 71314566 # number of demand (read+write) accesses
821system.cpu0.icache.overall_accesses::cpu0.inst 71314566 # number of overall (read+write) accesses
822system.cpu0.icache.overall_accesses::total 71314566 # number of overall (read+write) accesses
823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028647 # miss rate for ReadReq accesses
824system.cpu0.icache.ReadReq_miss_rate::total 0.028647 # miss rate for ReadReq accesses
825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028647 # miss rate for demand accesses
826system.cpu0.icache.demand_miss_rate::total 0.028647 # miss rate for demand accesses
827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028647 # miss rate for overall accesses
828system.cpu0.icache.overall_miss_rate::total 0.028647 # miss rate for overall accesses
829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10073.051428 # average ReadReq miss latency
830system.cpu0.icache.ReadReq_avg_miss_latency::total 10073.051428 # average ReadReq miss latency
831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency
832system.cpu0.icache.demand_avg_miss_latency::total 10073.051428 # average overall miss latency
833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency
834system.cpu0.icache.overall_avg_miss_latency::total 10073.051428 # average overall miss latency
835system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
839system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

848system.cpu0.icache.fast_writes 0 # number of fast writes performed
849system.cpu0.icache.cache_copies 0 # number of cache copies performed

850system.cpu0.icache.writebacks::writebacks 2042425 # number of writebacks
851system.cpu0.icache.writebacks::total 2042425 # number of writebacks
852system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2042958 # number of ReadReq MSHR misses
853system.cpu0.icache.ReadReq_mshr_misses::total 2042958 # number of ReadReq MSHR misses
854system.cpu0.icache.demand_mshr_misses::cpu0.inst 2042958 # number of demand (read+write) MSHR misses
855system.cpu0.icache.demand_mshr_misses::total 2042958 # number of demand (read+write) MSHR misses
856system.cpu0.icache.overall_mshr_misses::cpu0.inst 2042958 # number of overall MSHR misses
857system.cpu0.icache.overall_mshr_misses::total 2042958 # number of overall MSHR misses
858system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable
859system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable
860system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses
861system.cpu0.icache.overall_mshr_uncacheable_misses::total 3917 # number of overall MSHR uncacheable misses
862system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19557342500 # number of ReadReq MSHR miss cycles
863system.cpu0.icache.ReadReq_mshr_miss_latency::total 19557342500 # number of ReadReq MSHR miss cycles
864system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19557342500 # number of demand (read+write) MSHR miss cycles
865system.cpu0.icache.demand_mshr_miss_latency::total 19557342500 # number of demand (read+write) MSHR miss cycles
866system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19557342500 # number of overall MSHR miss cycles
867system.cpu0.icache.overall_mshr_miss_latency::total 19557342500 # number of overall MSHR miss cycles
868system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles
869system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles
870system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles
871system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles
872system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for ReadReq accesses
873system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028647 # mshr miss rate for ReadReq accesses
874system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for demand accesses
875system.cpu0.icache.demand_mshr_miss_rate::total 0.028647 # mshr miss rate for demand accesses
876system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for overall accesses
877system.cpu0.icache.overall_mshr_miss_rate::total 0.028647 # mshr miss rate for overall accesses
878system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average ReadReq mshr miss latency
879system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9573.051673 # average ReadReq mshr miss latency
880system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
881system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
882system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
883system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
884system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency
885system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency
886system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency
887system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency

841system.cpu0.icache.writebacks::writebacks 2042425 # number of writebacks
842system.cpu0.icache.writebacks::total 2042425 # number of writebacks
843system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2042958 # number of ReadReq MSHR misses
844system.cpu0.icache.ReadReq_mshr_misses::total 2042958 # number of ReadReq MSHR misses
845system.cpu0.icache.demand_mshr_misses::cpu0.inst 2042958 # number of demand (read+write) MSHR misses
846system.cpu0.icache.demand_mshr_misses::total 2042958 # number of demand (read+write) MSHR misses
847system.cpu0.icache.overall_mshr_misses::cpu0.inst 2042958 # number of overall MSHR misses
848system.cpu0.icache.overall_mshr_misses::total 2042958 # number of overall MSHR misses
849system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable
850system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable
851system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses
852system.cpu0.icache.overall_mshr_uncacheable_misses::total 3917 # number of overall MSHR uncacheable misses
853system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19557342500 # number of ReadReq MSHR miss cycles
854system.cpu0.icache.ReadReq_mshr_miss_latency::total 19557342500 # number of ReadReq MSHR miss cycles
855system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19557342500 # number of demand (read+write) MSHR miss cycles
856system.cpu0.icache.demand_mshr_miss_latency::total 19557342500 # number of demand (read+write) MSHR miss cycles
857system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19557342500 # number of overall MSHR miss cycles
858system.cpu0.icache.overall_mshr_miss_latency::total 19557342500 # number of overall MSHR miss cycles
859system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles
860system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles
861system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles
862system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles
863system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for ReadReq accesses
864system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028647 # mshr miss rate for ReadReq accesses
865system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for demand accesses
866system.cpu0.icache.demand_mshr_miss_rate::total 0.028647 # mshr miss rate for demand accesses
867system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for overall accesses
868system.cpu0.icache.overall_mshr_miss_rate::total 0.028647 # mshr miss rate for overall accesses
869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average ReadReq mshr miss latency
870system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9573.051673 # average ReadReq mshr miss latency
871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
872system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
874system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency
876system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency
877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency
878system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency

888system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate

889system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued
890system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified
891system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue
892system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
893system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
894system.cpu0.l2cache.prefetcher.pfSpanPage 244697 # number of prefetches not generated due to page crossing
895system.cpu0.l2cache.tags.replacements 304900 # number of replacements
896system.cpu0.l2cache.tags.tagsinuse 16120.127106 # Cycle average of tags in use
897system.cpu0.l2cache.tags.total_refs 4899871 # Total number of references to valid blocks.
898system.cpu0.l2cache.tags.sampled_refs 321020 # Sample count of references to valid blocks.
899system.cpu0.l2cache.tags.avg_refs 15.263445 # Average number of references to valid blocks.
900system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
901system.cpu0.l2cache.tags.occ_blocks::writebacks 14747.855464 # Average occupied blocks per requestor
902system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.322901 # Average occupied blocks per requestor
903system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062340 # Average occupied blocks per requestor
904system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1306.886401 # Average occupied blocks per requestor
905system.cpu0.l2cache.tags.occ_percent::writebacks 0.900138 # Average percentage of cache occupancy
906system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003987 # Average percentage of cache occupancy
907system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
908system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.079766 # Average percentage of cache occupancy
909system.cpu0.l2cache.tags.occ_percent::total 0.983894 # Average percentage of cache occupancy
910system.cpu0.l2cache.tags.occ_task_id_blocks::1022 987 # Occupied blocks per task id
911system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
912system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15123 # Occupied blocks per task id
913system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
914system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 320 # Occupied blocks per task id
915system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 459 # Occupied blocks per task id
916system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 198 # Occupied blocks per task id
917system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
918system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
919system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
920system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id
921system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4117 # Occupied blocks per task id
922system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8290 # Occupied blocks per task id
923system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2270 # Occupied blocks per task id
924system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.060242 # Percentage of cache occupancy per task id
925system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
926system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923035 # Percentage of cache occupancy per task id
927system.cpu0.l2cache.tags.tag_accesses 93327543 # Number of tag accesses
928system.cpu0.l2cache.tags.data_accesses 93327543 # Number of data accesses
929system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 87658 # number of ReadReq hits
930system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5814 # number of ReadReq hits
931system.cpu0.l2cache.ReadReq_hits::total 93472 # number of ReadReq hits
932system.cpu0.l2cache.WritebackDirty_hits::writebacks 506036 # number of WritebackDirty hits
933system.cpu0.l2cache.WritebackDirty_hits::total 506036 # number of WritebackDirty hits
934system.cpu0.l2cache.WritebackClean_hits::writebacks 2249753 # number of WritebackClean hits
935system.cpu0.l2cache.WritebackClean_hits::total 2249753 # number of WritebackClean hits
936system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits
937system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
938system.cpu0.l2cache.ReadExReq_hits::cpu0.data 233559 # number of ReadExReq hits
939system.cpu0.l2cache.ReadExReq_hits::total 233559 # number of ReadExReq hits
940system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1972952 # number of ReadCleanReq hits
941system.cpu0.l2cache.ReadCleanReq_hits::total 1972952 # number of ReadCleanReq hits
942system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 430429 # number of ReadSharedReq hits
943system.cpu0.l2cache.ReadSharedReq_hits::total 430429 # number of ReadSharedReq hits
944system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 87658 # number of demand (read+write) hits
945system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5814 # number of demand (read+write) hits
946system.cpu0.l2cache.demand_hits::cpu0.inst 1972952 # number of demand (read+write) hits
947system.cpu0.l2cache.demand_hits::cpu0.data 663988 # number of demand (read+write) hits
948system.cpu0.l2cache.demand_hits::total 2730412 # number of demand (read+write) hits
949system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 87658 # number of overall hits
950system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5814 # number of overall hits
951system.cpu0.l2cache.overall_hits::cpu0.inst 1972952 # number of overall hits
952system.cpu0.l2cache.overall_hits::cpu0.data 663988 # number of overall hits
953system.cpu0.l2cache.overall_hits::total 2730412 # number of overall hits
954system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 757 # number of ReadReq misses
955system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses
956system.cpu0.l2cache.ReadReq_misses::total 854 # number of ReadReq misses
957system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56432 # number of UpgradeReq misses
958system.cpu0.l2cache.UpgradeReq_misses::total 56432 # number of UpgradeReq misses
959system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20439 # number of SCUpgradeReq misses
960system.cpu0.l2cache.SCUpgradeReq_misses::total 20439 # number of SCUpgradeReq misses
961system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47758 # number of ReadExReq misses
962system.cpu0.l2cache.ReadExReq_misses::total 47758 # number of ReadExReq misses
963system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70006 # number of ReadCleanReq misses
964system.cpu0.l2cache.ReadCleanReq_misses::total 70006 # number of ReadCleanReq misses
965system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100757 # number of ReadSharedReq misses
966system.cpu0.l2cache.ReadSharedReq_misses::total 100757 # number of ReadSharedReq misses
967system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 757 # number of demand (read+write) misses
968system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses
969system.cpu0.l2cache.demand_misses::cpu0.inst 70006 # number of demand (read+write) misses
970system.cpu0.l2cache.demand_misses::cpu0.data 148515 # number of demand (read+write) misses
971system.cpu0.l2cache.demand_misses::total 219375 # number of demand (read+write) misses
972system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 757 # number of overall misses
973system.cpu0.l2cache.overall_misses::cpu0.itb.walker 97 # number of overall misses
974system.cpu0.l2cache.overall_misses::cpu0.inst 70006 # number of overall misses
975system.cpu0.l2cache.overall_misses::cpu0.data 148515 # number of overall misses
976system.cpu0.l2cache.overall_misses::total 219375 # number of overall misses
977system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 36443000 # number of ReadReq miss cycles
978system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2415000 # number of ReadReq miss cycles
979system.cpu0.l2cache.ReadReq_miss_latency::total 38858000 # number of ReadReq miss cycles
980system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 190345500 # number of UpgradeReq miss cycles
981system.cpu0.l2cache.UpgradeReq_miss_latency::total 190345500 # number of UpgradeReq miss cycles
982system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 44203000 # number of SCUpgradeReq miss cycles
983system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 44203000 # number of SCUpgradeReq miss cycles
984system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 625500 # number of SCUpgradeFailReq miss cycles
985system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 625500 # number of SCUpgradeFailReq miss cycles
986system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3189953500 # number of ReadExReq miss cycles
987system.cpu0.l2cache.ReadExReq_miss_latency::total 3189953500 # number of ReadExReq miss cycles
988system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4522745000 # number of ReadCleanReq miss cycles
989system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4522745000 # number of ReadCleanReq miss cycles
990system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3552121999 # number of ReadSharedReq miss cycles
991system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3552121999 # number of ReadSharedReq miss cycles
992system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 36443000 # number of demand (read+write) miss cycles
993system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2415000 # number of demand (read+write) miss cycles
994system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4522745000 # number of demand (read+write) miss cycles
995system.cpu0.l2cache.demand_miss_latency::cpu0.data 6742075499 # number of demand (read+write) miss cycles
996system.cpu0.l2cache.demand_miss_latency::total 11303678499 # number of demand (read+write) miss cycles
997system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 36443000 # number of overall miss cycles
998system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2415000 # number of overall miss cycles
999system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4522745000 # number of overall miss cycles
1000system.cpu0.l2cache.overall_miss_latency::cpu0.data 6742075499 # number of overall miss cycles
1001system.cpu0.l2cache.overall_miss_latency::total 11303678499 # number of overall miss cycles
1002system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 88415 # number of ReadReq accesses(hits+misses)
1003system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5911 # number of ReadReq accesses(hits+misses)
1004system.cpu0.l2cache.ReadReq_accesses::total 94326 # number of ReadReq accesses(hits+misses)
1005system.cpu0.l2cache.WritebackDirty_accesses::writebacks 506036 # number of WritebackDirty accesses(hits+misses)
1006system.cpu0.l2cache.WritebackDirty_accesses::total 506036 # number of WritebackDirty accesses(hits+misses)
1007system.cpu0.l2cache.WritebackClean_accesses::writebacks 2249753 # number of WritebackClean accesses(hits+misses)
1008system.cpu0.l2cache.WritebackClean_accesses::total 2249753 # number of WritebackClean accesses(hits+misses)
1009system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56433 # number of UpgradeReq accesses(hits+misses)
1010system.cpu0.l2cache.UpgradeReq_accesses::total 56433 # number of UpgradeReq accesses(hits+misses)
1011system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20439 # number of SCUpgradeReq accesses(hits+misses)
1012system.cpu0.l2cache.SCUpgradeReq_accesses::total 20439 # number of SCUpgradeReq accesses(hits+misses)
1013system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 281317 # number of ReadExReq accesses(hits+misses)
1014system.cpu0.l2cache.ReadExReq_accesses::total 281317 # number of ReadExReq accesses(hits+misses)
1015system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2042958 # number of ReadCleanReq accesses(hits+misses)
1016system.cpu0.l2cache.ReadCleanReq_accesses::total 2042958 # number of ReadCleanReq accesses(hits+misses)
1017system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 531186 # number of ReadSharedReq accesses(hits+misses)
1018system.cpu0.l2cache.ReadSharedReq_accesses::total 531186 # number of ReadSharedReq accesses(hits+misses)
1019system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 88415 # number of demand (read+write) accesses
1020system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5911 # number of demand (read+write) accesses
1021system.cpu0.l2cache.demand_accesses::cpu0.inst 2042958 # number of demand (read+write) accesses
1022system.cpu0.l2cache.demand_accesses::cpu0.data 812503 # number of demand (read+write) accesses
1023system.cpu0.l2cache.demand_accesses::total 2949787 # number of demand (read+write) accesses
1024system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 88415 # number of overall (read+write) accesses
1025system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5911 # number of overall (read+write) accesses
1026system.cpu0.l2cache.overall_accesses::cpu0.inst 2042958 # number of overall (read+write) accesses
1027system.cpu0.l2cache.overall_accesses::cpu0.data 812503 # number of overall (read+write) accesses
1028system.cpu0.l2cache.overall_accesses::total 2949787 # number of overall (read+write) accesses
1029system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008562 # miss rate for ReadReq accesses
1030system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016410 # miss rate for ReadReq accesses
1031system.cpu0.l2cache.ReadReq_miss_rate::total 0.009054 # miss rate for ReadReq accesses
1032system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses
1033system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses
1034system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1035system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1036system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169766 # miss rate for ReadExReq accesses
1037system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169766 # miss rate for ReadExReq accesses
1038system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034267 # miss rate for ReadCleanReq accesses
1039system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034267 # miss rate for ReadCleanReq accesses
1040system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.189683 # miss rate for ReadSharedReq accesses
1041system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.189683 # miss rate for ReadSharedReq accesses
1042system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008562 # miss rate for demand accesses
1043system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016410 # miss rate for demand accesses
1044system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034267 # miss rate for demand accesses
1045system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.182787 # miss rate for demand accesses
1046system.cpu0.l2cache.demand_miss_rate::total 0.074370 # miss rate for demand accesses
1047system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008562 # miss rate for overall accesses
1048system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016410 # miss rate for overall accesses
1049system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034267 # miss rate for overall accesses
1050system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.182787 # miss rate for overall accesses
1051system.cpu0.l2cache.overall_miss_rate::total 0.074370 # miss rate for overall accesses
1052system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48141.347424 # average ReadReq miss latency
1053system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24896.907216 # average ReadReq miss latency
1054system.cpu0.l2cache.ReadReq_avg_miss_latency::total 45501.170960 # average ReadReq miss latency
1055system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3373.006450 # average UpgradeReq miss latency
1056system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3373.006450 # average UpgradeReq miss latency
1057system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2162.679192 # average SCUpgradeReq miss latency
1058system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2162.679192 # average SCUpgradeReq miss latency
1059system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
1060system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
1061system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66794.118263 # average ReadExReq miss latency
1062system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66794.118263 # average ReadExReq miss latency
1063system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64605.105277 # average ReadCleanReq miss latency
1064system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64605.105277 # average ReadCleanReq miss latency
1065system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35254.344601 # average ReadSharedReq miss latency
1066system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35254.344601 # average ReadSharedReq miss latency
1067system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48141.347424 # average overall miss latency
1068system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24896.907216 # average overall miss latency
1069system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64605.105277 # average overall miss latency
1070system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45396.596297 # average overall miss latency
1071system.cpu0.l2cache.demand_avg_miss_latency::total 51526.739597 # average overall miss latency
1072system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48141.347424 # average overall miss latency
1073system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24896.907216 # average overall miss latency
1074system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64605.105277 # average overall miss latency
1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45396.596297 # average overall miss latency
1076system.cpu0.l2cache.overall_avg_miss_latency::total 51526.739597 # average overall miss latency
1077system.cpu0.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked
1078system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1079system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1080system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1081system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1082system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

879system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued
880system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified
881system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue
882system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
883system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
884system.cpu0.l2cache.prefetcher.pfSpanPage 244697 # number of prefetches not generated due to page crossing
885system.cpu0.l2cache.tags.replacements 304900 # number of replacements
886system.cpu0.l2cache.tags.tagsinuse 16120.127106 # Cycle average of tags in use
887system.cpu0.l2cache.tags.total_refs 4899871 # Total number of references to valid blocks.
888system.cpu0.l2cache.tags.sampled_refs 321020 # Sample count of references to valid blocks.
889system.cpu0.l2cache.tags.avg_refs 15.263445 # Average number of references to valid blocks.
890system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
891system.cpu0.l2cache.tags.occ_blocks::writebacks 14747.855464 # Average occupied blocks per requestor
892system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.322901 # Average occupied blocks per requestor
893system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062340 # Average occupied blocks per requestor
894system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1306.886401 # Average occupied blocks per requestor
895system.cpu0.l2cache.tags.occ_percent::writebacks 0.900138 # Average percentage of cache occupancy
896system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003987 # Average percentage of cache occupancy
897system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
898system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.079766 # Average percentage of cache occupancy
899system.cpu0.l2cache.tags.occ_percent::total 0.983894 # Average percentage of cache occupancy
900system.cpu0.l2cache.tags.occ_task_id_blocks::1022 987 # Occupied blocks per task id
901system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
902system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15123 # Occupied blocks per task id
903system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
904system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 320 # Occupied blocks per task id
905system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 459 # Occupied blocks per task id
906system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 198 # Occupied blocks per task id
907system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
908system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
909system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
910system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id
911system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4117 # Occupied blocks per task id
912system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8290 # Occupied blocks per task id
913system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2270 # Occupied blocks per task id
914system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.060242 # Percentage of cache occupancy per task id
915system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
916system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923035 # Percentage of cache occupancy per task id
917system.cpu0.l2cache.tags.tag_accesses 93327543 # Number of tag accesses
918system.cpu0.l2cache.tags.data_accesses 93327543 # Number of data accesses
919system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 87658 # number of ReadReq hits
920system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5814 # number of ReadReq hits
921system.cpu0.l2cache.ReadReq_hits::total 93472 # number of ReadReq hits
922system.cpu0.l2cache.WritebackDirty_hits::writebacks 506036 # number of WritebackDirty hits
923system.cpu0.l2cache.WritebackDirty_hits::total 506036 # number of WritebackDirty hits
924system.cpu0.l2cache.WritebackClean_hits::writebacks 2249753 # number of WritebackClean hits
925system.cpu0.l2cache.WritebackClean_hits::total 2249753 # number of WritebackClean hits
926system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits
927system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
928system.cpu0.l2cache.ReadExReq_hits::cpu0.data 233559 # number of ReadExReq hits
929system.cpu0.l2cache.ReadExReq_hits::total 233559 # number of ReadExReq hits
930system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1972952 # number of ReadCleanReq hits
931system.cpu0.l2cache.ReadCleanReq_hits::total 1972952 # number of ReadCleanReq hits
932system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 430429 # number of ReadSharedReq hits
933system.cpu0.l2cache.ReadSharedReq_hits::total 430429 # number of ReadSharedReq hits
934system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 87658 # number of demand (read+write) hits
935system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5814 # number of demand (read+write) hits
936system.cpu0.l2cache.demand_hits::cpu0.inst 1972952 # number of demand (read+write) hits
937system.cpu0.l2cache.demand_hits::cpu0.data 663988 # number of demand (read+write) hits
938system.cpu0.l2cache.demand_hits::total 2730412 # number of demand (read+write) hits
939system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 87658 # number of overall hits
940system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5814 # number of overall hits
941system.cpu0.l2cache.overall_hits::cpu0.inst 1972952 # number of overall hits
942system.cpu0.l2cache.overall_hits::cpu0.data 663988 # number of overall hits
943system.cpu0.l2cache.overall_hits::total 2730412 # number of overall hits
944system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 757 # number of ReadReq misses
945system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses
946system.cpu0.l2cache.ReadReq_misses::total 854 # number of ReadReq misses
947system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56432 # number of UpgradeReq misses
948system.cpu0.l2cache.UpgradeReq_misses::total 56432 # number of UpgradeReq misses
949system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20439 # number of SCUpgradeReq misses
950system.cpu0.l2cache.SCUpgradeReq_misses::total 20439 # number of SCUpgradeReq misses
951system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47758 # number of ReadExReq misses
952system.cpu0.l2cache.ReadExReq_misses::total 47758 # number of ReadExReq misses
953system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70006 # number of ReadCleanReq misses
954system.cpu0.l2cache.ReadCleanReq_misses::total 70006 # number of ReadCleanReq misses
955system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100757 # number of ReadSharedReq misses
956system.cpu0.l2cache.ReadSharedReq_misses::total 100757 # number of ReadSharedReq misses
957system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 757 # number of demand (read+write) misses
958system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses
959system.cpu0.l2cache.demand_misses::cpu0.inst 70006 # number of demand (read+write) misses
960system.cpu0.l2cache.demand_misses::cpu0.data 148515 # number of demand (read+write) misses
961system.cpu0.l2cache.demand_misses::total 219375 # number of demand (read+write) misses
962system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 757 # number of overall misses
963system.cpu0.l2cache.overall_misses::cpu0.itb.walker 97 # number of overall misses
964system.cpu0.l2cache.overall_misses::cpu0.inst 70006 # number of overall misses
965system.cpu0.l2cache.overall_misses::cpu0.data 148515 # number of overall misses
966system.cpu0.l2cache.overall_misses::total 219375 # number of overall misses
967system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 36443000 # number of ReadReq miss cycles
968system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2415000 # number of ReadReq miss cycles
969system.cpu0.l2cache.ReadReq_miss_latency::total 38858000 # number of ReadReq miss cycles
970system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 190345500 # number of UpgradeReq miss cycles
971system.cpu0.l2cache.UpgradeReq_miss_latency::total 190345500 # number of UpgradeReq miss cycles
972system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 44203000 # number of SCUpgradeReq miss cycles
973system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 44203000 # number of SCUpgradeReq miss cycles
974system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 625500 # number of SCUpgradeFailReq miss cycles
975system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 625500 # number of SCUpgradeFailReq miss cycles
976system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3189953500 # number of ReadExReq miss cycles
977system.cpu0.l2cache.ReadExReq_miss_latency::total 3189953500 # number of ReadExReq miss cycles
978system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4522745000 # number of ReadCleanReq miss cycles
979system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4522745000 # number of ReadCleanReq miss cycles
980system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3552121999 # number of ReadSharedReq miss cycles
981system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3552121999 # number of ReadSharedReq miss cycles
982system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 36443000 # number of demand (read+write) miss cycles
983system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2415000 # number of demand (read+write) miss cycles
984system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4522745000 # number of demand (read+write) miss cycles
985system.cpu0.l2cache.demand_miss_latency::cpu0.data 6742075499 # number of demand (read+write) miss cycles
986system.cpu0.l2cache.demand_miss_latency::total 11303678499 # number of demand (read+write) miss cycles
987system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 36443000 # number of overall miss cycles
988system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2415000 # number of overall miss cycles
989system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4522745000 # number of overall miss cycles
990system.cpu0.l2cache.overall_miss_latency::cpu0.data 6742075499 # number of overall miss cycles
991system.cpu0.l2cache.overall_miss_latency::total 11303678499 # number of overall miss cycles
992system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 88415 # number of ReadReq accesses(hits+misses)
993system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5911 # number of ReadReq accesses(hits+misses)
994system.cpu0.l2cache.ReadReq_accesses::total 94326 # number of ReadReq accesses(hits+misses)
995system.cpu0.l2cache.WritebackDirty_accesses::writebacks 506036 # number of WritebackDirty accesses(hits+misses)
996system.cpu0.l2cache.WritebackDirty_accesses::total 506036 # number of WritebackDirty accesses(hits+misses)
997system.cpu0.l2cache.WritebackClean_accesses::writebacks 2249753 # number of WritebackClean accesses(hits+misses)
998system.cpu0.l2cache.WritebackClean_accesses::total 2249753 # number of WritebackClean accesses(hits+misses)
999system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56433 # number of UpgradeReq accesses(hits+misses)
1000system.cpu0.l2cache.UpgradeReq_accesses::total 56433 # number of UpgradeReq accesses(hits+misses)
1001system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20439 # number of SCUpgradeReq accesses(hits+misses)
1002system.cpu0.l2cache.SCUpgradeReq_accesses::total 20439 # number of SCUpgradeReq accesses(hits+misses)
1003system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 281317 # number of ReadExReq accesses(hits+misses)
1004system.cpu0.l2cache.ReadExReq_accesses::total 281317 # number of ReadExReq accesses(hits+misses)
1005system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2042958 # number of ReadCleanReq accesses(hits+misses)
1006system.cpu0.l2cache.ReadCleanReq_accesses::total 2042958 # number of ReadCleanReq accesses(hits+misses)
1007system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 531186 # number of ReadSharedReq accesses(hits+misses)
1008system.cpu0.l2cache.ReadSharedReq_accesses::total 531186 # number of ReadSharedReq accesses(hits+misses)
1009system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 88415 # number of demand (read+write) accesses
1010system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5911 # number of demand (read+write) accesses
1011system.cpu0.l2cache.demand_accesses::cpu0.inst 2042958 # number of demand (read+write) accesses
1012system.cpu0.l2cache.demand_accesses::cpu0.data 812503 # number of demand (read+write) accesses
1013system.cpu0.l2cache.demand_accesses::total 2949787 # number of demand (read+write) accesses
1014system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 88415 # number of overall (read+write) accesses
1015system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5911 # number of overall (read+write) accesses
1016system.cpu0.l2cache.overall_accesses::cpu0.inst 2042958 # number of overall (read+write) accesses
1017system.cpu0.l2cache.overall_accesses::cpu0.data 812503 # number of overall (read+write) accesses
1018system.cpu0.l2cache.overall_accesses::total 2949787 # number of overall (read+write) accesses
1019system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008562 # miss rate for ReadReq accesses
1020system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016410 # miss rate for ReadReq accesses
1021system.cpu0.l2cache.ReadReq_miss_rate::total 0.009054 # miss rate for ReadReq accesses
1022system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses
1023system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses
1024system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1025system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1026system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169766 # miss rate for ReadExReq accesses
1027system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169766 # miss rate for ReadExReq accesses
1028system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034267 # miss rate for ReadCleanReq accesses
1029system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034267 # miss rate for ReadCleanReq accesses
1030system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.189683 # miss rate for ReadSharedReq accesses
1031system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.189683 # miss rate for ReadSharedReq accesses
1032system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008562 # miss rate for demand accesses
1033system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016410 # miss rate for demand accesses
1034system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034267 # miss rate for demand accesses
1035system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.182787 # miss rate for demand accesses
1036system.cpu0.l2cache.demand_miss_rate::total 0.074370 # miss rate for demand accesses
1037system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008562 # miss rate for overall accesses
1038system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016410 # miss rate for overall accesses
1039system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034267 # miss rate for overall accesses
1040system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.182787 # miss rate for overall accesses
1041system.cpu0.l2cache.overall_miss_rate::total 0.074370 # miss rate for overall accesses
1042system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48141.347424 # average ReadReq miss latency
1043system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24896.907216 # average ReadReq miss latency
1044system.cpu0.l2cache.ReadReq_avg_miss_latency::total 45501.170960 # average ReadReq miss latency
1045system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3373.006450 # average UpgradeReq miss latency
1046system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3373.006450 # average UpgradeReq miss latency
1047system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2162.679192 # average SCUpgradeReq miss latency
1048system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2162.679192 # average SCUpgradeReq miss latency
1049system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
1050system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
1051system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66794.118263 # average ReadExReq miss latency
1052system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66794.118263 # average ReadExReq miss latency
1053system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64605.105277 # average ReadCleanReq miss latency
1054system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64605.105277 # average ReadCleanReq miss latency
1055system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35254.344601 # average ReadSharedReq miss latency
1056system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35254.344601 # average ReadSharedReq miss latency
1057system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48141.347424 # average overall miss latency
1058system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24896.907216 # average overall miss latency
1059system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64605.105277 # average overall miss latency
1060system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45396.596297 # average overall miss latency
1061system.cpu0.l2cache.demand_avg_miss_latency::total 51526.739597 # average overall miss latency
1062system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48141.347424 # average overall miss latency
1063system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24896.907216 # average overall miss latency
1064system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64605.105277 # average overall miss latency
1065system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45396.596297 # average overall miss latency
1066system.cpu0.l2cache.overall_avg_miss_latency::total 51526.739597 # average overall miss latency
1067system.cpu0.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked
1068system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1069system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1070system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1071system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1072system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1083system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1084system.cpu0.l2cache.cache_copies 0 # number of cache copies performed

1085system.cpu0.l2cache.unused_prefetches 10897 # number of HardPF blocks evicted w/o reference
1086system.cpu0.l2cache.writebacks::writebacks 237171 # number of writebacks
1087system.cpu0.l2cache.writebacks::total 237171 # number of writebacks
1088system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5426 # number of ReadExReq MSHR hits
1089system.cpu0.l2cache.ReadExReq_mshr_hits::total 5426 # number of ReadExReq MSHR hits
1090system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 72 # number of ReadCleanReq MSHR hits
1091system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 72 # number of ReadCleanReq MSHR hits
1092system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 591 # number of ReadSharedReq MSHR hits
1093system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 591 # number of ReadSharedReq MSHR hits
1094system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 72 # number of demand (read+write) MSHR hits
1095system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6017 # number of demand (read+write) MSHR hits
1096system.cpu0.l2cache.demand_mshr_hits::total 6089 # number of demand (read+write) MSHR hits
1097system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 72 # number of overall MSHR hits
1098system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6017 # number of overall MSHR hits
1099system.cpu0.l2cache.overall_mshr_hits::total 6089 # number of overall MSHR hits
1100system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 757 # number of ReadReq MSHR misses
1101system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 97 # number of ReadReq MSHR misses
1102system.cpu0.l2cache.ReadReq_mshr_misses::total 854 # number of ReadReq MSHR misses
1103system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264383 # number of HardPFReq MSHR misses
1104system.cpu0.l2cache.HardPFReq_mshr_misses::total 264383 # number of HardPFReq MSHR misses
1105system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56432 # number of UpgradeReq MSHR misses
1106system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56432 # number of UpgradeReq MSHR misses
1107system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20439 # number of SCUpgradeReq MSHR misses
1108system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20439 # number of SCUpgradeReq MSHR misses
1109system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42332 # number of ReadExReq MSHR misses
1110system.cpu0.l2cache.ReadExReq_mshr_misses::total 42332 # number of ReadExReq MSHR misses
1111system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 69934 # number of ReadCleanReq MSHR misses
1112system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 69934 # number of ReadCleanReq MSHR misses
1113system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100166 # number of ReadSharedReq MSHR misses
1114system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100166 # number of ReadSharedReq MSHR misses
1115system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 757 # number of demand (read+write) MSHR misses
1116system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 97 # number of demand (read+write) MSHR misses
1117system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69934 # number of demand (read+write) MSHR misses
1118system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142498 # number of demand (read+write) MSHR misses
1119system.cpu0.l2cache.demand_mshr_misses::total 213286 # number of demand (read+write) MSHR misses
1120system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 757 # number of overall MSHR misses
1121system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 97 # number of overall MSHR misses
1122system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69934 # number of overall MSHR misses
1123system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142498 # number of overall MSHR misses
1124system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264383 # number of overall MSHR misses
1125system.cpu0.l2cache.overall_mshr_misses::total 477669 # number of overall MSHR misses
1126system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable
1127system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32042 # number of ReadReq MSHR uncacheable
1128system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35959 # number of ReadReq MSHR uncacheable
1129system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable
1130system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable
1131system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses
1132system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60766 # number of overall MSHR uncacheable misses
1133system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 64683 # number of overall MSHR uncacheable misses
1134system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 31901000 # number of ReadReq MSHR miss cycles
1135system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1833000 # number of ReadReq MSHR miss cycles
1136system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33734000 # number of ReadReq MSHR miss cycles
1137system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21051299430 # number of HardPFReq MSHR miss cycles
1138system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21051299430 # number of HardPFReq MSHR miss cycles
1139system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1467303000 # number of UpgradeReq MSHR miss cycles
1140system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1467303000 # number of UpgradeReq MSHR miss cycles
1141system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 356079000 # number of SCUpgradeReq MSHR miss cycles
1142system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 356079000 # number of SCUpgradeReq MSHR miss cycles
1143system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 565500 # number of SCUpgradeFailReq MSHR miss cycles
1144system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 565500 # number of SCUpgradeFailReq MSHR miss cycles
1145system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2440300000 # number of ReadExReq MSHR miss cycles
1146system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2440300000 # number of ReadExReq MSHR miss cycles
1147system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4100378000 # number of ReadCleanReq MSHR miss cycles
1148system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4100378000 # number of ReadCleanReq MSHR miss cycles
1149system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2916947999 # number of ReadSharedReq MSHR miss cycles
1150system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2916947999 # number of ReadSharedReq MSHR miss cycles
1151system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 31901000 # number of demand (read+write) MSHR miss cycles
1152system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1833000 # number of demand (read+write) MSHR miss cycles
1153system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4100378000 # number of demand (read+write) MSHR miss cycles
1154system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5357247999 # number of demand (read+write) MSHR miss cycles
1155system.cpu0.l2cache.demand_mshr_miss_latency::total 9491359999 # number of demand (read+write) MSHR miss cycles
1156system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 31901000 # number of overall MSHR miss cycles
1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1833000 # number of overall MSHR miss cycles
1158system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4100378000 # number of overall MSHR miss cycles
1159system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5357247999 # number of overall MSHR miss cycles
1160system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21051299430 # number of overall MSHR miss cycles
1161system.cpu0.l2cache.overall_mshr_miss_latency::total 30542659429 # number of overall MSHR miss cycles
1162system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles
1163system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445890500 # number of ReadReq MSHR uncacheable cycles
1164system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971910500 # number of ReadReq MSHR uncacheable cycles

1073system.cpu0.l2cache.unused_prefetches 10897 # number of HardPF blocks evicted w/o reference
1074system.cpu0.l2cache.writebacks::writebacks 237171 # number of writebacks
1075system.cpu0.l2cache.writebacks::total 237171 # number of writebacks
1076system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5426 # number of ReadExReq MSHR hits
1077system.cpu0.l2cache.ReadExReq_mshr_hits::total 5426 # number of ReadExReq MSHR hits
1078system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 72 # number of ReadCleanReq MSHR hits
1079system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 72 # number of ReadCleanReq MSHR hits
1080system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 591 # number of ReadSharedReq MSHR hits
1081system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 591 # number of ReadSharedReq MSHR hits
1082system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 72 # number of demand (read+write) MSHR hits
1083system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6017 # number of demand (read+write) MSHR hits
1084system.cpu0.l2cache.demand_mshr_hits::total 6089 # number of demand (read+write) MSHR hits
1085system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 72 # number of overall MSHR hits
1086system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6017 # number of overall MSHR hits
1087system.cpu0.l2cache.overall_mshr_hits::total 6089 # number of overall MSHR hits
1088system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 757 # number of ReadReq MSHR misses
1089system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 97 # number of ReadReq MSHR misses
1090system.cpu0.l2cache.ReadReq_mshr_misses::total 854 # number of ReadReq MSHR misses
1091system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264383 # number of HardPFReq MSHR misses
1092system.cpu0.l2cache.HardPFReq_mshr_misses::total 264383 # number of HardPFReq MSHR misses
1093system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56432 # number of UpgradeReq MSHR misses
1094system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56432 # number of UpgradeReq MSHR misses
1095system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20439 # number of SCUpgradeReq MSHR misses
1096system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20439 # number of SCUpgradeReq MSHR misses
1097system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42332 # number of ReadExReq MSHR misses
1098system.cpu0.l2cache.ReadExReq_mshr_misses::total 42332 # number of ReadExReq MSHR misses
1099system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 69934 # number of ReadCleanReq MSHR misses
1100system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 69934 # number of ReadCleanReq MSHR misses
1101system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100166 # number of ReadSharedReq MSHR misses
1102system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100166 # number of ReadSharedReq MSHR misses
1103system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 757 # number of demand (read+write) MSHR misses
1104system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 97 # number of demand (read+write) MSHR misses
1105system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69934 # number of demand (read+write) MSHR misses
1106system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142498 # number of demand (read+write) MSHR misses
1107system.cpu0.l2cache.demand_mshr_misses::total 213286 # number of demand (read+write) MSHR misses
1108system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 757 # number of overall MSHR misses
1109system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 97 # number of overall MSHR misses
1110system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69934 # number of overall MSHR misses
1111system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142498 # number of overall MSHR misses
1112system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264383 # number of overall MSHR misses
1113system.cpu0.l2cache.overall_mshr_misses::total 477669 # number of overall MSHR misses
1114system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable
1115system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32042 # number of ReadReq MSHR uncacheable
1116system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35959 # number of ReadReq MSHR uncacheable
1117system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable
1118system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable
1119system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses
1120system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60766 # number of overall MSHR uncacheable misses
1121system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 64683 # number of overall MSHR uncacheable misses
1122system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 31901000 # number of ReadReq MSHR miss cycles
1123system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1833000 # number of ReadReq MSHR miss cycles
1124system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33734000 # number of ReadReq MSHR miss cycles
1125system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21051299430 # number of HardPFReq MSHR miss cycles
1126system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21051299430 # number of HardPFReq MSHR miss cycles
1127system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1467303000 # number of UpgradeReq MSHR miss cycles
1128system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1467303000 # number of UpgradeReq MSHR miss cycles
1129system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 356079000 # number of SCUpgradeReq MSHR miss cycles
1130system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 356079000 # number of SCUpgradeReq MSHR miss cycles
1131system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 565500 # number of SCUpgradeFailReq MSHR miss cycles
1132system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 565500 # number of SCUpgradeFailReq MSHR miss cycles
1133system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2440300000 # number of ReadExReq MSHR miss cycles
1134system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2440300000 # number of ReadExReq MSHR miss cycles
1135system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4100378000 # number of ReadCleanReq MSHR miss cycles
1136system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4100378000 # number of ReadCleanReq MSHR miss cycles
1137system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2916947999 # number of ReadSharedReq MSHR miss cycles
1138system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2916947999 # number of ReadSharedReq MSHR miss cycles
1139system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 31901000 # number of demand (read+write) MSHR miss cycles
1140system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1833000 # number of demand (read+write) MSHR miss cycles
1141system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4100378000 # number of demand (read+write) MSHR miss cycles
1142system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5357247999 # number of demand (read+write) MSHR miss cycles
1143system.cpu0.l2cache.demand_mshr_miss_latency::total 9491359999 # number of demand (read+write) MSHR miss cycles
1144system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 31901000 # number of overall MSHR miss cycles
1145system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1833000 # number of overall MSHR miss cycles
1146system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4100378000 # number of overall MSHR miss cycles
1147system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5357247999 # number of overall MSHR miss cycles
1148system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21051299430 # number of overall MSHR miss cycles
1149system.cpu0.l2cache.overall_mshr_miss_latency::total 30542659429 # number of overall MSHR miss cycles
1150system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles
1151system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445890500 # number of ReadReq MSHR uncacheable cycles
1152system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971910500 # number of ReadReq MSHR uncacheable cycles

1165system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5229022000 # number of WriteReq MSHR uncacheable cycles
1166system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5229022000 # number of WriteReq MSHR uncacheable cycles

1167system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles

1153system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles

1168system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11674912500 # number of overall MSHR uncacheable cycles
1169system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12200932500 # number of overall MSHR uncacheable cycles

1154system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6445890500 # number of overall MSHR uncacheable cycles
1155system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6971910500 # number of overall MSHR uncacheable cycles

1170system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for ReadReq accesses
1171system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for ReadReq accesses
1172system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009054 # mshr miss rate for ReadReq accesses
1173system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1174system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1175system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1176system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1177system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1178system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1179system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150478 # mshr miss rate for ReadExReq accesses
1180system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150478 # mshr miss rate for ReadExReq accesses
1181system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for ReadCleanReq accesses
1182system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034232 # mshr miss rate for ReadCleanReq accesses
1183system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188570 # mshr miss rate for ReadSharedReq accesses
1184system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188570 # mshr miss rate for ReadSharedReq accesses
1185system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for demand accesses
1186system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for demand accesses
1187system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for demand accesses
1188system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for demand accesses
1189system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072306 # mshr miss rate for demand accesses
1190system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for overall accesses
1191system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for overall accesses
1192system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for overall accesses
1193system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for overall accesses
1194system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1195system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161933 # mshr miss rate for overall accesses
1196system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average ReadReq mshr miss latency
1197system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average ReadReq mshr miss latency
1198system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 39501.170960 # average ReadReq mshr miss latency
1199system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average HardPFReq mshr miss latency
1200system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79624.255077 # average HardPFReq mshr miss latency
1201system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26001.258151 # average UpgradeReq mshr miss latency
1202system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26001.258151 # average UpgradeReq mshr miss latency
1203system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.547042 # average SCUpgradeReq mshr miss latency
1204system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17421.547042 # average SCUpgradeReq mshr miss latency
1205system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
1206system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
1207system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57646.697534 # average ReadExReq mshr miss latency
1208system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57646.697534 # average ReadExReq mshr miss latency
1209system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average ReadCleanReq mshr miss latency
1210system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58632.110275 # average ReadCleanReq mshr miss latency
1211system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29121.138899 # average ReadSharedReq mshr miss latency
1212system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29121.138899 # average ReadSharedReq mshr miss latency
1213system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency
1214system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
1215system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
1216system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
1217system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44500.623571 # average overall mshr miss latency
1218system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency
1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency
1223system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency
1224system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency
1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency
1226system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency

1156system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for ReadReq accesses
1157system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for ReadReq accesses
1158system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009054 # mshr miss rate for ReadReq accesses
1159system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1160system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1161system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1162system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1163system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1164system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1165system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150478 # mshr miss rate for ReadExReq accesses
1166system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150478 # mshr miss rate for ReadExReq accesses
1167system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for ReadCleanReq accesses
1168system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034232 # mshr miss rate for ReadCleanReq accesses
1169system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188570 # mshr miss rate for ReadSharedReq accesses
1170system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188570 # mshr miss rate for ReadSharedReq accesses
1171system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for demand accesses
1172system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for demand accesses
1173system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for demand accesses
1174system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for demand accesses
1175system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072306 # mshr miss rate for demand accesses
1176system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for overall accesses
1177system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for overall accesses
1178system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for overall accesses
1179system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for overall accesses
1180system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1181system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161933 # mshr miss rate for overall accesses
1182system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average ReadReq mshr miss latency
1183system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average ReadReq mshr miss latency
1184system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 39501.170960 # average ReadReq mshr miss latency
1185system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average HardPFReq mshr miss latency
1186system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79624.255077 # average HardPFReq mshr miss latency
1187system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26001.258151 # average UpgradeReq mshr miss latency
1188system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26001.258151 # average UpgradeReq mshr miss latency
1189system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.547042 # average SCUpgradeReq mshr miss latency
1190system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17421.547042 # average SCUpgradeReq mshr miss latency
1191system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
1192system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
1193system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57646.697534 # average ReadExReq mshr miss latency
1194system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57646.697534 # average ReadExReq mshr miss latency
1195system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average ReadCleanReq mshr miss latency
1196system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58632.110275 # average ReadCleanReq mshr miss latency
1197system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29121.138899 # average ReadSharedReq mshr miss latency
1198system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29121.138899 # average ReadSharedReq mshr miss latency
1199system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency
1200system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
1201system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
1202system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
1203system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44500.623571 # average overall mshr miss latency
1204system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency
1205system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
1206system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
1207system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
1208system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency
1209system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency
1210system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency
1211system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency
1212system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency

1227system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872 # average WriteReq mshr uncacheable latency
1228system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872 # average WriteReq mshr uncacheable latency

1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency

1213system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency

1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746 # average overall mshr uncacheable latency
1231system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124 # average overall mshr uncacheable latency
1232system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

1214system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 106077.255373 # average overall mshr uncacheable latency
1215system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 107785.824714 # average overall mshr uncacheable latency

1233system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter.
1234system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1235system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1236system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter.
1237system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1238system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1239system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution
1240system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution
1241system.cpu0.toL2Bus.trans_dist::WriteReq 28724 # Transaction distribution
1242system.cpu0.toL2Bus.trans_dist::WriteResp 28724 # Transaction distribution
1243system.cpu0.toL2Bus.trans_dist::WritebackDirty 743774 # Transaction distribution
1244system.cpu0.toL2Bus.trans_dist::WritebackClean 2294086 # Transaction distribution
1245system.cpu0.toL2Bus.trans_dist::CleanEvict 245615 # Transaction distribution
1246system.cpu0.toL2Bus.trans_dist::HardPFReq 332229 # Transaction distribution
1247system.cpu0.toL2Bus.trans_dist::UpgradeReq 86791 # Transaction distribution
1248system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42912 # Transaction distribution
1249system.cpu0.toL2Bus.trans_dist::UpgradeResp 113818 # Transaction distribution
1250system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
1251system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
1252system.cpu0.toL2Bus.trans_dist::ReadExReq 300259 # Transaction distribution
1253system.cpu0.toL2Bus.trans_dist::ReadExResp 296935 # Transaction distribution
1254system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2042958 # Transaction distribution
1255system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604813 # Transaction distribution
1256system.cpu0.toL2Bus.trans_dist::InvalidateReq 3110 # Transaction distribution
1257system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6136174 # Packet count per connected master and slave (bytes)
1258system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2759564 # Packet count per connected master and slave (bytes)
1259system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14116 # Packet count per connected master and slave (bytes)
1260system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185351 # Packet count per connected master and slave (bytes)
1261system.cpu0.toL2Bus.pkt_count::total 9095205 # Packet count per connected master and slave (bytes)
1262system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261715136 # Cumulative packet size per connected master and slave (bytes)
1263system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104822354 # Cumulative packet size per connected master and slave (bytes)
1264system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23644 # Cumulative packet size per connected master and slave (bytes)
1265system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 353660 # Cumulative packet size per connected master and slave (bytes)
1266system.cpu0.toL2Bus.pkt_size::total 366914794 # Cumulative packet size per connected master and slave (bytes)
1267system.cpu0.toL2Bus.snoops 1076546 # Total snoops (count)
1268system.cpu0.toL2Bus.snoop_fanout::samples 4066304 # Request fanout histogram
1269system.cpu0.toL2Bus.snoop_fanout::mean 0.104124 # Request fanout histogram
1270system.cpu0.toL2Bus.snoop_fanout::stdev 0.309432 # Request fanout histogram
1271system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1272system.cpu0.toL2Bus.snoop_fanout::0 3647917 89.71% 89.71% # Request fanout histogram
1273system.cpu0.toL2Bus.snoop_fanout::1 413374 10.17% 99.88% # Request fanout histogram
1274system.cpu0.toL2Bus.snoop_fanout::2 5013 0.12% 100.00% # Request fanout histogram
1275system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1276system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1277system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1278system.cpu0.toL2Bus.snoop_fanout::total 4066304 # Request fanout histogram
1279system.cpu0.toL2Bus.reqLayer0.occupancy 5765624998 # Layer occupancy (ticks)
1280system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1281system.cpu0.toL2Bus.snoopLayer0.occupancy 115477021 # Layer occupancy (ticks)
1282system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1283system.cpu0.toL2Bus.respLayer0.occupancy 3070848423 # Layer occupancy (ticks)
1284system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1285system.cpu0.toL2Bus.respLayer1.occupancy 1304480252 # Layer occupancy (ticks)
1286system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1287system.cpu0.toL2Bus.respLayer2.occupancy 8215479 # Layer occupancy (ticks)
1288system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1289system.cpu0.toL2Bus.respLayer3.occupancy 96957457 # Layer occupancy (ticks)
1290system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1291system.cpu1.branchPred.lookups 3600044 # Number of BP lookups
1292system.cpu1.branchPred.condPredicted 2023819 # Number of conditional branches predicted
1293system.cpu1.branchPred.condIncorrect 196135 # Number of conditional branches incorrect
1294system.cpu1.branchPred.BTBLookups 2284720 # Number of BTB lookups
1295system.cpu1.branchPred.BTBHits 1344428 # Number of BTB hits
1296system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1297system.cpu1.branchPred.BTBHitPct 58.844322 # BTB Hit Percentage
1298system.cpu1.branchPred.usedRAS 748131 # Number of times the RAS was used to get a target.
1299system.cpu1.branchPred.RASInCorrect 53981 # Number of incorrect RAS predictions.
1300system.cpu1.branchPred.indirectLookups 144785 # Number of indirect predictor lookups.
1301system.cpu1.branchPred.indirectHits 107908 # Number of indirect target hits.
1302system.cpu1.branchPred.indirectMisses 36877 # Number of indirect misses.
1303system.cpu1.branchPredindirectMispredicted 17103 # Number of mispredicted indirect branches.
1304system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1305system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1306system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1307system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1308system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1309system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1310system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1311system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1312system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1313system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1314system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1315system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1316system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1317system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1318system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1319system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1320system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1321system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1322system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1323system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1324system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1325system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1326system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1327system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1328system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1329system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1330system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1331system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1332system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1333system.cpu1.dtb.walker.walks 22955 # Table walker walks requested
1334system.cpu1.dtb.walker.walksShort 22955 # Table walker walks initiated with short descriptors
1335system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18858 # Level at which table walker walks with short descriptors terminate
1336system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4097 # Level at which table walker walks with short descriptors terminate
1337system.cpu1.dtb.walker.walkWaitTime::samples 22955 # Table walker wait (enqueue to first request) latency
1338system.cpu1.dtb.walker.walkWaitTime::0 22955 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1339system.cpu1.dtb.walker.walkWaitTime::total 22955 # Table walker wait (enqueue to first request) latency
1340system.cpu1.dtb.walker.walkCompletionTime::samples 1846 # Table walker service (enqueue to completion) latency
1341system.cpu1.dtb.walker.walkCompletionTime::mean 11730.498375 # Table walker service (enqueue to completion) latency
1342system.cpu1.dtb.walker.walkCompletionTime::gmean 11025.049339 # Table walker service (enqueue to completion) latency
1343system.cpu1.dtb.walker.walkCompletionTime::stdev 6418.983235 # Table walker service (enqueue to completion) latency
1344system.cpu1.dtb.walker.walkCompletionTime::0-16383 1704 92.31% 92.31% # Table walker service (enqueue to completion) latency
1345system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 7.04% 99.35% # Table walker service (enqueue to completion) latency
1346system.cpu1.dtb.walker.walkCompletionTime::32768-49151 9 0.49% 99.84% # Table walker service (enqueue to completion) latency
1347system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.89% # Table walker service (enqueue to completion) latency
1348system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.95% # Table walker service (enqueue to completion) latency
1349system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
1350system.cpu1.dtb.walker.walkCompletionTime::total 1846 # Table walker service (enqueue to completion) latency
1351system.cpu1.dtb.walker.walksPending::samples -1572230032 # Table walker pending requests distribution
1352system.cpu1.dtb.walker.walksPending::0 -1572230032 100.00% 100.00% # Table walker pending requests distribution
1353system.cpu1.dtb.walker.walksPending::total -1572230032 # Table walker pending requests distribution
1354system.cpu1.dtb.walker.walkPageSizes::4K 1316 71.29% 71.29% # Table walker page sizes translated
1355system.cpu1.dtb.walker.walkPageSizes::1M 530 28.71% 100.00% # Table walker page sizes translated
1356system.cpu1.dtb.walker.walkPageSizes::total 1846 # Table walker page sizes translated
1357system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22955 # Table walker requests started/completed, data/inst
1358system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1359system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22955 # Table walker requests started/completed, data/inst
1360system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1846 # Table walker requests started/completed, data/inst
1361system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1362system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1846 # Table walker requests started/completed, data/inst
1363system.cpu1.dtb.walker.walkRequestOrigin::total 24801 # Table walker requests started/completed, data/inst
1364system.cpu1.dtb.inst_hits 0 # ITB inst hits
1365system.cpu1.dtb.inst_misses 0 # ITB inst misses
1366system.cpu1.dtb.read_hits 3573471 # DTB read hits
1367system.cpu1.dtb.read_misses 21372 # DTB read misses
1368system.cpu1.dtb.write_hits 2968093 # DTB write hits
1369system.cpu1.dtb.write_misses 1583 # DTB write misses
1370system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1371system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1372system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1373system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1374system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB
1375system.cpu1.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions
1376system.cpu1.dtb.prefetch_faults 261 # Number of TLB faults due to prefetch
1377system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1378system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions
1379system.cpu1.dtb.read_accesses 3594843 # DTB read accesses
1380system.cpu1.dtb.write_accesses 2969676 # DTB write accesses
1381system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1382system.cpu1.dtb.hits 6541564 # DTB hits
1383system.cpu1.dtb.misses 22955 # DTB misses
1384system.cpu1.dtb.accesses 6564519 # DTB accesses
1385system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1386system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1387system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1388system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1389system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1390system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1391system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1392system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1393system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1394system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1395system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1396system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1397system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1398system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1399system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1400system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1401system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1402system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1403system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1404system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1405system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1406system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1407system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1408system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1409system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1410system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1411system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1412system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1413system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1414system.cpu1.itb.walker.walks 2082 # Table walker walks requested
1415system.cpu1.itb.walker.walksShort 2082 # Table walker walks initiated with short descriptors
1416system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate
1417system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1931 # Level at which table walker walks with short descriptors terminate
1418system.cpu1.itb.walker.walkWaitTime::samples 2082 # Table walker wait (enqueue to first request) latency
1419system.cpu1.itb.walker.walkWaitTime::0 2082 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1420system.cpu1.itb.walker.walkWaitTime::total 2082 # Table walker wait (enqueue to first request) latency
1421system.cpu1.itb.walker.walkCompletionTime::samples 843 # Table walker service (enqueue to completion) latency
1422system.cpu1.itb.walker.walkCompletionTime::mean 11844.009490 # Table walker service (enqueue to completion) latency
1423system.cpu1.itb.walker.walkCompletionTime::gmean 11365.721789 # Table walker service (enqueue to completion) latency
1424system.cpu1.itb.walker.walkCompletionTime::stdev 4291.658656 # Table walker service (enqueue to completion) latency
1425system.cpu1.itb.walker.walkCompletionTime::4096-8191 129 15.30% 15.30% # Table walker service (enqueue to completion) latency
1426system.cpu1.itb.walker.walkCompletionTime::8192-12287 559 66.31% 81.61% # Table walker service (enqueue to completion) latency
1427system.cpu1.itb.walker.walkCompletionTime::12288-16383 106 12.57% 94.19% # Table walker service (enqueue to completion) latency
1428system.cpu1.itb.walker.walkCompletionTime::16384-20479 28 3.32% 97.51% # Table walker service (enqueue to completion) latency
1429system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency
1430system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.81% # Table walker service (enqueue to completion) latency
1431system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 98.93% # Table walker service (enqueue to completion) latency
1432system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.24% 99.17% # Table walker service (enqueue to completion) latency
1433system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency
1434system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency
1435system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.12% 100.00% # Table walker service (enqueue to completion) latency
1436system.cpu1.itb.walker.walkCompletionTime::total 843 # Table walker service (enqueue to completion) latency
1437system.cpu1.itb.walker.walksPending::samples -1573105532 # Table walker pending requests distribution
1438system.cpu1.itb.walker.walksPending::0 -1573105532 100.00% 100.00% # Table walker pending requests distribution
1439system.cpu1.itb.walker.walksPending::total -1573105532 # Table walker pending requests distribution
1440system.cpu1.itb.walker.walkPageSizes::4K 703 83.39% 83.39% # Table walker page sizes translated
1441system.cpu1.itb.walker.walkPageSizes::1M 140 16.61% 100.00% # Table walker page sizes translated
1442system.cpu1.itb.walker.walkPageSizes::total 843 # Table walker page sizes translated
1443system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1444system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2082 # Table walker requests started/completed, data/inst
1445system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2082 # Table walker requests started/completed, data/inst
1446system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1447system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 843 # Table walker requests started/completed, data/inst
1448system.cpu1.itb.walker.walkRequestOrigin_Completed::total 843 # Table walker requests started/completed, data/inst
1449system.cpu1.itb.walker.walkRequestOrigin::total 2925 # Table walker requests started/completed, data/inst
1450system.cpu1.itb.inst_hits 6880260 # ITB inst hits
1451system.cpu1.itb.inst_misses 2082 # ITB inst misses
1452system.cpu1.itb.read_hits 0 # DTB read hits
1453system.cpu1.itb.read_misses 0 # DTB read misses
1454system.cpu1.itb.write_hits 0 # DTB write hits
1455system.cpu1.itb.write_misses 0 # DTB write misses
1456system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1457system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1458system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1459system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1460system.cpu1.itb.flush_entries 907 # Number of entries that have been flushed from TLB
1461system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1462system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1463system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1464system.cpu1.itb.perms_faults 1103 # Number of TLB faults due to permissions restrictions
1465system.cpu1.itb.read_accesses 0 # DTB read accesses
1466system.cpu1.itb.write_accesses 0 # DTB write accesses
1467system.cpu1.itb.inst_accesses 6882342 # ITB inst accesses
1468system.cpu1.itb.hits 6880260 # DTB hits
1469system.cpu1.itb.misses 2082 # DTB misses
1470system.cpu1.itb.accesses 6882342 # DTB accesses
1471system.cpu1.numCycles 40344479 # number of cpu cycles simulated
1472system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1473system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1474system.cpu1.committedInsts 14007066 # Number of instructions committed
1475system.cpu1.committedOps 17164558 # Number of ops (including micro ops) committed
1476system.cpu1.discardedOps 1348197 # Number of ops (including micro ops) which were discarded before commit
1477system.cpu1.numFetchSuspends 2750 # Number of times Execute suspended instruction fetching
1478system.cpu1.quiesceCycles 5656772716 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1479system.cpu1.cpi 2.880295 # CPI: cycles per instruction
1480system.cpu1.ipc 0.347187 # IPC: instructions per cycle
1481system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction
1482system.cpu1.op_class_0::IntAlu 10609725 61.81% 61.81% # Class of committed instruction
1483system.cpu1.op_class_0::IntMult 25154 0.15% 61.96% # Class of committed instruction
1484system.cpu1.op_class_0::IntDiv 0 0.00% 61.96% # Class of committed instruction
1485system.cpu1.op_class_0::FloatAdd 0 0.00% 61.96% # Class of committed instruction
1486system.cpu1.op_class_0::FloatCmp 0 0.00% 61.96% # Class of committed instruction
1487system.cpu1.op_class_0::FloatCvt 0 0.00% 61.96% # Class of committed instruction
1488system.cpu1.op_class_0::FloatMult 0 0.00% 61.96% # Class of committed instruction
1489system.cpu1.op_class_0::FloatDiv 0 0.00% 61.96% # Class of committed instruction
1490system.cpu1.op_class_0::FloatSqrt 0 0.00% 61.96% # Class of committed instruction
1491system.cpu1.op_class_0::SimdAdd 0 0.00% 61.96% # Class of committed instruction
1492system.cpu1.op_class_0::SimdAddAcc 0 0.00% 61.96% # Class of committed instruction
1493system.cpu1.op_class_0::SimdAlu 0 0.00% 61.96% # Class of committed instruction
1494system.cpu1.op_class_0::SimdCmp 0 0.00% 61.96% # Class of committed instruction
1495system.cpu1.op_class_0::SimdCvt 0 0.00% 61.96% # Class of committed instruction
1496system.cpu1.op_class_0::SimdMisc 0 0.00% 61.96% # Class of committed instruction
1497system.cpu1.op_class_0::SimdMult 0 0.00% 61.96% # Class of committed instruction
1498system.cpu1.op_class_0::SimdMultAcc 0 0.00% 61.96% # Class of committed instruction
1499system.cpu1.op_class_0::SimdShift 0 0.00% 61.96% # Class of committed instruction
1500system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 61.96% # Class of committed instruction
1501system.cpu1.op_class_0::SimdSqrt 0 0.00% 61.96% # Class of committed instruction
1502system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 61.96% # Class of committed instruction
1503system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 61.96% # Class of committed instruction
1504system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 61.96% # Class of committed instruction
1505system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 61.96% # Class of committed instruction
1506system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 61.96% # Class of committed instruction
1507system.cpu1.op_class_0::SimdFloatMisc 3180 0.02% 61.98% # Class of committed instruction
1508system.cpu1.op_class_0::SimdFloatMult 0 0.00% 61.98% # Class of committed instruction
1509system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 61.98% # Class of committed instruction
1510system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 61.98% # Class of committed instruction
1511system.cpu1.op_class_0::MemRead 3461168 20.16% 82.14% # Class of committed instruction
1512system.cpu1.op_class_0::MemWrite 3065307 17.86% 100.00% # Class of committed instruction
1513system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1514system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1515system.cpu1.op_class_0::total 17164558 # Class of committed instruction
1516system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1517system.cpu1.kern.inst.quiesce 2755 # number of quiesce instructions executed
1518system.cpu1.tickCycles 27219778 # Number of cycles that the object actually ticked
1519system.cpu1.idleCycles 13124701 # Total number of cycles that the object has spent stopped
1520system.cpu1.dcache.tags.replacements 155125 # number of replacements
1521system.cpu1.dcache.tags.tagsinuse 474.675908 # Cycle average of tags in use
1522system.cpu1.dcache.tags.total_refs 6200474 # Total number of references to valid blocks.
1523system.cpu1.dcache.tags.sampled_refs 155475 # Sample count of references to valid blocks.
1524system.cpu1.dcache.tags.avg_refs 39.880843 # Average number of references to valid blocks.
1525system.cpu1.dcache.tags.warmup_cycle 91637729500 # Cycle when the warmup percentage was hit.
1526system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.675908 # Average occupied blocks per requestor
1527system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927101 # Average percentage of cache occupancy
1528system.cpu1.dcache.tags.occ_percent::total 0.927101 # Average percentage of cache occupancy
1529system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
1530system.cpu1.dcache.tags.age_task_id_blocks_1024::2 281 # Occupied blocks per task id
1531system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id
1532system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id
1533system.cpu1.dcache.tags.tag_accesses 13156233 # Number of tag accesses
1534system.cpu1.dcache.tags.data_accesses 13156233 # Number of data accesses
1535system.cpu1.dcache.ReadReq_hits::cpu1.data 3254524 # number of ReadReq hits
1536system.cpu1.dcache.ReadReq_hits::total 3254524 # number of ReadReq hits
1537system.cpu1.dcache.WriteReq_hits::cpu1.data 2729726 # number of WriteReq hits
1538system.cpu1.dcache.WriteReq_hits::total 2729726 # number of WriteReq hits
1539system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42620 # number of SoftPFReq hits
1540system.cpu1.dcache.SoftPFReq_hits::total 42620 # number of SoftPFReq hits
1541system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70434 # number of LoadLockedReq hits
1542system.cpu1.dcache.LoadLockedReq_hits::total 70434 # number of LoadLockedReq hits
1543system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61835 # number of StoreCondReq hits
1544system.cpu1.dcache.StoreCondReq_hits::total 61835 # number of StoreCondReq hits
1545system.cpu1.dcache.demand_hits::cpu1.data 5984250 # number of demand (read+write) hits
1546system.cpu1.dcache.demand_hits::total 5984250 # number of demand (read+write) hits
1547system.cpu1.dcache.overall_hits::cpu1.data 6026870 # number of overall hits
1548system.cpu1.dcache.overall_hits::total 6026870 # number of overall hits
1549system.cpu1.dcache.ReadReq_misses::cpu1.data 133031 # number of ReadReq misses
1550system.cpu1.dcache.ReadReq_misses::total 133031 # number of ReadReq misses
1551system.cpu1.dcache.WriteReq_misses::cpu1.data 121759 # number of WriteReq misses
1552system.cpu1.dcache.WriteReq_misses::total 121759 # number of WriteReq misses
1553system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24466 # number of SoftPFReq misses
1554system.cpu1.dcache.SoftPFReq_misses::total 24466 # number of SoftPFReq misses
1555system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16570 # number of LoadLockedReq misses
1556system.cpu1.dcache.LoadLockedReq_misses::total 16570 # number of LoadLockedReq misses
1557system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23417 # number of StoreCondReq misses
1558system.cpu1.dcache.StoreCondReq_misses::total 23417 # number of StoreCondReq misses
1559system.cpu1.dcache.demand_misses::cpu1.data 254790 # number of demand (read+write) misses
1560system.cpu1.dcache.demand_misses::total 254790 # number of demand (read+write) misses
1561system.cpu1.dcache.overall_misses::cpu1.data 279256 # number of overall misses
1562system.cpu1.dcache.overall_misses::total 279256 # number of overall misses
1563system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2166796500 # number of ReadReq miss cycles
1564system.cpu1.dcache.ReadReq_miss_latency::total 2166796500 # number of ReadReq miss cycles
1565system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4455024500 # number of WriteReq miss cycles
1566system.cpu1.dcache.WriteReq_miss_latency::total 4455024500 # number of WriteReq miss cycles
1567system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320532500 # number of LoadLockedReq miss cycles
1568system.cpu1.dcache.LoadLockedReq_miss_latency::total 320532500 # number of LoadLockedReq miss cycles
1569system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 635944000 # number of StoreCondReq miss cycles
1570system.cpu1.dcache.StoreCondReq_miss_latency::total 635944000 # number of StoreCondReq miss cycles
1571system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1106500 # number of StoreCondFailReq miss cycles
1572system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1106500 # number of StoreCondFailReq miss cycles
1573system.cpu1.dcache.demand_miss_latency::cpu1.data 6621821000 # number of demand (read+write) miss cycles
1574system.cpu1.dcache.demand_miss_latency::total 6621821000 # number of demand (read+write) miss cycles
1575system.cpu1.dcache.overall_miss_latency::cpu1.data 6621821000 # number of overall miss cycles
1576system.cpu1.dcache.overall_miss_latency::total 6621821000 # number of overall miss cycles
1577system.cpu1.dcache.ReadReq_accesses::cpu1.data 3387555 # number of ReadReq accesses(hits+misses)
1578system.cpu1.dcache.ReadReq_accesses::total 3387555 # number of ReadReq accesses(hits+misses)
1579system.cpu1.dcache.WriteReq_accesses::cpu1.data 2851485 # number of WriteReq accesses(hits+misses)
1580system.cpu1.dcache.WriteReq_accesses::total 2851485 # number of WriteReq accesses(hits+misses)
1581system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67086 # number of SoftPFReq accesses(hits+misses)
1582system.cpu1.dcache.SoftPFReq_accesses::total 67086 # number of SoftPFReq accesses(hits+misses)
1583system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87004 # number of LoadLockedReq accesses(hits+misses)
1584system.cpu1.dcache.LoadLockedReq_accesses::total 87004 # number of LoadLockedReq accesses(hits+misses)
1585system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85252 # number of StoreCondReq accesses(hits+misses)
1586system.cpu1.dcache.StoreCondReq_accesses::total 85252 # number of StoreCondReq accesses(hits+misses)
1587system.cpu1.dcache.demand_accesses::cpu1.data 6239040 # number of demand (read+write) accesses
1588system.cpu1.dcache.demand_accesses::total 6239040 # number of demand (read+write) accesses
1589system.cpu1.dcache.overall_accesses::cpu1.data 6306126 # number of overall (read+write) accesses
1590system.cpu1.dcache.overall_accesses::total 6306126 # number of overall (read+write) accesses
1591system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039271 # miss rate for ReadReq accesses
1592system.cpu1.dcache.ReadReq_miss_rate::total 0.039271 # miss rate for ReadReq accesses
1593system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042700 # miss rate for WriteReq accesses
1594system.cpu1.dcache.WriteReq_miss_rate::total 0.042700 # miss rate for WriteReq accesses
1595system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.364696 # miss rate for SoftPFReq accesses
1596system.cpu1.dcache.SoftPFReq_miss_rate::total 0.364696 # miss rate for SoftPFReq accesses
1597system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190451 # miss rate for LoadLockedReq accesses
1598system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190451 # miss rate for LoadLockedReq accesses
1599system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274680 # miss rate for StoreCondReq accesses
1600system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274680 # miss rate for StoreCondReq accesses
1601system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040838 # miss rate for demand accesses
1602system.cpu1.dcache.demand_miss_rate::total 0.040838 # miss rate for demand accesses
1603system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044283 # miss rate for overall accesses
1604system.cpu1.dcache.overall_miss_rate::total 0.044283 # miss rate for overall accesses
1605system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16287.906578 # average ReadReq miss latency
1606system.cpu1.dcache.ReadReq_avg_miss_latency::total 16287.906578 # average ReadReq miss latency
1607system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36588.872280 # average WriteReq miss latency
1608system.cpu1.dcache.WriteReq_avg_miss_latency::total 36588.872280 # average WriteReq miss latency
1609system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19344.146047 # average LoadLockedReq miss latency
1610system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19344.146047 # average LoadLockedReq miss latency
1611system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27157.364308 # average StoreCondReq miss latency
1612system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27157.364308 # average StoreCondReq miss latency
1613system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1614system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1615system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25989.328467 # average overall miss latency
1616system.cpu1.dcache.demand_avg_miss_latency::total 25989.328467 # average overall miss latency
1617system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23712.367863 # average overall miss latency
1618system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863 # average overall miss latency
1619system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1620system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1621system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1622system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1623system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1624system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1216system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter.
1217system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1218system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1219system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter.
1220system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1221system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1222system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution
1223system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution
1224system.cpu0.toL2Bus.trans_dist::WriteReq 28724 # Transaction distribution
1225system.cpu0.toL2Bus.trans_dist::WriteResp 28724 # Transaction distribution
1226system.cpu0.toL2Bus.trans_dist::WritebackDirty 743774 # Transaction distribution
1227system.cpu0.toL2Bus.trans_dist::WritebackClean 2294086 # Transaction distribution
1228system.cpu0.toL2Bus.trans_dist::CleanEvict 245615 # Transaction distribution
1229system.cpu0.toL2Bus.trans_dist::HardPFReq 332229 # Transaction distribution
1230system.cpu0.toL2Bus.trans_dist::UpgradeReq 86791 # Transaction distribution
1231system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42912 # Transaction distribution
1232system.cpu0.toL2Bus.trans_dist::UpgradeResp 113818 # Transaction distribution
1233system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
1234system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
1235system.cpu0.toL2Bus.trans_dist::ReadExReq 300259 # Transaction distribution
1236system.cpu0.toL2Bus.trans_dist::ReadExResp 296935 # Transaction distribution
1237system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2042958 # Transaction distribution
1238system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604813 # Transaction distribution
1239system.cpu0.toL2Bus.trans_dist::InvalidateReq 3110 # Transaction distribution
1240system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6136174 # Packet count per connected master and slave (bytes)
1241system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2759564 # Packet count per connected master and slave (bytes)
1242system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14116 # Packet count per connected master and slave (bytes)
1243system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185351 # Packet count per connected master and slave (bytes)
1244system.cpu0.toL2Bus.pkt_count::total 9095205 # Packet count per connected master and slave (bytes)
1245system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261715136 # Cumulative packet size per connected master and slave (bytes)
1246system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104822354 # Cumulative packet size per connected master and slave (bytes)
1247system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23644 # Cumulative packet size per connected master and slave (bytes)
1248system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 353660 # Cumulative packet size per connected master and slave (bytes)
1249system.cpu0.toL2Bus.pkt_size::total 366914794 # Cumulative packet size per connected master and slave (bytes)
1250system.cpu0.toL2Bus.snoops 1076546 # Total snoops (count)
1251system.cpu0.toL2Bus.snoop_fanout::samples 4066304 # Request fanout histogram
1252system.cpu0.toL2Bus.snoop_fanout::mean 0.104124 # Request fanout histogram
1253system.cpu0.toL2Bus.snoop_fanout::stdev 0.309432 # Request fanout histogram
1254system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1255system.cpu0.toL2Bus.snoop_fanout::0 3647917 89.71% 89.71% # Request fanout histogram
1256system.cpu0.toL2Bus.snoop_fanout::1 413374 10.17% 99.88% # Request fanout histogram
1257system.cpu0.toL2Bus.snoop_fanout::2 5013 0.12% 100.00% # Request fanout histogram
1258system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1259system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1260system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1261system.cpu0.toL2Bus.snoop_fanout::total 4066304 # Request fanout histogram
1262system.cpu0.toL2Bus.reqLayer0.occupancy 5765624998 # Layer occupancy (ticks)
1263system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1264system.cpu0.toL2Bus.snoopLayer0.occupancy 115477021 # Layer occupancy (ticks)
1265system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1266system.cpu0.toL2Bus.respLayer0.occupancy 3070848423 # Layer occupancy (ticks)
1267system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1268system.cpu0.toL2Bus.respLayer1.occupancy 1304480252 # Layer occupancy (ticks)
1269system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1270system.cpu0.toL2Bus.respLayer2.occupancy 8215479 # Layer occupancy (ticks)
1271system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1272system.cpu0.toL2Bus.respLayer3.occupancy 96957457 # Layer occupancy (ticks)
1273system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1274system.cpu1.branchPred.lookups 3600044 # Number of BP lookups
1275system.cpu1.branchPred.condPredicted 2023819 # Number of conditional branches predicted
1276system.cpu1.branchPred.condIncorrect 196135 # Number of conditional branches incorrect
1277system.cpu1.branchPred.BTBLookups 2284720 # Number of BTB lookups
1278system.cpu1.branchPred.BTBHits 1344428 # Number of BTB hits
1279system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1280system.cpu1.branchPred.BTBHitPct 58.844322 # BTB Hit Percentage
1281system.cpu1.branchPred.usedRAS 748131 # Number of times the RAS was used to get a target.
1282system.cpu1.branchPred.RASInCorrect 53981 # Number of incorrect RAS predictions.
1283system.cpu1.branchPred.indirectLookups 144785 # Number of indirect predictor lookups.
1284system.cpu1.branchPred.indirectHits 107908 # Number of indirect target hits.
1285system.cpu1.branchPred.indirectMisses 36877 # Number of indirect misses.
1286system.cpu1.branchPredindirectMispredicted 17103 # Number of mispredicted indirect branches.
1287system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1288system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1289system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1290system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1291system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1292system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1293system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1294system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1295system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1296system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1297system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1298system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1299system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1300system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1301system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1302system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1303system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1304system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1305system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1306system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1307system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1308system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1309system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1310system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1311system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1312system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1313system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1314system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1315system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1316system.cpu1.dtb.walker.walks 22955 # Table walker walks requested
1317system.cpu1.dtb.walker.walksShort 22955 # Table walker walks initiated with short descriptors
1318system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18858 # Level at which table walker walks with short descriptors terminate
1319system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4097 # Level at which table walker walks with short descriptors terminate
1320system.cpu1.dtb.walker.walkWaitTime::samples 22955 # Table walker wait (enqueue to first request) latency
1321system.cpu1.dtb.walker.walkWaitTime::0 22955 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1322system.cpu1.dtb.walker.walkWaitTime::total 22955 # Table walker wait (enqueue to first request) latency
1323system.cpu1.dtb.walker.walkCompletionTime::samples 1846 # Table walker service (enqueue to completion) latency
1324system.cpu1.dtb.walker.walkCompletionTime::mean 11730.498375 # Table walker service (enqueue to completion) latency
1325system.cpu1.dtb.walker.walkCompletionTime::gmean 11025.049339 # Table walker service (enqueue to completion) latency
1326system.cpu1.dtb.walker.walkCompletionTime::stdev 6418.983235 # Table walker service (enqueue to completion) latency
1327system.cpu1.dtb.walker.walkCompletionTime::0-16383 1704 92.31% 92.31% # Table walker service (enqueue to completion) latency
1328system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 7.04% 99.35% # Table walker service (enqueue to completion) latency
1329system.cpu1.dtb.walker.walkCompletionTime::32768-49151 9 0.49% 99.84% # Table walker service (enqueue to completion) latency
1330system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.89% # Table walker service (enqueue to completion) latency
1331system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.95% # Table walker service (enqueue to completion) latency
1332system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
1333system.cpu1.dtb.walker.walkCompletionTime::total 1846 # Table walker service (enqueue to completion) latency
1334system.cpu1.dtb.walker.walksPending::samples -1572230032 # Table walker pending requests distribution
1335system.cpu1.dtb.walker.walksPending::0 -1572230032 100.00% 100.00% # Table walker pending requests distribution
1336system.cpu1.dtb.walker.walksPending::total -1572230032 # Table walker pending requests distribution
1337system.cpu1.dtb.walker.walkPageSizes::4K 1316 71.29% 71.29% # Table walker page sizes translated
1338system.cpu1.dtb.walker.walkPageSizes::1M 530 28.71% 100.00% # Table walker page sizes translated
1339system.cpu1.dtb.walker.walkPageSizes::total 1846 # Table walker page sizes translated
1340system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22955 # Table walker requests started/completed, data/inst
1341system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1342system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22955 # Table walker requests started/completed, data/inst
1343system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1846 # Table walker requests started/completed, data/inst
1344system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1345system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1846 # Table walker requests started/completed, data/inst
1346system.cpu1.dtb.walker.walkRequestOrigin::total 24801 # Table walker requests started/completed, data/inst
1347system.cpu1.dtb.inst_hits 0 # ITB inst hits
1348system.cpu1.dtb.inst_misses 0 # ITB inst misses
1349system.cpu1.dtb.read_hits 3573471 # DTB read hits
1350system.cpu1.dtb.read_misses 21372 # DTB read misses
1351system.cpu1.dtb.write_hits 2968093 # DTB write hits
1352system.cpu1.dtb.write_misses 1583 # DTB write misses
1353system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1354system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1355system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1356system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1357system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB
1358system.cpu1.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions
1359system.cpu1.dtb.prefetch_faults 261 # Number of TLB faults due to prefetch
1360system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1361system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions
1362system.cpu1.dtb.read_accesses 3594843 # DTB read accesses
1363system.cpu1.dtb.write_accesses 2969676 # DTB write accesses
1364system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1365system.cpu1.dtb.hits 6541564 # DTB hits
1366system.cpu1.dtb.misses 22955 # DTB misses
1367system.cpu1.dtb.accesses 6564519 # DTB accesses
1368system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1369system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1370system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1371system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1372system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1373system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1374system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1375system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1376system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1377system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1378system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1379system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1380system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1381system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1382system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1383system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1384system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1385system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1386system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1387system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1388system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1389system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1390system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1391system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1392system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1393system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1394system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1395system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1396system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1397system.cpu1.itb.walker.walks 2082 # Table walker walks requested
1398system.cpu1.itb.walker.walksShort 2082 # Table walker walks initiated with short descriptors
1399system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate
1400system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1931 # Level at which table walker walks with short descriptors terminate
1401system.cpu1.itb.walker.walkWaitTime::samples 2082 # Table walker wait (enqueue to first request) latency
1402system.cpu1.itb.walker.walkWaitTime::0 2082 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1403system.cpu1.itb.walker.walkWaitTime::total 2082 # Table walker wait (enqueue to first request) latency
1404system.cpu1.itb.walker.walkCompletionTime::samples 843 # Table walker service (enqueue to completion) latency
1405system.cpu1.itb.walker.walkCompletionTime::mean 11844.009490 # Table walker service (enqueue to completion) latency
1406system.cpu1.itb.walker.walkCompletionTime::gmean 11365.721789 # Table walker service (enqueue to completion) latency
1407system.cpu1.itb.walker.walkCompletionTime::stdev 4291.658656 # Table walker service (enqueue to completion) latency
1408system.cpu1.itb.walker.walkCompletionTime::4096-8191 129 15.30% 15.30% # Table walker service (enqueue to completion) latency
1409system.cpu1.itb.walker.walkCompletionTime::8192-12287 559 66.31% 81.61% # Table walker service (enqueue to completion) latency
1410system.cpu1.itb.walker.walkCompletionTime::12288-16383 106 12.57% 94.19% # Table walker service (enqueue to completion) latency
1411system.cpu1.itb.walker.walkCompletionTime::16384-20479 28 3.32% 97.51% # Table walker service (enqueue to completion) latency
1412system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency
1413system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.81% # Table walker service (enqueue to completion) latency
1414system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 98.93% # Table walker service (enqueue to completion) latency
1415system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.24% 99.17% # Table walker service (enqueue to completion) latency
1416system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency
1417system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency
1418system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.12% 100.00% # Table walker service (enqueue to completion) latency
1419system.cpu1.itb.walker.walkCompletionTime::total 843 # Table walker service (enqueue to completion) latency
1420system.cpu1.itb.walker.walksPending::samples -1573105532 # Table walker pending requests distribution
1421system.cpu1.itb.walker.walksPending::0 -1573105532 100.00% 100.00% # Table walker pending requests distribution
1422system.cpu1.itb.walker.walksPending::total -1573105532 # Table walker pending requests distribution
1423system.cpu1.itb.walker.walkPageSizes::4K 703 83.39% 83.39% # Table walker page sizes translated
1424system.cpu1.itb.walker.walkPageSizes::1M 140 16.61% 100.00% # Table walker page sizes translated
1425system.cpu1.itb.walker.walkPageSizes::total 843 # Table walker page sizes translated
1426system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1427system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2082 # Table walker requests started/completed, data/inst
1428system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2082 # Table walker requests started/completed, data/inst
1429system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1430system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 843 # Table walker requests started/completed, data/inst
1431system.cpu1.itb.walker.walkRequestOrigin_Completed::total 843 # Table walker requests started/completed, data/inst
1432system.cpu1.itb.walker.walkRequestOrigin::total 2925 # Table walker requests started/completed, data/inst
1433system.cpu1.itb.inst_hits 6880260 # ITB inst hits
1434system.cpu1.itb.inst_misses 2082 # ITB inst misses
1435system.cpu1.itb.read_hits 0 # DTB read hits
1436system.cpu1.itb.read_misses 0 # DTB read misses
1437system.cpu1.itb.write_hits 0 # DTB write hits
1438system.cpu1.itb.write_misses 0 # DTB write misses
1439system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1440system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1441system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1442system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1443system.cpu1.itb.flush_entries 907 # Number of entries that have been flushed from TLB
1444system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1445system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1446system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1447system.cpu1.itb.perms_faults 1103 # Number of TLB faults due to permissions restrictions
1448system.cpu1.itb.read_accesses 0 # DTB read accesses
1449system.cpu1.itb.write_accesses 0 # DTB write accesses
1450system.cpu1.itb.inst_accesses 6882342 # ITB inst accesses
1451system.cpu1.itb.hits 6880260 # DTB hits
1452system.cpu1.itb.misses 2082 # DTB misses
1453system.cpu1.itb.accesses 6882342 # DTB accesses
1454system.cpu1.numCycles 40344479 # number of cpu cycles simulated
1455system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1456system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1457system.cpu1.committedInsts 14007066 # Number of instructions committed
1458system.cpu1.committedOps 17164558 # Number of ops (including micro ops) committed
1459system.cpu1.discardedOps 1348197 # Number of ops (including micro ops) which were discarded before commit
1460system.cpu1.numFetchSuspends 2750 # Number of times Execute suspended instruction fetching
1461system.cpu1.quiesceCycles 5656772716 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1462system.cpu1.cpi 2.880295 # CPI: cycles per instruction
1463system.cpu1.ipc 0.347187 # IPC: instructions per cycle
1464system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction
1465system.cpu1.op_class_0::IntAlu 10609725 61.81% 61.81% # Class of committed instruction
1466system.cpu1.op_class_0::IntMult 25154 0.15% 61.96% # Class of committed instruction
1467system.cpu1.op_class_0::IntDiv 0 0.00% 61.96% # Class of committed instruction
1468system.cpu1.op_class_0::FloatAdd 0 0.00% 61.96% # Class of committed instruction
1469system.cpu1.op_class_0::FloatCmp 0 0.00% 61.96% # Class of committed instruction
1470system.cpu1.op_class_0::FloatCvt 0 0.00% 61.96% # Class of committed instruction
1471system.cpu1.op_class_0::FloatMult 0 0.00% 61.96% # Class of committed instruction
1472system.cpu1.op_class_0::FloatDiv 0 0.00% 61.96% # Class of committed instruction
1473system.cpu1.op_class_0::FloatSqrt 0 0.00% 61.96% # Class of committed instruction
1474system.cpu1.op_class_0::SimdAdd 0 0.00% 61.96% # Class of committed instruction
1475system.cpu1.op_class_0::SimdAddAcc 0 0.00% 61.96% # Class of committed instruction
1476system.cpu1.op_class_0::SimdAlu 0 0.00% 61.96% # Class of committed instruction
1477system.cpu1.op_class_0::SimdCmp 0 0.00% 61.96% # Class of committed instruction
1478system.cpu1.op_class_0::SimdCvt 0 0.00% 61.96% # Class of committed instruction
1479system.cpu1.op_class_0::SimdMisc 0 0.00% 61.96% # Class of committed instruction
1480system.cpu1.op_class_0::SimdMult 0 0.00% 61.96% # Class of committed instruction
1481system.cpu1.op_class_0::SimdMultAcc 0 0.00% 61.96% # Class of committed instruction
1482system.cpu1.op_class_0::SimdShift 0 0.00% 61.96% # Class of committed instruction
1483system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 61.96% # Class of committed instruction
1484system.cpu1.op_class_0::SimdSqrt 0 0.00% 61.96% # Class of committed instruction
1485system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 61.96% # Class of committed instruction
1486system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 61.96% # Class of committed instruction
1487system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 61.96% # Class of committed instruction
1488system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 61.96% # Class of committed instruction
1489system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 61.96% # Class of committed instruction
1490system.cpu1.op_class_0::SimdFloatMisc 3180 0.02% 61.98% # Class of committed instruction
1491system.cpu1.op_class_0::SimdFloatMult 0 0.00% 61.98% # Class of committed instruction
1492system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 61.98% # Class of committed instruction
1493system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 61.98% # Class of committed instruction
1494system.cpu1.op_class_0::MemRead 3461168 20.16% 82.14% # Class of committed instruction
1495system.cpu1.op_class_0::MemWrite 3065307 17.86% 100.00% # Class of committed instruction
1496system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1497system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1498system.cpu1.op_class_0::total 17164558 # Class of committed instruction
1499system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1500system.cpu1.kern.inst.quiesce 2755 # number of quiesce instructions executed
1501system.cpu1.tickCycles 27219778 # Number of cycles that the object actually ticked
1502system.cpu1.idleCycles 13124701 # Total number of cycles that the object has spent stopped
1503system.cpu1.dcache.tags.replacements 155125 # number of replacements
1504system.cpu1.dcache.tags.tagsinuse 474.675908 # Cycle average of tags in use
1505system.cpu1.dcache.tags.total_refs 6200474 # Total number of references to valid blocks.
1506system.cpu1.dcache.tags.sampled_refs 155475 # Sample count of references to valid blocks.
1507system.cpu1.dcache.tags.avg_refs 39.880843 # Average number of references to valid blocks.
1508system.cpu1.dcache.tags.warmup_cycle 91637729500 # Cycle when the warmup percentage was hit.
1509system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.675908 # Average occupied blocks per requestor
1510system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927101 # Average percentage of cache occupancy
1511system.cpu1.dcache.tags.occ_percent::total 0.927101 # Average percentage of cache occupancy
1512system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
1513system.cpu1.dcache.tags.age_task_id_blocks_1024::2 281 # Occupied blocks per task id
1514system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id
1515system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id
1516system.cpu1.dcache.tags.tag_accesses 13156233 # Number of tag accesses
1517system.cpu1.dcache.tags.data_accesses 13156233 # Number of data accesses
1518system.cpu1.dcache.ReadReq_hits::cpu1.data 3254524 # number of ReadReq hits
1519system.cpu1.dcache.ReadReq_hits::total 3254524 # number of ReadReq hits
1520system.cpu1.dcache.WriteReq_hits::cpu1.data 2729726 # number of WriteReq hits
1521system.cpu1.dcache.WriteReq_hits::total 2729726 # number of WriteReq hits
1522system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42620 # number of SoftPFReq hits
1523system.cpu1.dcache.SoftPFReq_hits::total 42620 # number of SoftPFReq hits
1524system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70434 # number of LoadLockedReq hits
1525system.cpu1.dcache.LoadLockedReq_hits::total 70434 # number of LoadLockedReq hits
1526system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61835 # number of StoreCondReq hits
1527system.cpu1.dcache.StoreCondReq_hits::total 61835 # number of StoreCondReq hits
1528system.cpu1.dcache.demand_hits::cpu1.data 5984250 # number of demand (read+write) hits
1529system.cpu1.dcache.demand_hits::total 5984250 # number of demand (read+write) hits
1530system.cpu1.dcache.overall_hits::cpu1.data 6026870 # number of overall hits
1531system.cpu1.dcache.overall_hits::total 6026870 # number of overall hits
1532system.cpu1.dcache.ReadReq_misses::cpu1.data 133031 # number of ReadReq misses
1533system.cpu1.dcache.ReadReq_misses::total 133031 # number of ReadReq misses
1534system.cpu1.dcache.WriteReq_misses::cpu1.data 121759 # number of WriteReq misses
1535system.cpu1.dcache.WriteReq_misses::total 121759 # number of WriteReq misses
1536system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24466 # number of SoftPFReq misses
1537system.cpu1.dcache.SoftPFReq_misses::total 24466 # number of SoftPFReq misses
1538system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16570 # number of LoadLockedReq misses
1539system.cpu1.dcache.LoadLockedReq_misses::total 16570 # number of LoadLockedReq misses
1540system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23417 # number of StoreCondReq misses
1541system.cpu1.dcache.StoreCondReq_misses::total 23417 # number of StoreCondReq misses
1542system.cpu1.dcache.demand_misses::cpu1.data 254790 # number of demand (read+write) misses
1543system.cpu1.dcache.demand_misses::total 254790 # number of demand (read+write) misses
1544system.cpu1.dcache.overall_misses::cpu1.data 279256 # number of overall misses
1545system.cpu1.dcache.overall_misses::total 279256 # number of overall misses
1546system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2166796500 # number of ReadReq miss cycles
1547system.cpu1.dcache.ReadReq_miss_latency::total 2166796500 # number of ReadReq miss cycles
1548system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4455024500 # number of WriteReq miss cycles
1549system.cpu1.dcache.WriteReq_miss_latency::total 4455024500 # number of WriteReq miss cycles
1550system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320532500 # number of LoadLockedReq miss cycles
1551system.cpu1.dcache.LoadLockedReq_miss_latency::total 320532500 # number of LoadLockedReq miss cycles
1552system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 635944000 # number of StoreCondReq miss cycles
1553system.cpu1.dcache.StoreCondReq_miss_latency::total 635944000 # number of StoreCondReq miss cycles
1554system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1106500 # number of StoreCondFailReq miss cycles
1555system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1106500 # number of StoreCondFailReq miss cycles
1556system.cpu1.dcache.demand_miss_latency::cpu1.data 6621821000 # number of demand (read+write) miss cycles
1557system.cpu1.dcache.demand_miss_latency::total 6621821000 # number of demand (read+write) miss cycles
1558system.cpu1.dcache.overall_miss_latency::cpu1.data 6621821000 # number of overall miss cycles
1559system.cpu1.dcache.overall_miss_latency::total 6621821000 # number of overall miss cycles
1560system.cpu1.dcache.ReadReq_accesses::cpu1.data 3387555 # number of ReadReq accesses(hits+misses)
1561system.cpu1.dcache.ReadReq_accesses::total 3387555 # number of ReadReq accesses(hits+misses)
1562system.cpu1.dcache.WriteReq_accesses::cpu1.data 2851485 # number of WriteReq accesses(hits+misses)
1563system.cpu1.dcache.WriteReq_accesses::total 2851485 # number of WriteReq accesses(hits+misses)
1564system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67086 # number of SoftPFReq accesses(hits+misses)
1565system.cpu1.dcache.SoftPFReq_accesses::total 67086 # number of SoftPFReq accesses(hits+misses)
1566system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87004 # number of LoadLockedReq accesses(hits+misses)
1567system.cpu1.dcache.LoadLockedReq_accesses::total 87004 # number of LoadLockedReq accesses(hits+misses)
1568system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85252 # number of StoreCondReq accesses(hits+misses)
1569system.cpu1.dcache.StoreCondReq_accesses::total 85252 # number of StoreCondReq accesses(hits+misses)
1570system.cpu1.dcache.demand_accesses::cpu1.data 6239040 # number of demand (read+write) accesses
1571system.cpu1.dcache.demand_accesses::total 6239040 # number of demand (read+write) accesses
1572system.cpu1.dcache.overall_accesses::cpu1.data 6306126 # number of overall (read+write) accesses
1573system.cpu1.dcache.overall_accesses::total 6306126 # number of overall (read+write) accesses
1574system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039271 # miss rate for ReadReq accesses
1575system.cpu1.dcache.ReadReq_miss_rate::total 0.039271 # miss rate for ReadReq accesses
1576system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042700 # miss rate for WriteReq accesses
1577system.cpu1.dcache.WriteReq_miss_rate::total 0.042700 # miss rate for WriteReq accesses
1578system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.364696 # miss rate for SoftPFReq accesses
1579system.cpu1.dcache.SoftPFReq_miss_rate::total 0.364696 # miss rate for SoftPFReq accesses
1580system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190451 # miss rate for LoadLockedReq accesses
1581system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190451 # miss rate for LoadLockedReq accesses
1582system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274680 # miss rate for StoreCondReq accesses
1583system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274680 # miss rate for StoreCondReq accesses
1584system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040838 # miss rate for demand accesses
1585system.cpu1.dcache.demand_miss_rate::total 0.040838 # miss rate for demand accesses
1586system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044283 # miss rate for overall accesses
1587system.cpu1.dcache.overall_miss_rate::total 0.044283 # miss rate for overall accesses
1588system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16287.906578 # average ReadReq miss latency
1589system.cpu1.dcache.ReadReq_avg_miss_latency::total 16287.906578 # average ReadReq miss latency
1590system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36588.872280 # average WriteReq miss latency
1591system.cpu1.dcache.WriteReq_avg_miss_latency::total 36588.872280 # average WriteReq miss latency
1592system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19344.146047 # average LoadLockedReq miss latency
1593system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19344.146047 # average LoadLockedReq miss latency
1594system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27157.364308 # average StoreCondReq miss latency
1595system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27157.364308 # average StoreCondReq miss latency
1596system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1597system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1598system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25989.328467 # average overall miss latency
1599system.cpu1.dcache.demand_avg_miss_latency::total 25989.328467 # average overall miss latency
1600system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23712.367863 # average overall miss latency
1601system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863 # average overall miss latency
1602system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1603system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1604system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1605system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1606system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1607system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1625system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1626system.cpu1.dcache.cache_copies 0 # number of cache copies performed

1627system.cpu1.dcache.writebacks::writebacks 155125 # number of writebacks
1628system.cpu1.dcache.writebacks::total 155125 # number of writebacks
1629system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12753 # number of ReadReq MSHR hits
1630system.cpu1.dcache.ReadReq_mshr_hits::total 12753 # number of ReadReq MSHR hits
1631system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42136 # number of WriteReq MSHR hits
1632system.cpu1.dcache.WriteReq_mshr_hits::total 42136 # number of WriteReq MSHR hits
1633system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11686 # number of LoadLockedReq MSHR hits
1634system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11686 # number of LoadLockedReq MSHR hits
1635system.cpu1.dcache.demand_mshr_hits::cpu1.data 54889 # number of demand (read+write) MSHR hits
1636system.cpu1.dcache.demand_mshr_hits::total 54889 # number of demand (read+write) MSHR hits
1637system.cpu1.dcache.overall_mshr_hits::cpu1.data 54889 # number of overall MSHR hits
1638system.cpu1.dcache.overall_mshr_hits::total 54889 # number of overall MSHR hits
1639system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 120278 # number of ReadReq MSHR misses
1640system.cpu1.dcache.ReadReq_mshr_misses::total 120278 # number of ReadReq MSHR misses
1641system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79623 # number of WriteReq MSHR misses
1642system.cpu1.dcache.WriteReq_mshr_misses::total 79623 # number of WriteReq MSHR misses
1643system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23936 # number of SoftPFReq MSHR misses
1644system.cpu1.dcache.SoftPFReq_mshr_misses::total 23936 # number of SoftPFReq MSHR misses
1645system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses
1646system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses
1647system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23417 # number of StoreCondReq MSHR misses
1648system.cpu1.dcache.StoreCondReq_mshr_misses::total 23417 # number of StoreCondReq MSHR misses
1649system.cpu1.dcache.demand_mshr_misses::cpu1.data 199901 # number of demand (read+write) MSHR misses
1650system.cpu1.dcache.demand_mshr_misses::total 199901 # number of demand (read+write) MSHR misses
1651system.cpu1.dcache.overall_mshr_misses::cpu1.data 223837 # number of overall MSHR misses
1652system.cpu1.dcache.overall_mshr_misses::total 223837 # number of overall MSHR misses
1653system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable
1654system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2973 # number of ReadReq MSHR uncacheable
1655system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable
1656system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable
1657system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5284 # number of overall MSHR uncacheable misses
1658system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5284 # number of overall MSHR uncacheable misses
1659system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1843019500 # number of ReadReq MSHR miss cycles
1660system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1843019500 # number of ReadReq MSHR miss cycles
1661system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2713747500 # number of WriteReq MSHR miss cycles
1662system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2713747500 # number of WriteReq MSHR miss cycles
1663system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 448609500 # number of SoftPFReq MSHR miss cycles
1664system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 448609500 # number of SoftPFReq MSHR miss cycles
1665system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89247000 # number of LoadLockedReq MSHR miss cycles
1666system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89247000 # number of LoadLockedReq MSHR miss cycles
1667system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 612539000 # number of StoreCondReq MSHR miss cycles
1668system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 612539000 # number of StoreCondReq MSHR miss cycles
1669system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1094500 # number of StoreCondFailReq MSHR miss cycles
1670system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1094500 # number of StoreCondFailReq MSHR miss cycles
1671system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4556767000 # number of demand (read+write) MSHR miss cycles
1672system.cpu1.dcache.demand_mshr_miss_latency::total 4556767000 # number of demand (read+write) MSHR miss cycles
1673system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500 # number of overall MSHR miss cycles
1674system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles
1675system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles
1676system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles

1608system.cpu1.dcache.writebacks::writebacks 155125 # number of writebacks
1609system.cpu1.dcache.writebacks::total 155125 # number of writebacks
1610system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12753 # number of ReadReq MSHR hits
1611system.cpu1.dcache.ReadReq_mshr_hits::total 12753 # number of ReadReq MSHR hits
1612system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42136 # number of WriteReq MSHR hits
1613system.cpu1.dcache.WriteReq_mshr_hits::total 42136 # number of WriteReq MSHR hits
1614system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11686 # number of LoadLockedReq MSHR hits
1615system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11686 # number of LoadLockedReq MSHR hits
1616system.cpu1.dcache.demand_mshr_hits::cpu1.data 54889 # number of demand (read+write) MSHR hits
1617system.cpu1.dcache.demand_mshr_hits::total 54889 # number of demand (read+write) MSHR hits
1618system.cpu1.dcache.overall_mshr_hits::cpu1.data 54889 # number of overall MSHR hits
1619system.cpu1.dcache.overall_mshr_hits::total 54889 # number of overall MSHR hits
1620system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 120278 # number of ReadReq MSHR misses
1621system.cpu1.dcache.ReadReq_mshr_misses::total 120278 # number of ReadReq MSHR misses
1622system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79623 # number of WriteReq MSHR misses
1623system.cpu1.dcache.WriteReq_mshr_misses::total 79623 # number of WriteReq MSHR misses
1624system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23936 # number of SoftPFReq MSHR misses
1625system.cpu1.dcache.SoftPFReq_mshr_misses::total 23936 # number of SoftPFReq MSHR misses
1626system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses
1627system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses
1628system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23417 # number of StoreCondReq MSHR misses
1629system.cpu1.dcache.StoreCondReq_mshr_misses::total 23417 # number of StoreCondReq MSHR misses
1630system.cpu1.dcache.demand_mshr_misses::cpu1.data 199901 # number of demand (read+write) MSHR misses
1631system.cpu1.dcache.demand_mshr_misses::total 199901 # number of demand (read+write) MSHR misses
1632system.cpu1.dcache.overall_mshr_misses::cpu1.data 223837 # number of overall MSHR misses
1633system.cpu1.dcache.overall_mshr_misses::total 223837 # number of overall MSHR misses
1634system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable
1635system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2973 # number of ReadReq MSHR uncacheable
1636system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable
1637system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable
1638system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5284 # number of overall MSHR uncacheable misses
1639system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5284 # number of overall MSHR uncacheable misses
1640system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1843019500 # number of ReadReq MSHR miss cycles
1641system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1843019500 # number of ReadReq MSHR miss cycles
1642system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2713747500 # number of WriteReq MSHR miss cycles
1643system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2713747500 # number of WriteReq MSHR miss cycles
1644system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 448609500 # number of SoftPFReq MSHR miss cycles
1645system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 448609500 # number of SoftPFReq MSHR miss cycles
1646system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89247000 # number of LoadLockedReq MSHR miss cycles
1647system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89247000 # number of LoadLockedReq MSHR miss cycles
1648system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 612539000 # number of StoreCondReq MSHR miss cycles
1649system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 612539000 # number of StoreCondReq MSHR miss cycles
1650system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1094500 # number of StoreCondFailReq MSHR miss cycles
1651system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1094500 # number of StoreCondFailReq MSHR miss cycles
1652system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4556767000 # number of demand (read+write) MSHR miss cycles
1653system.cpu1.dcache.demand_mshr_miss_latency::total 4556767000 # number of demand (read+write) MSHR miss cycles
1654system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500 # number of overall MSHR miss cycles
1655system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles
1656system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles
1657system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles

1677system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251809500 # number of WriteReq MSHR uncacheable cycles
1678system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251809500 # number of WriteReq MSHR uncacheable cycles
1679system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641276500 # number of overall MSHR uncacheable cycles
1680system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641276500 # number of overall MSHR uncacheable cycles

1658system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 389467000 # number of overall MSHR uncacheable cycles
1659system.cpu1.dcache.overall_mshr_uncacheable_latency::total 389467000 # number of overall MSHR uncacheable cycles

1681system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses
1682system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses
1683system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses
1684system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses
1685system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses
1686system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses
1687system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses
1688system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses
1689system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274680 # mshr miss rate for StoreCondReq accesses
1690system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274680 # mshr miss rate for StoreCondReq accesses
1691system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032040 # mshr miss rate for demand accesses
1692system.cpu1.dcache.demand_mshr_miss_rate::total 0.032040 # mshr miss rate for demand accesses
1693system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035495 # mshr miss rate for overall accesses
1694system.cpu1.dcache.overall_mshr_miss_rate::total 0.035495 # mshr miss rate for overall accesses
1695system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15322.997556 # average ReadReq mshr miss latency
1696system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15322.997556 # average ReadReq mshr miss latency
1697system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34082.457330 # average WriteReq mshr miss latency
1698system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34082.457330 # average WriteReq mshr miss latency
1699system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18742.041277 # average SoftPFReq mshr miss latency
1700system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18742.041277 # average SoftPFReq mshr miss latency
1701system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18273.341523 # average LoadLockedReq mshr miss latency
1702system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18273.341523 # average LoadLockedReq mshr miss latency
1703system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26157.876756 # average StoreCondReq mshr miss latency
1704system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26157.876756 # average StoreCondReq mshr miss latency
1705system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1706system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1707system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency
1708system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency
1709system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency
1710system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency
1711system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency
1712system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency

1660system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses
1661system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses
1662system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses
1663system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses
1664system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses
1665system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses
1666system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses
1667system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses
1668system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274680 # mshr miss rate for StoreCondReq accesses
1669system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274680 # mshr miss rate for StoreCondReq accesses
1670system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032040 # mshr miss rate for demand accesses
1671system.cpu1.dcache.demand_mshr_miss_rate::total 0.032040 # mshr miss rate for demand accesses
1672system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035495 # mshr miss rate for overall accesses
1673system.cpu1.dcache.overall_mshr_miss_rate::total 0.035495 # mshr miss rate for overall accesses
1674system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15322.997556 # average ReadReq mshr miss latency
1675system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15322.997556 # average ReadReq mshr miss latency
1676system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34082.457330 # average WriteReq mshr miss latency
1677system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34082.457330 # average WriteReq mshr miss latency
1678system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18742.041277 # average SoftPFReq mshr miss latency
1679system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18742.041277 # average SoftPFReq mshr miss latency
1680system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18273.341523 # average LoadLockedReq mshr miss latency
1681system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18273.341523 # average LoadLockedReq mshr miss latency
1682system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26157.876756 # average StoreCondReq mshr miss latency
1683system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26157.876756 # average StoreCondReq mshr miss latency
1684system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1685system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1686system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency
1687system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency
1688system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency
1689system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency
1690system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency
1691system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency

1713system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177 # average WriteReq mshr uncacheable latency
1714system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177 # average WriteReq mshr uncacheable latency
1715system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711 # average overall mshr uncacheable latency
1716system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711 # average overall mshr uncacheable latency
1717system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

1692system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 73706.850871 # average overall mshr uncacheable latency
1693system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 73706.850871 # average overall mshr uncacheable latency

1718system.cpu1.icache.tags.replacements 856657 # number of replacements
1719system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use
1720system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks.
1721system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks.
1722system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks.
1723system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit.
1724system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor
1725system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy
1726system.cpu1.icache.tags.occ_percent::total 0.974875 # Average percentage of cache occupancy
1727system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1728system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id
1729system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
1730system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
1731system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1732system.cpu1.icache.tags.tag_accesses 14615371 # Number of tag accesses
1733system.cpu1.icache.tags.data_accesses 14615371 # Number of data accesses
1734system.cpu1.icache.ReadReq_hits::cpu1.inst 6021932 # number of ReadReq hits
1735system.cpu1.icache.ReadReq_hits::total 6021932 # number of ReadReq hits
1736system.cpu1.icache.demand_hits::cpu1.inst 6021932 # number of demand (read+write) hits
1737system.cpu1.icache.demand_hits::total 6021932 # number of demand (read+write) hits
1738system.cpu1.icache.overall_hits::cpu1.inst 6021932 # number of overall hits
1739system.cpu1.icache.overall_hits::total 6021932 # number of overall hits
1740system.cpu1.icache.ReadReq_misses::cpu1.inst 857169 # number of ReadReq misses
1741system.cpu1.icache.ReadReq_misses::total 857169 # number of ReadReq misses
1742system.cpu1.icache.demand_misses::cpu1.inst 857169 # number of demand (read+write) misses
1743system.cpu1.icache.demand_misses::total 857169 # number of demand (read+write) misses
1744system.cpu1.icache.overall_misses::cpu1.inst 857169 # number of overall misses
1745system.cpu1.icache.overall_misses::total 857169 # number of overall misses
1746system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7590039500 # number of ReadReq miss cycles
1747system.cpu1.icache.ReadReq_miss_latency::total 7590039500 # number of ReadReq miss cycles
1748system.cpu1.icache.demand_miss_latency::cpu1.inst 7590039500 # number of demand (read+write) miss cycles
1749system.cpu1.icache.demand_miss_latency::total 7590039500 # number of demand (read+write) miss cycles
1750system.cpu1.icache.overall_miss_latency::cpu1.inst 7590039500 # number of overall miss cycles
1751system.cpu1.icache.overall_miss_latency::total 7590039500 # number of overall miss cycles
1752system.cpu1.icache.ReadReq_accesses::cpu1.inst 6879101 # number of ReadReq accesses(hits+misses)
1753system.cpu1.icache.ReadReq_accesses::total 6879101 # number of ReadReq accesses(hits+misses)
1754system.cpu1.icache.demand_accesses::cpu1.inst 6879101 # number of demand (read+write) accesses
1755system.cpu1.icache.demand_accesses::total 6879101 # number of demand (read+write) accesses
1756system.cpu1.icache.overall_accesses::cpu1.inst 6879101 # number of overall (read+write) accesses
1757system.cpu1.icache.overall_accesses::total 6879101 # number of overall (read+write) accesses
1758system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124605 # miss rate for ReadReq accesses
1759system.cpu1.icache.ReadReq_miss_rate::total 0.124605 # miss rate for ReadReq accesses
1760system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124605 # miss rate for demand accesses
1761system.cpu1.icache.demand_miss_rate::total 0.124605 # miss rate for demand accesses
1762system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124605 # miss rate for overall accesses
1763system.cpu1.icache.overall_miss_rate::total 0.124605 # miss rate for overall accesses
1764system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8854.776013 # average ReadReq miss latency
1765system.cpu1.icache.ReadReq_avg_miss_latency::total 8854.776013 # average ReadReq miss latency
1766system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency
1767system.cpu1.icache.demand_avg_miss_latency::total 8854.776013 # average overall miss latency
1768system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency
1769system.cpu1.icache.overall_avg_miss_latency::total 8854.776013 # average overall miss latency
1770system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1771system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1772system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1773system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1774system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1775system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1694system.cpu1.icache.tags.replacements 856657 # number of replacements
1695system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use
1696system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks.
1697system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks.
1698system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks.
1699system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit.
1700system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor
1701system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy
1702system.cpu1.icache.tags.occ_percent::total 0.974875 # Average percentage of cache occupancy
1703system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1704system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id
1705system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
1706system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
1707system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1708system.cpu1.icache.tags.tag_accesses 14615371 # Number of tag accesses
1709system.cpu1.icache.tags.data_accesses 14615371 # Number of data accesses
1710system.cpu1.icache.ReadReq_hits::cpu1.inst 6021932 # number of ReadReq hits
1711system.cpu1.icache.ReadReq_hits::total 6021932 # number of ReadReq hits
1712system.cpu1.icache.demand_hits::cpu1.inst 6021932 # number of demand (read+write) hits
1713system.cpu1.icache.demand_hits::total 6021932 # number of demand (read+write) hits
1714system.cpu1.icache.overall_hits::cpu1.inst 6021932 # number of overall hits
1715system.cpu1.icache.overall_hits::total 6021932 # number of overall hits
1716system.cpu1.icache.ReadReq_misses::cpu1.inst 857169 # number of ReadReq misses
1717system.cpu1.icache.ReadReq_misses::total 857169 # number of ReadReq misses
1718system.cpu1.icache.demand_misses::cpu1.inst 857169 # number of demand (read+write) misses
1719system.cpu1.icache.demand_misses::total 857169 # number of demand (read+write) misses
1720system.cpu1.icache.overall_misses::cpu1.inst 857169 # number of overall misses
1721system.cpu1.icache.overall_misses::total 857169 # number of overall misses
1722system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7590039500 # number of ReadReq miss cycles
1723system.cpu1.icache.ReadReq_miss_latency::total 7590039500 # number of ReadReq miss cycles
1724system.cpu1.icache.demand_miss_latency::cpu1.inst 7590039500 # number of demand (read+write) miss cycles
1725system.cpu1.icache.demand_miss_latency::total 7590039500 # number of demand (read+write) miss cycles
1726system.cpu1.icache.overall_miss_latency::cpu1.inst 7590039500 # number of overall miss cycles
1727system.cpu1.icache.overall_miss_latency::total 7590039500 # number of overall miss cycles
1728system.cpu1.icache.ReadReq_accesses::cpu1.inst 6879101 # number of ReadReq accesses(hits+misses)
1729system.cpu1.icache.ReadReq_accesses::total 6879101 # number of ReadReq accesses(hits+misses)
1730system.cpu1.icache.demand_accesses::cpu1.inst 6879101 # number of demand (read+write) accesses
1731system.cpu1.icache.demand_accesses::total 6879101 # number of demand (read+write) accesses
1732system.cpu1.icache.overall_accesses::cpu1.inst 6879101 # number of overall (read+write) accesses
1733system.cpu1.icache.overall_accesses::total 6879101 # number of overall (read+write) accesses
1734system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124605 # miss rate for ReadReq accesses
1735system.cpu1.icache.ReadReq_miss_rate::total 0.124605 # miss rate for ReadReq accesses
1736system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124605 # miss rate for demand accesses
1737system.cpu1.icache.demand_miss_rate::total 0.124605 # miss rate for demand accesses
1738system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124605 # miss rate for overall accesses
1739system.cpu1.icache.overall_miss_rate::total 0.124605 # miss rate for overall accesses
1740system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8854.776013 # average ReadReq miss latency
1741system.cpu1.icache.ReadReq_avg_miss_latency::total 8854.776013 # average ReadReq miss latency
1742system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency
1743system.cpu1.icache.demand_avg_miss_latency::total 8854.776013 # average overall miss latency
1744system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency
1745system.cpu1.icache.overall_avg_miss_latency::total 8854.776013 # average overall miss latency
1746system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1747system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1748system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1749system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1750system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1751system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1776system.cpu1.icache.fast_writes 0 # number of fast writes performed
1777system.cpu1.icache.cache_copies 0 # number of cache copies performed

1778system.cpu1.icache.writebacks::writebacks 856657 # number of writebacks
1779system.cpu1.icache.writebacks::total 856657 # number of writebacks
1780system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # number of ReadReq MSHR misses
1781system.cpu1.icache.ReadReq_mshr_misses::total 857169 # number of ReadReq MSHR misses
1782system.cpu1.icache.demand_mshr_misses::cpu1.inst 857169 # number of demand (read+write) MSHR misses
1783system.cpu1.icache.demand_mshr_misses::total 857169 # number of demand (read+write) MSHR misses
1784system.cpu1.icache.overall_mshr_misses::cpu1.inst 857169 # number of overall MSHR misses
1785system.cpu1.icache.overall_mshr_misses::total 857169 # number of overall MSHR misses
1786system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
1787system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable
1788system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
1789system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses
1790system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7161455000 # number of ReadReq MSHR miss cycles
1791system.cpu1.icache.ReadReq_mshr_miss_latency::total 7161455000 # number of ReadReq MSHR miss cycles
1792system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7161455000 # number of demand (read+write) MSHR miss cycles
1793system.cpu1.icache.demand_mshr_miss_latency::total 7161455000 # number of demand (read+write) MSHR miss cycles
1794system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7161455000 # number of overall MSHR miss cycles
1795system.cpu1.icache.overall_mshr_miss_latency::total 7161455000 # number of overall MSHR miss cycles
1796system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15471500 # number of ReadReq MSHR uncacheable cycles
1797system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15471500 # number of ReadReq MSHR uncacheable cycles
1798system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15471500 # number of overall MSHR uncacheable cycles
1799system.cpu1.icache.overall_mshr_uncacheable_latency::total 15471500 # number of overall MSHR uncacheable cycles
1800system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for ReadReq accesses
1801system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124605 # mshr miss rate for ReadReq accesses
1802system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for demand accesses
1803system.cpu1.icache.demand_mshr_miss_rate::total 0.124605 # mshr miss rate for demand accesses
1804system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for overall accesses
1805system.cpu1.icache.overall_mshr_miss_rate::total 0.124605 # mshr miss rate for overall accesses
1806system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average ReadReq mshr miss latency
1807system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8354.776013 # average ReadReq mshr miss latency
1808system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1809system.cpu1.icache.demand_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1810system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1811system.cpu1.icache.overall_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1812system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average ReadReq mshr uncacheable latency
1813system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency
1814system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency
1815system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency

1752system.cpu1.icache.writebacks::writebacks 856657 # number of writebacks
1753system.cpu1.icache.writebacks::total 856657 # number of writebacks
1754system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # number of ReadReq MSHR misses
1755system.cpu1.icache.ReadReq_mshr_misses::total 857169 # number of ReadReq MSHR misses
1756system.cpu1.icache.demand_mshr_misses::cpu1.inst 857169 # number of demand (read+write) MSHR misses
1757system.cpu1.icache.demand_mshr_misses::total 857169 # number of demand (read+write) MSHR misses
1758system.cpu1.icache.overall_mshr_misses::cpu1.inst 857169 # number of overall MSHR misses
1759system.cpu1.icache.overall_mshr_misses::total 857169 # number of overall MSHR misses
1760system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
1761system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable
1762system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
1763system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses
1764system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7161455000 # number of ReadReq MSHR miss cycles
1765system.cpu1.icache.ReadReq_mshr_miss_latency::total 7161455000 # number of ReadReq MSHR miss cycles
1766system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7161455000 # number of demand (read+write) MSHR miss cycles
1767system.cpu1.icache.demand_mshr_miss_latency::total 7161455000 # number of demand (read+write) MSHR miss cycles
1768system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7161455000 # number of overall MSHR miss cycles
1769system.cpu1.icache.overall_mshr_miss_latency::total 7161455000 # number of overall MSHR miss cycles
1770system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15471500 # number of ReadReq MSHR uncacheable cycles
1771system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15471500 # number of ReadReq MSHR uncacheable cycles
1772system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15471500 # number of overall MSHR uncacheable cycles
1773system.cpu1.icache.overall_mshr_uncacheable_latency::total 15471500 # number of overall MSHR uncacheable cycles
1774system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for ReadReq accesses
1775system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124605 # mshr miss rate for ReadReq accesses
1776system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for demand accesses
1777system.cpu1.icache.demand_mshr_miss_rate::total 0.124605 # mshr miss rate for demand accesses
1778system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for overall accesses
1779system.cpu1.icache.overall_mshr_miss_rate::total 0.124605 # mshr miss rate for overall accesses
1780system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average ReadReq mshr miss latency
1781system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8354.776013 # average ReadReq mshr miss latency
1782system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1783system.cpu1.icache.demand_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1784system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1785system.cpu1.icache.overall_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1786system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average ReadReq mshr uncacheable latency
1787system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency
1788system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency
1789system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency

1816system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate

1817system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued
1818system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified
1819system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue
1820system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1821system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1822system.cpu1.l2cache.prefetcher.pfSpanPage 49365 # number of prefetches not generated due to page crossing
1823system.cpu1.l2cache.tags.replacements 38167 # number of replacements
1824system.cpu1.l2cache.tags.tagsinuse 15174.819793 # Cycle average of tags in use
1825system.cpu1.l2cache.tags.total_refs 1843147 # Total number of references to valid blocks.
1826system.cpu1.l2cache.tags.sampled_refs 53515 # Sample count of references to valid blocks.
1827system.cpu1.l2cache.tags.avg_refs 34.441689 # Average number of references to valid blocks.
1828system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1829system.cpu1.l2cache.tags.occ_blocks::writebacks 14738.835731 # Average occupied blocks per requestor
1830system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.198599 # Average occupied blocks per requestor
1831system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.090889 # Average occupied blocks per requestor
1832system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 401.694574 # Average occupied blocks per requestor
1833system.cpu1.l2cache.tags.occ_percent::writebacks 0.899587 # Average percentage of cache occupancy
1834system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002087 # Average percentage of cache occupancy
1835system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy
1836system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.024517 # Average percentage of cache occupancy
1837system.cpu1.l2cache.tags.occ_percent::total 0.926197 # Average percentage of cache occupancy
1838system.cpu1.l2cache.tags.occ_task_id_blocks::1022 877 # Occupied blocks per task id
1839system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id
1840system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14388 # Occupied blocks per task id
1841system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id
1842system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id
1843system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 826 # Occupied blocks per task id
1844system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id
1845system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
1846system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id
1847system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id
1848system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2130 # Occupied blocks per task id
1849system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11914 # Occupied blocks per task id
1850system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.053528 # Percentage of cache occupancy per task id
1851system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id
1852system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.878174 # Percentage of cache occupancy per task id
1853system.cpu1.l2cache.tags.tag_accesses 34225299 # Number of tag accesses
1854system.cpu1.l2cache.tags.data_accesses 34225299 # Number of data accesses
1855system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24322 # number of ReadReq hits
1856system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2742 # number of ReadReq hits
1857system.cpu1.l2cache.ReadReq_hits::total 27064 # number of ReadReq hits
1858system.cpu1.l2cache.WritebackDirty_hits::writebacks 94449 # number of WritebackDirty hits
1859system.cpu1.l2cache.WritebackDirty_hits::total 94449 # number of WritebackDirty hits
1860system.cpu1.l2cache.WritebackClean_hits::writebacks 899051 # number of WritebackClean hits
1861system.cpu1.l2cache.WritebackClean_hits::total 899051 # number of WritebackClean hits
1862system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18073 # number of ReadExReq hits
1863system.cpu1.l2cache.ReadExReq_hits::total 18073 # number of ReadExReq hits
1864system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 844303 # number of ReadCleanReq hits
1865system.cpu1.l2cache.ReadCleanReq_hits::total 844303 # number of ReadCleanReq hits
1866system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 82475 # number of ReadSharedReq hits
1867system.cpu1.l2cache.ReadSharedReq_hits::total 82475 # number of ReadSharedReq hits
1868system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24322 # number of demand (read+write) hits
1869system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2742 # number of demand (read+write) hits
1870system.cpu1.l2cache.demand_hits::cpu1.inst 844303 # number of demand (read+write) hits
1871system.cpu1.l2cache.demand_hits::cpu1.data 100548 # number of demand (read+write) hits
1872system.cpu1.l2cache.demand_hits::total 971915 # number of demand (read+write) hits
1873system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24322 # number of overall hits
1874system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2742 # number of overall hits
1875system.cpu1.l2cache.overall_hits::cpu1.inst 844303 # number of overall hits
1876system.cpu1.l2cache.overall_hits::cpu1.data 100548 # number of overall hits
1877system.cpu1.l2cache.overall_hits::total 971915 # number of overall hits
1878system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 663 # number of ReadReq misses
1879system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 241 # number of ReadReq misses
1880system.cpu1.l2cache.ReadReq_misses::total 904 # number of ReadReq misses
1881system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29265 # number of UpgradeReq misses
1882system.cpu1.l2cache.UpgradeReq_misses::total 29265 # number of UpgradeReq misses
1883system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23415 # number of SCUpgradeReq misses
1884system.cpu1.l2cache.SCUpgradeReq_misses::total 23415 # number of SCUpgradeReq misses
1885system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
1886system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
1887system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32287 # number of ReadExReq misses
1888system.cpu1.l2cache.ReadExReq_misses::total 32287 # number of ReadExReq misses
1889system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12866 # number of ReadCleanReq misses
1890system.cpu1.l2cache.ReadCleanReq_misses::total 12866 # number of ReadCleanReq misses
1891system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 66621 # number of ReadSharedReq misses
1892system.cpu1.l2cache.ReadSharedReq_misses::total 66621 # number of ReadSharedReq misses
1893system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 663 # number of demand (read+write) misses
1894system.cpu1.l2cache.demand_misses::cpu1.itb.walker 241 # number of demand (read+write) misses
1895system.cpu1.l2cache.demand_misses::cpu1.inst 12866 # number of demand (read+write) misses
1896system.cpu1.l2cache.demand_misses::cpu1.data 98908 # number of demand (read+write) misses
1897system.cpu1.l2cache.demand_misses::total 112678 # number of demand (read+write) misses
1898system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 663 # number of overall misses
1899system.cpu1.l2cache.overall_misses::cpu1.itb.walker 241 # number of overall misses
1900system.cpu1.l2cache.overall_misses::cpu1.inst 12866 # number of overall misses
1901system.cpu1.l2cache.overall_misses::cpu1.data 98908 # number of overall misses
1902system.cpu1.l2cache.overall_misses::total 112678 # number of overall misses
1903system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14913000 # number of ReadReq miss cycles
1904system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4829500 # number of ReadReq miss cycles
1905system.cpu1.l2cache.ReadReq_miss_latency::total 19742500 # number of ReadReq miss cycles
1906system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64203500 # number of UpgradeReq miss cycles
1907system.cpu1.l2cache.UpgradeReq_miss_latency::total 64203500 # number of UpgradeReq miss cycles
1908system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 57147000 # number of SCUpgradeReq miss cycles
1909system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 57147000 # number of SCUpgradeReq miss cycles
1910system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1072999 # number of SCUpgradeFailReq miss cycles
1911system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1072999 # number of SCUpgradeFailReq miss cycles
1912system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1705106500 # number of ReadExReq miss cycles
1913system.cpu1.l2cache.ReadExReq_miss_latency::total 1705106500 # number of ReadExReq miss cycles
1914system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 739774500 # number of ReadCleanReq miss cycles
1915system.cpu1.l2cache.ReadCleanReq_miss_latency::total 739774500 # number of ReadCleanReq miss cycles
1916system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1604700496 # number of ReadSharedReq miss cycles
1917system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1604700496 # number of ReadSharedReq miss cycles
1918system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14913000 # number of demand (read+write) miss cycles
1919system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4829500 # number of demand (read+write) miss cycles
1920system.cpu1.l2cache.demand_miss_latency::cpu1.inst 739774500 # number of demand (read+write) miss cycles
1921system.cpu1.l2cache.demand_miss_latency::cpu1.data 3309806996 # number of demand (read+write) miss cycles
1922system.cpu1.l2cache.demand_miss_latency::total 4069323996 # number of demand (read+write) miss cycles
1923system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14913000 # number of overall miss cycles
1924system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4829500 # number of overall miss cycles
1925system.cpu1.l2cache.overall_miss_latency::cpu1.inst 739774500 # number of overall miss cycles
1926system.cpu1.l2cache.overall_miss_latency::cpu1.data 3309806996 # number of overall miss cycles
1927system.cpu1.l2cache.overall_miss_latency::total 4069323996 # number of overall miss cycles
1928system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24985 # number of ReadReq accesses(hits+misses)
1929system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2983 # number of ReadReq accesses(hits+misses)
1930system.cpu1.l2cache.ReadReq_accesses::total 27968 # number of ReadReq accesses(hits+misses)
1931system.cpu1.l2cache.WritebackDirty_accesses::writebacks 94449 # number of WritebackDirty accesses(hits+misses)
1932system.cpu1.l2cache.WritebackDirty_accesses::total 94449 # number of WritebackDirty accesses(hits+misses)
1933system.cpu1.l2cache.WritebackClean_accesses::writebacks 899051 # number of WritebackClean accesses(hits+misses)
1934system.cpu1.l2cache.WritebackClean_accesses::total 899051 # number of WritebackClean accesses(hits+misses)
1935system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29265 # number of UpgradeReq accesses(hits+misses)
1936system.cpu1.l2cache.UpgradeReq_accesses::total 29265 # number of UpgradeReq accesses(hits+misses)
1937system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23415 # number of SCUpgradeReq accesses(hits+misses)
1938system.cpu1.l2cache.SCUpgradeReq_accesses::total 23415 # number of SCUpgradeReq accesses(hits+misses)
1939system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1940system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1941system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50360 # number of ReadExReq accesses(hits+misses)
1942system.cpu1.l2cache.ReadExReq_accesses::total 50360 # number of ReadExReq accesses(hits+misses)
1943system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 857169 # number of ReadCleanReq accesses(hits+misses)
1944system.cpu1.l2cache.ReadCleanReq_accesses::total 857169 # number of ReadCleanReq accesses(hits+misses)
1945system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 149096 # number of ReadSharedReq accesses(hits+misses)
1946system.cpu1.l2cache.ReadSharedReq_accesses::total 149096 # number of ReadSharedReq accesses(hits+misses)
1947system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24985 # number of demand (read+write) accesses
1948system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2983 # number of demand (read+write) accesses
1949system.cpu1.l2cache.demand_accesses::cpu1.inst 857169 # number of demand (read+write) accesses
1950system.cpu1.l2cache.demand_accesses::cpu1.data 199456 # number of demand (read+write) accesses
1951system.cpu1.l2cache.demand_accesses::total 1084593 # number of demand (read+write) accesses
1952system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24985 # number of overall (read+write) accesses
1953system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2983 # number of overall (read+write) accesses
1954system.cpu1.l2cache.overall_accesses::cpu1.inst 857169 # number of overall (read+write) accesses
1955system.cpu1.l2cache.overall_accesses::cpu1.data 199456 # number of overall (read+write) accesses
1956system.cpu1.l2cache.overall_accesses::total 1084593 # number of overall (read+write) accesses
1957system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026536 # miss rate for ReadReq accesses
1958system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.080791 # miss rate for ReadReq accesses
1959system.cpu1.l2cache.ReadReq_miss_rate::total 0.032323 # miss rate for ReadReq accesses
1960system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1961system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1962system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1963system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1964system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1965system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1966system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.641124 # miss rate for ReadExReq accesses
1967system.cpu1.l2cache.ReadExReq_miss_rate::total 0.641124 # miss rate for ReadExReq accesses
1968system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.015010 # miss rate for ReadCleanReq accesses
1969system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.015010 # miss rate for ReadCleanReq accesses
1970system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.446833 # miss rate for ReadSharedReq accesses
1971system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.446833 # miss rate for ReadSharedReq accesses
1972system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026536 # miss rate for demand accesses
1973system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.080791 # miss rate for demand accesses
1974system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.015010 # miss rate for demand accesses
1975system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495889 # miss rate for demand accesses
1976system.cpu1.l2cache.demand_miss_rate::total 0.103890 # miss rate for demand accesses
1977system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026536 # miss rate for overall accesses
1978system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.080791 # miss rate for overall accesses
1979system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.015010 # miss rate for overall accesses
1980system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495889 # miss rate for overall accesses
1981system.cpu1.l2cache.overall_miss_rate::total 0.103890 # miss rate for overall accesses
1982system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22493.212670 # average ReadReq miss latency
1983system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20039.419087 # average ReadReq miss latency
1984system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21839.048673 # average ReadReq miss latency
1985system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2193.866393 # average UpgradeReq miss latency
1986system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2193.866393 # average UpgradeReq miss latency
1987system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2440.614990 # average SCUpgradeReq miss latency
1988system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2440.614990 # average SCUpgradeReq miss latency
1989system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 536499.500000 # average SCUpgradeFailReq miss latency
1990system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 536499.500000 # average SCUpgradeFailReq miss latency
1991system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52810.930096 # average ReadExReq miss latency
1992system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52810.930096 # average ReadExReq miss latency
1993system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 57498.406653 # average ReadCleanReq miss latency
1994system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 57498.406653 # average ReadCleanReq miss latency
1995system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24087.007040 # average ReadSharedReq miss latency
1996system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24087.007040 # average ReadSharedReq miss latency
1997system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22493.212670 # average overall miss latency
1998system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20039.419087 # average overall miss latency
1999system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 57498.406653 # average overall miss latency
2000system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33463.491285 # average overall miss latency
2001system.cpu1.l2cache.demand_avg_miss_latency::total 36114.627487 # average overall miss latency
2002system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22493.212670 # average overall miss latency
2003system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20039.419087 # average overall miss latency
2004system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 57498.406653 # average overall miss latency
2005system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33463.491285 # average overall miss latency
2006system.cpu1.l2cache.overall_avg_miss_latency::total 36114.627487 # average overall miss latency
2007system.cpu1.l2cache.blocked_cycles::no_mshrs 30 # number of cycles access was blocked
2008system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2009system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
2010system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2011system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
2012system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1790system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued
1791system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified
1792system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue
1793system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1794system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1795system.cpu1.l2cache.prefetcher.pfSpanPage 49365 # number of prefetches not generated due to page crossing
1796system.cpu1.l2cache.tags.replacements 38167 # number of replacements
1797system.cpu1.l2cache.tags.tagsinuse 15174.819793 # Cycle average of tags in use
1798system.cpu1.l2cache.tags.total_refs 1843147 # Total number of references to valid blocks.
1799system.cpu1.l2cache.tags.sampled_refs 53515 # Sample count of references to valid blocks.
1800system.cpu1.l2cache.tags.avg_refs 34.441689 # Average number of references to valid blocks.
1801system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1802system.cpu1.l2cache.tags.occ_blocks::writebacks 14738.835731 # Average occupied blocks per requestor
1803system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.198599 # Average occupied blocks per requestor
1804system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.090889 # Average occupied blocks per requestor
1805system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 401.694574 # Average occupied blocks per requestor
1806system.cpu1.l2cache.tags.occ_percent::writebacks 0.899587 # Average percentage of cache occupancy
1807system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002087 # Average percentage of cache occupancy
1808system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy
1809system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.024517 # Average percentage of cache occupancy
1810system.cpu1.l2cache.tags.occ_percent::total 0.926197 # Average percentage of cache occupancy
1811system.cpu1.l2cache.tags.occ_task_id_blocks::1022 877 # Occupied blocks per task id
1812system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id
1813system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14388 # Occupied blocks per task id
1814system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id
1815system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id
1816system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 826 # Occupied blocks per task id
1817system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id
1818system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
1819system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id
1820system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id
1821system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2130 # Occupied blocks per task id
1822system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11914 # Occupied blocks per task id
1823system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.053528 # Percentage of cache occupancy per task id
1824system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id
1825system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.878174 # Percentage of cache occupancy per task id
1826system.cpu1.l2cache.tags.tag_accesses 34225299 # Number of tag accesses
1827system.cpu1.l2cache.tags.data_accesses 34225299 # Number of data accesses
1828system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24322 # number of ReadReq hits
1829system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2742 # number of ReadReq hits
1830system.cpu1.l2cache.ReadReq_hits::total 27064 # number of ReadReq hits
1831system.cpu1.l2cache.WritebackDirty_hits::writebacks 94449 # number of WritebackDirty hits
1832system.cpu1.l2cache.WritebackDirty_hits::total 94449 # number of WritebackDirty hits
1833system.cpu1.l2cache.WritebackClean_hits::writebacks 899051 # number of WritebackClean hits
1834system.cpu1.l2cache.WritebackClean_hits::total 899051 # number of WritebackClean hits
1835system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18073 # number of ReadExReq hits
1836system.cpu1.l2cache.ReadExReq_hits::total 18073 # number of ReadExReq hits
1837system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 844303 # number of ReadCleanReq hits
1838system.cpu1.l2cache.ReadCleanReq_hits::total 844303 # number of ReadCleanReq hits
1839system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 82475 # number of ReadSharedReq hits
1840system.cpu1.l2cache.ReadSharedReq_hits::total 82475 # number of ReadSharedReq hits
1841system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24322 # number of demand (read+write) hits
1842system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2742 # number of demand (read+write) hits
1843system.cpu1.l2cache.demand_hits::cpu1.inst 844303 # number of demand (read+write) hits
1844system.cpu1.l2cache.demand_hits::cpu1.data 100548 # number of demand (read+write) hits
1845system.cpu1.l2cache.demand_hits::total 971915 # number of demand (read+write) hits
1846system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24322 # number of overall hits
1847system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2742 # number of overall hits
1848system.cpu1.l2cache.overall_hits::cpu1.inst 844303 # number of overall hits
1849system.cpu1.l2cache.overall_hits::cpu1.data 100548 # number of overall hits
1850system.cpu1.l2cache.overall_hits::total 971915 # number of overall hits
1851system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 663 # number of ReadReq misses
1852system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 241 # number of ReadReq misses
1853system.cpu1.l2cache.ReadReq_misses::total 904 # number of ReadReq misses
1854system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29265 # number of UpgradeReq misses
1855system.cpu1.l2cache.UpgradeReq_misses::total 29265 # number of UpgradeReq misses
1856system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23415 # number of SCUpgradeReq misses
1857system.cpu1.l2cache.SCUpgradeReq_misses::total 23415 # number of SCUpgradeReq misses
1858system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
1859system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
1860system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32287 # number of ReadExReq misses
1861system.cpu1.l2cache.ReadExReq_misses::total 32287 # number of ReadExReq misses
1862system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12866 # number of ReadCleanReq misses
1863system.cpu1.l2cache.ReadCleanReq_misses::total 12866 # number of ReadCleanReq misses
1864system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 66621 # number of ReadSharedReq misses
1865system.cpu1.l2cache.ReadSharedReq_misses::total 66621 # number of ReadSharedReq misses
1866system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 663 # number of demand (read+write) misses
1867system.cpu1.l2cache.demand_misses::cpu1.itb.walker 241 # number of demand (read+write) misses
1868system.cpu1.l2cache.demand_misses::cpu1.inst 12866 # number of demand (read+write) misses
1869system.cpu1.l2cache.demand_misses::cpu1.data 98908 # number of demand (read+write) misses
1870system.cpu1.l2cache.demand_misses::total 112678 # number of demand (read+write) misses
1871system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 663 # number of overall misses
1872system.cpu1.l2cache.overall_misses::cpu1.itb.walker 241 # number of overall misses
1873system.cpu1.l2cache.overall_misses::cpu1.inst 12866 # number of overall misses
1874system.cpu1.l2cache.overall_misses::cpu1.data 98908 # number of overall misses
1875system.cpu1.l2cache.overall_misses::total 112678 # number of overall misses
1876system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14913000 # number of ReadReq miss cycles
1877system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4829500 # number of ReadReq miss cycles
1878system.cpu1.l2cache.ReadReq_miss_latency::total 19742500 # number of ReadReq miss cycles
1879system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64203500 # number of UpgradeReq miss cycles
1880system.cpu1.l2cache.UpgradeReq_miss_latency::total 64203500 # number of UpgradeReq miss cycles
1881system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 57147000 # number of SCUpgradeReq miss cycles
1882system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 57147000 # number of SCUpgradeReq miss cycles
1883system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1072999 # number of SCUpgradeFailReq miss cycles
1884system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1072999 # number of SCUpgradeFailReq miss cycles
1885system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1705106500 # number of ReadExReq miss cycles
1886system.cpu1.l2cache.ReadExReq_miss_latency::total 1705106500 # number of ReadExReq miss cycles
1887system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 739774500 # number of ReadCleanReq miss cycles
1888system.cpu1.l2cache.ReadCleanReq_miss_latency::total 739774500 # number of ReadCleanReq miss cycles
1889system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1604700496 # number of ReadSharedReq miss cycles
1890system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1604700496 # number of ReadSharedReq miss cycles
1891system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14913000 # number of demand (read+write) miss cycles
1892system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4829500 # number of demand (read+write) miss cycles
1893system.cpu1.l2cache.demand_miss_latency::cpu1.inst 739774500 # number of demand (read+write) miss cycles
1894system.cpu1.l2cache.demand_miss_latency::cpu1.data 3309806996 # number of demand (read+write) miss cycles
1895system.cpu1.l2cache.demand_miss_latency::total 4069323996 # number of demand (read+write) miss cycles
1896system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14913000 # number of overall miss cycles
1897system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4829500 # number of overall miss cycles
1898system.cpu1.l2cache.overall_miss_latency::cpu1.inst 739774500 # number of overall miss cycles
1899system.cpu1.l2cache.overall_miss_latency::cpu1.data 3309806996 # number of overall miss cycles
1900system.cpu1.l2cache.overall_miss_latency::total 4069323996 # number of overall miss cycles
1901system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24985 # number of ReadReq accesses(hits+misses)
1902system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2983 # number of ReadReq accesses(hits+misses)
1903system.cpu1.l2cache.ReadReq_accesses::total 27968 # number of ReadReq accesses(hits+misses)
1904system.cpu1.l2cache.WritebackDirty_accesses::writebacks 94449 # number of WritebackDirty accesses(hits+misses)
1905system.cpu1.l2cache.WritebackDirty_accesses::total 94449 # number of WritebackDirty accesses(hits+misses)
1906system.cpu1.l2cache.WritebackClean_accesses::writebacks 899051 # number of WritebackClean accesses(hits+misses)
1907system.cpu1.l2cache.WritebackClean_accesses::total 899051 # number of WritebackClean accesses(hits+misses)
1908system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29265 # number of UpgradeReq accesses(hits+misses)
1909system.cpu1.l2cache.UpgradeReq_accesses::total 29265 # number of UpgradeReq accesses(hits+misses)
1910system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23415 # number of SCUpgradeReq accesses(hits+misses)
1911system.cpu1.l2cache.SCUpgradeReq_accesses::total 23415 # number of SCUpgradeReq accesses(hits+misses)
1912system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1913system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1914system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50360 # number of ReadExReq accesses(hits+misses)
1915system.cpu1.l2cache.ReadExReq_accesses::total 50360 # number of ReadExReq accesses(hits+misses)
1916system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 857169 # number of ReadCleanReq accesses(hits+misses)
1917system.cpu1.l2cache.ReadCleanReq_accesses::total 857169 # number of ReadCleanReq accesses(hits+misses)
1918system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 149096 # number of ReadSharedReq accesses(hits+misses)
1919system.cpu1.l2cache.ReadSharedReq_accesses::total 149096 # number of ReadSharedReq accesses(hits+misses)
1920system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24985 # number of demand (read+write) accesses
1921system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2983 # number of demand (read+write) accesses
1922system.cpu1.l2cache.demand_accesses::cpu1.inst 857169 # number of demand (read+write) accesses
1923system.cpu1.l2cache.demand_accesses::cpu1.data 199456 # number of demand (read+write) accesses
1924system.cpu1.l2cache.demand_accesses::total 1084593 # number of demand (read+write) accesses
1925system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24985 # number of overall (read+write) accesses
1926system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2983 # number of overall (read+write) accesses
1927system.cpu1.l2cache.overall_accesses::cpu1.inst 857169 # number of overall (read+write) accesses
1928system.cpu1.l2cache.overall_accesses::cpu1.data 199456 # number of overall (read+write) accesses
1929system.cpu1.l2cache.overall_accesses::total 1084593 # number of overall (read+write) accesses
1930system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026536 # miss rate for ReadReq accesses
1931system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.080791 # miss rate for ReadReq accesses
1932system.cpu1.l2cache.ReadReq_miss_rate::total 0.032323 # miss rate for ReadReq accesses
1933system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1934system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1935system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1936system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1937system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1938system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1939system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.641124 # miss rate for ReadExReq accesses
1940system.cpu1.l2cache.ReadExReq_miss_rate::total 0.641124 # miss rate for ReadExReq accesses
1941system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.015010 # miss rate for ReadCleanReq accesses
1942system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.015010 # miss rate for ReadCleanReq accesses
1943system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.446833 # miss rate for ReadSharedReq accesses
1944system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.446833 # miss rate for ReadSharedReq accesses
1945system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026536 # miss rate for demand accesses
1946system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.080791 # miss rate for demand accesses
1947system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.015010 # miss rate for demand accesses
1948system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495889 # miss rate for demand accesses
1949system.cpu1.l2cache.demand_miss_rate::total 0.103890 # miss rate for demand accesses
1950system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026536 # miss rate for overall accesses
1951system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.080791 # miss rate for overall accesses
1952system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.015010 # miss rate for overall accesses
1953system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495889 # miss rate for overall accesses
1954system.cpu1.l2cache.overall_miss_rate::total 0.103890 # miss rate for overall accesses
1955system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22493.212670 # average ReadReq miss latency
1956system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20039.419087 # average ReadReq miss latency
1957system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21839.048673 # average ReadReq miss latency
1958system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2193.866393 # average UpgradeReq miss latency
1959system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2193.866393 # average UpgradeReq miss latency
1960system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2440.614990 # average SCUpgradeReq miss latency
1961system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2440.614990 # average SCUpgradeReq miss latency
1962system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 536499.500000 # average SCUpgradeFailReq miss latency
1963system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 536499.500000 # average SCUpgradeFailReq miss latency
1964system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52810.930096 # average ReadExReq miss latency
1965system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52810.930096 # average ReadExReq miss latency
1966system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 57498.406653 # average ReadCleanReq miss latency
1967system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 57498.406653 # average ReadCleanReq miss latency
1968system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24087.007040 # average ReadSharedReq miss latency
1969system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24087.007040 # average ReadSharedReq miss latency
1970system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22493.212670 # average overall miss latency
1971system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20039.419087 # average overall miss latency
1972system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 57498.406653 # average overall miss latency
1973system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33463.491285 # average overall miss latency
1974system.cpu1.l2cache.demand_avg_miss_latency::total 36114.627487 # average overall miss latency
1975system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22493.212670 # average overall miss latency
1976system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20039.419087 # average overall miss latency
1977system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 57498.406653 # average overall miss latency
1978system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33463.491285 # average overall miss latency
1979system.cpu1.l2cache.overall_avg_miss_latency::total 36114.627487 # average overall miss latency
1980system.cpu1.l2cache.blocked_cycles::no_mshrs 30 # number of cycles access was blocked
1981system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1982system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1983system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1984system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
1985system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2013system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2014system.cpu1.l2cache.cache_copies 0 # number of cache copies performed

2015system.cpu1.l2cache.unused_prefetches 580 # number of HardPF blocks evicted w/o reference
2016system.cpu1.l2cache.writebacks::writebacks 29115 # number of writebacks
2017system.cpu1.l2cache.writebacks::total 29115 # number of writebacks
2018system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 240 # number of ReadExReq MSHR hits
2019system.cpu1.l2cache.ReadExReq_mshr_hits::total 240 # number of ReadExReq MSHR hits
2020system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
2021system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
2022system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 39 # number of ReadSharedReq MSHR hits
2023system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 39 # number of ReadSharedReq MSHR hits
2024system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
2025system.cpu1.l2cache.demand_mshr_hits::cpu1.data 279 # number of demand (read+write) MSHR hits
2026system.cpu1.l2cache.demand_mshr_hits::total 288 # number of demand (read+write) MSHR hits
2027system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
2028system.cpu1.l2cache.overall_mshr_hits::cpu1.data 279 # number of overall MSHR hits
2029system.cpu1.l2cache.overall_mshr_hits::total 288 # number of overall MSHR hits
2030system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 663 # number of ReadReq MSHR misses
2031system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 241 # number of ReadReq MSHR misses
2032system.cpu1.l2cache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses
2033system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19989 # number of HardPFReq MSHR misses
2034system.cpu1.l2cache.HardPFReq_mshr_misses::total 19989 # number of HardPFReq MSHR misses
2035system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29265 # number of UpgradeReq MSHR misses
2036system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29265 # number of UpgradeReq MSHR misses
2037system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23415 # number of SCUpgradeReq MSHR misses
2038system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23415 # number of SCUpgradeReq MSHR misses
2039system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
2040system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
2041system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32047 # number of ReadExReq MSHR misses
2042system.cpu1.l2cache.ReadExReq_mshr_misses::total 32047 # number of ReadExReq MSHR misses
2043system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 12857 # number of ReadCleanReq MSHR misses
2044system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 12857 # number of ReadCleanReq MSHR misses
2045system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 66582 # number of ReadSharedReq MSHR misses
2046system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 66582 # number of ReadSharedReq MSHR misses
2047system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 663 # number of demand (read+write) MSHR misses
2048system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 241 # number of demand (read+write) MSHR misses
2049system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 12857 # number of demand (read+write) MSHR misses
2050system.cpu1.l2cache.demand_mshr_misses::cpu1.data 98629 # number of demand (read+write) MSHR misses
2051system.cpu1.l2cache.demand_mshr_misses::total 112390 # number of demand (read+write) MSHR misses
2052system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 663 # number of overall MSHR misses
2053system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 241 # number of overall MSHR misses
2054system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 12857 # number of overall MSHR misses
2055system.cpu1.l2cache.overall_mshr_misses::cpu1.data 98629 # number of overall MSHR misses
2056system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19989 # number of overall MSHR misses
2057system.cpu1.l2cache.overall_mshr_misses::total 132379 # number of overall MSHR misses
2058system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
2059system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable
2060system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3085 # number of ReadReq MSHR uncacheable
2061system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable
2062system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable
2063system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
2064system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5284 # number of overall MSHR uncacheable misses
2065system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5396 # number of overall MSHR uncacheable misses
2066system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10935000 # number of ReadReq MSHR miss cycles
2067system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3383500 # number of ReadReq MSHR miss cycles
2068system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 14318500 # number of ReadReq MSHR miss cycles
2069system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of HardPFReq MSHR miss cycles
2070system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 962292245 # number of HardPFReq MSHR miss cycles
2071system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 589948999 # number of UpgradeReq MSHR miss cycles
2072system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 589948999 # number of UpgradeReq MSHR miss cycles
2073system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 435782000 # number of SCUpgradeReq MSHR miss cycles
2074system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 435782000 # number of SCUpgradeReq MSHR miss cycles
2075system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1000999 # number of SCUpgradeFailReq MSHR miss cycles
2076system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1000999 # number of SCUpgradeFailReq MSHR miss cycles
2077system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1490377000 # number of ReadExReq MSHR miss cycles
2078system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1490377000 # number of ReadExReq MSHR miss cycles
2079system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 662136000 # number of ReadCleanReq MSHR miss cycles
2080system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 662136000 # number of ReadCleanReq MSHR miss cycles
2081system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1202991996 # number of ReadSharedReq MSHR miss cycles
2082system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1202991996 # number of ReadSharedReq MSHR miss cycles
2083system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10935000 # number of demand (read+write) MSHR miss cycles
2084system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3383500 # number of demand (read+write) MSHR miss cycles
2085system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 662136000 # number of demand (read+write) MSHR miss cycles
2086system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2693368996 # number of demand (read+write) MSHR miss cycles
2087system.cpu1.l2cache.demand_mshr_miss_latency::total 3369823496 # number of demand (read+write) MSHR miss cycles
2088system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10935000 # number of overall MSHR miss cycles
2089system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3383500 # number of overall MSHR miss cycles
2090system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 662136000 # number of overall MSHR miss cycles
2091system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2693368996 # number of overall MSHR miss cycles
2092system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of overall MSHR miss cycles
2093system.cpu1.l2cache.overall_mshr_miss_latency::total 4332115741 # number of overall MSHR miss cycles
2094system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14575500 # number of ReadReq MSHR uncacheable cycles
2095system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365633500 # number of ReadReq MSHR uncacheable cycles
2096system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 380209000 # number of ReadReq MSHR uncacheable cycles

1986system.cpu1.l2cache.unused_prefetches 580 # number of HardPF blocks evicted w/o reference
1987system.cpu1.l2cache.writebacks::writebacks 29115 # number of writebacks
1988system.cpu1.l2cache.writebacks::total 29115 # number of writebacks
1989system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 240 # number of ReadExReq MSHR hits
1990system.cpu1.l2cache.ReadExReq_mshr_hits::total 240 # number of ReadExReq MSHR hits
1991system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
1992system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
1993system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 39 # number of ReadSharedReq MSHR hits
1994system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 39 # number of ReadSharedReq MSHR hits
1995system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
1996system.cpu1.l2cache.demand_mshr_hits::cpu1.data 279 # number of demand (read+write) MSHR hits
1997system.cpu1.l2cache.demand_mshr_hits::total 288 # number of demand (read+write) MSHR hits
1998system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
1999system.cpu1.l2cache.overall_mshr_hits::cpu1.data 279 # number of overall MSHR hits
2000system.cpu1.l2cache.overall_mshr_hits::total 288 # number of overall MSHR hits
2001system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 663 # number of ReadReq MSHR misses
2002system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 241 # number of ReadReq MSHR misses
2003system.cpu1.l2cache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses
2004system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19989 # number of HardPFReq MSHR misses
2005system.cpu1.l2cache.HardPFReq_mshr_misses::total 19989 # number of HardPFReq MSHR misses
2006system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29265 # number of UpgradeReq MSHR misses
2007system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29265 # number of UpgradeReq MSHR misses
2008system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23415 # number of SCUpgradeReq MSHR misses
2009system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23415 # number of SCUpgradeReq MSHR misses
2010system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
2011system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
2012system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32047 # number of ReadExReq MSHR misses
2013system.cpu1.l2cache.ReadExReq_mshr_misses::total 32047 # number of ReadExReq MSHR misses
2014system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 12857 # number of ReadCleanReq MSHR misses
2015system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 12857 # number of ReadCleanReq MSHR misses
2016system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 66582 # number of ReadSharedReq MSHR misses
2017system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 66582 # number of ReadSharedReq MSHR misses
2018system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 663 # number of demand (read+write) MSHR misses
2019system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 241 # number of demand (read+write) MSHR misses
2020system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 12857 # number of demand (read+write) MSHR misses
2021system.cpu1.l2cache.demand_mshr_misses::cpu1.data 98629 # number of demand (read+write) MSHR misses
2022system.cpu1.l2cache.demand_mshr_misses::total 112390 # number of demand (read+write) MSHR misses
2023system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 663 # number of overall MSHR misses
2024system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 241 # number of overall MSHR misses
2025system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 12857 # number of overall MSHR misses
2026system.cpu1.l2cache.overall_mshr_misses::cpu1.data 98629 # number of overall MSHR misses
2027system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19989 # number of overall MSHR misses
2028system.cpu1.l2cache.overall_mshr_misses::total 132379 # number of overall MSHR misses
2029system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
2030system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable
2031system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3085 # number of ReadReq MSHR uncacheable
2032system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable
2033system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable
2034system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
2035system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5284 # number of overall MSHR uncacheable misses
2036system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5396 # number of overall MSHR uncacheable misses
2037system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10935000 # number of ReadReq MSHR miss cycles
2038system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3383500 # number of ReadReq MSHR miss cycles
2039system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 14318500 # number of ReadReq MSHR miss cycles
2040system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of HardPFReq MSHR miss cycles
2041system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 962292245 # number of HardPFReq MSHR miss cycles
2042system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 589948999 # number of UpgradeReq MSHR miss cycles
2043system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 589948999 # number of UpgradeReq MSHR miss cycles
2044system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 435782000 # number of SCUpgradeReq MSHR miss cycles
2045system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 435782000 # number of SCUpgradeReq MSHR miss cycles
2046system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1000999 # number of SCUpgradeFailReq MSHR miss cycles
2047system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1000999 # number of SCUpgradeFailReq MSHR miss cycles
2048system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1490377000 # number of ReadExReq MSHR miss cycles
2049system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1490377000 # number of ReadExReq MSHR miss cycles
2050system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 662136000 # number of ReadCleanReq MSHR miss cycles
2051system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 662136000 # number of ReadCleanReq MSHR miss cycles
2052system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1202991996 # number of ReadSharedReq MSHR miss cycles
2053system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1202991996 # number of ReadSharedReq MSHR miss cycles
2054system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10935000 # number of demand (read+write) MSHR miss cycles
2055system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3383500 # number of demand (read+write) MSHR miss cycles
2056system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 662136000 # number of demand (read+write) MSHR miss cycles
2057system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2693368996 # number of demand (read+write) MSHR miss cycles
2058system.cpu1.l2cache.demand_mshr_miss_latency::total 3369823496 # number of demand (read+write) MSHR miss cycles
2059system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10935000 # number of overall MSHR miss cycles
2060system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3383500 # number of overall MSHR miss cycles
2061system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 662136000 # number of overall MSHR miss cycles
2062system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2693368996 # number of overall MSHR miss cycles
2063system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of overall MSHR miss cycles
2064system.cpu1.l2cache.overall_mshr_miss_latency::total 4332115741 # number of overall MSHR miss cycles
2065system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14575500 # number of ReadReq MSHR uncacheable cycles
2066system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365633500 # number of ReadReq MSHR uncacheable cycles
2067system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 380209000 # number of ReadReq MSHR uncacheable cycles

2097system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 234344500 # number of WriteReq MSHR uncacheable cycles
2098system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 234344500 # number of WriteReq MSHR uncacheable cycles

2099system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14575500 # number of overall MSHR uncacheable cycles

2068system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14575500 # number of overall MSHR uncacheable cycles

2100system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 599978000 # number of overall MSHR uncacheable cycles
2101system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614553500 # number of overall MSHR uncacheable cycles

2069system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 365633500 # number of overall MSHR uncacheable cycles
2070system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 380209000 # number of overall MSHR uncacheable cycles

2102system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses
2103system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for ReadReq accesses
2104system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032323 # mshr miss rate for ReadReq accesses
2105system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2106system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2107system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2108system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2109system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2110system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2111system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2112system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2113system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.636358 # mshr miss rate for ReadExReq accesses
2114system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.636358 # mshr miss rate for ReadExReq accesses
2115system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for ReadCleanReq accesses
2116system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014999 # mshr miss rate for ReadCleanReq accesses
2117system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.446571 # mshr miss rate for ReadSharedReq accesses
2118system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.446571 # mshr miss rate for ReadSharedReq accesses
2119system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for demand accesses
2120system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for demand accesses
2121system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for demand accesses
2122system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for demand accesses
2123system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103624 # mshr miss rate for demand accesses
2124system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for overall accesses
2125system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for overall accesses
2126system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for overall accesses
2127system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for overall accesses
2128system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2129system.cpu1.l2cache.overall_mshr_miss_rate::total 0.122054 # mshr miss rate for overall accesses
2130system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average ReadReq mshr miss latency
2131system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average ReadReq mshr miss latency
2132system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15839.048673 # average ReadReq mshr miss latency
2133system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average HardPFReq mshr miss latency
2134system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48141.089849 # average HardPFReq mshr miss latency
2135system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20158.858671 # average UpgradeReq mshr miss latency
2136system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20158.858671 # average UpgradeReq mshr miss latency
2137system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18611.232116 # average SCUpgradeReq mshr miss latency
2138system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18611.232116 # average SCUpgradeReq mshr miss latency
2139system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500499.500000 # average SCUpgradeFailReq mshr miss latency
2140system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500499.500000 # average SCUpgradeFailReq mshr miss latency
2141system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46505.975598 # average ReadExReq mshr miss latency
2142system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46505.975598 # average ReadExReq mshr miss latency
2143system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average ReadCleanReq mshr miss latency
2144system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51500.038889 # average ReadCleanReq mshr miss latency
2145system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18067.826079 # average ReadSharedReq mshr miss latency
2146system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18067.826079 # average ReadSharedReq mshr miss latency
2147system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency
2148system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
2149system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
2150system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
2151system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29983.303639 # average overall mshr miss latency
2152system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency
2153system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
2154system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
2155system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
2156system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency
2157system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency
2158system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency
2159system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency
2160system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency

2071system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses
2072system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for ReadReq accesses
2073system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032323 # mshr miss rate for ReadReq accesses
2074system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2075system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2076system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2077system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2078system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2079system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2080system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2081system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2082system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.636358 # mshr miss rate for ReadExReq accesses
2083system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.636358 # mshr miss rate for ReadExReq accesses
2084system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for ReadCleanReq accesses
2085system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014999 # mshr miss rate for ReadCleanReq accesses
2086system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.446571 # mshr miss rate for ReadSharedReq accesses
2087system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.446571 # mshr miss rate for ReadSharedReq accesses
2088system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for demand accesses
2089system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for demand accesses
2090system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for demand accesses
2091system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for demand accesses
2092system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103624 # mshr miss rate for demand accesses
2093system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for overall accesses
2094system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for overall accesses
2095system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for overall accesses
2096system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for overall accesses
2097system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2098system.cpu1.l2cache.overall_mshr_miss_rate::total 0.122054 # mshr miss rate for overall accesses
2099system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average ReadReq mshr miss latency
2100system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average ReadReq mshr miss latency
2101system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15839.048673 # average ReadReq mshr miss latency
2102system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average HardPFReq mshr miss latency
2103system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48141.089849 # average HardPFReq mshr miss latency
2104system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20158.858671 # average UpgradeReq mshr miss latency
2105system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20158.858671 # average UpgradeReq mshr miss latency
2106system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18611.232116 # average SCUpgradeReq mshr miss latency
2107system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18611.232116 # average SCUpgradeReq mshr miss latency
2108system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500499.500000 # average SCUpgradeFailReq mshr miss latency
2109system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500499.500000 # average SCUpgradeFailReq mshr miss latency
2110system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46505.975598 # average ReadExReq mshr miss latency
2111system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46505.975598 # average ReadExReq mshr miss latency
2112system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average ReadCleanReq mshr miss latency
2113system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51500.038889 # average ReadCleanReq mshr miss latency
2114system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18067.826079 # average ReadSharedReq mshr miss latency
2115system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18067.826079 # average ReadSharedReq mshr miss latency
2116system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency
2117system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
2118system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
2119system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
2120system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29983.303639 # average overall mshr miss latency
2121system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency
2122system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
2123system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
2124system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
2125system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency
2126system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency
2127system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency
2128system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency
2129system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency

2161system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689 # average WriteReq mshr uncacheable latency
2162system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689 # average WriteReq mshr uncacheable latency

2163system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency

2130system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency

2164system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139 # average overall mshr uncacheable latency
2165system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087 # average overall mshr uncacheable latency
2166system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

2131system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69196.347464 # average overall mshr uncacheable latency
2132system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70461.267606 # average overall mshr uncacheable latency

2167system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter.
2168system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2169system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2170system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter.
2171system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2172system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2173system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution
2174system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution
2175system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution
2176system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution
2177system.cpu1.toL2Bus.trans_dist::WritebackDirty 124900 # Transaction distribution
2178system.cpu1.toL2Bus.trans_dist::WritebackClean 917333 # Transaction distribution
2179system.cpu1.toL2Bus.trans_dist::CleanEvict 97527 # Transaction distribution
2180system.cpu1.toL2Bus.trans_dist::HardPFReq 24473 # Transaction distribution
2181system.cpu1.toL2Bus.trans_dist::UpgradeReq 71017 # Transaction distribution
2182system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41707 # Transaction distribution
2183system.cpu1.toL2Bus.trans_dist::UpgradeResp 84949 # Transaction distribution
2184system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
2185system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
2186system.cpu1.toL2Bus.trans_dist::ReadExReq 57470 # Transaction distribution
2187system.cpu1.toL2Bus.trans_dist::ReadExResp 55019 # Transaction distribution
2188system.cpu1.toL2Bus.trans_dist::ReadCleanReq 857169 # Transaction distribution
2189system.cpu1.toL2Bus.trans_dist::ReadSharedReq 232907 # Transaction distribution
2190system.cpu1.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution
2191system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2571219 # Packet count per connected master and slave (bytes)
2192system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 743876 # Packet count per connected master and slave (bytes)
2193system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6996 # Packet count per connected master and slave (bytes)
2194system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 52037 # Packet count per connected master and slave (bytes)
2195system.cpu1.toL2Bus.pkt_count::total 3374128 # Packet count per connected master and slave (bytes)
2196system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 109692032 # Cumulative packet size per connected master and slave (bytes)
2197system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25376564 # Cumulative packet size per connected master and slave (bytes)
2198system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11932 # Cumulative packet size per connected master and slave (bytes)
2199system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 99940 # Cumulative packet size per connected master and slave (bytes)
2200system.cpu1.toL2Bus.pkt_size::total 135180468 # Cumulative packet size per connected master and slave (bytes)
2201system.cpu1.toL2Bus.snoops 380471 # Total snoops (count)
2202system.cpu1.toL2Bus.snoop_fanout::samples 1449236 # Request fanout histogram
2203system.cpu1.toL2Bus.snoop_fanout::mean 0.140738 # Request fanout histogram
2204system.cpu1.toL2Bus.snoop_fanout::stdev 0.350577 # Request fanout histogram
2205system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2206system.cpu1.toL2Bus.snoop_fanout::0 1246703 86.02% 86.02% # Request fanout histogram
2207system.cpu1.toL2Bus.snoop_fanout::1 201103 13.88% 99.90% # Request fanout histogram
2208system.cpu1.toL2Bus.snoop_fanout::2 1430 0.10% 100.00% # Request fanout histogram
2209system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2210system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2211system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2212system.cpu1.toL2Bus.snoop_fanout::total 1449236 # Request fanout histogram
2213system.cpu1.toL2Bus.reqLayer0.occupancy 2091716493 # Layer occupancy (ticks)
2214system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2215system.cpu1.toL2Bus.snoopLayer0.occupancy 78610365 # Layer occupancy (ticks)
2216system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2217system.cpu1.toL2Bus.respLayer0.occupancy 1286047248 # Layer occupancy (ticks)
2218system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2219system.cpu1.toL2Bus.respLayer1.occupancy 331216893 # Layer occupancy (ticks)
2220system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2221system.cpu1.toL2Bus.respLayer2.occupancy 4013000 # Layer occupancy (ticks)
2222system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2223system.cpu1.toL2Bus.respLayer3.occupancy 27068966 # Layer occupancy (ticks)
2224system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2225system.iobus.trans_dist::ReadReq 31009 # Transaction distribution
2226system.iobus.trans_dist::ReadResp 31009 # Transaction distribution
2227system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
2228system.iobus.trans_dist::WriteResp 59425 # Transaction distribution
2229system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes)
2230system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2231system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2232system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2233system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2234system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2235system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2236system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2237system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2238system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2239system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2240system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2241system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2242system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2243system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2244system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2245system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2246system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2247system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2248system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes)
2249system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
2250system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
2251system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes)
2252system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes)
2253system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2254system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2255system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2256system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2257system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2258system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2259system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2260system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2261system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2262system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2263system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2264system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2265system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2266system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2267system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2268system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2269system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2270system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2271system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes)
2272system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
2273system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
2274system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes)
2275system.iobus.reqLayer0.occupancy 48277500 # Layer occupancy (ticks)
2276system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2277system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks)
2278system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2279system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks)
2280system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2281system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks)
2282system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2283system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
2284system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2285system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks)
2286system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2287system.iobus.reqLayer8.occupancy 577000 # Layer occupancy (ticks)
2288system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2289system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks)
2290system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2291system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks)
2292system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2293system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2294system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2295system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2296system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2297system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
2298system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2299system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2300system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2301system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
2302system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2303system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2304system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2305system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks)
2306system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2307system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
2308system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2309system.iobus.reqLayer23.occupancy 6148000 # Layer occupancy (ticks)
2310system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2311system.iobus.reqLayer24.occupancy 33110001 # Layer occupancy (ticks)
2312system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2313system.iobus.reqLayer25.occupancy 187086234 # Layer occupancy (ticks)
2314system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2315system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks)
2316system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2317system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks)
2318system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2319system.iocache.tags.replacements 36433 # number of replacements
2320system.iocache.tags.tagsinuse 14.469289 # Cycle average of tags in use
2321system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2322system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks.
2323system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2324system.iocache.tags.warmup_cycle 272370801000 # Cycle when the warmup percentage was hit.
2325system.iocache.tags.occ_blocks::realview.ide 14.469289 # Average occupied blocks per requestor
2326system.iocache.tags.occ_percent::realview.ide 0.904331 # Average percentage of cache occupancy
2327system.iocache.tags.occ_percent::total 0.904331 # Average percentage of cache occupancy
2328system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2329system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2330system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2331system.iocache.tags.tag_accesses 328203 # Number of tag accesses
2332system.iocache.tags.data_accesses 328203 # Number of data accesses
2333system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
2334system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
2335system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2336system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses

2133system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter.
2134system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2135system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2136system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter.
2137system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2138system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2139system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution
2140system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution
2141system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution
2142system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution
2143system.cpu1.toL2Bus.trans_dist::WritebackDirty 124900 # Transaction distribution
2144system.cpu1.toL2Bus.trans_dist::WritebackClean 917333 # Transaction distribution
2145system.cpu1.toL2Bus.trans_dist::CleanEvict 97527 # Transaction distribution
2146system.cpu1.toL2Bus.trans_dist::HardPFReq 24473 # Transaction distribution
2147system.cpu1.toL2Bus.trans_dist::UpgradeReq 71017 # Transaction distribution
2148system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41707 # Transaction distribution
2149system.cpu1.toL2Bus.trans_dist::UpgradeResp 84949 # Transaction distribution
2150system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
2151system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
2152system.cpu1.toL2Bus.trans_dist::ReadExReq 57470 # Transaction distribution
2153system.cpu1.toL2Bus.trans_dist::ReadExResp 55019 # Transaction distribution
2154system.cpu1.toL2Bus.trans_dist::ReadCleanReq 857169 # Transaction distribution
2155system.cpu1.toL2Bus.trans_dist::ReadSharedReq 232907 # Transaction distribution
2156system.cpu1.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution
2157system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2571219 # Packet count per connected master and slave (bytes)
2158system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 743876 # Packet count per connected master and slave (bytes)
2159system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6996 # Packet count per connected master and slave (bytes)
2160system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 52037 # Packet count per connected master and slave (bytes)
2161system.cpu1.toL2Bus.pkt_count::total 3374128 # Packet count per connected master and slave (bytes)
2162system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 109692032 # Cumulative packet size per connected master and slave (bytes)
2163system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25376564 # Cumulative packet size per connected master and slave (bytes)
2164system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11932 # Cumulative packet size per connected master and slave (bytes)
2165system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 99940 # Cumulative packet size per connected master and slave (bytes)
2166system.cpu1.toL2Bus.pkt_size::total 135180468 # Cumulative packet size per connected master and slave (bytes)
2167system.cpu1.toL2Bus.snoops 380471 # Total snoops (count)
2168system.cpu1.toL2Bus.snoop_fanout::samples 1449236 # Request fanout histogram
2169system.cpu1.toL2Bus.snoop_fanout::mean 0.140738 # Request fanout histogram
2170system.cpu1.toL2Bus.snoop_fanout::stdev 0.350577 # Request fanout histogram
2171system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2172system.cpu1.toL2Bus.snoop_fanout::0 1246703 86.02% 86.02% # Request fanout histogram
2173system.cpu1.toL2Bus.snoop_fanout::1 201103 13.88% 99.90% # Request fanout histogram
2174system.cpu1.toL2Bus.snoop_fanout::2 1430 0.10% 100.00% # Request fanout histogram
2175system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2176system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2177system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2178system.cpu1.toL2Bus.snoop_fanout::total 1449236 # Request fanout histogram
2179system.cpu1.toL2Bus.reqLayer0.occupancy 2091716493 # Layer occupancy (ticks)
2180system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2181system.cpu1.toL2Bus.snoopLayer0.occupancy 78610365 # Layer occupancy (ticks)
2182system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2183system.cpu1.toL2Bus.respLayer0.occupancy 1286047248 # Layer occupancy (ticks)
2184system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2185system.cpu1.toL2Bus.respLayer1.occupancy 331216893 # Layer occupancy (ticks)
2186system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2187system.cpu1.toL2Bus.respLayer2.occupancy 4013000 # Layer occupancy (ticks)
2188system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2189system.cpu1.toL2Bus.respLayer3.occupancy 27068966 # Layer occupancy (ticks)
2190system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2191system.iobus.trans_dist::ReadReq 31009 # Transaction distribution
2192system.iobus.trans_dist::ReadResp 31009 # Transaction distribution
2193system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
2194system.iobus.trans_dist::WriteResp 59425 # Transaction distribution
2195system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes)
2196system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2197system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2198system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2199system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2200system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2201system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2202system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2203system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2204system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2205system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2206system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2207system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2208system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2209system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2210system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2211system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2212system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2213system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2214system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes)
2215system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
2216system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
2217system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes)
2218system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes)
2219system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2220system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2221system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2222system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2223system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2224system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2225system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2226system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2227system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2228system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2229system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2230system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2231system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2232system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2233system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2234system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2235system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2236system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2237system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes)
2238system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
2239system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
2240system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes)
2241system.iobus.reqLayer0.occupancy 48277500 # Layer occupancy (ticks)
2242system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2243system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks)
2244system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2245system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks)
2246system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2247system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks)
2248system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2249system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
2250system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2251system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks)
2252system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2253system.iobus.reqLayer8.occupancy 577000 # Layer occupancy (ticks)
2254system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2255system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks)
2256system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2257system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks)
2258system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2259system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2260system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2261system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2262system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2263system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
2264system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2265system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2266system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2267system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
2268system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2269system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2270system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2271system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks)
2272system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2273system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
2274system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2275system.iobus.reqLayer23.occupancy 6148000 # Layer occupancy (ticks)
2276system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2277system.iobus.reqLayer24.occupancy 33110001 # Layer occupancy (ticks)
2278system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2279system.iobus.reqLayer25.occupancy 187086234 # Layer occupancy (ticks)
2280system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2281system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks)
2282system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2283system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks)
2284system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2285system.iocache.tags.replacements 36433 # number of replacements
2286system.iocache.tags.tagsinuse 14.469289 # Cycle average of tags in use
2287system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2288system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks.
2289system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2290system.iocache.tags.warmup_cycle 272370801000 # Cycle when the warmup percentage was hit.
2291system.iocache.tags.occ_blocks::realview.ide 14.469289 # Average occupied blocks per requestor
2292system.iocache.tags.occ_percent::realview.ide 0.904331 # Average percentage of cache occupancy
2293system.iocache.tags.occ_percent::total 0.904331 # Average percentage of cache occupancy
2294system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2295system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2296system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2297system.iocache.tags.tag_accesses 328203 # Number of tag accesses
2298system.iocache.tags.data_accesses 328203 # Number of data accesses
2299system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
2300system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
2301system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2302system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses

2337system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
2338system.iocache.demand_misses::total 243 # number of demand (read+write) misses
2339system.iocache.overall_misses::realview.ide 243 # number of overall misses
2340system.iocache.overall_misses::total 243 # number of overall misses

2303system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses
2304system.iocache.demand_misses::total 36467 # number of demand (read+write) misses
2305system.iocache.overall_misses::realview.ide 36467 # number of overall misses
2306system.iocache.overall_misses::total 36467 # number of overall misses

2341system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles
2342system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles
2343system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles
2344system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles

2307system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles
2308system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles
2309system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles
2310system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles

2345system.iocache.demand_miss_latency::realview.ide 31660877 # number of demand (read+write) miss cycles
2346system.iocache.demand_miss_latency::total 31660877 # number of demand (read+write) miss cycles
2347system.iocache.overall_miss_latency::realview.ide 31660877 # number of overall miss cycles
2348system.iocache.overall_miss_latency::total 31660877 # number of overall miss cycles

2311system.iocache.demand_miss_latency::realview.ide 4609920234 # number of demand (read+write) miss cycles
2312system.iocache.demand_miss_latency::total 4609920234 # number of demand (read+write) miss cycles
2313system.iocache.overall_miss_latency::realview.ide 4609920234 # number of overall miss cycles
2314system.iocache.overall_miss_latency::total 4609920234 # number of overall miss cycles

2349system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
2350system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
2351system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2352system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)

2315system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
2316system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
2317system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2318system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)

2353system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
2354system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
2355system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
2356system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses

2319system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses
2320system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses
2321system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses
2322system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses

2357system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2358system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2359system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2360system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2361system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2362system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2363system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2364system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2365system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency
2366system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency
2367system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency
2368system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency

2323system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2324system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2325system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2326system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2327system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2328system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2329system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2330system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2331system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency
2332system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency
2333system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency
2334system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency

2369system.iocache.demand_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
2370system.iocache.demand_avg_miss_latency::total 130291.674897 # average overall miss latency
2371system.iocache.overall_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
2372system.iocache.overall_avg_miss_latency::total 130291.674897 # average overall miss latency

2335system.iocache.demand_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
2336system.iocache.demand_avg_miss_latency::total 126413.476129 # average overall miss latency
2337system.iocache.overall_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
2338system.iocache.overall_avg_miss_latency::total 126413.476129 # average overall miss latency

2373system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2374system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2375system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2376system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2377system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2378system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2339system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2340system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2341system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2342system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2343system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2344system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2379system.iocache.fast_writes 0 # number of fast writes performed
2380system.iocache.cache_copies 0 # number of cache copies performed

2381system.iocache.writebacks::writebacks 36190 # number of writebacks
2382system.iocache.writebacks::total 36190 # number of writebacks
2383system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
2384system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
2385system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2386system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses

2345system.iocache.writebacks::writebacks 36190 # number of writebacks
2346system.iocache.writebacks::total 36190 # number of writebacks
2347system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
2348system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
2349system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2350system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses

2387system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
2388system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
2389system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
2390system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses

2351system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses
2352system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses
2353system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses
2354system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses

2391system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles
2392system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles
2393system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles
2394system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles

2355system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles
2356system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles
2357system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles
2358system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles

2395system.iocache.demand_mshr_miss_latency::realview.ide 19510877 # number of demand (read+write) MSHR miss cycles
2396system.iocache.demand_mshr_miss_latency::total 19510877 # number of demand (read+write) MSHR miss cycles
2397system.iocache.overall_mshr_miss_latency::realview.ide 19510877 # number of overall MSHR miss cycles
2398system.iocache.overall_mshr_miss_latency::total 19510877 # number of overall MSHR miss cycles

2359system.iocache.demand_mshr_miss_latency::realview.ide 2784909291 # number of demand (read+write) MSHR miss cycles
2360system.iocache.demand_mshr_miss_latency::total 2784909291 # number of demand (read+write) MSHR miss cycles
2361system.iocache.overall_mshr_miss_latency::realview.ide 2784909291 # number of overall MSHR miss cycles
2362system.iocache.overall_mshr_miss_latency::total 2784909291 # number of overall MSHR miss cycles

2399system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2400system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2401system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2402system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2403system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2404system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2405system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2406system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2407system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897 # average ReadReq mshr miss latency
2408system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency
2409system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency
2410system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency

2363system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2364system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2365system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2366system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2367system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2368system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2369system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2370system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2371system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897 # average ReadReq mshr miss latency
2372system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency
2373system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency
2374system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency

2411system.iocache.demand_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
2412system.iocache.demand_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
2413system.iocache.overall_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
2414system.iocache.overall_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
2415system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate

2375system.iocache.demand_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
2376system.iocache.demand_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
2377system.iocache.overall_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
2378system.iocache.overall_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency

2416system.l2c.tags.replacements 132278 # number of replacements
2417system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use
2418system.l2c.tags.total_refs 475189 # Total number of references to valid blocks.
2419system.l2c.tags.sampled_refs 196356 # Sample count of references to valid blocks.
2420system.l2c.tags.avg_refs 2.420038 # Average number of references to valid blocks.
2421system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2422system.l2c.tags.occ_blocks::writebacks 13432.084830 # Average occupied blocks per requestor
2423system.l2c.tags.occ_blocks::cpu0.dtb.walker 86.256901 # Average occupied blocks per requestor
2424system.l2c.tags.occ_blocks::cpu0.itb.walker 0.025522 # Average occupied blocks per requestor
2425system.l2c.tags.occ_blocks::cpu0.inst 9264.781047 # Average occupied blocks per requestor
2426system.l2c.tags.occ_blocks::cpu0.data 2924.876995 # Average occupied blocks per requestor
2427system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33297.808041 # Average occupied blocks per requestor
2428system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.154929 # Average occupied blocks per requestor
2429system.l2c.tags.occ_blocks::cpu1.inst 1918.631510 # Average occupied blocks per requestor
2430system.l2c.tags.occ_blocks::cpu1.data 571.851499 # Average occupied blocks per requestor
2431system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1782.583876 # Average occupied blocks per requestor
2432system.l2c.tags.occ_percent::writebacks 0.204957 # Average percentage of cache occupancy
2433system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001316 # Average percentage of cache occupancy
2434system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
2435system.l2c.tags.occ_percent::cpu0.inst 0.141369 # Average percentage of cache occupancy
2436system.l2c.tags.occ_percent::cpu0.data 0.044630 # Average percentage of cache occupancy
2437system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.508084 # Average percentage of cache occupancy
2438system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000079 # Average percentage of cache occupancy
2439system.l2c.tags.occ_percent::cpu1.inst 0.029276 # Average percentage of cache occupancy
2440system.l2c.tags.occ_percent::cpu1.data 0.008726 # Average percentage of cache occupancy
2441system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027200 # Average percentage of cache occupancy
2442system.l2c.tags.occ_percent::total 0.965638 # Average percentage of cache occupancy
2443system.l2c.tags.occ_task_id_blocks::1022 29131 # Occupied blocks per task id
2444system.l2c.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id
2445system.l2c.tags.occ_task_id_blocks::1024 34885 # Occupied blocks per task id
2446system.l2c.tags.age_task_id_blocks_1022::2 127 # Occupied blocks per task id
2447system.l2c.tags.age_task_id_blocks_1022::3 5182 # Occupied blocks per task id
2448system.l2c.tags.age_task_id_blocks_1022::4 23822 # Occupied blocks per task id
2449system.l2c.tags.age_task_id_blocks_1023::4 62 # Occupied blocks per task id
2450system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
2451system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
2452system.l2c.tags.age_task_id_blocks_1024::2 413 # Occupied blocks per task id
2453system.l2c.tags.age_task_id_blocks_1024::3 3378 # Occupied blocks per task id
2454system.l2c.tags.age_task_id_blocks_1024::4 31070 # Occupied blocks per task id
2455system.l2c.tags.occ_task_id_percent::1022 0.444504 # Percentage of cache occupancy per task id
2456system.l2c.tags.occ_task_id_percent::1023 0.000946 # Percentage of cache occupancy per task id
2457system.l2c.tags.occ_task_id_percent::1024 0.532303 # Percentage of cache occupancy per task id
2458system.l2c.tags.tag_accesses 6384287 # Number of tag accesses
2459system.l2c.tags.data_accesses 6384287 # Number of data accesses
2460system.l2c.WritebackDirty_hits::writebacks 266285 # number of WritebackDirty hits
2461system.l2c.WritebackDirty_hits::total 266285 # number of WritebackDirty hits
2462system.l2c.UpgradeReq_hits::cpu0.data 34059 # number of UpgradeReq hits
2463system.l2c.UpgradeReq_hits::cpu1.data 2216 # number of UpgradeReq hits
2464system.l2c.UpgradeReq_hits::total 36275 # number of UpgradeReq hits
2465system.l2c.SCUpgradeReq_hits::cpu0.data 2214 # number of SCUpgradeReq hits
2466system.l2c.SCUpgradeReq_hits::cpu1.data 916 # number of SCUpgradeReq hits
2467system.l2c.SCUpgradeReq_hits::total 3130 # number of SCUpgradeReq hits
2468system.l2c.ReadExReq_hits::cpu0.data 4440 # number of ReadExReq hits
2469system.l2c.ReadExReq_hits::cpu1.data 1284 # number of ReadExReq hits
2470system.l2c.ReadExReq_hits::total 5724 # number of ReadExReq hits
2471system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 468 # number of ReadSharedReq hits
2472system.l2c.ReadSharedReq_hits::cpu0.itb.walker 93 # number of ReadSharedReq hits
2473system.l2c.ReadSharedReq_hits::cpu0.inst 47246 # number of ReadSharedReq hits
2474system.l2c.ReadSharedReq_hits::cpu0.data 51272 # number of ReadSharedReq hits
2475system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 49179 # number of ReadSharedReq hits
2476system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 71 # number of ReadSharedReq hits
2477system.l2c.ReadSharedReq_hits::cpu1.itb.walker 15 # number of ReadSharedReq hits
2478system.l2c.ReadSharedReq_hits::cpu1.inst 9697 # number of ReadSharedReq hits
2479system.l2c.ReadSharedReq_hits::cpu1.data 5512 # number of ReadSharedReq hits
2480system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3623 # number of ReadSharedReq hits
2481system.l2c.ReadSharedReq_hits::total 167176 # number of ReadSharedReq hits
2482system.l2c.demand_hits::cpu0.dtb.walker 468 # number of demand (read+write) hits
2483system.l2c.demand_hits::cpu0.itb.walker 93 # number of demand (read+write) hits
2484system.l2c.demand_hits::cpu0.inst 47246 # number of demand (read+write) hits
2485system.l2c.demand_hits::cpu0.data 55712 # number of demand (read+write) hits
2486system.l2c.demand_hits::cpu0.l2cache.prefetcher 49179 # number of demand (read+write) hits
2487system.l2c.demand_hits::cpu1.dtb.walker 71 # number of demand (read+write) hits
2488system.l2c.demand_hits::cpu1.itb.walker 15 # number of demand (read+write) hits
2489system.l2c.demand_hits::cpu1.inst 9697 # number of demand (read+write) hits
2490system.l2c.demand_hits::cpu1.data 6796 # number of demand (read+write) hits
2491system.l2c.demand_hits::cpu1.l2cache.prefetcher 3623 # number of demand (read+write) hits
2492system.l2c.demand_hits::total 172900 # number of demand (read+write) hits
2493system.l2c.overall_hits::cpu0.dtb.walker 468 # number of overall hits
2494system.l2c.overall_hits::cpu0.itb.walker 93 # number of overall hits
2495system.l2c.overall_hits::cpu0.inst 47246 # number of overall hits
2496system.l2c.overall_hits::cpu0.data 55712 # number of overall hits
2497system.l2c.overall_hits::cpu0.l2cache.prefetcher 49179 # number of overall hits
2498system.l2c.overall_hits::cpu1.dtb.walker 71 # number of overall hits
2499system.l2c.overall_hits::cpu1.itb.walker 15 # number of overall hits
2500system.l2c.overall_hits::cpu1.inst 9697 # number of overall hits
2501system.l2c.overall_hits::cpu1.data 6796 # number of overall hits
2502system.l2c.overall_hits::cpu1.l2cache.prefetcher 3623 # number of overall hits
2503system.l2c.overall_hits::total 172900 # number of overall hits
2504system.l2c.UpgradeReq_misses::cpu0.data 9961 # number of UpgradeReq misses
2505system.l2c.UpgradeReq_misses::cpu1.data 2371 # number of UpgradeReq misses
2506system.l2c.UpgradeReq_misses::total 12332 # number of UpgradeReq misses
2507system.l2c.SCUpgradeReq_misses::cpu0.data 734 # number of SCUpgradeReq misses
2508system.l2c.SCUpgradeReq_misses::cpu1.data 1296 # number of SCUpgradeReq misses
2509system.l2c.SCUpgradeReq_misses::total 2030 # number of SCUpgradeReq misses
2510system.l2c.ReadExReq_misses::cpu0.data 11316 # number of ReadExReq misses
2511system.l2c.ReadExReq_misses::cpu1.data 8107 # number of ReadExReq misses
2512system.l2c.ReadExReq_misses::total 19423 # number of ReadExReq misses
2513system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 140 # number of ReadSharedReq misses
2514system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses
2515system.l2c.ReadSharedReq_misses::cpu0.inst 22687 # number of ReadSharedReq misses
2516system.l2c.ReadSharedReq_misses::cpu0.data 9939 # number of ReadSharedReq misses
2517system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134210 # number of ReadSharedReq misses
2518system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 11 # number of ReadSharedReq misses
2519system.l2c.ReadSharedReq_misses::cpu1.inst 3160 # number of ReadSharedReq misses
2520system.l2c.ReadSharedReq_misses::cpu1.data 1668 # number of ReadSharedReq misses
2521system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5252 # number of ReadSharedReq misses
2522system.l2c.ReadSharedReq_misses::total 177068 # number of ReadSharedReq misses
2523system.l2c.demand_misses::cpu0.dtb.walker 140 # number of demand (read+write) misses
2524system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
2525system.l2c.demand_misses::cpu0.inst 22687 # number of demand (read+write) misses
2526system.l2c.demand_misses::cpu0.data 21255 # number of demand (read+write) misses
2527system.l2c.demand_misses::cpu0.l2cache.prefetcher 134210 # number of demand (read+write) misses
2528system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
2529system.l2c.demand_misses::cpu1.inst 3160 # number of demand (read+write) misses
2530system.l2c.demand_misses::cpu1.data 9775 # number of demand (read+write) misses
2531system.l2c.demand_misses::cpu1.l2cache.prefetcher 5252 # number of demand (read+write) misses
2532system.l2c.demand_misses::total 196491 # number of demand (read+write) misses
2533system.l2c.overall_misses::cpu0.dtb.walker 140 # number of overall misses
2534system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
2535system.l2c.overall_misses::cpu0.inst 22687 # number of overall misses
2536system.l2c.overall_misses::cpu0.data 21255 # number of overall misses
2537system.l2c.overall_misses::cpu0.l2cache.prefetcher 134210 # number of overall misses
2538system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses
2539system.l2c.overall_misses::cpu1.inst 3160 # number of overall misses
2540system.l2c.overall_misses::cpu1.data 9775 # number of overall misses
2541system.l2c.overall_misses::cpu1.l2cache.prefetcher 5252 # number of overall misses
2542system.l2c.overall_misses::total 196491 # number of overall misses
2543system.l2c.UpgradeReq_miss_latency::cpu0.data 28980000 # number of UpgradeReq miss cycles
2544system.l2c.UpgradeReq_miss_latency::cpu1.data 5338000 # number of UpgradeReq miss cycles
2545system.l2c.UpgradeReq_miss_latency::total 34318000 # number of UpgradeReq miss cycles
2546system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4765000 # number of SCUpgradeReq miss cycles
2547system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2590000 # number of SCUpgradeReq miss cycles
2548system.l2c.SCUpgradeReq_miss_latency::total 7355000 # number of SCUpgradeReq miss cycles
2549system.l2c.ReadExReq_miss_latency::cpu0.data 1685307000 # number of ReadExReq miss cycles
2550system.l2c.ReadExReq_miss_latency::cpu1.data 1070056000 # number of ReadExReq miss cycles
2551system.l2c.ReadExReq_miss_latency::total 2755363000 # number of ReadExReq miss cycles
2552system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 20017500 # number of ReadSharedReq miss cycles
2553system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 133000 # number of ReadSharedReq miss cycles
2554system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2974322500 # number of ReadSharedReq miss cycles
2555system.l2c.ReadSharedReq_miss_latency::cpu0.data 1361155500 # number of ReadSharedReq miss cycles
2556system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20176294779 # number of ReadSharedReq miss cycles
2557system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1494500 # number of ReadSharedReq miss cycles
2558system.l2c.ReadSharedReq_miss_latency::cpu1.inst 420880000 # number of ReadSharedReq miss cycles
2559system.l2c.ReadSharedReq_miss_latency::cpu1.data 230733500 # number of ReadSharedReq miss cycles
2560system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 884118696 # number of ReadSharedReq miss cycles
2561system.l2c.ReadSharedReq_miss_latency::total 26069149975 # number of ReadSharedReq miss cycles
2562system.l2c.demand_miss_latency::cpu0.dtb.walker 20017500 # number of demand (read+write) miss cycles
2563system.l2c.demand_miss_latency::cpu0.itb.walker 133000 # number of demand (read+write) miss cycles
2564system.l2c.demand_miss_latency::cpu0.inst 2974322500 # number of demand (read+write) miss cycles
2565system.l2c.demand_miss_latency::cpu0.data 3046462500 # number of demand (read+write) miss cycles
2566system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20176294779 # number of demand (read+write) miss cycles
2567system.l2c.demand_miss_latency::cpu1.dtb.walker 1494500 # number of demand (read+write) miss cycles
2568system.l2c.demand_miss_latency::cpu1.inst 420880000 # number of demand (read+write) miss cycles
2569system.l2c.demand_miss_latency::cpu1.data 1300789500 # number of demand (read+write) miss cycles
2570system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 884118696 # number of demand (read+write) miss cycles
2571system.l2c.demand_miss_latency::total 28824512975 # number of demand (read+write) miss cycles
2572system.l2c.overall_miss_latency::cpu0.dtb.walker 20017500 # number of overall miss cycles
2573system.l2c.overall_miss_latency::cpu0.itb.walker 133000 # number of overall miss cycles
2574system.l2c.overall_miss_latency::cpu0.inst 2974322500 # number of overall miss cycles
2575system.l2c.overall_miss_latency::cpu0.data 3046462500 # number of overall miss cycles
2576system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20176294779 # number of overall miss cycles
2577system.l2c.overall_miss_latency::cpu1.dtb.walker 1494500 # number of overall miss cycles
2578system.l2c.overall_miss_latency::cpu1.inst 420880000 # number of overall miss cycles
2579system.l2c.overall_miss_latency::cpu1.data 1300789500 # number of overall miss cycles
2580system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 884118696 # number of overall miss cycles
2581system.l2c.overall_miss_latency::total 28824512975 # number of overall miss cycles
2582system.l2c.WritebackDirty_accesses::writebacks 266285 # number of WritebackDirty accesses(hits+misses)
2583system.l2c.WritebackDirty_accesses::total 266285 # number of WritebackDirty accesses(hits+misses)
2584system.l2c.UpgradeReq_accesses::cpu0.data 44020 # number of UpgradeReq accesses(hits+misses)
2585system.l2c.UpgradeReq_accesses::cpu1.data 4587 # number of UpgradeReq accesses(hits+misses)
2586system.l2c.UpgradeReq_accesses::total 48607 # number of UpgradeReq accesses(hits+misses)
2587system.l2c.SCUpgradeReq_accesses::cpu0.data 2948 # number of SCUpgradeReq accesses(hits+misses)
2588system.l2c.SCUpgradeReq_accesses::cpu1.data 2212 # number of SCUpgradeReq accesses(hits+misses)
2589system.l2c.SCUpgradeReq_accesses::total 5160 # number of SCUpgradeReq accesses(hits+misses)
2590system.l2c.ReadExReq_accesses::cpu0.data 15756 # number of ReadExReq accesses(hits+misses)
2591system.l2c.ReadExReq_accesses::cpu1.data 9391 # number of ReadExReq accesses(hits+misses)
2592system.l2c.ReadExReq_accesses::total 25147 # number of ReadExReq accesses(hits+misses)
2593system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 608 # number of ReadSharedReq accesses(hits+misses)
2594system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 94 # number of ReadSharedReq accesses(hits+misses)
2595system.l2c.ReadSharedReq_accesses::cpu0.inst 69933 # number of ReadSharedReq accesses(hits+misses)
2596system.l2c.ReadSharedReq_accesses::cpu0.data 61211 # number of ReadSharedReq accesses(hits+misses)
2597system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183389 # number of ReadSharedReq accesses(hits+misses)
2598system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 82 # number of ReadSharedReq accesses(hits+misses)
2599system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 15 # number of ReadSharedReq accesses(hits+misses)
2600system.l2c.ReadSharedReq_accesses::cpu1.inst 12857 # number of ReadSharedReq accesses(hits+misses)
2601system.l2c.ReadSharedReq_accesses::cpu1.data 7180 # number of ReadSharedReq accesses(hits+misses)
2602system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8875 # number of ReadSharedReq accesses(hits+misses)
2603system.l2c.ReadSharedReq_accesses::total 344244 # number of ReadSharedReq accesses(hits+misses)
2604system.l2c.demand_accesses::cpu0.dtb.walker 608 # number of demand (read+write) accesses
2605system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses
2606system.l2c.demand_accesses::cpu0.inst 69933 # number of demand (read+write) accesses
2607system.l2c.demand_accesses::cpu0.data 76967 # number of demand (read+write) accesses
2608system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183389 # number of demand (read+write) accesses
2609system.l2c.demand_accesses::cpu1.dtb.walker 82 # number of demand (read+write) accesses
2610system.l2c.demand_accesses::cpu1.itb.walker 15 # number of demand (read+write) accesses
2611system.l2c.demand_accesses::cpu1.inst 12857 # number of demand (read+write) accesses
2612system.l2c.demand_accesses::cpu1.data 16571 # number of demand (read+write) accesses
2613system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8875 # number of demand (read+write) accesses
2614system.l2c.demand_accesses::total 369391 # number of demand (read+write) accesses
2615system.l2c.overall_accesses::cpu0.dtb.walker 608 # number of overall (read+write) accesses
2616system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses
2617system.l2c.overall_accesses::cpu0.inst 69933 # number of overall (read+write) accesses
2618system.l2c.overall_accesses::cpu0.data 76967 # number of overall (read+write) accesses
2619system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183389 # number of overall (read+write) accesses
2620system.l2c.overall_accesses::cpu1.dtb.walker 82 # number of overall (read+write) accesses
2621system.l2c.overall_accesses::cpu1.itb.walker 15 # number of overall (read+write) accesses
2622system.l2c.overall_accesses::cpu1.inst 12857 # number of overall (read+write) accesses
2623system.l2c.overall_accesses::cpu1.data 16571 # number of overall (read+write) accesses
2624system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8875 # number of overall (read+write) accesses
2625system.l2c.overall_accesses::total 369391 # number of overall (read+write) accesses
2626system.l2c.UpgradeReq_miss_rate::cpu0.data 0.226284 # miss rate for UpgradeReq accesses
2627system.l2c.UpgradeReq_miss_rate::cpu1.data 0.516896 # miss rate for UpgradeReq accesses
2628system.l2c.UpgradeReq_miss_rate::total 0.253708 # miss rate for UpgradeReq accesses
2629system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.248982 # miss rate for SCUpgradeReq accesses
2630system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.585895 # miss rate for SCUpgradeReq accesses
2631system.l2c.SCUpgradeReq_miss_rate::total 0.393411 # miss rate for SCUpgradeReq accesses
2632system.l2c.ReadExReq_miss_rate::cpu0.data 0.718203 # miss rate for ReadExReq accesses
2633system.l2c.ReadExReq_miss_rate::cpu1.data 0.863273 # miss rate for ReadExReq accesses
2634system.l2c.ReadExReq_miss_rate::total 0.772378 # miss rate for ReadExReq accesses
2635system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.230263 # miss rate for ReadSharedReq accesses
2636system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.010638 # miss rate for ReadSharedReq accesses
2637system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.324411 # miss rate for ReadSharedReq accesses
2638system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162373 # miss rate for ReadSharedReq accesses
2639system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.731832 # miss rate for ReadSharedReq accesses
2640system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.134146 # miss rate for ReadSharedReq accesses
2641system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.245781 # miss rate for ReadSharedReq accesses
2642system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.232312 # miss rate for ReadSharedReq accesses
2643system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.591775 # miss rate for ReadSharedReq accesses
2644system.l2c.ReadSharedReq_miss_rate::total 0.514368 # miss rate for ReadSharedReq accesses
2645system.l2c.demand_miss_rate::cpu0.dtb.walker 0.230263 # miss rate for demand accesses
2646system.l2c.demand_miss_rate::cpu0.itb.walker 0.010638 # miss rate for demand accesses
2647system.l2c.demand_miss_rate::cpu0.inst 0.324411 # miss rate for demand accesses
2648system.l2c.demand_miss_rate::cpu0.data 0.276157 # miss rate for demand accesses
2649system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.731832 # miss rate for demand accesses
2650system.l2c.demand_miss_rate::cpu1.dtb.walker 0.134146 # miss rate for demand accesses
2651system.l2c.demand_miss_rate::cpu1.inst 0.245781 # miss rate for demand accesses
2652system.l2c.demand_miss_rate::cpu1.data 0.589886 # miss rate for demand accesses
2653system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.591775 # miss rate for demand accesses
2654system.l2c.demand_miss_rate::total 0.531932 # miss rate for demand accesses
2655system.l2c.overall_miss_rate::cpu0.dtb.walker 0.230263 # miss rate for overall accesses
2656system.l2c.overall_miss_rate::cpu0.itb.walker 0.010638 # miss rate for overall accesses
2657system.l2c.overall_miss_rate::cpu0.inst 0.324411 # miss rate for overall accesses
2658system.l2c.overall_miss_rate::cpu0.data 0.276157 # miss rate for overall accesses
2659system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.731832 # miss rate for overall accesses
2660system.l2c.overall_miss_rate::cpu1.dtb.walker 0.134146 # miss rate for overall accesses
2661system.l2c.overall_miss_rate::cpu1.inst 0.245781 # miss rate for overall accesses
2662system.l2c.overall_miss_rate::cpu1.data 0.589886 # miss rate for overall accesses
2663system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.591775 # miss rate for overall accesses
2664system.l2c.overall_miss_rate::total 0.531932 # miss rate for overall accesses
2665system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2909.346451 # average UpgradeReq miss latency
2666system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2251.370730 # average UpgradeReq miss latency
2667system.l2c.UpgradeReq_avg_miss_latency::total 2782.841388 # average UpgradeReq miss latency
2668system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6491.825613 # average SCUpgradeReq miss latency
2669system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1998.456790 # average SCUpgradeReq miss latency
2670system.l2c.SCUpgradeReq_avg_miss_latency::total 3623.152709 # average SCUpgradeReq miss latency
2671system.l2c.ReadExReq_avg_miss_latency::cpu0.data 148931.336161 # average ReadExReq miss latency
2672system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131991.612187 # average ReadExReq miss latency
2673system.l2c.ReadExReq_avg_miss_latency::total 141860.835092 # average ReadExReq miss latency
2674system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142982.142857 # average ReadSharedReq miss latency
2675system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 133000 # average ReadSharedReq miss latency
2676system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131102.503636 # average ReadSharedReq miss latency
2677system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136950.950800 # average ReadSharedReq miss latency
2678system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 150333.766329 # average ReadSharedReq miss latency
2679system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 135863.636364 # average ReadSharedReq miss latency
2680system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133189.873418 # average ReadSharedReq miss latency
2681system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138329.436451 # average ReadSharedReq miss latency
2682system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average ReadSharedReq miss latency
2683system.l2c.ReadSharedReq_avg_miss_latency::total 147226.771495 # average ReadSharedReq miss latency
2684system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142982.142857 # average overall miss latency
2685system.l2c.demand_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency
2686system.l2c.demand_avg_miss_latency::cpu0.inst 131102.503636 # average overall miss latency
2687system.l2c.demand_avg_miss_latency::cpu0.data 143329.216655 # average overall miss latency
2688system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150333.766329 # average overall miss latency
2689system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 135863.636364 # average overall miss latency
2690system.l2c.demand_avg_miss_latency::cpu1.inst 133189.873418 # average overall miss latency
2691system.l2c.demand_avg_miss_latency::cpu1.data 133073.094629 # average overall miss latency
2692system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average overall miss latency
2693system.l2c.demand_avg_miss_latency::total 146696.352377 # average overall miss latency
2694system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142982.142857 # average overall miss latency
2695system.l2c.overall_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency
2696system.l2c.overall_avg_miss_latency::cpu0.inst 131102.503636 # average overall miss latency
2697system.l2c.overall_avg_miss_latency::cpu0.data 143329.216655 # average overall miss latency
2698system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150333.766329 # average overall miss latency
2699system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135863.636364 # average overall miss latency
2700system.l2c.overall_avg_miss_latency::cpu1.inst 133189.873418 # average overall miss latency
2701system.l2c.overall_avg_miss_latency::cpu1.data 133073.094629 # average overall miss latency
2702system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average overall miss latency
2703system.l2c.overall_avg_miss_latency::total 146696.352377 # average overall miss latency
2704system.l2c.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
2705system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2706system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2707system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2708system.l2c.avg_blocked_cycles::no_mshrs 45 # average number of cycles each access was blocked
2709system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2379system.l2c.tags.replacements 132278 # number of replacements
2380system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use
2381system.l2c.tags.total_refs 475189 # Total number of references to valid blocks.
2382system.l2c.tags.sampled_refs 196356 # Sample count of references to valid blocks.
2383system.l2c.tags.avg_refs 2.420038 # Average number of references to valid blocks.
2384system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2385system.l2c.tags.occ_blocks::writebacks 13432.084830 # Average occupied blocks per requestor
2386system.l2c.tags.occ_blocks::cpu0.dtb.walker 86.256901 # Average occupied blocks per requestor
2387system.l2c.tags.occ_blocks::cpu0.itb.walker 0.025522 # Average occupied blocks per requestor
2388system.l2c.tags.occ_blocks::cpu0.inst 9264.781047 # Average occupied blocks per requestor
2389system.l2c.tags.occ_blocks::cpu0.data 2924.876995 # Average occupied blocks per requestor
2390system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33297.808041 # Average occupied blocks per requestor
2391system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.154929 # Average occupied blocks per requestor
2392system.l2c.tags.occ_blocks::cpu1.inst 1918.631510 # Average occupied blocks per requestor
2393system.l2c.tags.occ_blocks::cpu1.data 571.851499 # Average occupied blocks per requestor
2394system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1782.583876 # Average occupied blocks per requestor
2395system.l2c.tags.occ_percent::writebacks 0.204957 # Average percentage of cache occupancy
2396system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001316 # Average percentage of cache occupancy
2397system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
2398system.l2c.tags.occ_percent::cpu0.inst 0.141369 # Average percentage of cache occupancy
2399system.l2c.tags.occ_percent::cpu0.data 0.044630 # Average percentage of cache occupancy
2400system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.508084 # Average percentage of cache occupancy
2401system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000079 # Average percentage of cache occupancy
2402system.l2c.tags.occ_percent::cpu1.inst 0.029276 # Average percentage of cache occupancy
2403system.l2c.tags.occ_percent::cpu1.data 0.008726 # Average percentage of cache occupancy
2404system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027200 # Average percentage of cache occupancy
2405system.l2c.tags.occ_percent::total 0.965638 # Average percentage of cache occupancy
2406system.l2c.tags.occ_task_id_blocks::1022 29131 # Occupied blocks per task id
2407system.l2c.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id
2408system.l2c.tags.occ_task_id_blocks::1024 34885 # Occupied blocks per task id
2409system.l2c.tags.age_task_id_blocks_1022::2 127 # Occupied blocks per task id
2410system.l2c.tags.age_task_id_blocks_1022::3 5182 # Occupied blocks per task id
2411system.l2c.tags.age_task_id_blocks_1022::4 23822 # Occupied blocks per task id
2412system.l2c.tags.age_task_id_blocks_1023::4 62 # Occupied blocks per task id
2413system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
2414system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
2415system.l2c.tags.age_task_id_blocks_1024::2 413 # Occupied blocks per task id
2416system.l2c.tags.age_task_id_blocks_1024::3 3378 # Occupied blocks per task id
2417system.l2c.tags.age_task_id_blocks_1024::4 31070 # Occupied blocks per task id
2418system.l2c.tags.occ_task_id_percent::1022 0.444504 # Percentage of cache occupancy per task id
2419system.l2c.tags.occ_task_id_percent::1023 0.000946 # Percentage of cache occupancy per task id
2420system.l2c.tags.occ_task_id_percent::1024 0.532303 # Percentage of cache occupancy per task id
2421system.l2c.tags.tag_accesses 6384287 # Number of tag accesses
2422system.l2c.tags.data_accesses 6384287 # Number of data accesses
2423system.l2c.WritebackDirty_hits::writebacks 266285 # number of WritebackDirty hits
2424system.l2c.WritebackDirty_hits::total 266285 # number of WritebackDirty hits
2425system.l2c.UpgradeReq_hits::cpu0.data 34059 # number of UpgradeReq hits
2426system.l2c.UpgradeReq_hits::cpu1.data 2216 # number of UpgradeReq hits
2427system.l2c.UpgradeReq_hits::total 36275 # number of UpgradeReq hits
2428system.l2c.SCUpgradeReq_hits::cpu0.data 2214 # number of SCUpgradeReq hits
2429system.l2c.SCUpgradeReq_hits::cpu1.data 916 # number of SCUpgradeReq hits
2430system.l2c.SCUpgradeReq_hits::total 3130 # number of SCUpgradeReq hits
2431system.l2c.ReadExReq_hits::cpu0.data 4440 # number of ReadExReq hits
2432system.l2c.ReadExReq_hits::cpu1.data 1284 # number of ReadExReq hits
2433system.l2c.ReadExReq_hits::total 5724 # number of ReadExReq hits
2434system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 468 # number of ReadSharedReq hits
2435system.l2c.ReadSharedReq_hits::cpu0.itb.walker 93 # number of ReadSharedReq hits
2436system.l2c.ReadSharedReq_hits::cpu0.inst 47246 # number of ReadSharedReq hits
2437system.l2c.ReadSharedReq_hits::cpu0.data 51272 # number of ReadSharedReq hits
2438system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 49179 # number of ReadSharedReq hits
2439system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 71 # number of ReadSharedReq hits
2440system.l2c.ReadSharedReq_hits::cpu1.itb.walker 15 # number of ReadSharedReq hits
2441system.l2c.ReadSharedReq_hits::cpu1.inst 9697 # number of ReadSharedReq hits
2442system.l2c.ReadSharedReq_hits::cpu1.data 5512 # number of ReadSharedReq hits
2443system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3623 # number of ReadSharedReq hits
2444system.l2c.ReadSharedReq_hits::total 167176 # number of ReadSharedReq hits
2445system.l2c.demand_hits::cpu0.dtb.walker 468 # number of demand (read+write) hits
2446system.l2c.demand_hits::cpu0.itb.walker 93 # number of demand (read+write) hits
2447system.l2c.demand_hits::cpu0.inst 47246 # number of demand (read+write) hits
2448system.l2c.demand_hits::cpu0.data 55712 # number of demand (read+write) hits
2449system.l2c.demand_hits::cpu0.l2cache.prefetcher 49179 # number of demand (read+write) hits
2450system.l2c.demand_hits::cpu1.dtb.walker 71 # number of demand (read+write) hits
2451system.l2c.demand_hits::cpu1.itb.walker 15 # number of demand (read+write) hits
2452system.l2c.demand_hits::cpu1.inst 9697 # number of demand (read+write) hits
2453system.l2c.demand_hits::cpu1.data 6796 # number of demand (read+write) hits
2454system.l2c.demand_hits::cpu1.l2cache.prefetcher 3623 # number of demand (read+write) hits
2455system.l2c.demand_hits::total 172900 # number of demand (read+write) hits
2456system.l2c.overall_hits::cpu0.dtb.walker 468 # number of overall hits
2457system.l2c.overall_hits::cpu0.itb.walker 93 # number of overall hits
2458system.l2c.overall_hits::cpu0.inst 47246 # number of overall hits
2459system.l2c.overall_hits::cpu0.data 55712 # number of overall hits
2460system.l2c.overall_hits::cpu0.l2cache.prefetcher 49179 # number of overall hits
2461system.l2c.overall_hits::cpu1.dtb.walker 71 # number of overall hits
2462system.l2c.overall_hits::cpu1.itb.walker 15 # number of overall hits
2463system.l2c.overall_hits::cpu1.inst 9697 # number of overall hits
2464system.l2c.overall_hits::cpu1.data 6796 # number of overall hits
2465system.l2c.overall_hits::cpu1.l2cache.prefetcher 3623 # number of overall hits
2466system.l2c.overall_hits::total 172900 # number of overall hits
2467system.l2c.UpgradeReq_misses::cpu0.data 9961 # number of UpgradeReq misses
2468system.l2c.UpgradeReq_misses::cpu1.data 2371 # number of UpgradeReq misses
2469system.l2c.UpgradeReq_misses::total 12332 # number of UpgradeReq misses
2470system.l2c.SCUpgradeReq_misses::cpu0.data 734 # number of SCUpgradeReq misses
2471system.l2c.SCUpgradeReq_misses::cpu1.data 1296 # number of SCUpgradeReq misses
2472system.l2c.SCUpgradeReq_misses::total 2030 # number of SCUpgradeReq misses
2473system.l2c.ReadExReq_misses::cpu0.data 11316 # number of ReadExReq misses
2474system.l2c.ReadExReq_misses::cpu1.data 8107 # number of ReadExReq misses
2475system.l2c.ReadExReq_misses::total 19423 # number of ReadExReq misses
2476system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 140 # number of ReadSharedReq misses
2477system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses
2478system.l2c.ReadSharedReq_misses::cpu0.inst 22687 # number of ReadSharedReq misses
2479system.l2c.ReadSharedReq_misses::cpu0.data 9939 # number of ReadSharedReq misses
2480system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134210 # number of ReadSharedReq misses
2481system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 11 # number of ReadSharedReq misses
2482system.l2c.ReadSharedReq_misses::cpu1.inst 3160 # number of ReadSharedReq misses
2483system.l2c.ReadSharedReq_misses::cpu1.data 1668 # number of ReadSharedReq misses
2484system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5252 # number of ReadSharedReq misses
2485system.l2c.ReadSharedReq_misses::total 177068 # number of ReadSharedReq misses
2486system.l2c.demand_misses::cpu0.dtb.walker 140 # number of demand (read+write) misses
2487system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
2488system.l2c.demand_misses::cpu0.inst 22687 # number of demand (read+write) misses
2489system.l2c.demand_misses::cpu0.data 21255 # number of demand (read+write) misses
2490system.l2c.demand_misses::cpu0.l2cache.prefetcher 134210 # number of demand (read+write) misses
2491system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
2492system.l2c.demand_misses::cpu1.inst 3160 # number of demand (read+write) misses
2493system.l2c.demand_misses::cpu1.data 9775 # number of demand (read+write) misses
2494system.l2c.demand_misses::cpu1.l2cache.prefetcher 5252 # number of demand (read+write) misses
2495system.l2c.demand_misses::total 196491 # number of demand (read+write) misses
2496system.l2c.overall_misses::cpu0.dtb.walker 140 # number of overall misses
2497system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
2498system.l2c.overall_misses::cpu0.inst 22687 # number of overall misses
2499system.l2c.overall_misses::cpu0.data 21255 # number of overall misses
2500system.l2c.overall_misses::cpu0.l2cache.prefetcher 134210 # number of overall misses
2501system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses
2502system.l2c.overall_misses::cpu1.inst 3160 # number of overall misses
2503system.l2c.overall_misses::cpu1.data 9775 # number of overall misses
2504system.l2c.overall_misses::cpu1.l2cache.prefetcher 5252 # number of overall misses
2505system.l2c.overall_misses::total 196491 # number of overall misses
2506system.l2c.UpgradeReq_miss_latency::cpu0.data 28980000 # number of UpgradeReq miss cycles
2507system.l2c.UpgradeReq_miss_latency::cpu1.data 5338000 # number of UpgradeReq miss cycles
2508system.l2c.UpgradeReq_miss_latency::total 34318000 # number of UpgradeReq miss cycles
2509system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4765000 # number of SCUpgradeReq miss cycles
2510system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2590000 # number of SCUpgradeReq miss cycles
2511system.l2c.SCUpgradeReq_miss_latency::total 7355000 # number of SCUpgradeReq miss cycles
2512system.l2c.ReadExReq_miss_latency::cpu0.data 1685307000 # number of ReadExReq miss cycles
2513system.l2c.ReadExReq_miss_latency::cpu1.data 1070056000 # number of ReadExReq miss cycles
2514system.l2c.ReadExReq_miss_latency::total 2755363000 # number of ReadExReq miss cycles
2515system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 20017500 # number of ReadSharedReq miss cycles
2516system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 133000 # number of ReadSharedReq miss cycles
2517system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2974322500 # number of ReadSharedReq miss cycles
2518system.l2c.ReadSharedReq_miss_latency::cpu0.data 1361155500 # number of ReadSharedReq miss cycles
2519system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 20176294779 # number of ReadSharedReq miss cycles
2520system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1494500 # number of ReadSharedReq miss cycles
2521system.l2c.ReadSharedReq_miss_latency::cpu1.inst 420880000 # number of ReadSharedReq miss cycles
2522system.l2c.ReadSharedReq_miss_latency::cpu1.data 230733500 # number of ReadSharedReq miss cycles
2523system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 884118696 # number of ReadSharedReq miss cycles
2524system.l2c.ReadSharedReq_miss_latency::total 26069149975 # number of ReadSharedReq miss cycles
2525system.l2c.demand_miss_latency::cpu0.dtb.walker 20017500 # number of demand (read+write) miss cycles
2526system.l2c.demand_miss_latency::cpu0.itb.walker 133000 # number of demand (read+write) miss cycles
2527system.l2c.demand_miss_latency::cpu0.inst 2974322500 # number of demand (read+write) miss cycles
2528system.l2c.demand_miss_latency::cpu0.data 3046462500 # number of demand (read+write) miss cycles
2529system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 20176294779 # number of demand (read+write) miss cycles
2530system.l2c.demand_miss_latency::cpu1.dtb.walker 1494500 # number of demand (read+write) miss cycles
2531system.l2c.demand_miss_latency::cpu1.inst 420880000 # number of demand (read+write) miss cycles
2532system.l2c.demand_miss_latency::cpu1.data 1300789500 # number of demand (read+write) miss cycles
2533system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 884118696 # number of demand (read+write) miss cycles
2534system.l2c.demand_miss_latency::total 28824512975 # number of demand (read+write) miss cycles
2535system.l2c.overall_miss_latency::cpu0.dtb.walker 20017500 # number of overall miss cycles
2536system.l2c.overall_miss_latency::cpu0.itb.walker 133000 # number of overall miss cycles
2537system.l2c.overall_miss_latency::cpu0.inst 2974322500 # number of overall miss cycles
2538system.l2c.overall_miss_latency::cpu0.data 3046462500 # number of overall miss cycles
2539system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 20176294779 # number of overall miss cycles
2540system.l2c.overall_miss_latency::cpu1.dtb.walker 1494500 # number of overall miss cycles
2541system.l2c.overall_miss_latency::cpu1.inst 420880000 # number of overall miss cycles
2542system.l2c.overall_miss_latency::cpu1.data 1300789500 # number of overall miss cycles
2543system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 884118696 # number of overall miss cycles
2544system.l2c.overall_miss_latency::total 28824512975 # number of overall miss cycles
2545system.l2c.WritebackDirty_accesses::writebacks 266285 # number of WritebackDirty accesses(hits+misses)
2546system.l2c.WritebackDirty_accesses::total 266285 # number of WritebackDirty accesses(hits+misses)
2547system.l2c.UpgradeReq_accesses::cpu0.data 44020 # number of UpgradeReq accesses(hits+misses)
2548system.l2c.UpgradeReq_accesses::cpu1.data 4587 # number of UpgradeReq accesses(hits+misses)
2549system.l2c.UpgradeReq_accesses::total 48607 # number of UpgradeReq accesses(hits+misses)
2550system.l2c.SCUpgradeReq_accesses::cpu0.data 2948 # number of SCUpgradeReq accesses(hits+misses)
2551system.l2c.SCUpgradeReq_accesses::cpu1.data 2212 # number of SCUpgradeReq accesses(hits+misses)
2552system.l2c.SCUpgradeReq_accesses::total 5160 # number of SCUpgradeReq accesses(hits+misses)
2553system.l2c.ReadExReq_accesses::cpu0.data 15756 # number of ReadExReq accesses(hits+misses)
2554system.l2c.ReadExReq_accesses::cpu1.data 9391 # number of ReadExReq accesses(hits+misses)
2555system.l2c.ReadExReq_accesses::total 25147 # number of ReadExReq accesses(hits+misses)
2556system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 608 # number of ReadSharedReq accesses(hits+misses)
2557system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 94 # number of ReadSharedReq accesses(hits+misses)
2558system.l2c.ReadSharedReq_accesses::cpu0.inst 69933 # number of ReadSharedReq accesses(hits+misses)
2559system.l2c.ReadSharedReq_accesses::cpu0.data 61211 # number of ReadSharedReq accesses(hits+misses)
2560system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183389 # number of ReadSharedReq accesses(hits+misses)
2561system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 82 # number of ReadSharedReq accesses(hits+misses)
2562system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 15 # number of ReadSharedReq accesses(hits+misses)
2563system.l2c.ReadSharedReq_accesses::cpu1.inst 12857 # number of ReadSharedReq accesses(hits+misses)
2564system.l2c.ReadSharedReq_accesses::cpu1.data 7180 # number of ReadSharedReq accesses(hits+misses)
2565system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8875 # number of ReadSharedReq accesses(hits+misses)
2566system.l2c.ReadSharedReq_accesses::total 344244 # number of ReadSharedReq accesses(hits+misses)
2567system.l2c.demand_accesses::cpu0.dtb.walker 608 # number of demand (read+write) accesses
2568system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses
2569system.l2c.demand_accesses::cpu0.inst 69933 # number of demand (read+write) accesses
2570system.l2c.demand_accesses::cpu0.data 76967 # number of demand (read+write) accesses
2571system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183389 # number of demand (read+write) accesses
2572system.l2c.demand_accesses::cpu1.dtb.walker 82 # number of demand (read+write) accesses
2573system.l2c.demand_accesses::cpu1.itb.walker 15 # number of demand (read+write) accesses
2574system.l2c.demand_accesses::cpu1.inst 12857 # number of demand (read+write) accesses
2575system.l2c.demand_accesses::cpu1.data 16571 # number of demand (read+write) accesses
2576system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8875 # number of demand (read+write) accesses
2577system.l2c.demand_accesses::total 369391 # number of demand (read+write) accesses
2578system.l2c.overall_accesses::cpu0.dtb.walker 608 # number of overall (read+write) accesses
2579system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses
2580system.l2c.overall_accesses::cpu0.inst 69933 # number of overall (read+write) accesses
2581system.l2c.overall_accesses::cpu0.data 76967 # number of overall (read+write) accesses
2582system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183389 # number of overall (read+write) accesses
2583system.l2c.overall_accesses::cpu1.dtb.walker 82 # number of overall (read+write) accesses
2584system.l2c.overall_accesses::cpu1.itb.walker 15 # number of overall (read+write) accesses
2585system.l2c.overall_accesses::cpu1.inst 12857 # number of overall (read+write) accesses
2586system.l2c.overall_accesses::cpu1.data 16571 # number of overall (read+write) accesses
2587system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8875 # number of overall (read+write) accesses
2588system.l2c.overall_accesses::total 369391 # number of overall (read+write) accesses
2589system.l2c.UpgradeReq_miss_rate::cpu0.data 0.226284 # miss rate for UpgradeReq accesses
2590system.l2c.UpgradeReq_miss_rate::cpu1.data 0.516896 # miss rate for UpgradeReq accesses
2591system.l2c.UpgradeReq_miss_rate::total 0.253708 # miss rate for UpgradeReq accesses
2592system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.248982 # miss rate for SCUpgradeReq accesses
2593system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.585895 # miss rate for SCUpgradeReq accesses
2594system.l2c.SCUpgradeReq_miss_rate::total 0.393411 # miss rate for SCUpgradeReq accesses
2595system.l2c.ReadExReq_miss_rate::cpu0.data 0.718203 # miss rate for ReadExReq accesses
2596system.l2c.ReadExReq_miss_rate::cpu1.data 0.863273 # miss rate for ReadExReq accesses
2597system.l2c.ReadExReq_miss_rate::total 0.772378 # miss rate for ReadExReq accesses
2598system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.230263 # miss rate for ReadSharedReq accesses
2599system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.010638 # miss rate for ReadSharedReq accesses
2600system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.324411 # miss rate for ReadSharedReq accesses
2601system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162373 # miss rate for ReadSharedReq accesses
2602system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.731832 # miss rate for ReadSharedReq accesses
2603system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.134146 # miss rate for ReadSharedReq accesses
2604system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.245781 # miss rate for ReadSharedReq accesses
2605system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.232312 # miss rate for ReadSharedReq accesses
2606system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.591775 # miss rate for ReadSharedReq accesses
2607system.l2c.ReadSharedReq_miss_rate::total 0.514368 # miss rate for ReadSharedReq accesses
2608system.l2c.demand_miss_rate::cpu0.dtb.walker 0.230263 # miss rate for demand accesses
2609system.l2c.demand_miss_rate::cpu0.itb.walker 0.010638 # miss rate for demand accesses
2610system.l2c.demand_miss_rate::cpu0.inst 0.324411 # miss rate for demand accesses
2611system.l2c.demand_miss_rate::cpu0.data 0.276157 # miss rate for demand accesses
2612system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.731832 # miss rate for demand accesses
2613system.l2c.demand_miss_rate::cpu1.dtb.walker 0.134146 # miss rate for demand accesses
2614system.l2c.demand_miss_rate::cpu1.inst 0.245781 # miss rate for demand accesses
2615system.l2c.demand_miss_rate::cpu1.data 0.589886 # miss rate for demand accesses
2616system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.591775 # miss rate for demand accesses
2617system.l2c.demand_miss_rate::total 0.531932 # miss rate for demand accesses
2618system.l2c.overall_miss_rate::cpu0.dtb.walker 0.230263 # miss rate for overall accesses
2619system.l2c.overall_miss_rate::cpu0.itb.walker 0.010638 # miss rate for overall accesses
2620system.l2c.overall_miss_rate::cpu0.inst 0.324411 # miss rate for overall accesses
2621system.l2c.overall_miss_rate::cpu0.data 0.276157 # miss rate for overall accesses
2622system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.731832 # miss rate for overall accesses
2623system.l2c.overall_miss_rate::cpu1.dtb.walker 0.134146 # miss rate for overall accesses
2624system.l2c.overall_miss_rate::cpu1.inst 0.245781 # miss rate for overall accesses
2625system.l2c.overall_miss_rate::cpu1.data 0.589886 # miss rate for overall accesses
2626system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.591775 # miss rate for overall accesses
2627system.l2c.overall_miss_rate::total 0.531932 # miss rate for overall accesses
2628system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2909.346451 # average UpgradeReq miss latency
2629system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2251.370730 # average UpgradeReq miss latency
2630system.l2c.UpgradeReq_avg_miss_latency::total 2782.841388 # average UpgradeReq miss latency
2631system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6491.825613 # average SCUpgradeReq miss latency
2632system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1998.456790 # average SCUpgradeReq miss latency
2633system.l2c.SCUpgradeReq_avg_miss_latency::total 3623.152709 # average SCUpgradeReq miss latency
2634system.l2c.ReadExReq_avg_miss_latency::cpu0.data 148931.336161 # average ReadExReq miss latency
2635system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131991.612187 # average ReadExReq miss latency
2636system.l2c.ReadExReq_avg_miss_latency::total 141860.835092 # average ReadExReq miss latency
2637system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142982.142857 # average ReadSharedReq miss latency
2638system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 133000 # average ReadSharedReq miss latency
2639system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131102.503636 # average ReadSharedReq miss latency
2640system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136950.950800 # average ReadSharedReq miss latency
2641system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 150333.766329 # average ReadSharedReq miss latency
2642system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 135863.636364 # average ReadSharedReq miss latency
2643system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133189.873418 # average ReadSharedReq miss latency
2644system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138329.436451 # average ReadSharedReq miss latency
2645system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average ReadSharedReq miss latency
2646system.l2c.ReadSharedReq_avg_miss_latency::total 147226.771495 # average ReadSharedReq miss latency
2647system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142982.142857 # average overall miss latency
2648system.l2c.demand_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency
2649system.l2c.demand_avg_miss_latency::cpu0.inst 131102.503636 # average overall miss latency
2650system.l2c.demand_avg_miss_latency::cpu0.data 143329.216655 # average overall miss latency
2651system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150333.766329 # average overall miss latency
2652system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 135863.636364 # average overall miss latency
2653system.l2c.demand_avg_miss_latency::cpu1.inst 133189.873418 # average overall miss latency
2654system.l2c.demand_avg_miss_latency::cpu1.data 133073.094629 # average overall miss latency
2655system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average overall miss latency
2656system.l2c.demand_avg_miss_latency::total 146696.352377 # average overall miss latency
2657system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142982.142857 # average overall miss latency
2658system.l2c.overall_avg_miss_latency::cpu0.itb.walker 133000 # average overall miss latency
2659system.l2c.overall_avg_miss_latency::cpu0.inst 131102.503636 # average overall miss latency
2660system.l2c.overall_avg_miss_latency::cpu0.data 143329.216655 # average overall miss latency
2661system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150333.766329 # average overall miss latency
2662system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135863.636364 # average overall miss latency
2663system.l2c.overall_avg_miss_latency::cpu1.inst 133189.873418 # average overall miss latency
2664system.l2c.overall_avg_miss_latency::cpu1.data 133073.094629 # average overall miss latency
2665system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average overall miss latency
2666system.l2c.overall_avg_miss_latency::total 146696.352377 # average overall miss latency
2667system.l2c.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
2668system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2669system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2670system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2671system.l2c.avg_blocked_cycles::no_mshrs 45 # average number of cycles each access was blocked
2672system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

2710system.l2c.fast_writes 0 # number of fast writes performed
2711system.l2c.cache_copies 0 # number of cache copies performed

2712system.l2c.writebacks::writebacks 102335 # number of writebacks
2713system.l2c.writebacks::total 102335 # number of writebacks
2714system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
2715system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits
2716system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
2717system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
2718system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
2719system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
2720system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
2721system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
2722system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits
2723system.l2c.CleanEvict_mshr_misses::writebacks 3679 # number of CleanEvict MSHR misses
2724system.l2c.CleanEvict_mshr_misses::total 3679 # number of CleanEvict MSHR misses
2725system.l2c.UpgradeReq_mshr_misses::cpu0.data 9961 # number of UpgradeReq MSHR misses
2726system.l2c.UpgradeReq_mshr_misses::cpu1.data 2371 # number of UpgradeReq MSHR misses
2727system.l2c.UpgradeReq_mshr_misses::total 12332 # number of UpgradeReq MSHR misses
2728system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 734 # number of SCUpgradeReq MSHR misses
2729system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1296 # number of SCUpgradeReq MSHR misses
2730system.l2c.SCUpgradeReq_mshr_misses::total 2030 # number of SCUpgradeReq MSHR misses
2731system.l2c.ReadExReq_mshr_misses::cpu0.data 11316 # number of ReadExReq MSHR misses
2732system.l2c.ReadExReq_mshr_misses::cpu1.data 8107 # number of ReadExReq MSHR misses
2733system.l2c.ReadExReq_mshr_misses::total 19423 # number of ReadExReq MSHR misses
2734system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 140 # number of ReadSharedReq MSHR misses
2735system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses
2736system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22682 # number of ReadSharedReq MSHR misses
2737system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9939 # number of ReadSharedReq MSHR misses
2738system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134210 # number of ReadSharedReq MSHR misses
2739system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadSharedReq MSHR misses
2740system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3149 # number of ReadSharedReq MSHR misses
2741system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1668 # number of ReadSharedReq MSHR misses
2742system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5252 # number of ReadSharedReq MSHR misses
2743system.l2c.ReadSharedReq_mshr_misses::total 177052 # number of ReadSharedReq MSHR misses
2744system.l2c.demand_mshr_misses::cpu0.dtb.walker 140 # number of demand (read+write) MSHR misses
2745system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
2746system.l2c.demand_mshr_misses::cpu0.inst 22682 # number of demand (read+write) MSHR misses
2747system.l2c.demand_mshr_misses::cpu0.data 21255 # number of demand (read+write) MSHR misses
2748system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134210 # number of demand (read+write) MSHR misses
2749system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses
2750system.l2c.demand_mshr_misses::cpu1.inst 3149 # number of demand (read+write) MSHR misses
2751system.l2c.demand_mshr_misses::cpu1.data 9775 # number of demand (read+write) MSHR misses
2752system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5252 # number of demand (read+write) MSHR misses
2753system.l2c.demand_mshr_misses::total 196475 # number of demand (read+write) MSHR misses
2754system.l2c.overall_mshr_misses::cpu0.dtb.walker 140 # number of overall MSHR misses
2755system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
2756system.l2c.overall_mshr_misses::cpu0.inst 22682 # number of overall MSHR misses
2757system.l2c.overall_mshr_misses::cpu0.data 21255 # number of overall MSHR misses
2758system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134210 # number of overall MSHR misses
2759system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses
2760system.l2c.overall_mshr_misses::cpu1.inst 3149 # number of overall MSHR misses
2761system.l2c.overall_mshr_misses::cpu1.data 9775 # number of overall MSHR misses
2762system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5252 # number of overall MSHR misses
2763system.l2c.overall_mshr_misses::total 196475 # number of overall MSHR misses
2764system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable
2765system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32042 # number of ReadReq MSHR uncacheable
2766system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
2767system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2970 # number of ReadReq MSHR uncacheable
2768system.l2c.ReadReq_mshr_uncacheable::total 39041 # number of ReadReq MSHR uncacheable
2769system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable
2770system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable
2771system.l2c.WriteReq_mshr_uncacheable::total 31035 # number of WriteReq MSHR uncacheable
2772system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses
2773system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60766 # number of overall MSHR uncacheable misses
2774system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
2775system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5281 # number of overall MSHR uncacheable misses
2776system.l2c.overall_mshr_uncacheable_misses::total 70076 # number of overall MSHR uncacheable misses
2777system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 724560000 # number of UpgradeReq MSHR miss cycles
2778system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 171620000 # number of UpgradeReq MSHR miss cycles
2779system.l2c.UpgradeReq_mshr_miss_latency::total 896180000 # number of UpgradeReq MSHR miss cycles
2780system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 54722500 # number of SCUpgradeReq MSHR miss cycles
2781system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 95730500 # number of SCUpgradeReq MSHR miss cycles
2782system.l2c.SCUpgradeReq_mshr_miss_latency::total 150453000 # number of SCUpgradeReq MSHR miss cycles
2783system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1572143507 # number of ReadExReq MSHR miss cycles
2784system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 988981523 # number of ReadExReq MSHR miss cycles
2785system.l2c.ReadExReq_mshr_miss_latency::total 2561125030 # number of ReadExReq MSHR miss cycles
2786system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 18617001 # number of ReadSharedReq MSHR miss cycles
2787system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles
2788system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2746980529 # number of ReadSharedReq MSHR miss cycles
2789system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1261761509 # number of ReadSharedReq MSHR miss cycles
2790system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18834169861 # number of ReadSharedReq MSHR miss cycles
2791system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1384500 # number of ReadSharedReq MSHR miss cycles
2792system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 388132513 # number of ReadSharedReq MSHR miss cycles
2793system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 214052502 # number of ReadSharedReq MSHR miss cycles
2794system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of ReadSharedReq MSHR miss cycles
2795system.l2c.ReadSharedReq_mshr_miss_latency::total 24296806687 # number of ReadSharedReq MSHR miss cycles
2796system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 18617001 # number of demand (read+write) MSHR miss cycles
2797system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123000 # number of demand (read+write) MSHR miss cycles
2798system.l2c.demand_mshr_miss_latency::cpu0.inst 2746980529 # number of demand (read+write) MSHR miss cycles
2799system.l2c.demand_mshr_miss_latency::cpu0.data 2833905016 # number of demand (read+write) MSHR miss cycles
2800system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18834169861 # number of demand (read+write) MSHR miss cycles
2801system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1384500 # number of demand (read+write) MSHR miss cycles
2802system.l2c.demand_mshr_miss_latency::cpu1.inst 388132513 # number of demand (read+write) MSHR miss cycles
2803system.l2c.demand_mshr_miss_latency::cpu1.data 1203034025 # number of demand (read+write) MSHR miss cycles
2804system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of demand (read+write) MSHR miss cycles
2805system.l2c.demand_mshr_miss_latency::total 26857931717 # number of demand (read+write) MSHR miss cycles
2806system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 18617001 # number of overall MSHR miss cycles
2807system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123000 # number of overall MSHR miss cycles
2808system.l2c.overall_mshr_miss_latency::cpu0.inst 2746980529 # number of overall MSHR miss cycles
2809system.l2c.overall_mshr_miss_latency::cpu0.data 2833905016 # number of overall MSHR miss cycles
2810system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18834169861 # number of overall MSHR miss cycles
2811system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1384500 # number of overall MSHR miss cycles
2812system.l2c.overall_mshr_miss_latency::cpu1.inst 388132513 # number of overall MSHR miss cycles
2813system.l2c.overall_mshr_miss_latency::cpu1.data 1203034025 # number of overall MSHR miss cycles
2814system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of overall MSHR miss cycles
2815system.l2c.overall_mshr_miss_latency::total 26857931717 # number of overall MSHR miss cycles
2816system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443763000 # number of ReadReq MSHR uncacheable cycles
2817system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5869096507 # number of ReadReq MSHR uncacheable cycles
2818system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12223000 # number of ReadReq MSHR uncacheable cycles
2819system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 312114003 # number of ReadReq MSHR uncacheable cycles
2820system.l2c.ReadReq_mshr_uncacheable_latency::total 6637196510 # number of ReadReq MSHR uncacheable cycles

2673system.l2c.writebacks::writebacks 102335 # number of writebacks
2674system.l2c.writebacks::total 102335 # number of writebacks
2675system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
2676system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits
2677system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
2678system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
2679system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
2680system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
2681system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
2682system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
2683system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits
2684system.l2c.CleanEvict_mshr_misses::writebacks 3679 # number of CleanEvict MSHR misses
2685system.l2c.CleanEvict_mshr_misses::total 3679 # number of CleanEvict MSHR misses
2686system.l2c.UpgradeReq_mshr_misses::cpu0.data 9961 # number of UpgradeReq MSHR misses
2687system.l2c.UpgradeReq_mshr_misses::cpu1.data 2371 # number of UpgradeReq MSHR misses
2688system.l2c.UpgradeReq_mshr_misses::total 12332 # number of UpgradeReq MSHR misses
2689system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 734 # number of SCUpgradeReq MSHR misses
2690system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1296 # number of SCUpgradeReq MSHR misses
2691system.l2c.SCUpgradeReq_mshr_misses::total 2030 # number of SCUpgradeReq MSHR misses
2692system.l2c.ReadExReq_mshr_misses::cpu0.data 11316 # number of ReadExReq MSHR misses
2693system.l2c.ReadExReq_mshr_misses::cpu1.data 8107 # number of ReadExReq MSHR misses
2694system.l2c.ReadExReq_mshr_misses::total 19423 # number of ReadExReq MSHR misses
2695system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 140 # number of ReadSharedReq MSHR misses
2696system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses
2697system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22682 # number of ReadSharedReq MSHR misses
2698system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9939 # number of ReadSharedReq MSHR misses
2699system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134210 # number of ReadSharedReq MSHR misses
2700system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadSharedReq MSHR misses
2701system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3149 # number of ReadSharedReq MSHR misses
2702system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1668 # number of ReadSharedReq MSHR misses
2703system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5252 # number of ReadSharedReq MSHR misses
2704system.l2c.ReadSharedReq_mshr_misses::total 177052 # number of ReadSharedReq MSHR misses
2705system.l2c.demand_mshr_misses::cpu0.dtb.walker 140 # number of demand (read+write) MSHR misses
2706system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
2707system.l2c.demand_mshr_misses::cpu0.inst 22682 # number of demand (read+write) MSHR misses
2708system.l2c.demand_mshr_misses::cpu0.data 21255 # number of demand (read+write) MSHR misses
2709system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134210 # number of demand (read+write) MSHR misses
2710system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses
2711system.l2c.demand_mshr_misses::cpu1.inst 3149 # number of demand (read+write) MSHR misses
2712system.l2c.demand_mshr_misses::cpu1.data 9775 # number of demand (read+write) MSHR misses
2713system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5252 # number of demand (read+write) MSHR misses
2714system.l2c.demand_mshr_misses::total 196475 # number of demand (read+write) MSHR misses
2715system.l2c.overall_mshr_misses::cpu0.dtb.walker 140 # number of overall MSHR misses
2716system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
2717system.l2c.overall_mshr_misses::cpu0.inst 22682 # number of overall MSHR misses
2718system.l2c.overall_mshr_misses::cpu0.data 21255 # number of overall MSHR misses
2719system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134210 # number of overall MSHR misses
2720system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses
2721system.l2c.overall_mshr_misses::cpu1.inst 3149 # number of overall MSHR misses
2722system.l2c.overall_mshr_misses::cpu1.data 9775 # number of overall MSHR misses
2723system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5252 # number of overall MSHR misses
2724system.l2c.overall_mshr_misses::total 196475 # number of overall MSHR misses
2725system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable
2726system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32042 # number of ReadReq MSHR uncacheable
2727system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
2728system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2970 # number of ReadReq MSHR uncacheable
2729system.l2c.ReadReq_mshr_uncacheable::total 39041 # number of ReadReq MSHR uncacheable
2730system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable
2731system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable
2732system.l2c.WriteReq_mshr_uncacheable::total 31035 # number of WriteReq MSHR uncacheable
2733system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses
2734system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60766 # number of overall MSHR uncacheable misses
2735system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
2736system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5281 # number of overall MSHR uncacheable misses
2737system.l2c.overall_mshr_uncacheable_misses::total 70076 # number of overall MSHR uncacheable misses
2738system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 724560000 # number of UpgradeReq MSHR miss cycles
2739system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 171620000 # number of UpgradeReq MSHR miss cycles
2740system.l2c.UpgradeReq_mshr_miss_latency::total 896180000 # number of UpgradeReq MSHR miss cycles
2741system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 54722500 # number of SCUpgradeReq MSHR miss cycles
2742system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 95730500 # number of SCUpgradeReq MSHR miss cycles
2743system.l2c.SCUpgradeReq_mshr_miss_latency::total 150453000 # number of SCUpgradeReq MSHR miss cycles
2744system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1572143507 # number of ReadExReq MSHR miss cycles
2745system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 988981523 # number of ReadExReq MSHR miss cycles
2746system.l2c.ReadExReq_mshr_miss_latency::total 2561125030 # number of ReadExReq MSHR miss cycles
2747system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 18617001 # number of ReadSharedReq MSHR miss cycles
2748system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 123000 # number of ReadSharedReq MSHR miss cycles
2749system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2746980529 # number of ReadSharedReq MSHR miss cycles
2750system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1261761509 # number of ReadSharedReq MSHR miss cycles
2751system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18834169861 # number of ReadSharedReq MSHR miss cycles
2752system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1384500 # number of ReadSharedReq MSHR miss cycles
2753system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 388132513 # number of ReadSharedReq MSHR miss cycles
2754system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 214052502 # number of ReadSharedReq MSHR miss cycles
2755system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of ReadSharedReq MSHR miss cycles
2756system.l2c.ReadSharedReq_mshr_miss_latency::total 24296806687 # number of ReadSharedReq MSHR miss cycles
2757system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 18617001 # number of demand (read+write) MSHR miss cycles
2758system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123000 # number of demand (read+write) MSHR miss cycles
2759system.l2c.demand_mshr_miss_latency::cpu0.inst 2746980529 # number of demand (read+write) MSHR miss cycles
2760system.l2c.demand_mshr_miss_latency::cpu0.data 2833905016 # number of demand (read+write) MSHR miss cycles
2761system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18834169861 # number of demand (read+write) MSHR miss cycles
2762system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1384500 # number of demand (read+write) MSHR miss cycles
2763system.l2c.demand_mshr_miss_latency::cpu1.inst 388132513 # number of demand (read+write) MSHR miss cycles
2764system.l2c.demand_mshr_miss_latency::cpu1.data 1203034025 # number of demand (read+write) MSHR miss cycles
2765system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of demand (read+write) MSHR miss cycles
2766system.l2c.demand_mshr_miss_latency::total 26857931717 # number of demand (read+write) MSHR miss cycles
2767system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 18617001 # number of overall MSHR miss cycles
2768system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123000 # number of overall MSHR miss cycles
2769system.l2c.overall_mshr_miss_latency::cpu0.inst 2746980529 # number of overall MSHR miss cycles
2770system.l2c.overall_mshr_miss_latency::cpu0.data 2833905016 # number of overall MSHR miss cycles
2771system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18834169861 # number of overall MSHR miss cycles
2772system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1384500 # number of overall MSHR miss cycles
2773system.l2c.overall_mshr_miss_latency::cpu1.inst 388132513 # number of overall MSHR miss cycles
2774system.l2c.overall_mshr_miss_latency::cpu1.data 1203034025 # number of overall MSHR miss cycles
2775system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of overall MSHR miss cycles
2776system.l2c.overall_mshr_miss_latency::total 26857931717 # number of overall MSHR miss cycles
2777system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443763000 # number of ReadReq MSHR uncacheable cycles
2778system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5869096507 # number of ReadReq MSHR uncacheable cycles
2779system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12223000 # number of ReadReq MSHR uncacheable cycles
2780system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 312114003 # number of ReadReq MSHR uncacheable cycles
2781system.l2c.ReadReq_mshr_uncacheable_latency::total 6637196510 # number of ReadReq MSHR uncacheable cycles

2821system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4740559503 # number of WriteReq MSHR uncacheable cycles
2822system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 195045002 # number of WriteReq MSHR uncacheable cycles
2823system.l2c.WriteReq_mshr_uncacheable_latency::total 4935604505 # number of WriteReq MSHR uncacheable cycles

2824system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles

2782system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles

2825system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10609656010 # number of overall MSHR uncacheable cycles

2783system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5869096507 # number of overall MSHR uncacheable cycles

2826system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12223000 # number of overall MSHR uncacheable cycles

2784system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12223000 # number of overall MSHR uncacheable cycles

2827system.l2c.overall_mshr_uncacheable_latency::cpu1.data 507159005 # number of overall MSHR uncacheable cycles
2828system.l2c.overall_mshr_uncacheable_latency::total 11572801015 # number of overall MSHR uncacheable cycles

2785system.l2c.overall_mshr_uncacheable_latency::cpu1.data 312114003 # number of overall MSHR uncacheable cycles
2786system.l2c.overall_mshr_uncacheable_latency::total 6637196510 # number of overall MSHR uncacheable cycles

2829system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2830system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2831system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.226284 # mshr miss rate for UpgradeReq accesses
2832system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.516896 # mshr miss rate for UpgradeReq accesses
2833system.l2c.UpgradeReq_mshr_miss_rate::total 0.253708 # mshr miss rate for UpgradeReq accesses
2834system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.248982 # mshr miss rate for SCUpgradeReq accesses
2835system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585895 # mshr miss rate for SCUpgradeReq accesses
2836system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.393411 # mshr miss rate for SCUpgradeReq accesses
2837system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.718203 # mshr miss rate for ReadExReq accesses
2838system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.863273 # mshr miss rate for ReadExReq accesses
2839system.l2c.ReadExReq_mshr_miss_rate::total 0.772378 # mshr miss rate for ReadExReq accesses
2840system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.230263 # mshr miss rate for ReadSharedReq accesses
2841system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.010638 # mshr miss rate for ReadSharedReq accesses
2842system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.324339 # mshr miss rate for ReadSharedReq accesses
2843system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162373 # mshr miss rate for ReadSharedReq accesses
2844system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731832 # mshr miss rate for ReadSharedReq accesses
2845system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.134146 # mshr miss rate for ReadSharedReq accesses
2846system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.244925 # mshr miss rate for ReadSharedReq accesses
2847system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.232312 # mshr miss rate for ReadSharedReq accesses
2848system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.591775 # mshr miss rate for ReadSharedReq accesses
2849system.l2c.ReadSharedReq_mshr_miss_rate::total 0.514321 # mshr miss rate for ReadSharedReq accesses
2850system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.230263 # mshr miss rate for demand accesses
2851system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010638 # mshr miss rate for demand accesses
2852system.l2c.demand_mshr_miss_rate::cpu0.inst 0.324339 # mshr miss rate for demand accesses
2853system.l2c.demand_mshr_miss_rate::cpu0.data 0.276157 # mshr miss rate for demand accesses
2854system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731832 # mshr miss rate for demand accesses
2855system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.134146 # mshr miss rate for demand accesses
2856system.l2c.demand_mshr_miss_rate::cpu1.inst 0.244925 # mshr miss rate for demand accesses
2857system.l2c.demand_mshr_miss_rate::cpu1.data 0.589886 # mshr miss rate for demand accesses
2858system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.591775 # mshr miss rate for demand accesses
2859system.l2c.demand_mshr_miss_rate::total 0.531889 # mshr miss rate for demand accesses
2860system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.230263 # mshr miss rate for overall accesses
2861system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010638 # mshr miss rate for overall accesses
2862system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324339 # mshr miss rate for overall accesses
2863system.l2c.overall_mshr_miss_rate::cpu0.data 0.276157 # mshr miss rate for overall accesses
2864system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731832 # mshr miss rate for overall accesses
2865system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.134146 # mshr miss rate for overall accesses
2866system.l2c.overall_mshr_miss_rate::cpu1.inst 0.244925 # mshr miss rate for overall accesses
2867system.l2c.overall_mshr_miss_rate::cpu1.data 0.589886 # mshr miss rate for overall accesses
2868system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.591775 # mshr miss rate for overall accesses
2869system.l2c.overall_mshr_miss_rate::total 0.531889 # mshr miss rate for overall accesses
2870system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72739.684771 # average UpgradeReq mshr miss latency
2871system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72382.960776 # average UpgradeReq mshr miss latency
2872system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72671.099578 # average UpgradeReq mshr miss latency
2873system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74553.814714 # average SCUpgradeReq mshr miss latency
2874system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73866.126543 # average SCUpgradeReq mshr miss latency
2875system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74114.778325 # average SCUpgradeReq mshr miss latency
2876system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138931.027483 # average ReadExReq mshr miss latency
2877system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121991.059948 # average ReadExReq mshr miss latency
2878system.l2c.ReadExReq_avg_mshr_miss_latency::total 131860.424754 # average ReadExReq mshr miss latency
2879system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average ReadSharedReq mshr miss latency
2880system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency
2881system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average ReadSharedReq mshr miss latency
2882system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126950.549250 # average ReadSharedReq mshr miss latency
2883system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average ReadSharedReq mshr miss latency
2884system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average ReadSharedReq mshr miss latency
2885system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average ReadSharedReq mshr miss latency
2886system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128328.838129 # average ReadSharedReq mshr miss latency
2887system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average ReadSharedReq mshr miss latency
2888system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137229.778184 # average ReadSharedReq mshr miss latency
2889system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average overall mshr miss latency
2890system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
2891system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average overall mshr miss latency
2892system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133328.864550 # average overall mshr miss latency
2893system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average overall mshr miss latency
2894system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average overall mshr miss latency
2895system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average overall mshr miss latency
2896system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
2897system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
2898system.l2c.demand_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
2899system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average overall mshr miss latency
2900system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
2901system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average overall mshr miss latency
2902system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133328.864550 # average overall mshr miss latency
2903system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average overall mshr miss latency
2904system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average overall mshr miss latency
2905system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average overall mshr miss latency
2906system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
2907system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
2908system.l2c.overall_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
2909system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency
2910system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719 # average ReadReq mshr uncacheable latency
2911system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency
2912system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency
2913system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency

2787system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2788system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2789system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.226284 # mshr miss rate for UpgradeReq accesses
2790system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.516896 # mshr miss rate for UpgradeReq accesses
2791system.l2c.UpgradeReq_mshr_miss_rate::total 0.253708 # mshr miss rate for UpgradeReq accesses
2792system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.248982 # mshr miss rate for SCUpgradeReq accesses
2793system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585895 # mshr miss rate for SCUpgradeReq accesses
2794system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.393411 # mshr miss rate for SCUpgradeReq accesses
2795system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.718203 # mshr miss rate for ReadExReq accesses
2796system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.863273 # mshr miss rate for ReadExReq accesses
2797system.l2c.ReadExReq_mshr_miss_rate::total 0.772378 # mshr miss rate for ReadExReq accesses
2798system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.230263 # mshr miss rate for ReadSharedReq accesses
2799system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.010638 # mshr miss rate for ReadSharedReq accesses
2800system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.324339 # mshr miss rate for ReadSharedReq accesses
2801system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162373 # mshr miss rate for ReadSharedReq accesses
2802system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731832 # mshr miss rate for ReadSharedReq accesses
2803system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.134146 # mshr miss rate for ReadSharedReq accesses
2804system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.244925 # mshr miss rate for ReadSharedReq accesses
2805system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.232312 # mshr miss rate for ReadSharedReq accesses
2806system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.591775 # mshr miss rate for ReadSharedReq accesses
2807system.l2c.ReadSharedReq_mshr_miss_rate::total 0.514321 # mshr miss rate for ReadSharedReq accesses
2808system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.230263 # mshr miss rate for demand accesses
2809system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010638 # mshr miss rate for demand accesses
2810system.l2c.demand_mshr_miss_rate::cpu0.inst 0.324339 # mshr miss rate for demand accesses
2811system.l2c.demand_mshr_miss_rate::cpu0.data 0.276157 # mshr miss rate for demand accesses
2812system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731832 # mshr miss rate for demand accesses
2813system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.134146 # mshr miss rate for demand accesses
2814system.l2c.demand_mshr_miss_rate::cpu1.inst 0.244925 # mshr miss rate for demand accesses
2815system.l2c.demand_mshr_miss_rate::cpu1.data 0.589886 # mshr miss rate for demand accesses
2816system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.591775 # mshr miss rate for demand accesses
2817system.l2c.demand_mshr_miss_rate::total 0.531889 # mshr miss rate for demand accesses
2818system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.230263 # mshr miss rate for overall accesses
2819system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010638 # mshr miss rate for overall accesses
2820system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324339 # mshr miss rate for overall accesses
2821system.l2c.overall_mshr_miss_rate::cpu0.data 0.276157 # mshr miss rate for overall accesses
2822system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731832 # mshr miss rate for overall accesses
2823system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.134146 # mshr miss rate for overall accesses
2824system.l2c.overall_mshr_miss_rate::cpu1.inst 0.244925 # mshr miss rate for overall accesses
2825system.l2c.overall_mshr_miss_rate::cpu1.data 0.589886 # mshr miss rate for overall accesses
2826system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.591775 # mshr miss rate for overall accesses
2827system.l2c.overall_mshr_miss_rate::total 0.531889 # mshr miss rate for overall accesses
2828system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72739.684771 # average UpgradeReq mshr miss latency
2829system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72382.960776 # average UpgradeReq mshr miss latency
2830system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72671.099578 # average UpgradeReq mshr miss latency
2831system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74553.814714 # average SCUpgradeReq mshr miss latency
2832system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73866.126543 # average SCUpgradeReq mshr miss latency
2833system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74114.778325 # average SCUpgradeReq mshr miss latency
2834system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138931.027483 # average ReadExReq mshr miss latency
2835system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121991.059948 # average ReadExReq mshr miss latency
2836system.l2c.ReadExReq_avg_mshr_miss_latency::total 131860.424754 # average ReadExReq mshr miss latency
2837system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average ReadSharedReq mshr miss latency
2838system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency
2839system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average ReadSharedReq mshr miss latency
2840system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126950.549250 # average ReadSharedReq mshr miss latency
2841system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average ReadSharedReq mshr miss latency
2842system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average ReadSharedReq mshr miss latency
2843system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average ReadSharedReq mshr miss latency
2844system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128328.838129 # average ReadSharedReq mshr miss latency
2845system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average ReadSharedReq mshr miss latency
2846system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137229.778184 # average ReadSharedReq mshr miss latency
2847system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average overall mshr miss latency
2848system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
2849system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average overall mshr miss latency
2850system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133328.864550 # average overall mshr miss latency
2851system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average overall mshr miss latency
2852system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average overall mshr miss latency
2853system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average overall mshr miss latency
2854system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
2855system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
2856system.l2c.demand_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
2857system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average overall mshr miss latency
2858system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
2859system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average overall mshr miss latency
2860system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133328.864550 # average overall mshr miss latency
2861system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average overall mshr miss latency
2862system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average overall mshr miss latency
2863system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average overall mshr miss latency
2864system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
2865system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
2866system.l2c.overall_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
2867system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency
2868system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719 # average ReadReq mshr uncacheable latency
2869system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency
2870system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency
2871system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency

2914system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199 # average WriteReq mshr uncacheable latency
2915system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641 # average WriteReq mshr uncacheable latency
2916system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603 # average WriteReq mshr uncacheable latency

2917system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency

2872system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency

2918system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569 # average overall mshr uncacheable latency

2873system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96585.204012 # average overall mshr uncacheable latency

2919system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency

2874system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency

2920system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475 # average overall mshr uncacheable latency
2921system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951 # average overall mshr uncacheable latency
2922system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate

2875system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 59101.307139 # average overall mshr uncacheable latency
2876system.l2c.overall_avg_mshr_uncacheable_latency::total 94714.260374 # average overall mshr uncacheable latency