1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.848927 # Number of seconds simulated
4sim_ticks 2848926718000 # Number of ticks simulated
5final_tick 2848926718000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 263408 # Simulator instruction rate (inst/s)
8host_op_rate 318982 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5866973599 # Simulator tick rate (ticks/s)
10host_mem_usage 626336 # Number of bytes of host memory used
11host_seconds 485.59 # Real time elapsed on the host
12sim_insts 127907365 # Number of instructions simulated
13sim_ops 154893549 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.dtb.walker 9536 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 1676224 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 1355764 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8486720 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 229952 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 664980 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 417216 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
27system.physmem.bytes_read::total 12842440 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 1676224 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 229952 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 1906176 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 9074368 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
34system.physmem.bytes_written::total 9091932 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 149 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 26191 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 21707 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 132605 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.inst 3593 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.data 10411 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.l2cache.prefetcher 6519 # Number of read requests responded to by this memory
44system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
45system.physmem.num_reads::total 201207 # Number of read requests responded to by this memory
46system.physmem.num_writes::writebacks 141787 # Number of write requests responded to by this memory
47system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
49system.physmem.num_writes::total 146178 # Number of write requests responded to by this memory
50system.physmem.bw_read::cpu0.dtb.walker 3347 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.inst 588370 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.data 475886 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.l2cache.prefetcher 2978918 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.dtb.walker 359 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.inst 80715 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.data 233414 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.l2cache.prefetcher 146447 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::total 4507817 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_inst_read::cpu0.inst 588370 # Instruction read bandwidth from this memory (bytes/s)
62system.physmem.bw_inst_read::cpu1.inst 80715 # Instruction read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::total 669086 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_write::writebacks 3185188 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s)
66system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::total 3191353 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_total::writebacks 3185188 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.dtb.walker 3347 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.inst 588370 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.data 482037 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.l2cache.prefetcher 2978918 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu1.dtb.walker 359 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu1.inst 80715 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.data 233428 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.l2cache.prefetcher 146447 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::total 7699170 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.readReqs 201207 # Number of read requests accepted
81system.physmem.writeReqs 146178 # Number of write requests accepted
82system.physmem.readBursts 201207 # Number of DRAM read bursts, including those serviced by the write queue
83system.physmem.writeBursts 146178 # Number of DRAM write bursts, including those merged in the write queue
84system.physmem.bytesReadDRAM 12868352 # Total number of bytes read from DRAM
85system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue
86system.physmem.bytesWritten 9104640 # Total number of bytes written to DRAM
87system.physmem.bytesReadSys 12842440 # Total read bytes from the system interface side
88system.physmem.bytesWrittenSys 9091932 # Total written bytes from the system interface side
89system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
90system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one
91system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
92system.physmem.perBankRdBursts::0 12387 # Per bank write bursts
93system.physmem.perBankRdBursts::1 12818 # Per bank write bursts
94system.physmem.perBankRdBursts::2 13574 # Per bank write bursts
95system.physmem.perBankRdBursts::3 13051 # Per bank write bursts
96system.physmem.perBankRdBursts::4 15332 # Per bank write bursts
97system.physmem.perBankRdBursts::5 12655 # Per bank write bursts
98system.physmem.perBankRdBursts::6 12896 # Per bank write bursts
99system.physmem.perBankRdBursts::7 13054 # Per bank write bursts
100system.physmem.perBankRdBursts::8 12485 # Per bank write bursts
101system.physmem.perBankRdBursts::9 12494 # Per bank write bursts
102system.physmem.perBankRdBursts::10 11451 # Per bank write bursts
103system.physmem.perBankRdBursts::11 10701 # Per bank write bursts
104system.physmem.perBankRdBursts::12 11947 # Per bank write bursts
105system.physmem.perBankRdBursts::13 12784 # Per bank write bursts
106system.physmem.perBankRdBursts::14 11815 # Per bank write bursts
107system.physmem.perBankRdBursts::15 11624 # Per bank write bursts
108system.physmem.perBankWrBursts::0 9013 # Per bank write bursts
109system.physmem.perBankWrBursts::1 9459 # Per bank write bursts
110system.physmem.perBankWrBursts::2 10048 # Per bank write bursts
111system.physmem.perBankWrBursts::3 9447 # Per bank write bursts
112system.physmem.perBankWrBursts::4 8653 # Per bank write bursts
113system.physmem.perBankWrBursts::5 8898 # Per bank write bursts
114system.physmem.perBankWrBursts::6 9273 # Per bank write bursts
115system.physmem.perBankWrBursts::7 9228 # Per bank write bursts
116system.physmem.perBankWrBursts::8 8869 # Per bank write bursts
117system.physmem.perBankWrBursts::9 8977 # Per bank write bursts
118system.physmem.perBankWrBursts::10 8270 # Per bank write bursts
119system.physmem.perBankWrBursts::11 7926 # Per bank write bursts
120system.physmem.perBankWrBursts::12 8743 # Per bank write bursts
121system.physmem.perBankWrBursts::13 8906 # Per bank write bursts
122system.physmem.perBankWrBursts::14 8530 # Per bank write bursts
123system.physmem.perBankWrBursts::15 8020 # Per bank write bursts
124system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
125system.physmem.numWrRetry 92 # Number of times write queue was full causing retry
126system.physmem.totGap 2848926179000 # Total gap between requests
127system.physmem.readPktSize::0 0 # Read request sizes (log2)
128system.physmem.readPktSize::1 0 # Read request sizes (log2)
129system.physmem.readPktSize::2 554 # Read request sizes (log2)
130system.physmem.readPktSize::3 28 # Read request sizes (log2)
131system.physmem.readPktSize::4 0 # Read request sizes (log2)
132system.physmem.readPktSize::5 0 # Read request sizes (log2)
133system.physmem.readPktSize::6 200625 # Read request sizes (log2)
134system.physmem.writePktSize::0 0 # Write request sizes (log2)
135system.physmem.writePktSize::1 0 # Write request sizes (log2)
136system.physmem.writePktSize::2 4391 # Write request sizes (log2)
137system.physmem.writePktSize::3 0 # Write request sizes (log2)
138system.physmem.writePktSize::4 0 # Write request sizes (log2)
139system.physmem.writePktSize::5 0 # Write request sizes (log2)
140system.physmem.writePktSize::6 141787 # Write request sizes (log2)
141system.physmem.rdQLenPdf::0 84607 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::1 63376 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::2 11777 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::3 9873 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::4 8134 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::5 6758 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::6 5703 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::7 4957 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::8 3992 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::9 1032 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::11 278 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
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180system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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186system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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189system.physmem.wrQLenPdf::16 3600 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::17 4519 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::18 5173 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::19 6096 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::20 6500 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::21 7158 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::22 7619 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::24 8503 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::25 9779 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::27 8948 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::28 8671 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::29 9120 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::30 10048 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::31 8490 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::32 8247 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::33 856 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::34 530 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::35 465 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::42 262 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::43 233 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::44 210 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::46 244 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::47 202 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::48 179 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::49 224 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::50 212 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::52 233 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::55 224 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::56 245 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::58 142 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::60 215 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::61 210 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::62 161 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::63 295 # What write queue length does an incoming req see
237system.physmem.bytesPerActivate::samples 89804 # Bytes accessed per row activation
238system.physmem.bytesPerActivate::mean 244.676495 # Bytes accessed per row activation
239system.physmem.bytesPerActivate::gmean 140.021398 # Bytes accessed per row activation
240system.physmem.bytesPerActivate::stdev 301.276619 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::0-127 45910 51.12% 51.12% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::128-255 18733 20.86% 71.98% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::256-383 6663 7.42% 79.40% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::384-511 3737 4.16% 83.56% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::512-639 2991 3.33% 86.89% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::640-767 1528 1.70% 88.60% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::768-895 943 1.05% 89.65% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::896-1023 1048 1.17% 90.81% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::1024-1151 8251 9.19% 100.00% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::total 89804 # Bytes accessed per row activation
251system.physmem.rdPerTurnAround::samples 7084 # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::mean 28.382976 # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::stdev 553.950604 # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::0-2047 7082 99.97% 99.97% # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::total 7084 # Reads before turning the bus around for writes
258system.physmem.wrPerTurnAround::samples 7084 # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::mean 20.081875 # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::gmean 18.511113 # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::stdev 13.183489 # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::16-19 5975 84.35% 84.35% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::20-23 419 5.91% 90.26% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::24-27 68 0.96% 91.22% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::28-31 50 0.71% 91.93% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::32-35 261 3.68% 95.61% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::36-39 21 0.30% 95.91% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::40-43 13 0.18% 96.09% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::44-47 17 0.24% 96.33% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::48-51 10 0.14% 96.47% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::52-55 6 0.08% 96.56% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::56-59 8 0.11% 96.67% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::60-63 9 0.13% 96.80% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::64-67 144 2.03% 98.83% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::68-71 9 0.13% 98.96% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::72-75 5 0.07% 99.03% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::76-79 4 0.06% 99.08% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::80-83 8 0.11% 99.20% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::84-87 1 0.01% 99.21% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::88-91 2 0.03% 99.24% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::96-99 5 0.07% 99.31% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::104-107 1 0.01% 99.34% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::108-111 9 0.13% 99.46% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::124-127 3 0.04% 99.59% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::128-131 11 0.16% 99.75% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::132-135 2 0.03% 99.77% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::136-139 4 0.06% 99.83% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::140-143 3 0.04% 99.87% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::172-175 2 0.03% 99.96% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::192-195 3 0.04% 100.00% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::total 7084 # Writes before turning the bus around for reads
299system.physmem.totQLat 9521946881 # Total ticks spent queuing
300system.physmem.totMemAccLat 13291971881 # Total ticks spent from burst creation until serviced by the DRAM
301system.physmem.totBusLat 1005340000 # Total ticks spent in databus transfers
302system.physmem.avgQLat 47356.85 # Average queueing delay per DRAM burst
303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
304system.physmem.avgMemAccLat 66106.85 # Average memory access latency per DRAM burst
305system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s
306system.physmem.avgWrBW 3.20 # Average achieved write bandwidth in MiByte/s
307system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s
308system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s
309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
310system.physmem.busUtil 0.06 # Data bus utilization in percentage
311system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
312system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
313system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
314system.physmem.avgWrQLen 25.49 # Average write queue length when enqueuing
315system.physmem.readRowHits 166479 # Number of row buffer hits during reads
316system.physmem.writeRowHits 87044 # Number of row buffer hits during writes
317system.physmem.readRowHitRate 82.80 # Row buffer hit rate for reads
318system.physmem.writeRowHitRate 61.18 # Row buffer hit rate for writes
319system.physmem.avgGap 8201062.74 # Average gap between requests
320system.physmem.pageHitRate 73.84 # Row buffer hit rate, read and write combined
321system.physmem_0.actEnergy 339864000 # Energy for activate commands per rank (pJ)
322system.physmem_0.preEnergy 180642000 # Energy for precharge commands per rank (pJ)
323system.physmem_0.readEnergy 755176380 # Energy for read commands per rank (pJ)
324system.physmem_0.writeEnergy 386379180 # Energy for write commands per rank (pJ)
325system.physmem_0.refreshEnergy 5802201600.000001 # Energy for refresh commands per rank (pJ)
326system.physmem_0.actBackEnergy 5394350610 # Energy for active background per rank (pJ)
327system.physmem_0.preBackEnergy 323555040 # Energy for precharge background per rank (pJ)
328system.physmem_0.actPowerDownEnergy 11564942040 # Energy for active power-down per rank (pJ)
329system.physmem_0.prePowerDownEnergy 8568107520 # Energy for precharge power-down per rank (pJ)
330system.physmem_0.selfRefreshEnergy 670261966035 # Energy for self refresh per rank (pJ)
331system.physmem_0.totalEnergy 703579433835 # Total energy per rank (pJ)
332system.physmem_0.averagePower 246.962980 # Core power per rank (mW)
333system.physmem_0.totalIdleTime 2836248193267 # Total Idle time Per DRAM Rank
334system.physmem_0.memoryStateTime::IDLE 586826713 # Time in different power states
335system.physmem_0.memoryStateTime::REF 2465512000 # Time in different power states
336system.physmem_0.memoryStateTime::SREF 2788574898250 # Time in different power states
337system.physmem_0.memoryStateTime::PRE_PDN 22312648073 # Time in different power states
338system.physmem_0.memoryStateTime::ACT 9624892520 # Time in different power states
339system.physmem_0.memoryStateTime::ACT_PDN 25361940444 # Time in different power states
340system.physmem_1.actEnergy 301343700 # Energy for activate commands per rank (pJ)
341system.physmem_1.preEnergy 160164180 # Energy for precharge commands per rank (pJ)
342system.physmem_1.readEnergy 680449140 # Energy for read commands per rank (pJ)
343system.physmem_1.writeEnergy 356218020 # Energy for write commands per rank (pJ)
344system.physmem_1.refreshEnergy 5736435120.000001 # Energy for refresh commands per rank (pJ)
345system.physmem_1.actBackEnergy 5416162800 # Energy for active background per rank (pJ)
346system.physmem_1.preBackEnergy 310781280 # Energy for precharge background per rank (pJ)
347system.physmem_1.actPowerDownEnergy 10711678260 # Energy for active power-down per rank (pJ)
348system.physmem_1.prePowerDownEnergy 8807078880 # Energy for precharge power-down per rank (pJ)
349system.physmem_1.selfRefreshEnergy 670588805775 # Energy for self refresh per rank (pJ)
350system.physmem_1.totalEnergy 703071916065 # Total energy per rank (pJ)
351system.physmem_1.averagePower 246.784837 # Core power per rank (mW)
352system.physmem_1.totalIdleTime 2836233678907 # Total Idle time Per DRAM Rank
353system.physmem_1.memoryStateTime::IDLE 556712196 # Time in different power states
354system.physmem_1.memoryStateTime::REF 2438058000 # Time in different power states
355system.physmem_1.memoryStateTime::SREF 2789808007000 # Time in different power states
356system.physmem_1.memoryStateTime::PRE_PDN 22935120354 # Time in different power states
357system.physmem_1.memoryStateTime::ACT 9698204397 # Time in different power states
358system.physmem_1.memoryStateTime::ACT_PDN 23490616053 # Time in different power states
359system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
360system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
361system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
362system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory
363system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory
364system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory
365system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
366system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
367system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
368system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
369system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s)
370system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s)
371system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s)
372system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s)
373system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s)
374system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s)
375system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
376system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
377system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
378system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
379system.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
380system.bridge.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
381system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
382system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
383system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
384system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
385system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
386system.cf0.dma_write_txs 631 # Number of DMA write transactions.
387system.cpu0.branchPred.lookups 20832099 # Number of BP lookups
388system.cpu0.branchPred.condPredicted 13651765 # Number of conditional branches predicted
389system.cpu0.branchPred.condIncorrect 1014112 # Number of conditional branches incorrect
390system.cpu0.branchPred.BTBLookups 13085676 # Number of BTB lookups
391system.cpu0.branchPred.BTBHits 8745572 # Number of BTB hits
392system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
393system.cpu0.branchPred.BTBHitPct 66.833169 # BTB Hit Percentage
394system.cpu0.branchPred.usedRAS 3412344 # Number of times the RAS was used to get a target.
395system.cpu0.branchPred.RASInCorrect 213562 # Number of incorrect RAS predictions.
396system.cpu0.branchPred.indirectLookups 762387 # Number of indirect predictor lookups.
397system.cpu0.branchPred.indirectHits 580471 # Number of indirect target hits.
398system.cpu0.branchPred.indirectMisses 181916 # Number of indirect misses.
399system.cpu0.branchPredindirectMispredicted 99152 # Number of mispredicted indirect branches.
400system.cpu_clk_domain.clock 500 # Clock period in ticks
401system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
402system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
404system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
405system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
406system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
407system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

423system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
424system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
425system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
426system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
427system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
428system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
429system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
430system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
431system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
432system.cpu0.dtb.walker.walks 65584 # Table walker walks requested
433system.cpu0.dtb.walker.walksShort 65584 # Table walker walks initiated with short descriptors
434system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44931 # Level at which table walker walks with short descriptors terminate
435system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20653 # Level at which table walker walks with short descriptors terminate
436system.cpu0.dtb.walker.walkWaitTime::samples 65584 # Table walker wait (enqueue to first request) latency
437system.cpu0.dtb.walker.walkWaitTime::0 65584 100.00% 100.00% # Table walker wait (enqueue to first request) latency
438system.cpu0.dtb.walker.walkWaitTime::total 65584 # Table walker wait (enqueue to first request) latency
439system.cpu0.dtb.walker.walkCompletionTime::samples 6815 # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::mean 12330.961115 # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::gmean 11272.043541 # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::stdev 9573.930789 # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::0-65535 6808 99.90% 99.90% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::65536-131071 5 0.07% 99.97% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::196608-262143 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walkCompletionTime::total 6815 # Table walker service (enqueue to completion) latency
448system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution
449system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution
450system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution
451system.cpu0.dtb.walker.walkPageSizes::4K 5268 77.30% 77.30% # Table walker page sizes translated
452system.cpu0.dtb.walker.walkPageSizes::1M 1547 22.70% 100.00% # Table walker page sizes translated
453system.cpu0.dtb.walker.walkPageSizes::total 6815 # Table walker page sizes translated
454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65584 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65584 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6815 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
459system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6815 # Table walker requests started/completed, data/inst
460system.cpu0.dtb.walker.walkRequestOrigin::total 72399 # Table walker requests started/completed, data/inst
461system.cpu0.dtb.inst_hits 0 # ITB inst hits
462system.cpu0.dtb.inst_misses 0 # ITB inst misses
463system.cpu0.dtb.read_hits 17333612 # DTB read hits
464system.cpu0.dtb.read_misses 59171 # DTB read misses
465system.cpu0.dtb.write_hits 14536785 # DTB write hits
466system.cpu0.dtb.write_misses 6413 # DTB write misses
467system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
468system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
469system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
470system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
471system.cpu0.dtb.flush_entries 3455 # Number of entries that have been flushed from TLB
472system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions
473system.cpu0.dtb.prefetch_faults 1951 # Number of TLB faults due to prefetch
474system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
475system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions
476system.cpu0.dtb.read_accesses 17392783 # DTB read accesses
477system.cpu0.dtb.write_accesses 14543198 # DTB write accesses
478system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
479system.cpu0.dtb.hits 31870397 # DTB hits
480system.cpu0.dtb.misses 65584 # DTB misses
481system.cpu0.dtb.accesses 31935981 # DTB accesses
482system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
483system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

504system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
505system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
506system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
507system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
508system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
509system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
510system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
511system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
512system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
513system.cpu0.itb.walker.walks 3993 # Table walker walks requested
514system.cpu0.itb.walker.walksShort 3993 # Table walker walks initiated with short descriptors
515system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate
516system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3689 # Level at which table walker walks with short descriptors terminate
517system.cpu0.itb.walker.walkWaitTime::samples 3993 # Table walker wait (enqueue to first request) latency
518system.cpu0.itb.walker.walkWaitTime::0 3993 100.00% 100.00% # Table walker wait (enqueue to first request) latency
519system.cpu0.itb.walker.walkWaitTime::total 3993 # Table walker wait (enqueue to first request) latency
520system.cpu0.itb.walker.walkCompletionTime::samples 2420 # Table walker service (enqueue to completion) latency
521system.cpu0.itb.walker.walkCompletionTime::mean 12562.190083 # Table walker service (enqueue to completion) latency
522system.cpu0.itb.walker.walkCompletionTime::gmean 11733.706609 # Table walker service (enqueue to completion) latency
523system.cpu0.itb.walker.walkCompletionTime::stdev 5199.448662 # Table walker service (enqueue to completion) latency
524system.cpu0.itb.walker.walkCompletionTime::0-8191 453 18.72% 18.72% # Table walker service (enqueue to completion) latency
525system.cpu0.itb.walker.walkCompletionTime::8192-16383 1764 72.89% 91.61% # Table walker service (enqueue to completion) latency
526system.cpu0.itb.walker.walkCompletionTime::16384-24575 139 5.74% 97.36% # Table walker service (enqueue to completion) latency
527system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 98.80% # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 1.12% 99.92% # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::total 2420 # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution
533system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution
534system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution
535system.cpu0.itb.walker.walkPageSizes::4K 2121 87.64% 87.64% # Table walker page sizes translated
536system.cpu0.itb.walker.walkPageSizes::1M 299 12.36% 100.00% # Table walker page sizes translated
537system.cpu0.itb.walker.walkPageSizes::total 2420 # Table walker page sizes translated
538system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
539system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3993 # Table walker requests started/completed, data/inst
540system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3993 # Table walker requests started/completed, data/inst
541system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
542system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2420 # Table walker requests started/completed, data/inst
543system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2420 # Table walker requests started/completed, data/inst
544system.cpu0.itb.walker.walkRequestOrigin::total 6413 # Table walker requests started/completed, data/inst
545system.cpu0.itb.inst_hits 38722571 # ITB inst hits
546system.cpu0.itb.inst_misses 3993 # ITB inst misses
547system.cpu0.itb.read_hits 0 # DTB read hits
548system.cpu0.itb.read_misses 0 # DTB read misses
549system.cpu0.itb.write_hits 0 # DTB write hits
550system.cpu0.itb.write_misses 0 # DTB write misses
551system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
552system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
553system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
554system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
555system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
556system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
557system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
558system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
559system.cpu0.itb.perms_faults 7056 # Number of TLB faults due to permissions restrictions
560system.cpu0.itb.read_accesses 0 # DTB read accesses
561system.cpu0.itb.write_accesses 0 # DTB write accesses
562system.cpu0.itb.inst_accesses 38726564 # ITB inst accesses
563system.cpu0.itb.hits 38722571 # DTB hits
564system.cpu0.itb.misses 3993 # DTB misses
565system.cpu0.itb.accesses 38726564 # DTB accesses
566system.cpu0.numPwrStateTransitions 3692 # Number of power state transitions
567system.cpu0.pwrStateClkGateDist::samples 1846 # Distribution of time spent in the clock gated state
568system.cpu0.pwrStateClkGateDist::mean 1496527734.232936 # Distribution of time spent in the clock gated state
569system.cpu0.pwrStateClkGateDist::stdev 23959432114.332718 # Distribution of time spent in the clock gated state
570system.cpu0.pwrStateClkGateDist::underflows 1066 57.75% 57.75% # Distribution of time spent in the clock gated state
571system.cpu0.pwrStateClkGateDist::1000-5e+10 773 41.87% 99.62% # Distribution of time spent in the clock gated state
572system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state
573system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
574system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
575system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
576system.cpu0.pwrStateClkGateDist::max_value 499963466540 # Distribution of time spent in the clock gated state
577system.cpu0.pwrStateClkGateDist::total 1846 # Distribution of time spent in the clock gated state
578system.cpu0.pwrStateResidencyTicks::ON 86336520606 # Cumulative time (in ticks) in various power states
579system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762590197394 # Cumulative time (in ticks) in various power states
580system.cpu0.numCycles 172675597 # number of cpu cycles simulated
581system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
582system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
583system.cpu0.committedInsts 79702454 # Number of instructions committed
584system.cpu0.committedOps 95912008 # Number of ops (including micro ops) committed
585system.cpu0.discardedOps 5263315 # Number of ops (including micro ops) which were discarded before commit
586system.cpu0.numFetchSuspends 1846 # Number of times Execute suspended instruction fetching
587system.cpu0.quiesceCycles 5525206368 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
588system.cpu0.cpi 2.166503 # CPI: cycles per instruction
589system.cpu0.ipc 0.461573 # IPC: instructions per cycle
590system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction
591system.cpu0.op_class_0::IntAlu 63720470 66.44% 66.44% # Class of committed instruction
592system.cpu0.op_class_0::IntMult 92091 0.10% 66.53% # Class of committed instruction
593system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction
594system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction
595system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction
596system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction
597system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction
598system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.53% # Class of committed instruction
599system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction
600system.cpu0.op_class_0::FloatMisc 0 0.00% 66.53% # Class of committed instruction
601system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction
602system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction
603system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction
604system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction
605system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction
606system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction
607system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction
608system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction
609system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction
610system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction
611system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction
612system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction
613system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction
614system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction
615system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction
616system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction
617system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction
618system.cpu0.op_class_0::SimdFloatMisc 8071 0.01% 66.54% # Class of committed instruction
619system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction
620system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction
621system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction
622system.cpu0.op_class_0::MemRead 16805556 17.52% 84.07% # Class of committed instruction
623system.cpu0.op_class_0::MemWrite 15273907 15.92% 99.99% # Class of committed instruction
624system.cpu0.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction
625system.cpu0.op_class_0::FloatMemWrite 7384 0.01% 100.00% # Class of committed instruction
626system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
627system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
628system.cpu0.op_class_0::total 95912008 # Class of committed instruction
629system.cpu0.kern.inst.arm 0 # number of arm instructions executed
630system.cpu0.kern.inst.quiesce 1846 # number of quiesce instructions executed
631system.cpu0.tickCycles 120803038 # Number of cycles that the object actually ticked
632system.cpu0.idleCycles 51872559 # Total number of cycles that the object has spent stopped
633system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
634system.cpu0.dcache.tags.replacements 716043 # number of replacements
635system.cpu0.dcache.tags.tagsinuse 497.070686 # Cycle average of tags in use
636system.cpu0.dcache.tags.total_refs 30430864 # Total number of references to valid blocks.
637system.cpu0.dcache.tags.sampled_refs 716555 # Sample count of references to valid blocks.
638system.cpu0.dcache.tags.avg_refs 42.468288 # Average number of references to valid blocks.
639system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit.
640system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.070686 # Average occupied blocks per requestor
641system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970841 # Average percentage of cache occupancy
642system.cpu0.dcache.tags.occ_percent::total 0.970841 # Average percentage of cache occupancy
643system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
644system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
645system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id
646system.cpu0.dcache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id
647system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
648system.cpu0.dcache.tags.tag_accesses 63800570 # Number of tag accesses
649system.cpu0.dcache.tags.data_accesses 63800570 # Number of data accesses
650system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
651system.cpu0.dcache.ReadReq_hits::cpu0.data 15847676 # number of ReadReq hits
652system.cpu0.dcache.ReadReq_hits::total 15847676 # number of ReadReq hits
653system.cpu0.dcache.WriteReq_hits::cpu0.data 13422923 # number of WriteReq hits
654system.cpu0.dcache.WriteReq_hits::total 13422923 # number of WriteReq hits
655system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320765 # number of SoftPFReq hits
656system.cpu0.dcache.SoftPFReq_hits::total 320765 # number of SoftPFReq hits
657system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365692 # number of LoadLockedReq hits
658system.cpu0.dcache.LoadLockedReq_hits::total 365692 # number of LoadLockedReq hits
659system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361178 # number of StoreCondReq hits
660system.cpu0.dcache.StoreCondReq_hits::total 361178 # number of StoreCondReq hits
661system.cpu0.dcache.demand_hits::cpu0.data 29270599 # number of demand (read+write) hits
662system.cpu0.dcache.demand_hits::total 29270599 # number of demand (read+write) hits
663system.cpu0.dcache.overall_hits::cpu0.data 29591364 # number of overall hits
664system.cpu0.dcache.overall_hits::total 29591364 # number of overall hits
665system.cpu0.dcache.ReadReq_misses::cpu0.data 438302 # number of ReadReq misses
666system.cpu0.dcache.ReadReq_misses::total 438302 # number of ReadReq misses
667system.cpu0.dcache.WriteReq_misses::cpu0.data 581071 # number of WriteReq misses
668system.cpu0.dcache.WriteReq_misses::total 581071 # number of WriteReq misses
669system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135874 # number of SoftPFReq misses
670system.cpu0.dcache.SoftPFReq_misses::total 135874 # number of SoftPFReq misses
671system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20748 # number of LoadLockedReq misses
672system.cpu0.dcache.LoadLockedReq_misses::total 20748 # number of LoadLockedReq misses
673system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20391 # number of StoreCondReq misses
674system.cpu0.dcache.StoreCondReq_misses::total 20391 # number of StoreCondReq misses
675system.cpu0.dcache.demand_misses::cpu0.data 1019373 # number of demand (read+write) misses
676system.cpu0.dcache.demand_misses::total 1019373 # number of demand (read+write) misses
677system.cpu0.dcache.overall_misses::cpu0.data 1155247 # number of overall misses
678system.cpu0.dcache.overall_misses::total 1155247 # number of overall misses
679system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6426011500 # number of ReadReq miss cycles
680system.cpu0.dcache.ReadReq_miss_latency::total 6426011500 # number of ReadReq miss cycles
681system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11337499000 # number of WriteReq miss cycles
682system.cpu0.dcache.WriteReq_miss_latency::total 11337499000 # number of WriteReq miss cycles
683system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330321500 # number of LoadLockedReq miss cycles
684system.cpu0.dcache.LoadLockedReq_miss_latency::total 330321500 # number of LoadLockedReq miss cycles
685system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481265000 # number of StoreCondReq miss cycles
686system.cpu0.dcache.StoreCondReq_miss_latency::total 481265000 # number of StoreCondReq miss cycles
687system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 655500 # number of StoreCondFailReq miss cycles
688system.cpu0.dcache.StoreCondFailReq_miss_latency::total 655500 # number of StoreCondFailReq miss cycles
689system.cpu0.dcache.demand_miss_latency::cpu0.data 17763510500 # number of demand (read+write) miss cycles
690system.cpu0.dcache.demand_miss_latency::total 17763510500 # number of demand (read+write) miss cycles
691system.cpu0.dcache.overall_miss_latency::cpu0.data 17763510500 # number of overall miss cycles
692system.cpu0.dcache.overall_miss_latency::total 17763510500 # number of overall miss cycles
693system.cpu0.dcache.ReadReq_accesses::cpu0.data 16285978 # number of ReadReq accesses(hits+misses)
694system.cpu0.dcache.ReadReq_accesses::total 16285978 # number of ReadReq accesses(hits+misses)
695system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003994 # number of WriteReq accesses(hits+misses)
696system.cpu0.dcache.WriteReq_accesses::total 14003994 # number of WriteReq accesses(hits+misses)
697system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456639 # number of SoftPFReq accesses(hits+misses)
698system.cpu0.dcache.SoftPFReq_accesses::total 456639 # number of SoftPFReq accesses(hits+misses)
699system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386440 # number of LoadLockedReq accesses(hits+misses)
700system.cpu0.dcache.LoadLockedReq_accesses::total 386440 # number of LoadLockedReq accesses(hits+misses)
701system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381569 # number of StoreCondReq accesses(hits+misses)
702system.cpu0.dcache.StoreCondReq_accesses::total 381569 # number of StoreCondReq accesses(hits+misses)
703system.cpu0.dcache.demand_accesses::cpu0.data 30289972 # number of demand (read+write) accesses
704system.cpu0.dcache.demand_accesses::total 30289972 # number of demand (read+write) accesses
705system.cpu0.dcache.overall_accesses::cpu0.data 30746611 # number of overall (read+write) accesses
706system.cpu0.dcache.overall_accesses::total 30746611 # number of overall (read+write) accesses
707system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026913 # miss rate for ReadReq accesses
708system.cpu0.dcache.ReadReq_miss_rate::total 0.026913 # miss rate for ReadReq accesses
709system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041493 # miss rate for WriteReq accesses
710system.cpu0.dcache.WriteReq_miss_rate::total 0.041493 # miss rate for WriteReq accesses
711system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297552 # miss rate for SoftPFReq accesses
712system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297552 # miss rate for SoftPFReq accesses
713system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053690 # miss rate for LoadLockedReq accesses
714system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053690 # miss rate for LoadLockedReq accesses
715system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053440 # miss rate for StoreCondReq accesses
716system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053440 # miss rate for StoreCondReq accesses
717system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033654 # miss rate for demand accesses
718system.cpu0.dcache.demand_miss_rate::total 0.033654 # miss rate for demand accesses
719system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037573 # miss rate for overall accesses
720system.cpu0.dcache.overall_miss_rate::total 0.037573 # miss rate for overall accesses
721system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14661.150303 # average ReadReq miss latency
722system.cpu0.dcache.ReadReq_avg_miss_latency::total 14661.150303 # average ReadReq miss latency
723system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19511.383291 # average WriteReq miss latency
724system.cpu0.dcache.WriteReq_avg_miss_latency::total 19511.383291 # average WriteReq miss latency
725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15920.642954 # average LoadLockedReq miss latency
726system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15920.642954 # average LoadLockedReq miss latency
727system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23601.834143 # average StoreCondReq miss latency
728system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23601.834143 # average StoreCondReq miss latency
729system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
730system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
731system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17425.918187 # average overall miss latency
732system.cpu0.dcache.demand_avg_miss_latency::total 17425.918187 # average overall miss latency
733system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15376.374490 # average overall miss latency
734system.cpu0.dcache.overall_avg_miss_latency::total 15376.374490 # average overall miss latency
735system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
736system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
737system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
738system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
739system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
740system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
741system.cpu0.dcache.writebacks::writebacks 716044 # number of writebacks
742system.cpu0.dcache.writebacks::total 716044 # number of writebacks
743system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44411 # number of ReadReq MSHR hits
744system.cpu0.dcache.ReadReq_mshr_hits::total 44411 # number of ReadReq MSHR hits
745system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255478 # number of WriteReq MSHR hits
746system.cpu0.dcache.WriteReq_mshr_hits::total 255478 # number of WriteReq MSHR hits
747system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14411 # number of LoadLockedReq MSHR hits
748system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14411 # number of LoadLockedReq MSHR hits
749system.cpu0.dcache.demand_mshr_hits::cpu0.data 299889 # number of demand (read+write) MSHR hits
750system.cpu0.dcache.demand_mshr_hits::total 299889 # number of demand (read+write) MSHR hits
751system.cpu0.dcache.overall_mshr_hits::cpu0.data 299889 # number of overall MSHR hits
752system.cpu0.dcache.overall_mshr_hits::total 299889 # number of overall MSHR hits
753system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393891 # number of ReadReq MSHR misses
754system.cpu0.dcache.ReadReq_mshr_misses::total 393891 # number of ReadReq MSHR misses
755system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325593 # number of WriteReq MSHR misses
756system.cpu0.dcache.WriteReq_mshr_misses::total 325593 # number of WriteReq MSHR misses
757system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102318 # number of SoftPFReq MSHR misses
758system.cpu0.dcache.SoftPFReq_mshr_misses::total 102318 # number of SoftPFReq MSHR misses
759system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6337 # number of LoadLockedReq MSHR misses
760system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6337 # number of LoadLockedReq MSHR misses
761system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20391 # number of StoreCondReq MSHR misses
762system.cpu0.dcache.StoreCondReq_mshr_misses::total 20391 # number of StoreCondReq MSHR misses
763system.cpu0.dcache.demand_mshr_misses::cpu0.data 719484 # number of demand (read+write) MSHR misses
764system.cpu0.dcache.demand_mshr_misses::total 719484 # number of demand (read+write) MSHR misses
765system.cpu0.dcache.overall_mshr_misses::cpu0.data 821802 # number of overall MSHR misses
766system.cpu0.dcache.overall_mshr_misses::total 821802 # number of overall MSHR misses
767system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable
768system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20577 # number of ReadReq MSHR uncacheable
769system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable
770system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable
771system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39847 # number of overall MSHR uncacheable misses
772system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39847 # number of overall MSHR uncacheable misses
773system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5265212000 # number of ReadReq MSHR miss cycles
774system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5265212000 # number of ReadReq MSHR miss cycles
775system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6193589500 # number of WriteReq MSHR miss cycles
776system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6193589500 # number of WriteReq MSHR miss cycles
777system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1698431500 # number of SoftPFReq MSHR miss cycles
778system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1698431500 # number of SoftPFReq MSHR miss cycles
779system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 100630000 # number of LoadLockedReq MSHR miss cycles
780system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100630000 # number of LoadLockedReq MSHR miss cycles
781system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 460892000 # number of StoreCondReq MSHR miss cycles
782system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 460892000 # number of StoreCondReq MSHR miss cycles
783system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 637500 # number of StoreCondFailReq MSHR miss cycles
784system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 637500 # number of StoreCondFailReq MSHR miss cycles
785system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11458801500 # number of demand (read+write) MSHR miss cycles
786system.cpu0.dcache.demand_mshr_miss_latency::total 11458801500 # number of demand (read+write) MSHR miss cycles
787system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13157233000 # number of overall MSHR miss cycles
788system.cpu0.dcache.overall_mshr_miss_latency::total 13157233000 # number of overall MSHR miss cycles
789system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4606601500 # number of ReadReq MSHR uncacheable cycles
790system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4606601500 # number of ReadReq MSHR uncacheable cycles
791system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4606601500 # number of overall MSHR uncacheable cycles
792system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4606601500 # number of overall MSHR uncacheable cycles
793system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024186 # mshr miss rate for ReadReq accesses
794system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024186 # mshr miss rate for ReadReq accesses
795system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023250 # mshr miss rate for WriteReq accesses
796system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023250 # mshr miss rate for WriteReq accesses
797system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224068 # mshr miss rate for SoftPFReq accesses
798system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224068 # mshr miss rate for SoftPFReq accesses
799system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016398 # mshr miss rate for LoadLockedReq accesses
800system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016398 # mshr miss rate for LoadLockedReq accesses
801system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053440 # mshr miss rate for StoreCondReq accesses
802system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053440 # mshr miss rate for StoreCondReq accesses
803system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023753 # mshr miss rate for demand accesses
804system.cpu0.dcache.demand_mshr_miss_rate::total 0.023753 # mshr miss rate for demand accesses
805system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026728 # mshr miss rate for overall accesses
806system.cpu0.dcache.overall_mshr_miss_rate::total 0.026728 # mshr miss rate for overall accesses
807system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13367.180261 # average ReadReq mshr miss latency
808system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13367.180261 # average ReadReq mshr miss latency
809system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19022.489734 # average WriteReq mshr miss latency
810system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19022.489734 # average WriteReq mshr miss latency
811system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16599.537716 # average SoftPFReq mshr miss latency
812system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16599.537716 # average SoftPFReq mshr miss latency
813system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15879.753827 # average LoadLockedReq mshr miss latency
814system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15879.753827 # average LoadLockedReq mshr miss latency
815system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22602.716885 # average StoreCondReq mshr miss latency
816system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22602.716885 # average StoreCondReq mshr miss latency
817system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
818system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
819system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15926.416015 # average overall mshr miss latency
820system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15926.416015 # average overall mshr miss latency
821system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16010.222657 # average overall mshr miss latency
822system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16010.222657 # average overall mshr miss latency
823system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.385528 # average ReadReq mshr uncacheable latency
824system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.385528 # average ReadReq mshr uncacheable latency
825system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115607.235175 # average overall mshr uncacheable latency
826system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115607.235175 # average overall mshr uncacheable latency
827system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
828system.cpu0.icache.tags.replacements 1964076 # number of replacements
829system.cpu0.icache.tags.tagsinuse 511.773099 # Cycle average of tags in use
830system.cpu0.icache.tags.total_refs 36750687 # Total number of references to valid blocks.
831system.cpu0.icache.tags.sampled_refs 1964588 # Sample count of references to valid blocks.
832system.cpu0.icache.tags.avg_refs 18.706562 # Average number of references to valid blocks.
833system.cpu0.icache.tags.warmup_cycle 6697445000 # Cycle when the warmup percentage was hit.
834system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773099 # Average occupied blocks per requestor
835system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999557 # Average percentage of cache occupancy
836system.cpu0.icache.tags.occ_percent::total 0.999557 # Average percentage of cache occupancy
837system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
838system.cpu0.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
839system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
840system.cpu0.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id
841system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
842system.cpu0.icache.tags.tag_accesses 79395176 # Number of tag accesses
843system.cpu0.icache.tags.data_accesses 79395176 # Number of data accesses
844system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
845system.cpu0.icache.ReadReq_hits::cpu0.inst 36750687 # number of ReadReq hits
846system.cpu0.icache.ReadReq_hits::total 36750687 # number of ReadReq hits
847system.cpu0.icache.demand_hits::cpu0.inst 36750687 # number of demand (read+write) hits
848system.cpu0.icache.demand_hits::total 36750687 # number of demand (read+write) hits
849system.cpu0.icache.overall_hits::cpu0.inst 36750687 # number of overall hits
850system.cpu0.icache.overall_hits::total 36750687 # number of overall hits
851system.cpu0.icache.ReadReq_misses::cpu0.inst 1964601 # number of ReadReq misses
852system.cpu0.icache.ReadReq_misses::total 1964601 # number of ReadReq misses
853system.cpu0.icache.demand_misses::cpu0.inst 1964601 # number of demand (read+write) misses
854system.cpu0.icache.demand_misses::total 1964601 # number of demand (read+write) misses
855system.cpu0.icache.overall_misses::cpu0.inst 1964601 # number of overall misses
856system.cpu0.icache.overall_misses::total 1964601 # number of overall misses
857system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19791309500 # number of ReadReq miss cycles
858system.cpu0.icache.ReadReq_miss_latency::total 19791309500 # number of ReadReq miss cycles
859system.cpu0.icache.demand_miss_latency::cpu0.inst 19791309500 # number of demand (read+write) miss cycles
860system.cpu0.icache.demand_miss_latency::total 19791309500 # number of demand (read+write) miss cycles
861system.cpu0.icache.overall_miss_latency::cpu0.inst 19791309500 # number of overall miss cycles
862system.cpu0.icache.overall_miss_latency::total 19791309500 # number of overall miss cycles
863system.cpu0.icache.ReadReq_accesses::cpu0.inst 38715288 # number of ReadReq accesses(hits+misses)
864system.cpu0.icache.ReadReq_accesses::total 38715288 # number of ReadReq accesses(hits+misses)
865system.cpu0.icache.demand_accesses::cpu0.inst 38715288 # number of demand (read+write) accesses
866system.cpu0.icache.demand_accesses::total 38715288 # number of demand (read+write) accesses
867system.cpu0.icache.overall_accesses::cpu0.inst 38715288 # number of overall (read+write) accesses
868system.cpu0.icache.overall_accesses::total 38715288 # number of overall (read+write) accesses
869system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050745 # miss rate for ReadReq accesses
870system.cpu0.icache.ReadReq_miss_rate::total 0.050745 # miss rate for ReadReq accesses
871system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050745 # miss rate for demand accesses
872system.cpu0.icache.demand_miss_rate::total 0.050745 # miss rate for demand accesses
873system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050745 # miss rate for overall accesses
874system.cpu0.icache.overall_miss_rate::total 0.050745 # miss rate for overall accesses
875system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10073.958783 # average ReadReq miss latency
876system.cpu0.icache.ReadReq_avg_miss_latency::total 10073.958783 # average ReadReq miss latency
877system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10073.958783 # average overall miss latency
878system.cpu0.icache.demand_avg_miss_latency::total 10073.958783 # average overall miss latency
879system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.958783 # average overall miss latency
880system.cpu0.icache.overall_avg_miss_latency::total 10073.958783 # average overall miss latency
881system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
882system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
883system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
884system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
885system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
886system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
887system.cpu0.icache.writebacks::writebacks 1964076 # number of writebacks
888system.cpu0.icache.writebacks::total 1964076 # number of writebacks
889system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1964601 # number of ReadReq MSHR misses
890system.cpu0.icache.ReadReq_mshr_misses::total 1964601 # number of ReadReq MSHR misses
891system.cpu0.icache.demand_mshr_misses::cpu0.inst 1964601 # number of demand (read+write) MSHR misses
892system.cpu0.icache.demand_mshr_misses::total 1964601 # number of demand (read+write) MSHR misses
893system.cpu0.icache.overall_mshr_misses::cpu0.inst 1964601 # number of overall MSHR misses
894system.cpu0.icache.overall_mshr_misses::total 1964601 # number of overall MSHR misses
895system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable
896system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277 # number of ReadReq MSHR uncacheable
897system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses
898system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277 # number of overall MSHR uncacheable misses
899system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18809009500 # number of ReadReq MSHR miss cycles
900system.cpu0.icache.ReadReq_mshr_miss_latency::total 18809009500 # number of ReadReq MSHR miss cycles
901system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18809009500 # number of demand (read+write) MSHR miss cycles
902system.cpu0.icache.demand_mshr_miss_latency::total 18809009500 # number of demand (read+write) MSHR miss cycles
903system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18809009500 # number of overall MSHR miss cycles
904system.cpu0.icache.overall_mshr_miss_latency::total 18809009500 # number of overall MSHR miss cycles
905system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 # number of ReadReq MSHR uncacheable cycles
906system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 # number of ReadReq MSHR uncacheable cycles
907system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 # number of overall MSHR uncacheable cycles
908system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 # number of overall MSHR uncacheable cycles
909system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050745 # mshr miss rate for ReadReq accesses
910system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050745 # mshr miss rate for ReadReq accesses
911system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050745 # mshr miss rate for demand accesses
912system.cpu0.icache.demand_mshr_miss_rate::total 0.050745 # mshr miss rate for demand accesses
913system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050745 # mshr miss rate for overall accesses
914system.cpu0.icache.overall_mshr_miss_rate::total 0.050745 # mshr miss rate for overall accesses
915system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9573.959038 # average ReadReq mshr miss latency
916system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9573.959038 # average ReadReq mshr miss latency
917system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.959038 # average overall mshr miss latency
918system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.959038 # average overall mshr miss latency
919system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.959038 # average overall mshr miss latency
920system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.959038 # average overall mshr miss latency
921system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average ReadReq mshr uncacheable latency
922system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 # average ReadReq mshr uncacheable latency
923system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average overall mshr uncacheable latency
924system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 # average overall mshr uncacheable latency
925system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
926system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843459 # number of hwpf issued
927system.cpu0.l2cache.prefetcher.pfIdentified 1843558 # number of prefetch candidates identified
928system.cpu0.l2cache.prefetcher.pfBufferHit 87 # number of redundant prefetches already in prefetch queue
929system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
930system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
931system.cpu0.l2cache.prefetcher.pfSpanPage 234570 # number of prefetches not generated due to page crossing
932system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
933system.cpu0.l2cache.tags.replacements 289188 # number of replacements
934system.cpu0.l2cache.tags.tagsinuse 15635.373554 # Cycle average of tags in use
935system.cpu0.l2cache.tags.total_refs 2589127 # Total number of references to valid blocks.
936system.cpu0.l2cache.tags.sampled_refs 304798 # Sample count of references to valid blocks.
937system.cpu0.l2cache.tags.avg_refs 8.494567 # Average number of references to valid blocks.
938system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
939system.cpu0.l2cache.tags.occ_blocks::writebacks 14528.592543 # Average occupied blocks per requestor
940system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.479311 # Average occupied blocks per requestor
941system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.075767 # Average occupied blocks per requestor
942system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1041.225933 # Average occupied blocks per requestor
943system.cpu0.l2cache.tags.occ_percent::writebacks 0.886755 # Average percentage of cache occupancy
944system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003997 # Average percentage of cache occupancy
945system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
946system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063551 # Average percentage of cache occupancy
947system.cpu0.l2cache.tags.occ_percent::total 0.954307 # Average percentage of cache occupancy
948system.cpu0.l2cache.tags.occ_task_id_blocks::1022 228 # Occupied blocks per task id
949system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
950system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15366 # Occupied blocks per task id
951system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
952system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 19 # Occupied blocks per task id
953system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 147 # Occupied blocks per task id
954system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 59 # Occupied blocks per task id
955system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
956system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
957system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
958system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
959system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id
960system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1155 # Occupied blocks per task id
961system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7305 # Occupied blocks per task id
962system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5549 # Occupied blocks per task id
963system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1111 # Occupied blocks per task id
964system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.013916 # Percentage of cache occupancy per task id
965system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id
966system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937866 # Percentage of cache occupancy per task id
967system.cpu0.l2cache.tags.tag_accesses 91385031 # Number of tag accesses
968system.cpu0.l2cache.tags.data_accesses 91385031 # Number of data accesses
969system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
970system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77639 # number of ReadReq hits
971system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5220 # number of ReadReq hits
972system.cpu0.l2cache.ReadReq_hits::total 82859 # number of ReadReq hits
973system.cpu0.l2cache.WritebackDirty_hits::writebacks 481305 # number of WritebackDirty hits
974system.cpu0.l2cache.WritebackDirty_hits::total 481305 # number of WritebackDirty hits
975system.cpu0.l2cache.WritebackClean_hits::writebacks 2156745 # number of WritebackClean hits
976system.cpu0.l2cache.WritebackClean_hits::total 2156745 # number of WritebackClean hits
977system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222879 # number of ReadExReq hits
978system.cpu0.l2cache.ReadExReq_hits::total 222879 # number of ReadExReq hits
979system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1872794 # number of ReadCleanReq hits
980system.cpu0.l2cache.ReadCleanReq_hits::total 1872794 # number of ReadCleanReq hits
981system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 388786 # number of ReadSharedReq hits
982system.cpu0.l2cache.ReadSharedReq_hits::total 388786 # number of ReadSharedReq hits
983system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77639 # number of demand (read+write) hits
984system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5220 # number of demand (read+write) hits
985system.cpu0.l2cache.demand_hits::cpu0.inst 1872794 # number of demand (read+write) hits
986system.cpu0.l2cache.demand_hits::cpu0.data 611665 # number of demand (read+write) hits
987system.cpu0.l2cache.demand_hits::total 2567318 # number of demand (read+write) hits
988system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77639 # number of overall hits
989system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5220 # number of overall hits
990system.cpu0.l2cache.overall_hits::cpu0.inst 1872794 # number of overall hits
991system.cpu0.l2cache.overall_hits::cpu0.data 611665 # number of overall hits
992system.cpu0.l2cache.overall_hits::total 2567318 # number of overall hits
993system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 934 # number of ReadReq misses
994system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 150 # number of ReadReq misses
995system.cpu0.l2cache.ReadReq_misses::total 1084 # number of ReadReq misses
996system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56829 # number of UpgradeReq misses
997system.cpu0.l2cache.UpgradeReq_misses::total 56829 # number of UpgradeReq misses
998system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20390 # number of SCUpgradeReq misses
999system.cpu0.l2cache.SCUpgradeReq_misses::total 20390 # number of SCUpgradeReq misses
1000system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
1001system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
1002system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45892 # number of ReadExReq misses
1003system.cpu0.l2cache.ReadExReq_misses::total 45892 # number of ReadExReq misses
1004system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 91807 # number of ReadCleanReq misses
1005system.cpu0.l2cache.ReadCleanReq_misses::total 91807 # number of ReadCleanReq misses
1006system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 113754 # number of ReadSharedReq misses
1007system.cpu0.l2cache.ReadSharedReq_misses::total 113754 # number of ReadSharedReq misses
1008system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 934 # number of demand (read+write) misses
1009system.cpu0.l2cache.demand_misses::cpu0.itb.walker 150 # number of demand (read+write) misses
1010system.cpu0.l2cache.demand_misses::cpu0.inst 91807 # number of demand (read+write) misses
1011system.cpu0.l2cache.demand_misses::cpu0.data 159646 # number of demand (read+write) misses
1012system.cpu0.l2cache.demand_misses::total 252537 # number of demand (read+write) misses
1013system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 934 # number of overall misses
1014system.cpu0.l2cache.overall_misses::cpu0.itb.walker 150 # number of overall misses
1015system.cpu0.l2cache.overall_misses::cpu0.inst 91807 # number of overall misses
1016system.cpu0.l2cache.overall_misses::cpu0.data 159646 # number of overall misses
1017system.cpu0.l2cache.overall_misses::total 252537 # number of overall misses
1018system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 44624500 # number of ReadReq miss cycles
1019system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3518000 # number of ReadReq miss cycles
1020system.cpu0.l2cache.ReadReq_miss_latency::total 48142500 # number of ReadReq miss cycles
1021system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 45750500 # number of UpgradeReq miss cycles
1022system.cpu0.l2cache.UpgradeReq_miss_latency::total 45750500 # number of UpgradeReq miss cycles
1023system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9568000 # number of SCUpgradeReq miss cycles
1024system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9568000 # number of SCUpgradeReq miss cycles
1025system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 607499 # number of SCUpgradeFailReq miss cycles
1026system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 607499 # number of SCUpgradeFailReq miss cycles
1027system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2923141000 # number of ReadExReq miss cycles
1028system.cpu0.l2cache.ReadExReq_miss_latency::total 2923141000 # number of ReadExReq miss cycles
1029system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4535079000 # number of ReadCleanReq miss cycles
1030system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4535079000 # number of ReadCleanReq miss cycles
1031system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3749547498 # number of ReadSharedReq miss cycles
1032system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3749547498 # number of ReadSharedReq miss cycles
1033system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 44624500 # number of demand (read+write) miss cycles
1034system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3518000 # number of demand (read+write) miss cycles
1035system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4535079000 # number of demand (read+write) miss cycles
1036system.cpu0.l2cache.demand_miss_latency::cpu0.data 6672688498 # number of demand (read+write) miss cycles
1037system.cpu0.l2cache.demand_miss_latency::total 11255909998 # number of demand (read+write) miss cycles
1038system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 44624500 # number of overall miss cycles
1039system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3518000 # number of overall miss cycles
1040system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4535079000 # number of overall miss cycles
1041system.cpu0.l2cache.overall_miss_latency::cpu0.data 6672688498 # number of overall miss cycles
1042system.cpu0.l2cache.overall_miss_latency::total 11255909998 # number of overall miss cycles
1043system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78573 # number of ReadReq accesses(hits+misses)
1044system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5370 # number of ReadReq accesses(hits+misses)
1045system.cpu0.l2cache.ReadReq_accesses::total 83943 # number of ReadReq accesses(hits+misses)
1046system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481305 # number of WritebackDirty accesses(hits+misses)
1047system.cpu0.l2cache.WritebackDirty_accesses::total 481305 # number of WritebackDirty accesses(hits+misses)
1048system.cpu0.l2cache.WritebackClean_accesses::writebacks 2156745 # number of WritebackClean accesses(hits+misses)
1049system.cpu0.l2cache.WritebackClean_accesses::total 2156745 # number of WritebackClean accesses(hits+misses)
1050system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56829 # number of UpgradeReq accesses(hits+misses)
1051system.cpu0.l2cache.UpgradeReq_accesses::total 56829 # number of UpgradeReq accesses(hits+misses)
1052system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20390 # number of SCUpgradeReq accesses(hits+misses)
1053system.cpu0.l2cache.SCUpgradeReq_accesses::total 20390 # number of SCUpgradeReq accesses(hits+misses)
1054system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
1055system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
1056system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268771 # number of ReadExReq accesses(hits+misses)
1057system.cpu0.l2cache.ReadExReq_accesses::total 268771 # number of ReadExReq accesses(hits+misses)
1058system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1964601 # number of ReadCleanReq accesses(hits+misses)
1059system.cpu0.l2cache.ReadCleanReq_accesses::total 1964601 # number of ReadCleanReq accesses(hits+misses)
1060system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 502540 # number of ReadSharedReq accesses(hits+misses)
1061system.cpu0.l2cache.ReadSharedReq_accesses::total 502540 # number of ReadSharedReq accesses(hits+misses)
1062system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78573 # number of demand (read+write) accesses
1063system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5370 # number of demand (read+write) accesses
1064system.cpu0.l2cache.demand_accesses::cpu0.inst 1964601 # number of demand (read+write) accesses
1065system.cpu0.l2cache.demand_accesses::cpu0.data 771311 # number of demand (read+write) accesses
1066system.cpu0.l2cache.demand_accesses::total 2819855 # number of demand (read+write) accesses
1067system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78573 # number of overall (read+write) accesses
1068system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5370 # number of overall (read+write) accesses
1069system.cpu0.l2cache.overall_accesses::cpu0.inst 1964601 # number of overall (read+write) accesses
1070system.cpu0.l2cache.overall_accesses::cpu0.data 771311 # number of overall (read+write) accesses
1071system.cpu0.l2cache.overall_accesses::total 2819855 # number of overall (read+write) accesses
1072system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.011887 # miss rate for ReadReq accesses
1073system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027933 # miss rate for ReadReq accesses
1074system.cpu0.l2cache.ReadReq_miss_rate::total 0.012914 # miss rate for ReadReq accesses
1075system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1076system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1077system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1078system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1079system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1080system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1081system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.170748 # miss rate for ReadExReq accesses
1082system.cpu0.l2cache.ReadExReq_miss_rate::total 0.170748 # miss rate for ReadExReq accesses
1083system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046731 # miss rate for ReadCleanReq accesses
1084system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046731 # miss rate for ReadCleanReq accesses
1085system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.226358 # miss rate for ReadSharedReq accesses
1086system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.226358 # miss rate for ReadSharedReq accesses
1087system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.011887 # miss rate for demand accesses
1088system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027933 # miss rate for demand accesses
1089system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046731 # miss rate for demand accesses
1090system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.206980 # miss rate for demand accesses
1091system.cpu0.l2cache.demand_miss_rate::total 0.089557 # miss rate for demand accesses
1092system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.011887 # miss rate for overall accesses
1093system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027933 # miss rate for overall accesses
1094system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046731 # miss rate for overall accesses
1095system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.206980 # miss rate for overall accesses
1096system.cpu0.l2cache.overall_miss_rate::total 0.089557 # miss rate for overall accesses
1097system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47777.837259 # average ReadReq miss latency
1098system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23453.333333 # average ReadReq miss latency
1099system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44411.900369 # average ReadReq miss latency
1100system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 805.055517 # average UpgradeReq miss latency
1101system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 805.055517 # average UpgradeReq miss latency
1102system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 469.249632 # average SCUpgradeReq miss latency
1103system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 469.249632 # average SCUpgradeReq miss latency
1104system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 607499 # average SCUpgradeFailReq miss latency
1105system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 607499 # average SCUpgradeFailReq miss latency
1106system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63696.090822 # average ReadExReq miss latency
1107system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63696.090822 # average ReadExReq miss latency
1108system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49397.965297 # average ReadCleanReq miss latency
1109system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49397.965297 # average ReadCleanReq miss latency
1110system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32961.895828 # average ReadSharedReq miss latency
1111system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32961.895828 # average ReadSharedReq miss latency
1112system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47777.837259 # average overall miss latency
1113system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23453.333333 # average overall miss latency
1114system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49397.965297 # average overall miss latency
1115system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41796.778485 # average overall miss latency
1116system.cpu0.l2cache.demand_avg_miss_latency::total 44571.330134 # average overall miss latency
1117system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47777.837259 # average overall miss latency
1118system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23453.333333 # average overall miss latency
1119system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49397.965297 # average overall miss latency
1120system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41796.778485 # average overall miss latency
1121system.cpu0.l2cache.overall_avg_miss_latency::total 44571.330134 # average overall miss latency
1122system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1123system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1124system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1125system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1126system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1127system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1128system.cpu0.l2cache.unused_prefetches 10760 # number of HardPF blocks evicted w/o reference
1129system.cpu0.l2cache.writebacks::writebacks 232550 # number of writebacks
1130system.cpu0.l2cache.writebacks::total 232550 # number of writebacks
1131system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
1132system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
1133system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3193 # number of ReadExReq MSHR hits
1134system.cpu0.l2cache.ReadExReq_mshr_hits::total 3193 # number of ReadExReq MSHR hits
1135system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 56 # number of ReadCleanReq MSHR hits
1136system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 56 # number of ReadCleanReq MSHR hits
1137system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 400 # number of ReadSharedReq MSHR hits
1138system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 400 # number of ReadSharedReq MSHR hits
1139system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
1140system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 56 # number of demand (read+write) MSHR hits
1141system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3593 # number of demand (read+write) MSHR hits
1142system.cpu0.l2cache.demand_mshr_hits::total 3650 # number of demand (read+write) MSHR hits
1143system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
1144system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 56 # number of overall MSHR hits
1145system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3593 # number of overall MSHR hits
1146system.cpu0.l2cache.overall_mshr_hits::total 3650 # number of overall MSHR hits
1147system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 933 # number of ReadReq MSHR misses
1148system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 150 # number of ReadReq MSHR misses
1149system.cpu0.l2cache.ReadReq_mshr_misses::total 1083 # number of ReadReq MSHR misses
1150system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264017 # number of HardPFReq MSHR misses
1151system.cpu0.l2cache.HardPFReq_mshr_misses::total 264017 # number of HardPFReq MSHR misses
1152system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56829 # number of UpgradeReq MSHR misses
1153system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56829 # number of UpgradeReq MSHR misses
1154system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20390 # number of SCUpgradeReq MSHR misses
1155system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20390 # number of SCUpgradeReq MSHR misses
1156system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
1157system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
1158system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42699 # number of ReadExReq MSHR misses
1159system.cpu0.l2cache.ReadExReq_mshr_misses::total 42699 # number of ReadExReq MSHR misses
1160system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 91751 # number of ReadCleanReq MSHR misses
1161system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 91751 # number of ReadCleanReq MSHR misses
1162system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 113354 # number of ReadSharedReq MSHR misses
1163system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 113354 # number of ReadSharedReq MSHR misses
1164system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 933 # number of demand (read+write) MSHR misses
1165system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 150 # number of demand (read+write) MSHR misses
1166system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 91751 # number of demand (read+write) MSHR misses
1167system.cpu0.l2cache.demand_mshr_misses::cpu0.data 156053 # number of demand (read+write) MSHR misses
1168system.cpu0.l2cache.demand_mshr_misses::total 248887 # number of demand (read+write) MSHR misses
1169system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 933 # number of overall MSHR misses
1170system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 150 # number of overall MSHR misses
1171system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 91751 # number of overall MSHR misses
1172system.cpu0.l2cache.overall_mshr_misses::cpu0.data 156053 # number of overall MSHR misses
1173system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264017 # number of overall MSHR misses
1174system.cpu0.l2cache.overall_mshr_misses::total 512904 # number of overall MSHR misses
1175system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable
1176system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable
1177system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23854 # number of ReadReq MSHR uncacheable
1178system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable
1179system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable
1180system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses
1181system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39847 # number of overall MSHR uncacheable misses
1182system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43124 # number of overall MSHR uncacheable misses
1183system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 39007500 # number of ReadReq MSHR miss cycles
1184system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2618000 # number of ReadReq MSHR miss cycles
1185system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 41625500 # number of ReadReq MSHR miss cycles
1186system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16806240735 # number of HardPFReq MSHR miss cycles
1187system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16806240735 # number of HardPFReq MSHR miss cycles
1188system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 985974500 # number of UpgradeReq MSHR miss cycles
1189system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 985974500 # number of UpgradeReq MSHR miss cycles
1190system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 307077498 # number of SCUpgradeReq MSHR miss cycles
1191system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 307077498 # number of SCUpgradeReq MSHR miss cycles
1192system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 499499 # number of SCUpgradeFailReq MSHR miss cycles
1193system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 499499 # number of SCUpgradeFailReq MSHR miss cycles
1194system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2171871000 # number of ReadExReq MSHR miss cycles
1195system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2171871000 # number of ReadExReq MSHR miss cycles
1196system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3982642000 # number of ReadCleanReq MSHR miss cycles
1197system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3982642000 # number of ReadCleanReq MSHR miss cycles
1198system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3045418498 # number of ReadSharedReq MSHR miss cycles
1199system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3045418498 # number of ReadSharedReq MSHR miss cycles
1200system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 39007500 # number of demand (read+write) MSHR miss cycles
1201system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2618000 # number of demand (read+write) MSHR miss cycles
1202system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3982642000 # number of demand (read+write) MSHR miss cycles
1203system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5217289498 # number of demand (read+write) MSHR miss cycles
1204system.cpu0.l2cache.demand_mshr_miss_latency::total 9241556998 # number of demand (read+write) MSHR miss cycles
1205system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 39007500 # number of overall MSHR miss cycles
1206system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2618000 # number of overall MSHR miss cycles
1207system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3982642000 # number of overall MSHR miss cycles
1208system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5217289498 # number of overall MSHR miss cycles
1209system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16806240735 # number of overall MSHR miss cycles
1210system.cpu0.l2cache.overall_mshr_miss_latency::total 26047797733 # number of overall MSHR miss cycles
1211system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 297666000 # number of ReadReq MSHR uncacheable cycles
1212system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4441867000 # number of ReadReq MSHR uncacheable cycles
1213system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4739533000 # number of ReadReq MSHR uncacheable cycles
1214system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000 # number of overall MSHR uncacheable cycles
1215system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4441867000 # number of overall MSHR uncacheable cycles
1216system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4739533000 # number of overall MSHR uncacheable cycles
1217system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.011874 # mshr miss rate for ReadReq accesses
1218system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027933 # mshr miss rate for ReadReq accesses
1219system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.012902 # mshr miss rate for ReadReq accesses
1220system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1221system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1222system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1223system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1224system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1225system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1226system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1227system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1228system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158868 # mshr miss rate for ReadExReq accesses
1229system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158868 # mshr miss rate for ReadExReq accesses
1230system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046702 # mshr miss rate for ReadCleanReq accesses
1231system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046702 # mshr miss rate for ReadCleanReq accesses
1232system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.225562 # mshr miss rate for ReadSharedReq accesses
1233system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.225562 # mshr miss rate for ReadSharedReq accesses
1234system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.011874 # mshr miss rate for demand accesses
1235system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027933 # mshr miss rate for demand accesses
1236system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046702 # mshr miss rate for demand accesses
1237system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.202322 # mshr miss rate for demand accesses
1238system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088262 # mshr miss rate for demand accesses
1239system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.011874 # mshr miss rate for overall accesses
1240system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027933 # mshr miss rate for overall accesses
1241system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046702 # mshr miss rate for overall accesses
1242system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.202322 # mshr miss rate for overall accesses
1243system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1244system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181890 # mshr miss rate for overall accesses
1245system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average ReadReq mshr miss latency
1246system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average ReadReq mshr miss latency
1247system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38435.364728 # average ReadReq mshr miss latency
1248system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average HardPFReq mshr miss latency
1249system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63655.903730 # average HardPFReq mshr miss latency
1250system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17349.847789 # average UpgradeReq mshr miss latency
1251system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17349.847789 # average UpgradeReq mshr miss latency
1252system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15060.200981 # average SCUpgradeReq mshr miss latency
1253system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15060.200981 # average SCUpgradeReq mshr miss latency
1254system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 499499 # average SCUpgradeFailReq mshr miss latency
1255system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 499499 # average SCUpgradeFailReq mshr miss latency
1256system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50864.680672 # average ReadExReq mshr miss latency
1257system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.680672 # average ReadExReq mshr miss latency
1258system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average ReadCleanReq mshr miss latency
1259system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43407.069133 # average ReadCleanReq mshr miss latency
1260system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26866.440514 # average ReadSharedReq mshr miss latency
1261system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26866.440514 # average ReadSharedReq mshr miss latency
1262system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency
1263system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency
1264system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency
1265system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency
1266system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37131.537597 # average overall mshr miss latency
1267system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency
1268system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency
1269system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency
1270system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency
1271system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average overall mshr miss latency
1272system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50784.937791 # average overall mshr miss latency
1273system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency
1274system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215865.626671 # average ReadReq mshr uncacheable latency
1275system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198689.234510 # average ReadReq mshr uncacheable latency
1276system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency
1277system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111473.059452 # average overall mshr uncacheable latency
1278system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109904.763009 # average overall mshr uncacheable latency
1279system.cpu0.toL2Bus.snoop_filter.tot_requests 5514708 # Total number of requests made to the snoop filter.
1280system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2778846 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1281system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1282system.cpu0.toL2Bus.snoop_filter.tot_snoops 220650 # Total number of snoops made to the snoop filter.
1283system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216436 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1284system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4214 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1285system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1286system.cpu0.toL2Bus.trans_dist::ReadReq 117829 # Transaction distribution
1287system.cpu0.toL2Bus.trans_dist::ReadResp 2634124 # Transaction distribution
1288system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution
1289system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution
1290system.cpu0.toL2Bus.trans_dist::WritebackDirty 714129 # Transaction distribution
1291system.cpu0.toL2Bus.trans_dist::WritebackClean 2198813 # Transaction distribution
1292system.cpu0.toL2Bus.trans_dist::CleanEvict 105915 # Transaction distribution
1293system.cpu0.toL2Bus.trans_dist::HardPFReq 313152 # Transaction distribution
1294system.cpu0.toL2Bus.trans_dist::UpgradeReq 88836 # Transaction distribution
1295system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution
1296system.cpu0.toL2Bus.trans_dist::UpgradeResp 114292 # Transaction distribution
1297system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
1298system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution
1299system.cpu0.toL2Bus.trans_dist::ReadExReq 287887 # Transaction distribution
1300system.cpu0.toL2Bus.trans_dist::ReadExResp 284399 # Transaction distribution
1301system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1964601 # Transaction distribution
1302system.cpu0.toL2Bus.trans_dist::ReadSharedReq 602822 # Transaction distribution
1303system.cpu0.toL2Bus.trans_dist::InvalidateReq 3087 # Transaction distribution
1304system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5899831 # Packet count per connected master and slave (bytes)
1305system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2594741 # Packet count per connected master and slave (bytes)
1306system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13052 # Packet count per connected master and slave (bytes)
1307system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164810 # Packet count per connected master and slave (bytes)
1308system.cpu0.toL2Bus.pkt_count::total 8672434 # Packet count per connected master and slave (bytes)
1309system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251644992 # Cumulative packet size per connected master and slave (bytes)
1310system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99451448 # Cumulative packet size per connected master and slave (bytes)
1311system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21480 # Cumulative packet size per connected master and slave (bytes)
1312system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314292 # Cumulative packet size per connected master and slave (bytes)
1313system.cpu0.toL2Bus.pkt_size::total 351432212 # Cumulative packet size per connected master and slave (bytes)
1314system.cpu0.toL2Bus.snoops 940964 # Total snoops (count)
1315system.cpu0.toL2Bus.snoopTraffic 19090924 # Total snoop traffic (bytes)
1316system.cpu0.toL2Bus.snoop_fanout::samples 3779220 # Request fanout histogram
1317system.cpu0.toL2Bus.snoop_fanout::mean 0.076318 # Request fanout histogram
1318system.cpu0.toL2Bus.snoop_fanout::stdev 0.269673 # Request fanout histogram
1319system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1320system.cpu0.toL2Bus.snoop_fanout::0 3495013 92.48% 92.48% # Request fanout histogram
1321system.cpu0.toL2Bus.snoop_fanout::1 279993 7.41% 99.89% # Request fanout histogram
1322system.cpu0.toL2Bus.snoop_fanout::2 4214 0.11% 100.00% # Request fanout histogram
1323system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1324system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1325system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1326system.cpu0.toL2Bus.snoop_fanout::total 3779220 # Request fanout histogram
1327system.cpu0.toL2Bus.reqLayer0.occupancy 5504902494 # Layer occupancy (ticks)
1328system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1329system.cpu0.toL2Bus.snoopLayer0.occupancy 115882925 # Layer occupancy (ticks)
1330system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1331system.cpu0.toL2Bus.respLayer0.occupancy 2952081467 # Layer occupancy (ticks)
1332system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1333system.cpu0.toL2Bus.respLayer1.occupancy 1226789533 # Layer occupancy (ticks)
1334system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1335system.cpu0.toL2Bus.respLayer2.occupancy 7686990 # Layer occupancy (ticks)
1336system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1337system.cpu0.toL2Bus.respLayer3.occupancy 86252968 # Layer occupancy (ticks)
1338system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1339system.cpu1.branchPred.lookups 19393527 # Number of BP lookups
1340system.cpu1.branchPred.condPredicted 6185527 # Number of conditional branches predicted
1341system.cpu1.branchPred.condIncorrect 769783 # Number of conditional branches incorrect
1342system.cpu1.branchPred.BTBLookups 9956759 # Number of BTB lookups
1343system.cpu1.branchPred.BTBHits 3606289 # Number of BTB hits
1344system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1345system.cpu1.branchPred.BTBHitPct 36.219507 # BTB Hit Percentage
1346system.cpu1.branchPred.usedRAS 8702764 # Number of times the RAS was used to get a target.
1347system.cpu1.branchPred.RASInCorrect 566393 # Number of incorrect RAS predictions.
1348system.cpu1.branchPred.indirectLookups 3646067 # Number of indirect predictor lookups.
1349system.cpu1.branchPred.indirectHits 3582470 # Number of indirect target hits.
1350system.cpu1.branchPred.indirectMisses 63597 # Number of indirect misses.
1351system.cpu1.branchPredindirectMispredicted 23601 # Number of mispredicted indirect branches.
1352system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1353system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1354system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1355system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1356system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1357system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1358system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1359system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1360system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1374system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1375system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1376system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1377system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1378system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1379system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1380system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1381system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1382system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1383system.cpu1.dtb.walker.walks 26638 # Table walker walks requested
1384system.cpu1.dtb.walker.walksShort 26638 # Table walker walks initiated with short descriptors
1385system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20208 # Level at which table walker walks with short descriptors terminate
1386system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6430 # Level at which table walker walks with short descriptors terminate
1387system.cpu1.dtb.walker.walkWaitTime::samples 26638 # Table walker wait (enqueue to first request) latency
1388system.cpu1.dtb.walker.walkWaitTime::0 26638 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1389system.cpu1.dtb.walker.walkWaitTime::total 26638 # Table walker wait (enqueue to first request) latency
1390system.cpu1.dtb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency
1391system.cpu1.dtb.walker.walkCompletionTime::mean 12533.532042 # Table walker service (enqueue to completion) latency
1392system.cpu1.dtb.walker.walkCompletionTime::gmean 11490.379150 # Table walker service (enqueue to completion) latency
1393system.cpu1.dtb.walker.walkCompletionTime::stdev 8690.810286 # Table walker service (enqueue to completion) latency
1394system.cpu1.dtb.walker.walkCompletionTime::0-32767 2656 98.96% 98.96% # Table walker service (enqueue to completion) latency
1395system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26 0.97% 99.93% # Table walker service (enqueue to completion) latency
1396system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
1397system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
1398system.cpu1.dtb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency
1399system.cpu1.dtb.walker.walksPending::samples -1849661032 # Table walker pending requests distribution
1400system.cpu1.dtb.walker.walksPending::0 -1849661032 100.00% 100.00% # Table walker pending requests distribution
1401system.cpu1.dtb.walker.walksPending::total -1849661032 # Table walker pending requests distribution
1402system.cpu1.dtb.walker.walkPageSizes::4K 1998 74.44% 74.44% # Table walker page sizes translated
1403system.cpu1.dtb.walker.walkPageSizes::1M 686 25.56% 100.00% # Table walker page sizes translated
1404system.cpu1.dtb.walker.walkPageSizes::total 2684 # Table walker page sizes translated
1405system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26638 # Table walker requests started/completed, data/inst
1406system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1407system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26638 # Table walker requests started/completed, data/inst
1408system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2684 # Table walker requests started/completed, data/inst
1409system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1410system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst
1411system.cpu1.dtb.walker.walkRequestOrigin::total 29322 # Table walker requests started/completed, data/inst
1412system.cpu1.dtb.inst_hits 0 # ITB inst hits
1413system.cpu1.dtb.inst_misses 0 # ITB inst misses
1414system.cpu1.dtb.read_hits 11320530 # DTB read hits
1415system.cpu1.dtb.read_misses 24586 # DTB read misses
1416system.cpu1.dtb.write_hits 7061626 # DTB write hits
1417system.cpu1.dtb.write_misses 2052 # DTB write misses
1418system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1419system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1420system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1421system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1422system.cpu1.dtb.flush_entries 1992 # Number of entries that have been flushed from TLB
1423system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions
1424system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch
1425system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1426system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions
1427system.cpu1.dtb.read_accesses 11345116 # DTB read accesses
1428system.cpu1.dtb.write_accesses 7063678 # DTB write accesses
1429system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1430system.cpu1.dtb.hits 18382156 # DTB hits
1431system.cpu1.dtb.misses 26638 # DTB misses
1432system.cpu1.dtb.accesses 18408794 # DTB accesses
1433system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1434system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1435system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1436system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1437system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1438system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1439system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1440system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1441system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1455system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1456system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1457system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1458system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1459system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1460system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1461system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1462system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1463system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1464system.cpu1.itb.walker.walks 2499 # Table walker walks requested
1465system.cpu1.itb.walker.walksShort 2499 # Table walker walks initiated with short descriptors
1466system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate
1467system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2319 # Level at which table walker walks with short descriptors terminate
1468system.cpu1.itb.walker.walkWaitTime::samples 2499 # Table walker wait (enqueue to first request) latency
1469system.cpu1.itb.walker.walkWaitTime::0 2499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1470system.cpu1.itb.walker.walkWaitTime::total 2499 # Table walker wait (enqueue to first request) latency
1471system.cpu1.itb.walker.walkCompletionTime::samples 1128 # Table walker service (enqueue to completion) latency
1472system.cpu1.itb.walker.walkCompletionTime::mean 12699.024823 # Table walker service (enqueue to completion) latency
1473system.cpu1.itb.walker.walkCompletionTime::gmean 11989.496313 # Table walker service (enqueue to completion) latency
1474system.cpu1.itb.walker.walkCompletionTime::stdev 4984.320484 # Table walker service (enqueue to completion) latency
1475system.cpu1.itb.walker.walkCompletionTime::4096-8191 166 14.72% 14.72% # Table walker service (enqueue to completion) latency
1476system.cpu1.itb.walker.walkCompletionTime::8192-12287 634 56.21% 70.92% # Table walker service (enqueue to completion) latency
1477system.cpu1.itb.walker.walkCompletionTime::12288-16383 206 18.26% 89.18% # Table walker service (enqueue to completion) latency
1478system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.34% 93.53% # Table walker service (enqueue to completion) latency
1479system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 1.95% 95.48% # Table walker service (enqueue to completion) latency
1480system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.48% 97.96% # Table walker service (enqueue to completion) latency
1481system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.42% 99.38% # Table walker service (enqueue to completion) latency
1482system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.65% # Table walker service (enqueue to completion) latency
1483system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.18% 99.82% # Table walker service (enqueue to completion) latency
1484system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
1485system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
1486system.cpu1.itb.walker.walkCompletionTime::total 1128 # Table walker service (enqueue to completion) latency
1487system.cpu1.itb.walker.walksPending::samples -1850303532 # Table walker pending requests distribution
1488system.cpu1.itb.walker.walksPending::0 -1850303532 100.00% 100.00% # Table walker pending requests distribution
1489system.cpu1.itb.walker.walksPending::total -1850303532 # Table walker pending requests distribution
1490system.cpu1.itb.walker.walkPageSizes::4K 963 85.37% 85.37% # Table walker page sizes translated
1491system.cpu1.itb.walker.walkPageSizes::1M 165 14.63% 100.00% # Table walker page sizes translated
1492system.cpu1.itb.walker.walkPageSizes::total 1128 # Table walker page sizes translated
1493system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1494system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2499 # Table walker requests started/completed, data/inst
1495system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2499 # Table walker requests started/completed, data/inst
1496system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1497system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1128 # Table walker requests started/completed, data/inst
1498system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1128 # Table walker requests started/completed, data/inst
1499system.cpu1.itb.walker.walkRequestOrigin::total 3627 # Table walker requests started/completed, data/inst
1500system.cpu1.itb.inst_hits 39699373 # ITB inst hits
1501system.cpu1.itb.inst_misses 2499 # ITB inst misses
1502system.cpu1.itb.read_hits 0 # DTB read hits
1503system.cpu1.itb.read_misses 0 # DTB read misses
1504system.cpu1.itb.write_hits 0 # DTB write hits
1505system.cpu1.itb.write_misses 0 # DTB write misses
1506system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1507system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1508system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1509system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1510system.cpu1.itb.flush_entries 1101 # Number of entries that have been flushed from TLB
1511system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1512system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1513system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1514system.cpu1.itb.perms_faults 1838 # Number of TLB faults due to permissions restrictions
1515system.cpu1.itb.read_accesses 0 # DTB read accesses
1516system.cpu1.itb.write_accesses 0 # DTB write accesses
1517system.cpu1.itb.inst_accesses 39701872 # ITB inst accesses
1518system.cpu1.itb.hits 39699373 # DTB hits
1519system.cpu1.itb.misses 2499 # DTB misses
1520system.cpu1.itb.accesses 39701872 # DTB accesses
1521system.cpu1.numPwrStateTransitions 5523 # Number of power state transitions
1522system.cpu1.pwrStateClkGateDist::samples 2762 # Distribution of time spent in the clock gated state
1523system.cpu1.pwrStateClkGateDist::mean 1010212132.618392 # Distribution of time spent in the clock gated state
1524system.cpu1.pwrStateClkGateDist::stdev 25718871891.755051 # Distribution of time spent in the clock gated state
1525system.cpu1.pwrStateClkGateDist::underflows 1964 71.11% 71.11% # Distribution of time spent in the clock gated state
1526system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.75% 99.86% # Distribution of time spent in the clock gated state
1527system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
1528system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
1529system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
1530system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state
1531system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1532system.cpu1.pwrStateClkGateDist::max_value 949979704076 # Distribution of time spent in the clock gated state
1533system.cpu1.pwrStateClkGateDist::total 2762 # Distribution of time spent in the clock gated state
1534system.cpu1.pwrStateResidencyTicks::ON 58720807708 # Cumulative time (in ticks) in various power states
1535system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790205910292 # Cumulative time (in ticks) in various power states
1536system.cpu1.numCycles 117445100 # number of cpu cycles simulated
1537system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1538system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1539system.cpu1.committedInsts 48204911 # Number of instructions committed
1540system.cpu1.committedOps 58981541 # Number of ops (including micro ops) committed
1541system.cpu1.discardedOps 5132548 # Number of ops (including micro ops) which were discarded before commit
1542system.cpu1.numFetchSuspends 2762 # Number of times Execute suspended instruction fetching
1543system.cpu1.quiesceCycles 5579768700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1544system.cpu1.cpi 2.436372 # CPI: cycles per instruction
1545system.cpu1.ipc 0.410446 # IPC: instructions per cycle
1546system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction
1547system.cpu1.op_class_0::IntAlu 40607989 68.85% 68.85% # Class of committed instruction
1548system.cpu1.op_class_0::IntMult 45709 0.08% 68.93% # Class of committed instruction
1549system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction
1550system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction
1551system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction
1552system.cpu1.op_class_0::FloatCvt 0 0.00% 68.93% # Class of committed instruction
1553system.cpu1.op_class_0::FloatMult 0 0.00% 68.93% # Class of committed instruction
1554system.cpu1.op_class_0::FloatMultAcc 0 0.00% 68.93% # Class of committed instruction
1555system.cpu1.op_class_0::FloatDiv 0 0.00% 68.93% # Class of committed instruction
1556system.cpu1.op_class_0::FloatMisc 0 0.00% 68.93% # Class of committed instruction

--- 9 unchanged lines hidden (view full) ---

1566system.cpu1.op_class_0::SimdShift 0 0.00% 68.93% # Class of committed instruction
1567system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.93% # Class of committed instruction
1568system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.93% # Class of committed instruction
1569system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.93% # Class of committed instruction
1570system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Class of committed instruction
1571system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction
1572system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction
1573system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction
1574system.cpu1.op_class_0::SimdFloatMisc 3353 0.01% 68.93% # Class of committed instruction
1575system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.93% # Class of committed instruction
1576system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.93% # Class of committed instruction
1577system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.93% # Class of committed instruction
1578system.cpu1.op_class_0::MemRead 11146731 18.90% 87.83% # Class of committed instruction
1579system.cpu1.op_class_0::MemWrite 7175909 12.17% 100.00% # Class of committed instruction
1580system.cpu1.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction
1581system.cpu1.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction
1582system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1583system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1584system.cpu1.op_class_0::total 58981541 # Class of committed instruction
1585system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1586system.cpu1.kern.inst.quiesce 2762 # number of quiesce instructions executed
1587system.cpu1.tickCycles 94223774 # Number of cycles that the object actually ticked
1588system.cpu1.idleCycles 23221326 # Total number of cycles that the object has spent stopped
1589system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1590system.cpu1.dcache.tags.replacements 197231 # number of replacements
1591system.cpu1.dcache.tags.tagsinuse 476.160023 # Cycle average of tags in use
1592system.cpu1.dcache.tags.total_refs 17961880 # Total number of references to valid blocks.
1593system.cpu1.dcache.tags.sampled_refs 197583 # Sample count of references to valid blocks.
1594system.cpu1.dcache.tags.avg_refs 90.908023 # Average number of references to valid blocks.
1595system.cpu1.dcache.tags.warmup_cycle 91326739500 # Cycle when the warmup percentage was hit.
1596system.cpu1.dcache.tags.occ_blocks::cpu1.data 476.160023 # Average occupied blocks per requestor
1597system.cpu1.dcache.tags.occ_percent::cpu1.data 0.930000 # Average percentage of cache occupancy
1598system.cpu1.dcache.tags.occ_percent::total 0.930000 # Average percentage of cache occupancy
1599system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id
1600system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
1601system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id
1602system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
1603system.cpu1.dcache.tags.tag_accesses 36815018 # Number of tag accesses
1604system.cpu1.dcache.tags.data_accesses 36815018 # Number of data accesses
1605system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1606system.cpu1.dcache.ReadReq_hits::cpu1.data 10942799 # number of ReadReq hits
1607system.cpu1.dcache.ReadReq_hits::total 10942799 # number of ReadReq hits
1608system.cpu1.dcache.WriteReq_hits::cpu1.data 6773317 # number of WriteReq hits
1609system.cpu1.dcache.WriteReq_hits::total 6773317 # number of WriteReq hits
1610system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50710 # number of SoftPFReq hits
1611system.cpu1.dcache.SoftPFReq_hits::total 50710 # number of SoftPFReq hits
1612system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80304 # number of LoadLockedReq hits
1613system.cpu1.dcache.LoadLockedReq_hits::total 80304 # number of LoadLockedReq hits
1614system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71747 # number of StoreCondReq hits
1615system.cpu1.dcache.StoreCondReq_hits::total 71747 # number of StoreCondReq hits
1616system.cpu1.dcache.demand_hits::cpu1.data 17716116 # number of demand (read+write) hits
1617system.cpu1.dcache.demand_hits::total 17716116 # number of demand (read+write) hits
1618system.cpu1.dcache.overall_hits::cpu1.data 17766826 # number of overall hits
1619system.cpu1.dcache.overall_hits::total 17766826 # number of overall hits
1620system.cpu1.dcache.ReadReq_misses::cpu1.data 150509 # number of ReadReq misses
1621system.cpu1.dcache.ReadReq_misses::total 150509 # number of ReadReq misses
1622system.cpu1.dcache.WriteReq_misses::cpu1.data 145770 # number of WriteReq misses
1623system.cpu1.dcache.WriteReq_misses::total 145770 # number of WriteReq misses
1624system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30651 # number of SoftPFReq misses
1625system.cpu1.dcache.SoftPFReq_misses::total 30651 # number of SoftPFReq misses
1626system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses
1627system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses
1628system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23697 # number of StoreCondReq misses
1629system.cpu1.dcache.StoreCondReq_misses::total 23697 # number of StoreCondReq misses
1630system.cpu1.dcache.demand_misses::cpu1.data 296279 # number of demand (read+write) misses
1631system.cpu1.dcache.demand_misses::total 296279 # number of demand (read+write) misses
1632system.cpu1.dcache.overall_misses::cpu1.data 326930 # number of overall misses
1633system.cpu1.dcache.overall_misses::total 326930 # number of overall misses
1634system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2503108000 # number of ReadReq miss cycles
1635system.cpu1.dcache.ReadReq_miss_latency::total 2503108000 # number of ReadReq miss cycles
1636system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4131089000 # number of WriteReq miss cycles
1637system.cpu1.dcache.WriteReq_miss_latency::total 4131089000 # number of WriteReq miss cycles
1638system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325863000 # number of LoadLockedReq miss cycles
1639system.cpu1.dcache.LoadLockedReq_miss_latency::total 325863000 # number of LoadLockedReq miss cycles
1640system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557327500 # number of StoreCondReq miss cycles
1641system.cpu1.dcache.StoreCondReq_miss_latency::total 557327500 # number of StoreCondReq miss cycles
1642system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 612000 # number of StoreCondFailReq miss cycles
1643system.cpu1.dcache.StoreCondFailReq_miss_latency::total 612000 # number of StoreCondFailReq miss cycles
1644system.cpu1.dcache.demand_miss_latency::cpu1.data 6634197000 # number of demand (read+write) miss cycles
1645system.cpu1.dcache.demand_miss_latency::total 6634197000 # number of demand (read+write) miss cycles
1646system.cpu1.dcache.overall_miss_latency::cpu1.data 6634197000 # number of overall miss cycles
1647system.cpu1.dcache.overall_miss_latency::total 6634197000 # number of overall miss cycles
1648system.cpu1.dcache.ReadReq_accesses::cpu1.data 11093308 # number of ReadReq accesses(hits+misses)
1649system.cpu1.dcache.ReadReq_accesses::total 11093308 # number of ReadReq accesses(hits+misses)
1650system.cpu1.dcache.WriteReq_accesses::cpu1.data 6919087 # number of WriteReq accesses(hits+misses)
1651system.cpu1.dcache.WriteReq_accesses::total 6919087 # number of WriteReq accesses(hits+misses)
1652system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81361 # number of SoftPFReq accesses(hits+misses)
1653system.cpu1.dcache.SoftPFReq_accesses::total 81361 # number of SoftPFReq accesses(hits+misses)
1654system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97264 # number of LoadLockedReq accesses(hits+misses)
1655system.cpu1.dcache.LoadLockedReq_accesses::total 97264 # number of LoadLockedReq accesses(hits+misses)
1656system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95444 # number of StoreCondReq accesses(hits+misses)
1657system.cpu1.dcache.StoreCondReq_accesses::total 95444 # number of StoreCondReq accesses(hits+misses)
1658system.cpu1.dcache.demand_accesses::cpu1.data 18012395 # number of demand (read+write) accesses
1659system.cpu1.dcache.demand_accesses::total 18012395 # number of demand (read+write) accesses
1660system.cpu1.dcache.overall_accesses::cpu1.data 18093756 # number of overall (read+write) accesses
1661system.cpu1.dcache.overall_accesses::total 18093756 # number of overall (read+write) accesses
1662system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013568 # miss rate for ReadReq accesses
1663system.cpu1.dcache.ReadReq_miss_rate::total 0.013568 # miss rate for ReadReq accesses
1664system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021068 # miss rate for WriteReq accesses
1665system.cpu1.dcache.WriteReq_miss_rate::total 0.021068 # miss rate for WriteReq accesses
1666system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.376728 # miss rate for SoftPFReq accesses
1667system.cpu1.dcache.SoftPFReq_miss_rate::total 0.376728 # miss rate for SoftPFReq accesses
1668system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174371 # miss rate for LoadLockedReq accesses
1669system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174371 # miss rate for LoadLockedReq accesses
1670system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248282 # miss rate for StoreCondReq accesses
1671system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248282 # miss rate for StoreCondReq accesses
1672system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016449 # miss rate for demand accesses
1673system.cpu1.dcache.demand_miss_rate::total 0.016449 # miss rate for demand accesses
1674system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018069 # miss rate for overall accesses
1675system.cpu1.dcache.overall_miss_rate::total 0.018069 # miss rate for overall accesses
1676system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16630.952302 # average ReadReq miss latency
1677system.cpu1.dcache.ReadReq_avg_miss_latency::total 16630.952302 # average ReadReq miss latency
1678system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28339.774988 # average WriteReq miss latency
1679system.cpu1.dcache.WriteReq_avg_miss_latency::total 28339.774988 # average WriteReq miss latency
1680system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19213.620283 # average LoadLockedReq miss latency
1681system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19213.620283 # average LoadLockedReq miss latency
1682system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23518.905347 # average StoreCondReq miss latency
1683system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23518.905347 # average StoreCondReq miss latency
1684system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1685system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1686system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22391.721992 # average overall miss latency
1687system.cpu1.dcache.demand_avg_miss_latency::total 22391.721992 # average overall miss latency
1688system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20292.408161 # average overall miss latency
1689system.cpu1.dcache.overall_avg_miss_latency::total 20292.408161 # average overall miss latency
1690system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1691system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1692system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1693system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1694system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1695system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1696system.cpu1.dcache.writebacks::writebacks 197231 # number of writebacks
1697system.cpu1.dcache.writebacks::total 197231 # number of writebacks
1698system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5831 # number of ReadReq MSHR hits
1699system.cpu1.dcache.ReadReq_mshr_hits::total 5831 # number of ReadReq MSHR hits
1700system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53065 # number of WriteReq MSHR hits
1701system.cpu1.dcache.WriteReq_mshr_hits::total 53065 # number of WriteReq MSHR hits
1702system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12062 # number of LoadLockedReq MSHR hits
1703system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12062 # number of LoadLockedReq MSHR hits
1704system.cpu1.dcache.demand_mshr_hits::cpu1.data 58896 # number of demand (read+write) MSHR hits
1705system.cpu1.dcache.demand_mshr_hits::total 58896 # number of demand (read+write) MSHR hits
1706system.cpu1.dcache.overall_mshr_hits::cpu1.data 58896 # number of overall MSHR hits
1707system.cpu1.dcache.overall_mshr_hits::total 58896 # number of overall MSHR hits
1708system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144678 # number of ReadReq MSHR misses
1709system.cpu1.dcache.ReadReq_mshr_misses::total 144678 # number of ReadReq MSHR misses
1710system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92705 # number of WriteReq MSHR misses
1711system.cpu1.dcache.WriteReq_mshr_misses::total 92705 # number of WriteReq MSHR misses
1712system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29814 # number of SoftPFReq MSHR misses
1713system.cpu1.dcache.SoftPFReq_mshr_misses::total 29814 # number of SoftPFReq MSHR misses
1714system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4898 # number of LoadLockedReq MSHR misses
1715system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4898 # number of LoadLockedReq MSHR misses
1716system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23697 # number of StoreCondReq MSHR misses
1717system.cpu1.dcache.StoreCondReq_mshr_misses::total 23697 # number of StoreCondReq MSHR misses
1718system.cpu1.dcache.demand_mshr_misses::cpu1.data 237383 # number of demand (read+write) MSHR misses
1719system.cpu1.dcache.demand_mshr_misses::total 237383 # number of demand (read+write) MSHR misses
1720system.cpu1.dcache.overall_mshr_misses::cpu1.data 267197 # number of overall MSHR misses
1721system.cpu1.dcache.overall_mshr_misses::total 267197 # number of overall MSHR misses
1722system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14423 # number of ReadReq MSHR uncacheable
1723system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14423 # number of ReadReq MSHR uncacheable
1724system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11756 # number of WriteReq MSHR uncacheable
1725system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11756 # number of WriteReq MSHR uncacheable
1726system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses
1727system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26179 # number of overall MSHR uncacheable misses
1728system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2254716500 # number of ReadReq MSHR miss cycles
1729system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2254716500 # number of ReadReq MSHR miss cycles
1730system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2475419500 # number of WriteReq MSHR miss cycles
1731system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2475419500 # number of WriteReq MSHR miss cycles
1732system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 516532000 # number of SoftPFReq MSHR miss cycles
1733system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 516532000 # number of SoftPFReq MSHR miss cycles
1734system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86654500 # number of LoadLockedReq MSHR miss cycles
1735system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86654500 # number of LoadLockedReq MSHR miss cycles
1736system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533644500 # number of StoreCondReq MSHR miss cycles
1737system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533644500 # number of StoreCondReq MSHR miss cycles
1738system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 598000 # number of StoreCondFailReq MSHR miss cycles
1739system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 598000 # number of StoreCondFailReq MSHR miss cycles
1740system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4730136000 # number of demand (read+write) MSHR miss cycles
1741system.cpu1.dcache.demand_mshr_miss_latency::total 4730136000 # number of demand (read+write) MSHR miss cycles
1742system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5246668000 # number of overall MSHR miss cycles
1743system.cpu1.dcache.overall_mshr_miss_latency::total 5246668000 # number of overall MSHR miss cycles
1744system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2493280000 # number of ReadReq MSHR uncacheable cycles
1745system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2493280000 # number of ReadReq MSHR uncacheable cycles
1746system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2493280000 # number of overall MSHR uncacheable cycles
1747system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2493280000 # number of overall MSHR uncacheable cycles
1748system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013042 # mshr miss rate for ReadReq accesses
1749system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013042 # mshr miss rate for ReadReq accesses
1750system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013398 # mshr miss rate for WriteReq accesses
1751system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013398 # mshr miss rate for WriteReq accesses
1752system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.366441 # mshr miss rate for SoftPFReq accesses
1753system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.366441 # mshr miss rate for SoftPFReq accesses
1754system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050358 # mshr miss rate for LoadLockedReq accesses
1755system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050358 # mshr miss rate for LoadLockedReq accesses
1756system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248282 # mshr miss rate for StoreCondReq accesses
1757system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248282 # mshr miss rate for StoreCondReq accesses
1758system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013179 # mshr miss rate for demand accesses
1759system.cpu1.dcache.demand_mshr_miss_rate::total 0.013179 # mshr miss rate for demand accesses
1760system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014767 # mshr miss rate for overall accesses
1761system.cpu1.dcache.overall_mshr_miss_rate::total 0.014767 # mshr miss rate for overall accesses
1762system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15584.377030 # average ReadReq mshr miss latency
1763system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15584.377030 # average ReadReq mshr miss latency
1764system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26702.114233 # average WriteReq mshr miss latency
1765system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26702.114233 # average WriteReq mshr miss latency
1766system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17325.149259 # average SoftPFReq mshr miss latency
1767system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17325.149259 # average SoftPFReq mshr miss latency
1768system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17691.812985 # average LoadLockedReq mshr miss latency
1769system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17691.812985 # average LoadLockedReq mshr miss latency
1770system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22519.496139 # average StoreCondReq mshr miss latency
1771system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22519.496139 # average StoreCondReq mshr miss latency
1772system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1773system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1774system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19926.178370 # average overall mshr miss latency
1775system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19926.178370 # average overall mshr miss latency
1776system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19635.953996 # average overall mshr miss latency
1777system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19635.953996 # average overall mshr miss latency
1778system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172868.335298 # average ReadReq mshr uncacheable latency
1779system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172868.335298 # average ReadReq mshr uncacheable latency
1780system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.695939 # average overall mshr uncacheable latency
1781system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95239.695939 # average overall mshr uncacheable latency
1782system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1783system.cpu1.icache.tags.replacements 951926 # number of replacements
1784system.cpu1.icache.tags.tagsinuse 499.186802 # Cycle average of tags in use
1785system.cpu1.icache.tags.total_refs 38745002 # Total number of references to valid blocks.
1786system.cpu1.icache.tags.sampled_refs 952438 # Sample count of references to valid blocks.
1787system.cpu1.icache.tags.avg_refs 40.679815 # Average number of references to valid blocks.
1788system.cpu1.icache.tags.warmup_cycle 73025806000 # Cycle when the warmup percentage was hit.
1789system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.186802 # Average occupied blocks per requestor
1790system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974974 # Average percentage of cache occupancy
1791system.cpu1.icache.tags.occ_percent::total 0.974974 # Average percentage of cache occupancy
1792system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1793system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id
1794system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id
1795system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1796system.cpu1.icache.tags.tag_accesses 80347318 # Number of tag accesses
1797system.cpu1.icache.tags.data_accesses 80347318 # Number of data accesses
1798system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1799system.cpu1.icache.ReadReq_hits::cpu1.inst 38745002 # number of ReadReq hits
1800system.cpu1.icache.ReadReq_hits::total 38745002 # number of ReadReq hits
1801system.cpu1.icache.demand_hits::cpu1.inst 38745002 # number of demand (read+write) hits
1802system.cpu1.icache.demand_hits::total 38745002 # number of demand (read+write) hits
1803system.cpu1.icache.overall_hits::cpu1.inst 38745002 # number of overall hits
1804system.cpu1.icache.overall_hits::total 38745002 # number of overall hits
1805system.cpu1.icache.ReadReq_misses::cpu1.inst 952438 # number of ReadReq misses
1806system.cpu1.icache.ReadReq_misses::total 952438 # number of ReadReq misses
1807system.cpu1.icache.demand_misses::cpu1.inst 952438 # number of demand (read+write) misses
1808system.cpu1.icache.demand_misses::total 952438 # number of demand (read+write) misses
1809system.cpu1.icache.overall_misses::cpu1.inst 952438 # number of overall misses
1810system.cpu1.icache.overall_misses::total 952438 # number of overall misses
1811system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8816320000 # number of ReadReq miss cycles
1812system.cpu1.icache.ReadReq_miss_latency::total 8816320000 # number of ReadReq miss cycles
1813system.cpu1.icache.demand_miss_latency::cpu1.inst 8816320000 # number of demand (read+write) miss cycles
1814system.cpu1.icache.demand_miss_latency::total 8816320000 # number of demand (read+write) miss cycles
1815system.cpu1.icache.overall_miss_latency::cpu1.inst 8816320000 # number of overall miss cycles
1816system.cpu1.icache.overall_miss_latency::total 8816320000 # number of overall miss cycles
1817system.cpu1.icache.ReadReq_accesses::cpu1.inst 39697440 # number of ReadReq accesses(hits+misses)
1818system.cpu1.icache.ReadReq_accesses::total 39697440 # number of ReadReq accesses(hits+misses)
1819system.cpu1.icache.demand_accesses::cpu1.inst 39697440 # number of demand (read+write) accesses
1820system.cpu1.icache.demand_accesses::total 39697440 # number of demand (read+write) accesses
1821system.cpu1.icache.overall_accesses::cpu1.inst 39697440 # number of overall (read+write) accesses
1822system.cpu1.icache.overall_accesses::total 39697440 # number of overall (read+write) accesses
1823system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023992 # miss rate for ReadReq accesses
1824system.cpu1.icache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses
1825system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023992 # miss rate for demand accesses
1826system.cpu1.icache.demand_miss_rate::total 0.023992 # miss rate for demand accesses
1827system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023992 # miss rate for overall accesses
1828system.cpu1.icache.overall_miss_rate::total 0.023992 # miss rate for overall accesses
1829system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.581531 # average ReadReq miss latency
1830system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.581531 # average ReadReq miss latency
1831system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.581531 # average overall miss latency
1832system.cpu1.icache.demand_avg_miss_latency::total 9256.581531 # average overall miss latency
1833system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9256.581531 # average overall miss latency
1834system.cpu1.icache.overall_avg_miss_latency::total 9256.581531 # average overall miss latency
1835system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1836system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1837system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1838system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1839system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1840system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1841system.cpu1.icache.writebacks::writebacks 951926 # number of writebacks
1842system.cpu1.icache.writebacks::total 951926 # number of writebacks
1843system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 952438 # number of ReadReq MSHR misses
1844system.cpu1.icache.ReadReq_mshr_misses::total 952438 # number of ReadReq MSHR misses
1845system.cpu1.icache.demand_mshr_misses::cpu1.inst 952438 # number of demand (read+write) MSHR misses
1846system.cpu1.icache.demand_mshr_misses::total 952438 # number of demand (read+write) MSHR misses
1847system.cpu1.icache.overall_mshr_misses::cpu1.inst 952438 # number of overall MSHR misses
1848system.cpu1.icache.overall_mshr_misses::total 952438 # number of overall MSHR misses
1849system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
1850system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable
1851system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
1852system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses
1853system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8340101000 # number of ReadReq MSHR miss cycles
1854system.cpu1.icache.ReadReq_mshr_miss_latency::total 8340101000 # number of ReadReq MSHR miss cycles
1855system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8340101000 # number of demand (read+write) MSHR miss cycles
1856system.cpu1.icache.demand_mshr_miss_latency::total 8340101000 # number of demand (read+write) MSHR miss cycles
1857system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8340101000 # number of overall MSHR miss cycles
1858system.cpu1.icache.overall_mshr_miss_latency::total 8340101000 # number of overall MSHR miss cycles
1859system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11130500 # number of ReadReq MSHR uncacheable cycles
1860system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11130500 # number of ReadReq MSHR uncacheable cycles
1861system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11130500 # number of overall MSHR uncacheable cycles
1862system.cpu1.icache.overall_mshr_uncacheable_latency::total 11130500 # number of overall MSHR uncacheable cycles
1863system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for ReadReq accesses
1864system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses
1865system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for demand accesses
1866system.cpu1.icache.demand_mshr_miss_rate::total 0.023992 # mshr miss rate for demand accesses
1867system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for overall accesses
1868system.cpu1.icache.overall_mshr_miss_rate::total 0.023992 # mshr miss rate for overall accesses
1869system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average ReadReq mshr miss latency
1870system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.581531 # average ReadReq mshr miss latency
1871system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average overall mshr miss latency
1872system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.581531 # average overall mshr miss latency
1873system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average overall mshr miss latency
1874system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.581531 # average overall mshr miss latency
1875system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286 # average ReadReq mshr uncacheable latency
1876system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99379.464286 # average ReadReq mshr uncacheable latency
1877system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286 # average overall mshr uncacheable latency
1878system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99379.464286 # average overall mshr uncacheable latency
1879system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1880system.cpu1.l2cache.prefetcher.num_hwpf_issued 201450 # number of hwpf issued
1881system.cpu1.l2cache.prefetcher.pfIdentified 201482 # number of prefetch candidates identified
1882system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue
1883system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1884system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1885system.cpu1.l2cache.prefetcher.pfSpanPage 57990 # number of prefetches not generated due to page crossing
1886system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1887system.cpu1.l2cache.tags.replacements 53299 # number of replacements
1888system.cpu1.l2cache.tags.tagsinuse 14769.496108 # Cycle average of tags in use
1889system.cpu1.l2cache.tags.total_refs 1064390 # Total number of references to valid blocks.
1890system.cpu1.l2cache.tags.sampled_refs 67600 # Sample count of references to valid blocks.
1891system.cpu1.l2cache.tags.avg_refs 15.745414 # Average number of references to valid blocks.
1892system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1893system.cpu1.l2cache.tags.occ_blocks::writebacks 14396.977583 # Average occupied blocks per requestor
1894system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.648393 # Average occupied blocks per requestor
1895system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.118214 # Average occupied blocks per requestor
1896system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 333.751919 # Average occupied blocks per requestor
1897system.cpu1.l2cache.tags.occ_percent::writebacks 0.878722 # Average percentage of cache occupancy
1898system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002359 # Average percentage of cache occupancy
1899system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy
1900system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.020371 # Average percentage of cache occupancy
1901system.cpu1.l2cache.tags.occ_percent::total 0.901459 # Average percentage of cache occupancy
1902system.cpu1.l2cache.tags.occ_task_id_blocks::1022 279 # Occupied blocks per task id
1903system.cpu1.l2cache.tags.occ_task_id_blocks::1023 41 # Occupied blocks per task id
1904system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13981 # Occupied blocks per task id
1905system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id
1906system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 82 # Occupied blocks per task id
1907system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 194 # Occupied blocks per task id
1908system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
1909system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id
1910system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
1911system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1305 # Occupied blocks per task id
1912system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7821 # Occupied blocks per task id
1913system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4855 # Occupied blocks per task id
1914system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017029 # Percentage of cache occupancy per task id
1915system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002502 # Percentage of cache occupancy per task id
1916system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.853333 # Percentage of cache occupancy per task id
1917system.cpu1.l2cache.tags.tag_accesses 39716759 # Number of tag accesses
1918system.cpu1.l2cache.tags.data_accesses 39716759 # Number of data accesses
1919system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
1920system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29141 # number of ReadReq hits
1921system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3302 # number of ReadReq hits
1922system.cpu1.l2cache.ReadReq_hits::total 32443 # number of ReadReq hits
1923system.cpu1.l2cache.WritebackDirty_hits::writebacks 117742 # number of WritebackDirty hits
1924system.cpu1.l2cache.WritebackDirty_hits::total 117742 # number of WritebackDirty hits
1925system.cpu1.l2cache.WritebackClean_hits::writebacks 1011389 # number of WritebackClean hits
1926system.cpu1.l2cache.WritebackClean_hits::total 1011389 # number of WritebackClean hits
1927system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27835 # number of ReadExReq hits
1928system.cpu1.l2cache.ReadExReq_hits::total 27835 # number of ReadExReq hits
1929system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 916991 # number of ReadCleanReq hits
1930system.cpu1.l2cache.ReadCleanReq_hits::total 916991 # number of ReadCleanReq hits
1931system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 103815 # number of ReadSharedReq hits
1932system.cpu1.l2cache.ReadSharedReq_hits::total 103815 # number of ReadSharedReq hits
1933system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29141 # number of demand (read+write) hits
1934system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3302 # number of demand (read+write) hits
1935system.cpu1.l2cache.demand_hits::cpu1.inst 916991 # number of demand (read+write) hits
1936system.cpu1.l2cache.demand_hits::cpu1.data 131650 # number of demand (read+write) hits
1937system.cpu1.l2cache.demand_hits::total 1081084 # number of demand (read+write) hits
1938system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29141 # number of overall hits
1939system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3302 # number of overall hits
1940system.cpu1.l2cache.overall_hits::cpu1.inst 916991 # number of overall hits
1941system.cpu1.l2cache.overall_hits::cpu1.data 131650 # number of overall hits
1942system.cpu1.l2cache.overall_hits::total 1081084 # number of overall hits
1943system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 704 # number of ReadReq misses
1944system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 285 # number of ReadReq misses
1945system.cpu1.l2cache.ReadReq_misses::total 989 # number of ReadReq misses
1946system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 30019 # number of UpgradeReq misses
1947system.cpu1.l2cache.UpgradeReq_misses::total 30019 # number of UpgradeReq misses
1948system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23697 # number of SCUpgradeReq misses
1949system.cpu1.l2cache.SCUpgradeReq_misses::total 23697 # number of SCUpgradeReq misses
1950system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34851 # number of ReadExReq misses
1951system.cpu1.l2cache.ReadExReq_misses::total 34851 # number of ReadExReq misses
1952system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 35447 # number of ReadCleanReq misses
1953system.cpu1.l2cache.ReadCleanReq_misses::total 35447 # number of ReadCleanReq misses
1954system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75575 # number of ReadSharedReq misses
1955system.cpu1.l2cache.ReadSharedReq_misses::total 75575 # number of ReadSharedReq misses
1956system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 704 # number of demand (read+write) misses
1957system.cpu1.l2cache.demand_misses::cpu1.itb.walker 285 # number of demand (read+write) misses
1958system.cpu1.l2cache.demand_misses::cpu1.inst 35447 # number of demand (read+write) misses
1959system.cpu1.l2cache.demand_misses::cpu1.data 110426 # number of demand (read+write) misses
1960system.cpu1.l2cache.demand_misses::total 146862 # number of demand (read+write) misses
1961system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 704 # number of overall misses
1962system.cpu1.l2cache.overall_misses::cpu1.itb.walker 285 # number of overall misses
1963system.cpu1.l2cache.overall_misses::cpu1.inst 35447 # number of overall misses
1964system.cpu1.l2cache.overall_misses::cpu1.data 110426 # number of overall misses
1965system.cpu1.l2cache.overall_misses::total 146862 # number of overall misses
1966system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 18655500 # number of ReadReq miss cycles
1967system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5724000 # number of ReadReq miss cycles
1968system.cpu1.l2cache.ReadReq_miss_latency::total 24379500 # number of ReadReq miss cycles
1969system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14027500 # number of UpgradeReq miss cycles
1970system.cpu1.l2cache.UpgradeReq_miss_latency::total 14027500 # number of UpgradeReq miss cycles
1971system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17693000 # number of SCUpgradeReq miss cycles
1972system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17693000 # number of SCUpgradeReq miss cycles
1973system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 577000 # number of SCUpgradeFailReq miss cycles
1974system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 577000 # number of SCUpgradeFailReq miss cycles
1975system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1507211500 # number of ReadExReq miss cycles
1976system.cpu1.l2cache.ReadExReq_miss_latency::total 1507211500 # number of ReadExReq miss cycles
1977system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1359433500 # number of ReadCleanReq miss cycles
1978system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1359433500 # number of ReadCleanReq miss cycles
1979system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1899319493 # number of ReadSharedReq miss cycles
1980system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1899319493 # number of ReadSharedReq miss cycles
1981system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 18655500 # number of demand (read+write) miss cycles
1982system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5724000 # number of demand (read+write) miss cycles
1983system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1359433500 # number of demand (read+write) miss cycles
1984system.cpu1.l2cache.demand_miss_latency::cpu1.data 3406530993 # number of demand (read+write) miss cycles
1985system.cpu1.l2cache.demand_miss_latency::total 4790343993 # number of demand (read+write) miss cycles
1986system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 18655500 # number of overall miss cycles
1987system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5724000 # number of overall miss cycles
1988system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1359433500 # number of overall miss cycles
1989system.cpu1.l2cache.overall_miss_latency::cpu1.data 3406530993 # number of overall miss cycles
1990system.cpu1.l2cache.overall_miss_latency::total 4790343993 # number of overall miss cycles
1991system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29845 # number of ReadReq accesses(hits+misses)
1992system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3587 # number of ReadReq accesses(hits+misses)
1993system.cpu1.l2cache.ReadReq_accesses::total 33432 # number of ReadReq accesses(hits+misses)
1994system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117742 # number of WritebackDirty accesses(hits+misses)
1995system.cpu1.l2cache.WritebackDirty_accesses::total 117742 # number of WritebackDirty accesses(hits+misses)
1996system.cpu1.l2cache.WritebackClean_accesses::writebacks 1011389 # number of WritebackClean accesses(hits+misses)
1997system.cpu1.l2cache.WritebackClean_accesses::total 1011389 # number of WritebackClean accesses(hits+misses)
1998system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30019 # number of UpgradeReq accesses(hits+misses)
1999system.cpu1.l2cache.UpgradeReq_accesses::total 30019 # number of UpgradeReq accesses(hits+misses)
2000system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23697 # number of SCUpgradeReq accesses(hits+misses)
2001system.cpu1.l2cache.SCUpgradeReq_accesses::total 23697 # number of SCUpgradeReq accesses(hits+misses)
2002system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62686 # number of ReadExReq accesses(hits+misses)
2003system.cpu1.l2cache.ReadExReq_accesses::total 62686 # number of ReadExReq accesses(hits+misses)
2004system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 952438 # number of ReadCleanReq accesses(hits+misses)
2005system.cpu1.l2cache.ReadCleanReq_accesses::total 952438 # number of ReadCleanReq accesses(hits+misses)
2006system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 179390 # number of ReadSharedReq accesses(hits+misses)
2007system.cpu1.l2cache.ReadSharedReq_accesses::total 179390 # number of ReadSharedReq accesses(hits+misses)
2008system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29845 # number of demand (read+write) accesses
2009system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3587 # number of demand (read+write) accesses
2010system.cpu1.l2cache.demand_accesses::cpu1.inst 952438 # number of demand (read+write) accesses
2011system.cpu1.l2cache.demand_accesses::cpu1.data 242076 # number of demand (read+write) accesses
2012system.cpu1.l2cache.demand_accesses::total 1227946 # number of demand (read+write) accesses
2013system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29845 # number of overall (read+write) accesses
2014system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3587 # number of overall (read+write) accesses
2015system.cpu1.l2cache.overall_accesses::cpu1.inst 952438 # number of overall (read+write) accesses
2016system.cpu1.l2cache.overall_accesses::cpu1.data 242076 # number of overall (read+write) accesses
2017system.cpu1.l2cache.overall_accesses::total 1227946 # number of overall (read+write) accesses
2018system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023589 # miss rate for ReadReq accesses
2019system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079454 # miss rate for ReadReq accesses
2020system.cpu1.l2cache.ReadReq_miss_rate::total 0.029582 # miss rate for ReadReq accesses
2021system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2022system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2023system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2024system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2025system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555961 # miss rate for ReadExReq accesses
2026system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555961 # miss rate for ReadExReq accesses
2027system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.037217 # miss rate for ReadCleanReq accesses
2028system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.037217 # miss rate for ReadCleanReq accesses
2029system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421289 # miss rate for ReadSharedReq accesses
2030system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421289 # miss rate for ReadSharedReq accesses
2031system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023589 # miss rate for demand accesses
2032system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.079454 # miss rate for demand accesses
2033system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.037217 # miss rate for demand accesses
2034system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456163 # miss rate for demand accesses
2035system.cpu1.l2cache.demand_miss_rate::total 0.119600 # miss rate for demand accesses
2036system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023589 # miss rate for overall accesses
2037system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.079454 # miss rate for overall accesses
2038system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.037217 # miss rate for overall accesses
2039system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456163 # miss rate for overall accesses
2040system.cpu1.l2cache.overall_miss_rate::total 0.119600 # miss rate for overall accesses
2041system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 26499.289773 # average ReadReq miss latency
2042system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20084.210526 # average ReadReq miss latency
2043system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24650.657230 # average ReadReq miss latency
2044system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 467.287385 # average UpgradeReq miss latency
2045system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 467.287385 # average UpgradeReq miss latency
2046system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 746.634595 # average SCUpgradeReq miss latency
2047system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 746.634595 # average SCUpgradeReq miss latency
2048system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
2049system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
2050system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43247.295630 # average ReadExReq miss latency
2051system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43247.295630 # average ReadExReq miss latency
2052system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38351.158067 # average ReadCleanReq miss latency
2053system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38351.158067 # average ReadCleanReq miss latency
2054system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25131.584426 # average ReadSharedReq miss latency
2055system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 25131.584426 # average ReadSharedReq miss latency
2056system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 26499.289773 # average overall miss latency
2057system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20084.210526 # average overall miss latency
2058system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38351.158067 # average overall miss latency
2059system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30848.993833 # average overall miss latency
2060system.cpu1.l2cache.demand_avg_miss_latency::total 32617.995077 # average overall miss latency
2061system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 26499.289773 # average overall miss latency
2062system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20084.210526 # average overall miss latency
2063system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38351.158067 # average overall miss latency
2064system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30848.993833 # average overall miss latency
2065system.cpu1.l2cache.overall_avg_miss_latency::total 32617.995077 # average overall miss latency
2066system.cpu1.l2cache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked
2067system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2068system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
2069system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2070system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked
2071system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2072system.cpu1.l2cache.unused_prefetches 874 # number of HardPF blocks evicted w/o reference
2073system.cpu1.l2cache.writebacks::writebacks 36491 # number of writebacks
2074system.cpu1.l2cache.writebacks::total 36491 # number of writebacks
2075system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits
2076system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits
2077system.cpu1.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
2078system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 204 # number of ReadExReq MSHR hits
2079system.cpu1.l2cache.ReadExReq_mshr_hits::total 204 # number of ReadExReq MSHR hits
2080system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 18 # number of ReadCleanReq MSHR hits
2081system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits
2082system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 78 # number of ReadSharedReq MSHR hits
2083system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 78 # number of ReadSharedReq MSHR hits
2084system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits
2085system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits
2086system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits
2087system.cpu1.l2cache.demand_mshr_hits::cpu1.data 282 # number of demand (read+write) MSHR hits
2088system.cpu1.l2cache.demand_mshr_hits::total 305 # number of demand (read+write) MSHR hits
2089system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits
2090system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits
2091system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits
2092system.cpu1.l2cache.overall_mshr_hits::cpu1.data 282 # number of overall MSHR hits
2093system.cpu1.l2cache.overall_mshr_hits::total 305 # number of overall MSHR hits
2094system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 701 # number of ReadReq MSHR misses
2095system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 283 # number of ReadReq MSHR misses
2096system.cpu1.l2cache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses
2097system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26312 # number of HardPFReq MSHR misses
2098system.cpu1.l2cache.HardPFReq_mshr_misses::total 26312 # number of HardPFReq MSHR misses
2099system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 30019 # number of UpgradeReq MSHR misses
2100system.cpu1.l2cache.UpgradeReq_mshr_misses::total 30019 # number of UpgradeReq MSHR misses
2101system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23697 # number of SCUpgradeReq MSHR misses
2102system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23697 # number of SCUpgradeReq MSHR misses
2103system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34647 # number of ReadExReq MSHR misses
2104system.cpu1.l2cache.ReadExReq_mshr_misses::total 34647 # number of ReadExReq MSHR misses
2105system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 35429 # number of ReadCleanReq MSHR misses
2106system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 35429 # number of ReadCleanReq MSHR misses
2107system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 75497 # number of ReadSharedReq MSHR misses
2108system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 75497 # number of ReadSharedReq MSHR misses
2109system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 701 # number of demand (read+write) MSHR misses
2110system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 283 # number of demand (read+write) MSHR misses
2111system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 35429 # number of demand (read+write) MSHR misses
2112system.cpu1.l2cache.demand_mshr_misses::cpu1.data 110144 # number of demand (read+write) MSHR misses
2113system.cpu1.l2cache.demand_mshr_misses::total 146557 # number of demand (read+write) MSHR misses
2114system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 701 # number of overall MSHR misses
2115system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 283 # number of overall MSHR misses
2116system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 35429 # number of overall MSHR misses
2117system.cpu1.l2cache.overall_mshr_misses::cpu1.data 110144 # number of overall MSHR misses
2118system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26312 # number of overall MSHR misses
2119system.cpu1.l2cache.overall_mshr_misses::total 172869 # number of overall MSHR misses
2120system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
2121system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14423 # number of ReadReq MSHR uncacheable
2122system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14535 # number of ReadReq MSHR uncacheable
2123system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11756 # number of WriteReq MSHR uncacheable
2124system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11756 # number of WriteReq MSHR uncacheable
2125system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
2126system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses
2127system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26291 # number of overall MSHR uncacheable misses
2128system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 14391500 # number of ReadReq MSHR miss cycles
2129system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3995000 # number of ReadReq MSHR miss cycles
2130system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 18386500 # number of ReadReq MSHR miss cycles
2131system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 996240965 # number of HardPFReq MSHR miss cycles
2132system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 996240965 # number of HardPFReq MSHR miss cycles
2133system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 460605000 # number of UpgradeReq MSHR miss cycles
2134system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 460605000 # number of UpgradeReq MSHR miss cycles
2135system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 354483500 # number of SCUpgradeReq MSHR miss cycles
2136system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354483500 # number of SCUpgradeReq MSHR miss cycles
2137system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 493000 # number of SCUpgradeFailReq MSHR miss cycles
2138system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 493000 # number of SCUpgradeFailReq MSHR miss cycles
2139system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1271760500 # number of ReadExReq MSHR miss cycles
2140system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1271760500 # number of ReadExReq MSHR miss cycles
2141system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1146491500 # number of ReadCleanReq MSHR miss cycles
2142system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1146491500 # number of ReadCleanReq MSHR miss cycles
2143system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1443582493 # number of ReadSharedReq MSHR miss cycles
2144system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1443582493 # number of ReadSharedReq MSHR miss cycles
2145system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 14391500 # number of demand (read+write) MSHR miss cycles
2146system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3995000 # number of demand (read+write) MSHR miss cycles
2147system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1146491500 # number of demand (read+write) MSHR miss cycles
2148system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2715342993 # number of demand (read+write) MSHR miss cycles
2149system.cpu1.l2cache.demand_mshr_miss_latency::total 3880220993 # number of demand (read+write) MSHR miss cycles
2150system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 14391500 # number of overall MSHR miss cycles
2151system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3995000 # number of overall MSHR miss cycles
2152system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1146491500 # number of overall MSHR miss cycles
2153system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2715342993 # number of overall MSHR miss cycles
2154system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 996240965 # number of overall MSHR miss cycles
2155system.cpu1.l2cache.overall_mshr_miss_latency::total 4876461958 # number of overall MSHR miss cycles
2156system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10234500 # number of ReadReq MSHR uncacheable cycles
2157system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2377871000 # number of ReadReq MSHR uncacheable cycles
2158system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2388105500 # number of ReadReq MSHR uncacheable cycles
2159system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10234500 # number of overall MSHR uncacheable cycles
2160system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2377871000 # number of overall MSHR uncacheable cycles
2161system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2388105500 # number of overall MSHR uncacheable cycles
2162system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for ReadReq accesses
2163system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for ReadReq accesses
2164system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029433 # mshr miss rate for ReadReq accesses
2165system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2166system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2167system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2168system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2169system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2170system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2171system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.552707 # mshr miss rate for ReadExReq accesses
2172system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.552707 # mshr miss rate for ReadExReq accesses
2173system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for ReadCleanReq accesses
2174system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037198 # mshr miss rate for ReadCleanReq accesses
2175system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420854 # mshr miss rate for ReadSharedReq accesses
2176system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420854 # mshr miss rate for ReadSharedReq accesses
2177system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for demand accesses
2178system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for demand accesses
2179system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for demand accesses
2180system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454998 # mshr miss rate for demand accesses
2181system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119351 # mshr miss rate for demand accesses
2182system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for overall accesses
2183system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for overall accesses
2184system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for overall accesses
2185system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454998 # mshr miss rate for overall accesses
2186system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2187system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140779 # mshr miss rate for overall accesses
2188system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average ReadReq mshr miss latency
2189system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average ReadReq mshr miss latency
2190system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18685.467480 # average ReadReq mshr miss latency
2191system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average HardPFReq mshr miss latency
2192system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37862.608886 # average HardPFReq mshr miss latency
2193system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.782271 # average UpgradeReq mshr miss latency
2194system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15343.782271 # average UpgradeReq mshr miss latency
2195system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.003249 # average SCUpgradeReq mshr miss latency
2196system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.003249 # average SCUpgradeReq mshr miss latency
2197system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
2198system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
2199system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36706.222761 # average ReadExReq mshr miss latency
2200system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36706.222761 # average ReadExReq mshr miss latency
2201system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average ReadCleanReq mshr miss latency
2202system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32360.255723 # average ReadCleanReq mshr miss latency
2203system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19121.057698 # average ReadSharedReq mshr miss latency
2204system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19121.057698 # average ReadSharedReq mshr miss latency
2205system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency
2206system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency
2207system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency
2208system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency
2209system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.848939 # average overall mshr miss latency
2210system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency
2211system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency
2212system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency
2213system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency
2214system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average overall mshr miss latency
2215system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28209.001949 # average overall mshr miss latency
2216system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average ReadReq mshr uncacheable latency
2217system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164866.601955 # average ReadReq mshr uncacheable latency
2218system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164300.343997 # average ReadReq mshr uncacheable latency
2219system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average overall mshr uncacheable latency
2220system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90831.238779 # average overall mshr uncacheable latency
2221system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90833.574227 # average overall mshr uncacheable latency
2222system.cpu1.toL2Bus.snoop_filter.tot_requests 2407842 # Total number of requests made to the snoop filter.
2223system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1213344 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2224system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20026 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2225system.cpu1.toL2Bus.snoop_filter.tot_snoops 118526 # Total number of snoops made to the snoop filter.
2226system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110630 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2227system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7896 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2228system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
2229system.cpu1.toL2Bus.trans_dist::ReadReq 52421 # Transaction distribution
2230system.cpu1.toL2Bus.trans_dist::ReadResp 1221670 # Transaction distribution
2231system.cpu1.toL2Bus.trans_dist::WriteReq 11756 # Transaction distribution
2232system.cpu1.toL2Bus.trans_dist::WriteResp 11756 # Transaction distribution
2233system.cpu1.toL2Bus.trans_dist::WritebackDirty 155519 # Transaction distribution
2234system.cpu1.toL2Bus.trans_dist::WritebackClean 1031415 # Transaction distribution
2235system.cpu1.toL2Bus.trans_dist::CleanEvict 35412 # Transaction distribution
2236system.cpu1.toL2Bus.trans_dist::HardPFReq 31701 # Transaction distribution
2237system.cpu1.toL2Bus.trans_dist::UpgradeReq 73485 # Transaction distribution
2238system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42116 # Transaction distribution
2239system.cpu1.toL2Bus.trans_dist::UpgradeResp 86132 # Transaction distribution
2240system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution
2241system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution
2242system.cpu1.toL2Bus.trans_dist::ReadExReq 69767 # Transaction distribution
2243system.cpu1.toL2Bus.trans_dist::ReadExResp 67286 # Transaction distribution
2244system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952438 # Transaction distribution
2245system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295145 # Transaction distribution
2246system.cpu1.toL2Bus.trans_dist::InvalidateReq 55 # Transaction distribution
2247system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2857026 # Packet count per connected master and slave (bytes)
2248system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915642 # Packet count per connected master and slave (bytes)
2249system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8405 # Packet count per connected master and slave (bytes)
2250system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62913 # Packet count per connected master and slave (bytes)
2251system.cpu1.toL2Bus.pkt_count::total 3843986 # Packet count per connected master and slave (bytes)
2252system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121886464 # Cumulative packet size per connected master and slave (bytes)
2253system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30908928 # Cumulative packet size per connected master and slave (bytes)
2254system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14348 # Cumulative packet size per connected master and slave (bytes)
2255system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119380 # Cumulative packet size per connected master and slave (bytes)
2256system.cpu1.toL2Bus.pkt_size::total 152929120 # Cumulative packet size per connected master and slave (bytes)
2257system.cpu1.toL2Bus.snoops 368607 # Total snoops (count)
2258system.cpu1.toL2Bus.snoopTraffic 5126040 # Total snoop traffic (bytes)
2259system.cpu1.toL2Bus.snoop_fanout::samples 1602092 # Request fanout histogram
2260system.cpu1.toL2Bus.snoop_fanout::mean 0.097939 # Request fanout histogram
2261system.cpu1.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram
2262system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2263system.cpu1.toL2Bus.snoop_fanout::0 1453081 90.70% 90.70% # Request fanout histogram
2264system.cpu1.toL2Bus.snoop_fanout::1 141115 8.81% 99.51% # Request fanout histogram
2265system.cpu1.toL2Bus.snoop_fanout::2 7896 0.49% 100.00% # Request fanout histogram
2266system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2267system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2268system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2269system.cpu1.toL2Bus.snoop_fanout::total 1602092 # Request fanout histogram
2270system.cpu1.toL2Bus.reqLayer0.occupancy 2385821492 # Layer occupancy (ticks)
2271system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2272system.cpu1.toL2Bus.snoopLayer0.occupancy 79306117 # Layer occupancy (ticks)
2273system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2274system.cpu1.toL2Bus.respLayer0.occupancy 1428899351 # Layer occupancy (ticks)
2275system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2276system.cpu1.toL2Bus.respLayer1.occupancy 412338887 # Layer occupancy (ticks)
2277system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2278system.cpu1.toL2Bus.respLayer2.occupancy 4820495 # Layer occupancy (ticks)
2279system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2280system.cpu1.toL2Bus.respLayer3.occupancy 33080974 # Layer occupancy (ticks)
2281system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2282system.iobus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
2283system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
2284system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
2285system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
2286system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
2287system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
2288system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2289system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2290system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)

--- 34 unchanged lines hidden (view full) ---

2325system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2326system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2327system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2328system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2329system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
2330system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
2331system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
2332system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes)
2333system.iobus.reqLayer0.occupancy 48391001 # Layer occupancy (ticks)
2334system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2335system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks)
2336system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2337system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks)
2338system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2339system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks)
2340system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2341system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
2342system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2343system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks)
2344system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2345system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks)
2346system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2347system.iobus.reqLayer10.occupancy 20000 # Layer occupancy (ticks)
2348system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2349system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
2350system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2351system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2352system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2353system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2354system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2355system.iobus.reqLayer16.occupancy 47000 # Layer occupancy (ticks)
2356system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2357system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2358system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2359system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
2360system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2361system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2362system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2363system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2364system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2365system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
2366system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2367system.iobus.reqLayer23.occupancy 6378000 # Layer occupancy (ticks)
2368system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2369system.iobus.reqLayer24.occupancy 38950500 # Layer occupancy (ticks)
2370system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2371system.iobus.reqLayer25.occupancy 187782564 # Layer occupancy (ticks)
2372system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2373system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
2374system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2375system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
2376system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2377system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
2378system.iocache.tags.replacements 36461 # number of replacements
2379system.iocache.tags.tagsinuse 14.472132 # Cycle average of tags in use
2380system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2381system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks.
2382system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2383system.iocache.tags.warmup_cycle 272036828000 # Cycle when the warmup percentage was hit.
2384system.iocache.tags.occ_blocks::realview.ide 14.472132 # Average occupied blocks per requestor
2385system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy
2386system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy
2387system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2388system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2389system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2390system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2391system.iocache.tags.data_accesses 328311 # Number of data accesses
2392system.iocache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
2393system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2394system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2395system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2396system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2397system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
2398system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
2399system.iocache.overall_misses::realview.ide 36479 # number of overall misses
2400system.iocache.overall_misses::total 36479 # number of overall misses
2401system.iocache.ReadReq_miss_latency::realview.ide 33219876 # number of ReadReq miss cycles
2402system.iocache.ReadReq_miss_latency::total 33219876 # number of ReadReq miss cycles
2403system.iocache.WriteLineReq_miss_latency::realview.ide 4376166688 # number of WriteLineReq miss cycles
2404system.iocache.WriteLineReq_miss_latency::total 4376166688 # number of WriteLineReq miss cycles
2405system.iocache.demand_miss_latency::realview.ide 4409386564 # number of demand (read+write) miss cycles
2406system.iocache.demand_miss_latency::total 4409386564 # number of demand (read+write) miss cycles
2407system.iocache.overall_miss_latency::realview.ide 4409386564 # number of overall miss cycles
2408system.iocache.overall_miss_latency::total 4409386564 # number of overall miss cycles
2409system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2410system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2411system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2412system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2413system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
2414system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
2415system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
2416system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
2417system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2418system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2419system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2420system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2421system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2422system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2423system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2424system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2425system.iocache.ReadReq_avg_miss_latency::realview.ide 130274.023529 # average ReadReq miss latency
2426system.iocache.ReadReq_avg_miss_latency::total 130274.023529 # average ReadReq miss latency
2427system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120808.488516 # average WriteLineReq miss latency
2428system.iocache.WriteLineReq_avg_miss_latency::total 120808.488516 # average WriteLineReq miss latency
2429system.iocache.demand_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency
2430system.iocache.demand_avg_miss_latency::total 120874.655665 # average overall miss latency
2431system.iocache.overall_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency
2432system.iocache.overall_avg_miss_latency::total 120874.655665 # average overall miss latency
2433system.iocache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked
2434system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2435system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked
2436system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2437system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
2438system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2439system.iocache.writebacks::writebacks 36206 # number of writebacks
2440system.iocache.writebacks::total 36206 # number of writebacks
2441system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2442system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2443system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2444system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2445system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
2446system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
2447system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
2448system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
2449system.iocache.ReadReq_mshr_miss_latency::realview.ide 20469876 # number of ReadReq MSHR miss cycles
2450system.iocache.ReadReq_mshr_miss_latency::total 20469876 # number of ReadReq MSHR miss cycles
2451system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2562591001 # number of WriteLineReq MSHR miss cycles
2452system.iocache.WriteLineReq_mshr_miss_latency::total 2562591001 # number of WriteLineReq MSHR miss cycles
2453system.iocache.demand_mshr_miss_latency::realview.ide 2583060877 # number of demand (read+write) MSHR miss cycles
2454system.iocache.demand_mshr_miss_latency::total 2583060877 # number of demand (read+write) MSHR miss cycles
2455system.iocache.overall_mshr_miss_latency::realview.ide 2583060877 # number of overall MSHR miss cycles
2456system.iocache.overall_mshr_miss_latency::total 2583060877 # number of overall MSHR miss cycles
2457system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2458system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2459system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2460system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2461system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2462system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2463system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2464system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2465system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80274.023529 # average ReadReq mshr miss latency
2466system.iocache.ReadReq_avg_mshr_miss_latency::total 80274.023529 # average ReadReq mshr miss latency
2467system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70742.905284 # average WriteLineReq mshr miss latency
2468system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70742.905284 # average WriteLineReq mshr miss latency
2469system.iocache.demand_avg_mshr_miss_latency::realview.ide 70809.530881 # average overall mshr miss latency
2470system.iocache.demand_avg_mshr_miss_latency::total 70809.530881 # average overall mshr miss latency
2471system.iocache.overall_avg_mshr_miss_latency::realview.ide 70809.530881 # average overall mshr miss latency
2472system.iocache.overall_avg_mshr_miss_latency::total 70809.530881 # average overall mshr miss latency
2473system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
2474system.l2c.tags.replacements 145308 # number of replacements
2475system.l2c.tags.tagsinuse 65153.014694 # Cycle average of tags in use
2476system.l2c.tags.total_refs 608197 # Total number of references to valid blocks.
2477system.l2c.tags.sampled_refs 210799 # Sample count of references to valid blocks.
2478system.l2c.tags.avg_refs 2.885199 # Average number of references to valid blocks.
2479system.l2c.tags.warmup_cycle 94570968000 # Cycle when the warmup percentage was hit.
2480system.l2c.tags.occ_blocks::writebacks 6725.818981 # Average occupied blocks per requestor
2481system.l2c.tags.occ_blocks::cpu0.dtb.walker 88.835717 # Average occupied blocks per requestor
2482system.l2c.tags.occ_blocks::cpu0.itb.walker 0.039308 # Average occupied blocks per requestor
2483system.l2c.tags.occ_blocks::cpu0.inst 8741.022578 # Average occupied blocks per requestor
2484system.l2c.tags.occ_blocks::cpu0.data 6775.934473 # Average occupied blocks per requestor
2485system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34864.204134 # Average occupied blocks per requestor
2486system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.618119 # Average occupied blocks per requestor
2487system.l2c.tags.occ_blocks::cpu1.inst 2235.319135 # Average occupied blocks per requestor
2488system.l2c.tags.occ_blocks::cpu1.data 3466.513349 # Average occupied blocks per requestor
2489system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2242.708901 # Average occupied blocks per requestor
2490system.l2c.tags.occ_percent::writebacks 0.102628 # Average percentage of cache occupancy
2491system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001356 # Average percentage of cache occupancy
2492system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2493system.l2c.tags.occ_percent::cpu0.inst 0.133377 # Average percentage of cache occupancy
2494system.l2c.tags.occ_percent::cpu0.data 0.103393 # Average percentage of cache occupancy
2495system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.531986 # Average percentage of cache occupancy
2496system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000193 # Average percentage of cache occupancy
2497system.l2c.tags.occ_percent::cpu1.inst 0.034108 # Average percentage of cache occupancy
2498system.l2c.tags.occ_percent::cpu1.data 0.052895 # Average percentage of cache occupancy
2499system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034221 # Average percentage of cache occupancy
2500system.l2c.tags.occ_percent::total 0.994156 # Average percentage of cache occupancy
2501system.l2c.tags.occ_task_id_blocks::1022 31590 # Occupied blocks per task id
2502system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id
2503system.l2c.tags.occ_task_id_blocks::1024 33841 # Occupied blocks per task id
2504system.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id
2505system.l2c.tags.age_task_id_blocks_1022::3 4772 # Occupied blocks per task id
2506system.l2c.tags.age_task_id_blocks_1022::4 26692 # Occupied blocks per task id
2507system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
2508system.l2c.tags.age_task_id_blocks_1023::4 58 # Occupied blocks per task id
2509system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
2510system.l2c.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
2511system.l2c.tags.age_task_id_blocks_1024::3 1899 # Occupied blocks per task id
2512system.l2c.tags.age_task_id_blocks_1024::4 31836 # Occupied blocks per task id
2513system.l2c.tags.occ_task_id_percent::1022 0.482025 # Percentage of cache occupancy per task id
2514system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id
2515system.l2c.tags.occ_task_id_percent::1024 0.516373 # Percentage of cache occupancy per task id
2516system.l2c.tags.tag_accesses 6845829 # Number of tag accesses
2517system.l2c.tags.data_accesses 6845829 # Number of data accesses
2518system.l2c.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
2519system.l2c.WritebackDirty_hits::writebacks 269041 # number of WritebackDirty hits
2520system.l2c.WritebackDirty_hits::total 269041 # number of WritebackDirty hits
2521system.l2c.UpgradeReq_hits::cpu0.data 43018 # number of UpgradeReq hits
2522system.l2c.UpgradeReq_hits::cpu1.data 5569 # number of UpgradeReq hits
2523system.l2c.UpgradeReq_hits::total 48587 # number of UpgradeReq hits
2524system.l2c.SCUpgradeReq_hits::cpu0.data 2756 # number of SCUpgradeReq hits
2525system.l2c.SCUpgradeReq_hits::cpu1.data 2348 # number of SCUpgradeReq hits
2526system.l2c.SCUpgradeReq_hits::total 5104 # number of SCUpgradeReq hits
2527system.l2c.ReadExReq_hits::cpu0.data 4245 # number of ReadExReq hits
2528system.l2c.ReadExReq_hits::cpu1.data 1488 # number of ReadExReq hits
2529system.l2c.ReadExReq_hits::total 5733 # number of ReadExReq hits
2530system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 501 # number of ReadSharedReq hits
2531system.l2c.ReadSharedReq_hits::cpu0.itb.walker 88 # number of ReadSharedReq hits
2532system.l2c.ReadSharedReq_hits::cpu0.inst 68822 # number of ReadSharedReq hits
2533system.l2c.ReadSharedReq_hits::cpu0.data 63059 # number of ReadSharedReq hits
2534system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47426 # number of ReadSharedReq hits
2535system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 132 # number of ReadSharedReq hits
2536system.l2c.ReadSharedReq_hits::cpu1.itb.walker 22 # number of ReadSharedReq hits
2537system.l2c.ReadSharedReq_hits::cpu1.inst 31931 # number of ReadSharedReq hits
2538system.l2c.ReadSharedReq_hits::cpu1.data 13672 # number of ReadSharedReq hits
2539system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5861 # number of ReadSharedReq hits
2540system.l2c.ReadSharedReq_hits::total 231514 # number of ReadSharedReq hits
2541system.l2c.demand_hits::cpu0.dtb.walker 501 # number of demand (read+write) hits
2542system.l2c.demand_hits::cpu0.itb.walker 88 # number of demand (read+write) hits
2543system.l2c.demand_hits::cpu0.inst 68822 # number of demand (read+write) hits
2544system.l2c.demand_hits::cpu0.data 67304 # number of demand (read+write) hits
2545system.l2c.demand_hits::cpu0.l2cache.prefetcher 47426 # number of demand (read+write) hits
2546system.l2c.demand_hits::cpu1.dtb.walker 132 # number of demand (read+write) hits
2547system.l2c.demand_hits::cpu1.itb.walker 22 # number of demand (read+write) hits
2548system.l2c.demand_hits::cpu1.inst 31931 # number of demand (read+write) hits
2549system.l2c.demand_hits::cpu1.data 15160 # number of demand (read+write) hits
2550system.l2c.demand_hits::cpu1.l2cache.prefetcher 5861 # number of demand (read+write) hits
2551system.l2c.demand_hits::total 237247 # number of demand (read+write) hits
2552system.l2c.overall_hits::cpu0.dtb.walker 501 # number of overall hits
2553system.l2c.overall_hits::cpu0.itb.walker 88 # number of overall hits
2554system.l2c.overall_hits::cpu0.inst 68822 # number of overall hits
2555system.l2c.overall_hits::cpu0.data 67304 # number of overall hits
2556system.l2c.overall_hits::cpu0.l2cache.prefetcher 47426 # number of overall hits
2557system.l2c.overall_hits::cpu1.dtb.walker 132 # number of overall hits
2558system.l2c.overall_hits::cpu1.itb.walker 22 # number of overall hits
2559system.l2c.overall_hits::cpu1.inst 31931 # number of overall hits
2560system.l2c.overall_hits::cpu1.data 15160 # number of overall hits
2561system.l2c.overall_hits::cpu1.l2cache.prefetcher 5861 # number of overall hits
2562system.l2c.overall_hits::total 237247 # number of overall hits
2563system.l2c.UpgradeReq_misses::cpu0.data 567 # number of UpgradeReq misses
2564system.l2c.UpgradeReq_misses::cpu1.data 233 # number of UpgradeReq misses
2565system.l2c.UpgradeReq_misses::total 800 # number of UpgradeReq misses
2566system.l2c.SCUpgradeReq_misses::cpu0.data 71 # number of SCUpgradeReq misses
2567system.l2c.SCUpgradeReq_misses::cpu1.data 57 # number of SCUpgradeReq misses
2568system.l2c.SCUpgradeReq_misses::total 128 # number of SCUpgradeReq misses
2569system.l2c.ReadExReq_misses::cpu0.data 11330 # number of ReadExReq misses
2570system.l2c.ReadExReq_misses::cpu1.data 8671 # number of ReadExReq misses
2571system.l2c.ReadExReq_misses::total 20001 # number of ReadExReq misses
2572system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 149 # number of ReadSharedReq misses
2573system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses
2574system.l2c.ReadSharedReq_misses::cpu0.inst 22928 # number of ReadSharedReq misses
2575system.l2c.ReadSharedReq_misses::cpu0.data 10009 # number of ReadSharedReq misses
2576system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132762 # number of ReadSharedReq misses
2577system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 16 # number of ReadSharedReq misses
2578system.l2c.ReadSharedReq_misses::cpu1.inst 3498 # number of ReadSharedReq misses
2579system.l2c.ReadSharedReq_misses::cpu1.data 1729 # number of ReadSharedReq misses
2580system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6519 # number of ReadSharedReq misses
2581system.l2c.ReadSharedReq_misses::total 177611 # number of ReadSharedReq misses
2582system.l2c.demand_misses::cpu0.dtb.walker 149 # number of demand (read+write) misses
2583system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
2584system.l2c.demand_misses::cpu0.inst 22928 # number of demand (read+write) misses
2585system.l2c.demand_misses::cpu0.data 21339 # number of demand (read+write) misses
2586system.l2c.demand_misses::cpu0.l2cache.prefetcher 132762 # number of demand (read+write) misses
2587system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses
2588system.l2c.demand_misses::cpu1.inst 3498 # number of demand (read+write) misses
2589system.l2c.demand_misses::cpu1.data 10400 # number of demand (read+write) misses
2590system.l2c.demand_misses::cpu1.l2cache.prefetcher 6519 # number of demand (read+write) misses
2591system.l2c.demand_misses::total 197612 # number of demand (read+write) misses
2592system.l2c.overall_misses::cpu0.dtb.walker 149 # number of overall misses
2593system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
2594system.l2c.overall_misses::cpu0.inst 22928 # number of overall misses
2595system.l2c.overall_misses::cpu0.data 21339 # number of overall misses
2596system.l2c.overall_misses::cpu0.l2cache.prefetcher 132762 # number of overall misses
2597system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses
2598system.l2c.overall_misses::cpu1.inst 3498 # number of overall misses
2599system.l2c.overall_misses::cpu1.data 10400 # number of overall misses
2600system.l2c.overall_misses::cpu1.l2cache.prefetcher 6519 # number of overall misses
2601system.l2c.overall_misses::total 197612 # number of overall misses
2602system.l2c.UpgradeReq_miss_latency::cpu0.data 7996500 # number of UpgradeReq miss cycles
2603system.l2c.UpgradeReq_miss_latency::cpu1.data 709500 # number of UpgradeReq miss cycles
2604system.l2c.UpgradeReq_miss_latency::total 8706000 # number of UpgradeReq miss cycles
2605system.l2c.SCUpgradeReq_miss_latency::cpu0.data 618000 # number of SCUpgradeReq miss cycles
2606system.l2c.SCUpgradeReq_miss_latency::cpu1.data 99500 # number of SCUpgradeReq miss cycles
2607system.l2c.SCUpgradeReq_miss_latency::total 717500 # number of SCUpgradeReq miss cycles
2608system.l2c.ReadExReq_miss_latency::cpu0.data 1582862000 # number of ReadExReq miss cycles
2609system.l2c.ReadExReq_miss_latency::cpu1.data 826941000 # number of ReadExReq miss cycles
2610system.l2c.ReadExReq_miss_latency::total 2409803000 # number of ReadExReq miss cycles
2611system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 24166000 # number of ReadSharedReq miss cycles
2612system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90000 # number of ReadSharedReq miss cycles
2613system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2324658500 # number of ReadSharedReq miss cycles
2614system.l2c.ReadSharedReq_miss_latency::cpu0.data 1196554000 # number of ReadSharedReq miss cycles
2615system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15972256455 # number of ReadSharedReq miss cycles
2616system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3966500 # number of ReadSharedReq miss cycles
2617system.l2c.ReadSharedReq_miss_latency::cpu1.inst 386401500 # number of ReadSharedReq miss cycles
2618system.l2c.ReadSharedReq_miss_latency::cpu1.data 279812500 # number of ReadSharedReq miss cycles
2619system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 875704589 # number of ReadSharedReq miss cycles
2620system.l2c.ReadSharedReq_miss_latency::total 21063610044 # number of ReadSharedReq miss cycles
2621system.l2c.demand_miss_latency::cpu0.dtb.walker 24166000 # number of demand (read+write) miss cycles
2622system.l2c.demand_miss_latency::cpu0.itb.walker 90000 # number of demand (read+write) miss cycles
2623system.l2c.demand_miss_latency::cpu0.inst 2324658500 # number of demand (read+write) miss cycles
2624system.l2c.demand_miss_latency::cpu0.data 2779416000 # number of demand (read+write) miss cycles
2625system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15972256455 # number of demand (read+write) miss cycles
2626system.l2c.demand_miss_latency::cpu1.dtb.walker 3966500 # number of demand (read+write) miss cycles
2627system.l2c.demand_miss_latency::cpu1.inst 386401500 # number of demand (read+write) miss cycles
2628system.l2c.demand_miss_latency::cpu1.data 1106753500 # number of demand (read+write) miss cycles
2629system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 875704589 # number of demand (read+write) miss cycles
2630system.l2c.demand_miss_latency::total 23473413044 # number of demand (read+write) miss cycles
2631system.l2c.overall_miss_latency::cpu0.dtb.walker 24166000 # number of overall miss cycles
2632system.l2c.overall_miss_latency::cpu0.itb.walker 90000 # number of overall miss cycles
2633system.l2c.overall_miss_latency::cpu0.inst 2324658500 # number of overall miss cycles
2634system.l2c.overall_miss_latency::cpu0.data 2779416000 # number of overall miss cycles
2635system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15972256455 # number of overall miss cycles
2636system.l2c.overall_miss_latency::cpu1.dtb.walker 3966500 # number of overall miss cycles
2637system.l2c.overall_miss_latency::cpu1.inst 386401500 # number of overall miss cycles
2638system.l2c.overall_miss_latency::cpu1.data 1106753500 # number of overall miss cycles
2639system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 875704589 # number of overall miss cycles
2640system.l2c.overall_miss_latency::total 23473413044 # number of overall miss cycles
2641system.l2c.WritebackDirty_accesses::writebacks 269041 # number of WritebackDirty accesses(hits+misses)
2642system.l2c.WritebackDirty_accesses::total 269041 # number of WritebackDirty accesses(hits+misses)
2643system.l2c.UpgradeReq_accesses::cpu0.data 43585 # number of UpgradeReq accesses(hits+misses)
2644system.l2c.UpgradeReq_accesses::cpu1.data 5802 # number of UpgradeReq accesses(hits+misses)
2645system.l2c.UpgradeReq_accesses::total 49387 # number of UpgradeReq accesses(hits+misses)
2646system.l2c.SCUpgradeReq_accesses::cpu0.data 2827 # number of SCUpgradeReq accesses(hits+misses)
2647system.l2c.SCUpgradeReq_accesses::cpu1.data 2405 # number of SCUpgradeReq accesses(hits+misses)
2648system.l2c.SCUpgradeReq_accesses::total 5232 # number of SCUpgradeReq accesses(hits+misses)
2649system.l2c.ReadExReq_accesses::cpu0.data 15575 # number of ReadExReq accesses(hits+misses)
2650system.l2c.ReadExReq_accesses::cpu1.data 10159 # number of ReadExReq accesses(hits+misses)
2651system.l2c.ReadExReq_accesses::total 25734 # number of ReadExReq accesses(hits+misses)
2652system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 650 # number of ReadSharedReq accesses(hits+misses)
2653system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 89 # number of ReadSharedReq accesses(hits+misses)
2654system.l2c.ReadSharedReq_accesses::cpu0.inst 91750 # number of ReadSharedReq accesses(hits+misses)
2655system.l2c.ReadSharedReq_accesses::cpu0.data 73068 # number of ReadSharedReq accesses(hits+misses)
2656system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180188 # number of ReadSharedReq accesses(hits+misses)
2657system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 148 # number of ReadSharedReq accesses(hits+misses)
2658system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 22 # number of ReadSharedReq accesses(hits+misses)
2659system.l2c.ReadSharedReq_accesses::cpu1.inst 35429 # number of ReadSharedReq accesses(hits+misses)
2660system.l2c.ReadSharedReq_accesses::cpu1.data 15401 # number of ReadSharedReq accesses(hits+misses)
2661system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 12380 # number of ReadSharedReq accesses(hits+misses)
2662system.l2c.ReadSharedReq_accesses::total 409125 # number of ReadSharedReq accesses(hits+misses)
2663system.l2c.demand_accesses::cpu0.dtb.walker 650 # number of demand (read+write) accesses
2664system.l2c.demand_accesses::cpu0.itb.walker 89 # number of demand (read+write) accesses
2665system.l2c.demand_accesses::cpu0.inst 91750 # number of demand (read+write) accesses
2666system.l2c.demand_accesses::cpu0.data 88643 # number of demand (read+write) accesses
2667system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180188 # number of demand (read+write) accesses
2668system.l2c.demand_accesses::cpu1.dtb.walker 148 # number of demand (read+write) accesses
2669system.l2c.demand_accesses::cpu1.itb.walker 22 # number of demand (read+write) accesses
2670system.l2c.demand_accesses::cpu1.inst 35429 # number of demand (read+write) accesses
2671system.l2c.demand_accesses::cpu1.data 25560 # number of demand (read+write) accesses
2672system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12380 # number of demand (read+write) accesses
2673system.l2c.demand_accesses::total 434859 # number of demand (read+write) accesses
2674system.l2c.overall_accesses::cpu0.dtb.walker 650 # number of overall (read+write) accesses
2675system.l2c.overall_accesses::cpu0.itb.walker 89 # number of overall (read+write) accesses
2676system.l2c.overall_accesses::cpu0.inst 91750 # number of overall (read+write) accesses
2677system.l2c.overall_accesses::cpu0.data 88643 # number of overall (read+write) accesses
2678system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180188 # number of overall (read+write) accesses
2679system.l2c.overall_accesses::cpu1.dtb.walker 148 # number of overall (read+write) accesses
2680system.l2c.overall_accesses::cpu1.itb.walker 22 # number of overall (read+write) accesses
2681system.l2c.overall_accesses::cpu1.inst 35429 # number of overall (read+write) accesses
2682system.l2c.overall_accesses::cpu1.data 25560 # number of overall (read+write) accesses
2683system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12380 # number of overall (read+write) accesses
2684system.l2c.overall_accesses::total 434859 # number of overall (read+write) accesses
2685system.l2c.UpgradeReq_miss_rate::cpu0.data 0.013009 # miss rate for UpgradeReq accesses
2686system.l2c.UpgradeReq_miss_rate::cpu1.data 0.040159 # miss rate for UpgradeReq accesses
2687system.l2c.UpgradeReq_miss_rate::total 0.016199 # miss rate for UpgradeReq accesses
2688system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.025115 # miss rate for SCUpgradeReq accesses
2689system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.023701 # miss rate for SCUpgradeReq accesses
2690system.l2c.SCUpgradeReq_miss_rate::total 0.024465 # miss rate for SCUpgradeReq accesses
2691system.l2c.ReadExReq_miss_rate::cpu0.data 0.727448 # miss rate for ReadExReq accesses
2692system.l2c.ReadExReq_miss_rate::cpu1.data 0.853529 # miss rate for ReadExReq accesses
2693system.l2c.ReadExReq_miss_rate::total 0.777221 # miss rate for ReadExReq accesses
2694system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.229231 # miss rate for ReadSharedReq accesses
2695system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.011236 # miss rate for ReadSharedReq accesses
2696system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.249896 # miss rate for ReadSharedReq accesses
2697system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.136982 # miss rate for ReadSharedReq accesses
2698system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.736797 # miss rate for ReadSharedReq accesses
2699system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.108108 # miss rate for ReadSharedReq accesses
2700system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098733 # miss rate for ReadSharedReq accesses
2701system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.112265 # miss rate for ReadSharedReq accesses
2702system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.526575 # miss rate for ReadSharedReq accesses
2703system.l2c.ReadSharedReq_miss_rate::total 0.434124 # miss rate for ReadSharedReq accesses
2704system.l2c.demand_miss_rate::cpu0.dtb.walker 0.229231 # miss rate for demand accesses
2705system.l2c.demand_miss_rate::cpu0.itb.walker 0.011236 # miss rate for demand accesses
2706system.l2c.demand_miss_rate::cpu0.inst 0.249896 # miss rate for demand accesses
2707system.l2c.demand_miss_rate::cpu0.data 0.240730 # miss rate for demand accesses
2708system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.736797 # miss rate for demand accesses
2709system.l2c.demand_miss_rate::cpu1.dtb.walker 0.108108 # miss rate for demand accesses
2710system.l2c.demand_miss_rate::cpu1.inst 0.098733 # miss rate for demand accesses
2711system.l2c.demand_miss_rate::cpu1.data 0.406886 # miss rate for demand accesses
2712system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.526575 # miss rate for demand accesses
2713system.l2c.demand_miss_rate::total 0.454428 # miss rate for demand accesses
2714system.l2c.overall_miss_rate::cpu0.dtb.walker 0.229231 # miss rate for overall accesses
2715system.l2c.overall_miss_rate::cpu0.itb.walker 0.011236 # miss rate for overall accesses
2716system.l2c.overall_miss_rate::cpu0.inst 0.249896 # miss rate for overall accesses
2717system.l2c.overall_miss_rate::cpu0.data 0.240730 # miss rate for overall accesses
2718system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.736797 # miss rate for overall accesses
2719system.l2c.overall_miss_rate::cpu1.dtb.walker 0.108108 # miss rate for overall accesses
2720system.l2c.overall_miss_rate::cpu1.inst 0.098733 # miss rate for overall accesses
2721system.l2c.overall_miss_rate::cpu1.data 0.406886 # miss rate for overall accesses
2722system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.526575 # miss rate for overall accesses
2723system.l2c.overall_miss_rate::total 0.454428 # miss rate for overall accesses
2724system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14103.174603 # average UpgradeReq miss latency
2725system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3045.064378 # average UpgradeReq miss latency
2726system.l2c.UpgradeReq_avg_miss_latency::total 10882.500000 # average UpgradeReq miss latency
2727system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8704.225352 # average SCUpgradeReq miss latency
2728system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1745.614035 # average SCUpgradeReq miss latency
2729system.l2c.SCUpgradeReq_avg_miss_latency::total 5605.468750 # average SCUpgradeReq miss latency
2730system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139705.383936 # average ReadExReq miss latency
2731system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95368.584938 # average ReadExReq miss latency
2732system.l2c.ReadExReq_avg_miss_latency::total 120484.125794 # average ReadExReq miss latency
2733system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 162187.919463 # average ReadSharedReq miss latency
2734system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency
2735system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 101389.501919 # average ReadSharedReq miss latency
2736system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 119547.806974 # average ReadSharedReq miss latency
2737system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 120307.440796 # average ReadSharedReq miss latency
2738system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 247906.250000 # average ReadSharedReq miss latency
2739system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110463.550600 # average ReadSharedReq miss latency
2740system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 161834.875651 # average ReadSharedReq miss latency
2741system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134331.122718 # average ReadSharedReq miss latency
2742system.l2c.ReadSharedReq_avg_miss_latency::total 118594.062552 # average ReadSharedReq miss latency
2743system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 162187.919463 # average overall miss latency
2744system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
2745system.l2c.demand_avg_miss_latency::cpu0.inst 101389.501919 # average overall miss latency
2746system.l2c.demand_avg_miss_latency::cpu0.data 130250.527204 # average overall miss latency
2747system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 120307.440796 # average overall miss latency
2748system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 247906.250000 # average overall miss latency
2749system.l2c.demand_avg_miss_latency::cpu1.inst 110463.550600 # average overall miss latency
2750system.l2c.demand_avg_miss_latency::cpu1.data 106418.605769 # average overall miss latency
2751system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134331.122718 # average overall miss latency
2752system.l2c.demand_avg_miss_latency::total 118785.362448 # average overall miss latency
2753system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 162187.919463 # average overall miss latency
2754system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
2755system.l2c.overall_avg_miss_latency::cpu0.inst 101389.501919 # average overall miss latency
2756system.l2c.overall_avg_miss_latency::cpu0.data 130250.527204 # average overall miss latency
2757system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 120307.440796 # average overall miss latency
2758system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 247906.250000 # average overall miss latency
2759system.l2c.overall_avg_miss_latency::cpu1.inst 110463.550600 # average overall miss latency
2760system.l2c.overall_avg_miss_latency::cpu1.data 106418.605769 # average overall miss latency
2761system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134331.122718 # average overall miss latency
2762system.l2c.overall_avg_miss_latency::total 118785.362448 # average overall miss latency
2763system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2764system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2765system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2766system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2767system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2768system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2769system.l2c.writebacks::writebacks 105581 # number of writebacks
2770system.l2c.writebacks::total 105581 # number of writebacks
2771system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits
2772system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits
2773system.l2c.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits
2774system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
2775system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
2776system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits
2777system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
2778system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
2779system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits
2780system.l2c.CleanEvict_mshr_misses::writebacks 4797 # number of CleanEvict MSHR misses
2781system.l2c.CleanEvict_mshr_misses::total 4797 # number of CleanEvict MSHR misses
2782system.l2c.UpgradeReq_mshr_misses::cpu0.data 567 # number of UpgradeReq MSHR misses
2783system.l2c.UpgradeReq_mshr_misses::cpu1.data 233 # number of UpgradeReq MSHR misses
2784system.l2c.UpgradeReq_mshr_misses::total 800 # number of UpgradeReq MSHR misses
2785system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 71 # number of SCUpgradeReq MSHR misses
2786system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 57 # number of SCUpgradeReq MSHR misses
2787system.l2c.SCUpgradeReq_mshr_misses::total 128 # number of SCUpgradeReq MSHR misses
2788system.l2c.ReadExReq_mshr_misses::cpu0.data 11330 # number of ReadExReq MSHR misses
2789system.l2c.ReadExReq_mshr_misses::cpu1.data 8671 # number of ReadExReq MSHR misses
2790system.l2c.ReadExReq_mshr_misses::total 20001 # number of ReadExReq MSHR misses
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2792system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses
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2794system.l2c.ReadSharedReq_mshr_misses::cpu0.data 10009 # number of ReadSharedReq MSHR misses
2795system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132762 # number of ReadSharedReq MSHR misses
2796system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadSharedReq MSHR misses
2797system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3494 # number of ReadSharedReq MSHR misses
2798system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1729 # number of ReadSharedReq MSHR misses
2799system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6519 # number of ReadSharedReq MSHR misses
2800system.l2c.ReadSharedReq_mshr_misses::total 177604 # number of ReadSharedReq MSHR misses
2801system.l2c.demand_mshr_misses::cpu0.dtb.walker 149 # number of demand (read+write) MSHR misses
2802system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
2803system.l2c.demand_mshr_misses::cpu0.inst 22925 # number of demand (read+write) MSHR misses
2804system.l2c.demand_mshr_misses::cpu0.data 21339 # number of demand (read+write) MSHR misses
2805system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132762 # number of demand (read+write) MSHR misses
2806system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses
2807system.l2c.demand_mshr_misses::cpu1.inst 3494 # number of demand (read+write) MSHR misses
2808system.l2c.demand_mshr_misses::cpu1.data 10400 # number of demand (read+write) MSHR misses
2809system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6519 # number of demand (read+write) MSHR misses
2810system.l2c.demand_mshr_misses::total 197605 # number of demand (read+write) MSHR misses
2811system.l2c.overall_mshr_misses::cpu0.dtb.walker 149 # number of overall MSHR misses
2812system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
2813system.l2c.overall_mshr_misses::cpu0.inst 22925 # number of overall MSHR misses
2814system.l2c.overall_mshr_misses::cpu0.data 21339 # number of overall MSHR misses
2815system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132762 # number of overall MSHR misses
2816system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses
2817system.l2c.overall_mshr_misses::cpu1.inst 3494 # number of overall MSHR misses
2818system.l2c.overall_mshr_misses::cpu1.data 10400 # number of overall MSHR misses
2819system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6519 # number of overall MSHR misses
2820system.l2c.overall_mshr_misses::total 197605 # number of overall MSHR misses
2821system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable
2822system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable
2823system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
2824system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14420 # number of ReadReq MSHR uncacheable
2825system.l2c.ReadReq_mshr_uncacheable::total 38386 # number of ReadReq MSHR uncacheable
2826system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable
2827system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11756 # number of WriteReq MSHR uncacheable
2828system.l2c.WriteReq_mshr_uncacheable::total 31026 # number of WriteReq MSHR uncacheable
2829system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses
2830system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39847 # number of overall MSHR uncacheable misses
2831system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
2832system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26176 # number of overall MSHR uncacheable misses
2833system.l2c.overall_mshr_uncacheable_misses::total 69412 # number of overall MSHR uncacheable misses
2834system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13077000 # number of UpgradeReq MSHR miss cycles
2835system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4990500 # number of UpgradeReq MSHR miss cycles
2836system.l2c.UpgradeReq_mshr_miss_latency::total 18067500 # number of UpgradeReq MSHR miss cycles
2837system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1886000 # number of SCUpgradeReq MSHR miss cycles
2838system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1373500 # number of SCUpgradeReq MSHR miss cycles
2839system.l2c.SCUpgradeReq_mshr_miss_latency::total 3259500 # number of SCUpgradeReq MSHR miss cycles
2840system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1469562000 # number of ReadExReq MSHR miss cycles
2841system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 740230501 # number of ReadExReq MSHR miss cycles
2842system.l2c.ReadExReq_mshr_miss_latency::total 2209792501 # number of ReadExReq MSHR miss cycles
2843system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 22676000 # number of ReadSharedReq MSHR miss cycles
2844system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles
2845system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2094658500 # number of ReadSharedReq MSHR miss cycles
2846system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1096464000 # number of ReadSharedReq MSHR miss cycles
2847system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14644634459 # number of ReadSharedReq MSHR miss cycles
2848system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 3806500 # number of ReadSharedReq MSHR miss cycles
2849system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 351259500 # number of ReadSharedReq MSHR miss cycles
2850system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 262522001 # number of ReadSharedReq MSHR miss cycles
2851system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 810514090 # number of ReadSharedReq MSHR miss cycles
2852system.l2c.ReadSharedReq_mshr_miss_latency::total 19286615050 # number of ReadSharedReq MSHR miss cycles
2853system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 22676000 # number of demand (read+write) MSHR miss cycles
2854system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles
2855system.l2c.demand_mshr_miss_latency::cpu0.inst 2094658500 # number of demand (read+write) MSHR miss cycles
2856system.l2c.demand_mshr_miss_latency::cpu0.data 2566026000 # number of demand (read+write) MSHR miss cycles
2857system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14644634459 # number of demand (read+write) MSHR miss cycles
2858system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3806500 # number of demand (read+write) MSHR miss cycles
2859system.l2c.demand_mshr_miss_latency::cpu1.inst 351259500 # number of demand (read+write) MSHR miss cycles
2860system.l2c.demand_mshr_miss_latency::cpu1.data 1002752502 # number of demand (read+write) MSHR miss cycles
2861system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 810514090 # number of demand (read+write) MSHR miss cycles
2862system.l2c.demand_mshr_miss_latency::total 21496407551 # number of demand (read+write) MSHR miss cycles
2863system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 22676000 # number of overall MSHR miss cycles
2864system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles
2865system.l2c.overall_mshr_miss_latency::cpu0.inst 2094658500 # number of overall MSHR miss cycles
2866system.l2c.overall_mshr_miss_latency::cpu0.data 2566026000 # number of overall MSHR miss cycles
2867system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14644634459 # number of overall MSHR miss cycles
2868system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3806500 # number of overall MSHR miss cycles
2869system.l2c.overall_mshr_miss_latency::cpu1.inst 351259500 # number of overall MSHR miss cycles
2870system.l2c.overall_mshr_miss_latency::cpu1.data 1002752502 # number of overall MSHR miss cycles
2871system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 810514090 # number of overall MSHR miss cycles
2872system.l2c.overall_mshr_miss_latency::total 21496407551 # number of overall MSHR miss cycles
2873system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 228848500 # number of ReadReq MSHR uncacheable cycles
2874system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4071417000 # number of ReadReq MSHR uncacheable cycles
2875system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7882500 # number of ReadReq MSHR uncacheable cycles
2876system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2118238500 # number of ReadReq MSHR uncacheable cycles
2877system.l2c.ReadReq_mshr_uncacheable_latency::total 6426386500 # number of ReadReq MSHR uncacheable cycles
2878system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500 # number of overall MSHR uncacheable cycles
2879system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4071417000 # number of overall MSHR uncacheable cycles
2880system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7882500 # number of overall MSHR uncacheable cycles
2881system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2118238500 # number of overall MSHR uncacheable cycles
2882system.l2c.overall_mshr_uncacheable_latency::total 6426386500 # number of overall MSHR uncacheable cycles
2883system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2884system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2885system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.013009 # mshr miss rate for UpgradeReq accesses
2886system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.040159 # mshr miss rate for UpgradeReq accesses
2887system.l2c.UpgradeReq_mshr_miss_rate::total 0.016199 # mshr miss rate for UpgradeReq accesses
2888system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.025115 # mshr miss rate for SCUpgradeReq accesses
2889system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.023701 # mshr miss rate for SCUpgradeReq accesses
2890system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.024465 # mshr miss rate for SCUpgradeReq accesses
2891system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727448 # mshr miss rate for ReadExReq accesses
2892system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853529 # mshr miss rate for ReadExReq accesses
2893system.l2c.ReadExReq_mshr_miss_rate::total 0.777221 # mshr miss rate for ReadExReq accesses
2894system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for ReadSharedReq accesses
2895system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for ReadSharedReq accesses
2896system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for ReadSharedReq accesses
2897system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.136982 # mshr miss rate for ReadSharedReq accesses
2898system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for ReadSharedReq accesses
2899system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for ReadSharedReq accesses
2900system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for ReadSharedReq accesses
2901system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.112265 # mshr miss rate for ReadSharedReq accesses
2902system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for ReadSharedReq accesses
2903system.l2c.ReadSharedReq_mshr_miss_rate::total 0.434107 # mshr miss rate for ReadSharedReq accesses
2904system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for demand accesses
2905system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for demand accesses
2906system.l2c.demand_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for demand accesses
2907system.l2c.demand_mshr_miss_rate::cpu0.data 0.240730 # mshr miss rate for demand accesses
2908system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for demand accesses
2909system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for demand accesses
2910system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for demand accesses
2911system.l2c.demand_mshr_miss_rate::cpu1.data 0.406886 # mshr miss rate for demand accesses
2912system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for demand accesses
2913system.l2c.demand_mshr_miss_rate::total 0.454412 # mshr miss rate for demand accesses
2914system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for overall accesses
2915system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for overall accesses
2916system.l2c.overall_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for overall accesses
2917system.l2c.overall_mshr_miss_rate::cpu0.data 0.240730 # mshr miss rate for overall accesses
2918system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for overall accesses
2919system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for overall accesses
2920system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for overall accesses
2921system.l2c.overall_mshr_miss_rate::cpu1.data 0.406886 # mshr miss rate for overall accesses
2922system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for overall accesses
2923system.l2c.overall_mshr_miss_rate::total 0.454412 # mshr miss rate for overall accesses
2924system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23063.492063 # average UpgradeReq mshr miss latency
2925system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21418.454936 # average UpgradeReq mshr miss latency
2926system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22584.375000 # average UpgradeReq mshr miss latency
2927system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26563.380282 # average SCUpgradeReq mshr miss latency
2928system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24096.491228 # average SCUpgradeReq mshr miss latency
2929system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25464.843750 # average SCUpgradeReq mshr miss latency
2930system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129705.383936 # average ReadExReq mshr miss latency
2931system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85368.527390 # average ReadExReq mshr miss latency
2932system.l2c.ReadExReq_avg_mshr_miss_latency::total 110484.100845 # average ReadExReq mshr miss latency
2933system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average ReadSharedReq mshr miss latency
2934system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency
2935system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average ReadSharedReq mshr miss latency
2936system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 109547.806974 # average ReadSharedReq mshr miss latency
2937system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average ReadSharedReq mshr miss latency
2938system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average ReadSharedReq mshr miss latency
2939system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average ReadSharedReq mshr miss latency
2940system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 151834.587045 # average ReadSharedReq mshr miss latency
2941system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average ReadSharedReq mshr miss latency
2942system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108593.359665 # average ReadSharedReq mshr miss latency
2943system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency
2944system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
2945system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency
2946system.l2c.demand_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency
2947system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency
2948system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency
2949system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency
2950system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency
2951system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency
2952system.l2c.demand_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency
2953system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency
2954system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
2955system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency
2956system.l2c.overall_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency
2957system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency
2958system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency
2959system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency
2960system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency
2961system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency
2962system.l2c.overall_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency
2963system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency
2964system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197862.516402 # average ReadReq mshr uncacheable latency
2965system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average ReadReq mshr uncacheable latency
2966system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146895.873786 # average ReadReq mshr uncacheable latency
2967system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167414.851769 # average ReadReq mshr uncacheable latency
2968system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency
2969system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102176.249153 # average overall mshr uncacheable latency
2970system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average overall mshr uncacheable latency
2971system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80922.925581 # average overall mshr uncacheable latency
2972system.l2c.overall_avg_mshr_uncacheable_latency::total 92583.220481 # average overall mshr uncacheable latency
2973system.membus.snoop_filter.tot_requests 519453 # Total number of requests made to the snoop filter.
2974system.membus.snoop_filter.hit_single_requests 291586 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2975system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2976system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2977system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2978system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2979system.membus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
2980system.membus.trans_dist::ReadReq 38386 # Transaction distribution
2981system.membus.trans_dist::ReadResp 216245 # Transaction distribution
2982system.membus.trans_dist::WriteReq 31026 # Transaction distribution
2983system.membus.trans_dist::WriteResp 31026 # Transaction distribution
2984system.membus.trans_dist::WritebackDirty 141787 # Transaction distribution
2985system.membus.trans_dist::CleanEvict 20009 # Transaction distribution
2986system.membus.trans_dist::UpgradeReq 64008 # Transaction distribution
2987system.membus.trans_dist::SCUpgradeReq 38952 # Transaction distribution
2988system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2989system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
2990system.membus.trans_dist::ReadExReq 40468 # Transaction distribution
2991system.membus.trans_dist::ReadExResp 19978 # Transaction distribution
2992system.membus.trans_dist::ReadSharedReq 177859 # Transaction distribution
2993system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2994system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
2995system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
2996system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14184 # Packet count per connected master and slave (bytes)
2997system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660292 # Packet count per connected master and slave (bytes)
2998system.membus.pkt_count_system.l2c.mem_side::total 782434 # Packet count per connected master and slave (bytes)
2999system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes)
3000system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes)
3001system.membus.pkt_count::total 855389 # Packet count per connected master and slave (bytes)
3002system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
3003system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes)
3004system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28368 # Cumulative packet size per connected master and slave (bytes)
3005system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19616228 # Cumulative packet size per connected master and slave (bytes)
3006system.membus.pkt_size_system.l2c.mem_side::total 19808736 # Cumulative packet size per connected master and slave (bytes)
3007system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
3008system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
3009system.membus.pkt_size::total 22126880 # Cumulative packet size per connected master and slave (bytes)
3010system.membus.snoops 123082 # Total snoops (count)
3011system.membus.snoopTraffic 37120 # Total snoop traffic (bytes)
3012system.membus.snoop_fanout::samples 426925 # Request fanout histogram
3013system.membus.snoop_fanout::mean 0.011573 # Request fanout histogram
3014system.membus.snoop_fanout::stdev 0.106956 # Request fanout histogram
3015system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3016system.membus.snoop_fanout::0 421984 98.84% 98.84% # Request fanout histogram
3017system.membus.snoop_fanout::1 4941 1.16% 100.00% # Request fanout histogram
3018system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3019system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3020system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3021system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3022system.membus.snoop_fanout::total 426925 # Request fanout histogram
3023system.membus.reqLayer0.occupancy 95052999 # Layer occupancy (ticks)
3024system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3025system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks)
3026system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3027system.membus.reqLayer2.occupancy 12480499 # Layer occupancy (ticks)
3028system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3029system.membus.reqLayer5.occupancy 1015492813 # Layer occupancy (ticks)
3030system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3031system.membus.respLayer2.occupancy 1151697269 # Layer occupancy (ticks)
3032system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3033system.membus.respLayer3.occupancy 1408128 # Layer occupancy (ticks)
3034system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3035system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3036system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3037system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3038system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3039system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3040system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3041system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3042system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3043system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3044system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3045system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3046system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3047system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3048system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3049system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3050system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3051system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3052system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3053system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3054system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3055system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
3056system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
3057system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

3073system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
3074system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3075system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3076system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
3077system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3078system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
3079system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
3080system.realview.ethernet.droppedPackets 0 # number of packets dropped
3081system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3082system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3083system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3084system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3085system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3086system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3087system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3088system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3089system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3090system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3091system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3092system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3093system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3094system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3095system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3096system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3097system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3098system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3099system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3100system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3101system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3102system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3103system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3104system.toL2Bus.snoop_filter.tot_requests 1122951 # Total number of requests made to the snoop filter.
3105system.toL2Bus.snoop_filter.hit_single_requests 592347 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3106system.toL2Bus.snoop_filter.hit_multi_requests 209143 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3107system.toL2Bus.snoop_filter.tot_snoops 29689 # Total number of snoops made to the snoop filter.
3108system.toL2Bus.snoop_filter.hit_single_snoops 28433 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3109system.toL2Bus.snoop_filter.hit_multi_snoops 1256 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3110system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states
3111system.toL2Bus.trans_dist::ReadReq 38389 # Transaction distribution
3112system.toL2Bus.trans_dist::ReadResp 568851 # Transaction distribution
3113system.toL2Bus.trans_dist::WriteReq 31026 # Transaction distribution
3114system.toL2Bus.trans_dist::WriteResp 31026 # Transaction distribution
3115system.toL2Bus.trans_dist::WritebackDirty 374622 # Transaction distribution
3116system.toL2Bus.trans_dist::CleanEvict 155080 # Transaction distribution
3117system.toL2Bus.trans_dist::UpgradeReq 112572 # Transaction distribution
3118system.toL2Bus.trans_dist::SCUpgradeReq 44056 # Transaction distribution
3119system.toL2Bus.trans_dist::UpgradeResp 156628 # Transaction distribution
3120system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
3121system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution
3122system.toL2Bus.trans_dist::ReadExReq 51647 # Transaction distribution
3123system.toL2Bus.trans_dist::ReadExResp 51647 # Transaction distribution
3124system.toL2Bus.trans_dist::ReadSharedReq 530464 # Transaction distribution
3125system.toL2Bus.trans_dist::InvalidateReq 4356 # Transaction distribution
3126system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1342563 # Packet count per connected master and slave (bytes)
3127system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408877 # Packet count per connected master and slave (bytes)
3128system.toL2Bus.pkt_count::total 1751440 # Packet count per connected master and slave (bytes)
3129system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38341228 # Cumulative packet size per connected master and slave (bytes)
3130system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7151796 # Cumulative packet size per connected master and slave (bytes)
3131system.toL2Bus.pkt_size::total 45493024 # Cumulative packet size per connected master and slave (bytes)
3132system.toL2Bus.snoops 399228 # Total snoops (count)
3133system.toL2Bus.snoopTraffic 16183244 # Total snoop traffic (bytes)
3134system.toL2Bus.snoop_fanout::samples 957878 # Request fanout histogram
3135system.toL2Bus.snoop_fanout::mean 0.406657 # Request fanout histogram
3136system.toL2Bus.snoop_fanout::stdev 0.493872 # Request fanout histogram
3137system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3138system.toL2Bus.snoop_fanout::0 569606 59.47% 59.47% # Request fanout histogram
3139system.toL2Bus.snoop_fanout::1 387016 40.40% 99.87% # Request fanout histogram
3140system.toL2Bus.snoop_fanout::2 1256 0.13% 100.00% # Request fanout histogram
3141system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3142system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3143system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3144system.toL2Bus.snoop_fanout::total 957878 # Request fanout histogram
3145system.toL2Bus.reqLayer0.occupancy 953761642 # Layer occupancy (ticks)
3146system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3147system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks)
3148system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3149system.toL2Bus.respLayer0.occupancy 722683237 # Layer occupancy (ticks)
3150system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3151system.toL2Bus.respLayer1.occupancy 286574903 # Layer occupancy (ticks)
3152system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3153
3154---------- End Simulation Statistics ----------