1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.647778 # Number of seconds simulated
4sim_ticks 2647778082500 # Number of ticks simulated
5final_tick 2647778082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 109262 # Simulator instruction rate (inst/s)
8host_op_rate 132319 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2267003011 # Simulator tick rate (ticks/s)
10host_mem_usage 618500 # Number of bytes of host memory used
11host_seconds 1167.96 # Real time elapsed on the host
12sim_insts 127613917 # Number of instructions simulated
13sim_ops 154544077 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.dtb.walker 8192 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 1505216 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 1244784 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8319232 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.dtb.walker 1920 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 374976 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 749140 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 607232 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
27system.physmem.bytes_read::total 12811716 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 1505216 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 374976 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 1880192 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 9040448 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
34system.physmem.bytes_written::total 9058012 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 128 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 23519 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 19972 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 129988 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 30 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.inst 5859 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.data 11726 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.l2cache.prefetcher 9488 # Number of read requests responded to by this memory
44system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
45system.physmem.num_reads::total 200726 # Number of read requests responded to by this memory
46system.physmem.num_writes::writebacks 141257 # Number of write requests responded to by this memory
47system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
49system.physmem.num_writes::total 145648 # Number of write requests responded to by this memory
50system.physmem.bw_read::cpu0.dtb.walker 3094 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.inst 568483 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.data 470124 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.l2cache.prefetcher 3141967 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.dtb.walker 725 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.inst 141619 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.data 282932 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.l2cache.prefetcher 229336 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::realview.ide 363 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::total 4838667 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_inst_read::cpu0.inst 568483 # Instruction read bandwidth from this memory (bytes/s)
62system.physmem.bw_inst_read::cpu1.inst 141619 # Instruction read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::total 710102 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_write::writebacks 3414353 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_write::cpu0.data 6618 # Write bandwidth from this memory (bytes/s)
66system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::total 3420986 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_total::writebacks 3414353 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.dtb.walker 3094 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.inst 568483 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.data 476742 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.l2cache.prefetcher 3141967 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu1.dtb.walker 725 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu1.inst 141619 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.data 282947 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.l2cache.prefetcher 229336 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::realview.ide 363 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::total 8259653 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.readReqs 200726 # Number of read requests accepted
81system.physmem.writeReqs 145648 # Number of write requests accepted
82system.physmem.readBursts 200726 # Number of DRAM read bursts, including those serviced by the write queue
83system.physmem.writeBursts 145648 # Number of DRAM write bursts, including those merged in the write queue
84system.physmem.bytesReadDRAM 12837568 # Total number of bytes read from DRAM
85system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue
86system.physmem.bytesWritten 9070080 # Total number of bytes written to DRAM
87system.physmem.bytesReadSys 12811716 # Total read bytes from the system interface side
88system.physmem.bytesWrittenSys 9058012 # Total written bytes from the system interface side
89system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
90system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
91system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
92system.physmem.perBankRdBursts::0 12684 # Per bank write bursts
93system.physmem.perBankRdBursts::1 12558 # Per bank write bursts
94system.physmem.perBankRdBursts::2 12677 # Per bank write bursts
95system.physmem.perBankRdBursts::3 12470 # Per bank write bursts
96system.physmem.perBankRdBursts::4 15173 # Per bank write bursts
97system.physmem.perBankRdBursts::5 12439 # Per bank write bursts
98system.physmem.perBankRdBursts::6 12705 # Per bank write bursts
99system.physmem.perBankRdBursts::7 12895 # Per bank write bursts
100system.physmem.perBankRdBursts::8 12483 # Per bank write bursts
101system.physmem.perBankRdBursts::9 12862 # Per bank write bursts
102system.physmem.perBankRdBursts::10 12103 # Per bank write bursts
103system.physmem.perBankRdBursts::11 11319 # Per bank write bursts
104system.physmem.perBankRdBursts::12 11938 # Per bank write bursts
105system.physmem.perBankRdBursts::13 12281 # Per bank write bursts
106system.physmem.perBankRdBursts::14 12069 # Per bank write bursts
107system.physmem.perBankRdBursts::15 11931 # Per bank write bursts
108system.physmem.perBankWrBursts::0 9144 # Per bank write bursts
109system.physmem.perBankWrBursts::1 9177 # Per bank write bursts
110system.physmem.perBankWrBursts::2 9224 # Per bank write bursts
111system.physmem.perBankWrBursts::3 8920 # Per bank write bursts
112system.physmem.perBankWrBursts::4 8442 # Per bank write bursts
113system.physmem.perBankWrBursts::5 8744 # Per bank write bursts
114system.physmem.perBankWrBursts::6 9263 # Per bank write bursts
115system.physmem.perBankWrBursts::7 9163 # Per bank write bursts
116system.physmem.perBankWrBursts::8 8908 # Per bank write bursts
117system.physmem.perBankWrBursts::9 9183 # Per bank write bursts
118system.physmem.perBankWrBursts::10 8711 # Per bank write bursts
119system.physmem.perBankWrBursts::11 8187 # Per bank write bursts
120system.physmem.perBankWrBursts::12 8717 # Per bank write bursts
121system.physmem.perBankWrBursts::13 8673 # Per bank write bursts
122system.physmem.perBankWrBursts::14 8851 # Per bank write bursts
123system.physmem.perBankWrBursts::15 8413 # Per bank write bursts
124system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
125system.physmem.numWrRetry 30 # Number of times write queue was full causing retry
126system.physmem.totGap 2647777471000 # Total gap between requests
127system.physmem.readPktSize::0 0 # Read request sizes (log2)
128system.physmem.readPktSize::1 0 # Read request sizes (log2)
129system.physmem.readPktSize::2 553 # Read request sizes (log2)
130system.physmem.readPktSize::3 28 # Read request sizes (log2)
131system.physmem.readPktSize::4 0 # Read request sizes (log2)
132system.physmem.readPktSize::5 0 # Read request sizes (log2)
133system.physmem.readPktSize::6 200145 # Read request sizes (log2)
134system.physmem.writePktSize::0 0 # Write request sizes (log2)
135system.physmem.writePktSize::1 0 # Write request sizes (log2)
136system.physmem.writePktSize::2 4391 # Write request sizes (log2)
137system.physmem.writePktSize::3 0 # Write request sizes (log2)
138system.physmem.writePktSize::4 0 # Write request sizes (log2)
139system.physmem.writePktSize::5 0 # Write request sizes (log2)
140system.physmem.writePktSize::6 141257 # Write request sizes (log2)
141system.physmem.rdQLenPdf::0 87468 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::1 62195 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::2 11522 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::3 9750 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::4 7877 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::5 6392 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::6 5324 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::7 4696 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::8 3790 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::9 756 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::10 271 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
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180system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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183system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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188system.physmem.wrQLenPdf::15 2893 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::16 3869 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::17 4699 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::18 5390 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::19 6259 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::20 6658 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::21 7374 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::22 7875 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::23 8716 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::24 8796 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::25 10315 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::26 10815 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::27 9202 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::28 9069 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::29 10663 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::30 8820 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::31 8088 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::32 7749 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::33 548 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::34 428 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::35 304 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::37 198 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::38 181 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::39 150 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::47 155 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::54 77 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::61 64 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::63 90 # What write queue length does an incoming req see
237system.physmem.bytesPerActivate::samples 94963 # Bytes accessed per row activation
238system.physmem.bytesPerActivate::mean 230.695997 # Bytes accessed per row activation
239system.physmem.bytesPerActivate::gmean 131.239554 # Bytes accessed per row activation
240system.physmem.bytesPerActivate::stdev 294.689609 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::0-127 52509 55.29% 55.29% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::128-255 18085 19.04% 74.34% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::256-383 6234 6.56% 80.90% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::384-511 3686 3.88% 84.78% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::512-639 2895 3.05% 87.83% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::640-767 1483 1.56% 89.39% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::768-895 908 0.96% 90.35% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::896-1023 1023 1.08% 91.43% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::1024-1151 8140 8.57% 100.00% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::total 94963 # Bytes accessed per row activation
251system.physmem.rdPerTurnAround::samples 7063 # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::mean 28.398839 # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::stdev 555.406402 # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::0-2047 7061 99.97% 99.97% # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::total 7063 # Reads before turning the bus around for writes
258system.physmem.wrPerTurnAround::samples 7063 # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::mean 20.065128 # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::gmean 18.613340 # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::stdev 12.212436 # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::16-19 5945 84.17% 84.17% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::20-23 392 5.55% 89.72% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::24-27 71 1.01% 90.73% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::28-31 48 0.68% 91.41% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::32-35 279 3.95% 95.36% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::36-39 27 0.38% 95.74% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::40-43 19 0.27% 96.01% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::44-47 25 0.35% 96.36% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::48-51 16 0.23% 96.59% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::52-55 12 0.17% 96.76% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::56-59 3 0.04% 96.80% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::60-63 7 0.10% 96.90% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::64-67 160 2.27% 99.16% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::68-71 6 0.08% 99.25% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::72-75 4 0.06% 99.31% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::76-79 5 0.07% 99.38% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::80-83 7 0.10% 99.48% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::84-87 1 0.01% 99.49% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::92-95 2 0.03% 99.52% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::104-107 4 0.06% 99.60% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::108-111 3 0.04% 99.65% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::128-131 8 0.11% 99.80% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::132-135 1 0.01% 99.82% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::136-139 1 0.01% 99.83% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::144-147 1 0.01% 99.87% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::156-159 2 0.03% 99.90% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::160-163 4 0.06% 99.96% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::172-175 2 0.03% 99.99% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::total 7063 # Writes before turning the bus around for reads
296system.physmem.totQLat 5391615341 # Total ticks spent queuing
297system.physmem.totMemAccLat 9152621591 # Total ticks spent from burst creation until serviced by the DRAM
298system.physmem.totBusLat 1002935000 # Total ticks spent in databus transfers
299system.physmem.avgQLat 26879.19 # Average queueing delay per DRAM burst
300system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
301system.physmem.avgMemAccLat 45629.19 # Average memory access latency per DRAM burst
302system.physmem.avgRdBW 4.85 # Average DRAM read bandwidth in MiByte/s
303system.physmem.avgWrBW 3.43 # Average achieved write bandwidth in MiByte/s
304system.physmem.avgRdBWSys 4.84 # Average system read bandwidth in MiByte/s
305system.physmem.avgWrBWSys 3.42 # Average system write bandwidth in MiByte/s
306system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
307system.physmem.busUtil 0.06 # Data bus utilization in percentage
308system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
309system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
310system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
311system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing
312system.physmem.readRowHits 166580 # Number of row buffer hits during reads
313system.physmem.writeRowHits 80763 # Number of row buffer hits during writes
314system.physmem.readRowHitRate 83.05 # Row buffer hit rate for reads
315system.physmem.writeRowHitRate 56.97 # Row buffer hit rate for writes
316system.physmem.avgGap 7644273.16 # Average gap between requests
317system.physmem.pageHitRate 72.25 # Row buffer hit rate, read and write combined
318system.physmem_0.actEnergy 370341720 # Energy for activate commands per rank (pJ)
319system.physmem_0.preEnergy 202071375 # Energy for precharge commands per rank (pJ)
320system.physmem_0.readEnergy 808080000 # Energy for read commands per rank (pJ)
321system.physmem_0.writeEnergy 467058960 # Energy for write commands per rank (pJ)
322system.physmem_0.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ)
323system.physmem_0.actBackEnergy 79567681680 # Energy for active background per rank (pJ)
324system.physmem_0.preBackEnergy 1518869897250 # Energy for precharge background per rank (pJ)
325system.physmem_0.totalEnergy 1773225027465 # Total energy per rank (pJ)
326system.physmem_0.averagePower 669.703351 # Core power per rank (mW)
327system.physmem_0.memoryStateTime::IDLE 2526645938707 # Time in different power states
328system.physmem_0.memoryStateTime::REF 88415080000 # Time in different power states
329system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
330system.physmem_0.memoryStateTime::ACT 32716967293 # Time in different power states
331system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
332system.physmem_1.actEnergy 347578560 # Energy for activate commands per rank (pJ)
333system.physmem_1.preEnergy 189651000 # Energy for precharge commands per rank (pJ)
334system.physmem_1.readEnergy 756490800 # Energy for read commands per rank (pJ)
335system.physmem_1.writeEnergy 451286640 # Energy for write commands per rank (pJ)
336system.physmem_1.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ)
337system.physmem_1.actBackEnergy 78874475895 # Energy for active background per rank (pJ)
338system.physmem_1.preBackEnergy 1519477980750 # Energy for precharge background per rank (pJ)
339system.physmem_1.totalEnergy 1773037360125 # Total energy per rank (pJ)
340system.physmem_1.averagePower 669.632470 # Core power per rank (mW)
341system.physmem_1.memoryStateTime::IDLE 2527659145749 # Time in different power states
342system.physmem_1.memoryStateTime::REF 88415080000 # Time in different power states
343system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
344system.physmem_1.memoryStateTime::ACT 31702650501 # Time in different power states
345system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
346system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
347system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
348system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
349system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory
350system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory
351system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory
352system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
353system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
354system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
355system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
356system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s)
357system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s)
358system.realview.nvmem.bw_read::total 508 # Total read bandwidth from this memory (bytes/s)
359system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s)
360system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s)
361system.realview.nvmem.bw_inst_read::total 508 # Instruction read bandwidth from this memory (bytes/s)
362system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s)
363system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s)
364system.realview.nvmem.bw_total::total 508 # Total bandwidth to/from this memory (bytes/s)
365system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
366system.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
367system.bridge.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
368system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
369system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
370system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
371system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
372system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
373system.cf0.dma_write_txs 631 # Number of DMA write transactions.
374system.cpu0.branchPred.lookups 34732065 # Number of BP lookups
375system.cpu0.branchPred.condPredicted 16497595 # Number of conditional branches predicted
376system.cpu0.branchPred.condIncorrect 1496295 # Number of conditional branches incorrect
377system.cpu0.branchPred.BTBLookups 19609177 # Number of BTB lookups
378system.cpu0.branchPred.BTBHits 10269070 # Number of BTB hits
379system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
380system.cpu0.branchPred.BTBHitPct 52.368695 # BTB Hit Percentage
381system.cpu0.branchPred.usedRAS 11117365 # Number of times the RAS was used to get a target.
382system.cpu0.branchPred.RASInCorrect 739154 # Number of incorrect RAS predictions.
383system.cpu0.branchPred.indirectLookups 4170441 # Number of indirect predictor lookups.
384system.cpu0.branchPred.indirectHits 3984607 # Number of indirect target hits.
385system.cpu0.branchPred.indirectMisses 185834 # Number of indirect misses.
386system.cpu0.branchPredindirectMispredicted 94839 # Number of mispredicted indirect branches.
387system.cpu_clk_domain.clock 500 # Clock period in ticks
388system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
389system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

410system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
411system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
412system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
413system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
414system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
415system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
416system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
417system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
418system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
419system.cpu0.dtb.walker.walks 65243 # Table walker walks requested
420system.cpu0.dtb.walker.walksShort 65243 # Table walker walks initiated with short descriptors
421system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44492 # Level at which table walker walks with short descriptors terminate
422system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20751 # Level at which table walker walks with short descriptors terminate
423system.cpu0.dtb.walker.walkWaitTime::samples 65243 # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::0 65243 100.00% 100.00% # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::total 65243 # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkCompletionTime::samples 6699 # Table walker service (enqueue to completion) latency
427system.cpu0.dtb.walker.walkCompletionTime::mean 12206.821914 # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walkCompletionTime::gmean 11332.778692 # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::stdev 5808.192470 # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::0-16383 6323 94.39% 94.39% # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::16384-32767 330 4.93% 99.31% # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walkCompletionTime::32768-49151 32 0.48% 99.79% # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.10% 99.90% # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.94% # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.04% 99.99% # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::total 6699 # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution
439system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution
440system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution
441system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.27% 77.27% # Table walker page sizes translated
442system.cpu0.dtb.walker.walkPageSizes::1M 1523 22.73% 100.00% # Table walker page sizes translated
443system.cpu0.dtb.walker.walkPageSizes::total 6699 # Table walker page sizes translated
444system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65243 # Table walker requests started/completed, data/inst
445system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
446system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65243 # Table walker requests started/completed, data/inst
447system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6699 # Table walker requests started/completed, data/inst
448system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
449system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6699 # Table walker requests started/completed, data/inst
450system.cpu0.dtb.walker.walkRequestOrigin::total 71942 # Table walker requests started/completed, data/inst
451system.cpu0.dtb.inst_hits 0 # ITB inst hits
452system.cpu0.dtb.inst_misses 0 # ITB inst misses
453system.cpu0.dtb.read_hits 23418517 # DTB read hits
454system.cpu0.dtb.read_misses 59363 # DTB read misses
455system.cpu0.dtb.write_hits 17357852 # DTB write hits
456system.cpu0.dtb.write_misses 5880 # DTB write misses
457system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
458system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
459system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
460system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
461system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB
462system.cpu0.dtb.align_faults 1178 # Number of TLB faults due to alignment restrictions
463system.cpu0.dtb.prefetch_faults 1722 # Number of TLB faults due to prefetch
464system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
465system.cpu0.dtb.perms_faults 516 # Number of TLB faults due to permissions restrictions
466system.cpu0.dtb.read_accesses 23477880 # DTB read accesses
467system.cpu0.dtb.write_accesses 17363732 # DTB write accesses
468system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
469system.cpu0.dtb.hits 40776369 # DTB hits
470system.cpu0.dtb.misses 65243 # DTB misses
471system.cpu0.dtb.accesses 40841612 # DTB accesses
472system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
473system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
475system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

494system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
495system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
496system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
497system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
498system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
499system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
500system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
501system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
502system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
503system.cpu0.itb.walker.walks 4001 # Table walker walks requested
504system.cpu0.itb.walker.walksShort 4001 # Table walker walks initiated with short descriptors
505system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate
506system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3695 # Level at which table walker walks with short descriptors terminate
507system.cpu0.itb.walker.walkWaitTime::samples 4001 # Table walker wait (enqueue to first request) latency
508system.cpu0.itb.walker.walkWaitTime::0 4001 100.00% 100.00% # Table walker wait (enqueue to first request) latency
509system.cpu0.itb.walker.walkWaitTime::total 4001 # Table walker wait (enqueue to first request) latency
510system.cpu0.itb.walker.walkCompletionTime::samples 2427 # Table walker service (enqueue to completion) latency
511system.cpu0.itb.walker.walkCompletionTime::mean 12648.125258 # Table walker service (enqueue to completion) latency
512system.cpu0.itb.walker.walkCompletionTime::gmean 11968.911523 # Table walker service (enqueue to completion) latency
513system.cpu0.itb.walker.walkCompletionTime::stdev 4734.087286 # Table walker service (enqueue to completion) latency
514system.cpu0.itb.walker.walkCompletionTime::0-8191 373 15.37% 15.37% # Table walker service (enqueue to completion) latency
515system.cpu0.itb.walker.walkCompletionTime::8192-16383 1885 77.67% 93.04% # Table walker service (enqueue to completion) latency
516system.cpu0.itb.walker.walkCompletionTime::16384-24575 118 4.86% 97.90% # Table walker service (enqueue to completion) latency
517system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.11% 99.01% # Table walker service (enqueue to completion) latency
518system.cpu0.itb.walker.walkCompletionTime::32768-40959 22 0.91% 99.92% # Table walker service (enqueue to completion) latency
519system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
520system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
521system.cpu0.itb.walker.walkCompletionTime::total 2427 # Table walker service (enqueue to completion) latency
522system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution
523system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution
524system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution
525system.cpu0.itb.walker.walkPageSizes::4K 2126 87.60% 87.60% # Table walker page sizes translated
526system.cpu0.itb.walker.walkPageSizes::1M 301 12.40% 100.00% # Table walker page sizes translated
527system.cpu0.itb.walker.walkPageSizes::total 2427 # Table walker page sizes translated
528system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
529system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4001 # Table walker requests started/completed, data/inst
530system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4001 # Table walker requests started/completed, data/inst
531system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
532system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2427 # Table walker requests started/completed, data/inst
533system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2427 # Table walker requests started/completed, data/inst
534system.cpu0.itb.walker.walkRequestOrigin::total 6428 # Table walker requests started/completed, data/inst
535system.cpu0.itb.inst_hits 68314752 # ITB inst hits
536system.cpu0.itb.inst_misses 4001 # ITB inst misses
537system.cpu0.itb.read_hits 0 # DTB read hits
538system.cpu0.itb.read_misses 0 # DTB read misses
539system.cpu0.itb.write_hits 0 # DTB write hits
540system.cpu0.itb.write_misses 0 # DTB write misses
541system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
542system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
543system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
544system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
545system.cpu0.itb.flush_entries 2164 # Number of entries that have been flushed from TLB
546system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
547system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
548system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
549system.cpu0.itb.perms_faults 7135 # Number of TLB faults due to permissions restrictions
550system.cpu0.itb.read_accesses 0 # DTB read accesses
551system.cpu0.itb.write_accesses 0 # DTB write accesses
552system.cpu0.itb.inst_accesses 68318753 # ITB inst accesses
553system.cpu0.itb.hits 68314752 # DTB hits
554system.cpu0.itb.misses 4001 # DTB misses
555system.cpu0.itb.accesses 68318753 # DTB accesses
556system.cpu0.numPwrStateTransitions 4126 # Number of power state transitions
557system.cpu0.pwrStateClkGateDist::samples 2063 # Distribution of time spent in the clock gated state
558system.cpu0.pwrStateClkGateDist::mean 1227700157.144935 # Distribution of time spent in the clock gated state
559system.cpu0.pwrStateClkGateDist::stdev 21500702795.368797 # Distribution of time spent in the clock gated state
560system.cpu0.pwrStateClkGateDist::underflows 1198 58.07% 58.07% # Distribution of time spent in the clock gated state
561system.cpu0.pwrStateClkGateDist::1000-5e+10 860 41.69% 99.76% # Distribution of time spent in the clock gated state
562system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.81% # Distribution of time spent in the clock gated state
563system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.05% 99.85% # Distribution of time spent in the clock gated state
564system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.15% 100.00% # Distribution of time spent in the clock gated state
565system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
566system.cpu0.pwrStateClkGateDist::max_value 499984309000 # Distribution of time spent in the clock gated state
567system.cpu0.pwrStateClkGateDist::total 2063 # Distribution of time spent in the clock gated state
568system.cpu0.pwrStateResidencyTicks::ON 115032658310 # Cumulative time (in ticks) in various power states
569system.cpu0.pwrStateResidencyTicks::CLK_GATED 2532745424190 # Cumulative time (in ticks) in various power states
570system.cpu0.numCycles 230068064 # number of cpu cycles simulated
571system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
572system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
573system.cpu0.committedInsts 106706103 # Number of instructions committed
574system.cpu0.committedOps 129024022 # Number of ops (including micro ops) committed
575system.cpu0.discardedOps 8506641 # Number of ops (including micro ops) which were discarded before commit
576system.cpu0.numFetchSuspends 2063 # Number of times Execute suspended instruction fetching
577system.cpu0.quiesceCycles 5065528558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
578system.cpu0.cpi 2.156091 # CPI: cycles per instruction
579system.cpu0.ipc 0.463802 # IPC: instructions per cycle
580system.cpu0.op_class_0::No_OpClass 2272 0.00% 0.00% # Class of committed instruction
581system.cpu0.op_class_0::IntAlu 87919988 68.14% 68.14% # Class of committed instruction
582system.cpu0.op_class_0::IntMult 105727 0.08% 68.23% # Class of committed instruction
583system.cpu0.op_class_0::IntDiv 0 0.00% 68.23% # Class of committed instruction
584system.cpu0.op_class_0::FloatAdd 0 0.00% 68.23% # Class of committed instruction
585system.cpu0.op_class_0::FloatCmp 0 0.00% 68.23% # Class of committed instruction
586system.cpu0.op_class_0::FloatCvt 0 0.00% 68.23% # Class of committed instruction
587system.cpu0.op_class_0::FloatMult 0 0.00% 68.23% # Class of committed instruction
588system.cpu0.op_class_0::FloatDiv 0 0.00% 68.23% # Class of committed instruction
589system.cpu0.op_class_0::FloatSqrt 0 0.00% 68.23% # Class of committed instruction
590system.cpu0.op_class_0::SimdAdd 0 0.00% 68.23% # Class of committed instruction
591system.cpu0.op_class_0::SimdAddAcc 0 0.00% 68.23% # Class of committed instruction
592system.cpu0.op_class_0::SimdAlu 0 0.00% 68.23% # Class of committed instruction
593system.cpu0.op_class_0::SimdCmp 0 0.00% 68.23% # Class of committed instruction
594system.cpu0.op_class_0::SimdCvt 0 0.00% 68.23% # Class of committed instruction
595system.cpu0.op_class_0::SimdMisc 0 0.00% 68.23% # Class of committed instruction
596system.cpu0.op_class_0::SimdMult 0 0.00% 68.23% # Class of committed instruction
597system.cpu0.op_class_0::SimdMultAcc 0 0.00% 68.23% # Class of committed instruction
598system.cpu0.op_class_0::SimdShift 0 0.00% 68.23% # Class of committed instruction
599system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 68.23% # Class of committed instruction
600system.cpu0.op_class_0::SimdSqrt 0 0.00% 68.23% # Class of committed instruction
601system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 68.23% # Class of committed instruction
602system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 68.23% # Class of committed instruction
603system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 68.23% # Class of committed instruction
604system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 68.23% # Class of committed instruction
605system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 68.23% # Class of committed instruction
606system.cpu0.op_class_0::SimdFloatMisc 7151 0.01% 68.23% # Class of committed instruction
607system.cpu0.op_class_0::SimdFloatMult 0 0.00% 68.23% # Class of committed instruction
608system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 68.23% # Class of committed instruction
609system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 68.23% # Class of committed instruction
610system.cpu0.op_class_0::MemRead 22900542 17.75% 85.98% # Class of committed instruction
611system.cpu0.op_class_0::MemWrite 18088342 14.02% 100.00% # Class of committed instruction
612system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
613system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
614system.cpu0.op_class_0::total 129024022 # Class of committed instruction
615system.cpu0.kern.inst.arm 0 # number of arm instructions executed
616system.cpu0.kern.inst.quiesce 2063 # number of quiesce instructions executed
617system.cpu0.tickCycles 178511666 # Number of cycles that the object actually ticked
618system.cpu0.idleCycles 51556398 # Total number of cycles that the object has spent stopped
619system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
620system.cpu0.dcache.tags.replacements 681177 # number of replacements
621system.cpu0.dcache.tags.tagsinuse 487.337065 # Cycle average of tags in use
622system.cpu0.dcache.tags.total_refs 39381714 # Total number of references to valid blocks.
623system.cpu0.dcache.tags.sampled_refs 681689 # Sample count of references to valid blocks.
624system.cpu0.dcache.tags.avg_refs 57.770793 # Average number of references to valid blocks.
625system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit.
626system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.337065 # Average occupied blocks per requestor
627system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951830 # Average percentage of cache occupancy
628system.cpu0.dcache.tags.occ_percent::total 0.951830 # Average percentage of cache occupancy
629system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
630system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
631system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
632system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id
633system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
634system.cpu0.dcache.tags.tag_accesses 81578447 # Number of tag accesses
635system.cpu0.dcache.tags.data_accesses 81578447 # Number of data accesses
636system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
637system.cpu0.dcache.ReadReq_hits::cpu0.data 21978387 # number of ReadReq hits
638system.cpu0.dcache.ReadReq_hits::total 21978387 # number of ReadReq hits
639system.cpu0.dcache.WriteReq_hits::cpu0.data 16273218 # number of WriteReq hits
640system.cpu0.dcache.WriteReq_hits::total 16273218 # number of WriteReq hits
641system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306177 # number of SoftPFReq hits
642system.cpu0.dcache.SoftPFReq_hits::total 306177 # number of SoftPFReq hits
643system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357355 # number of LoadLockedReq hits
644system.cpu0.dcache.LoadLockedReq_hits::total 357355 # number of LoadLockedReq hits
645system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352292 # number of StoreCondReq hits
646system.cpu0.dcache.StoreCondReq_hits::total 352292 # number of StoreCondReq hits
647system.cpu0.dcache.demand_hits::cpu0.data 38251605 # number of demand (read+write) hits
648system.cpu0.dcache.demand_hits::total 38251605 # number of demand (read+write) hits
649system.cpu0.dcache.overall_hits::cpu0.data 38557782 # number of overall hits
650system.cpu0.dcache.overall_hits::total 38557782 # number of overall hits
651system.cpu0.dcache.ReadReq_misses::cpu0.data 418335 # number of ReadReq misses
652system.cpu0.dcache.ReadReq_misses::total 418335 # number of ReadReq misses
653system.cpu0.dcache.WriteReq_misses::cpu0.data 561531 # number of WriteReq misses
654system.cpu0.dcache.WriteReq_misses::total 561531 # number of WriteReq misses
655system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131453 # number of SoftPFReq misses
656system.cpu0.dcache.SoftPFReq_misses::total 131453 # number of SoftPFReq misses
657system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20802 # number of LoadLockedReq misses
658system.cpu0.dcache.LoadLockedReq_misses::total 20802 # number of LoadLockedReq misses
659system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21460 # number of StoreCondReq misses
660system.cpu0.dcache.StoreCondReq_misses::total 21460 # number of StoreCondReq misses
661system.cpu0.dcache.demand_misses::cpu0.data 979866 # number of demand (read+write) misses
662system.cpu0.dcache.demand_misses::total 979866 # number of demand (read+write) misses
663system.cpu0.dcache.overall_misses::cpu0.data 1111319 # number of overall misses
664system.cpu0.dcache.overall_misses::total 1111319 # number of overall misses
665system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5562272000 # number of ReadReq miss cycles
666system.cpu0.dcache.ReadReq_miss_latency::total 5562272000 # number of ReadReq miss cycles
667system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10028849500 # number of WriteReq miss cycles
668system.cpu0.dcache.WriteReq_miss_latency::total 10028849500 # number of WriteReq miss cycles
669system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328076000 # number of LoadLockedReq miss cycles
670system.cpu0.dcache.LoadLockedReq_miss_latency::total 328076000 # number of LoadLockedReq miss cycles
671system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 523772000 # number of StoreCondReq miss cycles
672system.cpu0.dcache.StoreCondReq_miss_latency::total 523772000 # number of StoreCondReq miss cycles
673system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 516000 # number of StoreCondFailReq miss cycles
674system.cpu0.dcache.StoreCondFailReq_miss_latency::total 516000 # number of StoreCondFailReq miss cycles
675system.cpu0.dcache.demand_miss_latency::cpu0.data 15591121500 # number of demand (read+write) miss cycles
676system.cpu0.dcache.demand_miss_latency::total 15591121500 # number of demand (read+write) miss cycles
677system.cpu0.dcache.overall_miss_latency::cpu0.data 15591121500 # number of overall miss cycles
678system.cpu0.dcache.overall_miss_latency::total 15591121500 # number of overall miss cycles
679system.cpu0.dcache.ReadReq_accesses::cpu0.data 22396722 # number of ReadReq accesses(hits+misses)
680system.cpu0.dcache.ReadReq_accesses::total 22396722 # number of ReadReq accesses(hits+misses)
681system.cpu0.dcache.WriteReq_accesses::cpu0.data 16834749 # number of WriteReq accesses(hits+misses)
682system.cpu0.dcache.WriteReq_accesses::total 16834749 # number of WriteReq accesses(hits+misses)
683system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437630 # number of SoftPFReq accesses(hits+misses)
684system.cpu0.dcache.SoftPFReq_accesses::total 437630 # number of SoftPFReq accesses(hits+misses)
685system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378157 # number of LoadLockedReq accesses(hits+misses)
686system.cpu0.dcache.LoadLockedReq_accesses::total 378157 # number of LoadLockedReq accesses(hits+misses)
687system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373752 # number of StoreCondReq accesses(hits+misses)
688system.cpu0.dcache.StoreCondReq_accesses::total 373752 # number of StoreCondReq accesses(hits+misses)
689system.cpu0.dcache.demand_accesses::cpu0.data 39231471 # number of demand (read+write) accesses
690system.cpu0.dcache.demand_accesses::total 39231471 # number of demand (read+write) accesses
691system.cpu0.dcache.overall_accesses::cpu0.data 39669101 # number of overall (read+write) accesses
692system.cpu0.dcache.overall_accesses::total 39669101 # number of overall (read+write) accesses
693system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.018678 # miss rate for ReadReq accesses
694system.cpu0.dcache.ReadReq_miss_rate::total 0.018678 # miss rate for ReadReq accesses
695system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033355 # miss rate for WriteReq accesses
696system.cpu0.dcache.WriteReq_miss_rate::total 0.033355 # miss rate for WriteReq accesses
697system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300375 # miss rate for SoftPFReq accesses
698system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300375 # miss rate for SoftPFReq accesses
699system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055009 # miss rate for LoadLockedReq accesses
700system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055009 # miss rate for LoadLockedReq accesses
701system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057418 # miss rate for StoreCondReq accesses
702system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057418 # miss rate for StoreCondReq accesses
703system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024977 # miss rate for demand accesses
704system.cpu0.dcache.demand_miss_rate::total 0.024977 # miss rate for demand accesses
705system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028015 # miss rate for overall accesses
706system.cpu0.dcache.overall_miss_rate::total 0.028015 # miss rate for overall accesses
707system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13296.214756 # average ReadReq miss latency
708system.cpu0.dcache.ReadReq_avg_miss_latency::total 13296.214756 # average ReadReq miss latency
709system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17859.832316 # average WriteReq miss latency
710system.cpu0.dcache.WriteReq_avg_miss_latency::total 17859.832316 # average WriteReq miss latency
711system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.368138 # average LoadLockedReq miss latency
712system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.368138 # average LoadLockedReq miss latency
713system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24406.896552 # average StoreCondReq miss latency
714system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24406.896552 # average StoreCondReq miss latency
715system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
716system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
717system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15911.483305 # average overall miss latency
718system.cpu0.dcache.demand_avg_miss_latency::total 15911.483305 # average overall miss latency
719system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14029.384452 # average overall miss latency
720system.cpu0.dcache.overall_avg_miss_latency::total 14029.384452 # average overall miss latency
721system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
722system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
723system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
724system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
725system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
726system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
727system.cpu0.dcache.writebacks::writebacks 681177 # number of writebacks
728system.cpu0.dcache.writebacks::total 681177 # number of writebacks
729system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44450 # number of ReadReq MSHR hits
730system.cpu0.dcache.ReadReq_mshr_hits::total 44450 # number of ReadReq MSHR hits
731system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 246335 # number of WriteReq MSHR hits
732system.cpu0.dcache.WriteReq_mshr_hits::total 246335 # number of WriteReq MSHR hits
733system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14695 # number of LoadLockedReq MSHR hits
734system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14695 # number of LoadLockedReq MSHR hits
735system.cpu0.dcache.demand_mshr_hits::cpu0.data 290785 # number of demand (read+write) MSHR hits
736system.cpu0.dcache.demand_mshr_hits::total 290785 # number of demand (read+write) MSHR hits
737system.cpu0.dcache.overall_mshr_hits::cpu0.data 290785 # number of overall MSHR hits
738system.cpu0.dcache.overall_mshr_hits::total 290785 # number of overall MSHR hits
739system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373885 # number of ReadReq MSHR misses
740system.cpu0.dcache.ReadReq_mshr_misses::total 373885 # number of ReadReq MSHR misses
741system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 315196 # number of WriteReq MSHR misses
742system.cpu0.dcache.WriteReq_mshr_misses::total 315196 # number of WriteReq MSHR misses
743system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98829 # number of SoftPFReq MSHR misses
744system.cpu0.dcache.SoftPFReq_mshr_misses::total 98829 # number of SoftPFReq MSHR misses
745system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6107 # number of LoadLockedReq MSHR misses
746system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6107 # number of LoadLockedReq MSHR misses
747system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21460 # number of StoreCondReq MSHR misses
748system.cpu0.dcache.StoreCondReq_mshr_misses::total 21460 # number of StoreCondReq MSHR misses
749system.cpu0.dcache.demand_mshr_misses::cpu0.data 689081 # number of demand (read+write) MSHR misses
750system.cpu0.dcache.demand_mshr_misses::total 689081 # number of demand (read+write) MSHR misses
751system.cpu0.dcache.overall_mshr_misses::cpu0.data 787910 # number of overall MSHR misses
752system.cpu0.dcache.overall_mshr_misses::total 787910 # number of overall MSHR misses
753system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29629 # number of ReadReq MSHR uncacheable
754system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29629 # number of ReadReq MSHR uncacheable
755system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26357 # number of WriteReq MSHR uncacheable
756system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26357 # number of WriteReq MSHR uncacheable
757system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55986 # number of overall MSHR uncacheable misses
758system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55986 # number of overall MSHR uncacheable misses
759system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4452451000 # number of ReadReq MSHR miss cycles
760system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4452451000 # number of ReadReq MSHR miss cycles
761system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5571993500 # number of WriteReq MSHR miss cycles
762system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5571993500 # number of WriteReq MSHR miss cycles
763system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1619437000 # number of SoftPFReq MSHR miss cycles
764system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1619437000 # number of SoftPFReq MSHR miss cycles
765system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94023500 # number of LoadLockedReq MSHR miss cycles
766system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94023500 # number of LoadLockedReq MSHR miss cycles
767system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 502325000 # number of StoreCondReq MSHR miss cycles
768system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 502325000 # number of StoreCondReq MSHR miss cycles
769system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 503000 # number of StoreCondFailReq MSHR miss cycles
770system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 503000 # number of StoreCondFailReq MSHR miss cycles
771system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10024444500 # number of demand (read+write) MSHR miss cycles
772system.cpu0.dcache.demand_mshr_miss_latency::total 10024444500 # number of demand (read+write) MSHR miss cycles
773system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11643881500 # number of overall MSHR miss cycles
774system.cpu0.dcache.overall_mshr_miss_latency::total 11643881500 # number of overall MSHR miss cycles
775system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6101487500 # number of ReadReq MSHR uncacheable cycles
776system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6101487500 # number of ReadReq MSHR uncacheable cycles
777system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6101487500 # number of overall MSHR uncacheable cycles
778system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6101487500 # number of overall MSHR uncacheable cycles
779system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016694 # mshr miss rate for ReadReq accesses
780system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016694 # mshr miss rate for ReadReq accesses
781system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018723 # mshr miss rate for WriteReq accesses
782system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018723 # mshr miss rate for WriteReq accesses
783system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225828 # mshr miss rate for SoftPFReq accesses
784system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225828 # mshr miss rate for SoftPFReq accesses
785system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016149 # mshr miss rate for LoadLockedReq accesses
786system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016149 # mshr miss rate for LoadLockedReq accesses
787system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057418 # mshr miss rate for StoreCondReq accesses
788system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057418 # mshr miss rate for StoreCondReq accesses
789system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017564 # mshr miss rate for demand accesses
790system.cpu0.dcache.demand_mshr_miss_rate::total 0.017564 # mshr miss rate for demand accesses
791system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019862 # mshr miss rate for overall accesses
792system.cpu0.dcache.overall_mshr_miss_rate::total 0.019862 # mshr miss rate for overall accesses
793system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11908.610937 # average ReadReq mshr miss latency
794system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11908.610937 # average ReadReq mshr miss latency
795system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17677.868691 # average WriteReq mshr miss latency
796system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17677.868691 # average WriteReq mshr miss latency
797system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16386.253023 # average SoftPFReq mshr miss latency
798system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16386.253023 # average SoftPFReq mshr miss latency
799system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15396.020960 # average LoadLockedReq mshr miss latency
800system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15396.020960 # average LoadLockedReq mshr miss latency
801system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23407.502330 # average StoreCondReq mshr miss latency
802system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23407.502330 # average StoreCondReq mshr miss latency
803system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
804system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
805system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14547.556093 # average overall mshr miss latency
806system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14547.556093 # average overall mshr miss latency
807system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14778.187230 # average overall mshr miss latency
808system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14778.187230 # average overall mshr miss latency
809system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205929.579129 # average ReadReq mshr uncacheable latency
810system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205929.579129 # average ReadReq mshr uncacheable latency
811system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 108982.379523 # average overall mshr uncacheable latency
812system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 108982.379523 # average overall mshr uncacheable latency
813system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
814system.cpu0.icache.tags.replacements 1887196 # number of replacements
815system.cpu0.icache.tags.tagsinuse 511.757846 # Cycle average of tags in use
816system.cpu0.icache.tags.total_refs 66419655 # Total number of references to valid blocks.
817system.cpu0.icache.tags.sampled_refs 1887708 # Sample count of references to valid blocks.
818system.cpu0.icache.tags.avg_refs 35.185344 # Average number of references to valid blocks.
819system.cpu0.icache.tags.warmup_cycle 6638125000 # Cycle when the warmup percentage was hit.
820system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757846 # Average occupied blocks per requestor
821system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy
822system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy
823system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
824system.cpu0.icache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
825system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
826system.cpu0.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
827system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
828system.cpu0.icache.tags.tag_accesses 138502472 # Number of tag accesses
829system.cpu0.icache.tags.data_accesses 138502472 # Number of data accesses
830system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
831system.cpu0.icache.ReadReq_hits::cpu0.inst 66419655 # number of ReadReq hits
832system.cpu0.icache.ReadReq_hits::total 66419655 # number of ReadReq hits
833system.cpu0.icache.demand_hits::cpu0.inst 66419655 # number of demand (read+write) hits
834system.cpu0.icache.demand_hits::total 66419655 # number of demand (read+write) hits
835system.cpu0.icache.overall_hits::cpu0.inst 66419655 # number of overall hits
836system.cpu0.icache.overall_hits::total 66419655 # number of overall hits
837system.cpu0.icache.ReadReq_misses::cpu0.inst 1887721 # number of ReadReq misses
838system.cpu0.icache.ReadReq_misses::total 1887721 # number of ReadReq misses
839system.cpu0.icache.demand_misses::cpu0.inst 1887721 # number of demand (read+write) misses
840system.cpu0.icache.demand_misses::total 1887721 # number of demand (read+write) misses
841system.cpu0.icache.overall_misses::cpu0.inst 1887721 # number of overall misses
842system.cpu0.icache.overall_misses::total 1887721 # number of overall misses
843system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17836461000 # number of ReadReq miss cycles
844system.cpu0.icache.ReadReq_miss_latency::total 17836461000 # number of ReadReq miss cycles
845system.cpu0.icache.demand_miss_latency::cpu0.inst 17836461000 # number of demand (read+write) miss cycles
846system.cpu0.icache.demand_miss_latency::total 17836461000 # number of demand (read+write) miss cycles
847system.cpu0.icache.overall_miss_latency::cpu0.inst 17836461000 # number of overall miss cycles
848system.cpu0.icache.overall_miss_latency::total 17836461000 # number of overall miss cycles
849system.cpu0.icache.ReadReq_accesses::cpu0.inst 68307376 # number of ReadReq accesses(hits+misses)
850system.cpu0.icache.ReadReq_accesses::total 68307376 # number of ReadReq accesses(hits+misses)
851system.cpu0.icache.demand_accesses::cpu0.inst 68307376 # number of demand (read+write) accesses
852system.cpu0.icache.demand_accesses::total 68307376 # number of demand (read+write) accesses
853system.cpu0.icache.overall_accesses::cpu0.inst 68307376 # number of overall (read+write) accesses
854system.cpu0.icache.overall_accesses::total 68307376 # number of overall (read+write) accesses
855system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027636 # miss rate for ReadReq accesses
856system.cpu0.icache.ReadReq_miss_rate::total 0.027636 # miss rate for ReadReq accesses
857system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027636 # miss rate for demand accesses
858system.cpu0.icache.demand_miss_rate::total 0.027636 # miss rate for demand accesses
859system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027636 # miss rate for overall accesses
860system.cpu0.icache.overall_miss_rate::total 0.027636 # miss rate for overall accesses
861system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9448.674354 # average ReadReq miss latency
862system.cpu0.icache.ReadReq_avg_miss_latency::total 9448.674354 # average ReadReq miss latency
863system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9448.674354 # average overall miss latency
864system.cpu0.icache.demand_avg_miss_latency::total 9448.674354 # average overall miss latency
865system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9448.674354 # average overall miss latency
866system.cpu0.icache.overall_avg_miss_latency::total 9448.674354 # average overall miss latency
867system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
868system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
869system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
870system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
871system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
872system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
873system.cpu0.icache.writebacks::writebacks 1887196 # number of writebacks
874system.cpu0.icache.writebacks::total 1887196 # number of writebacks
875system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1887721 # number of ReadReq MSHR misses
876system.cpu0.icache.ReadReq_mshr_misses::total 1887721 # number of ReadReq MSHR misses
877system.cpu0.icache.demand_mshr_misses::cpu0.inst 1887721 # number of demand (read+write) MSHR misses
878system.cpu0.icache.demand_mshr_misses::total 1887721 # number of demand (read+write) MSHR misses
879system.cpu0.icache.overall_mshr_misses::cpu0.inst 1887721 # number of overall MSHR misses
880system.cpu0.icache.overall_mshr_misses::total 1887721 # number of overall MSHR misses
881system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3448 # number of ReadReq MSHR uncacheable
882system.cpu0.icache.ReadReq_mshr_uncacheable::total 3448 # number of ReadReq MSHR uncacheable
883system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3448 # number of overall MSHR uncacheable misses
884system.cpu0.icache.overall_mshr_uncacheable_misses::total 3448 # number of overall MSHR uncacheable misses
885system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16892601000 # number of ReadReq MSHR miss cycles
886system.cpu0.icache.ReadReq_mshr_miss_latency::total 16892601000 # number of ReadReq MSHR miss cycles
887system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16892601000 # number of demand (read+write) MSHR miss cycles
888system.cpu0.icache.demand_mshr_miss_latency::total 16892601000 # number of demand (read+write) MSHR miss cycles
889system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16892601000 # number of overall MSHR miss cycles
890system.cpu0.icache.overall_mshr_miss_latency::total 16892601000 # number of overall MSHR miss cycles
891system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319413000 # number of ReadReq MSHR uncacheable cycles
892system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319413000 # number of ReadReq MSHR uncacheable cycles
893system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319413000 # number of overall MSHR uncacheable cycles
894system.cpu0.icache.overall_mshr_uncacheable_latency::total 319413000 # number of overall MSHR uncacheable cycles
895system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for ReadReq accesses
896system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027636 # mshr miss rate for ReadReq accesses
897system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for demand accesses
898system.cpu0.icache.demand_mshr_miss_rate::total 0.027636 # mshr miss rate for demand accesses
899system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for overall accesses
900system.cpu0.icache.overall_mshr_miss_rate::total 0.027636 # mshr miss rate for overall accesses
901system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average ReadReq mshr miss latency
902system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8948.674619 # average ReadReq mshr miss latency
903system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average overall mshr miss latency
904system.cpu0.icache.demand_avg_mshr_miss_latency::total 8948.674619 # average overall mshr miss latency
905system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average overall mshr miss latency
906system.cpu0.icache.overall_avg_mshr_miss_latency::total 8948.674619 # average overall mshr miss latency
907system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average ReadReq mshr uncacheable latency
908system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92637.180974 # average ReadReq mshr uncacheable latency
909system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average overall mshr uncacheable latency
910system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92637.180974 # average overall mshr uncacheable latency
911system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
912system.cpu0.l2cache.prefetcher.num_hwpf_issued 1767222 # number of hwpf issued
913system.cpu0.l2cache.prefetcher.pfIdentified 1767306 # number of prefetch candidates identified
914system.cpu0.l2cache.prefetcher.pfBufferHit 74 # number of redundant prefetches already in prefetch queue
915system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
916system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
917system.cpu0.l2cache.prefetcher.pfSpanPage 225214 # number of prefetches not generated due to page crossing
918system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
919system.cpu0.l2cache.tags.replacements 281957 # number of replacements
920system.cpu0.l2cache.tags.tagsinuse 16020.304669 # Cycle average of tags in use
921system.cpu0.l2cache.tags.total_refs 4495555 # Total number of references to valid blocks.
922system.cpu0.l2cache.tags.sampled_refs 298080 # Sample count of references to valid blocks.
923system.cpu0.l2cache.tags.avg_refs 15.081706 # Average number of references to valid blocks.
924system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
925system.cpu0.l2cache.tags.occ_blocks::writebacks 15153.098614 # Average occupied blocks per requestor
926system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.898882 # Average occupied blocks per requestor
927system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.073768 # Average occupied blocks per requestor
928system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 805.233405 # Average occupied blocks per requestor
929system.cpu0.l2cache.tags.occ_percent::writebacks 0.924872 # Average percentage of cache occupancy
930system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003778 # Average percentage of cache occupancy
931system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
932system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049148 # Average percentage of cache occupancy
933system.cpu0.l2cache.tags.occ_percent::total 0.977802 # Average percentage of cache occupancy
934system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1000 # Occupied blocks per task id
935system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
936system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15110 # Occupied blocks per task id
937system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id
938system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 315 # Occupied blocks per task id
939system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 390 # Occupied blocks per task id
940system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id
941system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
942system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
943system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
944system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
945system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 335 # Occupied blocks per task id
946system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4038 # Occupied blocks per task id
947system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7911 # Occupied blocks per task id
948system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2755 # Occupied blocks per task id
949system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061035 # Percentage of cache occupancy per task id
950system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id
951system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922241 # Percentage of cache occupancy per task id
952system.cpu0.l2cache.tags.tag_accesses 85783129 # Number of tag accesses
953system.cpu0.l2cache.tags.data_accesses 85783129 # Number of data accesses
954system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
955system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77844 # number of ReadReq hits
956system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5474 # number of ReadReq hits
957system.cpu0.l2cache.ReadReq_hits::total 83318 # number of ReadReq hits
958system.cpu0.l2cache.WritebackDirty_hits::writebacks 465182 # number of WritebackDirty hits
959system.cpu0.l2cache.WritebackDirty_hits::total 465182 # number of WritebackDirty hits
960system.cpu0.l2cache.WritebackClean_hits::writebacks 2062277 # number of WritebackClean hits
961system.cpu0.l2cache.WritebackClean_hits::total 2062277 # number of WritebackClean hits
962system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213330 # number of ReadExReq hits
963system.cpu0.l2cache.ReadExReq_hits::total 213330 # number of ReadExReq hits
964system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1827339 # number of ReadCleanReq hits
965system.cpu0.l2cache.ReadCleanReq_hits::total 1827339 # number of ReadCleanReq hits
966system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 378100 # number of ReadSharedReq hits
967system.cpu0.l2cache.ReadSharedReq_hits::total 378100 # number of ReadSharedReq hits
968system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77844 # number of demand (read+write) hits
969system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5474 # number of demand (read+write) hits
970system.cpu0.l2cache.demand_hits::cpu0.inst 1827339 # number of demand (read+write) hits
971system.cpu0.l2cache.demand_hits::cpu0.data 591430 # number of demand (read+write) hits
972system.cpu0.l2cache.demand_hits::total 2502087 # number of demand (read+write) hits
973system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77844 # number of overall hits
974system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5474 # number of overall hits
975system.cpu0.l2cache.overall_hits::cpu0.inst 1827339 # number of overall hits
976system.cpu0.l2cache.overall_hits::cpu0.data 591430 # number of overall hits
977system.cpu0.l2cache.overall_hits::total 2502087 # number of overall hits
978system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 760 # number of ReadReq misses
979system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 121 # number of ReadReq misses
980system.cpu0.l2cache.ReadReq_misses::total 881 # number of ReadReq misses
981system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 57605 # number of UpgradeReq misses
982system.cpu0.l2cache.UpgradeReq_misses::total 57605 # number of UpgradeReq misses
983system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 21456 # number of SCUpgradeReq misses
984system.cpu0.l2cache.SCUpgradeReq_misses::total 21456 # number of SCUpgradeReq misses
985system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
986system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
987system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44266 # number of ReadExReq misses
988system.cpu0.l2cache.ReadExReq_misses::total 44266 # number of ReadExReq misses
989system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 60382 # number of ReadCleanReq misses
990system.cpu0.l2cache.ReadCleanReq_misses::total 60382 # number of ReadCleanReq misses
991system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100716 # number of ReadSharedReq misses
992system.cpu0.l2cache.ReadSharedReq_misses::total 100716 # number of ReadSharedReq misses
993system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 760 # number of demand (read+write) misses
994system.cpu0.l2cache.demand_misses::cpu0.itb.walker 121 # number of demand (read+write) misses
995system.cpu0.l2cache.demand_misses::cpu0.inst 60382 # number of demand (read+write) misses
996system.cpu0.l2cache.demand_misses::cpu0.data 144982 # number of demand (read+write) misses
997system.cpu0.l2cache.demand_misses::total 206245 # number of demand (read+write) misses
998system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 760 # number of overall misses
999system.cpu0.l2cache.overall_misses::cpu0.itb.walker 121 # number of overall misses
1000system.cpu0.l2cache.overall_misses::cpu0.inst 60382 # number of overall misses
1001system.cpu0.l2cache.overall_misses::cpu0.data 144982 # number of overall misses
1002system.cpu0.l2cache.overall_misses::total 206245 # number of overall misses
1003system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 27717500 # number of ReadReq miss cycles
1004system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2799500 # number of ReadReq miss cycles
1005system.cpu0.l2cache.ReadReq_miss_latency::total 30517000 # number of ReadReq miss cycles
1006system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 116554500 # number of UpgradeReq miss cycles
1007system.cpu0.l2cache.UpgradeReq_miss_latency::total 116554500 # number of UpgradeReq miss cycles
1008system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 30031000 # number of SCUpgradeReq miss cycles
1009system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 30031000 # number of SCUpgradeReq miss cycles
1010system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 482498 # number of SCUpgradeFailReq miss cycles
1011system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 482498 # number of SCUpgradeFailReq miss cycles
1012system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2238448000 # number of ReadExReq miss cycles
1013system.cpu0.l2cache.ReadExReq_miss_latency::total 2238448000 # number of ReadExReq miss cycles
1014system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2969526500 # number of ReadCleanReq miss cycles
1015system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2969526500 # number of ReadCleanReq miss cycles
1016system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2950737493 # number of ReadSharedReq miss cycles
1017system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2950737493 # number of ReadSharedReq miss cycles
1018system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 27717500 # number of demand (read+write) miss cycles
1019system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2799500 # number of demand (read+write) miss cycles
1020system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2969526500 # number of demand (read+write) miss cycles
1021system.cpu0.l2cache.demand_miss_latency::cpu0.data 5189185493 # number of demand (read+write) miss cycles
1022system.cpu0.l2cache.demand_miss_latency::total 8189228993 # number of demand (read+write) miss cycles
1023system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 27717500 # number of overall miss cycles
1024system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2799500 # number of overall miss cycles
1025system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2969526500 # number of overall miss cycles
1026system.cpu0.l2cache.overall_miss_latency::cpu0.data 5189185493 # number of overall miss cycles
1027system.cpu0.l2cache.overall_miss_latency::total 8189228993 # number of overall miss cycles
1028system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78604 # number of ReadReq accesses(hits+misses)
1029system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5595 # number of ReadReq accesses(hits+misses)
1030system.cpu0.l2cache.ReadReq_accesses::total 84199 # number of ReadReq accesses(hits+misses)
1031system.cpu0.l2cache.WritebackDirty_accesses::writebacks 465182 # number of WritebackDirty accesses(hits+misses)
1032system.cpu0.l2cache.WritebackDirty_accesses::total 465182 # number of WritebackDirty accesses(hits+misses)
1033system.cpu0.l2cache.WritebackClean_accesses::writebacks 2062277 # number of WritebackClean accesses(hits+misses)
1034system.cpu0.l2cache.WritebackClean_accesses::total 2062277 # number of WritebackClean accesses(hits+misses)
1035system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 57605 # number of UpgradeReq accesses(hits+misses)
1036system.cpu0.l2cache.UpgradeReq_accesses::total 57605 # number of UpgradeReq accesses(hits+misses)
1037system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21456 # number of SCUpgradeReq accesses(hits+misses)
1038system.cpu0.l2cache.SCUpgradeReq_accesses::total 21456 # number of SCUpgradeReq accesses(hits+misses)
1039system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
1040system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
1041system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257596 # number of ReadExReq accesses(hits+misses)
1042system.cpu0.l2cache.ReadExReq_accesses::total 257596 # number of ReadExReq accesses(hits+misses)
1043system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1887721 # number of ReadCleanReq accesses(hits+misses)
1044system.cpu0.l2cache.ReadCleanReq_accesses::total 1887721 # number of ReadCleanReq accesses(hits+misses)
1045system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 478816 # number of ReadSharedReq accesses(hits+misses)
1046system.cpu0.l2cache.ReadSharedReq_accesses::total 478816 # number of ReadSharedReq accesses(hits+misses)
1047system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78604 # number of demand (read+write) accesses
1048system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5595 # number of demand (read+write) accesses
1049system.cpu0.l2cache.demand_accesses::cpu0.inst 1887721 # number of demand (read+write) accesses
1050system.cpu0.l2cache.demand_accesses::cpu0.data 736412 # number of demand (read+write) accesses
1051system.cpu0.l2cache.demand_accesses::total 2708332 # number of demand (read+write) accesses
1052system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78604 # number of overall (read+write) accesses
1053system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5595 # number of overall (read+write) accesses
1054system.cpu0.l2cache.overall_accesses::cpu0.inst 1887721 # number of overall (read+write) accesses
1055system.cpu0.l2cache.overall_accesses::cpu0.data 736412 # number of overall (read+write) accesses
1056system.cpu0.l2cache.overall_accesses::total 2708332 # number of overall (read+write) accesses
1057system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009669 # miss rate for ReadReq accesses
1058system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.021626 # miss rate for ReadReq accesses
1059system.cpu0.l2cache.ReadReq_miss_rate::total 0.010463 # miss rate for ReadReq accesses
1060system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1061system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1062system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1063system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1064system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1065system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1066system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171843 # miss rate for ReadExReq accesses
1067system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171843 # miss rate for ReadExReq accesses
1068system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.031987 # miss rate for ReadCleanReq accesses
1069system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.031987 # miss rate for ReadCleanReq accesses
1070system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.210344 # miss rate for ReadSharedReq accesses
1071system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.210344 # miss rate for ReadSharedReq accesses
1072system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009669 # miss rate for demand accesses
1073system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.021626 # miss rate for demand accesses
1074system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.031987 # miss rate for demand accesses
1075system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.196876 # miss rate for demand accesses
1076system.cpu0.l2cache.demand_miss_rate::total 0.076152 # miss rate for demand accesses
1077system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009669 # miss rate for overall accesses
1078system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.021626 # miss rate for overall accesses
1079system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.031987 # miss rate for overall accesses
1080system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.196876 # miss rate for overall accesses
1081system.cpu0.l2cache.overall_miss_rate::total 0.076152 # miss rate for overall accesses
1082system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36470.394737 # average ReadReq miss latency
1083system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23136.363636 # average ReadReq miss latency
1084system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34639.046538 # average ReadReq miss latency
1085system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2023.339988 # average UpgradeReq miss latency
1086system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2023.339988 # average UpgradeReq miss latency
1087system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1399.655108 # average SCUpgradeReq miss latency
1088system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1399.655108 # average SCUpgradeReq miss latency
1089system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 120624.500000 # average SCUpgradeFailReq miss latency
1090system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 120624.500000 # average SCUpgradeFailReq miss latency
1091system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50568.110966 # average ReadExReq miss latency
1092system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50568.110966 # average ReadExReq miss latency
1093system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49179.002020 # average ReadCleanReq miss latency
1094system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49179.002020 # average ReadCleanReq miss latency
1095system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29297.604085 # average ReadSharedReq miss latency
1096system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29297.604085 # average ReadSharedReq miss latency
1097system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36470.394737 # average overall miss latency
1098system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23136.363636 # average overall miss latency
1099system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49179.002020 # average overall miss latency
1100system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35791.929295 # average overall miss latency
1101system.cpu0.l2cache.demand_avg_miss_latency::total 39706.315271 # average overall miss latency
1102system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36470.394737 # average overall miss latency
1103system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23136.363636 # average overall miss latency
1104system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49179.002020 # average overall miss latency
1105system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35791.929295 # average overall miss latency
1106system.cpu0.l2cache.overall_avg_miss_latency::total 39706.315271 # average overall miss latency
1107system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1108system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1109system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1110system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1111system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1112system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1113system.cpu0.l2cache.unused_prefetches 9085 # number of HardPF blocks evicted w/o reference
1114system.cpu0.l2cache.writebacks::writebacks 227660 # number of writebacks
1115system.cpu0.l2cache.writebacks::total 227660 # number of writebacks
1116system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2626 # number of ReadExReq MSHR hits
1117system.cpu0.l2cache.ReadExReq_mshr_hits::total 2626 # number of ReadExReq MSHR hits
1118system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 53 # number of ReadCleanReq MSHR hits
1119system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 53 # number of ReadCleanReq MSHR hits
1120system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 363 # number of ReadSharedReq MSHR hits
1121system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 363 # number of ReadSharedReq MSHR hits
1122system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 53 # number of demand (read+write) MSHR hits
1123system.cpu0.l2cache.demand_mshr_hits::cpu0.data 2989 # number of demand (read+write) MSHR hits
1124system.cpu0.l2cache.demand_mshr_hits::total 3042 # number of demand (read+write) MSHR hits
1125system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 53 # number of overall MSHR hits
1126system.cpu0.l2cache.overall_mshr_hits::cpu0.data 2989 # number of overall MSHR hits
1127system.cpu0.l2cache.overall_mshr_hits::total 3042 # number of overall MSHR hits
1128system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 760 # number of ReadReq MSHR misses
1129system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 121 # number of ReadReq MSHR misses
1130system.cpu0.l2cache.ReadReq_mshr_misses::total 881 # number of ReadReq MSHR misses
1131system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 247545 # number of HardPFReq MSHR misses
1132system.cpu0.l2cache.HardPFReq_mshr_misses::total 247545 # number of HardPFReq MSHR misses
1133system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 57605 # number of UpgradeReq MSHR misses
1134system.cpu0.l2cache.UpgradeReq_mshr_misses::total 57605 # number of UpgradeReq MSHR misses
1135system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 21456 # number of SCUpgradeReq MSHR misses
1136system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 21456 # number of SCUpgradeReq MSHR misses
1137system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
1138system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
1139system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41640 # number of ReadExReq MSHR misses
1140system.cpu0.l2cache.ReadExReq_mshr_misses::total 41640 # number of ReadExReq MSHR misses
1141system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 60329 # number of ReadCleanReq MSHR misses
1142system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 60329 # number of ReadCleanReq MSHR misses
1143system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100353 # number of ReadSharedReq MSHR misses
1144system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100353 # number of ReadSharedReq MSHR misses
1145system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 760 # number of demand (read+write) MSHR misses
1146system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 121 # number of demand (read+write) MSHR misses
1147system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 60329 # number of demand (read+write) MSHR misses
1148system.cpu0.l2cache.demand_mshr_misses::cpu0.data 141993 # number of demand (read+write) MSHR misses
1149system.cpu0.l2cache.demand_mshr_misses::total 203203 # number of demand (read+write) MSHR misses
1150system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 760 # number of overall MSHR misses
1151system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 121 # number of overall MSHR misses
1152system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 60329 # number of overall MSHR misses
1153system.cpu0.l2cache.overall_mshr_misses::cpu0.data 141993 # number of overall MSHR misses
1154system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 247545 # number of overall MSHR misses
1155system.cpu0.l2cache.overall_mshr_misses::total 450748 # number of overall MSHR misses
1156system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3448 # number of ReadReq MSHR uncacheable
1157system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29629 # number of ReadReq MSHR uncacheable
1158system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 33077 # number of ReadReq MSHR uncacheable
1159system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26357 # number of WriteReq MSHR uncacheable
1160system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26357 # number of WriteReq MSHR uncacheable
1161system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3448 # number of overall MSHR uncacheable misses
1162system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55986 # number of overall MSHR uncacheable misses
1163system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 59434 # number of overall MSHR uncacheable misses
1164system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 23157500 # number of ReadReq MSHR miss cycles
1165system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2073500 # number of ReadReq MSHR miss cycles
1166system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 25231000 # number of ReadReq MSHR miss cycles
1167system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14000669196 # number of HardPFReq MSHR miss cycles
1168system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14000669196 # number of HardPFReq MSHR miss cycles
1169system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1121106500 # number of UpgradeReq MSHR miss cycles
1170system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1121106500 # number of UpgradeReq MSHR miss cycles
1171system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 340294500 # number of SCUpgradeReq MSHR miss cycles
1172system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 340294500 # number of SCUpgradeReq MSHR miss cycles
1173system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 404498 # number of SCUpgradeFailReq MSHR miss cycles
1174system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 404498 # number of SCUpgradeFailReq MSHR miss cycles
1175system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1697761000 # number of ReadExReq MSHR miss cycles
1176system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1697761000 # number of ReadExReq MSHR miss cycles
1177system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2606173000 # number of ReadCleanReq MSHR miss cycles
1178system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2606173000 # number of ReadCleanReq MSHR miss cycles
1179system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2329095993 # number of ReadSharedReq MSHR miss cycles
1180system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2329095993 # number of ReadSharedReq MSHR miss cycles
1181system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 23157500 # number of demand (read+write) MSHR miss cycles
1182system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2073500 # number of demand (read+write) MSHR miss cycles
1183system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2606173000 # number of demand (read+write) MSHR miss cycles
1184system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4026856993 # number of demand (read+write) MSHR miss cycles
1185system.cpu0.l2cache.demand_mshr_miss_latency::total 6658260993 # number of demand (read+write) MSHR miss cycles
1186system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 23157500 # number of overall MSHR miss cycles
1187system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2073500 # number of overall MSHR miss cycles
1188system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2606173000 # number of overall MSHR miss cycles
1189system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4026856993 # number of overall MSHR miss cycles
1190system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14000669196 # number of overall MSHR miss cycles
1191system.cpu0.l2cache.overall_mshr_miss_latency::total 20658930189 # number of overall MSHR miss cycles
1192system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 291829000 # number of ReadReq MSHR uncacheable cycles
1193system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5864363500 # number of ReadReq MSHR uncacheable cycles
1194system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6156192500 # number of ReadReq MSHR uncacheable cycles
1195system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 291829000 # number of overall MSHR uncacheable cycles
1196system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5864363500 # number of overall MSHR uncacheable cycles
1197system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6156192500 # number of overall MSHR uncacheable cycles
1198system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for ReadReq accesses
1199system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for ReadReq accesses
1200system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010463 # mshr miss rate for ReadReq accesses
1201system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1202system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1203system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1204system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1205system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1206system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1207system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1208system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1209system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.161648 # mshr miss rate for ReadExReq accesses
1210system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.161648 # mshr miss rate for ReadExReq accesses
1211system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for ReadCleanReq accesses
1212system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.031959 # mshr miss rate for ReadCleanReq accesses
1213system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209586 # mshr miss rate for ReadSharedReq accesses
1214system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.209586 # mshr miss rate for ReadSharedReq accesses
1215system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for demand accesses
1216system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for demand accesses
1217system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for demand accesses
1218system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for demand accesses
1219system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses
1220system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for overall accesses
1221system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for overall accesses
1222system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for overall accesses
1223system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for overall accesses
1224system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1225system.cpu0.l2cache.overall_mshr_miss_rate::total 0.166430 # mshr miss rate for overall accesses
1226system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average ReadReq mshr miss latency
1227system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average ReadReq mshr miss latency
1228system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28639.046538 # average ReadReq mshr miss latency
1229system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average HardPFReq mshr miss latency
1230system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56558.077101 # average HardPFReq mshr miss latency
1231system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19461.965107 # average UpgradeReq mshr miss latency
1232system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19461.965107 # average UpgradeReq mshr miss latency
1233system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15860.109060 # average SCUpgradeReq mshr miss latency
1234system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15860.109060 # average SCUpgradeReq mshr miss latency
1235system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 101124.500000 # average SCUpgradeFailReq mshr miss latency
1236system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 101124.500000 # average SCUpgradeFailReq mshr miss latency
1237system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40772.358309 # average ReadExReq mshr miss latency
1238system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40772.358309 # average ReadExReq mshr miss latency
1239system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average ReadCleanReq mshr miss latency
1240system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43199.340284 # average ReadCleanReq mshr miss latency
1241system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23209.032047 # average ReadSharedReq mshr miss latency
1242system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23209.032047 # average ReadSharedReq mshr miss latency
1243system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency
1244system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency
1245system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency
1246system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency
1247system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32766.548688 # average overall mshr miss latency
1248system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency
1249system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency
1250system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency
1251system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency
1252system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average overall mshr miss latency
1253system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45832.549870 # average overall mshr miss latency
1254system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average ReadReq mshr uncacheable latency
1255system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197926.474063 # average ReadReq mshr uncacheable latency
1256system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 186117.014844 # average ReadReq mshr uncacheable latency
1257system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average overall mshr uncacheable latency
1258system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 104746.963527 # average overall mshr uncacheable latency
1259system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103580.315981 # average overall mshr uncacheable latency
1260system.cpu0.toL2Bus.snoop_filter.tot_requests 5292246 # Total number of requests made to the snoop filter.
1261system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2668157 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1262system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 40914 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1263system.cpu0.toL2Bus.snoop_filter.tot_snoops 334901 # Total number of snoops made to the snoop filter.
1264system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 330475 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1265system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1266system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1267system.cpu0.toL2Bus.trans_dist::ReadReq 126809 # Transaction distribution
1268system.cpu0.toL2Bus.trans_dist::ReadResp 2542571 # Transaction distribution
1269system.cpu0.toL2Bus.trans_dist::WriteReq 26357 # Transaction distribution
1270system.cpu0.toL2Bus.trans_dist::WriteResp 26357 # Transaction distribution
1271system.cpu0.toL2Bus.trans_dist::WritebackDirty 693110 # Transaction distribution
1272system.cpu0.toL2Bus.trans_dist::WritebackClean 2103191 # Transaction distribution
1273system.cpu0.toL2Bus.trans_dist::CleanEvict 223137 # Transaction distribution
1274system.cpu0.toL2Bus.trans_dist::HardPFReq 294264 # Transaction distribution
1275system.cpu0.toL2Bus.trans_dist::UpgradeReq 92982 # Transaction distribution
1276system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43850 # Transaction distribution
1277system.cpu0.toL2Bus.trans_dist::UpgradeResp 116200 # Transaction distribution
1278system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution
1279system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
1280system.cpu0.toL2Bus.trans_dist::ReadExReq 275510 # Transaction distribution
1281system.cpu0.toL2Bus.trans_dist::ReadExResp 272175 # Transaction distribution
1282system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1887721 # Transaction distribution
1283system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569608 # Transaction distribution
1284system.cpu0.toL2Bus.trans_dist::InvalidateReq 3113 # Transaction distribution
1285system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5669533 # Packet count per connected master and slave (bytes)
1286system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2525108 # Packet count per connected master and slave (bytes)
1287system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13291 # Packet count per connected master and slave (bytes)
1288system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164598 # Packet count per connected master and slave (bytes)
1289system.cpu0.toL2Bus.pkt_count::total 8372530 # Packet count per connected master and slave (bytes)
1290system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 241815296 # Cumulative packet size per connected master and slave (bytes)
1291system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94996751 # Cumulative packet size per connected master and slave (bytes)
1292system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22380 # Cumulative packet size per connected master and slave (bytes)
1293system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314416 # Cumulative packet size per connected master and slave (bytes)
1294system.cpu0.toL2Bus.pkt_size::total 337148843 # Cumulative packet size per connected master and slave (bytes)
1295system.cpu0.toL2Bus.snoops 1025467 # Total snoops (count)
1296system.cpu0.toL2Bus.snoopTraffic 18711896 # Total snoop traffic (bytes)
1297system.cpu0.toL2Bus.snoop_fanout::samples 3771293 # Request fanout histogram
1298system.cpu0.toL2Bus.snoop_fanout::mean 0.106316 # Request fanout histogram
1299system.cpu0.toL2Bus.snoop_fanout::stdev 0.312026 # Request fanout histogram
1300system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1301system.cpu0.toL2Bus.snoop_fanout::0 3374771 89.49% 89.49% # Request fanout histogram
1302system.cpu0.toL2Bus.snoop_fanout::1 392096 10.40% 99.88% # Request fanout histogram
1303system.cpu0.toL2Bus.snoop_fanout::2 4426 0.12% 100.00% # Request fanout histogram
1304system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1305system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1306system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1307system.cpu0.toL2Bus.snoop_fanout::total 3771293 # Request fanout histogram
1308system.cpu0.toL2Bus.reqLayer0.occupancy 5293903990 # Layer occupancy (ticks)
1309system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1310system.cpu0.toL2Bus.snoopLayer0.occupancy 114422325 # Layer occupancy (ticks)
1311system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1312system.cpu0.toL2Bus.respLayer0.occupancy 2837181638 # Layer occupancy (ticks)
1313system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1314system.cpu0.toL2Bus.respLayer1.occupancy 1188012916 # Layer occupancy (ticks)
1315system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1316system.cpu0.toL2Bus.respLayer2.occupancy 7701489 # Layer occupancy (ticks)
1317system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1318system.cpu0.toL2Bus.respLayer3.occupancy 86027432 # Layer occupancy (ticks)
1319system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1320system.cpu1.branchPred.lookups 5469499 # Number of BP lookups
1321system.cpu1.branchPred.condPredicted 3374978 # Number of conditional branches predicted
1322system.cpu1.branchPred.condIncorrect 316517 # Number of conditional branches incorrect
1323system.cpu1.branchPred.BTBLookups 3346860 # Number of BTB lookups
1324system.cpu1.branchPred.BTBHits 2136825 # Number of BTB hits
1325system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1326system.cpu1.branchPred.BTBHitPct 63.845664 # BTB Hit Percentage
1327system.cpu1.branchPred.usedRAS 972408 # Number of times the RAS was used to get a target.
1328system.cpu1.branchPred.RASInCorrect 68961 # Number of incorrect RAS predictions.
1329system.cpu1.branchPred.indirectLookups 195238 # Number of indirect predictor lookups.
1330system.cpu1.branchPred.indirectHits 132437 # Number of indirect target hits.
1331system.cpu1.branchPred.indirectMisses 62801 # Number of indirect misses.
1332system.cpu1.branchPredindirectMispredicted 28788 # Number of mispredicted indirect branches.
1333system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1334system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1335system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1336system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1339system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1340system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1341system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1355system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1356system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1357system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1358system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1359system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1360system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1361system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1362system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1363system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1364system.cpu1.dtb.walker.walks 30404 # Table walker walks requested
1365system.cpu1.dtb.walker.walksShort 30404 # Table walker walks initiated with short descriptors
1366system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23807 # Level at which table walker walks with short descriptors terminate
1367system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6597 # Level at which table walker walks with short descriptors terminate
1368system.cpu1.dtb.walker.walkWaitTime::samples 30404 # Table walker wait (enqueue to first request) latency
1369system.cpu1.dtb.walker.walkWaitTime::0 30404 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1370system.cpu1.dtb.walker.walkWaitTime::total 30404 # Table walker wait (enqueue to first request) latency
1371system.cpu1.dtb.walker.walkCompletionTime::samples 2736 # Table walker service (enqueue to completion) latency
1372system.cpu1.dtb.walker.walkCompletionTime::mean 12207.419591 # Table walker service (enqueue to completion) latency
1373system.cpu1.dtb.walker.walkCompletionTime::gmean 11247.456123 # Table walker service (enqueue to completion) latency
1374system.cpu1.dtb.walker.walkCompletionTime::stdev 8821.385005 # Table walker service (enqueue to completion) latency
1375system.cpu1.dtb.walker.walkCompletionTime::0-32767 2714 99.20% 99.20% # Table walker service (enqueue to completion) latency
1376system.cpu1.dtb.walker.walkCompletionTime::32768-65535 14 0.51% 99.71% # Table walker service (enqueue to completion) latency
1377system.cpu1.dtb.walker.walkCompletionTime::65536-98303 4 0.15% 99.85% # Table walker service (enqueue to completion) latency
1378system.cpu1.dtb.walker.walkCompletionTime::98304-131071 3 0.11% 99.96% # Table walker service (enqueue to completion) latency
1379system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
1380system.cpu1.dtb.walker.walkCompletionTime::total 2736 # Table walker service (enqueue to completion) latency
1381system.cpu1.dtb.walker.walksPending::samples -1954228032 # Table walker pending requests distribution
1382system.cpu1.dtb.walker.walksPending::0 -1954228032 100.00% 100.00% # Table walker pending requests distribution
1383system.cpu1.dtb.walker.walksPending::total -1954228032 # Table walker pending requests distribution
1384system.cpu1.dtb.walker.walkPageSizes::4K 2033 74.31% 74.31% # Table walker page sizes translated
1385system.cpu1.dtb.walker.walkPageSizes::1M 703 25.69% 100.00% # Table walker page sizes translated
1386system.cpu1.dtb.walker.walkPageSizes::total 2736 # Table walker page sizes translated
1387system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30404 # Table walker requests started/completed, data/inst
1388system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1389system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30404 # Table walker requests started/completed, data/inst
1390system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2736 # Table walker requests started/completed, data/inst
1391system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1392system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2736 # Table walker requests started/completed, data/inst
1393system.cpu1.dtb.walker.walkRequestOrigin::total 33140 # Table walker requests started/completed, data/inst
1394system.cpu1.dtb.inst_hits 0 # ITB inst hits
1395system.cpu1.dtb.inst_misses 0 # ITB inst misses
1396system.cpu1.dtb.read_hits 5173966 # DTB read hits
1397system.cpu1.dtb.read_misses 27871 # DTB read misses
1398system.cpu1.dtb.write_hits 4222414 # DTB write hits
1399system.cpu1.dtb.write_misses 2533 # DTB write misses
1400system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1401system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1402system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1403system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1404system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB
1405system.cpu1.dtb.align_faults 306 # Number of TLB faults due to alignment restrictions
1406system.cpu1.dtb.prefetch_faults 555 # Number of TLB faults due to prefetch
1407system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1408system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions
1409system.cpu1.dtb.read_accesses 5201837 # DTB read accesses
1410system.cpu1.dtb.write_accesses 4224947 # DTB write accesses
1411system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1412system.cpu1.dtb.hits 9396380 # DTB hits
1413system.cpu1.dtb.misses 30404 # DTB misses
1414system.cpu1.dtb.accesses 9426784 # DTB accesses
1415system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1416system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1417system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1418system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1419system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1420system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1421system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1422system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1437system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1438system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1439system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1440system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1441system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1442system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1443system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1444system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1445system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1446system.cpu1.itb.walker.walks 2488 # Table walker walks requested
1447system.cpu1.itb.walker.walksShort 2488 # Table walker walks initiated with short descriptors
1448system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate
1449system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2306 # Level at which table walker walks with short descriptors terminate
1450system.cpu1.itb.walker.walkWaitTime::samples 2488 # Table walker wait (enqueue to first request) latency
1451system.cpu1.itb.walker.walkWaitTime::0 2488 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1452system.cpu1.itb.walker.walkWaitTime::total 2488 # Table walker wait (enqueue to first request) latency
1453system.cpu1.itb.walker.walkCompletionTime::samples 1135 # Table walker service (enqueue to completion) latency
1454system.cpu1.itb.walker.walkCompletionTime::mean 12427.312775 # Table walker service (enqueue to completion) latency
1455system.cpu1.itb.walker.walkCompletionTime::gmean 11760.899210 # Table walker service (enqueue to completion) latency
1456system.cpu1.itb.walker.walkCompletionTime::stdev 5007.072010 # Table walker service (enqueue to completion) latency
1457system.cpu1.itb.walker.walkCompletionTime::0-4095 4 0.35% 0.35% # Table walker service (enqueue to completion) latency
1458system.cpu1.itb.walker.walkCompletionTime::4096-8191 156 13.74% 14.10% # Table walker service (enqueue to completion) latency
1459system.cpu1.itb.walker.walkCompletionTime::8192-12287 686 60.44% 74.54% # Table walker service (enqueue to completion) latency
1460system.cpu1.itb.walker.walkCompletionTime::12288-16383 210 18.50% 93.04% # Table walker service (enqueue to completion) latency
1461system.cpu1.itb.walker.walkCompletionTime::16384-20479 30 2.64% 95.68% # Table walker service (enqueue to completion) latency
1462system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 95.86% # Table walker service (enqueue to completion) latency
1463system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.85% 97.71% # Table walker service (enqueue to completion) latency
1464system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.70% 98.41% # Table walker service (enqueue to completion) latency
1465system.cpu1.itb.walker.walkCompletionTime::36864-40959 15 1.32% 99.74% # Table walker service (enqueue to completion) latency
1466system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.26% 100.00% # Table walker service (enqueue to completion) latency
1467system.cpu1.itb.walker.walkCompletionTime::total 1135 # Table walker service (enqueue to completion) latency
1468system.cpu1.itb.walker.walksPending::samples -1954817532 # Table walker pending requests distribution
1469system.cpu1.itb.walker.walksPending::0 -1954817532 100.00% 100.00% # Table walker pending requests distribution
1470system.cpu1.itb.walker.walksPending::total -1954817532 # Table walker pending requests distribution
1471system.cpu1.itb.walker.walkPageSizes::4K 965 85.02% 85.02% # Table walker page sizes translated
1472system.cpu1.itb.walker.walkPageSizes::1M 170 14.98% 100.00% # Table walker page sizes translated
1473system.cpu1.itb.walker.walkPageSizes::total 1135 # Table walker page sizes translated
1474system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1475system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2488 # Table walker requests started/completed, data/inst
1476system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2488 # Table walker requests started/completed, data/inst
1477system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1478system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1135 # Table walker requests started/completed, data/inst
1479system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1135 # Table walker requests started/completed, data/inst
1480system.cpu1.itb.walker.walkRequestOrigin::total 3623 # Table walker requests started/completed, data/inst
1481system.cpu1.itb.inst_hits 10174079 # ITB inst hits
1482system.cpu1.itb.inst_misses 2488 # ITB inst misses
1483system.cpu1.itb.read_hits 0 # DTB read hits
1484system.cpu1.itb.read_misses 0 # DTB read misses
1485system.cpu1.itb.write_hits 0 # DTB write hits
1486system.cpu1.itb.write_misses 0 # DTB write misses
1487system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1488system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1489system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1490system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1491system.cpu1.itb.flush_entries 1107 # Number of entries that have been flushed from TLB
1492system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1493system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1494system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1495system.cpu1.itb.perms_faults 1891 # Number of TLB faults due to permissions restrictions
1496system.cpu1.itb.read_accesses 0 # DTB read accesses
1497system.cpu1.itb.write_accesses 0 # DTB write accesses
1498system.cpu1.itb.inst_accesses 10176567 # ITB inst accesses
1499system.cpu1.itb.hits 10174079 # DTB hits
1500system.cpu1.itb.misses 2488 # DTB misses
1501system.cpu1.itb.accesses 10176567 # DTB accesses
1502system.cpu1.numPwrStateTransitions 5445 # Number of power state transitions
1503system.cpu1.pwrStateClkGateDist::samples 2723 # Distribution of time spent in the clock gated state
1504system.cpu1.pwrStateClkGateDist::mean 962192053.212266 # Distribution of time spent in the clock gated state
1505system.cpu1.pwrStateClkGateDist::stdev 19383110303.670654 # Distribution of time spent in the clock gated state
1506system.cpu1.pwrStateClkGateDist::underflows 1861 68.34% 68.34% # Distribution of time spent in the clock gated state
1507system.cpu1.pwrStateClkGateDist::1000-5e+10 855 31.40% 99.74% # Distribution of time spent in the clock gated state
1508system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.85% # Distribution of time spent in the clock gated state
1509system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 4 0.15% 100.00% # Distribution of time spent in the clock gated state
1510system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1511system.cpu1.pwrStateClkGateDist::max_value 499966911836 # Distribution of time spent in the clock gated state
1512system.cpu1.pwrStateClkGateDist::total 2723 # Distribution of time spent in the clock gated state
1513system.cpu1.pwrStateResidencyTicks::ON 27729121603 # Cumulative time (in ticks) in various power states
1514system.cpu1.pwrStateResidencyTicks::CLK_GATED 2620048960897 # Cumulative time (in ticks) in various power states
1515system.cpu1.numCycles 55461727 # number of cpu cycles simulated
1516system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1517system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1518system.cpu1.committedInsts 20907814 # Number of instructions committed
1519system.cpu1.committedOps 25520055 # Number of ops (including micro ops) committed
1520system.cpu1.discardedOps 1855956 # Number of ops (including micro ops) which were discarded before commit
1521system.cpu1.numFetchSuspends 2723 # Number of times Execute suspended instruction fetching
1522system.cpu1.quiesceCycles 5239453402 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1523system.cpu1.cpi 2.652679 # CPI: cycles per instruction
1524system.cpu1.ipc 0.376977 # IPC: instructions per cycle
1525system.cpu1.op_class_0::No_OpClass 67 0.00% 0.00% # Class of committed instruction
1526system.cpu1.op_class_0::IntAlu 16137166 63.23% 63.23% # Class of committed instruction
1527system.cpu1.op_class_0::IntMult 34169 0.13% 63.37% # Class of committed instruction
1528system.cpu1.op_class_0::IntDiv 0 0.00% 63.37% # Class of committed instruction
1529system.cpu1.op_class_0::FloatAdd 0 0.00% 63.37% # Class of committed instruction
1530system.cpu1.op_class_0::FloatCmp 0 0.00% 63.37% # Class of committed instruction
1531system.cpu1.op_class_0::FloatCvt 0 0.00% 63.37% # Class of committed instruction
1532system.cpu1.op_class_0::FloatMult 0 0.00% 63.37% # Class of committed instruction
1533system.cpu1.op_class_0::FloatDiv 0 0.00% 63.37% # Class of committed instruction
1534system.cpu1.op_class_0::FloatSqrt 0 0.00% 63.37% # Class of committed instruction
1535system.cpu1.op_class_0::SimdAdd 0 0.00% 63.37% # Class of committed instruction
1536system.cpu1.op_class_0::SimdAddAcc 0 0.00% 63.37% # Class of committed instruction
1537system.cpu1.op_class_0::SimdAlu 0 0.00% 63.37% # Class of committed instruction
1538system.cpu1.op_class_0::SimdCmp 0 0.00% 63.37% # Class of committed instruction
1539system.cpu1.op_class_0::SimdCvt 0 0.00% 63.37% # Class of committed instruction
1540system.cpu1.op_class_0::SimdMisc 0 0.00% 63.37% # Class of committed instruction
1541system.cpu1.op_class_0::SimdMult 0 0.00% 63.37% # Class of committed instruction
1542system.cpu1.op_class_0::SimdMultAcc 0 0.00% 63.37% # Class of committed instruction
1543system.cpu1.op_class_0::SimdShift 0 0.00% 63.37% # Class of committed instruction
1544system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 63.37% # Class of committed instruction
1545system.cpu1.op_class_0::SimdSqrt 0 0.00% 63.37% # Class of committed instruction
1546system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 63.37% # Class of committed instruction
1547system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 63.37% # Class of committed instruction
1548system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 63.37% # Class of committed instruction
1549system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 63.37% # Class of committed instruction
1550system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 63.37% # Class of committed instruction
1551system.cpu1.op_class_0::SimdFloatMisc 4083 0.02% 63.38% # Class of committed instruction
1552system.cpu1.op_class_0::SimdFloatMult 0 0.00% 63.38% # Class of committed instruction
1553system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 63.38% # Class of committed instruction
1554system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 63.38% # Class of committed instruction
1555system.cpu1.op_class_0::MemRead 4989153 19.55% 82.93% # Class of committed instruction
1556system.cpu1.op_class_0::MemWrite 4355417 17.07% 100.00% # Class of committed instruction
1557system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1558system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1559system.cpu1.op_class_0::total 25520055 # Class of committed instruction
1560system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1561system.cpu1.kern.inst.quiesce 2723 # number of quiesce instructions executed
1562system.cpu1.tickCycles 37036327 # Number of cycles that the object actually ticked
1563system.cpu1.idleCycles 18425400 # Total number of cycles that the object has spent stopped
1564system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1565system.cpu1.dcache.tags.replacements 231690 # number of replacements
1566system.cpu1.dcache.tags.tagsinuse 479.724430 # Cycle average of tags in use
1567system.cpu1.dcache.tags.total_refs 8932333 # Total number of references to valid blocks.
1568system.cpu1.dcache.tags.sampled_refs 232024 # Sample count of references to valid blocks.
1569system.cpu1.dcache.tags.avg_refs 38.497453 # Average number of references to valid blocks.
1570system.cpu1.dcache.tags.warmup_cycle 109862994000 # Cycle when the warmup percentage was hit.
1571system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.724430 # Average occupied blocks per requestor
1572system.cpu1.dcache.tags.occ_percent::cpu1.data 0.936962 # Average percentage of cache occupancy
1573system.cpu1.dcache.tags.occ_percent::total 0.936962 # Average percentage of cache occupancy
1574system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id
1575system.cpu1.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
1576system.cpu1.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id
1577system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id
1578system.cpu1.dcache.tags.tag_accesses 18884551 # Number of tag accesses
1579system.cpu1.dcache.tags.data_accesses 18884551 # Number of data accesses
1580system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1581system.cpu1.dcache.ReadReq_hits::cpu1.data 4750067 # number of ReadReq hits
1582system.cpu1.dcache.ReadReq_hits::total 4750067 # number of ReadReq hits
1583system.cpu1.dcache.WriteReq_hits::cpu1.data 3901959 # number of WriteReq hits
1584system.cpu1.dcache.WriteReq_hits::total 3901959 # number of WriteReq hits
1585system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65733 # number of SoftPFReq hits
1586system.cpu1.dcache.SoftPFReq_hits::total 65733 # number of SoftPFReq hits
1587system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87399 # number of LoadLockedReq hits
1588system.cpu1.dcache.LoadLockedReq_hits::total 87399 # number of LoadLockedReq hits
1589system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79392 # number of StoreCondReq hits
1590system.cpu1.dcache.StoreCondReq_hits::total 79392 # number of StoreCondReq hits
1591system.cpu1.dcache.demand_hits::cpu1.data 8652026 # number of demand (read+write) hits
1592system.cpu1.dcache.demand_hits::total 8652026 # number of demand (read+write) hits
1593system.cpu1.dcache.overall_hits::cpu1.data 8717759 # number of overall hits
1594system.cpu1.dcache.overall_hits::total 8717759 # number of overall hits
1595system.cpu1.dcache.ReadReq_misses::cpu1.data 172325 # number of ReadReq misses
1596system.cpu1.dcache.ReadReq_misses::total 172325 # number of ReadReq misses
1597system.cpu1.dcache.WriteReq_misses::cpu1.data 169730 # number of WriteReq misses
1598system.cpu1.dcache.WriteReq_misses::total 169730 # number of WriteReq misses
1599system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34831 # number of SoftPFReq misses
1600system.cpu1.dcache.SoftPFReq_misses::total 34831 # number of SoftPFReq misses
1601system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17668 # number of LoadLockedReq misses
1602system.cpu1.dcache.LoadLockedReq_misses::total 17668 # number of LoadLockedReq misses
1603system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23402 # number of StoreCondReq misses
1604system.cpu1.dcache.StoreCondReq_misses::total 23402 # number of StoreCondReq misses
1605system.cpu1.dcache.demand_misses::cpu1.data 342055 # number of demand (read+write) misses
1606system.cpu1.dcache.demand_misses::total 342055 # number of demand (read+write) misses
1607system.cpu1.dcache.overall_misses::cpu1.data 376886 # number of overall misses
1608system.cpu1.dcache.overall_misses::total 376886 # number of overall misses
1609system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2622225500 # number of ReadReq miss cycles
1610system.cpu1.dcache.ReadReq_miss_latency::total 2622225500 # number of ReadReq miss cycles
1611system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4369952500 # number of WriteReq miss cycles
1612system.cpu1.dcache.WriteReq_miss_latency::total 4369952500 # number of WriteReq miss cycles
1613system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 333352000 # number of LoadLockedReq miss cycles
1614system.cpu1.dcache.LoadLockedReq_miss_latency::total 333352000 # number of LoadLockedReq miss cycles
1615system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 570866500 # number of StoreCondReq miss cycles
1616system.cpu1.dcache.StoreCondReq_miss_latency::total 570866500 # number of StoreCondReq miss cycles
1617system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 547000 # number of StoreCondFailReq miss cycles
1618system.cpu1.dcache.StoreCondFailReq_miss_latency::total 547000 # number of StoreCondFailReq miss cycles
1619system.cpu1.dcache.demand_miss_latency::cpu1.data 6992178000 # number of demand (read+write) miss cycles
1620system.cpu1.dcache.demand_miss_latency::total 6992178000 # number of demand (read+write) miss cycles
1621system.cpu1.dcache.overall_miss_latency::cpu1.data 6992178000 # number of overall miss cycles
1622system.cpu1.dcache.overall_miss_latency::total 6992178000 # number of overall miss cycles
1623system.cpu1.dcache.ReadReq_accesses::cpu1.data 4922392 # number of ReadReq accesses(hits+misses)
1624system.cpu1.dcache.ReadReq_accesses::total 4922392 # number of ReadReq accesses(hits+misses)
1625system.cpu1.dcache.WriteReq_accesses::cpu1.data 4071689 # number of WriteReq accesses(hits+misses)
1626system.cpu1.dcache.WriteReq_accesses::total 4071689 # number of WriteReq accesses(hits+misses)
1627system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100564 # number of SoftPFReq accesses(hits+misses)
1628system.cpu1.dcache.SoftPFReq_accesses::total 100564 # number of SoftPFReq accesses(hits+misses)
1629system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105067 # number of LoadLockedReq accesses(hits+misses)
1630system.cpu1.dcache.LoadLockedReq_accesses::total 105067 # number of LoadLockedReq accesses(hits+misses)
1631system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102794 # number of StoreCondReq accesses(hits+misses)
1632system.cpu1.dcache.StoreCondReq_accesses::total 102794 # number of StoreCondReq accesses(hits+misses)
1633system.cpu1.dcache.demand_accesses::cpu1.data 8994081 # number of demand (read+write) accesses
1634system.cpu1.dcache.demand_accesses::total 8994081 # number of demand (read+write) accesses
1635system.cpu1.dcache.overall_accesses::cpu1.data 9094645 # number of overall (read+write) accesses
1636system.cpu1.dcache.overall_accesses::total 9094645 # number of overall (read+write) accesses
1637system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035008 # miss rate for ReadReq accesses
1638system.cpu1.dcache.ReadReq_miss_rate::total 0.035008 # miss rate for ReadReq accesses
1639system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041685 # miss rate for WriteReq accesses
1640system.cpu1.dcache.WriteReq_miss_rate::total 0.041685 # miss rate for WriteReq accesses
1641system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.346357 # miss rate for SoftPFReq accesses
1642system.cpu1.dcache.SoftPFReq_miss_rate::total 0.346357 # miss rate for SoftPFReq accesses
1643system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.168159 # miss rate for LoadLockedReq accesses
1644system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.168159 # miss rate for LoadLockedReq accesses
1645system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227659 # miss rate for StoreCondReq accesses
1646system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227659 # miss rate for StoreCondReq accesses
1647system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038031 # miss rate for demand accesses
1648system.cpu1.dcache.demand_miss_rate::total 0.038031 # miss rate for demand accesses
1649system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041440 # miss rate for overall accesses
1650system.cpu1.dcache.overall_miss_rate::total 0.041440 # miss rate for overall accesses
1651system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15216.744523 # average ReadReq miss latency
1652system.cpu1.dcache.ReadReq_avg_miss_latency::total 15216.744523 # average ReadReq miss latency
1653system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25746.494432 # average WriteReq miss latency
1654system.cpu1.dcache.WriteReq_avg_miss_latency::total 25746.494432 # average WriteReq miss latency
1655system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18867.557165 # average LoadLockedReq miss latency
1656system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18867.557165 # average LoadLockedReq miss latency
1657system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24393.919323 # average StoreCondReq miss latency
1658system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24393.919323 # average StoreCondReq miss latency
1659system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1660system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1661system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20441.677508 # average overall miss latency
1662system.cpu1.dcache.demand_avg_miss_latency::total 20441.677508 # average overall miss latency
1663system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18552.501287 # average overall miss latency
1664system.cpu1.dcache.overall_avg_miss_latency::total 18552.501287 # average overall miss latency
1665system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1666system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1667system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1668system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1669system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1670system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1671system.cpu1.dcache.writebacks::writebacks 231690 # number of writebacks
1672system.cpu1.dcache.writebacks::total 231690 # number of writebacks
1673system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 6182 # number of ReadReq MSHR hits
1674system.cpu1.dcache.ReadReq_mshr_hits::total 6182 # number of ReadReq MSHR hits
1675system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 63208 # number of WriteReq MSHR hits
1676system.cpu1.dcache.WriteReq_mshr_hits::total 63208 # number of WriteReq MSHR hits
1677system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12205 # number of LoadLockedReq MSHR hits
1678system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12205 # number of LoadLockedReq MSHR hits
1679system.cpu1.dcache.demand_mshr_hits::cpu1.data 69390 # number of demand (read+write) MSHR hits
1680system.cpu1.dcache.demand_mshr_hits::total 69390 # number of demand (read+write) MSHR hits
1681system.cpu1.dcache.overall_mshr_hits::cpu1.data 69390 # number of overall MSHR hits
1682system.cpu1.dcache.overall_mshr_hits::total 69390 # number of overall MSHR hits
1683system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166143 # number of ReadReq MSHR misses
1684system.cpu1.dcache.ReadReq_mshr_misses::total 166143 # number of ReadReq MSHR misses
1685system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106522 # number of WriteReq MSHR misses
1686system.cpu1.dcache.WriteReq_mshr_misses::total 106522 # number of WriteReq MSHR misses
1687system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33373 # number of SoftPFReq MSHR misses
1688system.cpu1.dcache.SoftPFReq_mshr_misses::total 33373 # number of SoftPFReq MSHR misses
1689system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5463 # number of LoadLockedReq MSHR misses
1690system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5463 # number of LoadLockedReq MSHR misses
1691system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23402 # number of StoreCondReq MSHR misses
1692system.cpu1.dcache.StoreCondReq_mshr_misses::total 23402 # number of StoreCondReq MSHR misses
1693system.cpu1.dcache.demand_mshr_misses::cpu1.data 272665 # number of demand (read+write) MSHR misses
1694system.cpu1.dcache.demand_mshr_misses::total 272665 # number of demand (read+write) MSHR misses
1695system.cpu1.dcache.overall_mshr_misses::cpu1.data 306038 # number of overall MSHR misses
1696system.cpu1.dcache.overall_mshr_misses::total 306038 # number of overall MSHR misses
1697system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5399 # number of ReadReq MSHR uncacheable
1698system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5399 # number of ReadReq MSHR uncacheable
1699system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4698 # number of WriteReq MSHR uncacheable
1700system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4698 # number of WriteReq MSHR uncacheable
1701system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10097 # number of overall MSHR uncacheable misses
1702system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10097 # number of overall MSHR uncacheable misses
1703system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2348457500 # number of ReadReq MSHR miss cycles
1704system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2348457500 # number of ReadReq MSHR miss cycles
1705system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2649909000 # number of WriteReq MSHR miss cycles
1706system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2649909000 # number of WriteReq MSHR miss cycles
1707system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 556338500 # number of SoftPFReq MSHR miss cycles
1708system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 556338500 # number of SoftPFReq MSHR miss cycles
1709system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95279500 # number of LoadLockedReq MSHR miss cycles
1710system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95279500 # number of LoadLockedReq MSHR miss cycles
1711system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 547474500 # number of StoreCondReq MSHR miss cycles
1712system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 547474500 # number of StoreCondReq MSHR miss cycles
1713system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 537000 # number of StoreCondFailReq MSHR miss cycles
1714system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 537000 # number of StoreCondFailReq MSHR miss cycles
1715system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4998366500 # number of demand (read+write) MSHR miss cycles
1716system.cpu1.dcache.demand_mshr_miss_latency::total 4998366500 # number of demand (read+write) MSHR miss cycles
1717system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5554705000 # number of overall MSHR miss cycles
1718system.cpu1.dcache.overall_mshr_miss_latency::total 5554705000 # number of overall MSHR miss cycles
1719system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 994956000 # number of ReadReq MSHR uncacheable cycles
1720system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 994956000 # number of ReadReq MSHR uncacheable cycles
1721system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 994956000 # number of overall MSHR uncacheable cycles
1722system.cpu1.dcache.overall_mshr_uncacheable_latency::total 994956000 # number of overall MSHR uncacheable cycles
1723system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033752 # mshr miss rate for ReadReq accesses
1724system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033752 # mshr miss rate for ReadReq accesses
1725system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for WriteReq accesses
1726system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026162 # mshr miss rate for WriteReq accesses
1727system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331858 # mshr miss rate for SoftPFReq accesses
1728system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331858 # mshr miss rate for SoftPFReq accesses
1729system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051995 # mshr miss rate for LoadLockedReq accesses
1730system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051995 # mshr miss rate for LoadLockedReq accesses
1731system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227659 # mshr miss rate for StoreCondReq accesses
1732system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227659 # mshr miss rate for StoreCondReq accesses
1733system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030316 # mshr miss rate for demand accesses
1734system.cpu1.dcache.demand_mshr_miss_rate::total 0.030316 # mshr miss rate for demand accesses
1735system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033650 # mshr miss rate for overall accesses
1736system.cpu1.dcache.overall_mshr_miss_rate::total 0.033650 # mshr miss rate for overall accesses
1737system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14135.157665 # average ReadReq mshr miss latency
1738system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14135.157665 # average ReadReq mshr miss latency
1739system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24876.635812 # average WriteReq mshr miss latency
1740system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24876.635812 # average WriteReq mshr miss latency
1741system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16670.317322 # average SoftPFReq mshr miss latency
1742system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16670.317322 # average SoftPFReq mshr miss latency
1743system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17440.874977 # average LoadLockedReq mshr miss latency
1744system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17440.874977 # average LoadLockedReq mshr miss latency
1745system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23394.346637 # average StoreCondReq mshr miss latency
1746system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23394.346637 # average StoreCondReq mshr miss latency
1747system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1748system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1749system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18331.529533 # average overall mshr miss latency
1750system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18331.529533 # average overall mshr miss latency
1751system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18150.376751 # average overall mshr miss latency
1752system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18150.376751 # average overall mshr miss latency
1753system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184285.238007 # average ReadReq mshr uncacheable latency
1754system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184285.238007 # average ReadReq mshr uncacheable latency
1755system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 98539.764286 # average overall mshr uncacheable latency
1756system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 98539.764286 # average overall mshr uncacheable latency
1757system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1758system.cpu1.icache.tags.replacements 1038587 # number of replacements
1759system.cpu1.icache.tags.tagsinuse 498.233977 # Cycle average of tags in use
1760system.cpu1.icache.tags.total_refs 9132995 # Total number of references to valid blocks.
1761system.cpu1.icache.tags.sampled_refs 1039099 # Sample count of references to valid blocks.
1762system.cpu1.icache.tags.avg_refs 8.789341 # Average number of references to valid blocks.
1763system.cpu1.icache.tags.warmup_cycle 72888333000 # Cycle when the warmup percentage was hit.
1764system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.233977 # Average occupied blocks per requestor
1765system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973113 # Average percentage of cache occupancy
1766system.cpu1.icache.tags.occ_percent::total 0.973113 # Average percentage of cache occupancy
1767system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1768system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id
1769system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id
1770system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1771system.cpu1.icache.tags.tag_accesses 21383287 # Number of tag accesses
1772system.cpu1.icache.tags.data_accesses 21383287 # Number of data accesses
1773system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1774system.cpu1.icache.ReadReq_hits::cpu1.inst 9132995 # number of ReadReq hits
1775system.cpu1.icache.ReadReq_hits::total 9132995 # number of ReadReq hits
1776system.cpu1.icache.demand_hits::cpu1.inst 9132995 # number of demand (read+write) hits
1777system.cpu1.icache.demand_hits::total 9132995 # number of demand (read+write) hits
1778system.cpu1.icache.overall_hits::cpu1.inst 9132995 # number of overall hits
1779system.cpu1.icache.overall_hits::total 9132995 # number of overall hits
1780system.cpu1.icache.ReadReq_misses::cpu1.inst 1039099 # number of ReadReq misses
1781system.cpu1.icache.ReadReq_misses::total 1039099 # number of ReadReq misses
1782system.cpu1.icache.demand_misses::cpu1.inst 1039099 # number of demand (read+write) misses
1783system.cpu1.icache.demand_misses::total 1039099 # number of demand (read+write) misses
1784system.cpu1.icache.overall_misses::cpu1.inst 1039099 # number of overall misses
1785system.cpu1.icache.overall_misses::total 1039099 # number of overall misses
1786system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9377315500 # number of ReadReq miss cycles
1787system.cpu1.icache.ReadReq_miss_latency::total 9377315500 # number of ReadReq miss cycles
1788system.cpu1.icache.demand_miss_latency::cpu1.inst 9377315500 # number of demand (read+write) miss cycles
1789system.cpu1.icache.demand_miss_latency::total 9377315500 # number of demand (read+write) miss cycles
1790system.cpu1.icache.overall_miss_latency::cpu1.inst 9377315500 # number of overall miss cycles
1791system.cpu1.icache.overall_miss_latency::total 9377315500 # number of overall miss cycles
1792system.cpu1.icache.ReadReq_accesses::cpu1.inst 10172094 # number of ReadReq accesses(hits+misses)
1793system.cpu1.icache.ReadReq_accesses::total 10172094 # number of ReadReq accesses(hits+misses)
1794system.cpu1.icache.demand_accesses::cpu1.inst 10172094 # number of demand (read+write) accesses
1795system.cpu1.icache.demand_accesses::total 10172094 # number of demand (read+write) accesses
1796system.cpu1.icache.overall_accesses::cpu1.inst 10172094 # number of overall (read+write) accesses
1797system.cpu1.icache.overall_accesses::total 10172094 # number of overall (read+write) accesses
1798system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.102152 # miss rate for ReadReq accesses
1799system.cpu1.icache.ReadReq_miss_rate::total 0.102152 # miss rate for ReadReq accesses
1800system.cpu1.icache.demand_miss_rate::cpu1.inst 0.102152 # miss rate for demand accesses
1801system.cpu1.icache.demand_miss_rate::total 0.102152 # miss rate for demand accesses
1802system.cpu1.icache.overall_miss_rate::cpu1.inst 0.102152 # miss rate for overall accesses
1803system.cpu1.icache.overall_miss_rate::total 0.102152 # miss rate for overall accesses
1804system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9024.467832 # average ReadReq miss latency
1805system.cpu1.icache.ReadReq_avg_miss_latency::total 9024.467832 # average ReadReq miss latency
1806system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9024.467832 # average overall miss latency
1807system.cpu1.icache.demand_avg_miss_latency::total 9024.467832 # average overall miss latency
1808system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9024.467832 # average overall miss latency
1809system.cpu1.icache.overall_avg_miss_latency::total 9024.467832 # average overall miss latency
1810system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1811system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1812system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1813system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1814system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1815system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1816system.cpu1.icache.writebacks::writebacks 1038587 # number of writebacks
1817system.cpu1.icache.writebacks::total 1038587 # number of writebacks
1818system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1039099 # number of ReadReq MSHR misses
1819system.cpu1.icache.ReadReq_mshr_misses::total 1039099 # number of ReadReq MSHR misses
1820system.cpu1.icache.demand_mshr_misses::cpu1.inst 1039099 # number of demand (read+write) MSHR misses
1821system.cpu1.icache.demand_mshr_misses::total 1039099 # number of demand (read+write) MSHR misses
1822system.cpu1.icache.overall_mshr_misses::cpu1.inst 1039099 # number of overall MSHR misses
1823system.cpu1.icache.overall_mshr_misses::total 1039099 # number of overall MSHR misses
1824system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
1825system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable
1826system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
1827system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses
1828system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857766000 # number of ReadReq MSHR miss cycles
1829system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857766000 # number of ReadReq MSHR miss cycles
1830system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857766000 # number of demand (read+write) MSHR miss cycles
1831system.cpu1.icache.demand_mshr_miss_latency::total 8857766000 # number of demand (read+write) MSHR miss cycles
1832system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857766000 # number of overall MSHR miss cycles
1833system.cpu1.icache.overall_mshr_miss_latency::total 8857766000 # number of overall MSHR miss cycles
1834system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10704000 # number of ReadReq MSHR uncacheable cycles
1835system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10704000 # number of ReadReq MSHR uncacheable cycles
1836system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10704000 # number of overall MSHR uncacheable cycles
1837system.cpu1.icache.overall_mshr_uncacheable_latency::total 10704000 # number of overall MSHR uncacheable cycles
1838system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for ReadReq accesses
1839system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.102152 # mshr miss rate for ReadReq accesses
1840system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for demand accesses
1841system.cpu1.icache.demand_mshr_miss_rate::total 0.102152 # mshr miss rate for demand accesses
1842system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for overall accesses
1843system.cpu1.icache.overall_mshr_miss_rate::total 0.102152 # mshr miss rate for overall accesses
1844system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average ReadReq mshr miss latency
1845system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8524.467832 # average ReadReq mshr miss latency
1846system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average overall mshr miss latency
1847system.cpu1.icache.demand_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency
1848system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average overall mshr miss latency
1849system.cpu1.icache.overall_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency
1850system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average ReadReq mshr uncacheable latency
1851system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95571.428571 # average ReadReq mshr uncacheable latency
1852system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average overall mshr uncacheable latency
1853system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95571.428571 # average overall mshr uncacheable latency
1854system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1855system.cpu1.l2cache.prefetcher.num_hwpf_issued 276399 # number of hwpf issued
1856system.cpu1.l2cache.prefetcher.pfIdentified 276459 # number of prefetch candidates identified
1857system.cpu1.l2cache.prefetcher.pfBufferHit 53 # number of redundant prefetches already in prefetch queue
1858system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1859system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1860system.cpu1.l2cache.prefetcher.pfSpanPage 69493 # number of prefetches not generated due to page crossing
1861system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1862system.cpu1.l2cache.tags.replacements 70219 # number of replacements
1863system.cpu1.l2cache.tags.tagsinuse 15563.656432 # Cycle average of tags in use
1864system.cpu1.l2cache.tags.total_refs 2283330 # Total number of references to valid blocks.
1865system.cpu1.l2cache.tags.sampled_refs 85023 # Sample count of references to valid blocks.
1866system.cpu1.l2cache.tags.avg_refs 26.855439 # Average number of references to valid blocks.
1867system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1868system.cpu1.l2cache.tags.occ_blocks::writebacks 14385.822816 # Average occupied blocks per requestor
1869system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 54.124799 # Average occupied blocks per requestor
1870system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.170471 # Average occupied blocks per requestor
1871system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1123.538345 # Average occupied blocks per requestor
1872system.cpu1.l2cache.tags.occ_percent::writebacks 0.878041 # Average percentage of cache occupancy
1873system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003304 # Average percentage of cache occupancy
1874system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000010 # Average percentage of cache occupancy
1875system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.068575 # Average percentage of cache occupancy
1876system.cpu1.l2cache.tags.occ_percent::total 0.949930 # Average percentage of cache occupancy
1877system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1056 # Occupied blocks per task id
1878system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id
1879system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13706 # Occupied blocks per task id
1880system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id
1881system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 291 # Occupied blocks per task id
1882system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 761 # Occupied blocks per task id
1883system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
1884system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id
1885system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id
1886system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id
1887system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5206 # Occupied blocks per task id
1888system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 8191 # Occupied blocks per task id
1889system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064453 # Percentage of cache occupancy per task id
1890system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id
1891system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.836548 # Percentage of cache occupancy per task id
1892system.cpu1.l2cache.tags.tag_accesses 42757972 # Number of tag accesses
1893system.cpu1.l2cache.tags.data_accesses 42757972 # Number of data accesses
1894system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
1895system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 32984 # number of ReadReq hits
1896system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3253 # number of ReadReq hits
1897system.cpu1.l2cache.ReadReq_hits::total 36237 # number of ReadReq hits
1898system.cpu1.l2cache.WritebackDirty_hits::writebacks 134317 # number of WritebackDirty hits
1899system.cpu1.l2cache.WritebackDirty_hits::total 134317 # number of WritebackDirty hits
1900system.cpu1.l2cache.WritebackClean_hits::writebacks 1113970 # number of WritebackClean hits
1901system.cpu1.l2cache.WritebackClean_hits::total 1113970 # number of WritebackClean hits
1902system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37754 # number of ReadExReq hits
1903system.cpu1.l2cache.ReadExReq_hits::total 37754 # number of ReadExReq hits
1904system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1012452 # number of ReadCleanReq hits
1905system.cpu1.l2cache.ReadCleanReq_hits::total 1012452 # number of ReadCleanReq hits
1906system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 130088 # number of ReadSharedReq hits
1907system.cpu1.l2cache.ReadSharedReq_hits::total 130088 # number of ReadSharedReq hits
1908system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 32984 # number of demand (read+write) hits
1909system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3253 # number of demand (read+write) hits
1910system.cpu1.l2cache.demand_hits::cpu1.inst 1012452 # number of demand (read+write) hits
1911system.cpu1.l2cache.demand_hits::cpu1.data 167842 # number of demand (read+write) hits
1912system.cpu1.l2cache.demand_hits::total 1216531 # number of demand (read+write) hits
1913system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 32984 # number of overall hits
1914system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3253 # number of overall hits
1915system.cpu1.l2cache.overall_hits::cpu1.inst 1012452 # number of overall hits
1916system.cpu1.l2cache.overall_hits::cpu1.data 167842 # number of overall hits
1917system.cpu1.l2cache.overall_hits::total 1216531 # number of overall hits
1918system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 703 # number of ReadReq misses
1919system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 237 # number of ReadReq misses
1920system.cpu1.l2cache.ReadReq_misses::total 940 # number of ReadReq misses
1921system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 31976 # number of UpgradeReq misses
1922system.cpu1.l2cache.UpgradeReq_misses::total 31976 # number of UpgradeReq misses
1923system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23401 # number of SCUpgradeReq misses
1924system.cpu1.l2cache.SCUpgradeReq_misses::total 23401 # number of SCUpgradeReq misses
1925system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
1926system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
1927system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36794 # number of ReadExReq misses
1928system.cpu1.l2cache.ReadExReq_misses::total 36794 # number of ReadExReq misses
1929system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 26647 # number of ReadCleanReq misses
1930system.cpu1.l2cache.ReadCleanReq_misses::total 26647 # number of ReadCleanReq misses
1931system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 74889 # number of ReadSharedReq misses
1932system.cpu1.l2cache.ReadSharedReq_misses::total 74889 # number of ReadSharedReq misses
1933system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 703 # number of demand (read+write) misses
1934system.cpu1.l2cache.demand_misses::cpu1.itb.walker 237 # number of demand (read+write) misses
1935system.cpu1.l2cache.demand_misses::cpu1.inst 26647 # number of demand (read+write) misses
1936system.cpu1.l2cache.demand_misses::cpu1.data 111683 # number of demand (read+write) misses
1937system.cpu1.l2cache.demand_misses::total 139270 # number of demand (read+write) misses
1938system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 703 # number of overall misses
1939system.cpu1.l2cache.overall_misses::cpu1.itb.walker 237 # number of overall misses
1940system.cpu1.l2cache.overall_misses::cpu1.inst 26647 # number of overall misses
1941system.cpu1.l2cache.overall_misses::cpu1.data 111683 # number of overall misses
1942system.cpu1.l2cache.overall_misses::total 139270 # number of overall misses
1943system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17920000 # number of ReadReq miss cycles
1944system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4860500 # number of ReadReq miss cycles
1945system.cpu1.l2cache.ReadReq_miss_latency::total 22780500 # number of ReadReq miss cycles
1946system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 79820500 # number of UpgradeReq miss cycles
1947system.cpu1.l2cache.UpgradeReq_miss_latency::total 79820500 # number of UpgradeReq miss cycles
1948system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 32048000 # number of SCUpgradeReq miss cycles
1949system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 32048000 # number of SCUpgradeReq miss cycles
1950system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 521000 # number of SCUpgradeFailReq miss cycles
1951system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 521000 # number of SCUpgradeFailReq miss cycles
1952system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1478483000 # number of ReadExReq miss cycles
1953system.cpu1.l2cache.ReadExReq_miss_latency::total 1478483000 # number of ReadExReq miss cycles
1954system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1147386500 # number of ReadCleanReq miss cycles
1955system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1147386500 # number of ReadCleanReq miss cycles
1956system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1827426992 # number of ReadSharedReq miss cycles
1957system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1827426992 # number of ReadSharedReq miss cycles
1958system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17920000 # number of demand (read+write) miss cycles
1959system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4860500 # number of demand (read+write) miss cycles
1960system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1147386500 # number of demand (read+write) miss cycles
1961system.cpu1.l2cache.demand_miss_latency::cpu1.data 3305909992 # number of demand (read+write) miss cycles
1962system.cpu1.l2cache.demand_miss_latency::total 4476076992 # number of demand (read+write) miss cycles
1963system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17920000 # number of overall miss cycles
1964system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4860500 # number of overall miss cycles
1965system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1147386500 # number of overall miss cycles
1966system.cpu1.l2cache.overall_miss_latency::cpu1.data 3305909992 # number of overall miss cycles
1967system.cpu1.l2cache.overall_miss_latency::total 4476076992 # number of overall miss cycles
1968system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33687 # number of ReadReq accesses(hits+misses)
1969system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3490 # number of ReadReq accesses(hits+misses)
1970system.cpu1.l2cache.ReadReq_accesses::total 37177 # number of ReadReq accesses(hits+misses)
1971system.cpu1.l2cache.WritebackDirty_accesses::writebacks 134317 # number of WritebackDirty accesses(hits+misses)
1972system.cpu1.l2cache.WritebackDirty_accesses::total 134317 # number of WritebackDirty accesses(hits+misses)
1973system.cpu1.l2cache.WritebackClean_accesses::writebacks 1113970 # number of WritebackClean accesses(hits+misses)
1974system.cpu1.l2cache.WritebackClean_accesses::total 1113970 # number of WritebackClean accesses(hits+misses)
1975system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31976 # number of UpgradeReq accesses(hits+misses)
1976system.cpu1.l2cache.UpgradeReq_accesses::total 31976 # number of UpgradeReq accesses(hits+misses)
1977system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23401 # number of SCUpgradeReq accesses(hits+misses)
1978system.cpu1.l2cache.SCUpgradeReq_accesses::total 23401 # number of SCUpgradeReq accesses(hits+misses)
1979system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
1980system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
1981system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74548 # number of ReadExReq accesses(hits+misses)
1982system.cpu1.l2cache.ReadExReq_accesses::total 74548 # number of ReadExReq accesses(hits+misses)
1983system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1039099 # number of ReadCleanReq accesses(hits+misses)
1984system.cpu1.l2cache.ReadCleanReq_accesses::total 1039099 # number of ReadCleanReq accesses(hits+misses)
1985system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 204977 # number of ReadSharedReq accesses(hits+misses)
1986system.cpu1.l2cache.ReadSharedReq_accesses::total 204977 # number of ReadSharedReq accesses(hits+misses)
1987system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33687 # number of demand (read+write) accesses
1988system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3490 # number of demand (read+write) accesses
1989system.cpu1.l2cache.demand_accesses::cpu1.inst 1039099 # number of demand (read+write) accesses
1990system.cpu1.l2cache.demand_accesses::cpu1.data 279525 # number of demand (read+write) accesses
1991system.cpu1.l2cache.demand_accesses::total 1355801 # number of demand (read+write) accesses
1992system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33687 # number of overall (read+write) accesses
1993system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3490 # number of overall (read+write) accesses
1994system.cpu1.l2cache.overall_accesses::cpu1.inst 1039099 # number of overall (read+write) accesses
1995system.cpu1.l2cache.overall_accesses::cpu1.data 279525 # number of overall (read+write) accesses
1996system.cpu1.l2cache.overall_accesses::total 1355801 # number of overall (read+write) accesses
1997system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020869 # miss rate for ReadReq accesses
1998system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.067908 # miss rate for ReadReq accesses
1999system.cpu1.l2cache.ReadReq_miss_rate::total 0.025284 # miss rate for ReadReq accesses
2000system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2001system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2002system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2003system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2004system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2005system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2006system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.493561 # miss rate for ReadExReq accesses
2007system.cpu1.l2cache.ReadExReq_miss_rate::total 0.493561 # miss rate for ReadExReq accesses
2008system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025644 # miss rate for ReadCleanReq accesses
2009system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025644 # miss rate for ReadCleanReq accesses
2010system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.365353 # miss rate for ReadSharedReq accesses
2011system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.365353 # miss rate for ReadSharedReq accesses
2012system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020869 # miss rate for demand accesses
2013system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.067908 # miss rate for demand accesses
2014system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025644 # miss rate for demand accesses
2015system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.399546 # miss rate for demand accesses
2016system.cpu1.l2cache.demand_miss_rate::total 0.102722 # miss rate for demand accesses
2017system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020869 # miss rate for overall accesses
2018system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.067908 # miss rate for overall accesses
2019system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025644 # miss rate for overall accesses
2020system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.399546 # miss rate for overall accesses
2021system.cpu1.l2cache.overall_miss_rate::total 0.102722 # miss rate for overall accesses
2022system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25490.753912 # average ReadReq miss latency
2023system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20508.438819 # average ReadReq miss latency
2024system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24234.574468 # average ReadReq miss latency
2025system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2496.262822 # average UpgradeReq miss latency
2026system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2496.262822 # average UpgradeReq miss latency
2027system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1369.514123 # average SCUpgradeReq miss latency
2028system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1369.514123 # average SCUpgradeReq miss latency
2029system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 521000 # average SCUpgradeFailReq miss latency
2030system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 521000 # average SCUpgradeFailReq miss latency
2031system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40182.720009 # average ReadExReq miss latency
2032system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40182.720009 # average ReadExReq miss latency
2033system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 43058.749578 # average ReadCleanReq miss latency
2034system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 43058.749578 # average ReadCleanReq miss latency
2035system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24401.807902 # average ReadSharedReq miss latency
2036system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24401.807902 # average ReadSharedReq miss latency
2037system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25490.753912 # average overall miss latency
2038system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20508.438819 # average overall miss latency
2039system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 43058.749578 # average overall miss latency
2040system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29600.834433 # average overall miss latency
2041system.cpu1.l2cache.demand_avg_miss_latency::total 32139.563380 # average overall miss latency
2042system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25490.753912 # average overall miss latency
2043system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20508.438819 # average overall miss latency
2044system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 43058.749578 # average overall miss latency
2045system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29600.834433 # average overall miss latency
2046system.cpu1.l2cache.overall_avg_miss_latency::total 32139.563380 # average overall miss latency
2047system.cpu1.l2cache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
2048system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2049system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
2050system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2051system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked
2052system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2053system.cpu1.l2cache.unused_prefetches 2265 # number of HardPF blocks evicted w/o reference
2054system.cpu1.l2cache.writebacks::writebacks 42373 # number of writebacks
2055system.cpu1.l2cache.writebacks::total 42373 # number of writebacks
2056system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 331 # number of ReadExReq MSHR hits
2057system.cpu1.l2cache.ReadExReq_mshr_hits::total 331 # number of ReadExReq MSHR hits
2058system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 22 # number of ReadCleanReq MSHR hits
2059system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 22 # number of ReadCleanReq MSHR hits
2060system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 129 # number of ReadSharedReq MSHR hits
2061system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 129 # number of ReadSharedReq MSHR hits
2062system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits
2063system.cpu1.l2cache.demand_mshr_hits::cpu1.data 460 # number of demand (read+write) MSHR hits
2064system.cpu1.l2cache.demand_mshr_hits::total 482 # number of demand (read+write) MSHR hits
2065system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits
2066system.cpu1.l2cache.overall_mshr_hits::cpu1.data 460 # number of overall MSHR hits
2067system.cpu1.l2cache.overall_mshr_hits::total 482 # number of overall MSHR hits
2068system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 703 # number of ReadReq MSHR misses
2069system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 237 # number of ReadReq MSHR misses
2070system.cpu1.l2cache.ReadReq_mshr_misses::total 940 # number of ReadReq MSHR misses
2071system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 38782 # number of HardPFReq MSHR misses
2072system.cpu1.l2cache.HardPFReq_mshr_misses::total 38782 # number of HardPFReq MSHR misses
2073system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 31976 # number of UpgradeReq MSHR misses
2074system.cpu1.l2cache.UpgradeReq_mshr_misses::total 31976 # number of UpgradeReq MSHR misses
2075system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23401 # number of SCUpgradeReq MSHR misses
2076system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23401 # number of SCUpgradeReq MSHR misses
2077system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
2078system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
2079system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 36463 # number of ReadExReq MSHR misses
2080system.cpu1.l2cache.ReadExReq_mshr_misses::total 36463 # number of ReadExReq MSHR misses
2081system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 26625 # number of ReadCleanReq MSHR misses
2082system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 26625 # number of ReadCleanReq MSHR misses
2083system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 74760 # number of ReadSharedReq MSHR misses
2084system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 74760 # number of ReadSharedReq MSHR misses
2085system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 703 # number of demand (read+write) MSHR misses
2086system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 237 # number of demand (read+write) MSHR misses
2087system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 26625 # number of demand (read+write) MSHR misses
2088system.cpu1.l2cache.demand_mshr_misses::cpu1.data 111223 # number of demand (read+write) MSHR misses
2089system.cpu1.l2cache.demand_mshr_misses::total 138788 # number of demand (read+write) MSHR misses
2090system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 703 # number of overall MSHR misses
2091system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 237 # number of overall MSHR misses
2092system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 26625 # number of overall MSHR misses
2093system.cpu1.l2cache.overall_mshr_misses::cpu1.data 111223 # number of overall MSHR misses
2094system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 38782 # number of overall MSHR misses
2095system.cpu1.l2cache.overall_mshr_misses::total 177570 # number of overall MSHR misses
2096system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
2097system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5399 # number of ReadReq MSHR uncacheable
2098system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5511 # number of ReadReq MSHR uncacheable
2099system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 4698 # number of WriteReq MSHR uncacheable
2100system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 4698 # number of WriteReq MSHR uncacheable
2101system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
2102system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10097 # number of overall MSHR uncacheable misses
2103system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10209 # number of overall MSHR uncacheable misses
2104system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of ReadReq MSHR miss cycles
2105system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3438500 # number of ReadReq MSHR miss cycles
2106system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 17140500 # number of ReadReq MSHR miss cycles
2107system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1312457547 # number of HardPFReq MSHR miss cycles
2108system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1312457547 # number of HardPFReq MSHR miss cycles
2109system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 566974500 # number of UpgradeReq MSHR miss cycles
2110system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 566974500 # number of UpgradeReq MSHR miss cycles
2111system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 370291999 # number of SCUpgradeReq MSHR miss cycles
2112system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 370291999 # number of SCUpgradeReq MSHR miss cycles
2113system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 461000 # number of SCUpgradeFailReq MSHR miss cycles
2114system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 461000 # number of SCUpgradeFailReq MSHR miss cycles
2115system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1222094000 # number of ReadExReq MSHR miss cycles
2116system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1222094000 # number of ReadExReq MSHR miss cycles
2117system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 987020000 # number of ReadCleanReq MSHR miss cycles
2118system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 987020000 # number of ReadCleanReq MSHR miss cycles
2119system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1373517992 # number of ReadSharedReq MSHR miss cycles
2120system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1373517992 # number of ReadSharedReq MSHR miss cycles
2121system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of demand (read+write) MSHR miss cycles
2122system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3438500 # number of demand (read+write) MSHR miss cycles
2123system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 987020000 # number of demand (read+write) MSHR miss cycles
2124system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2595611992 # number of demand (read+write) MSHR miss cycles
2125system.cpu1.l2cache.demand_mshr_miss_latency::total 3599772492 # number of demand (read+write) MSHR miss cycles
2126system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of overall MSHR miss cycles
2127system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3438500 # number of overall MSHR miss cycles
2128system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 987020000 # number of overall MSHR miss cycles
2129system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2595611992 # number of overall MSHR miss cycles
2130system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1312457547 # number of overall MSHR miss cycles
2131system.cpu1.l2cache.overall_mshr_miss_latency::total 4912230039 # number of overall MSHR miss cycles
2132system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9808000 # number of ReadReq MSHR uncacheable cycles
2133system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 951737000 # number of ReadReq MSHR uncacheable cycles
2134system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 961545000 # number of ReadReq MSHR uncacheable cycles
2135system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9808000 # number of overall MSHR uncacheable cycles
2136system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 951737000 # number of overall MSHR uncacheable cycles
2137system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 961545000 # number of overall MSHR uncacheable cycles
2138system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for ReadReq accesses
2139system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for ReadReq accesses
2140system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025284 # mshr miss rate for ReadReq accesses
2141system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2142system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2143system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2144system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2145system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2146system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2147system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2148system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2149system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.489121 # mshr miss rate for ReadExReq accesses
2150system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.489121 # mshr miss rate for ReadExReq accesses
2151system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for ReadCleanReq accesses
2152system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.025623 # mshr miss rate for ReadCleanReq accesses
2153system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.364724 # mshr miss rate for ReadSharedReq accesses
2154system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.364724 # mshr miss rate for ReadSharedReq accesses
2155system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for demand accesses
2156system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for demand accesses
2157system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for demand accesses
2158system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.397900 # mshr miss rate for demand accesses
2159system.cpu1.l2cache.demand_mshr_miss_rate::total 0.102366 # mshr miss rate for demand accesses
2160system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for overall accesses
2161system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for overall accesses
2162system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for overall accesses
2163system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.397900 # mshr miss rate for overall accesses
2164system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2165system.cpu1.l2cache.overall_mshr_miss_rate::total 0.130971 # mshr miss rate for overall accesses
2166system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average ReadReq mshr miss latency
2167system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average ReadReq mshr miss latency
2168system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18234.574468 # average ReadReq mshr miss latency
2169system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average HardPFReq mshr miss latency
2170system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33841.925300 # average HardPFReq mshr miss latency
2171system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17731.251564 # average UpgradeReq mshr miss latency
2172system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17731.251564 # average UpgradeReq mshr miss latency
2173system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15823.768172 # average SCUpgradeReq mshr miss latency
2174system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15823.768172 # average SCUpgradeReq mshr miss latency
2175system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 461000 # average SCUpgradeFailReq mshr miss latency
2176system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461000 # average SCUpgradeFailReq mshr miss latency
2177system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33516.002523 # average ReadExReq mshr miss latency
2178system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33516.002523 # average ReadExReq mshr miss latency
2179system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average ReadCleanReq mshr miss latency
2180system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37071.173709 # average ReadCleanReq mshr miss latency
2181system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18372.364794 # average ReadSharedReq mshr miss latency
2182system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18372.364794 # average ReadSharedReq mshr miss latency
2183system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency
2184system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency
2185system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency
2186system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency
2187system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25937.202726 # average overall mshr miss latency
2188system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency
2189system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency
2190system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency
2191system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency
2192system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average overall mshr miss latency
2193system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27663.625832 # average overall mshr miss latency
2194system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average ReadReq mshr uncacheable latency
2195system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176280.237081 # average ReadReq mshr uncacheable latency
2196system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174477.408819 # average ReadReq mshr uncacheable latency
2197system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average overall mshr uncacheable latency
2198system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 94259.383975 # average overall mshr uncacheable latency
2199system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 94186.012342 # average overall mshr uncacheable latency
2200system.cpu1.toL2Bus.snoop_filter.tot_requests 2654318 # Total number of requests made to the snoop filter.
2201system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1335711 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2202system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 21986 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2203system.cpu1.toL2Bus.snoop_filter.tot_snoops 212975 # Total number of snoops made to the snoop filter.
2204system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 211032 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2205system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1943 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2206system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
2207system.cpu1.toL2Bus.trans_dist::ReadReq 47306 # Transaction distribution
2208system.cpu1.toL2Bus.trans_dist::ReadResp 1331970 # Transaction distribution
2209system.cpu1.toL2Bus.trans_dist::WriteReq 4698 # Transaction distribution
2210system.cpu1.toL2Bus.trans_dist::WriteResp 4698 # Transaction distribution
2211system.cpu1.toL2Bus.trans_dist::WritebackDirty 177822 # Transaction distribution
2212system.cpu1.toL2Bus.trans_dist::WritebackClean 1135956 # Transaction distribution
2213system.cpu1.toL2Bus.trans_dist::CleanEvict 137781 # Transaction distribution
2214system.cpu1.toL2Bus.trans_dist::HardPFReq 47279 # Transaction distribution
2215system.cpu1.toL2Bus.trans_dist::UpgradeReq 75014 # Transaction distribution
2216system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42924 # Transaction distribution
2217system.cpu1.toL2Bus.trans_dist::UpgradeResp 89713 # Transaction distribution
2218system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution
2219system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
2220system.cpu1.toL2Bus.trans_dist::ReadExReq 82844 # Transaction distribution
2221system.cpu1.toL2Bus.trans_dist::ReadExResp 80563 # Transaction distribution
2222system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1039099 # Transaction distribution
2223system.cpu1.toL2Bus.trans_dist::ReadSharedReq 293637 # Transaction distribution
2224system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution
2225system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3117009 # Packet count per connected master and slave (bytes)
2226system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1002647 # Packet count per connected master and slave (bytes)
2227system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8284 # Packet count per connected master and slave (bytes)
2228system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70688 # Packet count per connected master and slave (bytes)
2229system.cpu1.toL2Bus.pkt_count::total 4198628 # Packet count per connected master and slave (bytes)
2230system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 132979072 # Cumulative packet size per connected master and slave (bytes)
2231system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35729427 # Cumulative packet size per connected master and slave (bytes)
2232system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13960 # Cumulative packet size per connected master and slave (bytes)
2233system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 134748 # Cumulative packet size per connected master and slave (bytes)
2234system.cpu1.toL2Bus.pkt_size::total 168857207 # Cumulative packet size per connected master and slave (bytes)
2235system.cpu1.toL2Bus.snoops 473910 # Total snoops (count)
2236system.cpu1.toL2Bus.snoopTraffic 5785960 # Total snoop traffic (bytes)
2237system.cpu1.toL2Bus.snoop_fanout::samples 1814338 # Request fanout histogram
2238system.cpu1.toL2Bus.snoop_fanout::mean 0.136111 # Request fanout histogram
2239system.cpu1.toL2Bus.snoop_fanout::stdev 0.346015 # Request fanout histogram
2240system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2241system.cpu1.toL2Bus.snoop_fanout::0 1569330 86.50% 86.50% # Request fanout histogram
2242system.cpu1.toL2Bus.snoop_fanout::1 243065 13.40% 99.89% # Request fanout histogram
2243system.cpu1.toL2Bus.snoop_fanout::2 1943 0.11% 100.00% # Request fanout histogram
2244system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2245system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2246system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2247system.cpu1.toL2Bus.snoop_fanout::total 1814338 # Request fanout histogram
2248system.cpu1.toL2Bus.reqLayer0.occupancy 2620766990 # Layer occupancy (ticks)
2249system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2250system.cpu1.toL2Bus.snoopLayer0.occupancy 87124018 # Layer occupancy (ticks)
2251system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2252system.cpu1.toL2Bus.respLayer0.occupancy 1558968196 # Layer occupancy (ticks)
2253system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2254system.cpu1.toL2Bus.respLayer1.occupancy 456771923 # Layer occupancy (ticks)
2255system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2256system.cpu1.toL2Bus.respLayer2.occupancy 4794998 # Layer occupancy (ticks)
2257system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2258system.cpu1.toL2Bus.respLayer3.occupancy 37016968 # Layer occupancy (ticks)
2259system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2260system.iobus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
2261system.iobus.trans_dist::ReadReq 31014 # Transaction distribution
2262system.iobus.trans_dist::ReadResp 31014 # Transaction distribution
2263system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
2264system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
2265system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
2266system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2267system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2268system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2269system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2270system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2271system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes)
2272system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2273system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2274system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2275system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2276system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2277system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2278system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2279system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2280system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2281system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2282system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2283system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2284system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
2285system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes)
2286system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes)
2287system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes)
2288system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
2289system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2290system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2291system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2292system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2293system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2294system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes)
2295system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2296system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2297system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2298system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2299system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2300system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2301system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2302system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2303system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2304system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2305system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2306system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2307system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
2308system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes)
2309system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes)
2310system.iobus.pkt_size::total 2484074 # Cumulative packet size per connected master and slave (bytes)
2311system.iobus.reqLayer0.occupancy 48375000 # Layer occupancy (ticks)
2312system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2313system.iobus.reqLayer1.occupancy 113500 # Layer occupancy (ticks)
2314system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2315system.iobus.reqLayer2.occupancy 329000 # Layer occupancy (ticks)
2316system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2317system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks)
2318system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2319system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks)
2320system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2321system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks)
2322system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2323system.iobus.reqLayer8.occupancy 619500 # Layer occupancy (ticks)
2324system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2325system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks)
2326system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2327system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
2328system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2329system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
2330system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2331system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2332system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2333system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks)
2334system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2335system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2336system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2337system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks)
2338system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2339system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2340system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2341system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2342system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2343system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
2344system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2345system.iobus.reqLayer23.occupancy 6358000 # Layer occupancy (ticks)
2346system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2347system.iobus.reqLayer24.occupancy 38893000 # Layer occupancy (ticks)
2348system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2349system.iobus.reqLayer25.occupancy 187720844 # Layer occupancy (ticks)
2350system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2351system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks)
2352system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2353system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks)
2354system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2355system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
2356system.iocache.tags.replacements 36462 # number of replacements
2357system.iocache.tags.tagsinuse 14.359878 # Cycle average of tags in use
2358system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2359system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks.
2360system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2361system.iocache.tags.warmup_cycle 271405535000 # Cycle when the warmup percentage was hit.
2362system.iocache.tags.occ_blocks::realview.ide 14.359878 # Average occupied blocks per requestor
2363system.iocache.tags.occ_percent::realview.ide 0.897492 # Average percentage of cache occupancy
2364system.iocache.tags.occ_percent::total 0.897492 # Average percentage of cache occupancy
2365system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2366system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2367system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2368system.iocache.tags.tag_accesses 328320 # Number of tag accesses
2369system.iocache.tags.data_accesses 328320 # Number of data accesses
2370system.iocache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
2371system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses
2372system.iocache.ReadReq_misses::total 256 # number of ReadReq misses
2373system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2374system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2375system.iocache.demand_misses::realview.ide 36480 # number of demand (read+write) misses
2376system.iocache.demand_misses::total 36480 # number of demand (read+write) misses
2377system.iocache.overall_misses::realview.ide 36480 # number of overall misses
2378system.iocache.overall_misses::total 36480 # number of overall misses
2379system.iocache.ReadReq_miss_latency::realview.ide 33042377 # number of ReadReq miss cycles
2380system.iocache.ReadReq_miss_latency::total 33042377 # number of ReadReq miss cycles
2381system.iocache.WriteLineReq_miss_latency::realview.ide 4307289467 # number of WriteLineReq miss cycles
2382system.iocache.WriteLineReq_miss_latency::total 4307289467 # number of WriteLineReq miss cycles
2383system.iocache.demand_miss_latency::realview.ide 4340331844 # number of demand (read+write) miss cycles
2384system.iocache.demand_miss_latency::total 4340331844 # number of demand (read+write) miss cycles
2385system.iocache.overall_miss_latency::realview.ide 4340331844 # number of overall miss cycles
2386system.iocache.overall_miss_latency::total 4340331844 # number of overall miss cycles
2387system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses)
2388system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses)
2389system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2390system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2391system.iocache.demand_accesses::realview.ide 36480 # number of demand (read+write) accesses
2392system.iocache.demand_accesses::total 36480 # number of demand (read+write) accesses
2393system.iocache.overall_accesses::realview.ide 36480 # number of overall (read+write) accesses
2394system.iocache.overall_accesses::total 36480 # number of overall (read+write) accesses
2395system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2396system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2397system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2398system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2399system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2400system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2401system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2402system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2403system.iocache.ReadReq_avg_miss_latency::realview.ide 129071.785156 # average ReadReq miss latency
2404system.iocache.ReadReq_avg_miss_latency::total 129071.785156 # average ReadReq miss latency
2405system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118907.063466 # average WriteLineReq miss latency
2406system.iocache.WriteLineReq_avg_miss_latency::total 118907.063466 # average WriteLineReq miss latency
2407system.iocache.demand_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency
2408system.iocache.demand_avg_miss_latency::total 118978.394846 # average overall miss latency
2409system.iocache.overall_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency
2410system.iocache.overall_avg_miss_latency::total 118978.394846 # average overall miss latency
2411system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked
2412system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2413system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked
2414system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2415system.iocache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked
2416system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2417system.iocache.writebacks::writebacks 36206 # number of writebacks
2418system.iocache.writebacks::total 36206 # number of writebacks
2419system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses
2420system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses
2421system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2422system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2423system.iocache.demand_mshr_misses::realview.ide 36480 # number of demand (read+write) MSHR misses
2424system.iocache.demand_mshr_misses::total 36480 # number of demand (read+write) MSHR misses
2425system.iocache.overall_mshr_misses::realview.ide 36480 # number of overall MSHR misses
2426system.iocache.overall_mshr_misses::total 36480 # number of overall MSHR misses
2427system.iocache.ReadReq_mshr_miss_latency::realview.ide 20242377 # number of ReadReq MSHR miss cycles
2428system.iocache.ReadReq_mshr_miss_latency::total 20242377 # number of ReadReq MSHR miss cycles
2429system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493740476 # number of WriteLineReq MSHR miss cycles
2430system.iocache.WriteLineReq_mshr_miss_latency::total 2493740476 # number of WriteLineReq MSHR miss cycles
2431system.iocache.demand_mshr_miss_latency::realview.ide 2513982853 # number of demand (read+write) MSHR miss cycles
2432system.iocache.demand_mshr_miss_latency::total 2513982853 # number of demand (read+write) MSHR miss cycles
2433system.iocache.overall_mshr_miss_latency::realview.ide 2513982853 # number of overall MSHR miss cycles
2434system.iocache.overall_mshr_miss_latency::total 2513982853 # number of overall MSHR miss cycles
2435system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2436system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2437system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2438system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2439system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2440system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2441system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2442system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2443system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79071.785156 # average ReadReq mshr miss latency
2444system.iocache.ReadReq_avg_mshr_miss_latency::total 79071.785156 # average ReadReq mshr miss latency
2445system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68842.217204 # average WriteLineReq mshr miss latency
2446system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68842.217204 # average WriteLineReq mshr miss latency
2447system.iocache.demand_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency
2448system.iocache.demand_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency
2449system.iocache.overall_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency
2450system.iocache.overall_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency
2451system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
2452system.l2c.tags.replacements 135113 # number of replacements
2453system.l2c.tags.tagsinuse 63251.941629 # Cycle average of tags in use
2454system.l2c.tags.total_refs 475115 # Total number of references to valid blocks.
2455system.l2c.tags.sampled_refs 198978 # Sample count of references to valid blocks.
2456system.l2c.tags.avg_refs 2.387777 # Average number of references to valid blocks.
2457system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2458system.l2c.tags.occ_blocks::writebacks 14216.048080 # Average occupied blocks per requestor
2459system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.910809 # Average occupied blocks per requestor
2460system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033810 # Average occupied blocks per requestor
2461system.l2c.tags.occ_blocks::cpu0.inst 7426.792759 # Average occupied blocks per requestor
2462system.l2c.tags.occ_blocks::cpu0.data 2102.106662 # Average occupied blocks per requestor
2463system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29896.915616 # Average occupied blocks per requestor
2464system.l2c.tags.occ_blocks::cpu1.dtb.walker 20.238831 # Average occupied blocks per requestor
2465system.l2c.tags.occ_blocks::cpu1.inst 3811.016358 # Average occupied blocks per requestor
2466system.l2c.tags.occ_blocks::cpu1.data 1509.520853 # Average occupied blocks per requestor
2467system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4194.357849 # Average occupied blocks per requestor
2468system.l2c.tags.occ_percent::writebacks 0.216920 # Average percentage of cache occupancy
2469system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001143 # Average percentage of cache occupancy
2470system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2471system.l2c.tags.occ_percent::cpu0.inst 0.113324 # Average percentage of cache occupancy
2472system.l2c.tags.occ_percent::cpu0.data 0.032076 # Average percentage of cache occupancy
2473system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.456191 # Average percentage of cache occupancy
2474system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000309 # Average percentage of cache occupancy
2475system.l2c.tags.occ_percent::cpu1.inst 0.058151 # Average percentage of cache occupancy
2476system.l2c.tags.occ_percent::cpu1.data 0.023033 # Average percentage of cache occupancy
2477system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064001 # Average percentage of cache occupancy
2478system.l2c.tags.occ_percent::total 0.965148 # Average percentage of cache occupancy
2479system.l2c.tags.occ_task_id_blocks::1022 27324 # Occupied blocks per task id
2480system.l2c.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id
2481system.l2c.tags.occ_task_id_blocks::1024 36452 # Occupied blocks per task id
2482system.l2c.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
2483system.l2c.tags.age_task_id_blocks_1022::2 105 # Occupied blocks per task id
2484system.l2c.tags.age_task_id_blocks_1022::3 4822 # Occupied blocks per task id
2485system.l2c.tags.age_task_id_blocks_1022::4 22394 # Occupied blocks per task id
2486system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
2487system.l2c.tags.age_task_id_blocks_1023::4 88 # Occupied blocks per task id
2488system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
2489system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
2490system.l2c.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id
2491system.l2c.tags.age_task_id_blocks_1024::3 3262 # Occupied blocks per task id
2492system.l2c.tags.age_task_id_blocks_1024::4 32736 # Occupied blocks per task id
2493system.l2c.tags.occ_task_id_percent::1022 0.416931 # Percentage of cache occupancy per task id
2494system.l2c.tags.occ_task_id_percent::1023 0.001358 # Percentage of cache occupancy per task id
2495system.l2c.tags.occ_task_id_percent::1024 0.556213 # Percentage of cache occupancy per task id
2496system.l2c.tags.tag_accesses 6444953 # Number of tag accesses
2497system.l2c.tags.data_accesses 6444953 # Number of data accesses
2498system.l2c.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
2499system.l2c.WritebackDirty_hits::writebacks 270033 # number of WritebackDirty hits
2500system.l2c.WritebackDirty_hits::total 270033 # number of WritebackDirty hits
2501system.l2c.UpgradeReq_hits::cpu0.data 32996 # number of UpgradeReq hits
2502system.l2c.UpgradeReq_hits::cpu1.data 3857 # number of UpgradeReq hits
2503system.l2c.UpgradeReq_hits::total 36853 # number of UpgradeReq hits
2504system.l2c.SCUpgradeReq_hits::cpu0.data 2004 # number of SCUpgradeReq hits
2505system.l2c.SCUpgradeReq_hits::cpu1.data 1040 # number of SCUpgradeReq hits
2506system.l2c.SCUpgradeReq_hits::total 3044 # number of SCUpgradeReq hits
2507system.l2c.ReadExReq_hits::cpu0.data 3941 # number of ReadExReq hits
2508system.l2c.ReadExReq_hits::cpu1.data 1936 # number of ReadExReq hits
2509system.l2c.ReadExReq_hits::total 5877 # number of ReadExReq hits
2510system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 357 # number of ReadSharedReq hits
2511system.l2c.ReadSharedReq_hits::cpu0.itb.walker 67 # number of ReadSharedReq hits
2512system.l2c.ReadSharedReq_hits::cpu0.inst 40247 # number of ReadSharedReq hits
2513system.l2c.ReadSharedReq_hits::cpu0.data 47388 # number of ReadSharedReq hits
2514system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 44871 # number of ReadSharedReq hits
2515system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 179 # number of ReadSharedReq hits
2516system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits
2517system.l2c.ReadSharedReq_hits::cpu1.inst 20863 # number of ReadSharedReq hits
2518system.l2c.ReadSharedReq_hits::cpu1.data 12359 # number of ReadSharedReq hits
2519system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8223 # number of ReadSharedReq hits
2520system.l2c.ReadSharedReq_hits::total 174583 # number of ReadSharedReq hits
2521system.l2c.demand_hits::cpu0.dtb.walker 357 # number of demand (read+write) hits
2522system.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits
2523system.l2c.demand_hits::cpu0.inst 40247 # number of demand (read+write) hits
2524system.l2c.demand_hits::cpu0.data 51329 # number of demand (read+write) hits
2525system.l2c.demand_hits::cpu0.l2cache.prefetcher 44871 # number of demand (read+write) hits
2526system.l2c.demand_hits::cpu1.dtb.walker 179 # number of demand (read+write) hits
2527system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits
2528system.l2c.demand_hits::cpu1.inst 20863 # number of demand (read+write) hits
2529system.l2c.demand_hits::cpu1.data 14295 # number of demand (read+write) hits
2530system.l2c.demand_hits::cpu1.l2cache.prefetcher 8223 # number of demand (read+write) hits
2531system.l2c.demand_hits::total 180460 # number of demand (read+write) hits
2532system.l2c.overall_hits::cpu0.dtb.walker 357 # number of overall hits
2533system.l2c.overall_hits::cpu0.itb.walker 67 # number of overall hits
2534system.l2c.overall_hits::cpu0.inst 40247 # number of overall hits
2535system.l2c.overall_hits::cpu0.data 51329 # number of overall hits
2536system.l2c.overall_hits::cpu0.l2cache.prefetcher 44871 # number of overall hits
2537system.l2c.overall_hits::cpu1.dtb.walker 179 # number of overall hits
2538system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits
2539system.l2c.overall_hits::cpu1.inst 20863 # number of overall hits
2540system.l2c.overall_hits::cpu1.data 14295 # number of overall hits
2541system.l2c.overall_hits::cpu1.l2cache.prefetcher 8223 # number of overall hits
2542system.l2c.overall_hits::total 180460 # number of overall hits
2543system.l2c.UpgradeReq_misses::cpu0.data 9513 # number of UpgradeReq misses
2544system.l2c.UpgradeReq_misses::cpu1.data 4300 # number of UpgradeReq misses
2545system.l2c.UpgradeReq_misses::total 13813 # number of UpgradeReq misses
2546system.l2c.SCUpgradeReq_misses::cpu0.data 964 # number of SCUpgradeReq misses
2547system.l2c.SCUpgradeReq_misses::cpu1.data 1203 # number of SCUpgradeReq misses
2548system.l2c.SCUpgradeReq_misses::total 2167 # number of SCUpgradeReq misses
2549system.l2c.ReadExReq_misses::cpu0.data 11039 # number of ReadExReq misses
2550system.l2c.ReadExReq_misses::cpu1.data 8960 # number of ReadExReq misses
2551system.l2c.ReadExReq_misses::total 19999 # number of ReadExReq misses
2552system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 128 # number of ReadSharedReq misses
2553system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses
2554system.l2c.ReadSharedReq_misses::cpu0.inst 20082 # number of ReadSharedReq misses
2555system.l2c.ReadSharedReq_misses::cpu0.data 8636 # number of ReadSharedReq misses
2556system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130145 # number of ReadSharedReq misses
2557system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 30 # number of ReadSharedReq misses
2558system.l2c.ReadSharedReq_misses::cpu1.inst 5762 # number of ReadSharedReq misses
2559system.l2c.ReadSharedReq_misses::cpu1.data 2791 # number of ReadSharedReq misses
2560system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 9488 # number of ReadSharedReq misses
2561system.l2c.ReadSharedReq_misses::total 177063 # number of ReadSharedReq misses
2562system.l2c.demand_misses::cpu0.dtb.walker 128 # number of demand (read+write) misses
2563system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
2564system.l2c.demand_misses::cpu0.inst 20082 # number of demand (read+write) misses
2565system.l2c.demand_misses::cpu0.data 19675 # number of demand (read+write) misses
2566system.l2c.demand_misses::cpu0.l2cache.prefetcher 130145 # number of demand (read+write) misses
2567system.l2c.demand_misses::cpu1.dtb.walker 30 # number of demand (read+write) misses
2568system.l2c.demand_misses::cpu1.inst 5762 # number of demand (read+write) misses
2569system.l2c.demand_misses::cpu1.data 11751 # number of demand (read+write) misses
2570system.l2c.demand_misses::cpu1.l2cache.prefetcher 9488 # number of demand (read+write) misses
2571system.l2c.demand_misses::total 197062 # number of demand (read+write) misses
2572system.l2c.overall_misses::cpu0.dtb.walker 128 # number of overall misses
2573system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
2574system.l2c.overall_misses::cpu0.inst 20082 # number of overall misses
2575system.l2c.overall_misses::cpu0.data 19675 # number of overall misses
2576system.l2c.overall_misses::cpu0.l2cache.prefetcher 130145 # number of overall misses
2577system.l2c.overall_misses::cpu1.dtb.walker 30 # number of overall misses
2578system.l2c.overall_misses::cpu1.inst 5762 # number of overall misses
2579system.l2c.overall_misses::cpu1.data 11751 # number of overall misses
2580system.l2c.overall_misses::cpu1.l2cache.prefetcher 9488 # number of overall misses
2581system.l2c.overall_misses::total 197062 # number of overall misses
2582system.l2c.UpgradeReq_miss_latency::cpu0.data 11061000 # number of UpgradeReq miss cycles
2583system.l2c.UpgradeReq_miss_latency::cpu1.data 7336000 # number of UpgradeReq miss cycles
2584system.l2c.UpgradeReq_miss_latency::total 18397000 # number of UpgradeReq miss cycles
2585system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1913000 # number of SCUpgradeReq miss cycles
2586system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1241000 # number of SCUpgradeReq miss cycles
2587system.l2c.SCUpgradeReq_miss_latency::total 3154000 # number of SCUpgradeReq miss cycles
2588system.l2c.ReadExReq_miss_latency::cpu0.data 1093563000 # number of ReadExReq miss cycles
2589system.l2c.ReadExReq_miss_latency::cpu1.data 738422000 # number of ReadExReq miss cycles
2590system.l2c.ReadExReq_miss_latency::total 1831985000 # number of ReadExReq miss cycles
2591system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 11632000 # number of ReadSharedReq miss cycles
2592system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 84000 # number of ReadSharedReq miss cycles
2593system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1625007000 # number of ReadSharedReq miss cycles
2594system.l2c.ReadSharedReq_miss_latency::cpu0.data 768151000 # number of ReadSharedReq miss cycles
2595system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13218838629 # number of ReadSharedReq miss cycles
2596system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3061500 # number of ReadSharedReq miss cycles
2597system.l2c.ReadSharedReq_miss_latency::cpu1.inst 480657500 # number of ReadSharedReq miss cycles
2598system.l2c.ReadSharedReq_miss_latency::cpu1.data 249182500 # number of ReadSharedReq miss cycles
2599system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1135921938 # number of ReadSharedReq miss cycles
2600system.l2c.ReadSharedReq_miss_latency::total 17492536067 # number of ReadSharedReq miss cycles
2601system.l2c.demand_miss_latency::cpu0.dtb.walker 11632000 # number of demand (read+write) miss cycles
2602system.l2c.demand_miss_latency::cpu0.itb.walker 84000 # number of demand (read+write) miss cycles
2603system.l2c.demand_miss_latency::cpu0.inst 1625007000 # number of demand (read+write) miss cycles
2604system.l2c.demand_miss_latency::cpu0.data 1861714000 # number of demand (read+write) miss cycles
2605system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13218838629 # number of demand (read+write) miss cycles
2606system.l2c.demand_miss_latency::cpu1.dtb.walker 3061500 # number of demand (read+write) miss cycles
2607system.l2c.demand_miss_latency::cpu1.inst 480657500 # number of demand (read+write) miss cycles
2608system.l2c.demand_miss_latency::cpu1.data 987604500 # number of demand (read+write) miss cycles
2609system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1135921938 # number of demand (read+write) miss cycles
2610system.l2c.demand_miss_latency::total 19324521067 # number of demand (read+write) miss cycles
2611system.l2c.overall_miss_latency::cpu0.dtb.walker 11632000 # number of overall miss cycles
2612system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles
2613system.l2c.overall_miss_latency::cpu0.inst 1625007000 # number of overall miss cycles
2614system.l2c.overall_miss_latency::cpu0.data 1861714000 # number of overall miss cycles
2615system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13218838629 # number of overall miss cycles
2616system.l2c.overall_miss_latency::cpu1.dtb.walker 3061500 # number of overall miss cycles
2617system.l2c.overall_miss_latency::cpu1.inst 480657500 # number of overall miss cycles
2618system.l2c.overall_miss_latency::cpu1.data 987604500 # number of overall miss cycles
2619system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1135921938 # number of overall miss cycles
2620system.l2c.overall_miss_latency::total 19324521067 # number of overall miss cycles
2621system.l2c.WritebackDirty_accesses::writebacks 270033 # number of WritebackDirty accesses(hits+misses)
2622system.l2c.WritebackDirty_accesses::total 270033 # number of WritebackDirty accesses(hits+misses)
2623system.l2c.UpgradeReq_accesses::cpu0.data 42509 # number of UpgradeReq accesses(hits+misses)
2624system.l2c.UpgradeReq_accesses::cpu1.data 8157 # number of UpgradeReq accesses(hits+misses)
2625system.l2c.UpgradeReq_accesses::total 50666 # number of UpgradeReq accesses(hits+misses)
2626system.l2c.SCUpgradeReq_accesses::cpu0.data 2968 # number of SCUpgradeReq accesses(hits+misses)
2627system.l2c.SCUpgradeReq_accesses::cpu1.data 2243 # number of SCUpgradeReq accesses(hits+misses)
2628system.l2c.SCUpgradeReq_accesses::total 5211 # number of SCUpgradeReq accesses(hits+misses)
2629system.l2c.ReadExReq_accesses::cpu0.data 14980 # number of ReadExReq accesses(hits+misses)
2630system.l2c.ReadExReq_accesses::cpu1.data 10896 # number of ReadExReq accesses(hits+misses)
2631system.l2c.ReadExReq_accesses::total 25876 # number of ReadExReq accesses(hits+misses)
2632system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 485 # number of ReadSharedReq accesses(hits+misses)
2633system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 68 # number of ReadSharedReq accesses(hits+misses)
2634system.l2c.ReadSharedReq_accesses::cpu0.inst 60329 # number of ReadSharedReq accesses(hits+misses)
2635system.l2c.ReadSharedReq_accesses::cpu0.data 56024 # number of ReadSharedReq accesses(hits+misses)
2636system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 175016 # number of ReadSharedReq accesses(hits+misses)
2637system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 209 # number of ReadSharedReq accesses(hits+misses)
2638system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 29 # number of ReadSharedReq accesses(hits+misses)
2639system.l2c.ReadSharedReq_accesses::cpu1.inst 26625 # number of ReadSharedReq accesses(hits+misses)
2640system.l2c.ReadSharedReq_accesses::cpu1.data 15150 # number of ReadSharedReq accesses(hits+misses)
2641system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 17711 # number of ReadSharedReq accesses(hits+misses)
2642system.l2c.ReadSharedReq_accesses::total 351646 # number of ReadSharedReq accesses(hits+misses)
2643system.l2c.demand_accesses::cpu0.dtb.walker 485 # number of demand (read+write) accesses
2644system.l2c.demand_accesses::cpu0.itb.walker 68 # number of demand (read+write) accesses
2645system.l2c.demand_accesses::cpu0.inst 60329 # number of demand (read+write) accesses
2646system.l2c.demand_accesses::cpu0.data 71004 # number of demand (read+write) accesses
2647system.l2c.demand_accesses::cpu0.l2cache.prefetcher 175016 # number of demand (read+write) accesses
2648system.l2c.demand_accesses::cpu1.dtb.walker 209 # number of demand (read+write) accesses
2649system.l2c.demand_accesses::cpu1.itb.walker 29 # number of demand (read+write) accesses
2650system.l2c.demand_accesses::cpu1.inst 26625 # number of demand (read+write) accesses
2651system.l2c.demand_accesses::cpu1.data 26046 # number of demand (read+write) accesses
2652system.l2c.demand_accesses::cpu1.l2cache.prefetcher 17711 # number of demand (read+write) accesses
2653system.l2c.demand_accesses::total 377522 # number of demand (read+write) accesses
2654system.l2c.overall_accesses::cpu0.dtb.walker 485 # number of overall (read+write) accesses
2655system.l2c.overall_accesses::cpu0.itb.walker 68 # number of overall (read+write) accesses
2656system.l2c.overall_accesses::cpu0.inst 60329 # number of overall (read+write) accesses
2657system.l2c.overall_accesses::cpu0.data 71004 # number of overall (read+write) accesses
2658system.l2c.overall_accesses::cpu0.l2cache.prefetcher 175016 # number of overall (read+write) accesses
2659system.l2c.overall_accesses::cpu1.dtb.walker 209 # number of overall (read+write) accesses
2660system.l2c.overall_accesses::cpu1.itb.walker 29 # number of overall (read+write) accesses
2661system.l2c.overall_accesses::cpu1.inst 26625 # number of overall (read+write) accesses
2662system.l2c.overall_accesses::cpu1.data 26046 # number of overall (read+write) accesses
2663system.l2c.overall_accesses::cpu1.l2cache.prefetcher 17711 # number of overall (read+write) accesses
2664system.l2c.overall_accesses::total 377522 # number of overall (read+write) accesses
2665system.l2c.UpgradeReq_miss_rate::cpu0.data 0.223788 # miss rate for UpgradeReq accesses
2666system.l2c.UpgradeReq_miss_rate::cpu1.data 0.527155 # miss rate for UpgradeReq accesses
2667system.l2c.UpgradeReq_miss_rate::total 0.272629 # miss rate for UpgradeReq accesses
2668system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.324798 # miss rate for SCUpgradeReq accesses
2669system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.536335 # miss rate for SCUpgradeReq accesses
2670system.l2c.SCUpgradeReq_miss_rate::total 0.415851 # miss rate for SCUpgradeReq accesses
2671system.l2c.ReadExReq_miss_rate::cpu0.data 0.736916 # miss rate for ReadExReq accesses
2672system.l2c.ReadExReq_miss_rate::cpu1.data 0.822320 # miss rate for ReadExReq accesses
2673system.l2c.ReadExReq_miss_rate::total 0.772878 # miss rate for ReadExReq accesses
2674system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.263918 # miss rate for ReadSharedReq accesses
2675system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.014706 # miss rate for ReadSharedReq accesses
2676system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.332875 # miss rate for ReadSharedReq accesses
2677system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.154148 # miss rate for ReadSharedReq accesses
2678system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743618 # miss rate for ReadSharedReq accesses
2679system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.143541 # miss rate for ReadSharedReq accesses
2680system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.216413 # miss rate for ReadSharedReq accesses
2681system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.184224 # miss rate for ReadSharedReq accesses
2682system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.535712 # miss rate for ReadSharedReq accesses
2683system.l2c.ReadSharedReq_miss_rate::total 0.503526 # miss rate for ReadSharedReq accesses
2684system.l2c.demand_miss_rate::cpu0.dtb.walker 0.263918 # miss rate for demand accesses
2685system.l2c.demand_miss_rate::cpu0.itb.walker 0.014706 # miss rate for demand accesses
2686system.l2c.demand_miss_rate::cpu0.inst 0.332875 # miss rate for demand accesses
2687system.l2c.demand_miss_rate::cpu0.data 0.277097 # miss rate for demand accesses
2688system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.743618 # miss rate for demand accesses
2689system.l2c.demand_miss_rate::cpu1.dtb.walker 0.143541 # miss rate for demand accesses
2690system.l2c.demand_miss_rate::cpu1.inst 0.216413 # miss rate for demand accesses
2691system.l2c.demand_miss_rate::cpu1.data 0.451163 # miss rate for demand accesses
2692system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.535712 # miss rate for demand accesses
2693system.l2c.demand_miss_rate::total 0.521988 # miss rate for demand accesses
2694system.l2c.overall_miss_rate::cpu0.dtb.walker 0.263918 # miss rate for overall accesses
2695system.l2c.overall_miss_rate::cpu0.itb.walker 0.014706 # miss rate for overall accesses
2696system.l2c.overall_miss_rate::cpu0.inst 0.332875 # miss rate for overall accesses
2697system.l2c.overall_miss_rate::cpu0.data 0.277097 # miss rate for overall accesses
2698system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743618 # miss rate for overall accesses
2699system.l2c.overall_miss_rate::cpu1.dtb.walker 0.143541 # miss rate for overall accesses
2700system.l2c.overall_miss_rate::cpu1.inst 0.216413 # miss rate for overall accesses
2701system.l2c.overall_miss_rate::cpu1.data 0.451163 # miss rate for overall accesses
2702system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.535712 # miss rate for overall accesses
2703system.l2c.overall_miss_rate::total 0.521988 # miss rate for overall accesses
2704system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1162.724693 # average UpgradeReq miss latency
2705system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1706.046512 # average UpgradeReq miss latency
2706system.l2c.UpgradeReq_avg_miss_latency::total 1331.861290 # average UpgradeReq miss latency
2707system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1984.439834 # average SCUpgradeReq miss latency
2708system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1031.587697 # average SCUpgradeReq miss latency
2709system.l2c.SCUpgradeReq_avg_miss_latency::total 1455.468389 # average SCUpgradeReq miss latency
2710system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99063.592717 # average ReadExReq miss latency
2711system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82413.169643 # average ReadExReq miss latency
2712system.l2c.ReadExReq_avg_miss_latency::total 91603.830192 # average ReadExReq miss latency
2713system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90875 # average ReadSharedReq miss latency
2714system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 84000 # average ReadSharedReq miss latency
2715system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80918.583806 # average ReadSharedReq miss latency
2716system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88947.545160 # average ReadSharedReq miss latency
2717system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101570.084360 # average ReadSharedReq miss latency
2718system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 102050 # average ReadSharedReq miss latency
2719system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83418.517876 # average ReadSharedReq miss latency
2720system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89280.723755 # average ReadSharedReq miss latency
2721system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119721.958052 # average ReadSharedReq miss latency
2722system.l2c.ReadSharedReq_avg_miss_latency::total 98792.723872 # average ReadSharedReq miss latency
2723system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90875 # average overall miss latency
2724system.l2c.demand_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency
2725system.l2c.demand_avg_miss_latency::cpu0.inst 80918.583806 # average overall miss latency
2726system.l2c.demand_avg_miss_latency::cpu0.data 94623.329098 # average overall miss latency
2727system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101570.084360 # average overall miss latency
2728system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 102050 # average overall miss latency
2729system.l2c.demand_avg_miss_latency::cpu1.inst 83418.517876 # average overall miss latency
2730system.l2c.demand_avg_miss_latency::cpu1.data 84044.294103 # average overall miss latency
2731system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119721.958052 # average overall miss latency
2732system.l2c.demand_avg_miss_latency::total 98063.153053 # average overall miss latency
2733system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90875 # average overall miss latency
2734system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency
2735system.l2c.overall_avg_miss_latency::cpu0.inst 80918.583806 # average overall miss latency
2736system.l2c.overall_avg_miss_latency::cpu0.data 94623.329098 # average overall miss latency
2737system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101570.084360 # average overall miss latency
2738system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 102050 # average overall miss latency
2739system.l2c.overall_avg_miss_latency::cpu1.inst 83418.517876 # average overall miss latency
2740system.l2c.overall_avg_miss_latency::cpu1.data 84044.294103 # average overall miss latency
2741system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119721.958052 # average overall miss latency
2742system.l2c.overall_avg_miss_latency::total 98063.153053 # average overall miss latency
2743system.l2c.blocked_cycles::no_mshrs 49 # number of cycles access was blocked
2744system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2745system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked
2746system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2747system.l2c.avg_blocked_cycles::no_mshrs 24.500000 # average number of cycles each access was blocked
2748system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2749system.l2c.writebacks::writebacks 105051 # number of writebacks
2750system.l2c.writebacks::total 105051 # number of writebacks
2751system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 2 # number of ReadSharedReq MSHR hits
2752system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits
2753system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
2754system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
2755system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
2756system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits
2757system.l2c.CleanEvict_mshr_misses::writebacks 4156 # number of CleanEvict MSHR misses
2758system.l2c.CleanEvict_mshr_misses::total 4156 # number of CleanEvict MSHR misses
2759system.l2c.UpgradeReq_mshr_misses::cpu0.data 9513 # number of UpgradeReq MSHR misses
2760system.l2c.UpgradeReq_mshr_misses::cpu1.data 4300 # number of UpgradeReq MSHR misses
2761system.l2c.UpgradeReq_mshr_misses::total 13813 # number of UpgradeReq MSHR misses
2762system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 964 # number of SCUpgradeReq MSHR misses
2763system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1203 # number of SCUpgradeReq MSHR misses
2764system.l2c.SCUpgradeReq_mshr_misses::total 2167 # number of SCUpgradeReq MSHR misses
2765system.l2c.ReadExReq_mshr_misses::cpu0.data 11039 # number of ReadExReq MSHR misses
2766system.l2c.ReadExReq_mshr_misses::cpu1.data 8960 # number of ReadExReq MSHR misses
2767system.l2c.ReadExReq_mshr_misses::total 19999 # number of ReadExReq MSHR misses
2768system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 128 # number of ReadSharedReq MSHR misses
2769system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses
2770system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 20082 # number of ReadSharedReq MSHR misses
2771system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8636 # number of ReadSharedReq MSHR misses
2772system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130145 # number of ReadSharedReq MSHR misses
2773system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 30 # number of ReadSharedReq MSHR misses
2774system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 5760 # number of ReadSharedReq MSHR misses
2775system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2791 # number of ReadSharedReq MSHR misses
2776system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 9488 # number of ReadSharedReq MSHR misses
2777system.l2c.ReadSharedReq_mshr_misses::total 177061 # number of ReadSharedReq MSHR misses
2778system.l2c.demand_mshr_misses::cpu0.dtb.walker 128 # number of demand (read+write) MSHR misses
2779system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
2780system.l2c.demand_mshr_misses::cpu0.inst 20082 # number of demand (read+write) MSHR misses
2781system.l2c.demand_mshr_misses::cpu0.data 19675 # number of demand (read+write) MSHR misses
2782system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130145 # number of demand (read+write) MSHR misses
2783system.l2c.demand_mshr_misses::cpu1.dtb.walker 30 # number of demand (read+write) MSHR misses
2784system.l2c.demand_mshr_misses::cpu1.inst 5760 # number of demand (read+write) MSHR misses
2785system.l2c.demand_mshr_misses::cpu1.data 11751 # number of demand (read+write) MSHR misses
2786system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9488 # number of demand (read+write) MSHR misses
2787system.l2c.demand_mshr_misses::total 197060 # number of demand (read+write) MSHR misses
2788system.l2c.overall_mshr_misses::cpu0.dtb.walker 128 # number of overall MSHR misses
2789system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
2790system.l2c.overall_mshr_misses::cpu0.inst 20082 # number of overall MSHR misses
2791system.l2c.overall_mshr_misses::cpu0.data 19675 # number of overall MSHR misses
2792system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130145 # number of overall MSHR misses
2793system.l2c.overall_mshr_misses::cpu1.dtb.walker 30 # number of overall MSHR misses
2794system.l2c.overall_mshr_misses::cpu1.inst 5760 # number of overall MSHR misses
2795system.l2c.overall_mshr_misses::cpu1.data 11751 # number of overall MSHR misses
2796system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9488 # number of overall MSHR misses
2797system.l2c.overall_mshr_misses::total 197060 # number of overall MSHR misses
2798system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3448 # number of ReadReq MSHR uncacheable
2799system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29629 # number of ReadReq MSHR uncacheable
2800system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable
2801system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5396 # number of ReadReq MSHR uncacheable
2802system.l2c.ReadReq_mshr_uncacheable::total 38585 # number of ReadReq MSHR uncacheable
2803system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26357 # number of WriteReq MSHR uncacheable
2804system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4698 # number of WriteReq MSHR uncacheable
2805system.l2c.WriteReq_mshr_uncacheable::total 31055 # number of WriteReq MSHR uncacheable
2806system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3448 # number of overall MSHR uncacheable misses
2807system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55986 # number of overall MSHR uncacheable misses
2808system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses
2809system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10094 # number of overall MSHR uncacheable misses
2810system.l2c.overall_mshr_uncacheable_misses::total 69640 # number of overall MSHR uncacheable misses
2811system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 226847000 # number of UpgradeReq MSHR miss cycles
2812system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 101654500 # number of UpgradeReq MSHR miss cycles
2813system.l2c.UpgradeReq_mshr_miss_latency::total 328501500 # number of UpgradeReq MSHR miss cycles
2814system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 24479500 # number of SCUpgradeReq MSHR miss cycles
2815system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 30201499 # number of SCUpgradeReq MSHR miss cycles
2816system.l2c.SCUpgradeReq_mshr_miss_latency::total 54680999 # number of SCUpgradeReq MSHR miss cycles
2817system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 983173000 # number of ReadExReq MSHR miss cycles
2818system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 648820503 # number of ReadExReq MSHR miss cycles
2819system.l2c.ReadExReq_mshr_miss_latency::total 1631993503 # number of ReadExReq MSHR miss cycles
2820system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 10352000 # number of ReadSharedReq MSHR miss cycles
2821system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 74000 # number of ReadSharedReq MSHR miss cycles
2822system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1424184505 # number of ReadSharedReq MSHR miss cycles
2823system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 681791000 # number of ReadSharedReq MSHR miss cycles
2824system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11917387132 # number of ReadSharedReq MSHR miss cycles
2825system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 2761500 # number of ReadSharedReq MSHR miss cycles
2826system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 422975502 # number of ReadSharedReq MSHR miss cycles
2827system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 221269506 # number of ReadSharedReq MSHR miss cycles
2828system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1041037947 # number of ReadSharedReq MSHR miss cycles
2829system.l2c.ReadSharedReq_mshr_miss_latency::total 15721833092 # number of ReadSharedReq MSHR miss cycles
2830system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10352000 # number of demand (read+write) MSHR miss cycles
2831system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 74000 # number of demand (read+write) MSHR miss cycles
2832system.l2c.demand_mshr_miss_latency::cpu0.inst 1424184505 # number of demand (read+write) MSHR miss cycles
2833system.l2c.demand_mshr_miss_latency::cpu0.data 1664964000 # number of demand (read+write) MSHR miss cycles
2834system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11917387132 # number of demand (read+write) MSHR miss cycles
2835system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2761500 # number of demand (read+write) MSHR miss cycles
2836system.l2c.demand_mshr_miss_latency::cpu1.inst 422975502 # number of demand (read+write) MSHR miss cycles
2837system.l2c.demand_mshr_miss_latency::cpu1.data 870090009 # number of demand (read+write) MSHR miss cycles
2838system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1041037947 # number of demand (read+write) MSHR miss cycles
2839system.l2c.demand_mshr_miss_latency::total 17353826595 # number of demand (read+write) MSHR miss cycles
2840system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10352000 # number of overall MSHR miss cycles
2841system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles
2842system.l2c.overall_mshr_miss_latency::cpu0.inst 1424184505 # number of overall MSHR miss cycles
2843system.l2c.overall_mshr_miss_latency::cpu0.data 1664964000 # number of overall MSHR miss cycles
2844system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11917387132 # number of overall MSHR miss cycles
2845system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2761500 # number of overall MSHR miss cycles
2846system.l2c.overall_mshr_miss_latency::cpu1.inst 422975502 # number of overall MSHR miss cycles
2847system.l2c.overall_mshr_miss_latency::cpu1.data 870090009 # number of overall MSHR miss cycles
2848system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1041037947 # number of overall MSHR miss cycles
2849system.l2c.overall_mshr_miss_latency::total 17353826595 # number of overall MSHR miss cycles
2850system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 219420500 # number of ReadReq MSHR uncacheable cycles
2851system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5330978502 # number of ReadReq MSHR uncacheable cycles
2852system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7456000 # number of ReadReq MSHR uncacheable cycles
2853system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 854539500 # number of ReadReq MSHR uncacheable cycles
2854system.l2c.ReadReq_mshr_uncacheable_latency::total 6412394502 # number of ReadReq MSHR uncacheable cycles
2855system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 219420500 # number of overall MSHR uncacheable cycles
2856system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5330978502 # number of overall MSHR uncacheable cycles
2857system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7456000 # number of overall MSHR uncacheable cycles
2858system.l2c.overall_mshr_uncacheable_latency::cpu1.data 854539500 # number of overall MSHR uncacheable cycles
2859system.l2c.overall_mshr_uncacheable_latency::total 6412394502 # number of overall MSHR uncacheable cycles
2860system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2861system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2862system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.223788 # mshr miss rate for UpgradeReq accesses
2863system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.527155 # mshr miss rate for UpgradeReq accesses
2864system.l2c.UpgradeReq_mshr_miss_rate::total 0.272629 # mshr miss rate for UpgradeReq accesses
2865system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.324798 # mshr miss rate for SCUpgradeReq accesses
2866system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.536335 # mshr miss rate for SCUpgradeReq accesses
2867system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.415851 # mshr miss rate for SCUpgradeReq accesses
2868system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736916 # mshr miss rate for ReadExReq accesses
2869system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.822320 # mshr miss rate for ReadExReq accesses
2870system.l2c.ReadExReq_mshr_miss_rate::total 0.772878 # mshr miss rate for ReadExReq accesses
2871system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.263918 # mshr miss rate for ReadSharedReq accesses
2872system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.014706 # mshr miss rate for ReadSharedReq accesses
2873system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.332875 # mshr miss rate for ReadSharedReq accesses
2874system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.154148 # mshr miss rate for ReadSharedReq accesses
2875system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743618 # mshr miss rate for ReadSharedReq accesses
2876system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.143541 # mshr miss rate for ReadSharedReq accesses
2877system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.216338 # mshr miss rate for ReadSharedReq accesses
2878system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.184224 # mshr miss rate for ReadSharedReq accesses
2879system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.535712 # mshr miss rate for ReadSharedReq accesses
2880system.l2c.ReadSharedReq_mshr_miss_rate::total 0.503521 # mshr miss rate for ReadSharedReq accesses
2881system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.263918 # mshr miss rate for demand accesses
2882system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014706 # mshr miss rate for demand accesses
2883system.l2c.demand_mshr_miss_rate::cpu0.inst 0.332875 # mshr miss rate for demand accesses
2884system.l2c.demand_mshr_miss_rate::cpu0.data 0.277097 # mshr miss rate for demand accesses
2885system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743618 # mshr miss rate for demand accesses
2886system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.143541 # mshr miss rate for demand accesses
2887system.l2c.demand_mshr_miss_rate::cpu1.inst 0.216338 # mshr miss rate for demand accesses
2888system.l2c.demand_mshr_miss_rate::cpu1.data 0.451163 # mshr miss rate for demand accesses
2889system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.535712 # mshr miss rate for demand accesses
2890system.l2c.demand_mshr_miss_rate::total 0.521983 # mshr miss rate for demand accesses
2891system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.263918 # mshr miss rate for overall accesses
2892system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014706 # mshr miss rate for overall accesses
2893system.l2c.overall_mshr_miss_rate::cpu0.inst 0.332875 # mshr miss rate for overall accesses
2894system.l2c.overall_mshr_miss_rate::cpu0.data 0.277097 # mshr miss rate for overall accesses
2895system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743618 # mshr miss rate for overall accesses
2896system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.143541 # mshr miss rate for overall accesses
2897system.l2c.overall_mshr_miss_rate::cpu1.inst 0.216338 # mshr miss rate for overall accesses
2898system.l2c.overall_mshr_miss_rate::cpu1.data 0.451163 # mshr miss rate for overall accesses
2899system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.535712 # mshr miss rate for overall accesses
2900system.l2c.overall_mshr_miss_rate::total 0.521983 # mshr miss rate for overall accesses
2901system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23846.000210 # average UpgradeReq mshr miss latency
2902system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23640.581395 # average UpgradeReq mshr miss latency
2903system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23782.053138 # average UpgradeReq mshr miss latency
2904system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25393.672199 # average SCUpgradeReq mshr miss latency
2905system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 25105.152951 # average SCUpgradeReq mshr miss latency
2906system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25233.502077 # average SCUpgradeReq mshr miss latency
2907system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89063.592717 # average ReadExReq mshr miss latency
2908system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72413.002567 # average ReadExReq mshr miss latency
2909system.l2c.ReadExReq_avg_mshr_miss_latency::total 81603.755338 # average ReadExReq mshr miss latency
2910system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80875 # average ReadSharedReq mshr miss latency
2911system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadSharedReq mshr miss latency
2912system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average ReadSharedReq mshr miss latency
2913system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78947.545160 # average ReadSharedReq mshr miss latency
2914system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average ReadSharedReq mshr miss latency
2915system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average ReadSharedReq mshr miss latency
2916system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average ReadSharedReq mshr miss latency
2917system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79279.651021 # average ReadSharedReq mshr miss latency
2918system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average ReadSharedReq mshr miss latency
2919system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88793.314688 # average ReadSharedReq mshr miss latency
2920system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80875 # average overall mshr miss latency
2921system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency
2922system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average overall mshr miss latency
2923system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84623.329098 # average overall mshr miss latency
2924system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average overall mshr miss latency
2925system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average overall mshr miss latency
2926system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average overall mshr miss latency
2927system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74043.911922 # average overall mshr miss latency
2928system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average overall mshr miss latency
2929system.l2c.demand_avg_mshr_miss_latency::total 88063.668908 # average overall mshr miss latency
2930system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80875 # average overall mshr miss latency
2931system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency
2932system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average overall mshr miss latency
2933system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84623.329098 # average overall mshr miss latency
2934system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average overall mshr miss latency
2935system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average overall mshr miss latency
2936system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average overall mshr miss latency
2937system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74043.911922 # average overall mshr miss latency
2938system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average overall mshr miss latency
2939system.l2c.overall_avg_mshr_miss_latency::total 88063.668908 # average overall mshr miss latency
2940system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average ReadReq mshr uncacheable latency
2941system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179924.347835 # average ReadReq mshr uncacheable latency
2942system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average ReadReq mshr uncacheable latency
2943system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158365.363232 # average ReadReq mshr uncacheable latency
2944system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166188.791033 # average ReadReq mshr uncacheable latency
2945system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average overall mshr uncacheable latency
2946system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 95219.849641 # average overall mshr uncacheable latency
2947system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average overall mshr uncacheable latency
2948system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84658.163265 # average overall mshr uncacheable latency
2949system.l2c.overall_avg_mshr_uncacheable_latency::total 92079.185841 # average overall mshr uncacheable latency
2950system.membus.snoop_filter.tot_requests 535318 # Total number of requests made to the snoop filter.
2951system.membus.snoop_filter.hit_single_requests 308111 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2952system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2953system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2954system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2955system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2956system.membus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
2957system.membus.trans_dist::ReadReq 38585 # Transaction distribution
2958system.membus.trans_dist::ReadResp 215902 # Transaction distribution
2959system.membus.trans_dist::WriteReq 31055 # Transaction distribution
2960system.membus.trans_dist::WriteResp 31055 # Transaction distribution
2961system.membus.trans_dist::WritebackDirty 141257 # Transaction distribution
2962system.membus.trans_dist::CleanEvict 18818 # Transaction distribution
2963system.membus.trans_dist::UpgradeReq 79128 # Transaction distribution
2964system.membus.trans_dist::SCUpgradeReq 41795 # Transaction distribution
2965system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2966system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
2967system.membus.trans_dist::ReadExReq 40708 # Transaction distribution
2968system.membus.trans_dist::ReadExResp 19870 # Transaction distribution
2969system.membus.trans_dist::ReadSharedReq 177317 # Transaction distribution
2970system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2971system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
2972system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
2973system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14304 # Packet count per connected master and slave (bytes)
2974system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 675920 # Packet count per connected master and slave (bytes)
2975system.membus.pkt_count_system.l2c.mem_side::total 798178 # Packet count per connected master and slave (bytes)
2976system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes)
2977system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes)
2978system.membus.pkt_count::total 871135 # Packet count per connected master and slave (bytes)
2979system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
2980system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes)
2981system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28608 # Cumulative packet size per connected master and slave (bytes)
2982system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19551584 # Cumulative packet size per connected master and slave (bytes)
2983system.membus.pkt_size_system.l2c.mem_side::total 19744330 # Cumulative packet size per connected master and slave (bytes)
2984system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
2985system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
2986system.membus.pkt_size::total 22062474 # Cumulative packet size per connected master and slave (bytes)
2987system.membus.snoops 126237 # Total snoops (count)
2988system.membus.snoopTraffic 37184 # Total snoop traffic (bytes)
2989system.membus.snoop_fanout::samples 444815 # Request fanout histogram
2990system.membus.snoop_fanout::mean 0.011558 # Request fanout histogram
2991system.membus.snoop_fanout::stdev 0.106883 # Request fanout histogram
2992system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2993system.membus.snoop_fanout::0 439674 98.84% 98.84% # Request fanout histogram
2994system.membus.snoop_fanout::1 5141 1.16% 100.00% # Request fanout histogram
2995system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2996system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2997system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2998system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2999system.membus.snoop_fanout::total 444815 # Request fanout histogram
3000system.membus.reqLayer0.occupancy 94951000 # Layer occupancy (ticks)
3001system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3002system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks)
3003system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3004system.membus.reqLayer2.occupancy 12539499 # Layer occupancy (ticks)
3005system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3006system.membus.reqLayer5.occupancy 1031011447 # Layer occupancy (ticks)
3007system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3008system.membus.respLayer2.occupancy 1149570495 # Layer occupancy (ticks)
3009system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3010system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks)
3011system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3012system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3013system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3014system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3015system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3016system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3017system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3018system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3019system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3020system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3021system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3022system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3023system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3024system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3025system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3026system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3027system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3028system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3029system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3030system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3031system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3032system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
3033system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
3034system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

3050system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
3051system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3052system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3053system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
3054system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3055system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
3056system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
3057system.realview.ethernet.droppedPackets 0 # number of packets dropped
3058system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3059system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3060system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3061system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3062system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3063system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3064system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3065system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3066system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3067system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3068system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3069system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3070system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3071system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3072system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3073system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3074system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3075system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3076system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3077system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3078system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3079system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3080system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3081system.toL2Bus.snoop_filter.tot_requests 1073312 # Total number of requests made to the snoop filter.
3082system.toL2Bus.snoop_filter.hit_single_requests 580718 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3083system.toL2Bus.snoop_filter.hit_multi_requests 172518 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3084system.toL2Bus.snoop_filter.tot_snoops 20634 # Total number of snoops made to the snoop filter.
3085system.toL2Bus.snoop_filter.hit_single_snoops 19568 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3086system.toL2Bus.snoop_filter.hit_multi_snoops 1066 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3087system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states
3088system.toL2Bus.trans_dist::ReadReq 38588 # Transaction distribution
3089system.toL2Bus.trans_dist::ReadResp 515387 # Transaction distribution
3090system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
3091system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution
3092system.toL2Bus.trans_dist::WritebackDirty 375084 # Transaction distribution
3093system.toL2Bus.trans_dist::CleanEvict 144219 # Transaction distribution
3094system.toL2Bus.trans_dist::UpgradeReq 115852 # Transaction distribution
3095system.toL2Bus.trans_dist::SCUpgradeReq 44839 # Transaction distribution
3096system.toL2Bus.trans_dist::UpgradeResp 160691 # Transaction distribution
3097system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
3098system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
3099system.toL2Bus.trans_dist::ReadExReq 51833 # Transaction distribution
3100system.toL2Bus.trans_dist::ReadExResp 51833 # Transaction distribution
3101system.toL2Bus.trans_dist::ReadSharedReq 476801 # Transaction distribution
3102system.toL2Bus.trans_dist::InvalidateReq 4556 # Transaction distribution
3103system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1253209 # Packet count per connected master and slave (bytes)
3104system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 392983 # Packet count per connected master and slave (bytes)
3105system.toL2Bus.pkt_count::total 1646192 # Packet count per connected master and slave (bytes)
3106system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34630659 # Cumulative packet size per connected master and slave (bytes)
3107system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7267527 # Cumulative packet size per connected master and slave (bytes)
3108system.toL2Bus.pkt_size::total 41898186 # Cumulative packet size per connected master and slave (bytes)
3109system.toL2Bus.snoops 395888 # Total snoops (count)
3110system.toL2Bus.snoopTraffic 16395788 # Total snoop traffic (bytes)
3111system.toL2Bus.snoop_fanout::samples 898686 # Request fanout histogram
3112system.toL2Bus.snoop_fanout::mean 0.386698 # Request fanout histogram
3113system.toL2Bus.snoop_fanout::stdev 0.489423 # Request fanout histogram
3114system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3115system.toL2Bus.snoop_fanout::0 552232 61.45% 61.45% # Request fanout histogram
3116system.toL2Bus.snoop_fanout::1 345388 38.43% 99.88% # Request fanout histogram
3117system.toL2Bus.snoop_fanout::2 1066 0.12% 100.00% # Request fanout histogram
3118system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3119system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3120system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3121system.toL2Bus.snoop_fanout::total 898686 # Request fanout histogram
3122system.toL2Bus.reqLayer0.occupancy 930017339 # Layer occupancy (ticks)
3123system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3124system.toL2Bus.snoopLayer0.occupancy 361623 # Layer occupancy (ticks)
3125system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3126system.toL2Bus.respLayer0.occupancy 658710189 # Layer occupancy (ticks)
3127system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3128system.toL2Bus.respLayer1.occupancy 272587474 # Layer occupancy (ticks)
3129system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3130
3131---------- End Simulation Statistics ----------