1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.848878 # Number of seconds simulated
4sim_ticks 2848878048000 # Number of ticks simulated
5final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 194660 # Simulator instruction rate (inst/s)
8host_op_rate 235713 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4372273286 # Simulator tick rate (ticks/s)
10host_mem_usage 620428 # Number of bytes of host memory used
11host_seconds 651.58 # Real time elapsed on the host
12sim_insts 126836472 # Number of instructions simulated
13sim_ops 153585571 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1701632 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1345580 # Number of bytes read from this memory
--- 669 unchanged lines hidden (view full) ---
689system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15694.801060 # average overall miss latency
690system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060 # average overall miss latency
691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
696system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
697system.cpu0.dcache.fast_writes 0 # number of fast writes performed
698system.cpu0.dcache.cache_copies 0 # number of cache copies performed
699system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks
700system.cpu0.dcache.writebacks::total 757698 # number of writebacks
701system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits
702system.cpu0.dcache.ReadReq_mshr_hits::total 75572 # number of ReadReq MSHR hits
703system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266010 # number of WriteReq MSHR hits
704system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits
705system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14891 # number of LoadLockedReq MSHR hits
706system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
741system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 641500 # number of StoreCondFailReq MSHR miss cycles
742system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles
743system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12322191000 # number of demand (read+write) MSHR miss cycles
744system.cpu0.dcache.demand_mshr_miss_latency::total 12322191000 # number of demand (read+write) MSHR miss cycles
745system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000 # number of overall MSHR miss cycles
746system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles
747system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles
748system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles
749system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5444959500 # number of WriteReq MSHR uncacheable cycles
750system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5444959500 # number of WriteReq MSHR uncacheable cycles
751system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12147316500 # number of overall MSHR uncacheable cycles
752system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12147316500 # number of overall MSHR uncacheable cycles
753system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses
754system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
755system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses
756system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses
757system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses
758system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses
759system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses
760system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
777system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
778system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
779system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency
780system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816 # average overall mshr miss latency
781system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency
782system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency
783system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency
784system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency
785system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024 # average WriteReq mshr uncacheable latency
786system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024 # average WriteReq mshr uncacheable latency
787system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199903.177764 # average overall mshr uncacheable latency
788system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764 # average overall mshr uncacheable latency
789system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
790system.cpu0.icache.tags.replacements 2042425 # number of replacements
791system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use
792system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks.
793system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks.
794system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks.
795system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit.
796system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor
797system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
840system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency
841system.cpu0.icache.overall_avg_miss_latency::total 10073.051428 # average overall miss latency
842system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
843system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
844system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
845system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
846system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
847system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
848system.cpu0.icache.fast_writes 0 # number of fast writes performed
849system.cpu0.icache.cache_copies 0 # number of cache copies performed
850system.cpu0.icache.writebacks::writebacks 2042425 # number of writebacks
851system.cpu0.icache.writebacks::total 2042425 # number of writebacks
852system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2042958 # number of ReadReq MSHR misses
853system.cpu0.icache.ReadReq_mshr_misses::total 2042958 # number of ReadReq MSHR misses
854system.cpu0.icache.demand_mshr_misses::cpu0.inst 2042958 # number of demand (read+write) MSHR misses
855system.cpu0.icache.demand_mshr_misses::total 2042958 # number of demand (read+write) MSHR misses
856system.cpu0.icache.overall_mshr_misses::cpu0.inst 2042958 # number of overall MSHR misses
857system.cpu0.icache.overall_mshr_misses::total 2042958 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
880system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
881system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
882system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
883system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
884system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency
885system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency
886system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency
887system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency
888system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
889system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued
890system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified
891system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue
892system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
893system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
894system.cpu0.l2cache.prefetcher.pfSpanPage 244697 # number of prefetches not generated due to page crossing
895system.cpu0.l2cache.tags.replacements 304900 # number of replacements
896system.cpu0.l2cache.tags.tagsinuse 16120.127106 # Cycle average of tags in use
--- 178 unchanged lines hidden (view full) ---
1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45396.596297 # average overall miss latency
1076system.cpu0.l2cache.overall_avg_miss_latency::total 51526.739597 # average overall miss latency
1077system.cpu0.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked
1078system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1079system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1080system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1081system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1082system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1083system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1084system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1085system.cpu0.l2cache.unused_prefetches 10897 # number of HardPF blocks evicted w/o reference
1086system.cpu0.l2cache.writebacks::writebacks 237171 # number of writebacks
1087system.cpu0.l2cache.writebacks::total 237171 # number of writebacks
1088system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5426 # number of ReadExReq MSHR hits
1089system.cpu0.l2cache.ReadExReq_mshr_hits::total 5426 # number of ReadExReq MSHR hits
1090system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 72 # number of ReadCleanReq MSHR hits
1091system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 72 # number of ReadCleanReq MSHR hits
1092system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 591 # number of ReadSharedReq MSHR hits
--- 64 unchanged lines hidden (view full) ---
1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1833000 # number of overall MSHR miss cycles
1158system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4100378000 # number of overall MSHR miss cycles
1159system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5357247999 # number of overall MSHR miss cycles
1160system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21051299430 # number of overall MSHR miss cycles
1161system.cpu0.l2cache.overall_mshr_miss_latency::total 30542659429 # number of overall MSHR miss cycles
1162system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles
1163system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445890500 # number of ReadReq MSHR uncacheable cycles
1164system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971910500 # number of ReadReq MSHR uncacheable cycles
1165system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5229022000 # number of WriteReq MSHR uncacheable cycles
1166system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5229022000 # number of WriteReq MSHR uncacheable cycles
1167system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles
1168system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11674912500 # number of overall MSHR uncacheable cycles
1169system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12200932500 # number of overall MSHR uncacheable cycles
1170system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for ReadReq accesses
1171system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for ReadReq accesses
1172system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009054 # mshr miss rate for ReadReq accesses
1173system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1174system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1175system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1176system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1177system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 41 unchanged lines hidden (view full) ---
1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency
1223system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency
1224system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency
1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency
1226system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency
1227system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872 # average WriteReq mshr uncacheable latency
1228system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872 # average WriteReq mshr uncacheable latency
1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency
1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746 # average overall mshr uncacheable latency
1231system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124 # average overall mshr uncacheable latency
1232system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1233system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter.
1234system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1235system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1236system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter.
1237system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1238system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1239system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution
1240system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution
--- 376 unchanged lines hidden (view full) ---
1617system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23712.367863 # average overall miss latency
1618system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863 # average overall miss latency
1619system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1620system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1621system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1622system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1623system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1624system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1625system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1626system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1627system.cpu1.dcache.writebacks::writebacks 155125 # number of writebacks
1628system.cpu1.dcache.writebacks::total 155125 # number of writebacks
1629system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12753 # number of ReadReq MSHR hits
1630system.cpu1.dcache.ReadReq_mshr_hits::total 12753 # number of ReadReq MSHR hits
1631system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42136 # number of WriteReq MSHR hits
1632system.cpu1.dcache.WriteReq_mshr_hits::total 42136 # number of WriteReq MSHR hits
1633system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11686 # number of LoadLockedReq MSHR hits
1634system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11686 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
1669system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1094500 # number of StoreCondFailReq MSHR miss cycles
1670system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1094500 # number of StoreCondFailReq MSHR miss cycles
1671system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4556767000 # number of demand (read+write) MSHR miss cycles
1672system.cpu1.dcache.demand_mshr_miss_latency::total 4556767000 # number of demand (read+write) MSHR miss cycles
1673system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500 # number of overall MSHR miss cycles
1674system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles
1675system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles
1676system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles
1677system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251809500 # number of WriteReq MSHR uncacheable cycles
1678system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251809500 # number of WriteReq MSHR uncacheable cycles
1679system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641276500 # number of overall MSHR uncacheable cycles
1680system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641276500 # number of overall MSHR uncacheable cycles
1681system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses
1682system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses
1683system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses
1684system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses
1685system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses
1686system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses
1687system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses
1688system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
1705system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1706system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1707system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency
1708system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency
1709system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency
1710system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency
1711system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency
1712system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency
1713system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177 # average WriteReq mshr uncacheable latency
1714system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177 # average WriteReq mshr uncacheable latency
1715system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711 # average overall mshr uncacheable latency
1716system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711 # average overall mshr uncacheable latency
1717system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1718system.cpu1.icache.tags.replacements 856657 # number of replacements
1719system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use
1720system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks.
1721system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks.
1722system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks.
1723system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit.
1724system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor
1725system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
1768system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency
1769system.cpu1.icache.overall_avg_miss_latency::total 8854.776013 # average overall miss latency
1770system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1771system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1772system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1773system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1774system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1775system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1776system.cpu1.icache.fast_writes 0 # number of fast writes performed
1777system.cpu1.icache.cache_copies 0 # number of cache copies performed
1778system.cpu1.icache.writebacks::writebacks 856657 # number of writebacks
1779system.cpu1.icache.writebacks::total 856657 # number of writebacks
1780system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # number of ReadReq MSHR misses
1781system.cpu1.icache.ReadReq_mshr_misses::total 857169 # number of ReadReq MSHR misses
1782system.cpu1.icache.demand_mshr_misses::cpu1.inst 857169 # number of demand (read+write) MSHR misses
1783system.cpu1.icache.demand_mshr_misses::total 857169 # number of demand (read+write) MSHR misses
1784system.cpu1.icache.overall_mshr_misses::cpu1.inst 857169 # number of overall MSHR misses
1785system.cpu1.icache.overall_mshr_misses::total 857169 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
1808system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1809system.cpu1.icache.demand_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1810system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1811system.cpu1.icache.overall_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1812system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average ReadReq mshr uncacheable latency
1813system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency
1814system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency
1815system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency
1816system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1817system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued
1818system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified
1819system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue
1820system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1821system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1822system.cpu1.l2cache.prefetcher.pfSpanPage 49365 # number of prefetches not generated due to page crossing
1823system.cpu1.l2cache.tags.replacements 38167 # number of replacements
1824system.cpu1.l2cache.tags.tagsinuse 15174.819793 # Cycle average of tags in use
--- 180 unchanged lines hidden (view full) ---
2005system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33463.491285 # average overall miss latency
2006system.cpu1.l2cache.overall_avg_miss_latency::total 36114.627487 # average overall miss latency
2007system.cpu1.l2cache.blocked_cycles::no_mshrs 30 # number of cycles access was blocked
2008system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2009system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
2010system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2011system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
2012system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2013system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2014system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2015system.cpu1.l2cache.unused_prefetches 580 # number of HardPF blocks evicted w/o reference
2016system.cpu1.l2cache.writebacks::writebacks 29115 # number of writebacks
2017system.cpu1.l2cache.writebacks::total 29115 # number of writebacks
2018system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 240 # number of ReadExReq MSHR hits
2019system.cpu1.l2cache.ReadExReq_mshr_hits::total 240 # number of ReadExReq MSHR hits
2020system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
2021system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
2022system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 39 # number of ReadSharedReq MSHR hits
--- 66 unchanged lines hidden (view full) ---
2089system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3383500 # number of overall MSHR miss cycles
2090system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 662136000 # number of overall MSHR miss cycles
2091system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2693368996 # number of overall MSHR miss cycles
2092system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of overall MSHR miss cycles
2093system.cpu1.l2cache.overall_mshr_miss_latency::total 4332115741 # number of overall MSHR miss cycles
2094system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14575500 # number of ReadReq MSHR uncacheable cycles
2095system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365633500 # number of ReadReq MSHR uncacheable cycles
2096system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 380209000 # number of ReadReq MSHR uncacheable cycles
2097system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 234344500 # number of WriteReq MSHR uncacheable cycles
2098system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 234344500 # number of WriteReq MSHR uncacheable cycles
2099system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14575500 # number of overall MSHR uncacheable cycles
2100system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 599978000 # number of overall MSHR uncacheable cycles
2101system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614553500 # number of overall MSHR uncacheable cycles
2102system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses
2103system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for ReadReq accesses
2104system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032323 # mshr miss rate for ReadReq accesses
2105system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2106system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2107system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2108system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2109system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 43 unchanged lines hidden (view full) ---
2153system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
2154system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
2155system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
2156system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency
2157system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency
2158system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency
2159system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency
2160system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency
2161system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689 # average WriteReq mshr uncacheable latency
2162system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689 # average WriteReq mshr uncacheable latency
2163system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency
2164system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139 # average overall mshr uncacheable latency
2165system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087 # average overall mshr uncacheable latency
2166system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2167system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter.
2168system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2169system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2170system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter.
2171system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2172system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2173system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution
2174system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution
--- 154 unchanged lines hidden (view full) ---
2329system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2330system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2331system.iocache.tags.tag_accesses 328203 # Number of tag accesses
2332system.iocache.tags.data_accesses 328203 # Number of data accesses
2333system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
2334system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
2335system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2336system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2337system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
2338system.iocache.demand_misses::total 243 # number of demand (read+write) misses
2339system.iocache.overall_misses::realview.ide 243 # number of overall misses
2340system.iocache.overall_misses::total 243 # number of overall misses
2341system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles
2342system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles
2343system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles
2344system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles
2345system.iocache.demand_miss_latency::realview.ide 31660877 # number of demand (read+write) miss cycles
2346system.iocache.demand_miss_latency::total 31660877 # number of demand (read+write) miss cycles
2347system.iocache.overall_miss_latency::realview.ide 31660877 # number of overall miss cycles
2348system.iocache.overall_miss_latency::total 31660877 # number of overall miss cycles
2349system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
2350system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
2351system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2352system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2353system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
2354system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
2355system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
2356system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
2357system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2358system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2359system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2360system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2361system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2362system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2363system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2364system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2365system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency
2366system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency
2367system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency
2368system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency
2369system.iocache.demand_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
2370system.iocache.demand_avg_miss_latency::total 130291.674897 # average overall miss latency
2371system.iocache.overall_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
2372system.iocache.overall_avg_miss_latency::total 130291.674897 # average overall miss latency
2373system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2374system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2375system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2376system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2377system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2378system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2379system.iocache.fast_writes 0 # number of fast writes performed
2380system.iocache.cache_copies 0 # number of cache copies performed
2381system.iocache.writebacks::writebacks 36190 # number of writebacks
2382system.iocache.writebacks::total 36190 # number of writebacks
2383system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
2384system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
2385system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2386system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2387system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
2388system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
2389system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
2390system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
2391system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles
2392system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles
2393system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles
2394system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles
2395system.iocache.demand_mshr_miss_latency::realview.ide 19510877 # number of demand (read+write) MSHR miss cycles
2396system.iocache.demand_mshr_miss_latency::total 19510877 # number of demand (read+write) MSHR miss cycles
2397system.iocache.overall_mshr_miss_latency::realview.ide 19510877 # number of overall MSHR miss cycles
2398system.iocache.overall_mshr_miss_latency::total 19510877 # number of overall MSHR miss cycles
2399system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2400system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2401system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2402system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2403system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2404system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2405system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2406system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2407system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897 # average ReadReq mshr miss latency
2408system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency
2409system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency
2410system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency
2411system.iocache.demand_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
2412system.iocache.demand_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
2413system.iocache.overall_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
2414system.iocache.overall_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
2415system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2416system.l2c.tags.replacements 132278 # number of replacements
2417system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use
2418system.l2c.tags.total_refs 475189 # Total number of references to valid blocks.
2419system.l2c.tags.sampled_refs 196356 # Sample count of references to valid blocks.
2420system.l2c.tags.avg_refs 2.420038 # Average number of references to valid blocks.
2421system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2422system.l2c.tags.occ_blocks::writebacks 13432.084830 # Average occupied blocks per requestor
2423system.l2c.tags.occ_blocks::cpu0.dtb.walker 86.256901 # Average occupied blocks per requestor
--- 278 unchanged lines hidden (view full) ---
2702system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average overall miss latency
2703system.l2c.overall_avg_miss_latency::total 146696.352377 # average overall miss latency
2704system.l2c.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
2705system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2706system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2707system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2708system.l2c.avg_blocked_cycles::no_mshrs 45 # average number of cycles each access was blocked
2709system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2710system.l2c.fast_writes 0 # number of fast writes performed
2711system.l2c.cache_copies 0 # number of cache copies performed
2712system.l2c.writebacks::writebacks 102335 # number of writebacks
2713system.l2c.writebacks::total 102335 # number of writebacks
2714system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
2715system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits
2716system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
2717system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
2718system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
2719system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
--- 93 unchanged lines hidden (view full) ---
2813system.l2c.overall_mshr_miss_latency::cpu1.data 1203034025 # number of overall MSHR miss cycles
2814system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of overall MSHR miss cycles
2815system.l2c.overall_mshr_miss_latency::total 26857931717 # number of overall MSHR miss cycles
2816system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443763000 # number of ReadReq MSHR uncacheable cycles
2817system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5869096507 # number of ReadReq MSHR uncacheable cycles
2818system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12223000 # number of ReadReq MSHR uncacheable cycles
2819system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 312114003 # number of ReadReq MSHR uncacheable cycles
2820system.l2c.ReadReq_mshr_uncacheable_latency::total 6637196510 # number of ReadReq MSHR uncacheable cycles
2821system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4740559503 # number of WriteReq MSHR uncacheable cycles
2822system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 195045002 # number of WriteReq MSHR uncacheable cycles
2823system.l2c.WriteReq_mshr_uncacheable_latency::total 4935604505 # number of WriteReq MSHR uncacheable cycles
2824system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles
2825system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10609656010 # number of overall MSHR uncacheable cycles
2826system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12223000 # number of overall MSHR uncacheable cycles
2827system.l2c.overall_mshr_uncacheable_latency::cpu1.data 507159005 # number of overall MSHR uncacheable cycles
2828system.l2c.overall_mshr_uncacheable_latency::total 11572801015 # number of overall MSHR uncacheable cycles
2829system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2830system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2831system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.226284 # mshr miss rate for UpgradeReq accesses
2832system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.516896 # mshr miss rate for UpgradeReq accesses
2833system.l2c.UpgradeReq_mshr_miss_rate::total 0.253708 # mshr miss rate for UpgradeReq accesses
2834system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.248982 # mshr miss rate for SCUpgradeReq accesses
2835system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585895 # mshr miss rate for SCUpgradeReq accesses
2836system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.393411 # mshr miss rate for SCUpgradeReq accesses
--- 69 unchanged lines hidden (view full) ---
2906system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
2907system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
2908system.l2c.overall_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
2909system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency
2910system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719 # average ReadReq mshr uncacheable latency
2911system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency
2912system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency
2913system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency
2914system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199 # average WriteReq mshr uncacheable latency
2915system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641 # average WriteReq mshr uncacheable latency
2916system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603 # average WriteReq mshr uncacheable latency
2917system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency
2918system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569 # average overall mshr uncacheable latency
2919system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency
2920system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475 # average overall mshr uncacheable latency
2921system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951 # average overall mshr uncacheable latency
2922system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2923system.membus.trans_dist::ReadReq 39041 # Transaction distribution
2924system.membus.trans_dist::ReadResp 216336 # Transaction distribution
2925system.membus.trans_dist::WriteReq 31035 # Transaction distribution
2926system.membus.trans_dist::WriteResp 31035 # Transaction distribution
2927system.membus.trans_dist::WritebackDirty 138525 # Transaction distribution
2928system.membus.trans_dist::CleanEvict 18214 # Transaction distribution
2929system.membus.trans_dist::UpgradeReq 73002 # Transaction distribution
2930system.membus.trans_dist::SCUpgradeReq 40704 # Transaction distribution
--- 136 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.848878 # Number of seconds simulated
4sim_ticks 2848878048000 # Number of ticks simulated
5final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 194660 # Simulator instruction rate (inst/s)
8host_op_rate 235713 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4372273286 # Simulator tick rate (ticks/s)
10host_mem_usage 620428 # Number of bytes of host memory used
11host_seconds 651.58 # Real time elapsed on the host
12sim_insts 126836472 # Number of instructions simulated
13sim_ops 153585571 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1701632 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1345580 # Number of bytes read from this memory
--- 669 unchanged lines hidden (view full) ---
689system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15694.801060 # average overall miss latency
690system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060 # average overall miss latency
691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
696system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
697system.cpu0.dcache.fast_writes 0 # number of fast writes performed
698system.cpu0.dcache.cache_copies 0 # number of cache copies performed
699system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks
700system.cpu0.dcache.writebacks::total 757698 # number of writebacks
701system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits
702system.cpu0.dcache.ReadReq_mshr_hits::total 75572 # number of ReadReq MSHR hits
703system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266010 # number of WriteReq MSHR hits
704system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits
705system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14891 # number of LoadLockedReq MSHR hits
706system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
741system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 641500 # number of StoreCondFailReq MSHR miss cycles
742system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles
743system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12322191000 # number of demand (read+write) MSHR miss cycles
744system.cpu0.dcache.demand_mshr_miss_latency::total 12322191000 # number of demand (read+write) MSHR miss cycles
745system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000 # number of overall MSHR miss cycles
746system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles
747system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles
748system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles
749system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5444959500 # number of WriteReq MSHR uncacheable cycles
750system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5444959500 # number of WriteReq MSHR uncacheable cycles
751system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12147316500 # number of overall MSHR uncacheable cycles
752system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12147316500 # number of overall MSHR uncacheable cycles
753system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses
754system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
755system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses
756system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses
757system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses
758system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses
759system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses
760system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
777system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
778system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
779system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency
780system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816 # average overall mshr miss latency
781system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency
782system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency
783system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency
784system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency
785system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024 # average WriteReq mshr uncacheable latency
786system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024 # average WriteReq mshr uncacheable latency
787system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199903.177764 # average overall mshr uncacheable latency
788system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764 # average overall mshr uncacheable latency
789system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
790system.cpu0.icache.tags.replacements 2042425 # number of replacements
791system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use
792system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks.
793system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks.
794system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks.
795system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit.
796system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor
797system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
840system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency
841system.cpu0.icache.overall_avg_miss_latency::total 10073.051428 # average overall miss latency
842system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
843system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
844system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
845system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
846system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
847system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
848system.cpu0.icache.fast_writes 0 # number of fast writes performed
849system.cpu0.icache.cache_copies 0 # number of cache copies performed
850system.cpu0.icache.writebacks::writebacks 2042425 # number of writebacks
851system.cpu0.icache.writebacks::total 2042425 # number of writebacks
852system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2042958 # number of ReadReq MSHR misses
853system.cpu0.icache.ReadReq_mshr_misses::total 2042958 # number of ReadReq MSHR misses
854system.cpu0.icache.demand_mshr_misses::cpu0.inst 2042958 # number of demand (read+write) MSHR misses
855system.cpu0.icache.demand_mshr_misses::total 2042958 # number of demand (read+write) MSHR misses
856system.cpu0.icache.overall_mshr_misses::cpu0.inst 2042958 # number of overall MSHR misses
857system.cpu0.icache.overall_mshr_misses::total 2042958 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
880system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
881system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
882system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
883system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
884system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency
885system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency
886system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency
887system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency
888system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
889system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued
890system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified
891system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue
892system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
893system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
894system.cpu0.l2cache.prefetcher.pfSpanPage 244697 # number of prefetches not generated due to page crossing
895system.cpu0.l2cache.tags.replacements 304900 # number of replacements
896system.cpu0.l2cache.tags.tagsinuse 16120.127106 # Cycle average of tags in use
--- 178 unchanged lines hidden (view full) ---
1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45396.596297 # average overall miss latency
1076system.cpu0.l2cache.overall_avg_miss_latency::total 51526.739597 # average overall miss latency
1077system.cpu0.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked
1078system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1079system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1080system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1081system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1082system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1083system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1084system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1085system.cpu0.l2cache.unused_prefetches 10897 # number of HardPF blocks evicted w/o reference
1086system.cpu0.l2cache.writebacks::writebacks 237171 # number of writebacks
1087system.cpu0.l2cache.writebacks::total 237171 # number of writebacks
1088system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5426 # number of ReadExReq MSHR hits
1089system.cpu0.l2cache.ReadExReq_mshr_hits::total 5426 # number of ReadExReq MSHR hits
1090system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 72 # number of ReadCleanReq MSHR hits
1091system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 72 # number of ReadCleanReq MSHR hits
1092system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 591 # number of ReadSharedReq MSHR hits
--- 64 unchanged lines hidden (view full) ---
1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1833000 # number of overall MSHR miss cycles
1158system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4100378000 # number of overall MSHR miss cycles
1159system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5357247999 # number of overall MSHR miss cycles
1160system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21051299430 # number of overall MSHR miss cycles
1161system.cpu0.l2cache.overall_mshr_miss_latency::total 30542659429 # number of overall MSHR miss cycles
1162system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles
1163system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445890500 # number of ReadReq MSHR uncacheable cycles
1164system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971910500 # number of ReadReq MSHR uncacheable cycles
1165system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5229022000 # number of WriteReq MSHR uncacheable cycles
1166system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5229022000 # number of WriteReq MSHR uncacheable cycles
1167system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles
1168system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11674912500 # number of overall MSHR uncacheable cycles
1169system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12200932500 # number of overall MSHR uncacheable cycles
1170system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for ReadReq accesses
1171system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for ReadReq accesses
1172system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009054 # mshr miss rate for ReadReq accesses
1173system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1174system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1175system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1176system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1177system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 41 unchanged lines hidden (view full) ---
1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency
1223system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency
1224system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency
1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency
1226system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency
1227system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872 # average WriteReq mshr uncacheable latency
1228system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872 # average WriteReq mshr uncacheable latency
1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency
1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746 # average overall mshr uncacheable latency
1231system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124 # average overall mshr uncacheable latency
1232system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1233system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter.
1234system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1235system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1236system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter.
1237system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1238system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1239system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution
1240system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution
--- 376 unchanged lines hidden (view full) ---
1617system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23712.367863 # average overall miss latency
1618system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863 # average overall miss latency
1619system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1620system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1621system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1622system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1623system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1624system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1625system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1626system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1627system.cpu1.dcache.writebacks::writebacks 155125 # number of writebacks
1628system.cpu1.dcache.writebacks::total 155125 # number of writebacks
1629system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12753 # number of ReadReq MSHR hits
1630system.cpu1.dcache.ReadReq_mshr_hits::total 12753 # number of ReadReq MSHR hits
1631system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42136 # number of WriteReq MSHR hits
1632system.cpu1.dcache.WriteReq_mshr_hits::total 42136 # number of WriteReq MSHR hits
1633system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11686 # number of LoadLockedReq MSHR hits
1634system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11686 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
1669system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1094500 # number of StoreCondFailReq MSHR miss cycles
1670system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1094500 # number of StoreCondFailReq MSHR miss cycles
1671system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4556767000 # number of demand (read+write) MSHR miss cycles
1672system.cpu1.dcache.demand_mshr_miss_latency::total 4556767000 # number of demand (read+write) MSHR miss cycles
1673system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500 # number of overall MSHR miss cycles
1674system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles
1675system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles
1676system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles
1677system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251809500 # number of WriteReq MSHR uncacheable cycles
1678system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251809500 # number of WriteReq MSHR uncacheable cycles
1679system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641276500 # number of overall MSHR uncacheable cycles
1680system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641276500 # number of overall MSHR uncacheable cycles
1681system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses
1682system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses
1683system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses
1684system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses
1685system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses
1686system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses
1687system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses
1688system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
1705system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1706system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1707system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency
1708system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency
1709system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency
1710system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency
1711system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency
1712system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency
1713system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177 # average WriteReq mshr uncacheable latency
1714system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177 # average WriteReq mshr uncacheable latency
1715system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711 # average overall mshr uncacheable latency
1716system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711 # average overall mshr uncacheable latency
1717system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1718system.cpu1.icache.tags.replacements 856657 # number of replacements
1719system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use
1720system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks.
1721system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks.
1722system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks.
1723system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit.
1724system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor
1725system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
1768system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency
1769system.cpu1.icache.overall_avg_miss_latency::total 8854.776013 # average overall miss latency
1770system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1771system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1772system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1773system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1774system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1775system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1776system.cpu1.icache.fast_writes 0 # number of fast writes performed
1777system.cpu1.icache.cache_copies 0 # number of cache copies performed
1778system.cpu1.icache.writebacks::writebacks 856657 # number of writebacks
1779system.cpu1.icache.writebacks::total 856657 # number of writebacks
1780system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # number of ReadReq MSHR misses
1781system.cpu1.icache.ReadReq_mshr_misses::total 857169 # number of ReadReq MSHR misses
1782system.cpu1.icache.demand_mshr_misses::cpu1.inst 857169 # number of demand (read+write) MSHR misses
1783system.cpu1.icache.demand_mshr_misses::total 857169 # number of demand (read+write) MSHR misses
1784system.cpu1.icache.overall_mshr_misses::cpu1.inst 857169 # number of overall MSHR misses
1785system.cpu1.icache.overall_mshr_misses::total 857169 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
1808system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1809system.cpu1.icache.demand_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1810system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1811system.cpu1.icache.overall_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1812system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average ReadReq mshr uncacheable latency
1813system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency
1814system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency
1815system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency
1816system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1817system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued
1818system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified
1819system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue
1820system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1821system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1822system.cpu1.l2cache.prefetcher.pfSpanPage 49365 # number of prefetches not generated due to page crossing
1823system.cpu1.l2cache.tags.replacements 38167 # number of replacements
1824system.cpu1.l2cache.tags.tagsinuse 15174.819793 # Cycle average of tags in use
--- 180 unchanged lines hidden (view full) ---
2005system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33463.491285 # average overall miss latency
2006system.cpu1.l2cache.overall_avg_miss_latency::total 36114.627487 # average overall miss latency
2007system.cpu1.l2cache.blocked_cycles::no_mshrs 30 # number of cycles access was blocked
2008system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2009system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
2010system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2011system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
2012system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2013system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2014system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2015system.cpu1.l2cache.unused_prefetches 580 # number of HardPF blocks evicted w/o reference
2016system.cpu1.l2cache.writebacks::writebacks 29115 # number of writebacks
2017system.cpu1.l2cache.writebacks::total 29115 # number of writebacks
2018system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 240 # number of ReadExReq MSHR hits
2019system.cpu1.l2cache.ReadExReq_mshr_hits::total 240 # number of ReadExReq MSHR hits
2020system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
2021system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
2022system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 39 # number of ReadSharedReq MSHR hits
--- 66 unchanged lines hidden (view full) ---
2089system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3383500 # number of overall MSHR miss cycles
2090system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 662136000 # number of overall MSHR miss cycles
2091system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2693368996 # number of overall MSHR miss cycles
2092system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of overall MSHR miss cycles
2093system.cpu1.l2cache.overall_mshr_miss_latency::total 4332115741 # number of overall MSHR miss cycles
2094system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14575500 # number of ReadReq MSHR uncacheable cycles
2095system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365633500 # number of ReadReq MSHR uncacheable cycles
2096system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 380209000 # number of ReadReq MSHR uncacheable cycles
2097system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 234344500 # number of WriteReq MSHR uncacheable cycles
2098system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 234344500 # number of WriteReq MSHR uncacheable cycles
2099system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14575500 # number of overall MSHR uncacheable cycles
2100system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 599978000 # number of overall MSHR uncacheable cycles
2101system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614553500 # number of overall MSHR uncacheable cycles
2102system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses
2103system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for ReadReq accesses
2104system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032323 # mshr miss rate for ReadReq accesses
2105system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2106system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2107system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2108system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2109system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 43 unchanged lines hidden (view full) ---
2153system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
2154system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
2155system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
2156system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency
2157system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency
2158system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency
2159system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency
2160system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency
2161system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689 # average WriteReq mshr uncacheable latency
2162system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689 # average WriteReq mshr uncacheable latency
2163system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency
2164system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139 # average overall mshr uncacheable latency
2165system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087 # average overall mshr uncacheable latency
2166system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2167system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter.
2168system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2169system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2170system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter.
2171system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2172system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2173system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution
2174system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution
--- 154 unchanged lines hidden (view full) ---
2329system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2330system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2331system.iocache.tags.tag_accesses 328203 # Number of tag accesses
2332system.iocache.tags.data_accesses 328203 # Number of data accesses
2333system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
2334system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
2335system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2336system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2337system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
2338system.iocache.demand_misses::total 243 # number of demand (read+write) misses
2339system.iocache.overall_misses::realview.ide 243 # number of overall misses
2340system.iocache.overall_misses::total 243 # number of overall misses
2341system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles
2342system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles
2343system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles
2344system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles
2345system.iocache.demand_miss_latency::realview.ide 31660877 # number of demand (read+write) miss cycles
2346system.iocache.demand_miss_latency::total 31660877 # number of demand (read+write) miss cycles
2347system.iocache.overall_miss_latency::realview.ide 31660877 # number of overall miss cycles
2348system.iocache.overall_miss_latency::total 31660877 # number of overall miss cycles
2349system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
2350system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
2351system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2352system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2353system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
2354system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
2355system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
2356system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
2357system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2358system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2359system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2360system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2361system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2362system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2363system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2364system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2365system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency
2366system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency
2367system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency
2368system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency
2369system.iocache.demand_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
2370system.iocache.demand_avg_miss_latency::total 130291.674897 # average overall miss latency
2371system.iocache.overall_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
2372system.iocache.overall_avg_miss_latency::total 130291.674897 # average overall miss latency
2373system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2374system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2375system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2376system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2377system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2378system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2379system.iocache.fast_writes 0 # number of fast writes performed
2380system.iocache.cache_copies 0 # number of cache copies performed
2381system.iocache.writebacks::writebacks 36190 # number of writebacks
2382system.iocache.writebacks::total 36190 # number of writebacks
2383system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
2384system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
2385system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2386system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2387system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
2388system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
2389system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
2390system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
2391system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles
2392system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles
2393system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles
2394system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles
2395system.iocache.demand_mshr_miss_latency::realview.ide 19510877 # number of demand (read+write) MSHR miss cycles
2396system.iocache.demand_mshr_miss_latency::total 19510877 # number of demand (read+write) MSHR miss cycles
2397system.iocache.overall_mshr_miss_latency::realview.ide 19510877 # number of overall MSHR miss cycles
2398system.iocache.overall_mshr_miss_latency::total 19510877 # number of overall MSHR miss cycles
2399system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2400system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2401system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2402system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2403system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2404system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2405system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2406system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2407system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897 # average ReadReq mshr miss latency
2408system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency
2409system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency
2410system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency
2411system.iocache.demand_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
2412system.iocache.demand_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
2413system.iocache.overall_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency
2414system.iocache.overall_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency
2415system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2416system.l2c.tags.replacements 132278 # number of replacements
2417system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use
2418system.l2c.tags.total_refs 475189 # Total number of references to valid blocks.
2419system.l2c.tags.sampled_refs 196356 # Sample count of references to valid blocks.
2420system.l2c.tags.avg_refs 2.420038 # Average number of references to valid blocks.
2421system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2422system.l2c.tags.occ_blocks::writebacks 13432.084830 # Average occupied blocks per requestor
2423system.l2c.tags.occ_blocks::cpu0.dtb.walker 86.256901 # Average occupied blocks per requestor
--- 278 unchanged lines hidden (view full) ---
2702system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average overall miss latency
2703system.l2c.overall_avg_miss_latency::total 146696.352377 # average overall miss latency
2704system.l2c.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
2705system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2706system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2707system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2708system.l2c.avg_blocked_cycles::no_mshrs 45 # average number of cycles each access was blocked
2709system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2710system.l2c.fast_writes 0 # number of fast writes performed
2711system.l2c.cache_copies 0 # number of cache copies performed
2712system.l2c.writebacks::writebacks 102335 # number of writebacks
2713system.l2c.writebacks::total 102335 # number of writebacks
2714system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
2715system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits
2716system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
2717system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
2718system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
2719system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
--- 93 unchanged lines hidden (view full) ---
2813system.l2c.overall_mshr_miss_latency::cpu1.data 1203034025 # number of overall MSHR miss cycles
2814system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of overall MSHR miss cycles
2815system.l2c.overall_mshr_miss_latency::total 26857931717 # number of overall MSHR miss cycles
2816system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443763000 # number of ReadReq MSHR uncacheable cycles
2817system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5869096507 # number of ReadReq MSHR uncacheable cycles
2818system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12223000 # number of ReadReq MSHR uncacheable cycles
2819system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 312114003 # number of ReadReq MSHR uncacheable cycles
2820system.l2c.ReadReq_mshr_uncacheable_latency::total 6637196510 # number of ReadReq MSHR uncacheable cycles
2821system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4740559503 # number of WriteReq MSHR uncacheable cycles
2822system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 195045002 # number of WriteReq MSHR uncacheable cycles
2823system.l2c.WriteReq_mshr_uncacheable_latency::total 4935604505 # number of WriteReq MSHR uncacheable cycles
2824system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles
2825system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10609656010 # number of overall MSHR uncacheable cycles
2826system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12223000 # number of overall MSHR uncacheable cycles
2827system.l2c.overall_mshr_uncacheable_latency::cpu1.data 507159005 # number of overall MSHR uncacheable cycles
2828system.l2c.overall_mshr_uncacheable_latency::total 11572801015 # number of overall MSHR uncacheable cycles
2829system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2830system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2831system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.226284 # mshr miss rate for UpgradeReq accesses
2832system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.516896 # mshr miss rate for UpgradeReq accesses
2833system.l2c.UpgradeReq_mshr_miss_rate::total 0.253708 # mshr miss rate for UpgradeReq accesses
2834system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.248982 # mshr miss rate for SCUpgradeReq accesses
2835system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585895 # mshr miss rate for SCUpgradeReq accesses
2836system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.393411 # mshr miss rate for SCUpgradeReq accesses
--- 69 unchanged lines hidden (view full) ---
2906system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
2907system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
2908system.l2c.overall_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
2909system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency
2910system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719 # average ReadReq mshr uncacheable latency
2911system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency
2912system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency
2913system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency
2914system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199 # average WriteReq mshr uncacheable latency
2915system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641 # average WriteReq mshr uncacheable latency
2916system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603 # average WriteReq mshr uncacheable latency
2917system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency
2918system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569 # average overall mshr uncacheable latency
2919system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency
2920system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475 # average overall mshr uncacheable latency
2921system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951 # average overall mshr uncacheable latency
2922system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2923system.membus.trans_dist::ReadReq 39041 # Transaction distribution
2924system.membus.trans_dist::ReadResp 216336 # Transaction distribution
2925system.membus.trans_dist::WriteReq 31035 # Transaction distribution
2926system.membus.trans_dist::WriteResp 31035 # Transaction distribution
2927system.membus.trans_dist::WritebackDirty 138525 # Transaction distribution
2928system.membus.trans_dist::CleanEvict 18214 # Transaction distribution
2929system.membus.trans_dist::UpgradeReq 73002 # Transaction distribution
2930system.membus.trans_dist::SCUpgradeReq 40704 # Transaction distribution
--- 136 unchanged lines hidden ---