1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.145505 # Number of seconds simulated
4sim_ticks 1145504982000 # Number of ticks simulated
5final_tick 1145504982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 113120 # Simulator instruction rate (inst/s)
8host_op_rate 136231 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2095202848 # Simulator tick rate (ticks/s)
10host_mem_usage 413760 # Number of bytes of host memory used
11host_seconds 546.73 # Real time elapsed on the host
12sim_insts 61845931 # Number of instructions simulated
13sim_ops 74481224 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory
17system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
18system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
19system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory
20system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
21system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
22system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory
23system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
24system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
25system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s)
26system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s)
27system.realview.nvmem.bw_read::total 615 # Total read bandwidth from this memory (bytes/s)
28system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s)
29system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s)
30system.realview.nvmem.bw_inst_read::total 615 # Instruction read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s)
32system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s)
33system.realview.nvmem.bw_total::total 615 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory
35system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
36system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
37system.physmem.bytes_read::cpu0.inst 7004988 # Number of bytes read from this memory
38system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory
39system.physmem.bytes_read::cpu1.inst 3603320 # Number of bytes read from this memory
40system.physmem.bytes_read::total 60941044 # Number of bytes read from this memory
41system.physmem.bytes_inst_read::cpu0.inst 751104 # Number of instructions bytes read from this memory
42system.physmem.bytes_inst_read::cpu1.inst 270784 # Number of instructions bytes read from this memory
43system.physmem.bytes_inst_read::total 1021888 # Number of instructions bytes read from this memory
44system.physmem.bytes_written::writebacks 4281152 # Number of bytes written to this memory
45system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory
46system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory
47system.physmem.bytes_written::total 7308496 # Number of bytes written to this memory
48system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory
49system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory
50system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
51system.physmem.num_reads::cpu0.inst 109512 # Number of read requests responded to by this memory
52system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory
53system.physmem.num_reads::cpu1.inst 56320 # Number of read requests responded to by this memory
54system.physmem.num_reads::total 6457305 # Number of read requests responded to by this memory
55system.physmem.num_writes::writebacks 66893 # Number of write requests responded to by this memory
56system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory
57system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory
58system.physmem.num_writes::total 823729 # Number of write requests responded to by this memory
59system.physmem.bw_read::realview.clcd 43938393 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu0.dtb.walker 335 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::cpu0.inst 6115196 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_read::cpu1.inst 3145617 # Total read bandwidth from this memory (bytes/s)
65system.physmem.bw_read::total 53200156 # Total read bandwidth from this memory (bytes/s)
66system.physmem.bw_inst_read::cpu0.inst 655697 # Instruction read bandwidth from this memory (bytes/s)
67system.physmem.bw_inst_read::cpu1.inst 236388 # Instruction read bandwidth from this memory (bytes/s)
68system.physmem.bw_inst_read::total 892085 # Instruction read bandwidth from this memory (bytes/s)
69system.physmem.bw_write::writebacks 3737349 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_write::cpu0.inst 14841 # Write bandwidth from this memory (bytes/s)
71system.physmem.bw_write::cpu1.inst 2627962 # Write bandwidth from this memory (bytes/s)
72system.physmem.bw_write::total 6380152 # Write bandwidth from this memory (bytes/s)
73system.physmem.bw_total::writebacks 3737349 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::realview.clcd 43938393 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.dtb.walker 335 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu0.inst 6130037 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.inst 5773579 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::total 59580308 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.readReqs 6457305 # Number of read requests accepted
82system.physmem.writeReqs 823729 # Number of write requests accepted
83system.physmem.readBursts 6457305 # Number of DRAM read bursts, including those serviced by the write queue
84system.physmem.writeBursts 823729 # Number of DRAM write bursts, including those merged in the write queue
85system.physmem.bytesReadDRAM 413239936 # Total number of bytes read from DRAM
86system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue
87system.physmem.bytesWritten 7320448 # Total number of bytes written to DRAM
88system.physmem.bytesReadSys 60941044 # Total read bytes from the system interface side
89system.physmem.bytesWrittenSys 7308496 # Total written bytes from the system interface side
90system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue
91system.physmem.mergedWrBursts 709326 # Number of DRAM write bursts merged with an existing one
92system.physmem.neitherReadNorWriteReqs 12284 # Number of requests that are neither read nor write
93system.physmem.perBankRdBursts::0 403300 # Per bank write bursts
94system.physmem.perBankRdBursts::1 403658 # Per bank write bursts
95system.physmem.perBankRdBursts::2 403038 # Per bank write bursts
96system.physmem.perBankRdBursts::3 403410 # Per bank write bursts
97system.physmem.perBankRdBursts::4 406147 # Per bank write bursts
98system.physmem.perBankRdBursts::5 403703 # Per bank write bursts
99system.physmem.perBankRdBursts::6 403511 # Per bank write bursts
100system.physmem.perBankRdBursts::7 403334 # Per bank write bursts
101system.physmem.perBankRdBursts::8 403656 # Per bank write bursts
102system.physmem.perBankRdBursts::9 404136 # Per bank write bursts
103system.physmem.perBankRdBursts::10 403079 # Per bank write bursts
104system.physmem.perBankRdBursts::11 402530 # Per bank write bursts
105system.physmem.perBankRdBursts::12 403635 # Per bank write bursts
106system.physmem.perBankRdBursts::13 403544 # Per bank write bursts
107system.physmem.perBankRdBursts::14 403293 # Per bank write bursts
108system.physmem.perBankRdBursts::15 402900 # Per bank write bursts
109system.physmem.perBankWrBursts::0 6991 # Per bank write bursts
110system.physmem.perBankWrBursts::1 7395 # Per bank write bursts
111system.physmem.perBankWrBursts::2 6850 # Per bank write bursts
112system.physmem.perBankWrBursts::3 7056 # Per bank write bursts
113system.physmem.perBankWrBursts::4 7584 # Per bank write bursts
114system.physmem.perBankWrBursts::5 7290 # Per bank write bursts
115system.physmem.perBankWrBursts::6 7311 # Per bank write bursts
116system.physmem.perBankWrBursts::7 7141 # Per bank write bursts
117system.physmem.perBankWrBursts::8 7309 # Per bank write bursts
118system.physmem.perBankWrBursts::9 7743 # Per bank write bursts
119system.physmem.perBankWrBursts::10 6877 # Per bank write bursts
120system.physmem.perBankWrBursts::11 6465 # Per bank write bursts
121system.physmem.perBankWrBursts::12 7382 # Per bank write bursts
122system.physmem.perBankWrBursts::13 7153 # Per bank write bursts
123system.physmem.perBankWrBursts::14 7067 # Per bank write bursts
124system.physmem.perBankWrBursts::15 6768 # Per bank write bursts
125system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
126system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
127system.physmem.totGap 1145502120500 # Total gap between requests
128system.physmem.readPktSize::0 0 # Read request sizes (log2)
129system.physmem.readPktSize::1 0 # Read request sizes (log2)
130system.physmem.readPktSize::2 59 # Read request sizes (log2)
131system.physmem.readPktSize::3 6291481 # Read request sizes (log2)
132system.physmem.readPktSize::4 0 # Read request sizes (log2)
133system.physmem.readPktSize::5 0 # Read request sizes (log2)
134system.physmem.readPktSize::6 165765 # Read request sizes (log2)
135system.physmem.writePktSize::0 0 # Write request sizes (log2)
136system.physmem.writePktSize::1 0 # Write request sizes (log2)
137system.physmem.writePktSize::2 756836 # Write request sizes (log2)
138system.physmem.writePktSize::3 0 # Write request sizes (log2)
139system.physmem.writePktSize::4 0 # Write request sizes (log2)
140system.physmem.writePktSize::5 0 # Write request sizes (log2)
141system.physmem.writePktSize::6 66893 # Write request sizes (log2)
142system.physmem.rdQLenPdf::0 558286 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::1 398741 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::2 399967 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::3 444496 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::4 405001 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::5 431562 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::6 1118263 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::7 1083915 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::8 1408608 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::9 55788 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::10 45494 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::11 41962 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::12 40334 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::13 8421 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::14 7962 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::15 7851 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::16 218 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
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174system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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180system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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182system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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190system.physmem.wrQLenPdf::16 3973 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::17 6584 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::18 6653 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::19 6664 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::20 6655 # What write queue length does an incoming req see
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196system.physmem.wrQLenPdf::22 6656 # What write queue length does an incoming req see
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198system.physmem.wrQLenPdf::24 6656 # What write queue length does an incoming req see
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202system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see
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204system.physmem.wrQLenPdf::30 6657 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::31 6660 # What write queue length does an incoming req see
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230system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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236system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
238system.physmem.bytesPerActivate::samples 460787 # Bytes accessed per row activation
239system.physmem.bytesPerActivate::mean 912.700193 # Bytes accessed per row activation
240system.physmem.bytesPerActivate::gmean 781.910252 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::stdev 290.668132 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::0-127 24338 5.28% 5.28% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::128-255 21658 4.70% 9.98% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::256-383 5935 1.29% 11.27% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::384-511 2553 0.55% 11.82% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::512-639 2424 0.53% 12.35% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::640-767 1615 0.35% 12.70% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::768-895 4021 0.87% 13.57% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::896-1023 977 0.21% 13.79% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::1024-1151 397266 86.21% 100.00% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::total 460787 # Bytes accessed per row activation
252system.physmem.rdPerTurnAround::samples 6652 # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::mean 970.665664 # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::stdev 26177.869763 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::0-65535 6645 99.89% 99.89% # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 6652 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 6652 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 17.195129 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 17.166489 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 0.984981 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16 2678 40.26% 40.26% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::17 22 0.33% 40.59% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::18 3930 59.08% 99.67% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::19 20 0.30% 99.97% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::total 6652 # Writes before turning the bus around for reads
272system.physmem.totQLat 165525335000 # Total ticks spent queuing
273system.physmem.totMemAccLat 286591722500 # Total ticks spent from burst creation until serviced by the DRAM
274system.physmem.totBusLat 32284370000 # Total ticks spent in databus transfers
275system.physmem.avgQLat 25635.52 # Average queueing delay per DRAM burst
276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
277system.physmem.avgMemAccLat 44385.52 # Average memory access latency per DRAM burst
278system.physmem.avgRdBW 360.75 # Average DRAM read bandwidth in MiByte/s
279system.physmem.avgWrBW 6.39 # Average achieved write bandwidth in MiByte/s
280system.physmem.avgRdBWSys 53.20 # Average system read bandwidth in MiByte/s
281system.physmem.avgWrBWSys 6.38 # Average system write bandwidth in MiByte/s
282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
283system.physmem.busUtil 2.87 # Data bus utilization in percentage
284system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads
285system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
286system.physmem.avgRdQLen 3.81 # Average read queue length when enqueuing
287system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing
288system.physmem.readRowHits 6016106 # Number of row buffer hits during reads
289system.physmem.writeRowHits 94363 # Number of row buffer hits during writes
290system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads
291system.physmem.writeRowHitRate 82.48 # Row buffer hit rate for writes
292system.physmem.avgGap 157326.85 # Average gap between requests
293system.physmem.pageHitRate 92.99 # Row buffer hit rate, read and write combined
294system.physmem.memoryStateTime::IDLE 907058635500 # Time in different power states
295system.physmem.memoryStateTime::REF 38250680000 # Time in different power states
296system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
297system.physmem.memoryStateTime::ACT 200188472000 # Time in different power states
298system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
299system.membus.throughput 61688542 # Throughput (bytes/s)
300system.membus.trans_dist::ReadReq 7506218 # Transaction distribution
301system.membus.trans_dist::ReadResp 7506218 # Transaction distribution
302system.membus.trans_dist::WriteReq 767823 # Transaction distribution
303system.membus.trans_dist::WriteResp 767823 # Transaction distribution
304system.membus.trans_dist::Writeback 66893 # Transaction distribution
305system.membus.trans_dist::UpgradeReq 33061 # Transaction distribution
306system.membus.trans_dist::SCUpgradeReq 17229 # Transaction distribution
307system.membus.trans_dist::UpgradeResp 12284 # Transaction distribution
308system.membus.trans_dist::ReadExReq 137868 # Transaction distribution
309system.membus.trans_dist::ReadExResp 137512 # Transaction distribution
310system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382652 # Packet count per connected master and slave (bytes)
311system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
312system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11272 # Packet count per connected master and slave (bytes)
313system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
314system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes)
315system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975193 # Packet count per connected master and slave (bytes)
316system.membus.pkt_count_system.l2c.mem_side::total 4370017 # Packet count per connected master and slave (bytes)
317system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes)
318system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes)
319system.membus.pkt_count::total 16952929 # Packet count per connected master and slave (bytes)
320system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389988 # Cumulative packet size per connected master and slave (bytes)
321system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
322system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22544 # Cumulative packet size per connected master and slave (bytes)
323system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
324system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes)
325system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17917892 # Cumulative packet size per connected master and slave (bytes)
326system.membus.tot_pkt_size_system.l2c.mem_side::total 20332884 # Cumulative packet size per connected master and slave (bytes)
327system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes)
328system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes)
329system.membus.tot_pkt_size::total 70664532 # Cumulative packet size per connected master and slave (bytes)
330system.membus.data_through_bus 70664532 # Total data (bytes)
331system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
332system.membus.reqLayer0.occupancy 1775897999 # Layer occupancy (ticks)
333system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
334system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks)
335system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
336system.membus.reqLayer2.occupancy 10198500 # Layer occupancy (ticks)
337system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
338system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
339system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
340system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks)
341system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
342system.membus.reqLayer6.occupancy 8866177000 # Layer occupancy (ticks)
343system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
344system.membus.respLayer1.occupancy 4931588399 # Layer occupancy (ticks)
345system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
346system.membus.respLayer2.occupancy 15569082998 # Layer occupancy (ticks)
347system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
348system.cpu_clk_domain.clock 500 # Clock period in ticks
349system.l2c.tags.replacements 73238 # number of replacements
350system.l2c.tags.tagsinuse 53823.910561 # Cycle average of tags in use
351system.l2c.tags.total_refs 2398257 # Total number of references to valid blocks.
352system.l2c.tags.sampled_refs 138408 # Sample count of references to valid blocks.
353system.l2c.tags.avg_refs 17.327445 # Average number of references to valid blocks.
354system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
355system.l2c.tags.occ_blocks::writebacks 38958.946929 # Average occupied blocks per requestor
356system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.880846 # Average occupied blocks per requestor
357system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001294 # Average occupied blocks per requestor
358system.l2c.tags.occ_blocks::cpu0.inst 8788.881914 # Average occupied blocks per requestor
359system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.740937 # Average occupied blocks per requestor
360system.l2c.tags.occ_blocks::cpu1.inst 6066.458640 # Average occupied blocks per requestor
361system.l2c.tags.occ_percent::writebacks 0.594466 # Average percentage of cache occupancy
362system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy
363system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
364system.l2c.tags.occ_percent::cpu0.inst 0.134108 # Average percentage of cache occupancy
365system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000118 # Average percentage of cache occupancy
366system.l2c.tags.occ_percent::cpu1.inst 0.092567 # Average percentage of cache occupancy
367system.l2c.tags.occ_percent::total 0.821288 # Average percentage of cache occupancy
368system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
369system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id
370system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
371system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
372system.l2c.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
373system.l2c.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id
374system.l2c.tags.age_task_id_blocks_1024::3 8664 # Occupied blocks per task id
375system.l2c.tags.age_task_id_blocks_1024::4 53947 # Occupied blocks per task id
376system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
377system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id
378system.l2c.tags.tag_accesses 23040420 # Number of tag accesses
379system.l2c.tags.data_accesses 23040420 # Number of data accesses
380system.l2c.ReadReq_hits::cpu0.dtb.walker 22272 # number of ReadReq hits
381system.l2c.ReadReq_hits::cpu0.itb.walker 6564 # number of ReadReq hits
382system.l2c.ReadReq_hits::cpu0.inst 949144 # number of ReadReq hits
383system.l2c.ReadReq_hits::cpu1.dtb.walker 22723 # number of ReadReq hits
384system.l2c.ReadReq_hits::cpu1.itb.walker 5189 # number of ReadReq hits
385system.l2c.ReadReq_hits::cpu1.inst 959680 # number of ReadReq hits
386system.l2c.ReadReq_hits::total 1965572 # number of ReadReq hits
387system.l2c.Writeback_hits::writebacks 575172 # number of Writeback hits
388system.l2c.Writeback_hits::total 575172 # number of Writeback hits
389system.l2c.UpgradeReq_hits::cpu0.inst 954 # number of UpgradeReq hits
390system.l2c.UpgradeReq_hits::cpu1.inst 1026 # number of UpgradeReq hits
391system.l2c.UpgradeReq_hits::total 1980 # number of UpgradeReq hits
392system.l2c.SCUpgradeReq_hits::cpu0.inst 203 # number of SCUpgradeReq hits
393system.l2c.SCUpgradeReq_hits::cpu1.inst 94 # number of SCUpgradeReq hits
394system.l2c.SCUpgradeReq_hits::total 297 # number of SCUpgradeReq hits
395system.l2c.ReadExReq_hits::cpu0.inst 58656 # number of ReadExReq hits
396system.l2c.ReadExReq_hits::cpu1.inst 50708 # number of ReadExReq hits
397system.l2c.ReadExReq_hits::total 109364 # number of ReadExReq hits
398system.l2c.demand_hits::cpu0.dtb.walker 22272 # number of demand (read+write) hits
399system.l2c.demand_hits::cpu0.itb.walker 6564 # number of demand (read+write) hits
400system.l2c.demand_hits::cpu0.inst 1007800 # number of demand (read+write) hits
401system.l2c.demand_hits::cpu1.dtb.walker 22723 # number of demand (read+write) hits
402system.l2c.demand_hits::cpu1.itb.walker 5189 # number of demand (read+write) hits
403system.l2c.demand_hits::cpu1.inst 1010388 # number of demand (read+write) hits
404system.l2c.demand_hits::total 2074936 # number of demand (read+write) hits
405system.l2c.overall_hits::cpu0.dtb.walker 22272 # number of overall hits
406system.l2c.overall_hits::cpu0.itb.walker 6564 # number of overall hits
407system.l2c.overall_hits::cpu0.inst 1007800 # number of overall hits
408system.l2c.overall_hits::cpu1.dtb.walker 22723 # number of overall hits
409system.l2c.overall_hits::cpu1.itb.walker 5189 # number of overall hits
410system.l2c.overall_hits::cpu1.inst 1010388 # number of overall hits
411system.l2c.overall_hits::total 2074936 # number of overall hits
412system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses
413system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
414system.l2c.ReadReq_misses::cpu0.inst 16107 # number of ReadReq misses
415system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses
416system.l2c.ReadReq_misses::cpu1.inst 9802 # number of ReadReq misses
417system.l2c.ReadReq_misses::total 25926 # number of ReadReq misses
418system.l2c.UpgradeReq_misses::cpu0.inst 4879 # number of UpgradeReq misses
419system.l2c.UpgradeReq_misses::cpu1.inst 4062 # number of UpgradeReq misses
420system.l2c.UpgradeReq_misses::total 8941 # number of UpgradeReq misses
421system.l2c.SCUpgradeReq_misses::cpu0.inst 695 # number of SCUpgradeReq misses
422system.l2c.SCUpgradeReq_misses::cpu1.inst 300 # number of SCUpgradeReq misses
423system.l2c.SCUpgradeReq_misses::total 995 # number of SCUpgradeReq misses
424system.l2c.ReadExReq_misses::cpu0.inst 92450 # number of ReadExReq misses
425system.l2c.ReadExReq_misses::cpu1.inst 47410 # number of ReadExReq misses
426system.l2c.ReadExReq_misses::total 139860 # number of ReadExReq misses
427system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses
428system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
429system.l2c.demand_misses::cpu0.inst 108557 # number of demand (read+write) misses
430system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses
431system.l2c.demand_misses::cpu1.inst 57212 # number of demand (read+write) misses
432system.l2c.demand_misses::total 165786 # number of demand (read+write) misses
433system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses
434system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
435system.l2c.overall_misses::cpu0.inst 108557 # number of overall misses
436system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses
437system.l2c.overall_misses::cpu1.inst 57212 # number of overall misses
438system.l2c.overall_misses::total 165786 # number of overall misses
439system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 592000 # number of ReadReq miss cycles
440system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles
441system.l2c.ReadReq_miss_latency::cpu0.inst 1134045250 # number of ReadReq miss cycles
442system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 716250 # number of ReadReq miss cycles
443system.l2c.ReadReq_miss_latency::cpu1.inst 732959500 # number of ReadReq miss cycles
444system.l2c.ReadReq_miss_latency::total 1868462500 # number of ReadReq miss cycles
445system.l2c.UpgradeReq_miss_latency::cpu0.inst 8149146 # number of UpgradeReq miss cycles
446system.l2c.UpgradeReq_miss_latency::cpu1.inst 13619415 # number of UpgradeReq miss cycles
447system.l2c.UpgradeReq_miss_latency::total 21768561 # number of UpgradeReq miss cycles
448system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 695470 # number of SCUpgradeReq miss cycles
449system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2181906 # number of SCUpgradeReq miss cycles
450system.l2c.SCUpgradeReq_miss_latency::total 2877376 # number of SCUpgradeReq miss cycles
451system.l2c.ReadExReq_miss_latency::cpu0.inst 6400503611 # number of ReadExReq miss cycles
452system.l2c.ReadExReq_miss_latency::cpu1.inst 3385304039 # number of ReadExReq miss cycles
453system.l2c.ReadExReq_miss_latency::total 9785807650 # number of ReadExReq miss cycles
454system.l2c.demand_miss_latency::cpu0.dtb.walker 592000 # number of demand (read+write) miss cycles
455system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles
456system.l2c.demand_miss_latency::cpu0.inst 7534548861 # number of demand (read+write) miss cycles
457system.l2c.demand_miss_latency::cpu1.dtb.walker 716250 # number of demand (read+write) miss cycles
458system.l2c.demand_miss_latency::cpu1.inst 4118263539 # number of demand (read+write) miss cycles
459system.l2c.demand_miss_latency::total 11654270150 # number of demand (read+write) miss cycles
460system.l2c.overall_miss_latency::cpu0.dtb.walker 592000 # number of overall miss cycles
461system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles
462system.l2c.overall_miss_latency::cpu0.inst 7534548861 # number of overall miss cycles
463system.l2c.overall_miss_latency::cpu1.dtb.walker 716250 # number of overall miss cycles
464system.l2c.overall_miss_latency::cpu1.inst 4118263539 # number of overall miss cycles
465system.l2c.overall_miss_latency::total 11654270150 # number of overall miss cycles
466system.l2c.ReadReq_accesses::cpu0.dtb.walker 22278 # number of ReadReq accesses(hits+misses)
467system.l2c.ReadReq_accesses::cpu0.itb.walker 6566 # number of ReadReq accesses(hits+misses)
468system.l2c.ReadReq_accesses::cpu0.inst 965251 # number of ReadReq accesses(hits+misses)
469system.l2c.ReadReq_accesses::cpu1.dtb.walker 22732 # number of ReadReq accesses(hits+misses)
470system.l2c.ReadReq_accesses::cpu1.itb.walker 5189 # number of ReadReq accesses(hits+misses)
471system.l2c.ReadReq_accesses::cpu1.inst 969482 # number of ReadReq accesses(hits+misses)
472system.l2c.ReadReq_accesses::total 1991498 # number of ReadReq accesses(hits+misses)
473system.l2c.Writeback_accesses::writebacks 575172 # number of Writeback accesses(hits+misses)
474system.l2c.Writeback_accesses::total 575172 # number of Writeback accesses(hits+misses)
475system.l2c.UpgradeReq_accesses::cpu0.inst 5833 # number of UpgradeReq accesses(hits+misses)
476system.l2c.UpgradeReq_accesses::cpu1.inst 5088 # number of UpgradeReq accesses(hits+misses)
477system.l2c.UpgradeReq_accesses::total 10921 # number of UpgradeReq accesses(hits+misses)
478system.l2c.SCUpgradeReq_accesses::cpu0.inst 898 # number of SCUpgradeReq accesses(hits+misses)
479system.l2c.SCUpgradeReq_accesses::cpu1.inst 394 # number of SCUpgradeReq accesses(hits+misses)
480system.l2c.SCUpgradeReq_accesses::total 1292 # number of SCUpgradeReq accesses(hits+misses)
481system.l2c.ReadExReq_accesses::cpu0.inst 151106 # number of ReadExReq accesses(hits+misses)
482system.l2c.ReadExReq_accesses::cpu1.inst 98118 # number of ReadExReq accesses(hits+misses)
483system.l2c.ReadExReq_accesses::total 249224 # number of ReadExReq accesses(hits+misses)
484system.l2c.demand_accesses::cpu0.dtb.walker 22278 # number of demand (read+write) accesses
485system.l2c.demand_accesses::cpu0.itb.walker 6566 # number of demand (read+write) accesses
486system.l2c.demand_accesses::cpu0.inst 1116357 # number of demand (read+write) accesses
487system.l2c.demand_accesses::cpu1.dtb.walker 22732 # number of demand (read+write) accesses
488system.l2c.demand_accesses::cpu1.itb.walker 5189 # number of demand (read+write) accesses
489system.l2c.demand_accesses::cpu1.inst 1067600 # number of demand (read+write) accesses
490system.l2c.demand_accesses::total 2240722 # number of demand (read+write) accesses
491system.l2c.overall_accesses::cpu0.dtb.walker 22278 # number of overall (read+write) accesses
492system.l2c.overall_accesses::cpu0.itb.walker 6566 # number of overall (read+write) accesses
493system.l2c.overall_accesses::cpu0.inst 1116357 # number of overall (read+write) accesses
494system.l2c.overall_accesses::cpu1.dtb.walker 22732 # number of overall (read+write) accesses
495system.l2c.overall_accesses::cpu1.itb.walker 5189 # number of overall (read+write) accesses
496system.l2c.overall_accesses::cpu1.inst 1067600 # number of overall (read+write) accesses
497system.l2c.overall_accesses::total 2240722 # number of overall (read+write) accesses
498system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for ReadReq accesses
499system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000305 # miss rate for ReadReq accesses
500system.l2c.ReadReq_miss_rate::cpu0.inst 0.016687 # miss rate for ReadReq accesses
501system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for ReadReq accesses
502system.l2c.ReadReq_miss_rate::cpu1.inst 0.010111 # miss rate for ReadReq accesses
503system.l2c.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses
504system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.836448 # miss rate for UpgradeReq accesses
505system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.798349 # miss rate for UpgradeReq accesses
506system.l2c.UpgradeReq_miss_rate::total 0.818698 # miss rate for UpgradeReq accesses
507system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.773942 # miss rate for SCUpgradeReq accesses
508system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.761421 # miss rate for SCUpgradeReq accesses
509system.l2c.SCUpgradeReq_miss_rate::total 0.770124 # miss rate for SCUpgradeReq accesses
510system.l2c.ReadExReq_miss_rate::cpu0.inst 0.611822 # miss rate for ReadExReq accesses
511system.l2c.ReadExReq_miss_rate::cpu1.inst 0.483194 # miss rate for ReadExReq accesses
512system.l2c.ReadExReq_miss_rate::total 0.561182 # miss rate for ReadExReq accesses
513system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for demand accesses
514system.l2c.demand_miss_rate::cpu0.itb.walker 0.000305 # miss rate for demand accesses
515system.l2c.demand_miss_rate::cpu0.inst 0.097242 # miss rate for demand accesses
516system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for demand accesses
517system.l2c.demand_miss_rate::cpu1.inst 0.053589 # miss rate for demand accesses
518system.l2c.demand_miss_rate::total 0.073988 # miss rate for demand accesses
519system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for overall accesses
520system.l2c.overall_miss_rate::cpu0.itb.walker 0.000305 # miss rate for overall accesses
521system.l2c.overall_miss_rate::cpu0.inst 0.097242 # miss rate for overall accesses
522system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for overall accesses
523system.l2c.overall_miss_rate::cpu1.inst 0.053589 # miss rate for overall accesses
524system.l2c.overall_miss_rate::total 0.073988 # miss rate for overall accesses
525system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average ReadReq miss latency
526system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency
527system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70406.981437 # average ReadReq miss latency
528system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average ReadReq miss latency
529system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74776.525199 # average ReadReq miss latency
530system.l2c.ReadReq_avg_miss_latency::total 72069.061946 # average ReadReq miss latency
531system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1670.249231 # average UpgradeReq miss latency
532system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 3352.884047 # average UpgradeReq miss latency
533system.l2c.UpgradeReq_avg_miss_latency::total 2434.689744 # average UpgradeReq miss latency
534system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 1000.676259 # average SCUpgradeReq miss latency
535system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 7273.020000 # average SCUpgradeReq miss latency
536system.l2c.SCUpgradeReq_avg_miss_latency::total 2891.835176 # average SCUpgradeReq miss latency
537system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 69232.056366 # average ReadExReq miss latency
538system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 71404.852120 # average ReadExReq miss latency
539system.l2c.ReadExReq_avg_miss_latency::total 69968.594666 # average ReadExReq miss latency
540system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency
541system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
542system.l2c.demand_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency
543system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency
544system.l2c.demand_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency
545system.l2c.demand_avg_miss_latency::total 70297.070621 # average overall miss latency
546system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency
547system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
548system.l2c.overall_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency
549system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency
550system.l2c.overall_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency
551system.l2c.overall_avg_miss_latency::total 70297.070621 # average overall miss latency
552system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
553system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
554system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
555system.l2c.blocked::no_targets 0 # number of cycles access was blocked
556system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
557system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
558system.l2c.fast_writes 0 # number of fast writes performed
559system.l2c.cache_copies 0 # number of cache copies performed
560system.l2c.writebacks::writebacks 66893 # number of writebacks
561system.l2c.writebacks::total 66893 # number of writebacks
562system.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits
563system.l2c.ReadReq_mshr_hits::cpu1.inst 22 # number of ReadReq MSHR hits
564system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
565system.l2c.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits
566system.l2c.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits
567system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
568system.l2c.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits
569system.l2c.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits
570system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits
571system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadReq MSHR misses
572system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
573system.l2c.ReadReq_mshr_misses::cpu0.inst 16058 # number of ReadReq MSHR misses
574system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses
575system.l2c.ReadReq_mshr_misses::cpu1.inst 9780 # number of ReadReq MSHR misses
576system.l2c.ReadReq_mshr_misses::total 25855 # number of ReadReq MSHR misses
577system.l2c.UpgradeReq_mshr_misses::cpu0.inst 4879 # number of UpgradeReq MSHR misses
578system.l2c.UpgradeReq_mshr_misses::cpu1.inst 4062 # number of UpgradeReq MSHR misses
579system.l2c.UpgradeReq_mshr_misses::total 8941 # number of UpgradeReq MSHR misses
580system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 695 # number of SCUpgradeReq MSHR misses
581system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 300 # number of SCUpgradeReq MSHR misses
582system.l2c.SCUpgradeReq_mshr_misses::total 995 # number of SCUpgradeReq MSHR misses
583system.l2c.ReadExReq_mshr_misses::cpu0.inst 92450 # number of ReadExReq MSHR misses
584system.l2c.ReadExReq_mshr_misses::cpu1.inst 47410 # number of ReadExReq MSHR misses
585system.l2c.ReadExReq_mshr_misses::total 139860 # number of ReadExReq MSHR misses
586system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses
587system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
588system.l2c.demand_mshr_misses::cpu0.inst 108508 # number of demand (read+write) MSHR misses
589system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses
590system.l2c.demand_mshr_misses::cpu1.inst 57190 # number of demand (read+write) MSHR misses
591system.l2c.demand_mshr_misses::total 165715 # number of demand (read+write) MSHR misses
592system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses
593system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
594system.l2c.overall_mshr_misses::cpu0.inst 108508 # number of overall MSHR misses
595system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses
596system.l2c.overall_mshr_misses::cpu1.inst 57190 # number of overall MSHR misses
597system.l2c.overall_mshr_misses::total 165715 # number of overall MSHR misses
598system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 518500 # number of ReadReq MSHR miss cycles
599system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles
600system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 929504000 # number of ReadReq MSHR miss cycles
601system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603750 # number of ReadReq MSHR miss cycles
602system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 609332000 # number of ReadReq MSHR miss cycles
603system.l2c.ReadReq_mshr_miss_latency::total 1540083250 # number of ReadReq MSHR miss cycles
604system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 48881350 # number of UpgradeReq MSHR miss cycles
605system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 40684546 # number of UpgradeReq MSHR miss cycles
606system.l2c.UpgradeReq_mshr_miss_latency::total 89565896 # number of UpgradeReq MSHR miss cycles
607system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6993689 # number of SCUpgradeReq MSHR miss cycles
608system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 3002299 # number of SCUpgradeReq MSHR miss cycles
609system.l2c.SCUpgradeReq_mshr_miss_latency::total 9995988 # number of SCUpgradeReq MSHR miss cycles
610system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5227989883 # number of ReadExReq MSHR miss cycles
611system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 2775821957 # number of ReadExReq MSHR miss cycles
612system.l2c.ReadExReq_mshr_miss_latency::total 8003811840 # number of ReadExReq MSHR miss cycles
613system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 518500 # number of demand (read+write) MSHR miss cycles
614system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
615system.l2c.demand_mshr_miss_latency::cpu0.inst 6157493883 # number of demand (read+write) MSHR miss cycles
616system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 603750 # number of demand (read+write) MSHR miss cycles
617system.l2c.demand_mshr_miss_latency::cpu1.inst 3385153957 # number of demand (read+write) MSHR miss cycles
618system.l2c.demand_mshr_miss_latency::total 9543895090 # number of demand (read+write) MSHR miss cycles
619system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 518500 # number of overall MSHR miss cycles
620system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles
621system.l2c.overall_mshr_miss_latency::cpu0.inst 6157493883 # number of overall MSHR miss cycles
622system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 603750 # number of overall MSHR miss cycles
623system.l2c.overall_mshr_miss_latency::cpu1.inst 3385153957 # number of overall MSHR miss cycles
624system.l2c.overall_mshr_miss_latency::total 9543895090 # number of overall MSHR miss cycles
625system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156449029487 # number of ReadReq MSHR uncacheable cycles
626system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10979297747 # number of ReadReq MSHR uncacheable cycles
627system.l2c.ReadReq_mshr_uncacheable_latency::total 167428327234 # number of ReadReq MSHR uncacheable cycles
628system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1364347483 # number of WriteReq MSHR uncacheable cycles
629system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15414886347 # number of WriteReq MSHR uncacheable cycles
630system.l2c.WriteReq_mshr_uncacheable_latency::total 16779233830 # number of WriteReq MSHR uncacheable cycles
631system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157813376970 # number of overall MSHR uncacheable cycles
632system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26394184094 # number of overall MSHR uncacheable cycles
633system.l2c.overall_mshr_uncacheable_latency::total 184207561064 # number of overall MSHR uncacheable cycles
634system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for ReadReq accesses
635system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for ReadReq accesses
636system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016636 # mshr miss rate for ReadReq accesses
637system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses
638system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010088 # mshr miss rate for ReadReq accesses
639system.l2c.ReadReq_mshr_miss_rate::total 0.012983 # mshr miss rate for ReadReq accesses
640system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.836448 # mshr miss rate for UpgradeReq accesses
641system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.798349 # mshr miss rate for UpgradeReq accesses
642system.l2c.UpgradeReq_mshr_miss_rate::total 0.818698 # mshr miss rate for UpgradeReq accesses
643system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.773942 # mshr miss rate for SCUpgradeReq accesses
644system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.761421 # mshr miss rate for SCUpgradeReq accesses
645system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770124 # mshr miss rate for SCUpgradeReq accesses
646system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.611822 # mshr miss rate for ReadExReq accesses
647system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.483194 # mshr miss rate for ReadExReq accesses
648system.l2c.ReadExReq_mshr_miss_rate::total 0.561182 # mshr miss rate for ReadExReq accesses
649system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for demand accesses
650system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for demand accesses
651system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for demand accesses
652system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for demand accesses
653system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for demand accesses
654system.l2c.demand_mshr_miss_rate::total 0.073956 # mshr miss rate for demand accesses
655system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for overall accesses
656system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for overall accesses
657system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for overall accesses
658system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for overall accesses
659system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for overall accesses
660system.l2c.overall_mshr_miss_rate::total 0.073956 # mshr miss rate for overall accesses
661system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average ReadReq mshr miss latency
662system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
663system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57884.169884 # average ReadReq mshr miss latency
664system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency
665system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62303.885481 # average ReadReq mshr miss latency
666system.l2c.ReadReq_avg_mshr_miss_latency::total 59566.167086 # average ReadReq mshr miss latency
667system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10018.723099 # average UpgradeReq mshr miss latency
668system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10015.890202 # average UpgradeReq mshr miss latency
669system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.436081 # average UpgradeReq mshr miss latency
670system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10062.861871 # average SCUpgradeReq mshr miss latency
671system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10007.663333 # average SCUpgradeReq mshr miss latency
672system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10046.219095 # average SCUpgradeReq mshr miss latency
673system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 56549.376777 # average ReadExReq mshr miss latency
674system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58549.292491 # average ReadExReq mshr miss latency
675system.l2c.ReadExReq_avg_mshr_miss_latency::total 57227.311883 # average ReadExReq mshr miss latency
676system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency
677system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
678system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency
679system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency
680system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency
681system.l2c.demand_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency
682system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency
683system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
684system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency
685system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency
686system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency
687system.l2c.overall_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency
688system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
689system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
690system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
691system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
692system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
693system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
694system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
695system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
696system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
697system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
698system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
699system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
700system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
701system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
702system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
703system.cf0.dma_write_txs 0 # Number of DMA write transactions.
704system.toL2Bus.throughput 163445997 # Throughput (bytes/s)
705system.toL2Bus.trans_dist::ReadReq 3265310 # Transaction distribution
706system.toL2Bus.trans_dist::ReadResp 3265309 # Transaction distribution
707system.toL2Bus.trans_dist::WriteReq 767823 # Transaction distribution
708system.toL2Bus.trans_dist::WriteResp 767823 # Transaction distribution
709system.toL2Bus.trans_dist::Writeback 575172 # Transaction distribution
710system.toL2Bus.trans_dist::UpgradeReq 32693 # Transaction distribution
711system.toL2Bus.trans_dist::SCUpgradeReq 17526 # Transaction distribution
712system.toL2Bus.trans_dist::UpgradeResp 50219 # Transaction distribution
713system.toL2Bus.trans_dist::ReadExReq 260531 # Transaction distribution
714system.toL2Bus.trans_dist::ReadExResp 260531 # Transaction distribution
715system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1555911 # Packet count per connected master and slave (bytes)
716system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3285118 # Packet count per connected master and slave (bytes)
717system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16087 # Packet count per connected master and slave (bytes)
718system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52607 # Packet count per connected master and slave (bytes)
719system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1583939 # Packet count per connected master and slave (bytes)
720system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2567940 # Packet count per connected master and slave (bytes)
721system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13476 # Packet count per connected master and slave (bytes)
722system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 53641 # Packet count per connected master and slave (bytes)
723system.toL2Bus.pkt_count::total 9128719 # Packet count per connected master and slave (bytes)
724system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49766528 # Cumulative packet size per connected master and slave (bytes)
725system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43750900 # Cumulative packet size per connected master and slave (bytes)
726system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26264 # Cumulative packet size per connected master and slave (bytes)
727system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 89112 # Cumulative packet size per connected master and slave (bytes)
728system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 50661248 # Cumulative packet size per connected master and slave (bytes)
729system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38001760 # Cumulative packet size per connected master and slave (bytes)
730system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20756 # Cumulative packet size per connected master and slave (bytes)
731system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 90928 # Cumulative packet size per connected master and slave (bytes)
732system.toL2Bus.tot_pkt_size::total 182407496 # Cumulative packet size per connected master and slave (bytes)
733system.toL2Bus.data_through_bus 182407496 # Total data (bytes)
734system.toL2Bus.snoop_data_through_bus 4820708 # Total snoop data (bytes)
735system.toL2Bus.reqLayer0.occupancy 5144551012 # Layer occupancy (ticks)
736system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
737system.toL2Bus.respLayer0.occupancy 3505001405 # Layer occupancy (ticks)
738system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
739system.toL2Bus.respLayer1.occupancy 2792622052 # Layer occupancy (ticks)
740system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
741system.toL2Bus.respLayer2.occupancy 9525491 # Layer occupancy (ticks)
742system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
743system.toL2Bus.respLayer3.occupancy 30330496 # Layer occupancy (ticks)
744system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
745system.toL2Bus.respLayer6.occupancy 3566573438 # Layer occupancy (ticks)
746system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%)
747system.toL2Bus.respLayer7.occupancy 1934335367 # Layer occupancy (ticks)
748system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
749system.toL2Bus.respLayer8.occupancy 8290992 # Layer occupancy (ticks)
750system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
751system.toL2Bus.respLayer9.occupancy 30912744 # Layer occupancy (ticks)
752system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
753system.iobus.throughput 46024799 # Throughput (bytes/s)
754system.iobus.trans_dist::ReadReq 7474816 # Transaction distribution
755system.iobus.trans_dist::ReadResp 7474816 # Transaction distribution
756system.iobus.trans_dist::WriteReq 7966 # Transaction distribution
757system.iobus.trans_dist::WriteResp 7966 # Transaction distribution
758system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes)
759system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8038 # Packet count per connected master and slave (bytes)
760system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
761system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes)
762system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
763system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
764system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 498 # Packet count per connected master and slave (bytes)
765system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
766system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
767system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
768system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
769system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
770system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
771system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
772system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
773system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
774system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
775system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
776system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
777system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
778system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
779system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
780system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
781system.iobus.pkt_count_system.bridge.master::total 2382652 # Packet count per connected master and slave (bytes)
782system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes)
783system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes)
784system.iobus.pkt_count::total 14965564 # Packet count per connected master and slave (bytes)
785system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes)
786system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16076 # Cumulative packet size per connected master and slave (bytes)
787system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
788system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes)
789system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
790system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
791system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 273 # Cumulative packet size per connected master and slave (bytes)
792system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
793system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
794system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
795system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
796system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
797system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
798system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
799system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
800system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
801system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
802system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
803system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
804system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
805system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
806system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
807system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
808system.iobus.tot_pkt_size_system.bridge.master::total 2389988 # Cumulative packet size per connected master and slave (bytes)
809system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes)
810system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes)
811system.iobus.tot_pkt_size::total 52721636 # Cumulative packet size per connected master and slave (bytes)
812system.iobus.data_through_bus 52721636 # Total data (bytes)
813system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks)
814system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
815system.iobus.reqLayer1.occupancy 4025000 # Layer occupancy (ticks)
816system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
817system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
818system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
819system.iobus.reqLayer3.occupancy 372000 # Layer occupancy (ticks)
820system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
821system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
822system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
823system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
824system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
825system.iobus.reqLayer6.occupancy 299000 # Layer occupancy (ticks)
826system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
827system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
828system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
829system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
830system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
831system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
832system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
833system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
834system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
835system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
836system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)

--- 14 unchanged lines hidden (view full) ---

851system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
852system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
853system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
854system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
855system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
856system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
857system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
858system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
859system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks)
860system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
861system.iobus.respLayer0.occupancy 2374686000 # Layer occupancy (ticks)
862system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
863system.iobus.respLayer1.occupancy 15862213002 # Layer occupancy (ticks)
864system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
865system.cpu0.branchPred.lookups 6670288 # Number of BP lookups
866system.cpu0.branchPred.condPredicted 4756995 # Number of conditional branches predicted
867system.cpu0.branchPred.condIncorrect 639495 # Number of conditional branches incorrect
868system.cpu0.branchPred.BTBLookups 4605007 # Number of BTB lookups
869system.cpu0.branchPred.BTBHits 3289427 # Number of BTB hits
870system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
871system.cpu0.branchPred.BTBHitPct 71.431531 # BTB Hit Percentage
872system.cpu0.branchPred.usedRAS 870926 # Number of times the RAS was used to get a target.
873system.cpu0.branchPred.RASInCorrect 69312 # Number of incorrect RAS predictions.
874system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
875system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
876system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
877system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
878system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
879system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
880system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
881system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

889system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
890system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
891system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
892system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
893system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
894system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
895system.cpu0.dtb.inst_hits 0 # ITB inst hits
896system.cpu0.dtb.inst_misses 0 # ITB inst misses
897system.cpu0.dtb.read_hits 7193152 # DTB read hits
898system.cpu0.dtb.read_misses 17493 # DTB read misses
899system.cpu0.dtb.write_hits 6058571 # DTB write hits
900system.cpu0.dtb.write_misses 1416 # DTB write misses
901system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
902system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
903system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
904system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
905system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB
906system.cpu0.dtb.align_faults 1486 # Number of TLB faults due to alignment restrictions
907system.cpu0.dtb.prefetch_faults 207 # Number of TLB faults due to prefetch
908system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
909system.cpu0.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions
910system.cpu0.dtb.read_accesses 7210645 # DTB read accesses
911system.cpu0.dtb.write_accesses 6059987 # DTB write accesses
912system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
913system.cpu0.dtb.hits 13251723 # DTB hits
914system.cpu0.dtb.misses 18909 # DTB misses
915system.cpu0.dtb.accesses 13270632 # DTB accesses
916system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
917system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
918system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
919system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
920system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
921system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
922system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
923system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

929system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
930system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
931system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
932system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
933system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
934system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
935system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
936system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
937system.cpu0.itb.inst_hits 12268451 # ITB inst hits
938system.cpu0.itb.inst_misses 4809 # ITB inst misses
939system.cpu0.itb.read_hits 0 # DTB read hits
940system.cpu0.itb.read_misses 0 # DTB read misses
941system.cpu0.itb.write_hits 0 # DTB write hits
942system.cpu0.itb.write_misses 0 # DTB write misses
943system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
944system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
945system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
946system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
947system.cpu0.itb.flush_entries 1294 # Number of entries that have been flushed from TLB
948system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
949system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
950system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
951system.cpu0.itb.perms_faults 2809 # Number of TLB faults due to permissions restrictions
952system.cpu0.itb.read_accesses 0 # DTB read accesses
953system.cpu0.itb.write_accesses 0 # DTB write accesses
954system.cpu0.itb.inst_accesses 12273260 # ITB inst accesses
955system.cpu0.itb.hits 12268451 # DTB hits
956system.cpu0.itb.misses 4809 # DTB misses
957system.cpu0.itb.accesses 12273260 # DTB accesses
958system.cpu0.numCycles 431172708 # number of cpu cycles simulated
959system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
960system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
961system.cpu0.committedInsts 29878954 # Number of instructions committed
962system.cpu0.committedOps 36403873 # Number of ops (including micro ops) committed
963system.cpu0.discardedOps 1704985 # Number of ops (including micro ops) which were discarded before commit
964system.cpu0.numFetchSuspends 39450 # Number of times Execute suspended instruction fetching
965system.cpu0.quiesceCycles 1859905219 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
966system.cpu0.cpi 14.430649 # CPI: cycles per instruction
967system.cpu0.ipc 0.069297 # IPC: instructions per cycle
968system.cpu0.kern.inst.arm 0 # number of arm instructions executed
969system.cpu0.kern.inst.quiesce 50317 # number of quiesce instructions executed
970system.cpu0.tickCycles 351703818 # Number of cycles that the object actually ticked
971system.cpu0.idleCycles 79468890 # Total number of cycles that the object has spent stopped
972system.cpu0.icache.tags.replacements 775463 # number of replacements
973system.cpu0.icache.tags.tagsinuse 510.771777 # Cycle average of tags in use
974system.cpu0.icache.tags.total_refs 11489502 # Total number of references to valid blocks.
975system.cpu0.icache.tags.sampled_refs 775975 # Sample count of references to valid blocks.
976system.cpu0.icache.tags.avg_refs 14.806536 # Average number of references to valid blocks.
977system.cpu0.icache.tags.warmup_cycle 10202297000 # Cycle when the warmup percentage was hit.
978system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.771777 # Average occupied blocks per requestor
979system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997601 # Average percentage of cache occupancy
980system.cpu0.icache.tags.occ_percent::total 0.997601 # Average percentage of cache occupancy
981system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
982system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id
983system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
984system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
985system.cpu0.icache.tags.tag_accesses 13041458 # Number of tag accesses
986system.cpu0.icache.tags.data_accesses 13041458 # Number of data accesses
987system.cpu0.icache.ReadReq_hits::cpu0.inst 11489502 # number of ReadReq hits
988system.cpu0.icache.ReadReq_hits::total 11489502 # number of ReadReq hits
989system.cpu0.icache.demand_hits::cpu0.inst 11489502 # number of demand (read+write) hits
990system.cpu0.icache.demand_hits::total 11489502 # number of demand (read+write) hits
991system.cpu0.icache.overall_hits::cpu0.inst 11489502 # number of overall hits
992system.cpu0.icache.overall_hits::total 11489502 # number of overall hits
993system.cpu0.icache.ReadReq_misses::cpu0.inst 775978 # number of ReadReq misses
994system.cpu0.icache.ReadReq_misses::total 775978 # number of ReadReq misses
995system.cpu0.icache.demand_misses::cpu0.inst 775978 # number of demand (read+write) misses
996system.cpu0.icache.demand_misses::total 775978 # number of demand (read+write) misses
997system.cpu0.icache.overall_misses::cpu0.inst 775978 # number of overall misses
998system.cpu0.icache.overall_misses::total 775978 # number of overall misses
999system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10689826155 # number of ReadReq miss cycles
1000system.cpu0.icache.ReadReq_miss_latency::total 10689826155 # number of ReadReq miss cycles
1001system.cpu0.icache.demand_miss_latency::cpu0.inst 10689826155 # number of demand (read+write) miss cycles
1002system.cpu0.icache.demand_miss_latency::total 10689826155 # number of demand (read+write) miss cycles
1003system.cpu0.icache.overall_miss_latency::cpu0.inst 10689826155 # number of overall miss cycles
1004system.cpu0.icache.overall_miss_latency::total 10689826155 # number of overall miss cycles
1005system.cpu0.icache.ReadReq_accesses::cpu0.inst 12265480 # number of ReadReq accesses(hits+misses)
1006system.cpu0.icache.ReadReq_accesses::total 12265480 # number of ReadReq accesses(hits+misses)
1007system.cpu0.icache.demand_accesses::cpu0.inst 12265480 # number of demand (read+write) accesses
1008system.cpu0.icache.demand_accesses::total 12265480 # number of demand (read+write) accesses
1009system.cpu0.icache.overall_accesses::cpu0.inst 12265480 # number of overall (read+write) accesses
1010system.cpu0.icache.overall_accesses::total 12265480 # number of overall (read+write) accesses
1011system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.063265 # miss rate for ReadReq accesses
1012system.cpu0.icache.ReadReq_miss_rate::total 0.063265 # miss rate for ReadReq accesses
1013system.cpu0.icache.demand_miss_rate::cpu0.inst 0.063265 # miss rate for demand accesses
1014system.cpu0.icache.demand_miss_rate::total 0.063265 # miss rate for demand accesses
1015system.cpu0.icache.overall_miss_rate::cpu0.inst 0.063265 # miss rate for overall accesses
1016system.cpu0.icache.overall_miss_rate::total 0.063265 # miss rate for overall accesses
1017system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13775.939724 # average ReadReq miss latency
1018system.cpu0.icache.ReadReq_avg_miss_latency::total 13775.939724 # average ReadReq miss latency
1019system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency
1020system.cpu0.icache.demand_avg_miss_latency::total 13775.939724 # average overall miss latency
1021system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency
1022system.cpu0.icache.overall_avg_miss_latency::total 13775.939724 # average overall miss latency
1023system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1024system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1025system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1026system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1027system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1028system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1029system.cpu0.icache.fast_writes 0 # number of fast writes performed
1030system.cpu0.icache.cache_copies 0 # number of cache copies performed
1031system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 775978 # number of ReadReq MSHR misses
1032system.cpu0.icache.ReadReq_mshr_misses::total 775978 # number of ReadReq MSHR misses
1033system.cpu0.icache.demand_mshr_misses::cpu0.inst 775978 # number of demand (read+write) MSHR misses
1034system.cpu0.icache.demand_mshr_misses::total 775978 # number of demand (read+write) MSHR misses
1035system.cpu0.icache.overall_mshr_misses::cpu0.inst 775978 # number of overall MSHR misses
1036system.cpu0.icache.overall_mshr_misses::total 775978 # number of overall MSHR misses
1037system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9133730845 # number of ReadReq MSHR miss cycles
1038system.cpu0.icache.ReadReq_mshr_miss_latency::total 9133730845 # number of ReadReq MSHR miss cycles
1039system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9133730845 # number of demand (read+write) MSHR miss cycles
1040system.cpu0.icache.demand_mshr_miss_latency::total 9133730845 # number of demand (read+write) MSHR miss cycles
1041system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9133730845 # number of overall MSHR miss cycles
1042system.cpu0.icache.overall_mshr_miss_latency::total 9133730845 # number of overall MSHR miss cycles
1043system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171407250 # number of ReadReq MSHR uncacheable cycles
1044system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171407250 # number of ReadReq MSHR uncacheable cycles
1045system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171407250 # number of overall MSHR uncacheable cycles
1046system.cpu0.icache.overall_mshr_uncacheable_latency::total 171407250 # number of overall MSHR uncacheable cycles
1047system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for ReadReq accesses
1048system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.063265 # mshr miss rate for ReadReq accesses
1049system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for demand accesses
1050system.cpu0.icache.demand_mshr_miss_rate::total 0.063265 # mshr miss rate for demand accesses
1051system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for overall accesses
1052system.cpu0.icache.overall_mshr_miss_rate::total 0.063265 # mshr miss rate for overall accesses
1053system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average ReadReq mshr miss latency
1054system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11770.605410 # average ReadReq mshr miss latency
1055system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency
1056system.cpu0.icache.demand_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency
1057system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency
1058system.cpu0.icache.overall_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency
1059system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1060system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1061system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1062system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1063system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1064system.cpu0.dcache.tags.replacements 331184 # number of replacements
1065system.cpu0.dcache.tags.tagsinuse 495.308279 # Cycle average of tags in use
1066system.cpu0.dcache.tags.total_refs 11419092 # Total number of references to valid blocks.
1067system.cpu0.dcache.tags.sampled_refs 331547 # Sample count of references to valid blocks.
1068system.cpu0.dcache.tags.avg_refs 34.441850 # Average number of references to valid blocks.
1069system.cpu0.dcache.tags.warmup_cycle 235572250 # Cycle when the warmup percentage was hit.
1070system.cpu0.dcache.tags.occ_blocks::cpu0.inst 495.308279 # Average occupied blocks per requestor
1071system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.967399 # Average percentage of cache occupancy
1072system.cpu0.dcache.tags.occ_percent::total 0.967399 # Average percentage of cache occupancy
1073system.cpu0.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id
1074system.cpu0.dcache.tags.age_task_id_blocks_1024::2 363 # Occupied blocks per task id
1075system.cpu0.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id
1076system.cpu0.dcache.tags.tag_accesses 48281639 # Number of tag accesses
1077system.cpu0.dcache.tags.data_accesses 48281639 # Number of data accesses
1078system.cpu0.dcache.ReadReq_hits::cpu0.inst 5587990 # number of ReadReq hits
1079system.cpu0.dcache.ReadReq_hits::total 5587990 # number of ReadReq hits
1080system.cpu0.dcache.WriteReq_hits::cpu0.inst 5501455 # number of WriteReq hits
1081system.cpu0.dcache.WriteReq_hits::total 5501455 # number of WriteReq hits
1082system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152609 # number of LoadLockedReq hits
1083system.cpu0.dcache.LoadLockedReq_hits::total 152609 # number of LoadLockedReq hits
1084system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 153662 # number of StoreCondReq hits
1085system.cpu0.dcache.StoreCondReq_hits::total 153662 # number of StoreCondReq hits
1086system.cpu0.dcache.demand_hits::cpu0.inst 11089445 # number of demand (read+write) hits
1087system.cpu0.dcache.demand_hits::total 11089445 # number of demand (read+write) hits
1088system.cpu0.dcache.overall_hits::cpu0.inst 11089445 # number of overall hits
1089system.cpu0.dcache.overall_hits::total 11089445 # number of overall hits
1090system.cpu0.dcache.ReadReq_misses::cpu0.inst 255115 # number of ReadReq misses
1091system.cpu0.dcache.ReadReq_misses::total 255115 # number of ReadReq misses
1092system.cpu0.dcache.WriteReq_misses::cpu0.inst 311930 # number of WriteReq misses
1093system.cpu0.dcache.WriteReq_misses::total 311930 # number of WriteReq misses
1094system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 8548 # number of LoadLockedReq misses
1095system.cpu0.dcache.LoadLockedReq_misses::total 8548 # number of LoadLockedReq misses
1096system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 7439 # number of StoreCondReq misses
1097system.cpu0.dcache.StoreCondReq_misses::total 7439 # number of StoreCondReq misses
1098system.cpu0.dcache.demand_misses::cpu0.inst 567045 # number of demand (read+write) misses
1099system.cpu0.dcache.demand_misses::total 567045 # number of demand (read+write) misses
1100system.cpu0.dcache.overall_misses::cpu0.inst 567045 # number of overall misses
1101system.cpu0.dcache.overall_misses::total 567045 # number of overall misses
1102system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3832963977 # number of ReadReq miss cycles
1103system.cpu0.dcache.ReadReq_miss_latency::total 3832963977 # number of ReadReq miss cycles
1104system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15354005377 # number of WriteReq miss cycles
1105system.cpu0.dcache.WriteReq_miss_latency::total 15354005377 # number of WriteReq miss cycles
1106system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 89150250 # number of LoadLockedReq miss cycles
1107system.cpu0.dcache.LoadLockedReq_miss_latency::total 89150250 # number of LoadLockedReq miss cycles
1108system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47371188 # number of StoreCondReq miss cycles
1109system.cpu0.dcache.StoreCondReq_miss_latency::total 47371188 # number of StoreCondReq miss cycles
1110system.cpu0.dcache.demand_miss_latency::cpu0.inst 19186969354 # number of demand (read+write) miss cycles
1111system.cpu0.dcache.demand_miss_latency::total 19186969354 # number of demand (read+write) miss cycles
1112system.cpu0.dcache.overall_miss_latency::cpu0.inst 19186969354 # number of overall miss cycles
1113system.cpu0.dcache.overall_miss_latency::total 19186969354 # number of overall miss cycles
1114system.cpu0.dcache.ReadReq_accesses::cpu0.inst 5843105 # number of ReadReq accesses(hits+misses)
1115system.cpu0.dcache.ReadReq_accesses::total 5843105 # number of ReadReq accesses(hits+misses)
1116system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5813385 # number of WriteReq accesses(hits+misses)
1117system.cpu0.dcache.WriteReq_accesses::total 5813385 # number of WriteReq accesses(hits+misses)
1118system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 161157 # number of LoadLockedReq accesses(hits+misses)
1119system.cpu0.dcache.LoadLockedReq_accesses::total 161157 # number of LoadLockedReq accesses(hits+misses)
1120system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 161101 # number of StoreCondReq accesses(hits+misses)
1121system.cpu0.dcache.StoreCondReq_accesses::total 161101 # number of StoreCondReq accesses(hits+misses)
1122system.cpu0.dcache.demand_accesses::cpu0.inst 11656490 # number of demand (read+write) accesses
1123system.cpu0.dcache.demand_accesses::total 11656490 # number of demand (read+write) accesses
1124system.cpu0.dcache.overall_accesses::cpu0.inst 11656490 # number of overall (read+write) accesses
1125system.cpu0.dcache.overall_accesses::total 11656490 # number of overall (read+write) accesses
1126system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.043661 # miss rate for ReadReq accesses
1127system.cpu0.dcache.ReadReq_miss_rate::total 0.043661 # miss rate for ReadReq accesses
1128system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.053657 # miss rate for WriteReq accesses
1129system.cpu0.dcache.WriteReq_miss_rate::total 0.053657 # miss rate for WriteReq accesses
1130system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.053041 # miss rate for LoadLockedReq accesses
1131system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053041 # miss rate for LoadLockedReq accesses
1132system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046176 # miss rate for StoreCondReq accesses
1133system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046176 # miss rate for StoreCondReq accesses
1134system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.048646 # miss rate for demand accesses
1135system.cpu0.dcache.demand_miss_rate::total 0.048646 # miss rate for demand accesses
1136system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.048646 # miss rate for overall accesses
1137system.cpu0.dcache.overall_miss_rate::total 0.048646 # miss rate for overall accesses
1138system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15024.455547 # average ReadReq miss latency
1139system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.455547 # average ReadReq miss latency
1140system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49222.599227 # average WriteReq miss latency
1141system.cpu0.dcache.WriteReq_avg_miss_latency::total 49222.599227 # average WriteReq miss latency
1142system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10429.369443 # average LoadLockedReq miss latency
1143system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10429.369443 # average LoadLockedReq miss latency
1144system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6367.951069 # average StoreCondReq miss latency
1145system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6367.951069 # average StoreCondReq miss latency
1146system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency
1147system.cpu0.dcache.demand_avg_miss_latency::total 33836.766666 # average overall miss latency
1148system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency
1149system.cpu0.dcache.overall_avg_miss_latency::total 33836.766666 # average overall miss latency
1150system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1151system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1152system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1153system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1154system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1155system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1156system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1157system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1158system.cpu0.dcache.writebacks::writebacks 307170 # number of writebacks
1159system.cpu0.dcache.writebacks::total 307170 # number of writebacks
1160system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 50178 # number of ReadReq MSHR hits
1161system.cpu0.dcache.ReadReq_mshr_hits::total 50178 # number of ReadReq MSHR hits
1162system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 144238 # number of WriteReq MSHR hits
1163system.cpu0.dcache.WriteReq_mshr_hits::total 144238 # number of WriteReq MSHR hits
1164system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 22 # number of LoadLockedReq MSHR hits
1165system.cpu0.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
1166system.cpu0.dcache.demand_mshr_hits::cpu0.inst 194416 # number of demand (read+write) MSHR hits
1167system.cpu0.dcache.demand_mshr_hits::total 194416 # number of demand (read+write) MSHR hits
1168system.cpu0.dcache.overall_mshr_hits::cpu0.inst 194416 # number of overall MSHR hits
1169system.cpu0.dcache.overall_mshr_hits::total 194416 # number of overall MSHR hits
1170system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 204937 # number of ReadReq MSHR misses
1171system.cpu0.dcache.ReadReq_mshr_misses::total 204937 # number of ReadReq MSHR misses
1172system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167692 # number of WriteReq MSHR misses
1173system.cpu0.dcache.WriteReq_mshr_misses::total 167692 # number of WriteReq MSHR misses
1174system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8526 # number of LoadLockedReq MSHR misses
1175system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses
1176system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7439 # number of StoreCondReq MSHR misses
1177system.cpu0.dcache.StoreCondReq_mshr_misses::total 7439 # number of StoreCondReq MSHR misses
1178system.cpu0.dcache.demand_mshr_misses::cpu0.inst 372629 # number of demand (read+write) MSHR misses
1179system.cpu0.dcache.demand_mshr_misses::total 372629 # number of demand (read+write) MSHR misses
1180system.cpu0.dcache.overall_mshr_misses::cpu0.inst 372629 # number of overall MSHR misses
1181system.cpu0.dcache.overall_mshr_misses::total 372629 # number of overall MSHR misses
1182system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2523643558 # number of ReadReq MSHR miss cycles
1183system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2523643558 # number of ReadReq MSHR miss cycles
1184system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7293302576 # number of WriteReq MSHR miss cycles
1185system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7293302576 # number of WriteReq MSHR miss cycles
1186system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71695750 # number of LoadLockedReq MSHR miss cycles
1187system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71695750 # number of LoadLockedReq MSHR miss cycles
1188system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32490812 # number of StoreCondReq MSHR miss cycles
1189system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32490812 # number of StoreCondReq MSHR miss cycles
1190system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9816946134 # number of demand (read+write) MSHR miss cycles
1191system.cpu0.dcache.demand_mshr_miss_latency::total 9816946134 # number of demand (read+write) MSHR miss cycles
1192system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9816946134 # number of overall MSHR miss cycles
1193system.cpu0.dcache.overall_mshr_miss_latency::total 9816946134 # number of overall MSHR miss cycles
1194system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170796523752 # number of ReadReq MSHR uncacheable cycles
1195system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170796523752 # number of ReadReq MSHR uncacheable cycles
1196system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513122000 # number of WriteReq MSHR uncacheable cycles
1197system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513122000 # number of WriteReq MSHR uncacheable cycles
1198system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172309645752 # number of overall MSHR uncacheable cycles
1199system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172309645752 # number of overall MSHR uncacheable cycles
1200system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.035073 # mshr miss rate for ReadReq accesses
1201system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035073 # mshr miss rate for ReadReq accesses
1202system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028846 # mshr miss rate for WriteReq accesses
1203system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028846 # mshr miss rate for WriteReq accesses
1204system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.052905 # mshr miss rate for LoadLockedReq accesses
1205system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.052905 # mshr miss rate for LoadLockedReq accesses
1206system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046176 # mshr miss rate for StoreCondReq accesses
1207system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046176 # mshr miss rate for StoreCondReq accesses
1208system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for demand accesses
1209system.cpu0.dcache.demand_mshr_miss_rate::total 0.031968 # mshr miss rate for demand accesses
1210system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for overall accesses
1211system.cpu0.dcache.overall_mshr_miss_rate::total 0.031968 # mshr miss rate for overall accesses
1212system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12314.240757 # average ReadReq mshr miss latency
1213system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12314.240757 # average ReadReq mshr miss latency
1214system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 43492.251127 # average WriteReq mshr miss latency
1215system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43492.251127 # average WriteReq mshr miss latency
1216system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8409.072250 # average LoadLockedReq mshr miss latency
1217system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8409.072250 # average LoadLockedReq mshr miss latency
1218system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4367.631671 # average StoreCondReq mshr miss latency
1219system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4367.631671 # average StoreCondReq mshr miss latency
1220system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency
1221system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency
1222system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency
1223system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency
1224system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1225system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1226system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
1227system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1228system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1229system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1230system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1231system.cpu1.branchPred.lookups 6159330 # Number of BP lookups
1232system.cpu1.branchPred.condPredicted 4534606 # Number of conditional branches predicted
1233system.cpu1.branchPred.condIncorrect 426160 # Number of conditional branches incorrect
1234system.cpu1.branchPred.BTBLookups 3924244 # Number of BTB lookups
1235system.cpu1.branchPred.BTBHits 3043762 # Number of BTB hits
1236system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1237system.cpu1.branchPred.BTBHitPct 77.563016 # BTB Hit Percentage
1238system.cpu1.branchPred.usedRAS 713205 # Number of times the RAS was used to get a target.
1239system.cpu1.branchPred.RASInCorrect 64399 # Number of incorrect RAS predictions.
1240system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1241system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1242system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1243system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1244system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1245system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1246system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1247system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

1255system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1256system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1257system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1258system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1259system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1260system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1261system.cpu1.dtb.inst_hits 0 # ITB inst hits
1262system.cpu1.dtb.inst_misses 0 # ITB inst misses
1263system.cpu1.dtb.read_hits 6763605 # DTB read hits
1264system.cpu1.dtb.read_misses 17087 # DTB read misses
1265system.cpu1.dtb.write_hits 5563764 # DTB write hits
1266system.cpu1.dtb.write_misses 2456 # DTB write misses
1267system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1268system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1269system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1270system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1271system.cpu1.dtb.flush_entries 1713 # Number of entries that have been flushed from TLB
1272system.cpu1.dtb.align_faults 1918 # Number of TLB faults due to alignment restrictions
1273system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch
1274system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1275system.cpu1.dtb.perms_faults 260 # Number of TLB faults due to permissions restrictions
1276system.cpu1.dtb.read_accesses 6780692 # DTB read accesses
1277system.cpu1.dtb.write_accesses 5566220 # DTB write accesses
1278system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1279system.cpu1.dtb.hits 12327369 # DTB hits
1280system.cpu1.dtb.misses 19543 # DTB misses
1281system.cpu1.dtb.accesses 12346912 # DTB accesses
1282system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1283system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1284system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1285system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1286system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1287system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1288system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1289system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1295system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1296system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1297system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1298system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1299system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1300system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1301system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1302system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1303system.cpu1.itb.inst_hits 11206823 # ITB inst hits
1304system.cpu1.itb.inst_misses 4156 # ITB inst misses
1305system.cpu1.itb.read_hits 0 # DTB read hits
1306system.cpu1.itb.read_misses 0 # DTB read misses
1307system.cpu1.itb.write_hits 0 # DTB write hits
1308system.cpu1.itb.write_misses 0 # DTB write misses
1309system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1310system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1311system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1312system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1313system.cpu1.itb.flush_entries 1190 # Number of entries that have been flushed from TLB
1314system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1315system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1316system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1317system.cpu1.itb.perms_faults 2956 # Number of TLB faults due to permissions restrictions
1318system.cpu1.itb.read_accesses 0 # DTB read accesses
1319system.cpu1.itb.write_accesses 0 # DTB write accesses
1320system.cpu1.itb.inst_accesses 11210979 # ITB inst accesses
1321system.cpu1.itb.hits 11206823 # DTB hits
1322system.cpu1.itb.misses 4156 # DTB misses
1323system.cpu1.itb.accesses 11210979 # DTB accesses
1324system.cpu1.numCycles 147611080 # number of cpu cycles simulated
1325system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1326system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1327system.cpu1.committedInsts 31966977 # Number of instructions committed
1328system.cpu1.committedOps 38077351 # Number of ops (including micro ops) committed
1329system.cpu1.discardedOps 1608279 # Number of ops (including micro ops) which were discarded before commit
1330system.cpu1.numFetchSuspends 39953 # Number of times Execute suspended instruction fetching
1331system.cpu1.quiesceCycles 2144312243 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1332system.cpu1.cpi 4.617611 # CPI: cycles per instruction
1333system.cpu1.ipc 0.216562 # IPC: instructions per cycle
1334system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1335system.cpu1.kern.inst.quiesce 40481 # number of quiesce instructions executed
1336system.cpu1.tickCycles 117794272 # Number of cycles that the object actually ticked
1337system.cpu1.idleCycles 29816808 # Total number of cycles that the object has spent stopped
1338system.cpu1.icache.tags.replacements 791766 # number of replacements
1339system.cpu1.icache.tags.tagsinuse 480.612166 # Cycle average of tags in use
1340system.cpu1.icache.tags.total_refs 10411414 # Total number of references to valid blocks.
1341system.cpu1.icache.tags.sampled_refs 792278 # Sample count of references to valid blocks.
1342system.cpu1.icache.tags.avg_refs 13.141112 # Average number of references to valid blocks.
1343system.cpu1.icache.tags.warmup_cycle 82581306250 # Cycle when the warmup percentage was hit.
1344system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.612166 # Average occupied blocks per requestor
1345system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938696 # Average percentage of cache occupancy
1346system.cpu1.icache.tags.occ_percent::total 0.938696 # Average percentage of cache occupancy
1347system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1348system.cpu1.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
1349system.cpu1.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id
1350system.cpu1.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
1351system.cpu1.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
1352system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1353system.cpu1.icache.tags.tag_accesses 11995971 # Number of tag accesses
1354system.cpu1.icache.tags.data_accesses 11995971 # Number of data accesses
1355system.cpu1.icache.ReadReq_hits::cpu1.inst 10411414 # number of ReadReq hits
1356system.cpu1.icache.ReadReq_hits::total 10411414 # number of ReadReq hits
1357system.cpu1.icache.demand_hits::cpu1.inst 10411414 # number of demand (read+write) hits
1358system.cpu1.icache.demand_hits::total 10411414 # number of demand (read+write) hits
1359system.cpu1.icache.overall_hits::cpu1.inst 10411414 # number of overall hits
1360system.cpu1.icache.overall_hits::total 10411414 # number of overall hits
1361system.cpu1.icache.ReadReq_misses::cpu1.inst 792279 # number of ReadReq misses
1362system.cpu1.icache.ReadReq_misses::total 792279 # number of ReadReq misses
1363system.cpu1.icache.demand_misses::cpu1.inst 792279 # number of demand (read+write) misses
1364system.cpu1.icache.demand_misses::total 792279 # number of demand (read+write) misses
1365system.cpu1.icache.overall_misses::cpu1.inst 792279 # number of overall misses
1366system.cpu1.icache.overall_misses::total 792279 # number of overall misses
1367system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10606605688 # number of ReadReq miss cycles
1368system.cpu1.icache.ReadReq_miss_latency::total 10606605688 # number of ReadReq miss cycles
1369system.cpu1.icache.demand_miss_latency::cpu1.inst 10606605688 # number of demand (read+write) miss cycles
1370system.cpu1.icache.demand_miss_latency::total 10606605688 # number of demand (read+write) miss cycles
1371system.cpu1.icache.overall_miss_latency::cpu1.inst 10606605688 # number of overall miss cycles
1372system.cpu1.icache.overall_miss_latency::total 10606605688 # number of overall miss cycles
1373system.cpu1.icache.ReadReq_accesses::cpu1.inst 11203693 # number of ReadReq accesses(hits+misses)
1374system.cpu1.icache.ReadReq_accesses::total 11203693 # number of ReadReq accesses(hits+misses)
1375system.cpu1.icache.demand_accesses::cpu1.inst 11203693 # number of demand (read+write) accesses
1376system.cpu1.icache.demand_accesses::total 11203693 # number of demand (read+write) accesses
1377system.cpu1.icache.overall_accesses::cpu1.inst 11203693 # number of overall (read+write) accesses
1378system.cpu1.icache.overall_accesses::total 11203693 # number of overall (read+write) accesses
1379system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070716 # miss rate for ReadReq accesses
1380system.cpu1.icache.ReadReq_miss_rate::total 0.070716 # miss rate for ReadReq accesses
1381system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070716 # miss rate for demand accesses
1382system.cpu1.icache.demand_miss_rate::total 0.070716 # miss rate for demand accesses
1383system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070716 # miss rate for overall accesses
1384system.cpu1.icache.overall_miss_rate::total 0.070716 # miss rate for overall accesses
1385system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.462861 # average ReadReq miss latency
1386system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.462861 # average ReadReq miss latency
1387system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency
1388system.cpu1.icache.demand_avg_miss_latency::total 13387.462861 # average overall miss latency
1389system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency
1390system.cpu1.icache.overall_avg_miss_latency::total 13387.462861 # average overall miss latency
1391system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1392system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1393system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1394system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1395system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1396system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1397system.cpu1.icache.fast_writes 0 # number of fast writes performed
1398system.cpu1.icache.cache_copies 0 # number of cache copies performed
1399system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 792279 # number of ReadReq MSHR misses
1400system.cpu1.icache.ReadReq_mshr_misses::total 792279 # number of ReadReq MSHR misses
1401system.cpu1.icache.demand_mshr_misses::cpu1.inst 792279 # number of demand (read+write) MSHR misses
1402system.cpu1.icache.demand_mshr_misses::total 792279 # number of demand (read+write) MSHR misses
1403system.cpu1.icache.overall_mshr_misses::cpu1.inst 792279 # number of overall MSHR misses
1404system.cpu1.icache.overall_mshr_misses::total 792279 # number of overall MSHR misses
1405system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9020137312 # number of ReadReq MSHR miss cycles
1406system.cpu1.icache.ReadReq_mshr_miss_latency::total 9020137312 # number of ReadReq MSHR miss cycles
1407system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9020137312 # number of demand (read+write) MSHR miss cycles
1408system.cpu1.icache.demand_mshr_miss_latency::total 9020137312 # number of demand (read+write) MSHR miss cycles
1409system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9020137312 # number of overall MSHR miss cycles
1410system.cpu1.icache.overall_mshr_miss_latency::total 9020137312 # number of overall MSHR miss cycles
1411system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5771250 # number of ReadReq MSHR uncacheable cycles
1412system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5771250 # number of ReadReq MSHR uncacheable cycles
1413system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5771250 # number of overall MSHR uncacheable cycles
1414system.cpu1.icache.overall_mshr_uncacheable_latency::total 5771250 # number of overall MSHR uncacheable cycles
1415system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for ReadReq accesses
1416system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070716 # mshr miss rate for ReadReq accesses
1417system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for demand accesses
1418system.cpu1.icache.demand_mshr_miss_rate::total 0.070716 # mshr miss rate for demand accesses
1419system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for overall accesses
1420system.cpu1.icache.overall_mshr_miss_rate::total 0.070716 # mshr miss rate for overall accesses
1421system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average ReadReq mshr miss latency
1422system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11385.051619 # average ReadReq mshr miss latency
1423system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency
1424system.cpu1.icache.demand_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency
1425system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency
1426system.cpu1.icache.overall_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency
1427system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1428system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1429system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1430system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1431system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1432system.cpu1.dcache.tags.replacements 300206 # number of replacements
1433system.cpu1.dcache.tags.tagsinuse 447.094079 # Cycle average of tags in use
1434system.cpu1.dcache.tags.total_refs 10899911 # Total number of references to valid blocks.
1435system.cpu1.dcache.tags.sampled_refs 300718 # Sample count of references to valid blocks.
1436system.cpu1.dcache.tags.avg_refs 36.246287 # Average number of references to valid blocks.
1437system.cpu1.dcache.tags.warmup_cycle 76416861250 # Cycle when the warmup percentage was hit.
1438system.cpu1.dcache.tags.occ_blocks::cpu1.inst 447.094079 # Average occupied blocks per requestor
1439system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.873231 # Average percentage of cache occupancy
1440system.cpu1.dcache.tags.occ_percent::total 0.873231 # Average percentage of cache occupancy
1441system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1442system.cpu1.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
1443system.cpu1.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id
1444system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
1445system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
1446system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1447system.cpu1.dcache.tags.tag_accesses 45736548 # Number of tag accesses
1448system.cpu1.dcache.tags.data_accesses 45736548 # Number of data accesses
1449system.cpu1.dcache.ReadReq_hits::cpu1.inst 6288103 # number of ReadReq hits
1450system.cpu1.dcache.ReadReq_hits::total 6288103 # number of ReadReq hits
1451system.cpu1.dcache.WriteReq_hits::cpu1.inst 4421998 # number of WriteReq hits
1452system.cpu1.dcache.WriteReq_hits::total 4421998 # number of WriteReq hits
1453system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78443 # number of LoadLockedReq hits
1454system.cpu1.dcache.LoadLockedReq_hits::total 78443 # number of LoadLockedReq hits
1455system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79055 # number of StoreCondReq hits
1456system.cpu1.dcache.StoreCondReq_hits::total 79055 # number of StoreCondReq hits
1457system.cpu1.dcache.demand_hits::cpu1.inst 10710101 # number of demand (read+write) hits
1458system.cpu1.dcache.demand_hits::total 10710101 # number of demand (read+write) hits
1459system.cpu1.dcache.overall_hits::cpu1.inst 10710101 # number of overall hits
1460system.cpu1.dcache.overall_hits::total 10710101 # number of overall hits
1461system.cpu1.dcache.ReadReq_misses::cpu1.inst 241320 # number of ReadReq misses
1462system.cpu1.dcache.ReadReq_misses::total 241320 # number of ReadReq misses
1463system.cpu1.dcache.WriteReq_misses::cpu1.inst 223635 # number of WriteReq misses
1464system.cpu1.dcache.WriteReq_misses::total 223635 # number of WriteReq misses
1465system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10750 # number of LoadLockedReq misses
1466system.cpu1.dcache.LoadLockedReq_misses::total 10750 # number of LoadLockedReq misses
1467system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10087 # number of StoreCondReq misses
1468system.cpu1.dcache.StoreCondReq_misses::total 10087 # number of StoreCondReq misses
1469system.cpu1.dcache.demand_misses::cpu1.inst 464955 # number of demand (read+write) misses
1470system.cpu1.dcache.demand_misses::total 464955 # number of demand (read+write) misses
1471system.cpu1.dcache.overall_misses::cpu1.inst 464955 # number of overall misses
1472system.cpu1.dcache.overall_misses::total 464955 # number of overall misses
1473system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3586794993 # number of ReadReq miss cycles
1474system.cpu1.dcache.ReadReq_miss_latency::total 3586794993 # number of ReadReq miss cycles
1475system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8773828993 # number of WriteReq miss cycles
1476system.cpu1.dcache.WriteReq_miss_latency::total 8773828993 # number of WriteReq miss cycles
1477system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90116500 # number of LoadLockedReq miss cycles
1478system.cpu1.dcache.LoadLockedReq_miss_latency::total 90116500 # number of LoadLockedReq miss cycles
1479system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50277799 # number of StoreCondReq miss cycles
1480system.cpu1.dcache.StoreCondReq_miss_latency::total 50277799 # number of StoreCondReq miss cycles
1481system.cpu1.dcache.demand_miss_latency::cpu1.inst 12360623986 # number of demand (read+write) miss cycles
1482system.cpu1.dcache.demand_miss_latency::total 12360623986 # number of demand (read+write) miss cycles
1483system.cpu1.dcache.overall_miss_latency::cpu1.inst 12360623986 # number of overall miss cycles
1484system.cpu1.dcache.overall_miss_latency::total 12360623986 # number of overall miss cycles
1485system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6529423 # number of ReadReq accesses(hits+misses)
1486system.cpu1.dcache.ReadReq_accesses::total 6529423 # number of ReadReq accesses(hits+misses)
1487system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4645633 # number of WriteReq accesses(hits+misses)
1488system.cpu1.dcache.WriteReq_accesses::total 4645633 # number of WriteReq accesses(hits+misses)
1489system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89193 # number of LoadLockedReq accesses(hits+misses)
1490system.cpu1.dcache.LoadLockedReq_accesses::total 89193 # number of LoadLockedReq accesses(hits+misses)
1491system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89142 # number of StoreCondReq accesses(hits+misses)
1492system.cpu1.dcache.StoreCondReq_accesses::total 89142 # number of StoreCondReq accesses(hits+misses)
1493system.cpu1.dcache.demand_accesses::cpu1.inst 11175056 # number of demand (read+write) accesses
1494system.cpu1.dcache.demand_accesses::total 11175056 # number of demand (read+write) accesses
1495system.cpu1.dcache.overall_accesses::cpu1.inst 11175056 # number of overall (read+write) accesses
1496system.cpu1.dcache.overall_accesses::total 11175056 # number of overall (read+write) accesses
1497system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.036959 # miss rate for ReadReq accesses
1498system.cpu1.dcache.ReadReq_miss_rate::total 0.036959 # miss rate for ReadReq accesses
1499system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048139 # miss rate for WriteReq accesses
1500system.cpu1.dcache.WriteReq_miss_rate::total 0.048139 # miss rate for WriteReq accesses
1501system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120525 # miss rate for LoadLockedReq accesses
1502system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120525 # miss rate for LoadLockedReq accesses
1503system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.113157 # miss rate for StoreCondReq accesses
1504system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113157 # miss rate for StoreCondReq accesses
1505system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.041607 # miss rate for demand accesses
1506system.cpu1.dcache.demand_miss_rate::total 0.041607 # miss rate for demand accesses
1507system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.041607 # miss rate for overall accesses
1508system.cpu1.dcache.overall_miss_rate::total 0.041607 # miss rate for overall accesses
1509system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14863.231365 # average ReadReq miss latency
1510system.cpu1.dcache.ReadReq_avg_miss_latency::total 14863.231365 # average ReadReq miss latency
1511system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 39232.807892 # average WriteReq miss latency
1512system.cpu1.dcache.WriteReq_avg_miss_latency::total 39232.807892 # average WriteReq miss latency
1513system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8382.930233 # average LoadLockedReq miss latency
1514system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8382.930233 # average LoadLockedReq miss latency
1515system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4984.415485 # average StoreCondReq miss latency
1516system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4984.415485 # average StoreCondReq miss latency
1517system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency
1518system.cpu1.dcache.demand_avg_miss_latency::total 26584.559766 # average overall miss latency
1519system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency
1520system.cpu1.dcache.overall_avg_miss_latency::total 26584.559766 # average overall miss latency
1521system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1522system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1523system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1524system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1525system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1526system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1527system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1528system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1529system.cpu1.dcache.writebacks::writebacks 268002 # number of writebacks
1530system.cpu1.dcache.writebacks::total 268002 # number of writebacks
1531system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36395 # number of ReadReq MSHR hits
1532system.cpu1.dcache.ReadReq_mshr_hits::total 36395 # number of ReadReq MSHR hits
1533system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98109 # number of WriteReq MSHR hits
1534system.cpu1.dcache.WriteReq_mshr_hits::total 98109 # number of WriteReq MSHR hits
1535system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 34 # number of LoadLockedReq MSHR hits
1536system.cpu1.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits
1537system.cpu1.dcache.demand_mshr_hits::cpu1.inst 134504 # number of demand (read+write) MSHR hits
1538system.cpu1.dcache.demand_mshr_hits::total 134504 # number of demand (read+write) MSHR hits
1539system.cpu1.dcache.overall_mshr_hits::cpu1.inst 134504 # number of overall MSHR hits
1540system.cpu1.dcache.overall_mshr_hits::total 134504 # number of overall MSHR hits
1541system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 204925 # number of ReadReq MSHR misses
1542system.cpu1.dcache.ReadReq_mshr_misses::total 204925 # number of ReadReq MSHR misses
1543system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125526 # number of WriteReq MSHR misses
1544system.cpu1.dcache.WriteReq_mshr_misses::total 125526 # number of WriteReq MSHR misses
1545system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10716 # number of LoadLockedReq MSHR misses
1546system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10716 # number of LoadLockedReq MSHR misses
1547system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10087 # number of StoreCondReq MSHR misses
1548system.cpu1.dcache.StoreCondReq_mshr_misses::total 10087 # number of StoreCondReq MSHR misses
1549system.cpu1.dcache.demand_mshr_misses::cpu1.inst 330451 # number of demand (read+write) MSHR misses
1550system.cpu1.dcache.demand_mshr_misses::total 330451 # number of demand (read+write) MSHR misses
1551system.cpu1.dcache.overall_mshr_misses::cpu1.inst 330451 # number of overall MSHR misses
1552system.cpu1.dcache.overall_mshr_misses::total 330451 # number of overall MSHR misses
1553system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2412502275 # number of ReadReq MSHR miss cycles
1554system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2412502275 # number of ReadReq MSHR miss cycles
1555system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4153602004 # number of WriteReq MSHR miss cycles
1556system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4153602004 # number of WriteReq MSHR miss cycles
1557system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68123500 # number of LoadLockedReq MSHR miss cycles
1558system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68123500 # number of LoadLockedReq MSHR miss cycles
1559system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30103201 # number of StoreCondReq MSHR miss cycles
1560system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30103201 # number of StoreCondReq MSHR miss cycles
1561system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6566104279 # number of demand (read+write) MSHR miss cycles
1562system.cpu1.dcache.demand_mshr_miss_latency::total 6566104279 # number of demand (read+write) MSHR miss cycles
1563system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6566104279 # number of overall MSHR miss cycles
1564system.cpu1.dcache.overall_mshr_miss_latency::total 6566104279 # number of overall MSHR miss cycles
1565system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11993503000 # number of ReadReq MSHR uncacheable cycles
1566system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11993503000 # number of ReadReq MSHR uncacheable cycles
1567system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672579152 # number of WriteReq MSHR uncacheable cycles
1568system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672579152 # number of WriteReq MSHR uncacheable cycles
1569system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36666082152 # number of overall MSHR uncacheable cycles
1570system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36666082152 # number of overall MSHR uncacheable cycles
1571system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.031385 # mshr miss rate for ReadReq accesses
1572system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.031385 # mshr miss rate for ReadReq accesses
1573system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027020 # mshr miss rate for WriteReq accesses
1574system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027020 # mshr miss rate for WriteReq accesses
1575system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120144 # mshr miss rate for LoadLockedReq accesses
1576system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120144 # mshr miss rate for LoadLockedReq accesses
1577system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113157 # mshr miss rate for StoreCondReq accesses
1578system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113157 # mshr miss rate for StoreCondReq accesses
1579system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for demand accesses
1580system.cpu1.dcache.demand_mshr_miss_rate::total 0.029570 # mshr miss rate for demand accesses
1581system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for overall accesses
1582system.cpu1.dcache.overall_mshr_miss_rate::total 0.029570 # mshr miss rate for overall accesses
1583system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.610833 # average ReadReq mshr miss latency
1584system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11772.610833 # average ReadReq mshr miss latency
1585system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 33089.575100 # average WriteReq mshr miss latency
1586system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33089.575100 # average WriteReq mshr miss latency
1587system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6357.176185 # average LoadLockedReq mshr miss latency
1588system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6357.176185 # average LoadLockedReq mshr miss latency
1589system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2984.356201 # average StoreCondReq mshr miss latency
1590system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2984.356201 # average StoreCondReq mshr miss latency
1591system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency
1592system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency
1593system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency
1594system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency
1595system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1596system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1597system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
1598system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1599system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1600system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1601system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1602system.iocache.tags.replacements 0 # number of replacements

--- 7 unchanged lines hidden (view full) ---

1610system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1611system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1612system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1613system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1614system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1615system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1616system.iocache.fast_writes 0 # number of fast writes performed
1617system.iocache.cache_copies 0 # number of cache copies performed
1618system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722335941002 # number of ReadReq MSHR uncacheable cycles
1619system.iocache.ReadReq_mshr_uncacheable_latency::total 722335941002 # number of ReadReq MSHR uncacheable cycles
1620system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722335941002 # number of overall MSHR uncacheable cycles
1621system.iocache.overall_mshr_uncacheable_latency::total 722335941002 # number of overall MSHR uncacheable cycles
1622system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1623system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1624system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1625system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1626system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1627
1628---------- End Simulation Statistics ----------