1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.848878 # Number of seconds simulated
4sim_ticks 2848878048000 # Number of ticks simulated
5final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 186843 # Simulator instruction rate (inst/s)
8host_op_rate 226247 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4196685224 # Simulator tick rate (ticks/s)
10host_mem_usage 620168 # Number of bytes of host memory used
11host_seconds 678.84 # Real time elapsed on the host
12sim_insts 126836472 # Number of instructions simulated
13sim_ops 153585571 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1701632 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1345580 # Number of bytes read from this memory
--- 669 unchanged lines hidden (view full) ---
689system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15694.801060 # average overall miss latency
690system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060 # average overall miss latency
691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
696system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
697system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks
698system.cpu0.dcache.writebacks::total 757698 # number of writebacks
699system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits
700system.cpu0.dcache.ReadReq_mshr_hits::total 75572 # number of ReadReq MSHR hits
701system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266010 # number of WriteReq MSHR hits
702system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits
703system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14891 # number of LoadLockedReq MSHR hits
704system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
739system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 641500 # number of StoreCondFailReq MSHR miss cycles
740system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles
741system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12322191000 # number of demand (read+write) MSHR miss cycles
742system.cpu0.dcache.demand_mshr_miss_latency::total 12322191000 # number of demand (read+write) MSHR miss cycles
743system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000 # number of overall MSHR miss cycles
744system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles
745system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles
746system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles
747system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6702357000 # number of overall MSHR uncacheable cycles
748system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6702357000 # number of overall MSHR uncacheable cycles
749system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses
750system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
751system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses
752system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses
753system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses
754system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses
755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses
756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency
776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816 # average overall mshr miss latency
777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency
778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency
779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency
780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency
781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110297.814567 # average overall mshr uncacheable latency
782system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110297.814567 # average overall mshr uncacheable latency
783system.cpu0.icache.tags.replacements 2042425 # number of replacements
784system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use
785system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks.
786system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks.
787system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks.
788system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit.
789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor
790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency
834system.cpu0.icache.overall_avg_miss_latency::total 10073.051428 # average overall miss latency
835system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
839system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
841system.cpu0.icache.writebacks::writebacks 2042425 # number of writebacks
842system.cpu0.icache.writebacks::total 2042425 # number of writebacks
843system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2042958 # number of ReadReq MSHR misses
844system.cpu0.icache.ReadReq_mshr_misses::total 2042958 # number of ReadReq MSHR misses
845system.cpu0.icache.demand_mshr_misses::cpu0.inst 2042958 # number of demand (read+write) MSHR misses
846system.cpu0.icache.demand_mshr_misses::total 2042958 # number of demand (read+write) MSHR misses
847system.cpu0.icache.overall_mshr_misses::cpu0.inst 2042958 # number of overall MSHR misses
848system.cpu0.icache.overall_mshr_misses::total 2042958 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
872system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
874system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency
876system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency
877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency
878system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency
879system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued
880system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified
881system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue
882system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
883system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
884system.cpu0.l2cache.prefetcher.pfSpanPage 244697 # number of prefetches not generated due to page crossing
885system.cpu0.l2cache.tags.replacements 304900 # number of replacements
886system.cpu0.l2cache.tags.tagsinuse 16120.127106 # Cycle average of tags in use
--- 178 unchanged lines hidden (view full) ---
1065system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45396.596297 # average overall miss latency
1066system.cpu0.l2cache.overall_avg_miss_latency::total 51526.739597 # average overall miss latency
1067system.cpu0.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked
1068system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1069system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1070system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1071system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1072system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1073system.cpu0.l2cache.unused_prefetches 10897 # number of HardPF blocks evicted w/o reference
1074system.cpu0.l2cache.writebacks::writebacks 237171 # number of writebacks
1075system.cpu0.l2cache.writebacks::total 237171 # number of writebacks
1076system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5426 # number of ReadExReq MSHR hits
1077system.cpu0.l2cache.ReadExReq_mshr_hits::total 5426 # number of ReadExReq MSHR hits
1078system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 72 # number of ReadCleanReq MSHR hits
1079system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 72 # number of ReadCleanReq MSHR hits
1080system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 591 # number of ReadSharedReq MSHR hits
--- 64 unchanged lines hidden (view full) ---
1145system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1833000 # number of overall MSHR miss cycles
1146system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4100378000 # number of overall MSHR miss cycles
1147system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5357247999 # number of overall MSHR miss cycles
1148system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21051299430 # number of overall MSHR miss cycles
1149system.cpu0.l2cache.overall_mshr_miss_latency::total 30542659429 # number of overall MSHR miss cycles
1150system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles
1151system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445890500 # number of ReadReq MSHR uncacheable cycles
1152system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971910500 # number of ReadReq MSHR uncacheable cycles
1153system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles
1154system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6445890500 # number of overall MSHR uncacheable cycles
1155system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6971910500 # number of overall MSHR uncacheable cycles
1156system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for ReadReq accesses
1157system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for ReadReq accesses
1158system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009054 # mshr miss rate for ReadReq accesses
1159system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1160system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1161system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1162system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1163system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 41 unchanged lines hidden (view full) ---
1205system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
1206system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
1207system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
1208system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency
1209system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency
1210system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency
1211system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency
1212system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency
1213system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency
1214system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 106077.255373 # average overall mshr uncacheable latency
1215system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 107785.824714 # average overall mshr uncacheable latency
1216system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter.
1217system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1218system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1219system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter.
1220system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1221system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1222system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution
1223system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution
--- 376 unchanged lines hidden (view full) ---
1600system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23712.367863 # average overall miss latency
1601system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863 # average overall miss latency
1602system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1603system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1604system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1605system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1606system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1607system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1608system.cpu1.dcache.writebacks::writebacks 155125 # number of writebacks
1609system.cpu1.dcache.writebacks::total 155125 # number of writebacks
1610system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12753 # number of ReadReq MSHR hits
1611system.cpu1.dcache.ReadReq_mshr_hits::total 12753 # number of ReadReq MSHR hits
1612system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42136 # number of WriteReq MSHR hits
1613system.cpu1.dcache.WriteReq_mshr_hits::total 42136 # number of WriteReq MSHR hits
1614system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11686 # number of LoadLockedReq MSHR hits
1615system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11686 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
1650system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1094500 # number of StoreCondFailReq MSHR miss cycles
1651system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1094500 # number of StoreCondFailReq MSHR miss cycles
1652system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4556767000 # number of demand (read+write) MSHR miss cycles
1653system.cpu1.dcache.demand_mshr_miss_latency::total 4556767000 # number of demand (read+write) MSHR miss cycles
1654system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500 # number of overall MSHR miss cycles
1655system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles
1656system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles
1657system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles
1658system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 389467000 # number of overall MSHR uncacheable cycles
1659system.cpu1.dcache.overall_mshr_uncacheable_latency::total 389467000 # number of overall MSHR uncacheable cycles
1660system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses
1661system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses
1662system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses
1663system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses
1664system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses
1665system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses
1666system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses
1667system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
1684system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1685system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1686system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency
1687system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency
1688system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency
1689system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency
1690system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency
1691system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency
1692system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 73706.850871 # average overall mshr uncacheable latency
1693system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 73706.850871 # average overall mshr uncacheable latency
1694system.cpu1.icache.tags.replacements 856657 # number of replacements
1695system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use
1696system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks.
1697system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks.
1698system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks.
1699system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit.
1700system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor
1701system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
1744system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency
1745system.cpu1.icache.overall_avg_miss_latency::total 8854.776013 # average overall miss latency
1746system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1747system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1748system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1749system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1750system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1751system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1752system.cpu1.icache.writebacks::writebacks 856657 # number of writebacks
1753system.cpu1.icache.writebacks::total 856657 # number of writebacks
1754system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # number of ReadReq MSHR misses
1755system.cpu1.icache.ReadReq_mshr_misses::total 857169 # number of ReadReq MSHR misses
1756system.cpu1.icache.demand_mshr_misses::cpu1.inst 857169 # number of demand (read+write) MSHR misses
1757system.cpu1.icache.demand_mshr_misses::total 857169 # number of demand (read+write) MSHR misses
1758system.cpu1.icache.overall_mshr_misses::cpu1.inst 857169 # number of overall MSHR misses
1759system.cpu1.icache.overall_mshr_misses::total 857169 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
1782system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1783system.cpu1.icache.demand_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1784system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1785system.cpu1.icache.overall_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1786system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average ReadReq mshr uncacheable latency
1787system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency
1788system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency
1789system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency
1790system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued
1791system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified
1792system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue
1793system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1794system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1795system.cpu1.l2cache.prefetcher.pfSpanPage 49365 # number of prefetches not generated due to page crossing
1796system.cpu1.l2cache.tags.replacements 38167 # number of replacements
1797system.cpu1.l2cache.tags.tagsinuse 15174.819793 # Cycle average of tags in use
--- 180 unchanged lines hidden (view full) ---
1978system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33463.491285 # average overall miss latency
1979system.cpu1.l2cache.overall_avg_miss_latency::total 36114.627487 # average overall miss latency
1980system.cpu1.l2cache.blocked_cycles::no_mshrs 30 # number of cycles access was blocked
1981system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1982system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1983system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1984system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
1985system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1986system.cpu1.l2cache.unused_prefetches 580 # number of HardPF blocks evicted w/o reference
1987system.cpu1.l2cache.writebacks::writebacks 29115 # number of writebacks
1988system.cpu1.l2cache.writebacks::total 29115 # number of writebacks
1989system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 240 # number of ReadExReq MSHR hits
1990system.cpu1.l2cache.ReadExReq_mshr_hits::total 240 # number of ReadExReq MSHR hits
1991system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
1992system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
1993system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 39 # number of ReadSharedReq MSHR hits
--- 66 unchanged lines hidden (view full) ---
2060system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3383500 # number of overall MSHR miss cycles
2061system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 662136000 # number of overall MSHR miss cycles
2062system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2693368996 # number of overall MSHR miss cycles
2063system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of overall MSHR miss cycles
2064system.cpu1.l2cache.overall_mshr_miss_latency::total 4332115741 # number of overall MSHR miss cycles
2065system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14575500 # number of ReadReq MSHR uncacheable cycles
2066system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365633500 # number of ReadReq MSHR uncacheable cycles
2067system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 380209000 # number of ReadReq MSHR uncacheable cycles
2068system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14575500 # number of overall MSHR uncacheable cycles
2069system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 365633500 # number of overall MSHR uncacheable cycles
2070system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 380209000 # number of overall MSHR uncacheable cycles
2071system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses
2072system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for ReadReq accesses
2073system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032323 # mshr miss rate for ReadReq accesses
2074system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2075system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2076system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2077system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2078system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 43 unchanged lines hidden (view full) ---
2122system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
2123system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
2124system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
2125system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency
2126system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency
2127system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency
2128system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency
2129system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency
2130system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency
2131system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69196.347464 # average overall mshr uncacheable latency
2132system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70461.267606 # average overall mshr uncacheable latency
2133system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter.
2134system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2135system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2136system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter.
2137system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2138system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2139system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution
2140system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution
--- 154 unchanged lines hidden (view full) ---
2295system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2296system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2297system.iocache.tags.tag_accesses 328203 # Number of tag accesses
2298system.iocache.tags.data_accesses 328203 # Number of data accesses
2299system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
2300system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
2301system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2302system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2303system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses
2304system.iocache.demand_misses::total 36467 # number of demand (read+write) misses
2305system.iocache.overall_misses::realview.ide 36467 # number of overall misses
2306system.iocache.overall_misses::total 36467 # number of overall misses
2307system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles
2308system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles
2309system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles
2310system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles
2311system.iocache.demand_miss_latency::realview.ide 4609920234 # number of demand (read+write) miss cycles
2312system.iocache.demand_miss_latency::total 4609920234 # number of demand (read+write) miss cycles
2313system.iocache.overall_miss_latency::realview.ide 4609920234 # number of overall miss cycles
2314system.iocache.overall_miss_latency::total 4609920234 # number of overall miss cycles
2315system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
2316system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
2317system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2318system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2319system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses
2320system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses
2321system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses
2322system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses
2323system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2324system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2325system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2326system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2327system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2328system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2329system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2330system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2331system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency
2332system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency
2333system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency
2334system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency
2335system.iocache.demand_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
2336system.iocache.demand_avg_miss_latency::total 126413.476129 # average overall miss latency
2337system.iocache.overall_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
2338system.iocache.overall_avg_miss_latency::total 126413.476129 # average overall miss latency
2339system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2340system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2341system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2342system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2343system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2344system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2345system.iocache.writebacks::writebacks 36190 # number of writebacks
2346system.iocache.writebacks::total 36190 # number of writebacks
2347system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
2348system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
2349system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2350system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2351system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses
2352system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses
2353system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses
2354system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses
2355system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles
2356system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles
2357system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles
2358system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles
2359system.iocache.demand_mshr_miss_latency::realview.ide 2784909291 # number of demand (read+write) MSHR miss cycles
2360system.iocache.demand_mshr_miss_latency::total 2784909291 # number of demand (read+write) MSHR miss cycles
2361system.iocache.overall_mshr_miss_latency::realview.ide 2784909291 # number of overall MSHR miss cycles
2362system.iocache.overall_mshr_miss_latency::total 2784909291 # number of overall MSHR miss cycles
2363system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2364system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2365system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2366system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2367system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2368system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2369system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2370system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2371system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897 # average ReadReq mshr miss latency
2372system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency
2373system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency
2374system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency
2375system.iocache.demand_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
2376system.iocache.demand_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
2377system.iocache.overall_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
2378system.iocache.overall_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
2379system.l2c.tags.replacements 132278 # number of replacements
2380system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use
2381system.l2c.tags.total_refs 475189 # Total number of references to valid blocks.
2382system.l2c.tags.sampled_refs 196356 # Sample count of references to valid blocks.
2383system.l2c.tags.avg_refs 2.420038 # Average number of references to valid blocks.
2384system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2385system.l2c.tags.occ_blocks::writebacks 13432.084830 # Average occupied blocks per requestor
2386system.l2c.tags.occ_blocks::cpu0.dtb.walker 86.256901 # Average occupied blocks per requestor
--- 278 unchanged lines hidden (view full) ---
2665system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average overall miss latency
2666system.l2c.overall_avg_miss_latency::total 146696.352377 # average overall miss latency
2667system.l2c.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
2668system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2669system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2670system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2671system.l2c.avg_blocked_cycles::no_mshrs 45 # average number of cycles each access was blocked
2672system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2673system.l2c.writebacks::writebacks 102335 # number of writebacks
2674system.l2c.writebacks::total 102335 # number of writebacks
2675system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
2676system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits
2677system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
2678system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
2679system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
2680system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
--- 93 unchanged lines hidden (view full) ---
2774system.l2c.overall_mshr_miss_latency::cpu1.data 1203034025 # number of overall MSHR miss cycles
2775system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of overall MSHR miss cycles
2776system.l2c.overall_mshr_miss_latency::total 26857931717 # number of overall MSHR miss cycles
2777system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443763000 # number of ReadReq MSHR uncacheable cycles
2778system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5869096507 # number of ReadReq MSHR uncacheable cycles
2779system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12223000 # number of ReadReq MSHR uncacheable cycles
2780system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 312114003 # number of ReadReq MSHR uncacheable cycles
2781system.l2c.ReadReq_mshr_uncacheable_latency::total 6637196510 # number of ReadReq MSHR uncacheable cycles
2782system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles
2783system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5869096507 # number of overall MSHR uncacheable cycles
2784system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12223000 # number of overall MSHR uncacheable cycles
2785system.l2c.overall_mshr_uncacheable_latency::cpu1.data 312114003 # number of overall MSHR uncacheable cycles
2786system.l2c.overall_mshr_uncacheable_latency::total 6637196510 # number of overall MSHR uncacheable cycles
2787system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2788system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2789system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.226284 # mshr miss rate for UpgradeReq accesses
2790system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.516896 # mshr miss rate for UpgradeReq accesses
2791system.l2c.UpgradeReq_mshr_miss_rate::total 0.253708 # mshr miss rate for UpgradeReq accesses
2792system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.248982 # mshr miss rate for SCUpgradeReq accesses
2793system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585895 # mshr miss rate for SCUpgradeReq accesses
2794system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.393411 # mshr miss rate for SCUpgradeReq accesses
--- 69 unchanged lines hidden (view full) ---
2864system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
2865system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
2866system.l2c.overall_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
2867system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency
2868system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719 # average ReadReq mshr uncacheable latency
2869system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency
2870system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency
2871system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency
2872system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency
2873system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96585.204012 # average overall mshr uncacheable latency
2874system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency
2875system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 59101.307139 # average overall mshr uncacheable latency
2876system.l2c.overall_avg_mshr_uncacheable_latency::total 94714.260374 # average overall mshr uncacheable latency
2877system.membus.trans_dist::ReadReq 39041 # Transaction distribution
2878system.membus.trans_dist::ReadResp 216336 # Transaction distribution
2879system.membus.trans_dist::WriteReq 31035 # Transaction distribution
2880system.membus.trans_dist::WriteResp 31035 # Transaction distribution
2881system.membus.trans_dist::WritebackDirty 138525 # Transaction distribution
2882system.membus.trans_dist::CleanEvict 18214 # Transaction distribution
2883system.membus.trans_dist::UpgradeReq 73002 # Transaction distribution
2884system.membus.trans_dist::SCUpgradeReq 40704 # Transaction distribution
--- 136 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.848878 # Number of seconds simulated
4sim_ticks 2848878048000 # Number of ticks simulated
5final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 186843 # Simulator instruction rate (inst/s)
8host_op_rate 226247 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4196685224 # Simulator tick rate (ticks/s)
10host_mem_usage 620168 # Number of bytes of host memory used
11host_seconds 678.84 # Real time elapsed on the host
12sim_insts 126836472 # Number of instructions simulated
13sim_ops 153585571 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1701632 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1345580 # Number of bytes read from this memory
--- 669 unchanged lines hidden (view full) ---
689system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15694.801060 # average overall miss latency
690system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060 # average overall miss latency
691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
696system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
697system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks
698system.cpu0.dcache.writebacks::total 757698 # number of writebacks
699system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits
700system.cpu0.dcache.ReadReq_mshr_hits::total 75572 # number of ReadReq MSHR hits
701system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266010 # number of WriteReq MSHR hits
702system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits
703system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14891 # number of LoadLockedReq MSHR hits
704system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
739system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 641500 # number of StoreCondFailReq MSHR miss cycles
740system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles
741system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12322191000 # number of demand (read+write) MSHR miss cycles
742system.cpu0.dcache.demand_mshr_miss_latency::total 12322191000 # number of demand (read+write) MSHR miss cycles
743system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000 # number of overall MSHR miss cycles
744system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles
745system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles
746system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles
747system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6702357000 # number of overall MSHR uncacheable cycles
748system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6702357000 # number of overall MSHR uncacheable cycles
749system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses
750system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
751system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses
752system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses
753system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses
754system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses
755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses
756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency
776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816 # average overall mshr miss latency
777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency
778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency
779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency
780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency
781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110297.814567 # average overall mshr uncacheable latency
782system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110297.814567 # average overall mshr uncacheable latency
783system.cpu0.icache.tags.replacements 2042425 # number of replacements
784system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use
785system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks.
786system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks.
787system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks.
788system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit.
789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor
790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency
834system.cpu0.icache.overall_avg_miss_latency::total 10073.051428 # average overall miss latency
835system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
839system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
841system.cpu0.icache.writebacks::writebacks 2042425 # number of writebacks
842system.cpu0.icache.writebacks::total 2042425 # number of writebacks
843system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2042958 # number of ReadReq MSHR misses
844system.cpu0.icache.ReadReq_mshr_misses::total 2042958 # number of ReadReq MSHR misses
845system.cpu0.icache.demand_mshr_misses::cpu0.inst 2042958 # number of demand (read+write) MSHR misses
846system.cpu0.icache.demand_mshr_misses::total 2042958 # number of demand (read+write) MSHR misses
847system.cpu0.icache.overall_mshr_misses::cpu0.inst 2042958 # number of overall MSHR misses
848system.cpu0.icache.overall_mshr_misses::total 2042958 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
872system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency
874system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency
875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency
876system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency
877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency
878system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency
879system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued
880system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified
881system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue
882system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
883system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
884system.cpu0.l2cache.prefetcher.pfSpanPage 244697 # number of prefetches not generated due to page crossing
885system.cpu0.l2cache.tags.replacements 304900 # number of replacements
886system.cpu0.l2cache.tags.tagsinuse 16120.127106 # Cycle average of tags in use
--- 178 unchanged lines hidden (view full) ---
1065system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45396.596297 # average overall miss latency
1066system.cpu0.l2cache.overall_avg_miss_latency::total 51526.739597 # average overall miss latency
1067system.cpu0.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked
1068system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1069system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1070system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1071system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1072system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1073system.cpu0.l2cache.unused_prefetches 10897 # number of HardPF blocks evicted w/o reference
1074system.cpu0.l2cache.writebacks::writebacks 237171 # number of writebacks
1075system.cpu0.l2cache.writebacks::total 237171 # number of writebacks
1076system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5426 # number of ReadExReq MSHR hits
1077system.cpu0.l2cache.ReadExReq_mshr_hits::total 5426 # number of ReadExReq MSHR hits
1078system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 72 # number of ReadCleanReq MSHR hits
1079system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 72 # number of ReadCleanReq MSHR hits
1080system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 591 # number of ReadSharedReq MSHR hits
--- 64 unchanged lines hidden (view full) ---
1145system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1833000 # number of overall MSHR miss cycles
1146system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4100378000 # number of overall MSHR miss cycles
1147system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5357247999 # number of overall MSHR miss cycles
1148system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21051299430 # number of overall MSHR miss cycles
1149system.cpu0.l2cache.overall_mshr_miss_latency::total 30542659429 # number of overall MSHR miss cycles
1150system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles
1151system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445890500 # number of ReadReq MSHR uncacheable cycles
1152system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971910500 # number of ReadReq MSHR uncacheable cycles
1153system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles
1154system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6445890500 # number of overall MSHR uncacheable cycles
1155system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6971910500 # number of overall MSHR uncacheable cycles
1156system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for ReadReq accesses
1157system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for ReadReq accesses
1158system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009054 # mshr miss rate for ReadReq accesses
1159system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1160system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1161system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1162system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1163system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 41 unchanged lines hidden (view full) ---
1205system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
1206system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
1207system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
1208system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency
1209system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency
1210system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency
1211system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency
1212system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency
1213system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency
1214system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 106077.255373 # average overall mshr uncacheable latency
1215system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 107785.824714 # average overall mshr uncacheable latency
1216system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter.
1217system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1218system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1219system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter.
1220system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1221system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1222system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution
1223system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution
--- 376 unchanged lines hidden (view full) ---
1600system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23712.367863 # average overall miss latency
1601system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863 # average overall miss latency
1602system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1603system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1604system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1605system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1606system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1607system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1608system.cpu1.dcache.writebacks::writebacks 155125 # number of writebacks
1609system.cpu1.dcache.writebacks::total 155125 # number of writebacks
1610system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12753 # number of ReadReq MSHR hits
1611system.cpu1.dcache.ReadReq_mshr_hits::total 12753 # number of ReadReq MSHR hits
1612system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42136 # number of WriteReq MSHR hits
1613system.cpu1.dcache.WriteReq_mshr_hits::total 42136 # number of WriteReq MSHR hits
1614system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11686 # number of LoadLockedReq MSHR hits
1615system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11686 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
1650system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1094500 # number of StoreCondFailReq MSHR miss cycles
1651system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1094500 # number of StoreCondFailReq MSHR miss cycles
1652system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4556767000 # number of demand (read+write) MSHR miss cycles
1653system.cpu1.dcache.demand_mshr_miss_latency::total 4556767000 # number of demand (read+write) MSHR miss cycles
1654system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500 # number of overall MSHR miss cycles
1655system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles
1656system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles
1657system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles
1658system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 389467000 # number of overall MSHR uncacheable cycles
1659system.cpu1.dcache.overall_mshr_uncacheable_latency::total 389467000 # number of overall MSHR uncacheable cycles
1660system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses
1661system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses
1662system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses
1663system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses
1664system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses
1665system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses
1666system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses
1667system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
1684system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1685system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1686system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency
1687system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency
1688system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency
1689system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency
1690system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency
1691system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency
1692system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 73706.850871 # average overall mshr uncacheable latency
1693system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 73706.850871 # average overall mshr uncacheable latency
1694system.cpu1.icache.tags.replacements 856657 # number of replacements
1695system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use
1696system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks.
1697system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks.
1698system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks.
1699system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit.
1700system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor
1701system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
1744system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency
1745system.cpu1.icache.overall_avg_miss_latency::total 8854.776013 # average overall miss latency
1746system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1747system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1748system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1749system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1750system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1751system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1752system.cpu1.icache.writebacks::writebacks 856657 # number of writebacks
1753system.cpu1.icache.writebacks::total 856657 # number of writebacks
1754system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # number of ReadReq MSHR misses
1755system.cpu1.icache.ReadReq_mshr_misses::total 857169 # number of ReadReq MSHR misses
1756system.cpu1.icache.demand_mshr_misses::cpu1.inst 857169 # number of demand (read+write) MSHR misses
1757system.cpu1.icache.demand_mshr_misses::total 857169 # number of demand (read+write) MSHR misses
1758system.cpu1.icache.overall_mshr_misses::cpu1.inst 857169 # number of overall MSHR misses
1759system.cpu1.icache.overall_mshr_misses::total 857169 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
1782system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1783system.cpu1.icache.demand_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1784system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency
1785system.cpu1.icache.overall_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency
1786system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average ReadReq mshr uncacheable latency
1787system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency
1788system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency
1789system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency
1790system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued
1791system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified
1792system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue
1793system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1794system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1795system.cpu1.l2cache.prefetcher.pfSpanPage 49365 # number of prefetches not generated due to page crossing
1796system.cpu1.l2cache.tags.replacements 38167 # number of replacements
1797system.cpu1.l2cache.tags.tagsinuse 15174.819793 # Cycle average of tags in use
--- 180 unchanged lines hidden (view full) ---
1978system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33463.491285 # average overall miss latency
1979system.cpu1.l2cache.overall_avg_miss_latency::total 36114.627487 # average overall miss latency
1980system.cpu1.l2cache.blocked_cycles::no_mshrs 30 # number of cycles access was blocked
1981system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1982system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1983system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1984system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
1985system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1986system.cpu1.l2cache.unused_prefetches 580 # number of HardPF blocks evicted w/o reference
1987system.cpu1.l2cache.writebacks::writebacks 29115 # number of writebacks
1988system.cpu1.l2cache.writebacks::total 29115 # number of writebacks
1989system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 240 # number of ReadExReq MSHR hits
1990system.cpu1.l2cache.ReadExReq_mshr_hits::total 240 # number of ReadExReq MSHR hits
1991system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
1992system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
1993system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 39 # number of ReadSharedReq MSHR hits
--- 66 unchanged lines hidden (view full) ---
2060system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3383500 # number of overall MSHR miss cycles
2061system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 662136000 # number of overall MSHR miss cycles
2062system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2693368996 # number of overall MSHR miss cycles
2063system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 962292245 # number of overall MSHR miss cycles
2064system.cpu1.l2cache.overall_mshr_miss_latency::total 4332115741 # number of overall MSHR miss cycles
2065system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14575500 # number of ReadReq MSHR uncacheable cycles
2066system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365633500 # number of ReadReq MSHR uncacheable cycles
2067system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 380209000 # number of ReadReq MSHR uncacheable cycles
2068system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14575500 # number of overall MSHR uncacheable cycles
2069system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 365633500 # number of overall MSHR uncacheable cycles
2070system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 380209000 # number of overall MSHR uncacheable cycles
2071system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses
2072system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for ReadReq accesses
2073system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032323 # mshr miss rate for ReadReq accesses
2074system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2075system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2076system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2077system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2078system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 43 unchanged lines hidden (view full) ---
2122system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
2123system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
2124system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
2125system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency
2126system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency
2127system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency
2128system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency
2129system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency
2130system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency
2131system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69196.347464 # average overall mshr uncacheable latency
2132system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70461.267606 # average overall mshr uncacheable latency
2133system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter.
2134system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2135system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2136system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter.
2137system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2138system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2139system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution
2140system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution
--- 154 unchanged lines hidden (view full) ---
2295system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2296system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2297system.iocache.tags.tag_accesses 328203 # Number of tag accesses
2298system.iocache.tags.data_accesses 328203 # Number of data accesses
2299system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
2300system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
2301system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2302system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2303system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses
2304system.iocache.demand_misses::total 36467 # number of demand (read+write) misses
2305system.iocache.overall_misses::realview.ide 36467 # number of overall misses
2306system.iocache.overall_misses::total 36467 # number of overall misses
2307system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles
2308system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles
2309system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles
2310system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles
2311system.iocache.demand_miss_latency::realview.ide 4609920234 # number of demand (read+write) miss cycles
2312system.iocache.demand_miss_latency::total 4609920234 # number of demand (read+write) miss cycles
2313system.iocache.overall_miss_latency::realview.ide 4609920234 # number of overall miss cycles
2314system.iocache.overall_miss_latency::total 4609920234 # number of overall miss cycles
2315system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
2316system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
2317system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2318system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2319system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses
2320system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses
2321system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses
2322system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses
2323system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2324system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2325system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2326system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2327system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2328system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2329system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2330system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2331system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency
2332system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency
2333system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency
2334system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency
2335system.iocache.demand_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
2336system.iocache.demand_avg_miss_latency::total 126413.476129 # average overall miss latency
2337system.iocache.overall_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency
2338system.iocache.overall_avg_miss_latency::total 126413.476129 # average overall miss latency
2339system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2340system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2341system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2342system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2343system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2344system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2345system.iocache.writebacks::writebacks 36190 # number of writebacks
2346system.iocache.writebacks::total 36190 # number of writebacks
2347system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
2348system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
2349system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2350system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2351system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses
2352system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses
2353system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses
2354system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses
2355system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles
2356system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles
2357system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles
2358system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles
2359system.iocache.demand_mshr_miss_latency::realview.ide 2784909291 # number of demand (read+write) MSHR miss cycles
2360system.iocache.demand_mshr_miss_latency::total 2784909291 # number of demand (read+write) MSHR miss cycles
2361system.iocache.overall_mshr_miss_latency::realview.ide 2784909291 # number of overall MSHR miss cycles
2362system.iocache.overall_mshr_miss_latency::total 2784909291 # number of overall MSHR miss cycles
2363system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2364system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2365system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2366system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2367system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2368system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2369system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2370system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2371system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897 # average ReadReq mshr miss latency
2372system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency
2373system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency
2374system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency
2375system.iocache.demand_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
2376system.iocache.demand_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
2377system.iocache.overall_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency
2378system.iocache.overall_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency
2379system.l2c.tags.replacements 132278 # number of replacements
2380system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use
2381system.l2c.tags.total_refs 475189 # Total number of references to valid blocks.
2382system.l2c.tags.sampled_refs 196356 # Sample count of references to valid blocks.
2383system.l2c.tags.avg_refs 2.420038 # Average number of references to valid blocks.
2384system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2385system.l2c.tags.occ_blocks::writebacks 13432.084830 # Average occupied blocks per requestor
2386system.l2c.tags.occ_blocks::cpu0.dtb.walker 86.256901 # Average occupied blocks per requestor
--- 278 unchanged lines hidden (view full) ---
2665system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 168339.431835 # average overall miss latency
2666system.l2c.overall_avg_miss_latency::total 146696.352377 # average overall miss latency
2667system.l2c.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
2668system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2669system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2670system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2671system.l2c.avg_blocked_cycles::no_mshrs 45 # average number of cycles each access was blocked
2672system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2673system.l2c.writebacks::writebacks 102335 # number of writebacks
2674system.l2c.writebacks::total 102335 # number of writebacks
2675system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
2676system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits
2677system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
2678system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
2679system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
2680system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
--- 93 unchanged lines hidden (view full) ---
2774system.l2c.overall_mshr_miss_latency::cpu1.data 1203034025 # number of overall MSHR miss cycles
2775system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 831585272 # number of overall MSHR miss cycles
2776system.l2c.overall_mshr_miss_latency::total 26857931717 # number of overall MSHR miss cycles
2777system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 443763000 # number of ReadReq MSHR uncacheable cycles
2778system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5869096507 # number of ReadReq MSHR uncacheable cycles
2779system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12223000 # number of ReadReq MSHR uncacheable cycles
2780system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 312114003 # number of ReadReq MSHR uncacheable cycles
2781system.l2c.ReadReq_mshr_uncacheable_latency::total 6637196510 # number of ReadReq MSHR uncacheable cycles
2782system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 443763000 # number of overall MSHR uncacheable cycles
2783system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5869096507 # number of overall MSHR uncacheable cycles
2784system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12223000 # number of overall MSHR uncacheable cycles
2785system.l2c.overall_mshr_uncacheable_latency::cpu1.data 312114003 # number of overall MSHR uncacheable cycles
2786system.l2c.overall_mshr_uncacheable_latency::total 6637196510 # number of overall MSHR uncacheable cycles
2787system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2788system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2789system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.226284 # mshr miss rate for UpgradeReq accesses
2790system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.516896 # mshr miss rate for UpgradeReq accesses
2791system.l2c.UpgradeReq_mshr_miss_rate::total 0.253708 # mshr miss rate for UpgradeReq accesses
2792system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.248982 # mshr miss rate for SCUpgradeReq accesses
2793system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585895 # mshr miss rate for SCUpgradeReq accesses
2794system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.393411 # mshr miss rate for SCUpgradeReq accesses
--- 69 unchanged lines hidden (view full) ---
2864system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
2865system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
2866system.l2c.overall_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
2867system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency
2868system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719 # average ReadReq mshr uncacheable latency
2869system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency
2870system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency
2871system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency
2872system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency
2873system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96585.204012 # average overall mshr uncacheable latency
2874system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency
2875system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 59101.307139 # average overall mshr uncacheable latency
2876system.l2c.overall_avg_mshr_uncacheable_latency::total 94714.260374 # average overall mshr uncacheable latency
2877system.membus.trans_dist::ReadReq 39041 # Transaction distribution
2878system.membus.trans_dist::ReadResp 216336 # Transaction distribution
2879system.membus.trans_dist::WriteReq 31035 # Transaction distribution
2880system.membus.trans_dist::WriteResp 31035 # Transaction distribution
2881system.membus.trans_dist::WritebackDirty 138525 # Transaction distribution
2882system.membus.trans_dist::CleanEvict 18214 # Transaction distribution
2883system.membus.trans_dist::UpgradeReq 73002 # Transaction distribution
2884system.membus.trans_dist::SCUpgradeReq 40704 # Transaction distribution
--- 136 unchanged lines hidden ---