1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.846057 # Number of seconds simulated
4sim_ticks 2846057099000 # Number of ticks simulated
5final_tick 2846057099000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 155095 # Simulator instruction rate (inst/s)
8host_op_rate 187821 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3461671389 # Simulator tick rate (ticks/s)
10host_mem_usage 654788 # Number of bytes of host memory used
11host_seconds 822.16 # Real time elapsed on the host
12sim_insts 127513349 # Number of instructions simulated
13sim_ops 154419501 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1469184 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1233972 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8227712 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 2752 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 383104 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 711064 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.l2cache.prefetcher 574528 # Number of bytes read from this memory
25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
26system.physmem.bytes_read::total 12611084 # Number of bytes read from this memory
27system.physmem.bytes_inst_read::cpu0.inst 1469184 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu1.inst 383104 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 1852288 # Number of instructions bytes read from this memory
30system.physmem.bytes_written::writebacks 8917568 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
33system.physmem.bytes_written::total 8935132 # Number of bytes written to this memory
34system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.inst 22956 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.data 19804 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.l2cache.prefetcher 128558 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.dtb.walker 43 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.inst 5986 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.data 11132 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.l2cache.prefetcher 8977 # Number of read requests responded to by this memory
43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
44system.physmem.num_reads::total 197593 # Number of read requests responded to by this memory
45system.physmem.num_writes::writebacks 139337 # Number of write requests responded to by this memory
46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
48system.physmem.num_writes::total 143728 # Number of write requests responded to by this memory
49system.physmem.bw_read::cpu0.dtb.walker 2721 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.inst 516217 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.data 433572 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.l2cache.prefetcher 2890916 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.dtb.walker 967 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.inst 134609 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.data 249842 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.l2cache.prefetcher 201868 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::total 4431072 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_inst_read::cpu0.inst 516217 # Instruction read bandwidth from this memory (bytes/s)
61system.physmem.bw_inst_read::cpu1.inst 134609 # Instruction read bandwidth from this memory (bytes/s)
62system.physmem.bw_inst_read::total 650826 # Instruction read bandwidth from this memory (bytes/s)
63system.physmem.bw_write::writebacks 3133306 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
66system.physmem.bw_write::total 3139477 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_total::writebacks 3133306 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.dtb.walker 2721 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu0.inst 516217 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.data 439730 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.l2cache.prefetcher 2890916 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu1.dtb.walker 967 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu1.inst 134609 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu1.data 249856 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.l2cache.prefetcher 201868 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::total 7570549 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.readReqs 197593 # Number of read requests accepted
80system.physmem.writeReqs 143728 # Number of write requests accepted
81system.physmem.readBursts 197593 # Number of DRAM read bursts, including those serviced by the write queue
82system.physmem.writeBursts 143728 # Number of DRAM write bursts, including those merged in the write queue
83system.physmem.bytesReadDRAM 12635520 # Total number of bytes read from DRAM
84system.physmem.bytesReadWrQ 10432 # Total number of bytes read from write queue
85system.physmem.bytesWritten 8947648 # Total number of bytes written to DRAM
86system.physmem.bytesReadSys 12611084 # Total read bytes from the system interface side
87system.physmem.bytesWrittenSys 8935132 # Total written bytes from the system interface side
88system.physmem.servicedByWrQ 163 # Number of DRAM read bursts serviced by the write queue
89system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
90system.physmem.neitherReadNorWriteReqs 51189 # Number of requests that are neither read nor write
91system.physmem.perBankRdBursts::0 12157 # Per bank write bursts
92system.physmem.perBankRdBursts::1 12292 # Per bank write bursts
93system.physmem.perBankRdBursts::2 12950 # Per bank write bursts
94system.physmem.perBankRdBursts::3 12405 # Per bank write bursts
95system.physmem.perBankRdBursts::4 15321 # Per bank write bursts
96system.physmem.perBankRdBursts::5 12434 # Per bank write bursts
97system.physmem.perBankRdBursts::6 12677 # Per bank write bursts
98system.physmem.perBankRdBursts::7 13084 # Per bank write bursts
99system.physmem.perBankRdBursts::8 12267 # Per bank write bursts
100system.physmem.perBankRdBursts::9 12426 # Per bank write bursts
101system.physmem.perBankRdBursts::10 11655 # Per bank write bursts
102system.physmem.perBankRdBursts::11 11073 # Per bank write bursts
103system.physmem.perBankRdBursts::12 11997 # Per bank write bursts
104system.physmem.perBankRdBursts::13 11769 # Per bank write bursts
105system.physmem.perBankRdBursts::14 11320 # Per bank write bursts
106system.physmem.perBankRdBursts::15 11603 # Per bank write bursts
107system.physmem.perBankWrBursts::0 8631 # Per bank write bursts
108system.physmem.perBankWrBursts::1 8804 # Per bank write bursts
109system.physmem.perBankWrBursts::2 9518 # Per bank write bursts
110system.physmem.perBankWrBursts::3 8865 # Per bank write bursts
111system.physmem.perBankWrBursts::4 8658 # Per bank write bursts
112system.physmem.perBankWrBursts::5 8780 # Per bank write bursts
113system.physmem.perBankWrBursts::6 9135 # Per bank write bursts
114system.physmem.perBankWrBursts::7 9275 # Per bank write bursts
115system.physmem.perBankWrBursts::8 8996 # Per bank write bursts
116system.physmem.perBankWrBursts::9 8951 # Per bank write bursts
117system.physmem.perBankWrBursts::10 8409 # Per bank write bursts
118system.physmem.perBankWrBursts::11 8136 # Per bank write bursts
119system.physmem.perBankWrBursts::12 8895 # Per bank write bursts
120system.physmem.perBankWrBursts::13 8304 # Per bank write bursts
121system.physmem.perBankWrBursts::14 8310 # Per bank write bursts
122system.physmem.perBankWrBursts::15 8140 # Per bank write bursts
123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
124system.physmem.numWrRetry 40 # Number of times write queue was full causing retry
125system.physmem.totGap 2846056522500 # Total gap between requests
126system.physmem.readPktSize::0 0 # Read request sizes (log2)
127system.physmem.readPktSize::1 0 # Read request sizes (log2)
128system.physmem.readPktSize::2 555 # Read request sizes (log2)
129system.physmem.readPktSize::3 28 # Read request sizes (log2)
130system.physmem.readPktSize::4 0 # Read request sizes (log2)
131system.physmem.readPktSize::5 0 # Read request sizes (log2)
132system.physmem.readPktSize::6 197010 # Read request sizes (log2)
133system.physmem.writePktSize::0 0 # Write request sizes (log2)
134system.physmem.writePktSize::1 0 # Write request sizes (log2)
135system.physmem.writePktSize::2 4391 # Write request sizes (log2)
136system.physmem.writePktSize::3 0 # Write request sizes (log2)
137system.physmem.writePktSize::4 0 # Write request sizes (log2)
138system.physmem.writePktSize::5 0 # Write request sizes (log2)
139system.physmem.writePktSize::6 139337 # Write request sizes (log2)
140system.physmem.rdQLenPdf::0 84527 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::1 62953 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::2 11439 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::3 9638 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::4 7653 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::6 5113 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::7 4583 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::8 3751 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::9 746 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::11 267 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::12 175 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
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179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::15 2731 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::16 3213 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::17 4878 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::18 5520 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::19 6053 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::20 6627 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::21 7062 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::22 8465 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::23 8859 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::24 10175 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::25 9630 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::26 9702 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::27 8882 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::28 9201 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::29 10384 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::30 8548 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::31 7940 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::32 7665 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::33 412 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::34 283 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::35 342 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::36 221 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::40 188 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::41 200 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::43 169 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::44 157 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::50 100 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::57 44 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see
236system.physmem.bytesPerActivate::samples 90385 # Bytes accessed per row activation
237system.physmem.bytesPerActivate::mean 238.790065 # Bytes accessed per row activation
238system.physmem.bytesPerActivate::gmean 135.540737 # Bytes accessed per row activation
239system.physmem.bytesPerActivate::stdev 300.321787 # Bytes accessed per row activation
240system.physmem.bytesPerActivate::0-127 48391 53.54% 53.54% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::128-255 17645 19.52% 73.06% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::256-383 6369 7.05% 80.11% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::384-511 3664 4.05% 84.16% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::512-639 2743 3.03% 87.20% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::640-767 1397 1.55% 88.74% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::768-895 884 0.98% 89.72% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::896-1023 1036 1.15% 90.87% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::1024-1151 8256 9.13% 100.00% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::total 90385 # Bytes accessed per row activation
250system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::mean 28.264567 # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::stdev 537.756673 # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::0-2047 6984 99.99% 99.99% # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes
256system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::mean 20.015319 # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::gmean 18.579154 # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::stdev 12.029266 # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::16-19 5867 83.99% 83.99% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::20-23 359 5.14% 89.13% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::24-27 198 2.83% 91.97% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::28-31 50 0.72% 92.68% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::32-35 72 1.03% 93.72% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::36-39 159 2.28% 95.99% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::40-43 19 0.27% 96.26% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::44-47 12 0.17% 96.44% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::48-51 11 0.16% 96.59% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::52-55 8 0.11% 96.71% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::56-59 6 0.09% 96.79% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::60-63 5 0.07% 96.86% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::64-67 162 2.32% 99.18% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::68-71 6 0.09% 99.27% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::72-75 6 0.09% 99.36% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::76-79 10 0.14% 99.50% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::80-83 1 0.01% 99.51% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::84-87 2 0.03% 99.54% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::88-91 2 0.03% 99.57% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::92-95 2 0.03% 99.60% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::100-103 1 0.01% 99.61% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::108-111 1 0.01% 99.64% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::128-131 14 0.20% 99.86% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::132-135 1 0.01% 99.87% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::164-167 4 0.06% 99.96% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads
291system.physmem.totQLat 5478181174 # Total ticks spent queuing
292system.physmem.totMemAccLat 9179993674 # Total ticks spent from burst creation until serviced by the DRAM
293system.physmem.totBusLat 987150000 # Total ticks spent in databus transfers
294system.physmem.avgQLat 27747.46 # Average queueing delay per DRAM burst
295system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
296system.physmem.avgMemAccLat 46497.46 # Average memory access latency per DRAM burst
297system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s
298system.physmem.avgWrBW 3.14 # Average achieved write bandwidth in MiByte/s
299system.physmem.avgRdBWSys 4.43 # Average system read bandwidth in MiByte/s
300system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s
301system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
302system.physmem.busUtil 0.06 # Data bus utilization in percentage
303system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
304system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
305system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
306system.physmem.avgWrQLen 23.99 # Average write queue length when enqueuing
307system.physmem.readRowHits 164056 # Number of row buffer hits during reads
308system.physmem.writeRowHits 82794 # Number of row buffer hits during writes
309system.physmem.readRowHitRate 83.10 # Row buffer hit rate for reads
310system.physmem.writeRowHitRate 59.21 # Row buffer hit rate for writes
311system.physmem.avgGap 8338357.51 # Average gap between requests
312system.physmem.pageHitRate 73.19 # Row buffer hit rate, read and write combined
313system.physmem_0.actEnergy 356771520 # Energy for activate commands per rank (pJ)
314system.physmem_0.preEnergy 194667000 # Energy for precharge commands per rank (pJ)
315system.physmem_0.readEnergy 805888200 # Energy for read commands per rank (pJ)
316system.physmem_0.writeEnergy 464395680 # Energy for write commands per rank (pJ)
317system.physmem_0.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ)
318system.physmem_0.actBackEnergy 83219414895 # Energy for active background per rank (pJ)
319system.physmem_0.preBackEnergy 1634632736250 # Energy for precharge background per rank (pJ)
320system.physmem_0.totalEnergy 1905564250425 # Total energy per rank (pJ)
321system.physmem_0.averagePower 669.546132 # Core power per rank (mW)
322system.physmem_0.memoryStateTime::IDLE 2719229075521 # Time in different power states
323system.physmem_0.memoryStateTime::REF 95035980000 # Time in different power states
324system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
325system.physmem_0.memoryStateTime::ACT 31791929979 # Time in different power states
326system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
327system.physmem_1.actEnergy 326539080 # Energy for activate commands per rank (pJ)
328system.physmem_1.preEnergy 178171125 # Energy for precharge commands per rank (pJ)
329system.physmem_1.readEnergy 734050200 # Energy for read commands per rank (pJ)
330system.physmem_1.writeEnergy 441553680 # Energy for write commands per rank (pJ)
331system.physmem_1.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ)
332system.physmem_1.actBackEnergy 82136174355 # Energy for active background per rank (pJ)
333system.physmem_1.preBackEnergy 1635582947250 # Energy for precharge background per rank (pJ)
334system.physmem_1.totalEnergy 1905289812570 # Total energy per rank (pJ)
335system.physmem_1.averagePower 669.449705 # Core power per rank (mW)
336system.physmem_1.memoryStateTime::IDLE 2720812978493 # Time in different power states
337system.physmem_1.memoryStateTime::REF 95035980000 # Time in different power states
338system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
339system.physmem_1.memoryStateTime::ACT 30205644507 # Time in different power states
340system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
341system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
342system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
343system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory
344system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory
345system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory
346system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
347system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory

--- 9 unchanged lines hidden (view full) ---

357system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
358system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
359system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
360system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
361system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
362system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
363system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
364system.cf0.dma_write_txs 631 # Number of DMA write transactions.
365system.cpu0.branchPred.lookups 19599196 # Number of BP lookups
366system.cpu0.branchPred.condPredicted 12768904 # Number of conditional branches predicted
367system.cpu0.branchPred.condIncorrect 991514 # Number of conditional branches incorrect
368system.cpu0.branchPred.BTBLookups 12558764 # Number of BTB lookups
369system.cpu0.branchPred.BTBHits 8839837 # Number of BTB hits
370system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
371system.cpu0.branchPred.BTBHitPct 70.387795 # BTB Hit Percentage
372system.cpu0.branchPred.usedRAS 3295346 # Number of times the RAS was used to get a target.
373system.cpu0.branchPred.RASInCorrect 199810 # Number of incorrect RAS predictions.
374system.cpu_clk_domain.clock 500 # Clock period in ticks
375system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

396system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
397system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
398system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
399system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
400system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
401system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
402system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
403system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
404system.cpu0.dtb.walker.walks 67395 # Table walker walks requested
405system.cpu0.dtb.walker.walksShort 67395 # Table walker walks initiated with short descriptors
406system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44710 # Level at which table walker walks with short descriptors terminate
407system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22685 # Level at which table walker walks with short descriptors terminate
408system.cpu0.dtb.walker.walkWaitTime::samples 67395 # Table walker wait (enqueue to first request) latency
409system.cpu0.dtb.walker.walkWaitTime::0 67395 100.00% 100.00% # Table walker wait (enqueue to first request) latency
410system.cpu0.dtb.walker.walkWaitTime::total 67395 # Table walker wait (enqueue to first request) latency
411system.cpu0.dtb.walker.walkCompletionTime::samples 6692 # Table walker service (enqueue to completion) latency
412system.cpu0.dtb.walker.walkCompletionTime::mean 10409.593545 # Table walker service (enqueue to completion) latency
413system.cpu0.dtb.walker.walkCompletionTime::gmean 9352.624092 # Table walker service (enqueue to completion) latency
414system.cpu0.dtb.walker.walkCompletionTime::stdev 5969.180600 # Table walker service (enqueue to completion) latency
415system.cpu0.dtb.walker.walkCompletionTime::0-16383 6501 97.15% 97.15% # Table walker service (enqueue to completion) latency
416system.cpu0.dtb.walker.walkCompletionTime::16384-32767 173 2.59% 99.73% # Table walker service (enqueue to completion) latency
417system.cpu0.dtb.walker.walkCompletionTime::32768-49151 11 0.16% 99.90% # Table walker service (enqueue to completion) latency
418system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.97% # Table walker service (enqueue to completion) latency
419system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
420system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
421system.cpu0.dtb.walker.walkCompletionTime::total 6692 # Table walker service (enqueue to completion) latency
422system.cpu0.dtb.walker.walksPending::samples 327753000 # Table walker pending requests distribution
423system.cpu0.dtb.walker.walksPending::0 327753000 100.00% 100.00% # Table walker pending requests distribution
424system.cpu0.dtb.walker.walksPending::total 327753000 # Table walker pending requests distribution
425system.cpu0.dtb.walker.walkPageSizes::4K 5137 76.76% 76.76% # Table walker page sizes translated
426system.cpu0.dtb.walker.walkPageSizes::1M 1555 23.24% 100.00% # Table walker page sizes translated
427system.cpu0.dtb.walker.walkPageSizes::total 6692 # Table walker page sizes translated
428system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67395 # Table walker requests started/completed, data/inst
429system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
430system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67395 # Table walker requests started/completed, data/inst
431system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6692 # Table walker requests started/completed, data/inst
432system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
433system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6692 # Table walker requests started/completed, data/inst
434system.cpu0.dtb.walker.walkRequestOrigin::total 74087 # Table walker requests started/completed, data/inst
435system.cpu0.dtb.inst_hits 0 # ITB inst hits
436system.cpu0.dtb.inst_misses 0 # ITB inst misses
437system.cpu0.dtb.read_hits 16492967 # DTB read hits
438system.cpu0.dtb.read_misses 61485 # DTB read misses
439system.cpu0.dtb.write_hits 13879033 # DTB write hits
440system.cpu0.dtb.write_misses 5910 # DTB write misses
441system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
442system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
443system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
444system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
445system.cpu0.dtb.flush_entries 3512 # Number of entries that have been flushed from TLB
446system.cpu0.dtb.align_faults 1104 # Number of TLB faults due to alignment restrictions
447system.cpu0.dtb.prefetch_faults 1584 # Number of TLB faults due to prefetch
448system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
449system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
450system.cpu0.dtb.read_accesses 16554452 # DTB read accesses
451system.cpu0.dtb.write_accesses 13884943 # DTB write accesses
452system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
453system.cpu0.dtb.hits 30372000 # DTB hits
454system.cpu0.dtb.misses 67395 # DTB misses
455system.cpu0.dtb.accesses 30439395 # DTB accesses
456system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

477system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
478system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
479system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
480system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
481system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
482system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
483system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
484system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
485system.cpu0.itb.walker.walks 3867 # Table walker walks requested
486system.cpu0.itb.walker.walksShort 3867 # Table walker walks initiated with short descriptors
487system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate
488system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate
489system.cpu0.itb.walker.walkWaitTime::samples 3867 # Table walker wait (enqueue to first request) latency
490system.cpu0.itb.walker.walkWaitTime::0 3867 100.00% 100.00% # Table walker wait (enqueue to first request) latency
491system.cpu0.itb.walker.walkWaitTime::total 3867 # Table walker wait (enqueue to first request) latency
492system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency
493system.cpu0.itb.walker.walkCompletionTime::mean 10756.092524 # Table walker service (enqueue to completion) latency
494system.cpu0.itb.walker.walkCompletionTime::gmean 9615.276250 # Table walker service (enqueue to completion) latency
495system.cpu0.itb.walker.walkCompletionTime::stdev 7885.681727 # Table walker service (enqueue to completion) latency
496system.cpu0.itb.walker.walkCompletionTime::0-32767 2419 99.92% 99.92% # Table walker service (enqueue to completion) latency
497system.cpu0.itb.walker.walkCompletionTime::32768-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
498system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
499system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency
500system.cpu0.itb.walker.walksPending::samples 327059500 # Table walker pending requests distribution
501system.cpu0.itb.walker.walksPending::0 327059500 100.00% 100.00% # Table walker pending requests distribution
502system.cpu0.itb.walker.walksPending::total 327059500 # Table walker pending requests distribution
503system.cpu0.itb.walker.walkPageSizes::4K 2121 87.61% 87.61% # Table walker page sizes translated
504system.cpu0.itb.walker.walkPageSizes::1M 300 12.39% 100.00% # Table walker page sizes translated
505system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated
506system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
507system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3867 # Table walker requests started/completed, data/inst
508system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3867 # Table walker requests started/completed, data/inst
509system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
510system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst
511system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst
512system.cpu0.itb.walker.walkRequestOrigin::total 6288 # Table walker requests started/completed, data/inst
513system.cpu0.itb.inst_hits 36759532 # ITB inst hits
514system.cpu0.itb.inst_misses 3867 # ITB inst misses
515system.cpu0.itb.read_hits 0 # DTB read hits
516system.cpu0.itb.read_misses 0 # DTB read misses
517system.cpu0.itb.write_hits 0 # DTB write hits
518system.cpu0.itb.write_misses 0 # DTB write misses
519system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
520system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
521system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
522system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
523system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB
524system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
525system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
526system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
527system.cpu0.itb.perms_faults 7295 # Number of TLB faults due to permissions restrictions
528system.cpu0.itb.read_accesses 0 # DTB read accesses
529system.cpu0.itb.write_accesses 0 # DTB write accesses
530system.cpu0.itb.inst_accesses 36763399 # ITB inst accesses
531system.cpu0.itb.hits 36759532 # DTB hits
532system.cpu0.itb.misses 3867 # DTB misses
533system.cpu0.itb.accesses 36763399 # DTB accesses
534system.cpu0.numCycles 154883476 # number of cpu cycles simulated
535system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
536system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
537system.cpu0.committedInsts 75627253 # Number of instructions committed
538system.cpu0.committedOps 91033342 # Number of ops (including micro ops) committed
539system.cpu0.discardedOps 4957970 # Number of ops (including micro ops) which were discarded before commit
540system.cpu0.numFetchSuspends 2062 # Number of times Execute suspended instruction fetching
541system.cpu0.quiesceCycles 5537267530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
542system.cpu0.cpi 2.047985 # CPI: cycles per instruction
543system.cpu0.ipc 0.488285 # IPC: instructions per cycle
544system.cpu0.kern.inst.arm 0 # number of arm instructions executed
545system.cpu0.kern.inst.quiesce 2064 # number of quiesce instructions executed
546system.cpu0.tickCycles 121009607 # Number of cycles that the object actually ticked
547system.cpu0.idleCycles 33873869 # Total number of cycles that the object has spent stopped
548system.cpu0.dcache.tags.replacements 680149 # number of replacements
549system.cpu0.dcache.tags.tagsinuse 489.017964 # Cycle average of tags in use
550system.cpu0.dcache.tags.total_refs 28930962 # Total number of references to valid blocks.
551system.cpu0.dcache.tags.sampled_refs 680661 # Sample count of references to valid blocks.
552system.cpu0.dcache.tags.avg_refs 42.504216 # Average number of references to valid blocks.
553system.cpu0.dcache.tags.warmup_cycle 345600000 # Cycle when the warmup percentage was hit.
554system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.017964 # Average occupied blocks per requestor
555system.cpu0.dcache.tags.occ_percent::cpu0.data 0.955113 # Average percentage of cache occupancy
556system.cpu0.dcache.tags.occ_percent::total 0.955113 # Average percentage of cache occupancy
557system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
558system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
559system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
560system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
561system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
562system.cpu0.dcache.tags.tag_accesses 60723709 # Number of tag accesses
563system.cpu0.dcache.tags.data_accesses 60723709 # Number of data accesses
564system.cpu0.dcache.ReadReq_hits::cpu0.data 15008806 # number of ReadReq hits
565system.cpu0.dcache.ReadReq_hits::total 15008806 # number of ReadReq hits
566system.cpu0.dcache.WriteReq_hits::cpu0.data 12795540 # number of WriteReq hits
567system.cpu0.dcache.WriteReq_hits::total 12795540 # number of WriteReq hits
568system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306691 # number of SoftPFReq hits
569system.cpu0.dcache.SoftPFReq_hits::total 306691 # number of SoftPFReq hits
570system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356713 # number of LoadLockedReq hits
571system.cpu0.dcache.LoadLockedReq_hits::total 356713 # number of LoadLockedReq hits
572system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352309 # number of StoreCondReq hits
573system.cpu0.dcache.StoreCondReq_hits::total 352309 # number of StoreCondReq hits
574system.cpu0.dcache.demand_hits::cpu0.data 27804346 # number of demand (read+write) hits
575system.cpu0.dcache.demand_hits::total 27804346 # number of demand (read+write) hits
576system.cpu0.dcache.overall_hits::cpu0.data 28111037 # number of overall hits
577system.cpu0.dcache.overall_hits::total 28111037 # number of overall hits
578system.cpu0.dcache.ReadReq_misses::cpu0.data 442745 # number of ReadReq misses
579system.cpu0.dcache.ReadReq_misses::total 442745 # number of ReadReq misses
580system.cpu0.dcache.WriteReq_misses::cpu0.data 557072 # number of WriteReq misses
581system.cpu0.dcache.WriteReq_misses::total 557072 # number of WriteReq misses
582system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131875 # number of SoftPFReq misses
583system.cpu0.dcache.SoftPFReq_misses::total 131875 # number of SoftPFReq misses
584system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21262 # number of LoadLockedReq misses
585system.cpu0.dcache.LoadLockedReq_misses::total 21262 # number of LoadLockedReq misses
586system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21236 # number of StoreCondReq misses
587system.cpu0.dcache.StoreCondReq_misses::total 21236 # number of StoreCondReq misses
588system.cpu0.dcache.demand_misses::cpu0.data 999817 # number of demand (read+write) misses
589system.cpu0.dcache.demand_misses::total 999817 # number of demand (read+write) misses
590system.cpu0.dcache.overall_misses::cpu0.data 1131692 # number of overall misses
591system.cpu0.dcache.overall_misses::total 1131692 # number of overall misses
592system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5845429500 # number of ReadReq miss cycles
593system.cpu0.dcache.ReadReq_miss_latency::total 5845429500 # number of ReadReq miss cycles
594system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8925410000 # number of WriteReq miss cycles
595system.cpu0.dcache.WriteReq_miss_latency::total 8925410000 # number of WriteReq miss cycles
596system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 323710500 # number of LoadLockedReq miss cycles
597system.cpu0.dcache.LoadLockedReq_miss_latency::total 323710500 # number of LoadLockedReq miss cycles
598system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 479970000 # number of StoreCondReq miss cycles
599system.cpu0.dcache.StoreCondReq_miss_latency::total 479970000 # number of StoreCondReq miss cycles
600system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 445000 # number of StoreCondFailReq miss cycles
601system.cpu0.dcache.StoreCondFailReq_miss_latency::total 445000 # number of StoreCondFailReq miss cycles
602system.cpu0.dcache.demand_miss_latency::cpu0.data 14770839500 # number of demand (read+write) miss cycles
603system.cpu0.dcache.demand_miss_latency::total 14770839500 # number of demand (read+write) miss cycles
604system.cpu0.dcache.overall_miss_latency::cpu0.data 14770839500 # number of overall miss cycles
605system.cpu0.dcache.overall_miss_latency::total 14770839500 # number of overall miss cycles
606system.cpu0.dcache.ReadReq_accesses::cpu0.data 15451551 # number of ReadReq accesses(hits+misses)
607system.cpu0.dcache.ReadReq_accesses::total 15451551 # number of ReadReq accesses(hits+misses)
608system.cpu0.dcache.WriteReq_accesses::cpu0.data 13352612 # number of WriteReq accesses(hits+misses)
609system.cpu0.dcache.WriteReq_accesses::total 13352612 # number of WriteReq accesses(hits+misses)
610system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438566 # number of SoftPFReq accesses(hits+misses)
611system.cpu0.dcache.SoftPFReq_accesses::total 438566 # number of SoftPFReq accesses(hits+misses)
612system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377975 # number of LoadLockedReq accesses(hits+misses)
613system.cpu0.dcache.LoadLockedReq_accesses::total 377975 # number of LoadLockedReq accesses(hits+misses)
614system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373545 # number of StoreCondReq accesses(hits+misses)
615system.cpu0.dcache.StoreCondReq_accesses::total 373545 # number of StoreCondReq accesses(hits+misses)
616system.cpu0.dcache.demand_accesses::cpu0.data 28804163 # number of demand (read+write) accesses
617system.cpu0.dcache.demand_accesses::total 28804163 # number of demand (read+write) accesses
618system.cpu0.dcache.overall_accesses::cpu0.data 29242729 # number of overall (read+write) accesses
619system.cpu0.dcache.overall_accesses::total 29242729 # number of overall (read+write) accesses
620system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028654 # miss rate for ReadReq accesses
621system.cpu0.dcache.ReadReq_miss_rate::total 0.028654 # miss rate for ReadReq accesses
622system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041720 # miss rate for WriteReq accesses
623system.cpu0.dcache.WriteReq_miss_rate::total 0.041720 # miss rate for WriteReq accesses
624system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300696 # miss rate for SoftPFReq accesses
625system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300696 # miss rate for SoftPFReq accesses
626system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056252 # miss rate for LoadLockedReq accesses
627system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056252 # miss rate for LoadLockedReq accesses
628system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056850 # miss rate for StoreCondReq accesses
629system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056850 # miss rate for StoreCondReq accesses
630system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034711 # miss rate for demand accesses
631system.cpu0.dcache.demand_miss_rate::total 0.034711 # miss rate for demand accesses
632system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038700 # miss rate for overall accesses
633system.cpu0.dcache.overall_miss_rate::total 0.038700 # miss rate for overall accesses
634system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13202.700200 # average ReadReq miss latency
635system.cpu0.dcache.ReadReq_avg_miss_latency::total 13202.700200 # average ReadReq miss latency
636system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16022.004337 # average WriteReq miss latency
637system.cpu0.dcache.WriteReq_avg_miss_latency::total 16022.004337 # average WriteReq miss latency
638system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15224.837739 # average LoadLockedReq miss latency
639system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15224.837739 # average LoadLockedReq miss latency
640system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22601.714070 # average StoreCondReq miss latency
641system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22601.714070 # average StoreCondReq miss latency
642system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
643system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
644system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14773.543058 # average overall miss latency
645system.cpu0.dcache.demand_avg_miss_latency::total 14773.543058 # average overall miss latency
646system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.996038 # average overall miss latency
647system.cpu0.dcache.overall_avg_miss_latency::total 13051.996038 # average overall miss latency
648system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
649system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
650system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
651system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
652system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
653system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
654system.cpu0.dcache.fast_writes 0 # number of fast writes performed
655system.cpu0.dcache.cache_copies 0 # number of cache copies performed
656system.cpu0.dcache.writebacks::writebacks 493052 # number of writebacks
657system.cpu0.dcache.writebacks::total 493052 # number of writebacks
658system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69962 # number of ReadReq MSHR hits
659system.cpu0.dcache.ReadReq_mshr_hits::total 69962 # number of ReadReq MSHR hits
660system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244118 # number of WriteReq MSHR hits
661system.cpu0.dcache.WriteReq_mshr_hits::total 244118 # number of WriteReq MSHR hits
662system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15072 # number of LoadLockedReq MSHR hits
663system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15072 # number of LoadLockedReq MSHR hits
664system.cpu0.dcache.demand_mshr_hits::cpu0.data 314080 # number of demand (read+write) MSHR hits
665system.cpu0.dcache.demand_mshr_hits::total 314080 # number of demand (read+write) MSHR hits
666system.cpu0.dcache.overall_mshr_hits::cpu0.data 314080 # number of overall MSHR hits
667system.cpu0.dcache.overall_mshr_hits::total 314080 # number of overall MSHR hits
668system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372783 # number of ReadReq MSHR misses
669system.cpu0.dcache.ReadReq_mshr_misses::total 372783 # number of ReadReq MSHR misses
670system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312954 # number of WriteReq MSHR misses
671system.cpu0.dcache.WriteReq_mshr_misses::total 312954 # number of WriteReq MSHR misses
672system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99314 # number of SoftPFReq MSHR misses
673system.cpu0.dcache.SoftPFReq_mshr_misses::total 99314 # number of SoftPFReq MSHR misses
674system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6190 # number of LoadLockedReq MSHR misses
675system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6190 # number of LoadLockedReq MSHR misses
676system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21236 # number of StoreCondReq MSHR misses
677system.cpu0.dcache.StoreCondReq_mshr_misses::total 21236 # number of StoreCondReq MSHR misses
678system.cpu0.dcache.demand_mshr_misses::cpu0.data 685737 # number of demand (read+write) MSHR misses
679system.cpu0.dcache.demand_mshr_misses::total 685737 # number of demand (read+write) MSHR misses
680system.cpu0.dcache.overall_mshr_misses::cpu0.data 785051 # number of overall MSHR misses
681system.cpu0.dcache.overall_mshr_misses::total 785051 # number of overall MSHR misses
682system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable
683system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18001 # number of ReadReq MSHR uncacheable
684system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16756 # number of WriteReq MSHR uncacheable
685system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16756 # number of WriteReq MSHR uncacheable
686system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34757 # number of overall MSHR uncacheable misses
687system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34757 # number of overall MSHR uncacheable misses
688system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4391149500 # number of ReadReq MSHR miss cycles
689system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4391149500 # number of ReadReq MSHR miss cycles
690system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4970740000 # number of WriteReq MSHR miss cycles
691system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4970740000 # number of WriteReq MSHR miss cycles
692system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1612906500 # number of SoftPFReq MSHR miss cycles
693system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1612906500 # number of SoftPFReq MSHR miss cycles
694system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94756000 # number of LoadLockedReq MSHR miss cycles
695system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94756000 # number of LoadLockedReq MSHR miss cycles
696system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 458745000 # number of StoreCondReq MSHR miss cycles
697system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458745000 # number of StoreCondReq MSHR miss cycles
698system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 434000 # number of StoreCondFailReq MSHR miss cycles
699system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 434000 # number of StoreCondFailReq MSHR miss cycles
700system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9361889500 # number of demand (read+write) MSHR miss cycles
701system.cpu0.dcache.demand_mshr_miss_latency::total 9361889500 # number of demand (read+write) MSHR miss cycles
702system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10974796000 # number of overall MSHR miss cycles
703system.cpu0.dcache.overall_mshr_miss_latency::total 10974796000 # number of overall MSHR miss cycles
704system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3751362500 # number of ReadReq MSHR uncacheable cycles
705system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3751362500 # number of ReadReq MSHR uncacheable cycles
706system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2725552500 # number of WriteReq MSHR uncacheable cycles
707system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725552500 # number of WriteReq MSHR uncacheable cycles
708system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6476915000 # number of overall MSHR uncacheable cycles
709system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6476915000 # number of overall MSHR uncacheable cycles
710system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024126 # mshr miss rate for ReadReq accesses
711system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024126 # mshr miss rate for ReadReq accesses
712system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023438 # mshr miss rate for WriteReq accesses
713system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023438 # mshr miss rate for WriteReq accesses
714system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226452 # mshr miss rate for SoftPFReq accesses
715system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226452 # mshr miss rate for SoftPFReq accesses
716system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016377 # mshr miss rate for LoadLockedReq accesses
717system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016377 # mshr miss rate for LoadLockedReq accesses
718system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056850 # mshr miss rate for StoreCondReq accesses
719system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056850 # mshr miss rate for StoreCondReq accesses
720system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023807 # mshr miss rate for demand accesses
721system.cpu0.dcache.demand_mshr_miss_rate::total 0.023807 # mshr miss rate for demand accesses
722system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026846 # mshr miss rate for overall accesses
723system.cpu0.dcache.overall_mshr_miss_rate::total 0.026846 # mshr miss rate for overall accesses
724system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11779.371645 # average ReadReq mshr miss latency
725system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11779.371645 # average ReadReq mshr miss latency
726system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15883.292752 # average WriteReq mshr miss latency
727system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15883.292752 # average WriteReq mshr miss latency
728system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16240.474656 # average SoftPFReq mshr miss latency
729system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16240.474656 # average SoftPFReq mshr miss latency
730system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15307.915994 # average LoadLockedReq mshr miss latency
731system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15307.915994 # average LoadLockedReq mshr miss latency
732system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21602.232059 # average StoreCondReq mshr miss latency
733system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21602.232059 # average StoreCondReq mshr miss latency
734system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
735system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
736system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13652.303288 # average overall mshr miss latency
737system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13652.303288 # average overall mshr miss latency
738system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13979.723610 # average overall mshr miss latency
739system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13979.723610 # average overall mshr miss latency
740system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208397.450142 # average ReadReq mshr uncacheable latency
741system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208397.450142 # average ReadReq mshr uncacheable latency
742system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162661.285510 # average WriteReq mshr uncacheable latency
743system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162661.285510 # average WriteReq mshr uncacheable latency
744system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186348.505337 # average overall mshr uncacheable latency
745system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186348.505337 # average overall mshr uncacheable latency
746system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
747system.cpu0.icache.tags.replacements 1879741 # number of replacements
748system.cpu0.icache.tags.tagsinuse 511.785261 # Cycle average of tags in use
749system.cpu0.icache.tags.total_refs 34871642 # Total number of references to valid blocks.
750system.cpu0.icache.tags.sampled_refs 1880253 # Sample count of references to valid blocks.
751system.cpu0.icache.tags.avg_refs 18.546250 # Average number of references to valid blocks.
752system.cpu0.icache.tags.warmup_cycle 6165545000 # Cycle when the warmup percentage was hit.
753system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785261 # Average occupied blocks per requestor
754system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999581 # Average percentage of cache occupancy
755system.cpu0.icache.tags.occ_percent::total 0.999581 # Average percentage of cache occupancy
756system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
757system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
758system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
759system.cpu0.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
760system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
761system.cpu0.icache.tags.tag_accesses 75384087 # Number of tag accesses
762system.cpu0.icache.tags.data_accesses 75384087 # Number of data accesses
763system.cpu0.icache.ReadReq_hits::cpu0.inst 34871642 # number of ReadReq hits
764system.cpu0.icache.ReadReq_hits::total 34871642 # number of ReadReq hits
765system.cpu0.icache.demand_hits::cpu0.inst 34871642 # number of demand (read+write) hits
766system.cpu0.icache.demand_hits::total 34871642 # number of demand (read+write) hits
767system.cpu0.icache.overall_hits::cpu0.inst 34871642 # number of overall hits
768system.cpu0.icache.overall_hits::total 34871642 # number of overall hits
769system.cpu0.icache.ReadReq_misses::cpu0.inst 1880268 # number of ReadReq misses
770system.cpu0.icache.ReadReq_misses::total 1880268 # number of ReadReq misses
771system.cpu0.icache.demand_misses::cpu0.inst 1880268 # number of demand (read+write) misses
772system.cpu0.icache.demand_misses::total 1880268 # number of demand (read+write) misses
773system.cpu0.icache.overall_misses::cpu0.inst 1880268 # number of overall misses
774system.cpu0.icache.overall_misses::total 1880268 # number of overall misses
775system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17494991000 # number of ReadReq miss cycles
776system.cpu0.icache.ReadReq_miss_latency::total 17494991000 # number of ReadReq miss cycles
777system.cpu0.icache.demand_miss_latency::cpu0.inst 17494991000 # number of demand (read+write) miss cycles
778system.cpu0.icache.demand_miss_latency::total 17494991000 # number of demand (read+write) miss cycles
779system.cpu0.icache.overall_miss_latency::cpu0.inst 17494991000 # number of overall miss cycles
780system.cpu0.icache.overall_miss_latency::total 17494991000 # number of overall miss cycles
781system.cpu0.icache.ReadReq_accesses::cpu0.inst 36751910 # number of ReadReq accesses(hits+misses)
782system.cpu0.icache.ReadReq_accesses::total 36751910 # number of ReadReq accesses(hits+misses)
783system.cpu0.icache.demand_accesses::cpu0.inst 36751910 # number of demand (read+write) accesses
784system.cpu0.icache.demand_accesses::total 36751910 # number of demand (read+write) accesses
785system.cpu0.icache.overall_accesses::cpu0.inst 36751910 # number of overall (read+write) accesses
786system.cpu0.icache.overall_accesses::total 36751910 # number of overall (read+write) accesses
787system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051161 # miss rate for ReadReq accesses
788system.cpu0.icache.ReadReq_miss_rate::total 0.051161 # miss rate for ReadReq accesses
789system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051161 # miss rate for demand accesses
790system.cpu0.icache.demand_miss_rate::total 0.051161 # miss rate for demand accesses
791system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051161 # miss rate for overall accesses
792system.cpu0.icache.overall_miss_rate::total 0.051161 # miss rate for overall accesses
793system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9304.519888 # average ReadReq miss latency
794system.cpu0.icache.ReadReq_avg_miss_latency::total 9304.519888 # average ReadReq miss latency
795system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency
796system.cpu0.icache.demand_avg_miss_latency::total 9304.519888 # average overall miss latency
797system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency
798system.cpu0.icache.overall_avg_miss_latency::total 9304.519888 # average overall miss latency
799system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
800system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
801system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
802system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
803system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
804system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
805system.cpu0.icache.fast_writes 0 # number of fast writes performed
806system.cpu0.icache.cache_copies 0 # number of cache copies performed
807system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1880268 # number of ReadReq MSHR misses
808system.cpu0.icache.ReadReq_mshr_misses::total 1880268 # number of ReadReq MSHR misses
809system.cpu0.icache.demand_mshr_misses::cpu0.inst 1880268 # number of demand (read+write) MSHR misses
810system.cpu0.icache.demand_mshr_misses::total 1880268 # number of demand (read+write) MSHR misses
811system.cpu0.icache.overall_mshr_misses::cpu0.inst 1880268 # number of overall MSHR misses
812system.cpu0.icache.overall_mshr_misses::total 1880268 # number of overall MSHR misses
813system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
814system.cpu0.icache.ReadReq_mshr_uncacheable::total 3426 # number of ReadReq MSHR uncacheable
815system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
816system.cpu0.icache.overall_mshr_uncacheable_misses::total 3426 # number of overall MSHR uncacheable misses
817system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16554857500 # number of ReadReq MSHR miss cycles
818system.cpu0.icache.ReadReq_mshr_miss_latency::total 16554857500 # number of ReadReq MSHR miss cycles
819system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16554857500 # number of demand (read+write) MSHR miss cycles
820system.cpu0.icache.demand_mshr_miss_latency::total 16554857500 # number of demand (read+write) MSHR miss cycles
821system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16554857500 # number of overall MSHR miss cycles
822system.cpu0.icache.overall_mshr_miss_latency::total 16554857500 # number of overall MSHR miss cycles
823system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 314279000 # number of ReadReq MSHR uncacheable cycles
824system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 314279000 # number of ReadReq MSHR uncacheable cycles
825system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 314279000 # number of overall MSHR uncacheable cycles
826system.cpu0.icache.overall_mshr_uncacheable_latency::total 314279000 # number of overall MSHR uncacheable cycles
827system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for ReadReq accesses
828system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051161 # mshr miss rate for ReadReq accesses
829system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for demand accesses
830system.cpu0.icache.demand_mshr_miss_rate::total 0.051161 # mshr miss rate for demand accesses
831system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for overall accesses
832system.cpu0.icache.overall_mshr_miss_rate::total 0.051161 # mshr miss rate for overall accesses
833system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average ReadReq mshr miss latency
834system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8804.520154 # average ReadReq mshr miss latency
835system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency
836system.cpu0.icache.demand_avg_mshr_miss_latency::total 8804.520154 # average overall mshr miss latency
837system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency
838system.cpu0.icache.overall_avg_mshr_miss_latency::total 8804.520154 # average overall mshr miss latency
839system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average ReadReq mshr uncacheable latency
840system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91733.508465 # average ReadReq mshr uncacheable latency
841system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91733.508465 # average overall mshr uncacheable latency
842system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91733.508465 # average overall mshr uncacheable latency
843system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
844system.cpu0.l2cache.prefetcher.num_hwpf_issued 1762988 # number of hwpf issued
845system.cpu0.l2cache.prefetcher.pfIdentified 1763146 # number of prefetch candidates identified
846system.cpu0.l2cache.prefetcher.pfBufferHit 137 # number of redundant prefetches already in prefetch queue
847system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
848system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
849system.cpu0.l2cache.prefetcher.pfSpanPage 223158 # number of prefetches not generated due to page crossing
850system.cpu0.l2cache.tags.replacements 285163 # number of replacements
851system.cpu0.l2cache.tags.tagsinuse 16064.441291 # Cycle average of tags in use
852system.cpu0.l2cache.tags.total_refs 4801094 # Total number of references to valid blocks.
853system.cpu0.l2cache.tags.sampled_refs 301400 # Sample count of references to valid blocks.
854system.cpu0.l2cache.tags.avg_refs 15.929310 # Average number of references to valid blocks.
855system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
856system.cpu0.l2cache.tags.occ_blocks::writebacks 8613.892017 # Average occupied blocks per requestor
857system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 45.679204 # Average occupied blocks per requestor
858system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.072727 # Average occupied blocks per requestor
859system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4663.239886 # Average occupied blocks per requestor
860system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1620.721287 # Average occupied blocks per requestor
861system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1120.836170 # Average occupied blocks per requestor
862system.cpu0.l2cache.tags.occ_percent::writebacks 0.525750 # Average percentage of cache occupancy
863system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002788 # Average percentage of cache occupancy
864system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
865system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.284622 # Average percentage of cache occupancy
866system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.098921 # Average percentage of cache occupancy
867system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068410 # Average percentage of cache occupancy
868system.cpu0.l2cache.tags.occ_percent::total 0.980496 # Average percentage of cache occupancy
869system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id
870system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
871system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15199 # Occupied blocks per task id
872system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
873system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 305 # Occupied blocks per task id
874system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 401 # Occupied blocks per task id
875system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 310 # Occupied blocks per task id
876system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
877system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
878system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
879system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
880system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
881system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4239 # Occupied blocks per task id
882system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7941 # Occupied blocks per task id
883system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2698 # Occupied blocks per task id
884system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id
885system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
886system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927673 # Percentage of cache occupancy per task id
887system.cpu0.l2cache.tags.tag_accesses 85389688 # Number of tag accesses
888system.cpu0.l2cache.tags.data_accesses 85389688 # Number of data accesses
889system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78899 # number of ReadReq hits
890system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4233 # number of ReadReq hits
891system.cpu0.l2cache.ReadReq_hits::total 83132 # number of ReadReq hits
892system.cpu0.l2cache.Writeback_hits::writebacks 493050 # number of Writeback hits
893system.cpu0.l2cache.Writeback_hits::total 493050 # number of Writeback hits
894system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28200 # number of UpgradeReq hits
895system.cpu0.l2cache.UpgradeReq_hits::total 28200 # number of UpgradeReq hits
896system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1701 # number of SCUpgradeReq hits
897system.cpu0.l2cache.SCUpgradeReq_hits::total 1701 # number of SCUpgradeReq hits
898system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212815 # number of ReadExReq hits
899system.cpu0.l2cache.ReadExReq_hits::total 212815 # number of ReadExReq hits
900system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1816263 # number of ReadCleanReq hits
901system.cpu0.l2cache.ReadCleanReq_hits::total 1816263 # number of ReadCleanReq hits
902system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 377267 # number of ReadSharedReq hits
903system.cpu0.l2cache.ReadSharedReq_hits::total 377267 # number of ReadSharedReq hits
904system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 78899 # number of demand (read+write) hits
905system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4233 # number of demand (read+write) hits
906system.cpu0.l2cache.demand_hits::cpu0.inst 1816263 # number of demand (read+write) hits
907system.cpu0.l2cache.demand_hits::cpu0.data 590082 # number of demand (read+write) hits
908system.cpu0.l2cache.demand_hits::total 2489477 # number of demand (read+write) hits
909system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 78899 # number of overall hits
910system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4233 # number of overall hits
911system.cpu0.l2cache.overall_hits::cpu0.inst 1816263 # number of overall hits
912system.cpu0.l2cache.overall_hits::cpu0.data 590082 # number of overall hits
913system.cpu0.l2cache.overall_hits::total 2489477 # number of overall hits
914system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 767 # number of ReadReq misses
915system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 105 # number of ReadReq misses
916system.cpu0.l2cache.ReadReq_misses::total 872 # number of ReadReq misses
917system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27843 # number of UpgradeReq misses
918system.cpu0.l2cache.UpgradeReq_misses::total 27843 # number of UpgradeReq misses
919system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19534 # number of SCUpgradeReq misses
920system.cpu0.l2cache.SCUpgradeReq_misses::total 19534 # number of SCUpgradeReq misses
921system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
922system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
923system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44100 # number of ReadExReq misses
924system.cpu0.l2cache.ReadExReq_misses::total 44100 # number of ReadExReq misses
925system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 64005 # number of ReadCleanReq misses
926system.cpu0.l2cache.ReadCleanReq_misses::total 64005 # number of ReadCleanReq misses
927system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101018 # number of ReadSharedReq misses
928system.cpu0.l2cache.ReadSharedReq_misses::total 101018 # number of ReadSharedReq misses
929system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 767 # number of demand (read+write) misses
930system.cpu0.l2cache.demand_misses::cpu0.itb.walker 105 # number of demand (read+write) misses
931system.cpu0.l2cache.demand_misses::cpu0.inst 64005 # number of demand (read+write) misses
932system.cpu0.l2cache.demand_misses::cpu0.data 145118 # number of demand (read+write) misses
933system.cpu0.l2cache.demand_misses::total 209995 # number of demand (read+write) misses
934system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 767 # number of overall misses
935system.cpu0.l2cache.overall_misses::cpu0.itb.walker 105 # number of overall misses
936system.cpu0.l2cache.overall_misses::cpu0.inst 64005 # number of overall misses
937system.cpu0.l2cache.overall_misses::cpu0.data 145118 # number of overall misses
938system.cpu0.l2cache.overall_misses::total 209995 # number of overall misses
939system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 26175500 # number of ReadReq miss cycles
940system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2558000 # number of ReadReq miss cycles
941system.cpu0.l2cache.ReadReq_miss_latency::total 28733500 # number of ReadReq miss cycles
942system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 514961000 # number of UpgradeReq miss cycles
943system.cpu0.l2cache.UpgradeReq_miss_latency::total 514961000 # number of UpgradeReq miss cycles
944system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 395123500 # number of SCUpgradeReq miss cycles
945system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 395123500 # number of SCUpgradeReq miss cycles
946system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 417500 # number of SCUpgradeFailReq miss cycles
947system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 417500 # number of SCUpgradeFailReq miss cycles
948system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2206381000 # number of ReadExReq miss cycles
949system.cpu0.l2cache.ReadExReq_miss_latency::total 2206381000 # number of ReadExReq miss cycles
950system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2858183000 # number of ReadCleanReq miss cycles
951system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2858183000 # number of ReadCleanReq miss cycles
952system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2907472497 # number of ReadSharedReq miss cycles
953system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2907472497 # number of ReadSharedReq miss cycles
954system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 26175500 # number of demand (read+write) miss cycles
955system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2558000 # number of demand (read+write) miss cycles
956system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2858183000 # number of demand (read+write) miss cycles
957system.cpu0.l2cache.demand_miss_latency::cpu0.data 5113853497 # number of demand (read+write) miss cycles
958system.cpu0.l2cache.demand_miss_latency::total 8000769997 # number of demand (read+write) miss cycles
959system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 26175500 # number of overall miss cycles
960system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2558000 # number of overall miss cycles
961system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2858183000 # number of overall miss cycles
962system.cpu0.l2cache.overall_miss_latency::cpu0.data 5113853497 # number of overall miss cycles
963system.cpu0.l2cache.overall_miss_latency::total 8000769997 # number of overall miss cycles
964system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 79666 # number of ReadReq accesses(hits+misses)
965system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4338 # number of ReadReq accesses(hits+misses)
966system.cpu0.l2cache.ReadReq_accesses::total 84004 # number of ReadReq accesses(hits+misses)
967system.cpu0.l2cache.Writeback_accesses::writebacks 493050 # number of Writeback accesses(hits+misses)
968system.cpu0.l2cache.Writeback_accesses::total 493050 # number of Writeback accesses(hits+misses)
969system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56043 # number of UpgradeReq accesses(hits+misses)
970system.cpu0.l2cache.UpgradeReq_accesses::total 56043 # number of UpgradeReq accesses(hits+misses)
971system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21235 # number of SCUpgradeReq accesses(hits+misses)
972system.cpu0.l2cache.SCUpgradeReq_accesses::total 21235 # number of SCUpgradeReq accesses(hits+misses)
973system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
974system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
975system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256915 # number of ReadExReq accesses(hits+misses)
976system.cpu0.l2cache.ReadExReq_accesses::total 256915 # number of ReadExReq accesses(hits+misses)
977system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1880268 # number of ReadCleanReq accesses(hits+misses)
978system.cpu0.l2cache.ReadCleanReq_accesses::total 1880268 # number of ReadCleanReq accesses(hits+misses)
979system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 478285 # number of ReadSharedReq accesses(hits+misses)
980system.cpu0.l2cache.ReadSharedReq_accesses::total 478285 # number of ReadSharedReq accesses(hits+misses)
981system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 79666 # number of demand (read+write) accesses
982system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4338 # number of demand (read+write) accesses
983system.cpu0.l2cache.demand_accesses::cpu0.inst 1880268 # number of demand (read+write) accesses
984system.cpu0.l2cache.demand_accesses::cpu0.data 735200 # number of demand (read+write) accesses
985system.cpu0.l2cache.demand_accesses::total 2699472 # number of demand (read+write) accesses
986system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 79666 # number of overall (read+write) accesses
987system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4338 # number of overall (read+write) accesses
988system.cpu0.l2cache.overall_accesses::cpu0.inst 1880268 # number of overall (read+write) accesses
989system.cpu0.l2cache.overall_accesses::cpu0.data 735200 # number of overall (read+write) accesses
990system.cpu0.l2cache.overall_accesses::total 2699472 # number of overall (read+write) accesses
991system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009628 # miss rate for ReadReq accesses
992system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.024205 # miss rate for ReadReq accesses
993system.cpu0.l2cache.ReadReq_miss_rate::total 0.010380 # miss rate for ReadReq accesses
994system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.496815 # miss rate for UpgradeReq accesses
995system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.496815 # miss rate for UpgradeReq accesses
996system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.919896 # miss rate for SCUpgradeReq accesses
997system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.919896 # miss rate for SCUpgradeReq accesses
998system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
999system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1000system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171652 # miss rate for ReadExReq accesses
1001system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171652 # miss rate for ReadExReq accesses
1002system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.034040 # miss rate for ReadCleanReq accesses
1003system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.034040 # miss rate for ReadCleanReq accesses
1004system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211209 # miss rate for ReadSharedReq accesses
1005system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211209 # miss rate for ReadSharedReq accesses
1006system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009628 # miss rate for demand accesses
1007system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.024205 # miss rate for demand accesses
1008system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.034040 # miss rate for demand accesses
1009system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197386 # miss rate for demand accesses
1010system.cpu0.l2cache.demand_miss_rate::total 0.077791 # miss rate for demand accesses
1011system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009628 # miss rate for overall accesses
1012system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.024205 # miss rate for overall accesses
1013system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.034040 # miss rate for overall accesses
1014system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197386 # miss rate for overall accesses
1015system.cpu0.l2cache.overall_miss_rate::total 0.077791 # miss rate for overall accesses
1016system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34127.118644 # average ReadReq miss latency
1017system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24361.904762 # average ReadReq miss latency
1018system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32951.261468 # average ReadReq miss latency
1019system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18495.169342 # average UpgradeReq miss latency
1020system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18495.169342 # average UpgradeReq miss latency
1021system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20227.475171 # average SCUpgradeReq miss latency
1022system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20227.475171 # average SCUpgradeReq miss latency
1023system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 417500 # average SCUpgradeFailReq miss latency
1024system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 417500 # average SCUpgradeFailReq miss latency
1025system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50031.315193 # average ReadExReq miss latency
1026system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50031.315193 # average ReadExReq miss latency
1027system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44655.620655 # average ReadCleanReq miss latency
1028system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44655.620655 # average ReadCleanReq miss latency
1029system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28781.726989 # average ReadSharedReq miss latency
1030system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28781.726989 # average ReadSharedReq miss latency
1031system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34127.118644 # average overall miss latency
1032system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24361.904762 # average overall miss latency
1033system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44655.620655 # average overall miss latency
1034system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35239.277671 # average overall miss latency
1035system.cpu0.l2cache.demand_avg_miss_latency::total 38099.811886 # average overall miss latency
1036system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34127.118644 # average overall miss latency
1037system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24361.904762 # average overall miss latency
1038system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44655.620655 # average overall miss latency
1039system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35239.277671 # average overall miss latency
1040system.cpu0.l2cache.overall_avg_miss_latency::total 38099.811886 # average overall miss latency
1041system.cpu0.l2cache.blocked_cycles::no_mshrs 60 # number of cycles access was blocked
1042system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1043system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
1044system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1045system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30 # average number of cycles each access was blocked
1046system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1047system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1048system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1049system.cpu0.l2cache.writebacks::writebacks 195910 # number of writebacks
1050system.cpu0.l2cache.writebacks::total 195910 # number of writebacks
1051system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2609 # number of ReadExReq MSHR hits
1052system.cpu0.l2cache.ReadExReq_mshr_hits::total 2609 # number of ReadExReq MSHR hits
1053system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 70 # number of ReadCleanReq MSHR hits
1054system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 70 # number of ReadCleanReq MSHR hits
1055system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 363 # number of ReadSharedReq MSHR hits
1056system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 363 # number of ReadSharedReq MSHR hits
1057system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 70 # number of demand (read+write) MSHR hits
1058system.cpu0.l2cache.demand_mshr_hits::cpu0.data 2972 # number of demand (read+write) MSHR hits
1059system.cpu0.l2cache.demand_mshr_hits::total 3042 # number of demand (read+write) MSHR hits
1060system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 70 # number of overall MSHR hits
1061system.cpu0.l2cache.overall_mshr_hits::cpu0.data 2972 # number of overall MSHR hits
1062system.cpu0.l2cache.overall_mshr_hits::total 3042 # number of overall MSHR hits
1063system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 767 # number of ReadReq MSHR misses
1064system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 105 # number of ReadReq MSHR misses
1065system.cpu0.l2cache.ReadReq_mshr_misses::total 872 # number of ReadReq MSHR misses
1066system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 9288 # number of CleanEvict MSHR misses
1067system.cpu0.l2cache.CleanEvict_mshr_misses::total 9288 # number of CleanEvict MSHR misses
1068system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 233934 # number of HardPFReq MSHR misses
1069system.cpu0.l2cache.HardPFReq_mshr_misses::total 233934 # number of HardPFReq MSHR misses
1070system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27843 # number of UpgradeReq MSHR misses
1071system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27843 # number of UpgradeReq MSHR misses
1072system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19534 # number of SCUpgradeReq MSHR misses
1073system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19534 # number of SCUpgradeReq MSHR misses
1074system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
1075system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
1076system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41491 # number of ReadExReq MSHR misses
1077system.cpu0.l2cache.ReadExReq_mshr_misses::total 41491 # number of ReadExReq MSHR misses
1078system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 63935 # number of ReadCleanReq MSHR misses
1079system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 63935 # number of ReadCleanReq MSHR misses
1080system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100655 # number of ReadSharedReq MSHR misses
1081system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100655 # number of ReadSharedReq MSHR misses
1082system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 767 # number of demand (read+write) MSHR misses
1083system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 105 # number of demand (read+write) MSHR misses
1084system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 63935 # number of demand (read+write) MSHR misses
1085system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142146 # number of demand (read+write) MSHR misses
1086system.cpu0.l2cache.demand_mshr_misses::total 206953 # number of demand (read+write) MSHR misses
1087system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 767 # number of overall MSHR misses
1088system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 105 # number of overall MSHR misses
1089system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 63935 # number of overall MSHR misses
1090system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142146 # number of overall MSHR misses
1091system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 233934 # number of overall MSHR misses
1092system.cpu0.l2cache.overall_mshr_misses::total 440887 # number of overall MSHR misses
1093system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable
1094system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable
1095system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 21427 # number of ReadReq MSHR uncacheable
1096system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16756 # number of WriteReq MSHR uncacheable
1097system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16756 # number of WriteReq MSHR uncacheable
1098system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses
1099system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34757 # number of overall MSHR uncacheable misses
1100system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 38183 # number of overall MSHR uncacheable misses
1101system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 21573500 # number of ReadReq MSHR miss cycles
1102system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1928000 # number of ReadReq MSHR miss cycles
1103system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 23501500 # number of ReadReq MSHR miss cycles
1104system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13851204796 # number of HardPFReq MSHR miss cycles
1105system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13851204796 # number of HardPFReq MSHR miss cycles
1106system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 554776500 # number of UpgradeReq MSHR miss cycles
1107system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 554776500 # number of UpgradeReq MSHR miss cycles
1108system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 298118500 # number of SCUpgradeReq MSHR miss cycles
1109system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 298118500 # number of SCUpgradeReq MSHR miss cycles
1110system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 351500 # number of SCUpgradeFailReq MSHR miss cycles
1111system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 351500 # number of SCUpgradeFailReq MSHR miss cycles
1112system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1669946000 # number of ReadExReq MSHR miss cycles
1113system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1669946000 # number of ReadExReq MSHR miss cycles
1114system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2472260000 # number of ReadCleanReq MSHR miss cycles
1115system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2472260000 # number of ReadCleanReq MSHR miss cycles
1116system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2283319997 # number of ReadSharedReq MSHR miss cycles
1117system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2283319997 # number of ReadSharedReq MSHR miss cycles
1118system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 21573500 # number of demand (read+write) MSHR miss cycles
1119system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1928000 # number of demand (read+write) MSHR miss cycles
1120system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2472260000 # number of demand (read+write) MSHR miss cycles
1121system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3953265997 # number of demand (read+write) MSHR miss cycles
1122system.cpu0.l2cache.demand_mshr_miss_latency::total 6449027497 # number of demand (read+write) MSHR miss cycles
1123system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 21573500 # number of overall MSHR miss cycles
1124system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1928000 # number of overall MSHR miss cycles
1125system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2472260000 # number of overall MSHR miss cycles
1126system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3953265997 # number of overall MSHR miss cycles
1127system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13851204796 # number of overall MSHR miss cycles
1128system.cpu0.l2cache.overall_mshr_miss_latency::total 20300232293 # number of overall MSHR miss cycles
1129system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 286870500 # number of ReadReq MSHR uncacheable cycles
1130system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3607256500 # number of ReadReq MSHR uncacheable cycles
1131system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3894127000 # number of ReadReq MSHR uncacheable cycles
1132system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2599622000 # number of WriteReq MSHR uncacheable cycles
1133system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2599622000 # number of WriteReq MSHR uncacheable cycles
1134system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 286870500 # number of overall MSHR uncacheable cycles
1135system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6206878500 # number of overall MSHR uncacheable cycles
1136system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6493749000 # number of overall MSHR uncacheable cycles
1137system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for ReadReq accesses
1138system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for ReadReq accesses
1139system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010380 # mshr miss rate for ReadReq accesses
1140system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1141system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1142system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1143system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1144system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.496815 # mshr miss rate for UpgradeReq accesses
1145system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.496815 # mshr miss rate for UpgradeReq accesses
1146system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.919896 # mshr miss rate for SCUpgradeReq accesses
1147system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.919896 # mshr miss rate for SCUpgradeReq accesses
1148system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1149system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1150system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.161497 # mshr miss rate for ReadExReq accesses
1151system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.161497 # mshr miss rate for ReadExReq accesses
1152system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for ReadCleanReq accesses
1153system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034003 # mshr miss rate for ReadCleanReq accesses
1154system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.210450 # mshr miss rate for ReadSharedReq accesses
1155system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.210450 # mshr miss rate for ReadSharedReq accesses
1156system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for demand accesses
1157system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for demand accesses
1158system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for demand accesses
1159system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193343 # mshr miss rate for demand accesses
1160system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076664 # mshr miss rate for demand accesses
1161system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for overall accesses
1162system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for overall accesses
1163system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for overall accesses
1164system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193343 # mshr miss rate for overall accesses
1165system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1166system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163323 # mshr miss rate for overall accesses
1167system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average ReadReq mshr miss latency
1168system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average ReadReq mshr miss latency
1169system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26951.261468 # average ReadReq mshr miss latency
1170system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112 # average HardPFReq mshr miss latency
1171system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59209.883112 # average HardPFReq mshr miss latency
1172system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19925.169702 # average UpgradeReq mshr miss latency
1173system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19925.169702 # average UpgradeReq mshr miss latency
1174system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15261.518378 # average SCUpgradeReq mshr miss latency
1175system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15261.518378 # average SCUpgradeReq mshr miss latency
1176system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 351500 # average SCUpgradeFailReq mshr miss latency
1177system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 351500 # average SCUpgradeFailReq mshr miss latency
1178system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40248.391217 # average ReadExReq mshr miss latency
1179system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40248.391217 # average ReadExReq mshr miss latency
1180system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average ReadCleanReq mshr miss latency
1181system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38668.335028 # average ReadCleanReq mshr miss latency
1182system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22684.615737 # average ReadSharedReq mshr miss latency
1183system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22684.615737 # average ReadSharedReq mshr miss latency
1184system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average overall mshr miss latency
1185system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average overall mshr miss latency
1186system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average overall mshr miss latency
1187system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27811.306664 # average overall mshr miss latency
1188system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31161.797592 # average overall mshr miss latency
1189system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average overall mshr miss latency
1190system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average overall mshr miss latency
1191system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average overall mshr miss latency
1192system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27811.306664 # average overall mshr miss latency
1193system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112 # average overall mshr miss latency
1194system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46044.070914 # average overall mshr miss latency
1195system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average ReadReq mshr uncacheable latency
1196system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200392.006000 # average ReadReq mshr uncacheable latency
1197system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.254212 # average ReadReq mshr uncacheable latency
1198system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155145.738840 # average WriteReq mshr uncacheable latency
1199system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155145.738840 # average WriteReq mshr uncacheable latency
1200system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average overall mshr uncacheable latency
1201system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178579.235837 # average overall mshr uncacheable latency
1202system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170069.114527 # average overall mshr uncacheable latency
1203system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1204system.cpu0.toL2Bus.trans_dist::ReadReq 136175 # Transaction distribution
1205system.cpu0.toL2Bus.trans_dist::ReadResp 2526619 # Transaction distribution
1206system.cpu0.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution
1207system.cpu0.toL2Bus.trans_dist::WriteResp 16756 # Transaction distribution
1208system.cpu0.toL2Bus.trans_dist::Writeback 865136 # Transaction distribution
1209system.cpu0.toL2Bus.trans_dist::CleanEvict 2178805 # Transaction distribution
1210system.cpu0.toL2Bus.trans_dist::HardPFReq 280675 # Transaction distribution
1211system.cpu0.toL2Bus.trans_dist::UpgradeReq 92865 # Transaction distribution
1212system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43660 # Transaction distribution
1213system.cpu0.toL2Bus.trans_dist::UpgradeResp 114593 # Transaction distribution
1214system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution
1215system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution
1216system.cpu0.toL2Bus.trans_dist::ReadExReq 285252 # Transaction distribution
1217system.cpu0.toL2Bus.trans_dist::ReadExResp 271172 # Transaction distribution
1218system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1880268 # Transaction distribution
1219system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604912 # Transaction distribution
1220system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
1221system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5613549 # Packet count per connected master and slave (bytes)
1222system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2467613 # Packet count per connected master and slave (bytes)
1223system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11765 # Packet count per connected master and slave (bytes)
1224system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 169746 # Packet count per connected master and slave (bytes)
1225system.cpu0.toL2Bus.pkt_count::total 8262673 # Packet count per connected master and slave (bytes)
1226system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120556352 # Cumulative packet size per connected master and slave (bytes)
1227system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82765674 # Cumulative packet size per connected master and slave (bytes)
1228system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17352 # Cumulative packet size per connected master and slave (bytes)
1229system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 318664 # Cumulative packet size per connected master and slave (bytes)
1230system.cpu0.toL2Bus.pkt_size::total 203658042 # Cumulative packet size per connected master and slave (bytes)
1231system.cpu0.toL2Bus.snoops 1202366 # Total snoops (count)
1232system.cpu0.toL2Bus.snoop_fanout::samples 6476462 # Request fanout histogram
1233system.cpu0.toL2Bus.snoop_fanout::mean 1.183069 # Request fanout histogram
1234system.cpu0.toL2Bus.snoop_fanout::stdev 0.386723 # Request fanout histogram
1235system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1236system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1237system.cpu0.toL2Bus.snoop_fanout::1 5290820 81.69% 81.69% # Request fanout histogram
1238system.cpu0.toL2Bus.snoop_fanout::2 1185642 18.31% 100.00% # Request fanout histogram
1239system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1240system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1241system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1242system.cpu0.toL2Bus.snoop_fanout::total 6476462 # Request fanout histogram
1243system.cpu0.toL2Bus.reqLayer0.occupancy 3195593995 # Layer occupancy (ticks)
1244system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1245system.cpu0.toL2Bus.snoopLayer0.occupancy 113765999 # Layer occupancy (ticks)
1246system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1247system.cpu0.toL2Bus.respLayer0.occupancy 2825774529 # Layer occupancy (ticks)
1248system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1249system.cpu0.toL2Bus.respLayer1.occupancy 1168364927 # Layer occupancy (ticks)
1250system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1251system.cpu0.toL2Bus.respLayer2.occupancy 7430992 # Layer occupancy (ticks)
1252system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1253system.cpu0.toL2Bus.respLayer3.occupancy 90084491 # Layer occupancy (ticks)
1254system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1255system.cpu1.branchPred.lookups 20439224 # Number of BP lookups
1256system.cpu1.branchPred.condPredicted 7037667 # Number of conditional branches predicted
1257system.cpu1.branchPred.condIncorrect 906738 # Number of conditional branches incorrect
1258system.cpu1.branchPred.BTBLookups 10483361 # Number of BTB lookups
1259system.cpu1.branchPred.BTBHits 7695105 # Number of BTB hits
1260system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1261system.cpu1.branchPred.BTBHitPct 73.403034 # BTB Hit Percentage
1262system.cpu1.branchPred.usedRAS 8822837 # Number of times the RAS was used to get a target.
1263system.cpu1.branchPred.RASInCorrect 629691 # Number of incorrect RAS predictions.
1264system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1265system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1266system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1267system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1268system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1269system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1270system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1271system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1285system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1286system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1287system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1288system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1289system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1290system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1291system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1292system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1293system.cpu1.dtb.walker.walks 30282 # Table walker walks requested
1294system.cpu1.dtb.walker.walksShort 30282 # Table walker walks initiated with short descriptors
1295system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22625 # Level at which table walker walks with short descriptors terminate
1296system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7657 # Level at which table walker walks with short descriptors terminate
1297system.cpu1.dtb.walker.walkWaitTime::samples 30282 # Table walker wait (enqueue to first request) latency
1298system.cpu1.dtb.walker.walkWaitTime::0 30282 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1299system.cpu1.dtb.walker.walkWaitTime::total 30282 # Table walker wait (enqueue to first request) latency
1300system.cpu1.dtb.walker.walkCompletionTime::samples 2657 # Table walker service (enqueue to completion) latency
1301system.cpu1.dtb.walker.walkCompletionTime::mean 10518.253670 # Table walker service (enqueue to completion) latency
1302system.cpu1.dtb.walker.walkCompletionTime::gmean 9441.717442 # Table walker service (enqueue to completion) latency
1303system.cpu1.dtb.walker.walkCompletionTime::stdev 7245.373074 # Table walker service (enqueue to completion) latency
1304system.cpu1.dtb.walker.walkCompletionTime::0-16383 2512 94.54% 94.54% # Table walker service (enqueue to completion) latency
1305system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 4.89% 99.44% # Table walker service (enqueue to completion) latency
1306system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.26% 99.70% # Table walker service (enqueue to completion) latency
1307system.cpu1.dtb.walker.walkCompletionTime::81920-98303 5 0.19% 99.89% # Table walker service (enqueue to completion) latency
1308system.cpu1.dtb.walker.walkCompletionTime::98304-114687 2 0.08% 99.96% # Table walker service (enqueue to completion) latency
1309system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
1310system.cpu1.dtb.walker.walkCompletionTime::total 2657 # Table walker service (enqueue to completion) latency
1311system.cpu1.dtb.walker.walksPending::samples 1594102264 # Table walker pending requests distribution
1312system.cpu1.dtb.walker.walksPending::0 1594102264 100.00% 100.00% # Table walker pending requests distribution
1313system.cpu1.dtb.walker.walksPending::total 1594102264 # Table walker pending requests distribution
1314system.cpu1.dtb.walker.walkPageSizes::4K 1972 74.22% 74.22% # Table walker page sizes translated
1315system.cpu1.dtb.walker.walkPageSizes::1M 685 25.78% 100.00% # Table walker page sizes translated
1316system.cpu1.dtb.walker.walkPageSizes::total 2657 # Table walker page sizes translated
1317system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30282 # Table walker requests started/completed, data/inst
1318system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1319system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30282 # Table walker requests started/completed, data/inst
1320system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2657 # Table walker requests started/completed, data/inst
1321system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1322system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2657 # Table walker requests started/completed, data/inst
1323system.cpu1.dtb.walker.walkRequestOrigin::total 32939 # Table walker requests started/completed, data/inst
1324system.cpu1.dtb.inst_hits 0 # ITB inst hits
1325system.cpu1.dtb.inst_misses 0 # ITB inst misses
1326system.cpu1.dtb.read_hits 12124185 # DTB read hits
1327system.cpu1.dtb.read_misses 27903 # DTB read misses
1328system.cpu1.dtb.write_hits 7716793 # DTB write hits
1329system.cpu1.dtb.write_misses 2379 # DTB write misses
1330system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1331system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1332system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1333system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1334system.cpu1.dtb.flush_entries 2053 # Number of entries that have been flushed from TLB
1335system.cpu1.dtb.align_faults 374 # Number of TLB faults due to alignment restrictions
1336system.cpu1.dtb.prefetch_faults 549 # Number of TLB faults due to prefetch
1337system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1338system.cpu1.dtb.perms_faults 291 # Number of TLB faults due to permissions restrictions
1339system.cpu1.dtb.read_accesses 12152088 # DTB read accesses
1340system.cpu1.dtb.write_accesses 7719172 # DTB write accesses
1341system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1342system.cpu1.dtb.hits 19840978 # DTB hits
1343system.cpu1.dtb.misses 30282 # DTB misses
1344system.cpu1.dtb.accesses 19871260 # DTB accesses
1345system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1346system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1347system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1348system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1349system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1350system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1351system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1352system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1366system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1367system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1368system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1369system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1370system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1371system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1372system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1373system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1374system.cpu1.itb.walker.walks 2290 # Table walker walks requested
1375system.cpu1.itb.walker.walksShort 2290 # Table walker walks initiated with short descriptors
1376system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate
1377system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2108 # Level at which table walker walks with short descriptors terminate
1378system.cpu1.itb.walker.walkWaitTime::samples 2290 # Table walker wait (enqueue to first request) latency
1379system.cpu1.itb.walker.walkWaitTime::0 2290 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1380system.cpu1.itb.walker.walkWaitTime::total 2290 # Table walker wait (enqueue to first request) latency
1381system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency
1382system.cpu1.itb.walker.walkCompletionTime::mean 10627.337489 # Table walker service (enqueue to completion) latency
1383system.cpu1.itb.walker.walkCompletionTime::gmean 9754.511529 # Table walker service (enqueue to completion) latency
1384system.cpu1.itb.walker.walkCompletionTime::stdev 5025.096618 # Table walker service (enqueue to completion) latency
1385system.cpu1.itb.walker.walkCompletionTime::4096-8191 329 29.30% 29.30% # Table walker service (enqueue to completion) latency
1386system.cpu1.itb.walker.walkCompletionTime::8192-12287 526 46.84% 76.14% # Table walker service (enqueue to completion) latency
1387system.cpu1.itb.walker.walkCompletionTime::12288-16383 229 20.39% 96.53% # Table walker service (enqueue to completion) latency
1388system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.71% # Table walker service (enqueue to completion) latency
1389system.cpu1.itb.walker.walkCompletionTime::24576-28671 14 1.25% 97.95% # Table walker service (enqueue to completion) latency
1390system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.87% 99.82% # Table walker service (enqueue to completion) latency
1391system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
1392system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
1393system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency
1394system.cpu1.itb.walker.walksPending::samples 1593536764 # Table walker pending requests distribution
1395system.cpu1.itb.walker.walksPending::0 1593536764 100.00% 100.00% # Table walker pending requests distribution
1396system.cpu1.itb.walker.walksPending::total 1593536764 # Table walker pending requests distribution
1397system.cpu1.itb.walker.walkPageSizes::4K 954 84.95% 84.95% # Table walker page sizes translated
1398system.cpu1.itb.walker.walkPageSizes::1M 169 15.05% 100.00% # Table walker page sizes translated
1399system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated
1400system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1401system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2290 # Table walker requests started/completed, data/inst
1402system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2290 # Table walker requests started/completed, data/inst
1403system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1404system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst
1405system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst
1406system.cpu1.itb.walker.walkRequestOrigin::total 3413 # Table walker requests started/completed, data/inst
1407system.cpu1.itb.inst_hits 41919801 # ITB inst hits
1408system.cpu1.itb.inst_misses 2290 # ITB inst misses
1409system.cpu1.itb.read_hits 0 # DTB read hits
1410system.cpu1.itb.read_misses 0 # DTB read misses
1411system.cpu1.itb.write_hits 0 # DTB write hits
1412system.cpu1.itb.write_misses 0 # DTB write misses
1413system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1414system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1415system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1416system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1417system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB
1418system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1419system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1420system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1421system.cpu1.itb.perms_faults 1868 # Number of TLB faults due to permissions restrictions
1422system.cpu1.itb.read_accesses 0 # DTB read accesses
1423system.cpu1.itb.write_accesses 0 # DTB write accesses
1424system.cpu1.itb.inst_accesses 41922091 # ITB inst accesses
1425system.cpu1.itb.hits 41919801 # DTB hits
1426system.cpu1.itb.misses 2290 # DTB misses
1427system.cpu1.itb.accesses 41922091 # DTB accesses
1428system.cpu1.numCycles 125017818 # number of cpu cycles simulated
1429system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1430system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1431system.cpu1.committedInsts 51886096 # Number of instructions committed
1432system.cpu1.committedOps 63386159 # Number of ops (including micro ops) committed
1433system.cpu1.discardedOps 5353179 # Number of ops (including micro ops) which were discarded before commit
1434system.cpu1.numFetchSuspends 2738 # Number of times Execute suspended instruction fetching
1435system.cpu1.quiesceCycles 5566469050 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1436system.cpu1.cpi 2.409467 # CPI: cycles per instruction
1437system.cpu1.ipc 0.415030 # IPC: instructions per cycle
1438system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1439system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
1440system.cpu1.tickCycles 105304281 # Number of cycles that the object actually ticked
1441system.cpu1.idleCycles 19713537 # Total number of cycles that the object has spent stopped
1442system.cpu1.dcache.tags.replacements 231375 # number of replacements
1443system.cpu1.dcache.tags.tagsinuse 483.037999 # Cycle average of tags in use
1444system.cpu1.dcache.tags.total_refs 19321104 # Total number of references to valid blocks.
1445system.cpu1.dcache.tags.sampled_refs 231701 # Sample count of references to valid blocks.
1446system.cpu1.dcache.tags.avg_refs 83.388091 # Average number of references to valid blocks.
1447system.cpu1.dcache.tags.warmup_cycle 90467560500 # Cycle when the warmup percentage was hit.
1448system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.037999 # Average occupied blocks per requestor
1449system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943434 # Average percentage of cache occupancy
1450system.cpu1.dcache.tags.occ_percent::total 0.943434 # Average percentage of cache occupancy
1451system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id
1452system.cpu1.dcache.tags.age_task_id_blocks_1024::2 253 # Occupied blocks per task id
1453system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id
1454system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id
1455system.cpu1.dcache.tags.tag_accesses 39693132 # Number of tag accesses
1456system.cpu1.dcache.tags.data_accesses 39693132 # Number of data accesses
1457system.cpu1.dcache.ReadReq_hits::cpu1.data 11664966 # number of ReadReq hits
1458system.cpu1.dcache.ReadReq_hits::total 11664966 # number of ReadReq hits
1459system.cpu1.dcache.WriteReq_hits::cpu1.data 7379255 # number of WriteReq hits
1460system.cpu1.dcache.WriteReq_hits::total 7379255 # number of WriteReq hits
1461system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66113 # number of SoftPFReq hits
1462system.cpu1.dcache.SoftPFReq_hits::total 66113 # number of SoftPFReq hits
1463system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88582 # number of LoadLockedReq hits
1464system.cpu1.dcache.LoadLockedReq_hits::total 88582 # number of LoadLockedReq hits
1465system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80498 # number of StoreCondReq hits
1466system.cpu1.dcache.StoreCondReq_hits::total 80498 # number of StoreCondReq hits
1467system.cpu1.dcache.demand_hits::cpu1.data 19044221 # number of demand (read+write) hits
1468system.cpu1.dcache.demand_hits::total 19044221 # number of demand (read+write) hits
1469system.cpu1.dcache.overall_hits::cpu1.data 19110334 # number of overall hits
1470system.cpu1.dcache.overall_hits::total 19110334 # number of overall hits
1471system.cpu1.dcache.ReadReq_misses::cpu1.data 184342 # number of ReadReq misses
1472system.cpu1.dcache.ReadReq_misses::total 184342 # number of ReadReq misses
1473system.cpu1.dcache.WriteReq_misses::cpu1.data 167268 # number of WriteReq misses
1474system.cpu1.dcache.WriteReq_misses::total 167268 # number of WriteReq misses
1475system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34982 # number of SoftPFReq misses
1476system.cpu1.dcache.SoftPFReq_misses::total 34982 # number of SoftPFReq misses
1477system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17676 # number of LoadLockedReq misses
1478system.cpu1.dcache.LoadLockedReq_misses::total 17676 # number of LoadLockedReq misses
1479system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23450 # number of StoreCondReq misses
1480system.cpu1.dcache.StoreCondReq_misses::total 23450 # number of StoreCondReq misses
1481system.cpu1.dcache.demand_misses::cpu1.data 351610 # number of demand (read+write) misses
1482system.cpu1.dcache.demand_misses::total 351610 # number of demand (read+write) misses
1483system.cpu1.dcache.overall_misses::cpu1.data 386592 # number of overall misses
1484system.cpu1.dcache.overall_misses::total 386592 # number of overall misses
1485system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2719374500 # number of ReadReq miss cycles
1486system.cpu1.dcache.ReadReq_miss_latency::total 2719374500 # number of ReadReq miss cycles
1487system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4153510500 # number of WriteReq miss cycles
1488system.cpu1.dcache.WriteReq_miss_latency::total 4153510500 # number of WriteReq miss cycles
1489system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325753000 # number of LoadLockedReq miss cycles
1490system.cpu1.dcache.LoadLockedReq_miss_latency::total 325753000 # number of LoadLockedReq miss cycles
1491system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548137000 # number of StoreCondReq miss cycles
1492system.cpu1.dcache.StoreCondReq_miss_latency::total 548137000 # number of StoreCondReq miss cycles
1493system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 684500 # number of StoreCondFailReq miss cycles
1494system.cpu1.dcache.StoreCondFailReq_miss_latency::total 684500 # number of StoreCondFailReq miss cycles
1495system.cpu1.dcache.demand_miss_latency::cpu1.data 6872885000 # number of demand (read+write) miss cycles
1496system.cpu1.dcache.demand_miss_latency::total 6872885000 # number of demand (read+write) miss cycles
1497system.cpu1.dcache.overall_miss_latency::cpu1.data 6872885000 # number of overall miss cycles
1498system.cpu1.dcache.overall_miss_latency::total 6872885000 # number of overall miss cycles
1499system.cpu1.dcache.ReadReq_accesses::cpu1.data 11849308 # number of ReadReq accesses(hits+misses)
1500system.cpu1.dcache.ReadReq_accesses::total 11849308 # number of ReadReq accesses(hits+misses)
1501system.cpu1.dcache.WriteReq_accesses::cpu1.data 7546523 # number of WriteReq accesses(hits+misses)
1502system.cpu1.dcache.WriteReq_accesses::total 7546523 # number of WriteReq accesses(hits+misses)
1503system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101095 # number of SoftPFReq accesses(hits+misses)
1504system.cpu1.dcache.SoftPFReq_accesses::total 101095 # number of SoftPFReq accesses(hits+misses)
1505system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106258 # number of LoadLockedReq accesses(hits+misses)
1506system.cpu1.dcache.LoadLockedReq_accesses::total 106258 # number of LoadLockedReq accesses(hits+misses)
1507system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103948 # number of StoreCondReq accesses(hits+misses)
1508system.cpu1.dcache.StoreCondReq_accesses::total 103948 # number of StoreCondReq accesses(hits+misses)
1509system.cpu1.dcache.demand_accesses::cpu1.data 19395831 # number of demand (read+write) accesses
1510system.cpu1.dcache.demand_accesses::total 19395831 # number of demand (read+write) accesses
1511system.cpu1.dcache.overall_accesses::cpu1.data 19496926 # number of overall (read+write) accesses
1512system.cpu1.dcache.overall_accesses::total 19496926 # number of overall (read+write) accesses
1513system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015557 # miss rate for ReadReq accesses
1514system.cpu1.dcache.ReadReq_miss_rate::total 0.015557 # miss rate for ReadReq accesses
1515system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022165 # miss rate for WriteReq accesses
1516system.cpu1.dcache.WriteReq_miss_rate::total 0.022165 # miss rate for WriteReq accesses
1517system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.346031 # miss rate for SoftPFReq accesses
1518system.cpu1.dcache.SoftPFReq_miss_rate::total 0.346031 # miss rate for SoftPFReq accesses
1519system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166350 # miss rate for LoadLockedReq accesses
1520system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166350 # miss rate for LoadLockedReq accesses
1521system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225594 # miss rate for StoreCondReq accesses
1522system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225594 # miss rate for StoreCondReq accesses
1523system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018128 # miss rate for demand accesses
1524system.cpu1.dcache.demand_miss_rate::total 0.018128 # miss rate for demand accesses
1525system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019828 # miss rate for overall accesses
1526system.cpu1.dcache.overall_miss_rate::total 0.019828 # miss rate for overall accesses
1527system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14751.790151 # average ReadReq miss latency
1528system.cpu1.dcache.ReadReq_avg_miss_latency::total 14751.790151 # average ReadReq miss latency
1529system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24831.471052 # average WriteReq miss latency
1530system.cpu1.dcache.WriteReq_avg_miss_latency::total 24831.471052 # average WriteReq miss latency
1531system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18429.112921 # average LoadLockedReq miss latency
1532system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18429.112921 # average LoadLockedReq miss latency
1533system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23374.712154 # average StoreCondReq miss latency
1534system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23374.712154 # average StoreCondReq miss latency
1535system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1536system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1537system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19546.898552 # average overall miss latency
1538system.cpu1.dcache.demand_avg_miss_latency::total 19546.898552 # average overall miss latency
1539system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17778.135605 # average overall miss latency
1540system.cpu1.dcache.overall_avg_miss_latency::total 17778.135605 # average overall miss latency
1541system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1542system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1543system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1544system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1545system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1546system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1547system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1548system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1549system.cpu1.dcache.writebacks::writebacks 138377 # number of writebacks
1550system.cpu1.dcache.writebacks::total 138377 # number of writebacks
1551system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18221 # number of ReadReq MSHR hits
1552system.cpu1.dcache.ReadReq_mshr_hits::total 18221 # number of ReadReq MSHR hits
1553system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62038 # number of WriteReq MSHR hits
1554system.cpu1.dcache.WriteReq_mshr_hits::total 62038 # number of WriteReq MSHR hits
1555system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12225 # number of LoadLockedReq MSHR hits
1556system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12225 # number of LoadLockedReq MSHR hits
1557system.cpu1.dcache.demand_mshr_hits::cpu1.data 80259 # number of demand (read+write) MSHR hits
1558system.cpu1.dcache.demand_mshr_hits::total 80259 # number of demand (read+write) MSHR hits
1559system.cpu1.dcache.overall_mshr_hits::cpu1.data 80259 # number of overall MSHR hits
1560system.cpu1.dcache.overall_mshr_hits::total 80259 # number of overall MSHR hits
1561system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166121 # number of ReadReq MSHR misses
1562system.cpu1.dcache.ReadReq_mshr_misses::total 166121 # number of ReadReq MSHR misses
1563system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105230 # number of WriteReq MSHR misses
1564system.cpu1.dcache.WriteReq_mshr_misses::total 105230 # number of WriteReq MSHR misses
1565system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33463 # number of SoftPFReq MSHR misses
1566system.cpu1.dcache.SoftPFReq_mshr_misses::total 33463 # number of SoftPFReq MSHR misses
1567system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5451 # number of LoadLockedReq MSHR misses
1568system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5451 # number of LoadLockedReq MSHR misses
1569system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23450 # number of StoreCondReq MSHR misses
1570system.cpu1.dcache.StoreCondReq_mshr_misses::total 23450 # number of StoreCondReq MSHR misses
1571system.cpu1.dcache.demand_mshr_misses::cpu1.data 271351 # number of demand (read+write) MSHR misses
1572system.cpu1.dcache.demand_mshr_misses::total 271351 # number of demand (read+write) MSHR misses
1573system.cpu1.dcache.overall_mshr_misses::cpu1.data 304814 # number of overall MSHR misses
1574system.cpu1.dcache.overall_mshr_misses::total 304814 # number of overall MSHR misses
1575system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17128 # number of ReadReq MSHR uncacheable
1576system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17128 # number of ReadReq MSHR uncacheable
1577system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14405 # number of WriteReq MSHR uncacheable
1578system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14405 # number of WriteReq MSHR uncacheable
1579system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31533 # number of overall MSHR uncacheable misses
1580system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31533 # number of overall MSHR uncacheable misses
1581system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2295109000 # number of ReadReq MSHR miss cycles
1582system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2295109000 # number of ReadReq MSHR miss cycles
1583system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2517034000 # number of WriteReq MSHR miss cycles
1584system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2517034000 # number of WriteReq MSHR miss cycles
1585system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 544638000 # number of SoftPFReq MSHR miss cycles
1586system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 544638000 # number of SoftPFReq MSHR miss cycles
1587system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 92810500 # number of LoadLockedReq MSHR miss cycles
1588system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 92810500 # number of LoadLockedReq MSHR miss cycles
1589system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524700000 # number of StoreCondReq MSHR miss cycles
1590system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524700000 # number of StoreCondReq MSHR miss cycles
1591system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 671500 # number of StoreCondFailReq MSHR miss cycles
1592system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 671500 # number of StoreCondFailReq MSHR miss cycles
1593system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4812143000 # number of demand (read+write) MSHR miss cycles
1594system.cpu1.dcache.demand_mshr_miss_latency::total 4812143000 # number of demand (read+write) MSHR miss cycles
1595system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5356781000 # number of overall MSHR miss cycles
1596system.cpu1.dcache.overall_mshr_miss_latency::total 5356781000 # number of overall MSHR miss cycles
1597system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2934873000 # number of ReadReq MSHR uncacheable cycles
1598system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2934873000 # number of ReadReq MSHR uncacheable cycles
1599system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2446602500 # number of WriteReq MSHR uncacheable cycles
1600system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2446602500 # number of WriteReq MSHR uncacheable cycles
1601system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5381475500 # number of overall MSHR uncacheable cycles
1602system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5381475500 # number of overall MSHR uncacheable cycles
1603system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014019 # mshr miss rate for ReadReq accesses
1604system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014019 # mshr miss rate for ReadReq accesses
1605system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013944 # mshr miss rate for WriteReq accesses
1606system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013944 # mshr miss rate for WriteReq accesses
1607system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331005 # mshr miss rate for SoftPFReq accesses
1608system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331005 # mshr miss rate for SoftPFReq accesses
1609system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051300 # mshr miss rate for LoadLockedReq accesses
1610system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051300 # mshr miss rate for LoadLockedReq accesses
1611system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225594 # mshr miss rate for StoreCondReq accesses
1612system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225594 # mshr miss rate for StoreCondReq accesses
1613system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013990 # mshr miss rate for demand accesses
1614system.cpu1.dcache.demand_mshr_miss_rate::total 0.013990 # mshr miss rate for demand accesses
1615system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015634 # mshr miss rate for overall accesses
1616system.cpu1.dcache.overall_mshr_miss_rate::total 0.015634 # mshr miss rate for overall accesses
1617system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13815.887215 # average ReadReq mshr miss latency
1618system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13815.887215 # average ReadReq mshr miss latency
1619system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23919.357598 # average WriteReq mshr miss latency
1620system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23919.357598 # average WriteReq mshr miss latency
1621system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16275.827033 # average SoftPFReq mshr miss latency
1622system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16275.827033 # average SoftPFReq mshr miss latency
1623system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17026.325445 # average LoadLockedReq mshr miss latency
1624system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17026.325445 # average LoadLockedReq mshr miss latency
1625system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22375.266525 # average StoreCondReq mshr miss latency
1626system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22375.266525 # average StoreCondReq mshr miss latency
1627system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1628system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1629system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17734.016090 # average overall mshr miss latency
1630system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17734.016090 # average overall mshr miss latency
1631system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17573.933612 # average overall mshr miss latency
1632system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17573.933612 # average overall mshr miss latency
1633system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171349.427837 # average ReadReq mshr uncacheable latency
1634system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171349.427837 # average ReadReq mshr uncacheable latency
1635system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169843.977785 # average WriteReq mshr uncacheable latency
1636system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169843.977785 # average WriteReq mshr uncacheable latency
1637system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170661.703612 # average overall mshr uncacheable latency
1638system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170661.703612 # average overall mshr uncacheable latency
1639system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1640system.cpu1.icache.tags.replacements 1042125 # number of replacements
1641system.cpu1.icache.tags.tagsinuse 499.329120 # Cycle average of tags in use
1642system.cpu1.icache.tags.total_refs 40875126 # Total number of references to valid blocks.
1643system.cpu1.icache.tags.sampled_refs 1042637 # Sample count of references to valid blocks.
1644system.cpu1.icache.tags.avg_refs 39.203602 # Average number of references to valid blocks.
1645system.cpu1.icache.tags.warmup_cycle 72106351500 # Cycle when the warmup percentage was hit.
1646system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.329120 # Average occupied blocks per requestor
1647system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975252 # Average percentage of cache occupancy
1648system.cpu1.icache.tags.occ_percent::total 0.975252 # Average percentage of cache occupancy
1649system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1650system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id
1651system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id
1652system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1653system.cpu1.icache.tags.tag_accesses 84878163 # Number of tag accesses
1654system.cpu1.icache.tags.data_accesses 84878163 # Number of data accesses
1655system.cpu1.icache.ReadReq_hits::cpu1.inst 40875126 # number of ReadReq hits
1656system.cpu1.icache.ReadReq_hits::total 40875126 # number of ReadReq hits
1657system.cpu1.icache.demand_hits::cpu1.inst 40875126 # number of demand (read+write) hits
1658system.cpu1.icache.demand_hits::total 40875126 # number of demand (read+write) hits
1659system.cpu1.icache.overall_hits::cpu1.inst 40875126 # number of overall hits
1660system.cpu1.icache.overall_hits::total 40875126 # number of overall hits
1661system.cpu1.icache.ReadReq_misses::cpu1.inst 1042637 # number of ReadReq misses
1662system.cpu1.icache.ReadReq_misses::total 1042637 # number of ReadReq misses
1663system.cpu1.icache.demand_misses::cpu1.inst 1042637 # number of demand (read+write) misses
1664system.cpu1.icache.demand_misses::total 1042637 # number of demand (read+write) misses
1665system.cpu1.icache.overall_misses::cpu1.inst 1042637 # number of overall misses
1666system.cpu1.icache.overall_misses::total 1042637 # number of overall misses
1667system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9237616500 # number of ReadReq miss cycles
1668system.cpu1.icache.ReadReq_miss_latency::total 9237616500 # number of ReadReq miss cycles
1669system.cpu1.icache.demand_miss_latency::cpu1.inst 9237616500 # number of demand (read+write) miss cycles
1670system.cpu1.icache.demand_miss_latency::total 9237616500 # number of demand (read+write) miss cycles
1671system.cpu1.icache.overall_miss_latency::cpu1.inst 9237616500 # number of overall miss cycles
1672system.cpu1.icache.overall_miss_latency::total 9237616500 # number of overall miss cycles
1673system.cpu1.icache.ReadReq_accesses::cpu1.inst 41917763 # number of ReadReq accesses(hits+misses)
1674system.cpu1.icache.ReadReq_accesses::total 41917763 # number of ReadReq accesses(hits+misses)
1675system.cpu1.icache.demand_accesses::cpu1.inst 41917763 # number of demand (read+write) accesses
1676system.cpu1.icache.demand_accesses::total 41917763 # number of demand (read+write) accesses
1677system.cpu1.icache.overall_accesses::cpu1.inst 41917763 # number of overall (read+write) accesses
1678system.cpu1.icache.overall_accesses::total 41917763 # number of overall (read+write) accesses
1679system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024873 # miss rate for ReadReq accesses
1680system.cpu1.icache.ReadReq_miss_rate::total 0.024873 # miss rate for ReadReq accesses
1681system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024873 # miss rate for demand accesses
1682system.cpu1.icache.demand_miss_rate::total 0.024873 # miss rate for demand accesses
1683system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024873 # miss rate for overall accesses
1684system.cpu1.icache.overall_miss_rate::total 0.024873 # miss rate for overall accesses
1685system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8859.858704 # average ReadReq miss latency
1686system.cpu1.icache.ReadReq_avg_miss_latency::total 8859.858704 # average ReadReq miss latency
1687system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8859.858704 # average overall miss latency
1688system.cpu1.icache.demand_avg_miss_latency::total 8859.858704 # average overall miss latency
1689system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8859.858704 # average overall miss latency
1690system.cpu1.icache.overall_avg_miss_latency::total 8859.858704 # average overall miss latency
1691system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1692system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1693system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1694system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1695system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1696system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1697system.cpu1.icache.fast_writes 0 # number of fast writes performed
1698system.cpu1.icache.cache_copies 0 # number of cache copies performed
1699system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1042637 # number of ReadReq MSHR misses
1700system.cpu1.icache.ReadReq_mshr_misses::total 1042637 # number of ReadReq MSHR misses
1701system.cpu1.icache.demand_mshr_misses::cpu1.inst 1042637 # number of demand (read+write) MSHR misses
1702system.cpu1.icache.demand_mshr_misses::total 1042637 # number of demand (read+write) MSHR misses
1703system.cpu1.icache.overall_mshr_misses::cpu1.inst 1042637 # number of overall MSHR misses
1704system.cpu1.icache.overall_mshr_misses::total 1042637 # number of overall MSHR misses
1705system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable
1706system.cpu1.icache.ReadReq_mshr_uncacheable::total 113 # number of ReadReq MSHR uncacheable
1707system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses
1708system.cpu1.icache.overall_mshr_uncacheable_misses::total 113 # number of overall MSHR uncacheable misses
1709system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8716298000 # number of ReadReq MSHR miss cycles
1710system.cpu1.icache.ReadReq_mshr_miss_latency::total 8716298000 # number of ReadReq MSHR miss cycles
1711system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8716298000 # number of demand (read+write) MSHR miss cycles
1712system.cpu1.icache.demand_mshr_miss_latency::total 8716298000 # number of demand (read+write) MSHR miss cycles
1713system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8716298000 # number of overall MSHR miss cycles
1714system.cpu1.icache.overall_mshr_miss_latency::total 8716298000 # number of overall MSHR miss cycles
1715system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10126000 # number of ReadReq MSHR uncacheable cycles
1716system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10126000 # number of ReadReq MSHR uncacheable cycles
1717system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10126000 # number of overall MSHR uncacheable cycles
1718system.cpu1.icache.overall_mshr_uncacheable_latency::total 10126000 # number of overall MSHR uncacheable cycles
1719system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for ReadReq accesses
1720system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024873 # mshr miss rate for ReadReq accesses
1721system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for demand accesses
1722system.cpu1.icache.demand_mshr_miss_rate::total 0.024873 # mshr miss rate for demand accesses
1723system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for overall accesses
1724system.cpu1.icache.overall_mshr_miss_rate::total 0.024873 # mshr miss rate for overall accesses
1725system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average ReadReq mshr miss latency
1726system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8359.858704 # average ReadReq mshr miss latency
1727system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average overall mshr miss latency
1728system.cpu1.icache.demand_avg_mshr_miss_latency::total 8359.858704 # average overall mshr miss latency
1729system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average overall mshr miss latency
1730system.cpu1.icache.overall_avg_mshr_miss_latency::total 8359.858704 # average overall mshr miss latency
1731system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469 # average ReadReq mshr uncacheable latency
1732system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89610.619469 # average ReadReq mshr uncacheable latency
1733system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469 # average overall mshr uncacheable latency
1734system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89610.619469 # average overall mshr uncacheable latency
1735system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1736system.cpu1.l2cache.prefetcher.num_hwpf_issued 270674 # number of hwpf issued
1737system.cpu1.l2cache.prefetcher.pfIdentified 270706 # number of prefetch candidates identified
1738system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue
1739system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1740system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1741system.cpu1.l2cache.prefetcher.pfSpanPage 70190 # number of prefetches not generated due to page crossing
1742system.cpu1.l2cache.tags.replacements 69559 # number of replacements
1743system.cpu1.l2cache.tags.tagsinuse 15624.003278 # Cycle average of tags in use
1744system.cpu1.l2cache.tags.total_refs 2421583 # Total number of references to valid blocks.
1745system.cpu1.l2cache.tags.sampled_refs 84278 # Sample count of references to valid blocks.
1746system.cpu1.l2cache.tags.avg_refs 28.733276 # Average number of references to valid blocks.
1747system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1748system.cpu1.l2cache.tags.occ_blocks::writebacks 6091.947681 # Average occupied blocks per requestor
1749system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 59.671167 # Average occupied blocks per requestor
1750system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.103493 # Average occupied blocks per requestor
1751system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5612.930096 # Average occupied blocks per requestor
1752system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2321.677903 # Average occupied blocks per requestor
1753system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1537.672938 # Average occupied blocks per requestor
1754system.cpu1.l2cache.tags.occ_percent::writebacks 0.371823 # Average percentage of cache occupancy
1755system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003642 # Average percentage of cache occupancy
1756system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy
1757system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.342586 # Average percentage of cache occupancy
1758system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.141704 # Average percentage of cache occupancy
1759system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093852 # Average percentage of cache occupancy
1760system.cpu1.l2cache.tags.occ_percent::total 0.953613 # Average percentage of cache occupancy
1761system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1225 # Occupied blocks per task id
1762system.cpu1.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
1763system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13444 # Occupied blocks per task id
1764system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id
1765system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 697 # Occupied blocks per task id
1766system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 522 # Occupied blocks per task id
1767system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id
1768system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
1769system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
1770system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id
1771system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5775 # Occupied blocks per task id
1772system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7342 # Occupied blocks per task id
1773system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074768 # Percentage of cache occupancy per task id
1774system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id
1775system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.820557 # Percentage of cache occupancy per task id
1776system.cpu1.l2cache.tags.tag_accesses 42869923 # Number of tag accesses
1777system.cpu1.l2cache.tags.data_accesses 42869923 # Number of data accesses
1778system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33040 # number of ReadReq hits
1779system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2583 # number of ReadReq hits
1780system.cpu1.l2cache.ReadReq_hits::total 35623 # number of ReadReq hits
1781system.cpu1.l2cache.Writeback_hits::writebacks 138377 # number of Writeback hits
1782system.cpu1.l2cache.Writeback_hits::total 138377 # number of Writeback hits
1783system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2042 # number of UpgradeReq hits
1784system.cpu1.l2cache.UpgradeReq_hits::total 2042 # number of UpgradeReq hits
1785system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1012 # number of SCUpgradeReq hits
1786system.cpu1.l2cache.SCUpgradeReq_hits::total 1012 # number of SCUpgradeReq hits
1787system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37732 # number of ReadExReq hits
1788system.cpu1.l2cache.ReadExReq_hits::total 37732 # number of ReadExReq hits
1789system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1015029 # number of ReadCleanReq hits
1790system.cpu1.l2cache.ReadCleanReq_hits::total 1015029 # number of ReadCleanReq hits
1791system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 131048 # number of ReadSharedReq hits
1792system.cpu1.l2cache.ReadSharedReq_hits::total 131048 # number of ReadSharedReq hits
1793system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 33040 # number of demand (read+write) hits
1794system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2583 # number of demand (read+write) hits
1795system.cpu1.l2cache.demand_hits::cpu1.inst 1015029 # number of demand (read+write) hits
1796system.cpu1.l2cache.demand_hits::cpu1.data 168780 # number of demand (read+write) hits
1797system.cpu1.l2cache.demand_hits::total 1219432 # number of demand (read+write) hits
1798system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 33040 # number of overall hits
1799system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2583 # number of overall hits
1800system.cpu1.l2cache.overall_hits::cpu1.inst 1015029 # number of overall hits
1801system.cpu1.l2cache.overall_hits::cpu1.data 168780 # number of overall hits
1802system.cpu1.l2cache.overall_hits::total 1219432 # number of overall hits
1803system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 727 # number of ReadReq misses
1804system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 221 # number of ReadReq misses
1805system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses
1806system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29373 # number of UpgradeReq misses
1807system.cpu1.l2cache.UpgradeReq_misses::total 29373 # number of UpgradeReq misses
1808system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22436 # number of SCUpgradeReq misses
1809system.cpu1.l2cache.SCUpgradeReq_misses::total 22436 # number of SCUpgradeReq misses
1810system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
1811system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
1812system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36088 # number of ReadExReq misses
1813system.cpu1.l2cache.ReadExReq_misses::total 36088 # number of ReadExReq misses
1814system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 27608 # number of ReadCleanReq misses
1815system.cpu1.l2cache.ReadCleanReq_misses::total 27608 # number of ReadCleanReq misses
1816system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73984 # number of ReadSharedReq misses
1817system.cpu1.l2cache.ReadSharedReq_misses::total 73984 # number of ReadSharedReq misses
1818system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 727 # number of demand (read+write) misses
1819system.cpu1.l2cache.demand_misses::cpu1.itb.walker 221 # number of demand (read+write) misses
1820system.cpu1.l2cache.demand_misses::cpu1.inst 27608 # number of demand (read+write) misses
1821system.cpu1.l2cache.demand_misses::cpu1.data 110072 # number of demand (read+write) misses
1822system.cpu1.l2cache.demand_misses::total 138628 # number of demand (read+write) misses
1823system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 727 # number of overall misses
1824system.cpu1.l2cache.overall_misses::cpu1.itb.walker 221 # number of overall misses
1825system.cpu1.l2cache.overall_misses::cpu1.inst 27608 # number of overall misses
1826system.cpu1.l2cache.overall_misses::cpu1.data 110072 # number of overall misses
1827system.cpu1.l2cache.overall_misses::total 138628 # number of overall misses
1828system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 18603000 # number of ReadReq miss cycles
1829system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4457500 # number of ReadReq miss cycles
1830system.cpu1.l2cache.ReadReq_miss_latency::total 23060500 # number of ReadReq miss cycles
1831system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 554124000 # number of UpgradeReq miss cycles
1832system.cpu1.l2cache.UpgradeReq_miss_latency::total 554124000 # number of UpgradeReq miss cycles
1833system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449909000 # number of SCUpgradeReq miss cycles
1834system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449909000 # number of SCUpgradeReq miss cycles
1835system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 652000 # number of SCUpgradeFailReq miss cycles
1836system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 652000 # number of SCUpgradeFailReq miss cycles
1837system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1418232500 # number of ReadExReq miss cycles
1838system.cpu1.l2cache.ReadExReq_miss_latency::total 1418232500 # number of ReadExReq miss cycles
1839system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1071283000 # number of ReadCleanReq miss cycles
1840system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1071283000 # number of ReadCleanReq miss cycles
1841system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1763586495 # number of ReadSharedReq miss cycles
1842system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1763586495 # number of ReadSharedReq miss cycles
1843system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 18603000 # number of demand (read+write) miss cycles
1844system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4457500 # number of demand (read+write) miss cycles
1845system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1071283000 # number of demand (read+write) miss cycles
1846system.cpu1.l2cache.demand_miss_latency::cpu1.data 3181818995 # number of demand (read+write) miss cycles
1847system.cpu1.l2cache.demand_miss_latency::total 4276162495 # number of demand (read+write) miss cycles
1848system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 18603000 # number of overall miss cycles
1849system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4457500 # number of overall miss cycles
1850system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1071283000 # number of overall miss cycles
1851system.cpu1.l2cache.overall_miss_latency::cpu1.data 3181818995 # number of overall miss cycles
1852system.cpu1.l2cache.overall_miss_latency::total 4276162495 # number of overall miss cycles
1853system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33767 # number of ReadReq accesses(hits+misses)
1854system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2804 # number of ReadReq accesses(hits+misses)
1855system.cpu1.l2cache.ReadReq_accesses::total 36571 # number of ReadReq accesses(hits+misses)
1856system.cpu1.l2cache.Writeback_accesses::writebacks 138377 # number of Writeback accesses(hits+misses)
1857system.cpu1.l2cache.Writeback_accesses::total 138377 # number of Writeback accesses(hits+misses)
1858system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31415 # number of UpgradeReq accesses(hits+misses)
1859system.cpu1.l2cache.UpgradeReq_accesses::total 31415 # number of UpgradeReq accesses(hits+misses)
1860system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23448 # number of SCUpgradeReq accesses(hits+misses)
1861system.cpu1.l2cache.SCUpgradeReq_accesses::total 23448 # number of SCUpgradeReq accesses(hits+misses)
1862system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1863system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1864system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73820 # number of ReadExReq accesses(hits+misses)
1865system.cpu1.l2cache.ReadExReq_accesses::total 73820 # number of ReadExReq accesses(hits+misses)
1866system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1042637 # number of ReadCleanReq accesses(hits+misses)
1867system.cpu1.l2cache.ReadCleanReq_accesses::total 1042637 # number of ReadCleanReq accesses(hits+misses)
1868system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 205032 # number of ReadSharedReq accesses(hits+misses)
1869system.cpu1.l2cache.ReadSharedReq_accesses::total 205032 # number of ReadSharedReq accesses(hits+misses)
1870system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33767 # number of demand (read+write) accesses
1871system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2804 # number of demand (read+write) accesses
1872system.cpu1.l2cache.demand_accesses::cpu1.inst 1042637 # number of demand (read+write) accesses
1873system.cpu1.l2cache.demand_accesses::cpu1.data 278852 # number of demand (read+write) accesses
1874system.cpu1.l2cache.demand_accesses::total 1358060 # number of demand (read+write) accesses
1875system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33767 # number of overall (read+write) accesses
1876system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2804 # number of overall (read+write) accesses
1877system.cpu1.l2cache.overall_accesses::cpu1.inst 1042637 # number of overall (read+write) accesses
1878system.cpu1.l2cache.overall_accesses::cpu1.data 278852 # number of overall (read+write) accesses
1879system.cpu1.l2cache.overall_accesses::total 1358060 # number of overall (read+write) accesses
1880system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021530 # miss rate for ReadReq accesses
1881system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.078816 # miss rate for ReadReq accesses
1882system.cpu1.l2cache.ReadReq_miss_rate::total 0.025922 # miss rate for ReadReq accesses
1883system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.934999 # miss rate for UpgradeReq accesses
1884system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.934999 # miss rate for UpgradeReq accesses
1885system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.956841 # miss rate for SCUpgradeReq accesses
1886system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.956841 # miss rate for SCUpgradeReq accesses
1887system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1888system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1889system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.488865 # miss rate for ReadExReq accesses
1890system.cpu1.l2cache.ReadExReq_miss_rate::total 0.488865 # miss rate for ReadExReq accesses
1891system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026479 # miss rate for ReadCleanReq accesses
1892system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026479 # miss rate for ReadCleanReq accesses
1893system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.360841 # miss rate for ReadSharedReq accesses
1894system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.360841 # miss rate for ReadSharedReq accesses
1895system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021530 # miss rate for demand accesses
1896system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.078816 # miss rate for demand accesses
1897system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026479 # miss rate for demand accesses
1898system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.394733 # miss rate for demand accesses
1899system.cpu1.l2cache.demand_miss_rate::total 0.102078 # miss rate for demand accesses
1900system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021530 # miss rate for overall accesses
1901system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.078816 # miss rate for overall accesses
1902system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026479 # miss rate for overall accesses
1903system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.394733 # miss rate for overall accesses
1904system.cpu1.l2cache.overall_miss_rate::total 0.102078 # miss rate for overall accesses
1905system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25588.720770 # average ReadReq miss latency
1906system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.683258 # average ReadReq miss latency
1907system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24325.421941 # average ReadReq miss latency
1908system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18865.080176 # average UpgradeReq miss latency
1909system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18865.080176 # average UpgradeReq miss latency
1910system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20052.995186 # average SCUpgradeReq miss latency
1911system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20052.995186 # average SCUpgradeReq miss latency
1912system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 326000 # average SCUpgradeFailReq miss latency
1913system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 326000 # average SCUpgradeFailReq miss latency
1914system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39299.282310 # average ReadExReq miss latency
1915system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39299.282310 # average ReadExReq miss latency
1916system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38803.354100 # average ReadCleanReq miss latency
1917system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38803.354100 # average ReadCleanReq miss latency
1918system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23837.403966 # average ReadSharedReq miss latency
1919system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23837.403966 # average ReadSharedReq miss latency
1920system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25588.720770 # average overall miss latency
1921system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.683258 # average overall miss latency
1922system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38803.354100 # average overall miss latency
1923system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28906.706474 # average overall miss latency
1924system.cpu1.l2cache.demand_avg_miss_latency::total 30846.311676 # average overall miss latency
1925system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25588.720770 # average overall miss latency
1926system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.683258 # average overall miss latency
1927system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38803.354100 # average overall miss latency
1928system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28906.706474 # average overall miss latency
1929system.cpu1.l2cache.overall_avg_miss_latency::total 30846.311676 # average overall miss latency
1930system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1931system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1932system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1933system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1934system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1935system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1936system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
1937system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
1938system.cpu1.l2cache.writebacks::writebacks 36799 # number of writebacks
1939system.cpu1.l2cache.writebacks::total 36799 # number of writebacks
1940system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 302 # number of ReadExReq MSHR hits
1941system.cpu1.l2cache.ReadExReq_mshr_hits::total 302 # number of ReadExReq MSHR hits
1942system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 26 # number of ReadCleanReq MSHR hits
1943system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
1944system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 134 # number of ReadSharedReq MSHR hits
1945system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 134 # number of ReadSharedReq MSHR hits
1946system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 26 # number of demand (read+write) MSHR hits
1947system.cpu1.l2cache.demand_mshr_hits::cpu1.data 436 # number of demand (read+write) MSHR hits
1948system.cpu1.l2cache.demand_mshr_hits::total 462 # number of demand (read+write) MSHR hits
1949system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 26 # number of overall MSHR hits
1950system.cpu1.l2cache.overall_mshr_hits::cpu1.data 436 # number of overall MSHR hits
1951system.cpu1.l2cache.overall_mshr_hits::total 462 # number of overall MSHR hits
1952system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 727 # number of ReadReq MSHR misses
1953system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 221 # number of ReadReq MSHR misses
1954system.cpu1.l2cache.ReadReq_mshr_misses::total 948 # number of ReadReq MSHR misses
1955system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3205 # number of CleanEvict MSHR misses
1956system.cpu1.l2cache.CleanEvict_mshr_misses::total 3205 # number of CleanEvict MSHR misses
1957system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35196 # number of HardPFReq MSHR misses
1958system.cpu1.l2cache.HardPFReq_mshr_misses::total 35196 # number of HardPFReq MSHR misses
1959system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29373 # number of UpgradeReq MSHR misses
1960system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29373 # number of UpgradeReq MSHR misses
1961system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22436 # number of SCUpgradeReq MSHR misses
1962system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22436 # number of SCUpgradeReq MSHR misses
1963system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
1964system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
1965system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35786 # number of ReadExReq MSHR misses
1966system.cpu1.l2cache.ReadExReq_mshr_misses::total 35786 # number of ReadExReq MSHR misses
1967system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 27582 # number of ReadCleanReq MSHR misses
1968system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 27582 # number of ReadCleanReq MSHR misses
1969system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73850 # number of ReadSharedReq MSHR misses
1970system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73850 # number of ReadSharedReq MSHR misses
1971system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 727 # number of demand (read+write) MSHR misses
1972system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 221 # number of demand (read+write) MSHR misses
1973system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27582 # number of demand (read+write) MSHR misses
1974system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109636 # number of demand (read+write) MSHR misses
1975system.cpu1.l2cache.demand_mshr_misses::total 138166 # number of demand (read+write) MSHR misses
1976system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 727 # number of overall MSHR misses
1977system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 221 # number of overall MSHR misses
1978system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27582 # number of overall MSHR misses
1979system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109636 # number of overall MSHR misses
1980system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35196 # number of overall MSHR misses
1981system.cpu1.l2cache.overall_mshr_misses::total 173362 # number of overall MSHR misses
1982system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 113 # number of ReadReq MSHR uncacheable
1983system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17128 # number of ReadReq MSHR uncacheable
1984system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17241 # number of ReadReq MSHR uncacheable
1985system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14405 # number of WriteReq MSHR uncacheable
1986system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14405 # number of WriteReq MSHR uncacheable
1987system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 113 # number of overall MSHR uncacheable misses
1988system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31533 # number of overall MSHR uncacheable misses
1989system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31646 # number of overall MSHR uncacheable misses
1990system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of ReadReq MSHR miss cycles
1991system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3131500 # number of ReadReq MSHR miss cycles
1992system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 17372500 # number of ReadReq MSHR miss cycles
1993system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1238467331 # number of HardPFReq MSHR miss cycles
1994system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1238467331 # number of HardPFReq MSHR miss cycles
1995system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 502709499 # number of UpgradeReq MSHR miss cycles
1996system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 502709499 # number of UpgradeReq MSHR miss cycles
1997system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348029000 # number of SCUpgradeReq MSHR miss cycles
1998system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348029000 # number of SCUpgradeReq MSHR miss cycles
1999system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 574000 # number of SCUpgradeFailReq MSHR miss cycles
2000system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 574000 # number of SCUpgradeFailReq MSHR miss cycles
2001system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1167759000 # number of ReadExReq MSHR miss cycles
2002system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1167759000 # number of ReadExReq MSHR miss cycles
2003system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 904893000 # number of ReadCleanReq MSHR miss cycles
2004system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 904893000 # number of ReadCleanReq MSHR miss cycles
2005system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1316095995 # number of ReadSharedReq MSHR miss cycles
2006system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1316095995 # number of ReadSharedReq MSHR miss cycles
2007system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of demand (read+write) MSHR miss cycles
2008system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3131500 # number of demand (read+write) MSHR miss cycles
2009system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 904893000 # number of demand (read+write) MSHR miss cycles
2010system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2483854995 # number of demand (read+write) MSHR miss cycles
2011system.cpu1.l2cache.demand_mshr_miss_latency::total 3406120495 # number of demand (read+write) MSHR miss cycles
2012system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of overall MSHR miss cycles
2013system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3131500 # number of overall MSHR miss cycles
2014system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 904893000 # number of overall MSHR miss cycles
2015system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2483854995 # number of overall MSHR miss cycles
2016system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1238467331 # number of overall MSHR miss cycles
2017system.cpu1.l2cache.overall_mshr_miss_latency::total 4644587826 # number of overall MSHR miss cycles
2018system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9222000 # number of ReadReq MSHR uncacheable cycles
2019system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2797805500 # number of ReadReq MSHR uncacheable cycles
2020system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2807027500 # number of ReadReq MSHR uncacheable cycles
2021system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2338455000 # number of WriteReq MSHR uncacheable cycles
2022system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2338455000 # number of WriteReq MSHR uncacheable cycles
2023system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9222000 # number of overall MSHR uncacheable cycles
2024system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5136260500 # number of overall MSHR uncacheable cycles
2025system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5145482500 # number of overall MSHR uncacheable cycles
2026system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for ReadReq accesses
2027system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for ReadReq accesses
2028system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025922 # mshr miss rate for ReadReq accesses
2029system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2030system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2031system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2032system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2033system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.934999 # mshr miss rate for UpgradeReq accesses
2034system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.934999 # mshr miss rate for UpgradeReq accesses
2035system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.956841 # mshr miss rate for SCUpgradeReq accesses
2036system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.956841 # mshr miss rate for SCUpgradeReq accesses
2037system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2038system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2039system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.484774 # mshr miss rate for ReadExReq accesses
2040system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.484774 # mshr miss rate for ReadExReq accesses
2041system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for ReadCleanReq accesses
2042system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026454 # mshr miss rate for ReadCleanReq accesses
2043system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.360188 # mshr miss rate for ReadSharedReq accesses
2044system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.360188 # mshr miss rate for ReadSharedReq accesses
2045system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for demand accesses
2046system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for demand accesses
2047system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for demand accesses
2048system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393169 # mshr miss rate for demand accesses
2049system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101738 # mshr miss rate for demand accesses
2050system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for overall accesses
2051system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for overall accesses
2052system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for overall accesses
2053system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393169 # mshr miss rate for overall accesses
2054system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2055system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127654 # mshr miss rate for overall accesses
2056system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average ReadReq mshr miss latency
2057system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average ReadReq mshr miss latency
2058system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18325.421941 # average ReadReq mshr miss latency
2059system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600 # average HardPFReq mshr miss latency
2060system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35187.729600 # average HardPFReq mshr miss latency
2061system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17114.680114 # average UpgradeReq mshr miss latency
2062system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17114.680114 # average UpgradeReq mshr miss latency
2063system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15512.078802 # average SCUpgradeReq mshr miss latency
2064system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15512.078802 # average SCUpgradeReq mshr miss latency
2065system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 287000 # average SCUpgradeFailReq mshr miss latency
2066system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 287000 # average SCUpgradeFailReq mshr miss latency
2067system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32631.727491 # average ReadExReq mshr miss latency
2068system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32631.727491 # average ReadExReq mshr miss latency
2069system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average ReadCleanReq mshr miss latency
2070system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32807.374375 # average ReadCleanReq mshr miss latency
2071system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17821.205078 # average ReadSharedReq mshr miss latency
2072system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17821.205078 # average ReadSharedReq mshr miss latency
2073system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average overall mshr miss latency
2074system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average overall mshr miss latency
2075system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average overall mshr miss latency
2076system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22655.468961 # average overall mshr miss latency
2077system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24652.378262 # average overall mshr miss latency
2078system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average overall mshr miss latency
2079system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average overall mshr miss latency
2080system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average overall mshr miss latency
2081system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22655.468961 # average overall mshr miss latency
2082system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600 # average overall mshr miss latency
2083system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26791.268133 # average overall mshr miss latency
2084system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469 # average ReadReq mshr uncacheable latency
2085system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163346.888136 # average ReadReq mshr uncacheable latency
2086system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162811.176846 # average ReadReq mshr uncacheable latency
2087system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162336.341548 # average WriteReq mshr uncacheable latency
2088system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162336.341548 # average WriteReq mshr uncacheable latency
2089system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469 # average overall mshr uncacheable latency
2090system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162885.247201 # average overall mshr uncacheable latency
2091system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162595.035708 # average overall mshr uncacheable latency
2092system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2093system.cpu1.toL2Bus.trans_dist::ReadReq 81005 # Transaction distribution
2094system.cpu1.toL2Bus.trans_dist::ReadResp 1348099 # Transaction distribution
2095system.cpu1.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution
2096system.cpu1.toL2Bus.trans_dist::WriteResp 14405 # Transaction distribution
2097system.cpu1.toL2Bus.trans_dist::Writeback 510462 # Transaction distribution
2098system.cpu1.toL2Bus.trans_dist::CleanEvict 1265020 # Transaction distribution
2099system.cpu1.toL2Bus.trans_dist::HardPFReq 43516 # Transaction distribution
2100system.cpu1.toL2Bus.trans_dist::UpgradeReq 77320 # Transaction distribution
2101system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42972 # Transaction distribution
2102system.cpu1.toL2Bus.trans_dist::UpgradeResp 89288 # Transaction distribution
2103system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
2104system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution
2105system.cpu1.toL2Bus.trans_dist::ReadExReq 97251 # Transaction distribution
2106system.cpu1.toL2Bus.trans_dist::ReadExResp 79776 # Transaction distribution
2107system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1042637 # Transaction distribution
2108system.cpu1.toL2Bus.trans_dist::ReadSharedReq 559861 # Transaction distribution
2109system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2110system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3108261 # Packet count per connected master and slave (bytes)
2111system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1040223 # Packet count per connected master and slave (bytes)
2112system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7202 # Packet count per connected master and slave (bytes)
2113system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71706 # Packet count per connected master and slave (bytes)
2114system.cpu1.toL2Bus.pkt_count::total 4227392 # Packet count per connected master and slave (bytes)
2115system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66736000 # Cumulative packet size per connected master and slave (bytes)
2116system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29812791 # Cumulative packet size per connected master and slave (bytes)
2117system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11216 # Cumulative packet size per connected master and slave (bytes)
2118system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135068 # Cumulative packet size per connected master and slave (bytes)
2119system.cpu1.toL2Bus.pkt_size::total 96695075 # Cumulative packet size per connected master and slave (bytes)
2120system.cpu1.toL2Bus.snoops 1172897 # Total snoops (count)
2121system.cpu1.toL2Bus.snoop_fanout::samples 3809713 # Request fanout histogram
2122system.cpu1.toL2Bus.snoop_fanout::mean 1.296141 # Request fanout histogram
2123system.cpu1.toL2Bus.snoop_fanout::stdev 0.456554 # Request fanout histogram
2124system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2125system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2126system.cpu1.toL2Bus.snoop_fanout::1 2681500 70.39% 70.39% # Request fanout histogram
2127system.cpu1.toL2Bus.snoop_fanout::2 1128213 29.61% 100.00% # Request fanout histogram
2128system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2129system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2130system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2131system.cpu1.toL2Bus.snoop_fanout::total 3809713 # Request fanout histogram
2132system.cpu1.toL2Bus.reqLayer0.occupancy 1507501992 # Layer occupancy (ticks)
2133system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2134system.cpu1.toL2Bus.snoopLayer0.occupancy 87443999 # Layer occupancy (ticks)
2135system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2136system.cpu1.toL2Bus.respLayer0.occupancy 1564193862 # Layer occupancy (ticks)
2137system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2138system.cpu1.toL2Bus.respLayer1.occupancy 470956198 # Layer occupancy (ticks)
2139system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2140system.cpu1.toL2Bus.respLayer2.occupancy 4398499 # Layer occupancy (ticks)
2141system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2142system.cpu1.toL2Bus.respLayer3.occupancy 37948980 # Layer occupancy (ticks)
2143system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2144system.iobus.trans_dist::ReadReq 31013 # Transaction distribution
2145system.iobus.trans_dist::ReadResp 31013 # Transaction distribution
2146system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
2147system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
2148system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
2149system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2150system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2151system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2152system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2153system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes)
2154system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2155system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2156system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2157system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2158system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2159system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2160system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2161system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2162system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2163system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2164system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2165system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2166system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2167system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2168system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2169system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes)
2170system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes)
2171system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes)
2172system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
2173system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
2174system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2175system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2176system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2177system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2178system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes)
2179system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2180system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2181system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2182system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2183system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2184system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2185system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2186system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2187system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2188system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2189system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2190system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
2191system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2192system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
2193system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2194system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes)
2195system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes)
2196system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes)
2197system.iobus.pkt_size::total 2484073 # Cumulative packet size per connected master and slave (bytes)
2198system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks)
2199system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2200system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
2201system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2202system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
2203system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2204system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
2205system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2206system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
2207system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2208system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks)
2209system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2210system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
2211system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2212system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2213system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2214system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
2215system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2216system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)

--- 13 unchanged lines hidden (view full) ---

2230system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
2231system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2232system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
2233system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2234system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
2235system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2236system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
2237system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2238system.iobus.reqLayer27.occupancy 187545199 # Layer occupancy (ticks)
2239system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2240system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2241system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2242system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks)
2243system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2244system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks)
2245system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2246system.iocache.tags.replacements 36462 # number of replacements
2247system.iocache.tags.tagsinuse 14.479963 # Cycle average of tags in use
2248system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2249system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks.
2250system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2251system.iocache.tags.warmup_cycle 270370198000 # Cycle when the warmup percentage was hit.
2252system.iocache.tags.occ_blocks::realview.ide 14.479963 # Average occupied blocks per requestor
2253system.iocache.tags.occ_percent::realview.ide 0.904998 # Average percentage of cache occupancy
2254system.iocache.tags.occ_percent::total 0.904998 # Average percentage of cache occupancy
2255system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2256system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2257system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2258system.iocache.tags.tag_accesses 328320 # Number of tag accesses
2259system.iocache.tags.data_accesses 328320 # Number of data accesses
2260system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses
2261system.iocache.ReadReq_misses::total 256 # number of ReadReq misses
2262system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2263system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2264system.iocache.demand_misses::realview.ide 256 # number of demand (read+write) misses
2265system.iocache.demand_misses::total 256 # number of demand (read+write) misses
2266system.iocache.overall_misses::realview.ide 256 # number of overall misses
2267system.iocache.overall_misses::total 256 # number of overall misses
2268system.iocache.ReadReq_miss_latency::realview.ide 32688877 # number of ReadReq miss cycles
2269system.iocache.ReadReq_miss_latency::total 32688877 # number of ReadReq miss cycles
2270system.iocache.WriteLineReq_miss_latency::realview.ide 4277206322 # number of WriteLineReq miss cycles
2271system.iocache.WriteLineReq_miss_latency::total 4277206322 # number of WriteLineReq miss cycles
2272system.iocache.demand_miss_latency::realview.ide 32688877 # number of demand (read+write) miss cycles
2273system.iocache.demand_miss_latency::total 32688877 # number of demand (read+write) miss cycles
2274system.iocache.overall_miss_latency::realview.ide 32688877 # number of overall miss cycles
2275system.iocache.overall_miss_latency::total 32688877 # number of overall miss cycles
2276system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses)
2277system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses)
2278system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2279system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2280system.iocache.demand_accesses::realview.ide 256 # number of demand (read+write) accesses
2281system.iocache.demand_accesses::total 256 # number of demand (read+write) accesses
2282system.iocache.overall_accesses::realview.ide 256 # number of overall (read+write) accesses
2283system.iocache.overall_accesses::total 256 # number of overall (read+write) accesses
2284system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2285system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2286system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2287system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2288system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2289system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2290system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2291system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2292system.iocache.ReadReq_avg_miss_latency::realview.ide 127690.925781 # average ReadReq miss latency
2293system.iocache.ReadReq_avg_miss_latency::total 127690.925781 # average ReadReq miss latency
2294system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118076.587953 # average WriteLineReq miss latency
2295system.iocache.WriteLineReq_avg_miss_latency::total 118076.587953 # average WriteLineReq miss latency
2296system.iocache.demand_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency
2297system.iocache.demand_avg_miss_latency::total 127690.925781 # average overall miss latency
2298system.iocache.overall_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency
2299system.iocache.overall_avg_miss_latency::total 127690.925781 # average overall miss latency
2300system.iocache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked
2301system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2302system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
2303system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2304system.iocache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked
2305system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2306system.iocache.fast_writes 0 # number of fast writes performed
2307system.iocache.cache_copies 0 # number of cache copies performed
2308system.iocache.writebacks::writebacks 36206 # number of writebacks
2309system.iocache.writebacks::total 36206 # number of writebacks
2310system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses
2311system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses
2312system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2313system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2314system.iocache.demand_mshr_misses::realview.ide 256 # number of demand (read+write) MSHR misses
2315system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses
2316system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses
2317system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses
2318system.iocache.ReadReq_mshr_miss_latency::realview.ide 19888877 # number of ReadReq MSHR miss cycles
2319system.iocache.ReadReq_mshr_miss_latency::total 19888877 # number of ReadReq MSHR miss cycles
2320system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466006322 # number of WriteLineReq MSHR miss cycles
2321system.iocache.WriteLineReq_mshr_miss_latency::total 2466006322 # number of WriteLineReq MSHR miss cycles
2322system.iocache.demand_mshr_miss_latency::realview.ide 19888877 # number of demand (read+write) MSHR miss cycles
2323system.iocache.demand_mshr_miss_latency::total 19888877 # number of demand (read+write) MSHR miss cycles
2324system.iocache.overall_mshr_miss_latency::realview.ide 19888877 # number of overall MSHR miss cycles
2325system.iocache.overall_mshr_miss_latency::total 19888877 # number of overall MSHR miss cycles
2326system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2327system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2328system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2329system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2330system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2331system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2332system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2333system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2334system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77690.925781 # average ReadReq mshr miss latency
2335system.iocache.ReadReq_avg_mshr_miss_latency::total 77690.925781 # average ReadReq mshr miss latency
2336system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68076.587953 # average WriteLineReq mshr miss latency
2337system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68076.587953 # average WriteLineReq mshr miss latency
2338system.iocache.demand_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency
2339system.iocache.demand_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency
2340system.iocache.overall_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency
2341system.iocache.overall_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency
2342system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2343system.l2c.tags.replacements 134724 # number of replacements
2344system.l2c.tags.tagsinuse 64068.233504 # Cycle average of tags in use
2345system.l2c.tags.total_refs 443602 # Total number of references to valid blocks.
2346system.l2c.tags.sampled_refs 199053 # Sample count of references to valid blocks.
2347system.l2c.tags.avg_refs 2.228562 # Average number of references to valid blocks.
2348system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2349system.l2c.tags.occ_blocks::writebacks 12835.902941 # Average occupied blocks per requestor
2350system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.531822 # Average occupied blocks per requestor
2351system.l2c.tags.occ_blocks::cpu0.itb.walker 0.025215 # Average occupied blocks per requestor
2352system.l2c.tags.occ_blocks::cpu0.inst 7257.127456 # Average occupied blocks per requestor
2353system.l2c.tags.occ_blocks::cpu0.data 2101.817094 # Average occupied blocks per requestor
2354system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32009.024605 # Average occupied blocks per requestor
2355system.l2c.tags.occ_blocks::cpu1.dtb.walker 30.126345 # Average occupied blocks per requestor
2356system.l2c.tags.occ_blocks::cpu1.inst 4045.876721 # Average occupied blocks per requestor
2357system.l2c.tags.occ_blocks::cpu1.data 1535.093827 # Average occupied blocks per requestor
2358system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4184.707478 # Average occupied blocks per requestor
2359system.l2c.tags.occ_percent::writebacks 0.195860 # Average percentage of cache occupancy
2360system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001046 # Average percentage of cache occupancy
2361system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
2362system.l2c.tags.occ_percent::cpu0.inst 0.110735 # Average percentage of cache occupancy
2363system.l2c.tags.occ_percent::cpu0.data 0.032071 # Average percentage of cache occupancy
2364system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.488419 # Average percentage of cache occupancy
2365system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000460 # Average percentage of cache occupancy
2366system.l2c.tags.occ_percent::cpu1.inst 0.061735 # Average percentage of cache occupancy
2367system.l2c.tags.occ_percent::cpu1.data 0.023424 # Average percentage of cache occupancy
2368system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.063854 # Average percentage of cache occupancy
2369system.l2c.tags.occ_percent::total 0.977604 # Average percentage of cache occupancy
2370system.l2c.tags.occ_task_id_blocks::1022 29296 # Occupied blocks per task id
2371system.l2c.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id
2372system.l2c.tags.occ_task_id_blocks::1024 34966 # Occupied blocks per task id
2373system.l2c.tags.age_task_id_blocks_1022::2 113 # Occupied blocks per task id
2374system.l2c.tags.age_task_id_blocks_1022::3 5383 # Occupied blocks per task id
2375system.l2c.tags.age_task_id_blocks_1022::4 23800 # Occupied blocks per task id
2376system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
2377system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id
2378system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
2379system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
2380system.l2c.tags.age_task_id_blocks_1024::2 313 # Occupied blocks per task id
2381system.l2c.tags.age_task_id_blocks_1024::3 2923 # Occupied blocks per task id
2382system.l2c.tags.age_task_id_blocks_1024::4 31711 # Occupied blocks per task id
2383system.l2c.tags.occ_task_id_percent::1022 0.447021 # Percentage of cache occupancy per task id
2384system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id
2385system.l2c.tags.occ_task_id_percent::1024 0.533539 # Percentage of cache occupancy per task id
2386system.l2c.tags.tag_accesses 5827626 # Number of tag accesses
2387system.l2c.tags.data_accesses 5827626 # Number of data accesses
2388system.l2c.Writeback_hits::writebacks 232709 # number of Writeback hits
2389system.l2c.Writeback_hits::total 232709 # number of Writeback hits
2390system.l2c.UpgradeReq_hits::cpu0.data 3025 # number of UpgradeReq hits
2391system.l2c.UpgradeReq_hits::cpu1.data 939 # number of UpgradeReq hits
2392system.l2c.UpgradeReq_hits::total 3964 # number of UpgradeReq hits
2393system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits
2394system.l2c.SCUpgradeReq_hits::cpu1.data 83 # number of SCUpgradeReq hits
2395system.l2c.SCUpgradeReq_hits::total 340 # number of SCUpgradeReq hits
2396system.l2c.ReadExReq_hits::cpu0.data 4055 # number of ReadExReq hits
2397system.l2c.ReadExReq_hits::cpu1.data 2183 # number of ReadExReq hits
2398system.l2c.ReadExReq_hits::total 6238 # number of ReadExReq hits
2399system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 387 # number of ReadSharedReq hits
2400system.l2c.ReadSharedReq_hits::cpu0.itb.walker 52 # number of ReadSharedReq hits
2401system.l2c.ReadSharedReq_hits::cpu0.inst 44381 # number of ReadSharedReq hits
2402system.l2c.ReadSharedReq_hits::cpu0.data 47292 # number of ReadSharedReq hits
2403system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46189 # number of ReadSharedReq hits
2404system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 171 # number of ReadSharedReq hits
2405system.l2c.ReadSharedReq_hits::cpu1.itb.walker 33 # number of ReadSharedReq hits
2406system.l2c.ReadSharedReq_hits::cpu1.inst 21681 # number of ReadSharedReq hits
2407system.l2c.ReadSharedReq_hits::cpu1.data 11241 # number of ReadSharedReq hits
2408system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8230 # number of ReadSharedReq hits
2409system.l2c.ReadSharedReq_hits::total 179657 # number of ReadSharedReq hits
2410system.l2c.demand_hits::cpu0.dtb.walker 387 # number of demand (read+write) hits
2411system.l2c.demand_hits::cpu0.itb.walker 52 # number of demand (read+write) hits
2412system.l2c.demand_hits::cpu0.inst 44381 # number of demand (read+write) hits
2413system.l2c.demand_hits::cpu0.data 51347 # number of demand (read+write) hits
2414system.l2c.demand_hits::cpu0.l2cache.prefetcher 46189 # number of demand (read+write) hits
2415system.l2c.demand_hits::cpu1.dtb.walker 171 # number of demand (read+write) hits
2416system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits
2417system.l2c.demand_hits::cpu1.inst 21681 # number of demand (read+write) hits
2418system.l2c.demand_hits::cpu1.data 13424 # number of demand (read+write) hits
2419system.l2c.demand_hits::cpu1.l2cache.prefetcher 8230 # number of demand (read+write) hits
2420system.l2c.demand_hits::total 185895 # number of demand (read+write) hits
2421system.l2c.overall_hits::cpu0.dtb.walker 387 # number of overall hits
2422system.l2c.overall_hits::cpu0.itb.walker 52 # number of overall hits
2423system.l2c.overall_hits::cpu0.inst 44381 # number of overall hits
2424system.l2c.overall_hits::cpu0.data 51347 # number of overall hits
2425system.l2c.overall_hits::cpu0.l2cache.prefetcher 46189 # number of overall hits
2426system.l2c.overall_hits::cpu1.dtb.walker 171 # number of overall hits
2427system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits
2428system.l2c.overall_hits::cpu1.inst 21681 # number of overall hits
2429system.l2c.overall_hits::cpu1.data 13424 # number of overall hits
2430system.l2c.overall_hits::cpu1.l2cache.prefetcher 8230 # number of overall hits
2431system.l2c.overall_hits::total 185895 # number of overall hits
2432system.l2c.UpgradeReq_misses::cpu0.data 8753 # number of UpgradeReq misses
2433system.l2c.UpgradeReq_misses::cpu1.data 4074 # number of UpgradeReq misses
2434system.l2c.UpgradeReq_misses::total 12827 # number of UpgradeReq misses
2435system.l2c.SCUpgradeReq_misses::cpu0.data 797 # number of SCUpgradeReq misses
2436system.l2c.SCUpgradeReq_misses::cpu1.data 1213 # number of SCUpgradeReq misses
2437system.l2c.SCUpgradeReq_misses::total 2010 # number of SCUpgradeReq misses
2438system.l2c.ReadExReq_misses::cpu0.data 10969 # number of ReadExReq misses
2439system.l2c.ReadExReq_misses::cpu1.data 8454 # number of ReadExReq misses
2440system.l2c.ReadExReq_misses::total 19423 # number of ReadExReq misses
2441system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 121 # number of ReadSharedReq misses
2442system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses
2443system.l2c.ReadSharedReq_misses::cpu0.inst 19546 # number of ReadSharedReq misses
2444system.l2c.ReadSharedReq_misses::cpu0.data 8542 # number of ReadSharedReq misses
2445system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 128715 # number of ReadSharedReq misses
2446system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 43 # number of ReadSharedReq misses
2447system.l2c.ReadSharedReq_misses::cpu1.inst 5890 # number of ReadSharedReq misses
2448system.l2c.ReadSharedReq_misses::cpu1.data 2696 # number of ReadSharedReq misses
2449system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8977 # number of ReadSharedReq misses
2450system.l2c.ReadSharedReq_misses::total 174531 # number of ReadSharedReq misses
2451system.l2c.demand_misses::cpu0.dtb.walker 121 # number of demand (read+write) misses
2452system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
2453system.l2c.demand_misses::cpu0.inst 19546 # number of demand (read+write) misses
2454system.l2c.demand_misses::cpu0.data 19511 # number of demand (read+write) misses
2455system.l2c.demand_misses::cpu0.l2cache.prefetcher 128715 # number of demand (read+write) misses
2456system.l2c.demand_misses::cpu1.dtb.walker 43 # number of demand (read+write) misses
2457system.l2c.demand_misses::cpu1.inst 5890 # number of demand (read+write) misses
2458system.l2c.demand_misses::cpu1.data 11150 # number of demand (read+write) misses
2459system.l2c.demand_misses::cpu1.l2cache.prefetcher 8977 # number of demand (read+write) misses
2460system.l2c.demand_misses::total 193954 # number of demand (read+write) misses
2461system.l2c.overall_misses::cpu0.dtb.walker 121 # number of overall misses
2462system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
2463system.l2c.overall_misses::cpu0.inst 19546 # number of overall misses
2464system.l2c.overall_misses::cpu0.data 19511 # number of overall misses
2465system.l2c.overall_misses::cpu0.l2cache.prefetcher 128715 # number of overall misses
2466system.l2c.overall_misses::cpu1.dtb.walker 43 # number of overall misses
2467system.l2c.overall_misses::cpu1.inst 5890 # number of overall misses
2468system.l2c.overall_misses::cpu1.data 11150 # number of overall misses
2469system.l2c.overall_misses::cpu1.l2cache.prefetcher 8977 # number of overall misses
2470system.l2c.overall_misses::total 193954 # number of overall misses
2471system.l2c.UpgradeReq_miss_latency::cpu0.data 9167000 # number of UpgradeReq miss cycles
2472system.l2c.UpgradeReq_miss_latency::cpu1.data 5104000 # number of UpgradeReq miss cycles
2473system.l2c.UpgradeReq_miss_latency::total 14271000 # number of UpgradeReq miss cycles
2474system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1330000 # number of SCUpgradeReq miss cycles
2475system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1451500 # number of SCUpgradeReq miss cycles
2476system.l2c.SCUpgradeReq_miss_latency::total 2781500 # number of SCUpgradeReq miss cycles
2477system.l2c.ReadExReq_miss_latency::cpu0.data 1087997000 # number of ReadExReq miss cycles
2478system.l2c.ReadExReq_miss_latency::cpu1.data 696148000 # number of ReadExReq miss cycles
2479system.l2c.ReadExReq_miss_latency::total 1784145000 # number of ReadExReq miss cycles
2480system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 10392000 # number of ReadSharedReq miss cycles
2481system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 303000 # number of ReadSharedReq miss cycles
2482system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1558395000 # number of ReadSharedReq miss cycles
2483system.l2c.ReadSharedReq_miss_latency::cpu0.data 749223000 # number of ReadSharedReq miss cycles
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2485system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 3962000 # number of ReadSharedReq miss cycles
2486system.l2c.ReadSharedReq_miss_latency::cpu1.inst 483846500 # number of ReadSharedReq miss cycles
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2489system.l2c.ReadSharedReq_miss_latency::total 17184117504 # number of ReadSharedReq miss cycles
2490system.l2c.demand_miss_latency::cpu0.dtb.walker 10392000 # number of demand (read+write) miss cycles
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2495system.l2c.demand_miss_latency::cpu1.dtb.walker 3962000 # number of demand (read+write) miss cycles
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2498system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1069849511 # number of demand (read+write) miss cycles
2499system.l2c.demand_miss_latency::total 18968262504 # number of demand (read+write) miss cycles
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2501system.l2c.overall_miss_latency::cpu0.itb.walker 303000 # number of overall miss cycles
2502system.l2c.overall_miss_latency::cpu0.inst 1558395000 # number of overall miss cycles
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2506system.l2c.overall_miss_latency::cpu1.inst 483846500 # number of overall miss cycles
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2509system.l2c.overall_miss_latency::total 18968262504 # number of overall miss cycles
2510system.l2c.Writeback_accesses::writebacks 232709 # number of Writeback accesses(hits+misses)
2511system.l2c.Writeback_accesses::total 232709 # number of Writeback accesses(hits+misses)
2512system.l2c.UpgradeReq_accesses::cpu0.data 11778 # number of UpgradeReq accesses(hits+misses)
2513system.l2c.UpgradeReq_accesses::cpu1.data 5013 # number of UpgradeReq accesses(hits+misses)
2514system.l2c.UpgradeReq_accesses::total 16791 # number of UpgradeReq accesses(hits+misses)
2515system.l2c.SCUpgradeReq_accesses::cpu0.data 1054 # number of SCUpgradeReq accesses(hits+misses)
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2527system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 33 # number of ReadSharedReq accesses(hits+misses)
2528system.l2c.ReadSharedReq_accesses::cpu1.inst 27571 # number of ReadSharedReq accesses(hits+misses)
2529system.l2c.ReadSharedReq_accesses::cpu1.data 13937 # number of ReadSharedReq accesses(hits+misses)
2530system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 17207 # number of ReadSharedReq accesses(hits+misses)
2531system.l2c.ReadSharedReq_accesses::total 354188 # number of ReadSharedReq accesses(hits+misses)
2532system.l2c.demand_accesses::cpu0.dtb.walker 508 # number of demand (read+write) accesses
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2543system.l2c.overall_accesses::cpu0.dtb.walker 508 # number of overall (read+write) accesses
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2553system.l2c.overall_accesses::total 379849 # number of overall (read+write) accesses
2554system.l2c.UpgradeReq_miss_rate::cpu0.data 0.743165 # miss rate for UpgradeReq accesses
2555system.l2c.UpgradeReq_miss_rate::cpu1.data 0.812687 # miss rate for UpgradeReq accesses
2556system.l2c.UpgradeReq_miss_rate::total 0.763921 # miss rate for UpgradeReq accesses
2557system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.756167 # miss rate for SCUpgradeReq accesses
2558system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.935957 # miss rate for SCUpgradeReq accesses
2559system.l2c.SCUpgradeReq_miss_rate::total 0.855319 # miss rate for SCUpgradeReq accesses
2560system.l2c.ReadExReq_miss_rate::cpu0.data 0.730099 # miss rate for ReadExReq accesses
2561system.l2c.ReadExReq_miss_rate::cpu1.data 0.794773 # miss rate for ReadExReq accesses
2562system.l2c.ReadExReq_miss_rate::total 0.756907 # miss rate for ReadExReq accesses
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2564system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.018868 # miss rate for ReadSharedReq accesses
2565system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.305755 # miss rate for ReadSharedReq accesses
2566system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.152989 # miss rate for ReadSharedReq accesses
2567system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.735918 # miss rate for ReadSharedReq accesses
2568system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.200935 # miss rate for ReadSharedReq accesses
2569system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.213630 # miss rate for ReadSharedReq accesses
2570system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.193442 # miss rate for ReadSharedReq accesses
2571system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.521706 # miss rate for ReadSharedReq accesses
2572system.l2c.ReadSharedReq_miss_rate::total 0.492764 # miss rate for ReadSharedReq accesses
2573system.l2c.demand_miss_rate::cpu0.dtb.walker 0.238189 # miss rate for demand accesses
2574system.l2c.demand_miss_rate::cpu0.itb.walker 0.018868 # miss rate for demand accesses
2575system.l2c.demand_miss_rate::cpu0.inst 0.305755 # miss rate for demand accesses
2576system.l2c.demand_miss_rate::cpu0.data 0.275354 # miss rate for demand accesses
2577system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735918 # miss rate for demand accesses
2578system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200935 # miss rate for demand accesses
2579system.l2c.demand_miss_rate::cpu1.inst 0.213630 # miss rate for demand accesses
2580system.l2c.demand_miss_rate::cpu1.data 0.453732 # miss rate for demand accesses
2581system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.521706 # miss rate for demand accesses
2582system.l2c.demand_miss_rate::total 0.510608 # miss rate for demand accesses
2583system.l2c.overall_miss_rate::cpu0.dtb.walker 0.238189 # miss rate for overall accesses
2584system.l2c.overall_miss_rate::cpu0.itb.walker 0.018868 # miss rate for overall accesses
2585system.l2c.overall_miss_rate::cpu0.inst 0.305755 # miss rate for overall accesses
2586system.l2c.overall_miss_rate::cpu0.data 0.275354 # miss rate for overall accesses
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2588system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200935 # miss rate for overall accesses
2589system.l2c.overall_miss_rate::cpu1.inst 0.213630 # miss rate for overall accesses
2590system.l2c.overall_miss_rate::cpu1.data 0.453732 # miss rate for overall accesses
2591system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.521706 # miss rate for overall accesses
2592system.l2c.overall_miss_rate::total 0.510608 # miss rate for overall accesses
2593system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1047.298069 # average UpgradeReq miss latency
2594system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1252.822779 # average UpgradeReq miss latency
2595system.l2c.UpgradeReq_avg_miss_latency::total 1112.575037 # average UpgradeReq miss latency
2596system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1668.757842 # average SCUpgradeReq miss latency
2597system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1196.619951 # average SCUpgradeReq miss latency
2598system.l2c.SCUpgradeReq_avg_miss_latency::total 1383.830846 # average SCUpgradeReq miss latency
2599system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99188.348983 # average ReadExReq miss latency
2600system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82345.398628 # average ReadExReq miss latency
2601system.l2c.ReadExReq_avg_miss_latency::total 91857.334088 # average ReadExReq miss latency
2602system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 85884.297521 # average ReadSharedReq miss latency
2603system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 303000 # average ReadSharedReq miss latency
2604system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 79729.612197 # average ReadSharedReq miss latency
2605system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87710.489347 # average ReadSharedReq miss latency
2606system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287 # average ReadSharedReq miss latency
2607system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92139.534884 # average ReadSharedReq miss latency
2608system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82147.113752 # average ReadSharedReq miss latency
2609system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89111.646884 # average ReadSharedReq miss latency
2610system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645 # average ReadSharedReq miss latency
2611system.l2c.ReadSharedReq_avg_miss_latency::total 98458.826822 # average ReadSharedReq miss latency
2612system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85884.297521 # average overall miss latency
2613system.l2c.demand_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency
2614system.l2c.demand_avg_miss_latency::cpu0.inst 79729.612197 # average overall miss latency
2615system.l2c.demand_avg_miss_latency::cpu0.data 94163.292502 # average overall miss latency
2616system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287 # average overall miss latency
2617system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92139.534884 # average overall miss latency
2618system.l2c.demand_avg_miss_latency::cpu1.inst 82147.113752 # average overall miss latency
2619system.l2c.demand_avg_miss_latency::cpu1.data 83981.434978 # average overall miss latency
2620system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645 # average overall miss latency
2621system.l2c.demand_avg_miss_latency::total 97797.738144 # average overall miss latency
2622system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85884.297521 # average overall miss latency
2623system.l2c.overall_avg_miss_latency::cpu0.itb.walker 303000 # average overall miss latency
2624system.l2c.overall_avg_miss_latency::cpu0.inst 79729.612197 # average overall miss latency
2625system.l2c.overall_avg_miss_latency::cpu0.data 94163.292502 # average overall miss latency
2626system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101525.863287 # average overall miss latency
2627system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92139.534884 # average overall miss latency
2628system.l2c.overall_avg_miss_latency::cpu1.inst 82147.113752 # average overall miss latency
2629system.l2c.overall_avg_miss_latency::cpu1.data 83981.434978 # average overall miss latency
2630system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119176.730645 # average overall miss latency
2631system.l2c.overall_avg_miss_latency::total 97797.738144 # average overall miss latency
2632system.l2c.blocked_cycles::no_mshrs 442 # number of cycles access was blocked
2633system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2634system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked
2635system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2636system.l2c.avg_blocked_cycles::no_mshrs 221 # average number of cycles each access was blocked
2637system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2638system.l2c.fast_writes 0 # number of fast writes performed
2639system.l2c.cache_copies 0 # number of cache copies performed
2640system.l2c.writebacks::writebacks 103131 # number of writebacks
2641system.l2c.writebacks::total 103131 # number of writebacks
2642system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
2643system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits
2644system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits
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2647system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
2648system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
2649system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
2650system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
2651system.l2c.CleanEvict_mshr_misses::writebacks 3812 # number of CleanEvict MSHR misses
2652system.l2c.CleanEvict_mshr_misses::total 3812 # number of CleanEvict MSHR misses
2653system.l2c.UpgradeReq_mshr_misses::cpu0.data 8753 # number of UpgradeReq MSHR misses
2654system.l2c.UpgradeReq_mshr_misses::cpu1.data 4074 # number of UpgradeReq MSHR misses
2655system.l2c.UpgradeReq_mshr_misses::total 12827 # number of UpgradeReq MSHR misses
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2657system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1213 # number of SCUpgradeReq MSHR misses
2658system.l2c.SCUpgradeReq_mshr_misses::total 2010 # number of SCUpgradeReq MSHR misses
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2671system.l2c.ReadSharedReq_mshr_misses::total 174522 # number of ReadSharedReq MSHR misses
2672system.l2c.demand_mshr_misses::cpu0.dtb.walker 121 # number of demand (read+write) MSHR misses
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2676system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128715 # number of demand (read+write) MSHR misses
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2680system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8977 # number of demand (read+write) MSHR misses
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2691system.l2c.overall_mshr_misses::total 193945 # number of overall MSHR misses
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2693system.l2c.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable
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2695system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17124 # number of ReadReq MSHR uncacheable
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2703system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31529 # number of overall MSHR uncacheable misses
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2706system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 84589501 # number of UpgradeReq MSHR miss cycles
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2708system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16646000 # number of SCUpgradeReq MSHR miss cycles
2709system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25174500 # number of SCUpgradeReq MSHR miss cycles
2710system.l2c.SCUpgradeReq_mshr_miss_latency::total 41820500 # number of SCUpgradeReq MSHR miss cycles
2711system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 978307000 # number of ReadExReq MSHR miss cycles
2712system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 611608000 # number of ReadExReq MSHR miss cycles
2713system.l2c.ReadExReq_mshr_miss_latency::total 1589915000 # number of ReadExReq MSHR miss cycles
2714system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 9182000 # number of ReadSharedReq MSHR miss cycles
2715system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 293000 # number of ReadSharedReq MSHR miss cycles
2716system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1362728000 # number of ReadSharedReq MSHR miss cycles
2717system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 663803000 # number of ReadSharedReq MSHR miss cycles
2718system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11780751493 # number of ReadSharedReq MSHR miss cycles
2719system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 3532000 # number of ReadSharedReq MSHR miss cycles
2720system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 424750500 # number of ReadSharedReq MSHR miss cycles
2721system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 213285000 # number of ReadSharedReq MSHR miss cycles
2722system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 980079511 # number of ReadSharedReq MSHR miss cycles
2723system.l2c.ReadSharedReq_mshr_miss_latency::total 15438404504 # number of ReadSharedReq MSHR miss cycles
2724system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9182000 # number of demand (read+write) MSHR miss cycles
2725system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) MSHR miss cycles
2726system.l2c.demand_mshr_miss_latency::cpu0.inst 1362728000 # number of demand (read+write) MSHR miss cycles
2727system.l2c.demand_mshr_miss_latency::cpu0.data 1642110000 # number of demand (read+write) MSHR miss cycles
2728system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11780751493 # number of demand (read+write) MSHR miss cycles
2729system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3532000 # number of demand (read+write) MSHR miss cycles
2730system.l2c.demand_mshr_miss_latency::cpu1.inst 424750500 # number of demand (read+write) MSHR miss cycles
2731system.l2c.demand_mshr_miss_latency::cpu1.data 824893000 # number of demand (read+write) MSHR miss cycles
2732system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 980079511 # number of demand (read+write) MSHR miss cycles
2733system.l2c.demand_mshr_miss_latency::total 17028319504 # number of demand (read+write) MSHR miss cycles
2734system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9182000 # number of overall MSHR miss cycles
2735system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 293000 # number of overall MSHR miss cycles
2736system.l2c.overall_mshr_miss_latency::cpu0.inst 1362728000 # number of overall MSHR miss cycles
2737system.l2c.overall_mshr_miss_latency::cpu0.data 1642110000 # number of overall MSHR miss cycles
2738system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11780751493 # number of overall MSHR miss cycles
2739system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3532000 # number of overall MSHR miss cycles
2740system.l2c.overall_mshr_miss_latency::cpu1.inst 424750500 # number of overall MSHR miss cycles
2741system.l2c.overall_mshr_miss_latency::cpu1.data 824893000 # number of overall MSHR miss cycles
2742system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 980079511 # number of overall MSHR miss cycles
2743system.l2c.overall_mshr_miss_latency::total 17028319504 # number of overall MSHR miss cycles
2744system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 214924500 # number of ReadReq MSHR uncacheable cycles
2745system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3283233500 # number of ReadReq MSHR uncacheable cycles
2746system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6848500 # number of ReadReq MSHR uncacheable cycles
2747system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2489515500 # number of ReadReq MSHR uncacheable cycles
2748system.l2c.ReadReq_mshr_uncacheable_latency::total 5994522000 # number of ReadReq MSHR uncacheable cycles
2749system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2314676500 # number of WriteReq MSHR uncacheable cycles
2750system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2093562500 # number of WriteReq MSHR uncacheable cycles
2751system.l2c.WriteReq_mshr_uncacheable_latency::total 4408239000 # number of WriteReq MSHR uncacheable cycles
2752system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 214924500 # number of overall MSHR uncacheable cycles
2753system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5597910000 # number of overall MSHR uncacheable cycles
2754system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6848500 # number of overall MSHR uncacheable cycles
2755system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4583078000 # number of overall MSHR uncacheable cycles
2756system.l2c.overall_mshr_uncacheable_latency::total 10402761000 # number of overall MSHR uncacheable cycles
2757system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2758system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2759system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.743165 # mshr miss rate for UpgradeReq accesses
2760system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.812687 # mshr miss rate for UpgradeReq accesses
2761system.l2c.UpgradeReq_mshr_miss_rate::total 0.763921 # mshr miss rate for UpgradeReq accesses
2762system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.756167 # mshr miss rate for SCUpgradeReq accesses
2763system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935957 # mshr miss rate for SCUpgradeReq accesses
2764system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.855319 # mshr miss rate for SCUpgradeReq accesses
2765system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.730099 # mshr miss rate for ReadExReq accesses
2766system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.794773 # mshr miss rate for ReadExReq accesses
2767system.l2c.ReadExReq_mshr_miss_rate::total 0.756907 # mshr miss rate for ReadExReq accesses
2768system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for ReadSharedReq accesses
2769system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for ReadSharedReq accesses
2770system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for ReadSharedReq accesses
2771system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.152989 # mshr miss rate for ReadSharedReq accesses
2772system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for ReadSharedReq accesses
2773system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for ReadSharedReq accesses
2774system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for ReadSharedReq accesses
2775system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.193442 # mshr miss rate for ReadSharedReq accesses
2776system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for ReadSharedReq accesses
2777system.l2c.ReadSharedReq_mshr_miss_rate::total 0.492738 # mshr miss rate for ReadSharedReq accesses
2778system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for demand accesses
2779system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for demand accesses
2780system.l2c.demand_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for demand accesses
2781system.l2c.demand_mshr_miss_rate::cpu0.data 0.275354 # mshr miss rate for demand accesses
2782system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for demand accesses
2783system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for demand accesses
2784system.l2c.demand_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for demand accesses
2785system.l2c.demand_mshr_miss_rate::cpu1.data 0.453732 # mshr miss rate for demand accesses
2786system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for demand accesses
2787system.l2c.demand_mshr_miss_rate::total 0.510584 # mshr miss rate for demand accesses
2788system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for overall accesses
2789system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for overall accesses
2790system.l2c.overall_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for overall accesses
2791system.l2c.overall_mshr_miss_rate::cpu0.data 0.275354 # mshr miss rate for overall accesses
2792system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for overall accesses
2793system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for overall accesses
2794system.l2c.overall_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for overall accesses
2795system.l2c.overall_mshr_miss_rate::cpu1.data 0.453732 # mshr miss rate for overall accesses
2796system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for overall accesses
2797system.l2c.overall_mshr_miss_rate::total 0.510584 # mshr miss rate for overall accesses
2798system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20769.507597 # average UpgradeReq mshr miss latency
2799system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.255032 # average UpgradeReq mshr miss latency
2800system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20767.521712 # average UpgradeReq mshr miss latency
2801system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20885.821832 # average SCUpgradeReq mshr miss latency
2802system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20753.915911 # average SCUpgradeReq mshr miss latency
2803system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20806.218905 # average SCUpgradeReq mshr miss latency
2804system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89188.348983 # average ReadExReq mshr miss latency
2805system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72345.398628 # average ReadExReq mshr miss latency
2806system.l2c.ReadExReq_avg_mshr_miss_latency::total 81857.334088 # average ReadExReq mshr miss latency
2807system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average ReadSharedReq mshr miss latency
2808system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average ReadSharedReq mshr miss latency
2809system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average ReadSharedReq mshr miss latency
2810system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77710.489347 # average ReadSharedReq mshr miss latency
2811system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average ReadSharedReq mshr miss latency
2812system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average ReadSharedReq mshr miss latency
2813system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average ReadSharedReq mshr miss latency
2814system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79111.646884 # average ReadSharedReq mshr miss latency
2815system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average ReadSharedReq mshr miss latency
2816system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88461.079428 # average ReadSharedReq mshr miss latency
2817system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average overall mshr miss latency
2818system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency
2819system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average overall mshr miss latency
2820system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84163.292502 # average overall mshr miss latency
2821system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average overall mshr miss latency
2822system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average overall mshr miss latency
2823system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average overall mshr miss latency
2824system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73981.434978 # average overall mshr miss latency
2825system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average overall mshr miss latency
2826system.l2c.demand_avg_mshr_miss_latency::total 87799.734481 # average overall mshr miss latency
2827system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average overall mshr miss latency
2828system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency
2829system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average overall mshr miss latency
2830system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84163.292502 # average overall mshr miss latency
2831system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average overall mshr miss latency
2832system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average overall mshr miss latency
2833system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average overall mshr miss latency
2834system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73981.434978 # average overall mshr miss latency
2835system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average overall mshr miss latency
2836system.l2c.overall_avg_mshr_miss_latency::total 87799.734481 # average overall mshr miss latency
2837system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average ReadReq mshr uncacheable latency
2838system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.728237 # average ReadReq mshr uncacheable latency
2839system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average ReadReq mshr uncacheable latency
2840system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145381.657323 # average ReadReq mshr uncacheable latency
2841system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 155041.433892 # average ReadReq mshr uncacheable latency
2842system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138140.158749 # average WriteReq mshr uncacheable latency
2843system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145335.820896 # average WriteReq mshr uncacheable latency
2844system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141466.544719 # average WriteReq mshr uncacheable latency
2845system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average overall mshr uncacheable latency
2846system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161058.491815 # average overall mshr uncacheable latency
2847system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average overall mshr uncacheable latency
2848system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145360.715532 # average overall mshr uncacheable latency
2849system.l2c.overall_avg_mshr_uncacheable_latency::total 148983.329753 # average overall mshr uncacheable latency
2850system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2851system.membus.trans_dist::ReadReq 38664 # Transaction distribution
2852system.membus.trans_dist::ReadResp 213442 # Transaction distribution
2853system.membus.trans_dist::WriteReq 31161 # Transaction distribution
2854system.membus.trans_dist::WriteResp 31161 # Transaction distribution
2855system.membus.trans_dist::Writeback 139337 # Transaction distribution
2856system.membus.trans_dist::CleanEvict 18210 # Transaction distribution
2857system.membus.trans_dist::UpgradeReq 78893 # Transaction distribution
2858system.membus.trans_dist::SCUpgradeReq 41609 # Transaction distribution
2859system.membus.trans_dist::UpgradeResp 14967 # Transaction distribution
2860system.membus.trans_dist::ReadExReq 39746 # Transaction distribution
2861system.membus.trans_dist::ReadExResp 19293 # Transaction distribution
2862system.membus.trans_dist::ReadSharedReq 174778 # Transaction distribution
2863system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2864system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
2865system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes)
2866system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
2867system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14714 # Packet count per connected master and slave (bytes)
2868system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 681524 # Packet count per connected master and slave (bytes)
2869system.membus.pkt_count_system.l2c.mem_side::total 804190 # Packet count per connected master and slave (bytes)
2870system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108938 # Packet count per connected master and slave (bytes)
2871system.membus.pkt_count_system.iocache.mem_side::total 108938 # Packet count per connected master and slave (bytes)
2872system.membus.pkt_count::total 913128 # Packet count per connected master and slave (bytes)
2873system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes)
2874system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes)
2875system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29428 # Cumulative packet size per connected master and slave (bytes)
2876system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19228072 # Cumulative packet size per connected master and slave (bytes)
2877system.membus.pkt_size_system.l2c.mem_side::total 19421637 # Cumulative packet size per connected master and slave (bytes)
2878system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
2879system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
2880system.membus.pkt_size::total 21739781 # Cumulative packet size per connected master and slave (bytes)
2881system.membus.snoops 126569 # Total snoops (count)
2882system.membus.snoop_fanout::samples 598906 # Request fanout histogram
2883system.membus.snoop_fanout::mean 1 # Request fanout histogram
2884system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2885system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2886system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2887system.membus.snoop_fanout::1 598906 100.00% 100.00% # Request fanout histogram
2888system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2889system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2890system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2891system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2892system.membus.snoop_fanout::total 598906 # Request fanout histogram
2893system.membus.reqLayer0.occupancy 91147500 # Layer occupancy (ticks)
2894system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2895system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks)
2896system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2897system.membus.reqLayer2.occupancy 12904500 # Layer occupancy (ticks)
2898system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2899system.membus.reqLayer5.occupancy 1003618732 # Layer occupancy (ticks)
2900system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2901system.membus.respLayer2.occupancy 1163956699 # Layer occupancy (ticks)
2902system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2903system.membus.respLayer3.occupancy 64493538 # Layer occupancy (ticks)
2904system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2905system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2906system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2907system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2908system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2909system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2910system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2911system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

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2928system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
2929system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2930system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2931system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2932system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2933system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2934system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
2935system.realview.ethernet.droppedPackets 0 # number of packets dropped
2936system.toL2Bus.trans_dist::ReadReq 38668 # Transaction distribution
2937system.toL2Bus.trans_dist::ReadResp 519865 # Transaction distribution
2938system.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution
2939system.toL2Bus.trans_dist::WriteResp 31161 # Transaction distribution
2940system.toL2Bus.trans_dist::Writeback 372085 # Transaction distribution
2941system.toL2Bus.trans_dist::CleanEvict 99404 # Transaction distribution
2942system.toL2Bus.trans_dist::UpgradeReq 82727 # Transaction distribution
2943system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution
2944system.toL2Bus.trans_dist::UpgradeResp 124676 # Transaction distribution
2945system.toL2Bus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution
2946system.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution
2947system.toL2Bus.trans_dist::ReadExReq 51768 # Transaction distribution
2948system.toL2Bus.trans_dist::ReadExResp 51768 # Transaction distribution
2949system.toL2Bus.trans_dist::ReadSharedReq 481212 # Transaction distribution
2950system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2951system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1091980 # Packet count per connected master and slave (bytes)
2952system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 404567 # Packet count per connected master and slave (bytes)
2953system.toL2Bus.pkt_count::total 1496547 # Packet count per connected master and slave (bytes)
2954system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32727326 # Cumulative packet size per connected master and slave (bytes)
2955system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6930535 # Cumulative packet size per connected master and slave (bytes)
2956system.toL2Bus.pkt_size::total 39657861 # Cumulative packet size per connected master and slave (bytes)
2957system.toL2Bus.snoops 466410 # Total snoops (count)
2958system.toL2Bus.snoop_fanout::samples 1287380 # Request fanout histogram
2959system.toL2Bus.snoop_fanout::mean 1.161360 # Request fanout histogram
2960system.toL2Bus.snoop_fanout::stdev 0.367862 # Request fanout histogram
2961system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2962system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2963system.toL2Bus.snoop_fanout::1 1079649 83.86% 83.86% # Request fanout histogram
2964system.toL2Bus.snoop_fanout::2 207731 16.14% 100.00% # Request fanout histogram
2965system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2966system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2967system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2968system.toL2Bus.snoop_fanout::total 1287380 # Request fanout histogram
2969system.toL2Bus.reqLayer0.occupancy 861414818 # Layer occupancy (ticks)
2970system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2971system.toL2Bus.snoopLayer0.occupancy 361500 # Layer occupancy (ticks)
2972system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2973system.toL2Bus.respLayer0.occupancy 631551677 # Layer occupancy (ticks)
2974system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2975system.toL2Bus.respLayer1.occupancy 286263459 # Layer occupancy (ticks)
2976system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2977
2978---------- End Simulation Statistics ----------