simerr (11570:4aac82f10951) simerr (11957:90bb43dfc028)
1warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
1warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
2info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
2warn: Sockets disabled, not accepting vnc client connections
3warn: Sockets disabled, not accepting terminal connections
4warn: Sockets disabled, not accepting gdb connections
5warn: ClockedObject: More than one power state change request encountered within the same simulation tick
6warn: ClockedObject: More than one power state change request encountered within the same simulation tick
3warn: Sockets disabled, not accepting vnc client connections
4warn: Sockets disabled, not accepting terminal connections
5warn: Sockets disabled, not accepting gdb connections
6warn: ClockedObject: More than one power state change request encountered within the same simulation tick
7warn: ClockedObject: More than one power state change request encountered within the same simulation tick
8info: Using bootloader at address 0x10
9info: Using kernel entry physical address at 0x80008000
10info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
7warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
11warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
12info: Entering event queue @ 0. Starting simulation...
8warn: Not doing anything for miscreg ACTLR
9warn: Not doing anything for write of miscreg ACTLR
10warn: The clidr register always reports 0 caches.
11warn: clidr LoUIS field of 0b001 to match current ARM implementations.
12warn: The csselr register isn't implemented.
13warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
14warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
15warn: instruction 'mcr dccmvau' unimplemented

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22warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
23warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
24warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
25warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
26warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
27warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
28warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
29warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
13warn: Not doing anything for miscreg ACTLR
14warn: Not doing anything for write of miscreg ACTLR
15warn: The clidr register always reports 0 caches.
16warn: clidr LoUIS field of 0b001 to match current ARM implementations.
17warn: The csselr register isn't implemented.
18warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
19warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
20warn: instruction 'mcr dccmvau' unimplemented

--- 6 unchanged lines hidden (view full) ---

27warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
28warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
29warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
30warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
31warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
32warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
33warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
34warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
35info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
36info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
37info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
38info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
39info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
40info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
41info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
30warn: Not doing anything for miscreg ACTLR
31warn: Not doing anything for write of miscreg ACTLR
32warn: instruction 'mcr bpiall' unimplemented
42warn: Not doing anything for miscreg ACTLR
43warn: Not doing anything for write of miscreg ACTLR
44warn: instruction 'mcr bpiall' unimplemented
45info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
46info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
33warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
47warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
48info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
49info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
50info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
51info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
52info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
53info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
34warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
35warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
36warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
37warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
38warn: Returning zero for read from miscreg pmcr
39warn: Ignoring write to miscreg pmcntenclr
40warn: Ignoring write to miscreg pmintenclr
41warn: Ignoring write to miscreg pmovsr
42warn: Ignoring write to miscreg pmcr
43warn: Ignoring write to miscreg pmcntenclr
44warn: Ignoring write to miscreg pmintenclr
45warn: Ignoring write to miscreg pmovsr
46warn: Ignoring write to miscreg pmcr
54warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
55warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
56warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
57warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
58warn: Returning zero for read from miscreg pmcr
59warn: Ignoring write to miscreg pmcntenclr
60warn: Ignoring write to miscreg pmintenclr
61warn: Ignoring write to miscreg pmovsr
62warn: Ignoring write to miscreg pmcr
63warn: Ignoring write to miscreg pmcntenclr
64warn: Ignoring write to miscreg pmintenclr
65warn: Ignoring write to miscreg pmovsr
66warn: Ignoring write to miscreg pmcr