| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.860198 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.860198 # Number of seconds simulated |
| 4sim_ticks 1860197608000 # Number of ticks simulated 5final_tick 1860197608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 1860197780500 # Number of ticks simulated 5final_tick 1860197780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 128608 # Simulator instruction rate (inst/s) 8host_op_rate 128608 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4515644283 # Simulator tick rate (ticks/s) 10host_mem_usage 336512 # Number of bytes of host memory used 11host_seconds 411.95 # Real time elapsed on the host 12sim_insts 52979573 # Number of instructions simulated 13sim_ops 52979573 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 964544 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24879808 # Number of bytes read from this memory | 7host_inst_rate 103834 # Simulator instruction rate (inst/s) 8host_op_rate 103834 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3645751305 # Simulator tick rate (ticks/s) 10host_mem_usage 355004 # Number of bytes of host memory used 11host_seconds 510.24 # Real time elapsed on the host 12sim_insts 52979882 # Number of instructions simulated 13sim_ops 52979882 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24878976 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::total 28496640 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 964544 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 964544 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7516672 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7516672 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15071 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388747 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::total 28495232 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7515456 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7515456 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388734 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory | 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::total 445260 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117448 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117448 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 518517 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13374820 # Total read bandwidth from this memory (bytes/s) | 25system.physmem.num_reads::total 445238 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117429 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117429 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 518207 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13374371 # Total read bandwidth from this memory (bytes/s) |
| 30system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s) | 30system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s) |
| 31system.physmem.bw_read::total 15319147 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 518517 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 518517 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4040792 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4040792 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4040792 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 518517 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13374820 # Total bandwidth to/from this memory (bytes/s) | 31system.physmem.bw_read::total 15318388 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 518207 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 518207 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4040138 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4040138 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4040138 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 518207 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13374371 # Total bandwidth to/from this memory (bytes/s) |
| 39system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s) |
| 40system.physmem.bw_total::total 19359939 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 445260 # Number of read requests accepted 42system.physmem.writeReqs 117448 # Number of write requests accepted 43system.physmem.readBursts 445260 # Number of DRAM read bursts, including those serviced by the write queue 44system.physmem.writeBursts 117448 # Number of DRAM write bursts, including those merged in the write queue 45system.physmem.bytesReadDRAM 28493888 # Total number of bytes read from DRAM 46system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue 47system.physmem.bytesWritten 7515904 # Total number of bytes written to DRAM 48system.physmem.bytesReadSys 28496640 # Total read bytes from the system interface side 49system.physmem.bytesWrittenSys 7516672 # Total written bytes from the system interface side 50system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue | 40system.physmem.bw_total::total 19358526 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 445238 # Number of read requests accepted 42system.physmem.writeReqs 117429 # Number of write requests accepted 43system.physmem.readBursts 445238 # Number of DRAM read bursts, including those serviced by the write queue 44system.physmem.writeBursts 117429 # Number of DRAM write bursts, including those merged in the write queue 45system.physmem.bytesReadDRAM 28492032 # Total number of bytes read from DRAM 46system.physmem.bytesReadWrQ 3200 # Total number of bytes read from write queue 47system.physmem.bytesWritten 7514752 # Total number of bytes written to DRAM 48system.physmem.bytesReadSys 28495232 # Total read bytes from the system interface side 49system.physmem.bytesWrittenSys 7515456 # Total written bytes from the system interface side 50system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by the write queue |
| 51system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 51system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 52system.physmem.neitherReadNorWriteReqs 177 # Number of requests that are neither read nor write | 52system.physmem.neitherReadNorWriteReqs 179 # Number of requests that are neither read nor write |
| 53system.physmem.perBankRdBursts::0 28229 # Per bank write bursts 54system.physmem.perBankRdBursts::1 27970 # Per bank write bursts | 53system.physmem.perBankRdBursts::0 28229 # Per bank write bursts 54system.physmem.perBankRdBursts::1 27970 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::2 28438 # Per bank write bursts 56system.physmem.perBankRdBursts::3 28034 # Per bank write bursts 57system.physmem.perBankRdBursts::4 27800 # Per bank write bursts 58system.physmem.perBankRdBursts::5 27233 # Per bank write bursts | 55system.physmem.perBankRdBursts::2 28433 # Per bank write bursts 56system.physmem.perBankRdBursts::3 28029 # Per bank write bursts 57system.physmem.perBankRdBursts::4 27802 # Per bank write bursts 58system.physmem.perBankRdBursts::5 27222 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::6 27248 # Per bank write bursts | 59system.physmem.perBankRdBursts::6 27248 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::7 27300 # Per bank write bursts 61system.physmem.perBankRdBursts::8 27656 # Per bank write bursts 62system.physmem.perBankRdBursts::9 27404 # Per bank write bursts 63system.physmem.perBankRdBursts::10 27929 # Per bank write bursts 64system.physmem.perBankRdBursts::11 27540 # Per bank write bursts 65system.physmem.perBankRdBursts::12 27555 # Per bank write bursts 66system.physmem.perBankRdBursts::13 28228 # Per bank write bursts 67system.physmem.perBankRdBursts::14 28334 # Per bank write bursts 68system.physmem.perBankRdBursts::15 28319 # Per bank write bursts 69system.physmem.perBankWrBursts::0 7929 # Per bank write bursts 70system.physmem.perBankWrBursts::1 7498 # Per bank write bursts 71system.physmem.perBankWrBursts::2 7947 # Per bank write bursts | 60system.physmem.perBankRdBursts::7 27296 # Per bank write bursts 61system.physmem.perBankRdBursts::8 27665 # Per bank write bursts 62system.physmem.perBankRdBursts::9 27395 # Per bank write bursts 63system.physmem.perBankRdBursts::10 27922 # Per bank write bursts 64system.physmem.perBankRdBursts::11 27539 # Per bank write bursts 65system.physmem.perBankRdBursts::12 27561 # Per bank write bursts 66system.physmem.perBankRdBursts::13 28227 # Per bank write bursts 67system.physmem.perBankRdBursts::14 28327 # Per bank write bursts 68system.physmem.perBankRdBursts::15 28323 # Per bank write bursts 69system.physmem.perBankWrBursts::0 7932 # Per bank write bursts 70system.physmem.perBankWrBursts::1 7497 # Per bank write bursts 71system.physmem.perBankWrBursts::2 7944 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::3 7517 # Per bank write bursts | 72system.physmem.perBankWrBursts::3 7517 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::4 7338 # Per bank write bursts 74system.physmem.perBankWrBursts::5 6689 # Per bank write bursts 75system.physmem.perBankWrBursts::6 6763 # Per bank write bursts 76system.physmem.perBankWrBursts::7 6689 # Per bank write bursts 77system.physmem.perBankWrBursts::8 7098 # Per bank write bursts 78system.physmem.perBankWrBursts::9 6803 # Per bank write bursts 79system.physmem.perBankWrBursts::10 7320 # Per bank write bursts 80system.physmem.perBankWrBursts::11 6984 # Per bank write bursts 81system.physmem.perBankWrBursts::12 7119 # Per bank write bursts 82system.physmem.perBankWrBursts::13 7873 # Per bank write bursts 83system.physmem.perBankWrBursts::14 8054 # Per bank write bursts 84system.physmem.perBankWrBursts::15 7815 # Per bank write bursts | 73system.physmem.perBankWrBursts::4 7343 # Per bank write bursts 74system.physmem.perBankWrBursts::5 6680 # Per bank write bursts 75system.physmem.perBankWrBursts::6 6761 # Per bank write bursts 76system.physmem.perBankWrBursts::7 6683 # Per bank write bursts 77system.physmem.perBankWrBursts::8 7104 # Per bank write bursts 78system.physmem.perBankWrBursts::9 6801 # Per bank write bursts 79system.physmem.perBankWrBursts::10 7313 # Per bank write bursts 80system.physmem.perBankWrBursts::11 6981 # Per bank write bursts 81system.physmem.perBankWrBursts::12 7123 # Per bank write bursts 82system.physmem.perBankWrBursts::13 7875 # Per bank write bursts 83system.physmem.perBankWrBursts::14 8050 # Per bank write bursts 84system.physmem.perBankWrBursts::15 7814 # Per bank write bursts |
| 85system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 85system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 86system.physmem.numWrRetry 10 # Number of times write queue was full causing retry 87system.physmem.totGap 1860192151000 # Total gap between requests | 86system.physmem.numWrRetry 8 # Number of times write queue was full causing retry 87system.physmem.totGap 1860192344000 # Total gap between requests |
| 88system.physmem.readPktSize::0 0 # Read request sizes (log2) 89system.physmem.readPktSize::1 0 # Read request sizes (log2) 90system.physmem.readPktSize::2 0 # Read request sizes (log2) 91system.physmem.readPktSize::3 0 # Read request sizes (log2) 92system.physmem.readPktSize::4 0 # Read request sizes (log2) 93system.physmem.readPktSize::5 0 # Read request sizes (log2) | 88system.physmem.readPktSize::0 0 # Read request sizes (log2) 89system.physmem.readPktSize::1 0 # Read request sizes (log2) 90system.physmem.readPktSize::2 0 # Read request sizes (log2) 91system.physmem.readPktSize::3 0 # Read request sizes (log2) 92system.physmem.readPktSize::4 0 # Read request sizes (log2) 93system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 94system.physmem.readPktSize::6 445260 # Read request sizes (log2) | 94system.physmem.readPktSize::6 445238 # Read request sizes (log2) |
| 95system.physmem.writePktSize::0 0 # Write request sizes (log2) 96system.physmem.writePktSize::1 0 # Write request sizes (log2) 97system.physmem.writePktSize::2 0 # Write request sizes (log2) 98system.physmem.writePktSize::3 0 # Write request sizes (log2) 99system.physmem.writePktSize::4 0 # Write request sizes (log2) 100system.physmem.writePktSize::5 0 # Write request sizes (log2) | 95system.physmem.writePktSize::0 0 # Write request sizes (log2) 96system.physmem.writePktSize::1 0 # Write request sizes (log2) 97system.physmem.writePktSize::2 0 # Write request sizes (log2) 98system.physmem.writePktSize::3 0 # Write request sizes (log2) 99system.physmem.writePktSize::4 0 # Write request sizes (log2) 100system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 101system.physmem.writePktSize::6 117448 # Write request sizes (log2) 102system.physmem.rdQLenPdf::0 332300 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::1 66452 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::2 20080 # What read queue length does an incoming req see | 101system.physmem.writePktSize::6 117429 # Write request sizes (log2) 102system.physmem.rdQLenPdf::0 332275 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::1 66533 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::2 19911 # What read queue length does an incoming req see |
| 105system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see | 105system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::4 2367 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::5 2323 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::6 1383 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::8 1330 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::10 1308 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::11 1260 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::12 1086 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::13 969 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::14 961 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::15 957 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::16 959 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::17 956 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see | 106system.physmem.rdQLenPdf::4 2385 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::5 2335 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::6 1391 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::7 1359 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::8 1343 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::9 1445 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::11 1259 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::12 1090 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::13 974 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::18 957 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::19 955 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see |
| 124system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 124system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 134system.physmem.wrQLenPdf::0 4575 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 4599 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 4612 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 5298 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 6030 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 5377 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 5380 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 5481 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 5547 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 4866 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 4858 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 4841 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 5677 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 5771 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 5766 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 5851 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 5889 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 5000 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 5021 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 4940 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 5474 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 342 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 195 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 52 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 31 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 28 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see 166system.physmem.bytesPerActivate::samples 43193 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::mean 833.653601 # Bytes accessed per row activation 168system.physmem.bytesPerActivate::gmean 238.014185 # Bytes accessed per row activation 169system.physmem.bytesPerActivate::stdev 1939.409877 # Bytes accessed per row activation 170system.physmem.bytesPerActivate::64-67 14703 34.04% 34.04% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::128-131 6277 14.53% 48.57% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::192-195 4438 10.27% 58.85% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::256-259 2692 6.23% 65.08% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::320-323 1642 3.80% 68.88% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::384-387 1371 3.17% 72.06% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::448-451 939 2.17% 74.23% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::512-515 792 1.83% 76.06% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::576-579 658 1.52% 77.59% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::640-643 515 1.19% 78.78% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::704-707 623 1.44% 80.22% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::768-771 600 1.39% 81.61% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::832-835 275 0.64% 82.25% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::896-899 275 0.64% 82.88% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::960-963 263 0.61% 83.49% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1024-1027 360 0.83% 84.33% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1088-1091 192 0.44% 84.77% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1152-1155 168 0.39% 85.16% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1216-1219 100 0.23% 85.39% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1280-1283 208 0.48% 85.87% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1344-1347 111 0.26% 86.13% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1408-1411 353 0.82% 86.95% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1472-1475 185 0.43% 87.38% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1536-1539 668 1.55% 88.92% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1600-1603 85 0.20% 89.12% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.18% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1728-1731 47 0.11% 89.29% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1792-1795 186 0.43% 89.72% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.82% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1920-1923 74 0.17% 89.99% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.19% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2048-2051 80 0.19% 90.37% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2112-2115 97 0.22% 90.60% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.77% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2240-2243 19 0.04% 90.81% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2304-2307 108 0.25% 91.06% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2368-2371 28 0.06% 91.13% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2432-2435 15 0.03% 91.16% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2496-2499 1 0.00% 91.16% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2560-2563 16 0.04% 91.20% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2624-2627 2 0.00% 91.20% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.23% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2752-2755 24 0.06% 91.29% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2816-2819 101 0.23% 91.52% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2880-2883 13 0.03% 91.55% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2944-2947 66 0.15% 91.71% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.90% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3072-3075 39 0.09% 91.99% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3136-3139 82 0.19% 92.18% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3200-3203 66 0.15% 92.33% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3264-3267 13 0.03% 92.36% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3328-3331 95 0.22% 92.58% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.63% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3456-3459 10 0.02% 92.65% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.66% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.69% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3648-3651 3 0.01% 92.70% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.72% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3776-3779 24 0.06% 92.78% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3840-3843 91 0.21% 92.99% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3904-3907 11 0.03% 93.02% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.17% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.36% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4096-4099 39 0.09% 93.45% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4160-4163 79 0.18% 93.63% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.79% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.81% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4352-4355 94 0.22% 94.03% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4416-4419 22 0.05% 94.08% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4480-4483 12 0.03% 94.11% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4544-4547 4 0.01% 94.12% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.14% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.15% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4736-4739 12 0.03% 94.18% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.23% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.44% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4928-4931 13 0.03% 94.47% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4992-4995 67 0.16% 94.63% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.82% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.90% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.08% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5248-5251 68 0.16% 95.24% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.27% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5376-5379 99 0.23% 95.49% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.55% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5504-5507 11 0.03% 95.57% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.57% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.60% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.63% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.68% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.89% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5952-5955 14 0.03% 95.92% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.07% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6080-6083 83 0.19% 96.26% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6144-6147 39 0.09% 96.35% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6208-6211 81 0.19% 96.54% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6272-6275 67 0.16% 96.69% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6336-6339 13 0.03% 96.72% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.94% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6464-6467 21 0.05% 96.99% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.01% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6592-6595 1 0.00% 97.01% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.04% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6720-6723 3 0.01% 97.05% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.07% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6848-6851 24 0.06% 97.12% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.33% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6976-6979 13 0.03% 97.36% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.51% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7104-7107 81 0.19% 97.70% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7168-7171 309 0.72% 98.42% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.42% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.42% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7424-7427 16 0.04% 98.46% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.46% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7680-7683 4 0.01% 98.47% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.47% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7808-7811 3 0.01% 98.48% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7936-7939 18 0.04% 98.52% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8000-8003 3 0.01% 98.53% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8192-8195 331 0.77% 99.30% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.30% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8448-8451 5 0.01% 99.31% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.32% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.32% # Bytes accessed per row activation | 134system.physmem.wrQLenPdf::0 4574 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 4622 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 4638 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 5300 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 6023 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 5386 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 5393 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 5463 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 5529 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 4863 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 4881 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 4845 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 5670 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 5759 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 5781 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 5838 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 5862 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 5005 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 5034 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 4942 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 5452 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 5842 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 354 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see 166system.physmem.bytesPerActivate::samples 43301 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::mean 831.507817 # Bytes accessed per row activation 168system.physmem.bytesPerActivate::gmean 237.255649 # Bytes accessed per row activation 169system.physmem.bytesPerActivate::stdev 1940.687281 # Bytes accessed per row activation 170system.physmem.bytesPerActivate::64-67 14819 34.22% 34.22% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::128-131 6274 14.49% 48.71% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::192-195 4433 10.24% 58.95% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::256-259 2614 6.04% 64.99% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::320-323 1636 3.78% 68.77% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::384-387 1435 3.31% 72.08% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::448-451 928 2.14% 74.22% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::512-515 854 1.97% 76.19% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::576-579 632 1.46% 77.65% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::640-643 524 1.21% 78.86% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::704-707 594 1.37% 80.24% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::768-771 623 1.44% 81.67% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::832-835 284 0.66% 82.33% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::896-899 262 0.61% 82.94% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::960-963 268 0.62% 83.55% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1024-1027 398 0.92% 84.47% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1088-1091 204 0.47% 84.94% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1152-1155 163 0.38% 85.32% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1216-1219 93 0.21% 85.54% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1280-1283 193 0.45% 85.98% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1344-1347 100 0.23% 86.21% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1408-1411 353 0.82% 87.03% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1472-1475 186 0.43% 87.46% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1536-1539 655 1.51% 88.97% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1600-1603 89 0.21% 89.18% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.24% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1728-1731 40 0.09% 89.33% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1792-1795 175 0.40% 89.74% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.83% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1920-1923 79 0.18% 90.01% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.21% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2048-2051 82 0.19% 90.40% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2112-2115 104 0.24% 90.64% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.81% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2240-2243 16 0.04% 90.85% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2304-2307 102 0.24% 91.08% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2368-2371 26 0.06% 91.14% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2432-2435 14 0.03% 91.18% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2496-2499 2 0.00% 91.18% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2560-2563 17 0.04% 91.22% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2624-2627 4 0.01% 91.23% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.26% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2752-2755 25 0.06% 91.32% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2816-2819 100 0.23% 91.55% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2880-2883 15 0.03% 91.58% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2944-2947 67 0.15% 91.74% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.93% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3072-3075 42 0.10% 92.02% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3136-3139 83 0.19% 92.21% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3200-3203 68 0.16% 92.37% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3264-3267 12 0.03% 92.40% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3328-3331 94 0.22% 92.62% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.67% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3456-3459 9 0.02% 92.69% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3520-3523 5 0.01% 92.70% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.73% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3648-3651 4 0.01% 92.74% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.76% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3776-3779 22 0.05% 92.81% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3840-3843 92 0.21% 93.03% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3904-3907 13 0.03% 93.06% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.21% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.40% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4096-4099 40 0.09% 93.49% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4160-4163 80 0.18% 93.67% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.83% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.86% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4352-4355 95 0.22% 94.08% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4416-4419 21 0.05% 94.12% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4480-4483 10 0.02% 94.15% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4544-4547 1 0.00% 94.15% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.18% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.18% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4736-4739 13 0.03% 94.21% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.26% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.48% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4928-4931 14 0.03% 94.51% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4992-4995 68 0.16% 94.67% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.85% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.93% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.12% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5248-5251 65 0.15% 95.27% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.29% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5376-5379 98 0.23% 95.52% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.57% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5504-5507 10 0.02% 95.59% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.60% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.62% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.65% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.70% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.91% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5952-5955 13 0.03% 95.94% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.09% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6080-6083 81 0.19% 96.27% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6144-6147 41 0.09% 96.37% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6208-6211 82 0.19% 96.56% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6272-6275 69 0.16% 96.72% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6336-6339 14 0.03% 96.75% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.97% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6464-6467 21 0.05% 97.02% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.03% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.06% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6720-6723 2 0.00% 97.07% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.09% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6848-6851 22 0.05% 97.14% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.35% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6976-6979 14 0.03% 97.38% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.53% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7104-7107 80 0.18% 97.72% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7168-7171 307 0.71% 98.42% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.43% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.43% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7424-7427 17 0.04% 98.47% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7488-7491 2 0.00% 98.47% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.48% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7680-7683 5 0.01% 98.49% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.49% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7872-7875 1 0.00% 98.49% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7936-7939 16 0.04% 98.53% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.53% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.54% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8192-8195 330 0.76% 99.30% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.30% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.30% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.31% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.31% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.32% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.32% # Bytes accessed per row activation |
| 295system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation | 298system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation |
| 296system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.33% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.34% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.34% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.34% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.34% # Bytes accessed per row activation | 299system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.33% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9408-9411 2 0.00% 99.34% # Bytes accessed per row activation |
| 301system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation | 301system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation |
| 302system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.35% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.35% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.36% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.36% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.37% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::11008-11011 3 0.01% 99.37% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.38% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.38% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.38% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.39% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.39% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::11840-11843 3 0.01% 99.40% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.40% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.41% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.41% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.41% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.42% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.42% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.43% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.43% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::13120-13123 2 0.00% 99.44% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.44% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.44% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.44% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.45% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.45% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.46% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.46% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.47% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.47% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.47% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.48% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::14656-14659 3 0.01% 99.48% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.49% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.49% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.49% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::15360-15363 37 0.09% 99.58% # Bytes accessed per row activation | 302system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.34% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.34% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.35% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.35% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.35% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.35% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.36% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.36% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.36% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.36% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.36% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.37% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::11648-11651 2 0.00% 99.37% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.37% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.38% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.39% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.39% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.39% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.39% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.40% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.40% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.41% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.41% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.42% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::13312-13315 4 0.01% 99.43% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.43% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.43% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.43% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::13696-13699 7 0.02% 99.45% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.45% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.46% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.47% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.47% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.48% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.48% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.48% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::15360-15363 40 0.09% 99.57% # Bytes accessed per row activation |
| 339system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation | 339system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation |
| 340system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.59% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.59% # Bytes accessed per row activation | 340system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.58% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::15808-15811 2 0.00% 99.59% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.59% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.59% # Bytes accessed per row activation |
| 342system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation | 344system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation |
| 343system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.59% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::16384-16387 176 0.41% 100.00% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::total 43193 # Bytes accessed per row activation 346system.physmem.totQLat 8380902250 # Total ticks spent queuing 347system.physmem.totMemAccLat 15783312250 # Total ticks spent from burst creation until serviced by the DRAM 348system.physmem.totBusLat 2226085000 # Total ticks spent in databus transfers 349system.physmem.totBankLat 5176325000 # Total ticks spent accessing banks 350system.physmem.avgQLat 18824.31 # Average queueing delay per DRAM burst 351system.physmem.avgBankLat 11626.52 # Average bank access latency per DRAM burst | 345system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.60% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.60% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::16384-16387 174 0.40% 100.00% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::total 43301 # Bytes accessed per row activation 349system.physmem.totQLat 8362787000 # Total ticks spent queuing 350system.physmem.totMemAccLat 15768695750 # Total ticks spent from burst creation until serviced by the DRAM 351system.physmem.totBusLat 2225940000 # Total ticks spent in databus transfers 352system.physmem.totBankLat 5179968750 # Total ticks spent accessing banks 353system.physmem.avgQLat 18784.84 # Average queueing delay per DRAM burst 354system.physmem.avgBankLat 11635.46 # Average bank access latency per DRAM burst |
| 352system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 355system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 353system.physmem.avgMemAccLat 35450.83 # Average memory access latency per DRAM burst | 356system.physmem.avgMemAccLat 35420.31 # Average memory access latency per DRAM burst |
| 354system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s 355system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 356system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s 357system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s 358system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 359system.physmem.busUtil 0.15 # Data bus utilization in percentage 360system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 361system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 362system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing | 357system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s 358system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 359system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s 360system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s 361system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 362system.physmem.busUtil 0.15 # Data bus utilization in percentage 363system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 364system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 365system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing |
| 363system.physmem.avgWrQLen 9.37 # Average write queue length when enqueuing 364system.physmem.readRowHits 424661 # Number of row buffer hits during reads 365system.physmem.writeRowHits 94799 # Number of row buffer hits during writes 366system.physmem.readRowHitRate 95.38 # Row buffer hit rate for reads 367system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes 368system.physmem.avgGap 3305785.86 # Average gap between requests 369system.physmem.pageHitRate 92.32 # Row buffer hit rate, read and write combined 370system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state 371system.membus.throughput 19402801 # Throughput (bytes/s) 372system.membus.trans_dist::ReadReq 295960 # Transaction distribution 373system.membus.trans_dist::ReadResp 295877 # Transaction distribution | 366system.physmem.avgWrQLen 11.24 # Average write queue length when enqueuing 367system.physmem.readRowHits 424550 # Number of row buffer hits during reads 368system.physmem.writeRowHits 94755 # Number of row buffer hits during writes 369system.physmem.readRowHitRate 95.36 # Row buffer hit rate for reads 370system.physmem.writeRowHitRate 80.69 # Row buffer hit rate for writes 371system.physmem.avgGap 3306027.09 # Average gap between requests 372system.physmem.pageHitRate 92.30 # Row buffer hit rate, read and write combined 373system.physmem.prechargeAllPercent 0.39 # Percentage of time for which DRAM has all the banks in precharge state 374system.membus.throughput 19401389 # Throughput (bytes/s) 375system.membus.trans_dist::ReadReq 295980 # Transaction distribution 376system.membus.trans_dist::ReadResp 295901 # Transaction distribution |
| 374system.membus.trans_dist::WriteReq 9598 # Transaction distribution 375system.membus.trans_dist::WriteResp 9598 # Transaction distribution | 377system.membus.trans_dist::WriteReq 9598 # Transaction distribution 378system.membus.trans_dist::WriteResp 9598 # Transaction distribution |
| 376system.membus.trans_dist::Writeback 117448 # Transaction distribution 377system.membus.trans_dist::UpgradeReq 180 # Transaction distribution 378system.membus.trans_dist::UpgradeResp 180 # Transaction distribution 379system.membus.trans_dist::ReadExReq 156869 # Transaction distribution 380system.membus.trans_dist::ReadExResp 156869 # Transaction distribution 381system.membus.trans_dist::BadAddressError 83 # Transaction distribution | 379system.membus.trans_dist::Writeback 117429 # Transaction distribution 380system.membus.trans_dist::UpgradeReq 181 # Transaction distribution 381system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 382system.membus.trans_dist::UpgradeResp 182 # Transaction distribution 383system.membus.trans_dist::ReadExReq 156823 # Transaction distribution 384system.membus.trans_dist::ReadExResp 156823 # Transaction distribution 385system.membus.trans_dist::BadAddressError 79 # Transaction distribution |
| 382system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) | 386system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) |
| 383system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884202 # Packet count per connected master and slave (bytes) 384system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) 385system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917424 # Packet count per connected master and slave (bytes) | 387system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884143 # Packet count per connected master and slave (bytes) 388system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes) 389system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917357 # Packet count per connected master and slave (bytes) |
| 386system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) 387system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) | 390system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) 391system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) |
| 388system.membus.pkt_count::total 1042103 # Packet count per connected master and slave (bytes) | 392system.membus.pkt_count::total 1042036 # Packet count per connected master and slave (bytes) |
| 389system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) | 393system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) |
| 390system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704256 # Cumulative packet size per connected master and slave (bytes) 391system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748404 # Cumulative packet size per connected master and slave (bytes) | 394system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701632 # Cumulative packet size per connected master and slave (bytes) 395system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745780 # Cumulative packet size per connected master and slave (bytes) |
| 392system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) 393system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) | 396system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) 397system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) |
| 394system.membus.tot_pkt_size::total 36057460 # Cumulative packet size per connected master and slave (bytes) 395system.membus.data_through_bus 36057460 # Total data (bytes) | 398system.membus.tot_pkt_size::total 36054836 # Cumulative packet size per connected master and slave (bytes) 399system.membus.data_through_bus 36054836 # Total data (bytes) |
| 396system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) | 400system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) |
| 397system.membus.reqLayer0.occupancy 29954500 # Layer occupancy (ticks) | 401system.membus.reqLayer0.occupancy 29837500 # Layer occupancy (ticks) |
| 398system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 402system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 399system.membus.reqLayer1.occupancy 1551414500 # Layer occupancy (ticks) | 403system.membus.reqLayer1.occupancy 1551324500 # Layer occupancy (ticks) |
| 400system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 404system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 401system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) | 405system.membus.reqLayer2.occupancy 96500 # Layer occupancy (ticks) |
| 402system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 406system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 403system.membus.respLayer1.occupancy 3763341794 # Layer occupancy (ticks) | 407system.membus.respLayer1.occupancy 3763216294 # Layer occupancy (ticks) |
| 404system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 408system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 405system.membus.respLayer2.occupancy 376305243 # Layer occupancy (ticks) | 409system.membus.respLayer2.occupancy 376313495 # Layer occupancy (ticks) |
| 406system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 407system.iocache.tags.replacements 41685 # number of replacements | 410system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 411system.iocache.tags.replacements 41685 # number of replacements |
| 408system.iocache.tags.tagsinuse 1.261102 # Cycle average of tags in use | 412system.iocache.tags.tagsinuse 1.261116 # Cycle average of tags in use |
| 409system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 410system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 411system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 413system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 414system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 415system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 412system.iocache.tags.warmup_cycle 1710341438000 # Cycle when the warmup percentage was hit. 413system.iocache.tags.occ_blocks::tsunami.ide 1.261102 # Average occupied blocks per requestor 414system.iocache.tags.occ_percent::tsunami.ide 0.078819 # Average percentage of cache occupancy 415system.iocache.tags.occ_percent::total 0.078819 # Average percentage of cache occupancy | 416system.iocache.tags.warmup_cycle 1710341603000 # Cycle when the warmup percentage was hit. 417system.iocache.tags.occ_blocks::tsunami.ide 1.261116 # Average occupied blocks per requestor 418system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy 419system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy |
| 416system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 417system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 418system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 419system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 420system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 421system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 422system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 423system.iocache.overall_misses::total 41725 # number of overall misses 424system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles 425system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles | 420system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 421system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 422system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 423system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 424system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 425system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 426system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 427system.iocache.overall_misses::total 41725 # number of overall misses 428system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles 429system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles |
| 426system.iocache.WriteReq_miss_latency::tsunami.ide 12983817806 # number of WriteReq miss cycles 427system.iocache.WriteReq_miss_latency::total 12983817806 # number of WriteReq miss cycles 428system.iocache.demand_miss_latency::tsunami.ide 13004951689 # number of demand (read+write) miss cycles 429system.iocache.demand_miss_latency::total 13004951689 # number of demand (read+write) miss cycles 430system.iocache.overall_miss_latency::tsunami.ide 13004951689 # number of overall miss cycles 431system.iocache.overall_miss_latency::total 13004951689 # number of overall miss cycles | 430system.iocache.WriteReq_miss_latency::tsunami.ide 12974928560 # number of WriteReq miss cycles 431system.iocache.WriteReq_miss_latency::total 12974928560 # number of WriteReq miss cycles 432system.iocache.demand_miss_latency::tsunami.ide 12996062443 # number of demand (read+write) miss cycles 433system.iocache.demand_miss_latency::total 12996062443 # number of demand (read+write) miss cycles 434system.iocache.overall_miss_latency::tsunami.ide 12996062443 # number of overall miss cycles 435system.iocache.overall_miss_latency::total 12996062443 # number of overall miss cycles |
| 432system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 433system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 434system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 435system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 436system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 437system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 438system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 439system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 440system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 441system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 442system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 443system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 444system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 445system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 446system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 447system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 448system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency 449system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency | 436system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 437system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 438system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 439system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 440system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 441system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 442system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 443system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 444system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 445system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 446system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 447system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 448system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 449system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 450system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 451system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 452system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency 453system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency |
| 450system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312471.549047 # average WriteReq miss latency 451system.iocache.WriteReq_avg_miss_latency::total 312471.549047 # average WriteReq miss latency 452system.iocache.demand_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency 453system.iocache.demand_avg_miss_latency::total 311682.485057 # average overall miss latency 454system.iocache.overall_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency 455system.iocache.overall_avg_miss_latency::total 311682.485057 # average overall miss latency 456system.iocache.blocked_cycles::no_mshrs 402476 # number of cycles access was blocked | 454system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312257.618406 # average WriteReq miss latency 455system.iocache.WriteReq_avg_miss_latency::total 312257.618406 # average WriteReq miss latency 456system.iocache.demand_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency 457system.iocache.demand_avg_miss_latency::total 311469.441414 # average overall miss latency 458system.iocache.overall_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency 459system.iocache.overall_avg_miss_latency::total 311469.441414 # average overall miss latency 460system.iocache.blocked_cycles::no_mshrs 401483 # number of cycles access was blocked |
| 457system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 461system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 458system.iocache.blocked::no_mshrs 29170 # number of cycles access was blocked | 462system.iocache.blocked::no_mshrs 29284 # number of cycles access was blocked |
| 459system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 463system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 460system.iocache.avg_blocked_cycles::no_mshrs 13.797600 # average number of cycles each access was blocked | 464system.iocache.avg_blocked_cycles::no_mshrs 13.709978 # average number of cycles each access was blocked |
| 461system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 462system.iocache.fast_writes 0 # number of fast writes performed 463system.iocache.cache_copies 0 # number of cache copies performed 464system.iocache.writebacks::writebacks 41512 # number of writebacks 465system.iocache.writebacks::total 41512 # number of writebacks 466system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 467system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 468system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 469system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 470system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 471system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 472system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 473system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 474system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles 475system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles | 465system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 466system.iocache.fast_writes 0 # number of fast writes performed 467system.iocache.cache_copies 0 # number of cache copies performed 468system.iocache.writebacks::writebacks 41512 # number of writebacks 469system.iocache.writebacks::total 41512 # number of writebacks 470system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 471system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 472system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 473system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 474system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 475system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 476system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 477system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 478system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles 479system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles |
| 476system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10821554320 # number of WriteReq MSHR miss cycles 477system.iocache.WriteReq_mshr_miss_latency::total 10821554320 # number of WriteReq MSHR miss cycles 478system.iocache.demand_mshr_miss_latency::tsunami.ide 10833691203 # number of demand (read+write) MSHR miss cycles 479system.iocache.demand_mshr_miss_latency::total 10833691203 # number of demand (read+write) MSHR miss cycles 480system.iocache.overall_mshr_miss_latency::tsunami.ide 10833691203 # number of overall MSHR miss cycles 481system.iocache.overall_mshr_miss_latency::total 10833691203 # number of overall MSHR miss cycles | 480system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10812648570 # number of WriteReq MSHR miss cycles 481system.iocache.WriteReq_mshr_miss_latency::total 10812648570 # number of WriteReq MSHR miss cycles 482system.iocache.demand_mshr_miss_latency::tsunami.ide 10824785453 # number of demand (read+write) MSHR miss cycles 483system.iocache.demand_mshr_miss_latency::total 10824785453 # number of demand (read+write) MSHR miss cycles 484system.iocache.overall_mshr_miss_latency::tsunami.ide 10824785453 # number of overall MSHR miss cycles 485system.iocache.overall_mshr_miss_latency::total 10824785453 # number of overall MSHR miss cycles |
| 482system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 483system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 484system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 485system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 486system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 487system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 488system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 489system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 490system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency 491system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency | 486system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 487system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 488system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 489system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 490system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 491system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 492system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 493system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 494system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency 495system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency |
| 492system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260434.018098 # average WriteReq mshr miss latency 493system.iocache.WriteReq_avg_mshr_miss_latency::total 260434.018098 # average WriteReq mshr miss latency 494system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency 495system.iocache.demand_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency 496system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency 497system.iocache.overall_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency | 496system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260219.690268 # average WriteReq mshr miss latency 497system.iocache.WriteReq_avg_mshr_miss_latency::total 260219.690268 # average WriteReq mshr miss latency 498system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency 499system.iocache.demand_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency 500system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency 501system.iocache.overall_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency |
| 498system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 499system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 500system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 501system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 502system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 503system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 504system.disk0.dma_write_txs 395 # Number of DMA write transactions. 505system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 506system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 507system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 508system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 509system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 510system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 502system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 503system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 504system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 505system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 506system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 507system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 508system.disk0.dma_write_txs 395 # Number of DMA write transactions. 509system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 510system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 511system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 512system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 513system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 514system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 511system.cpu.branchPred.lookups 13864479 # Number of BP lookups 512system.cpu.branchPred.condPredicted 11634507 # Number of conditional branches predicted 513system.cpu.branchPred.condIncorrect 398117 # Number of conditional branches incorrect 514system.cpu.branchPred.BTBLookups 9551974 # Number of BTB lookups 515system.cpu.branchPred.BTBHits 5822395 # Number of BTB hits | 515system.cpu.branchPred.lookups 13863448 # Number of BP lookups 516system.cpu.branchPred.condPredicted 11631259 # Number of conditional branches predicted 517system.cpu.branchPred.condIncorrect 399718 # Number of conditional branches incorrect 518system.cpu.branchPred.BTBLookups 9400932 # Number of BTB lookups 519system.cpu.branchPred.BTBHits 5821857 # Number of BTB hits |
| 516system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 520system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 517system.cpu.branchPred.BTBHitPct 60.954887 # BTB Hit Percentage 518system.cpu.branchPred.usedRAS 906213 # Number of times the RAS was used to get a target. 519system.cpu.branchPred.RASInCorrect 38605 # Number of incorrect RAS predictions. | 521system.cpu.branchPred.BTBHitPct 61.928509 # BTB Hit Percentage 522system.cpu.branchPred.usedRAS 906521 # Number of times the RAS was used to get a target. 523system.cpu.branchPred.RASInCorrect 39211 # Number of incorrect RAS predictions. |
| 520system.cpu.dtb.fetch_hits 0 # ITB hits 521system.cpu.dtb.fetch_misses 0 # ITB misses 522system.cpu.dtb.fetch_acv 0 # ITB acv 523system.cpu.dtb.fetch_accesses 0 # ITB accesses | 524system.cpu.dtb.fetch_hits 0 # ITB hits 525system.cpu.dtb.fetch_misses 0 # ITB misses 526system.cpu.dtb.fetch_acv 0 # ITB acv 527system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 524system.cpu.dtb.read_hits 9930859 # DTB read hits 525system.cpu.dtb.read_misses 42001 # DTB read misses 526system.cpu.dtb.read_acv 541 # DTB read access violations 527system.cpu.dtb.read_accesses 942214 # DTB read accesses 528system.cpu.dtb.write_hits 6592411 # DTB write hits 529system.cpu.dtb.write_misses 10345 # DTB write misses | 528system.cpu.dtb.read_hits 9926517 # DTB read hits 529system.cpu.dtb.read_misses 41406 # DTB read misses 530system.cpu.dtb.read_acv 531 # DTB read access violations 531system.cpu.dtb.read_accesses 940700 # DTB read accesses 532system.cpu.dtb.write_hits 6593963 # DTB write hits 533system.cpu.dtb.write_misses 10630 # DTB write misses |
| 530system.cpu.dtb.write_acv 410 # DTB write access violations | 534system.cpu.dtb.write_acv 410 # DTB write access violations |
| 531system.cpu.dtb.write_accesses 337923 # DTB write accesses 532system.cpu.dtb.data_hits 16523270 # DTB hits 533system.cpu.dtb.data_misses 52346 # DTB misses 534system.cpu.dtb.data_acv 951 # DTB access violations 535system.cpu.dtb.data_accesses 1280137 # DTB accesses 536system.cpu.itb.fetch_hits 1308071 # ITB hits 537system.cpu.itb.fetch_misses 36703 # ITB misses 538system.cpu.itb.fetch_acv 1058 # ITB acv 539system.cpu.itb.fetch_accesses 1344774 # ITB accesses | 535system.cpu.dtb.write_accesses 338096 # DTB write accesses 536system.cpu.dtb.data_hits 16520480 # DTB hits 537system.cpu.dtb.data_misses 52036 # DTB misses 538system.cpu.dtb.data_acv 941 # DTB access violations 539system.cpu.dtb.data_accesses 1278796 # DTB accesses 540system.cpu.itb.fetch_hits 1306353 # ITB hits 541system.cpu.itb.fetch_misses 36823 # ITB misses 542system.cpu.itb.fetch_acv 1069 # ITB acv 543system.cpu.itb.fetch_accesses 1343176 # ITB accesses |
| 540system.cpu.itb.read_hits 0 # DTB read hits 541system.cpu.itb.read_misses 0 # DTB read misses 542system.cpu.itb.read_acv 0 # DTB read access violations 543system.cpu.itb.read_accesses 0 # DTB read accesses 544system.cpu.itb.write_hits 0 # DTB write hits 545system.cpu.itb.write_misses 0 # DTB write misses 546system.cpu.itb.write_acv 0 # DTB write access violations 547system.cpu.itb.write_accesses 0 # DTB write accesses 548system.cpu.itb.data_hits 0 # DTB hits 549system.cpu.itb.data_misses 0 # DTB misses 550system.cpu.itb.data_acv 0 # DTB access violations 551system.cpu.itb.data_accesses 0 # DTB accesses | 544system.cpu.itb.read_hits 0 # DTB read hits 545system.cpu.itb.read_misses 0 # DTB read misses 546system.cpu.itb.read_acv 0 # DTB read access violations 547system.cpu.itb.read_accesses 0 # DTB read accesses 548system.cpu.itb.write_hits 0 # DTB write hits 549system.cpu.itb.write_misses 0 # DTB write misses 550system.cpu.itb.write_acv 0 # DTB write access violations 551system.cpu.itb.write_accesses 0 # DTB write accesses 552system.cpu.itb.data_hits 0 # DTB hits 553system.cpu.itb.data_misses 0 # DTB misses 554system.cpu.itb.data_acv 0 # DTB access violations 555system.cpu.itb.data_accesses 0 # DTB accesses |
| 552system.cpu.numCycles 121927488 # number of cpu cycles simulated | 556system.cpu.numCycles 121966998 # number of cpu cycles simulated |
| 553system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 554system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 557system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 558system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 555system.cpu.fetch.icacheStallCycles 28039089 # Number of cycles fetch is stalled on an Icache miss 556system.cpu.fetch.Insts 70847333 # Number of instructions fetch has processed 557system.cpu.fetch.Branches 13864479 # Number of branches that fetch encountered 558system.cpu.fetch.predictedBranches 6728608 # Number of branches that fetch has predicted taken 559system.cpu.fetch.Cycles 13268188 # Number of cycles fetch has run and was not squashing or blocked 560system.cpu.fetch.SquashCycles 1998523 # Number of cycles fetch has spent squashing 561system.cpu.fetch.BlockedCycles 38187764 # Number of cycles fetch has spent blocked 562system.cpu.fetch.MiscStallCycles 33374 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 563system.cpu.fetch.PendingTrapStallCycles 253703 # Number of stall cycles due to pending traps 564system.cpu.fetch.PendingQuiesceStallCycles 358378 # Number of stall cycles due to pending quiesce instructions 565system.cpu.fetch.IcacheWaitRetryStallCycles 313 # Number of stall cycles due to full MSHR 566system.cpu.fetch.CacheLines 8556240 # Number of cache lines fetched 567system.cpu.fetch.IcacheSquashes 264321 # Number of outstanding Icache misses that were squashed 568system.cpu.fetch.rateDist::samples 81433386 # Number of instructions fetched each cycle (Total) 569system.cpu.fetch.rateDist::mean 0.870004 # Number of instructions fetched each cycle (Total) 570system.cpu.fetch.rateDist::stdev 2.213508 # Number of instructions fetched each cycle (Total) | 559system.cpu.fetch.icacheStallCycles 28067964 # Number of cycles fetch is stalled on an Icache miss 560system.cpu.fetch.Insts 70813073 # Number of instructions fetch has processed 561system.cpu.fetch.Branches 13863448 # Number of branches that fetch encountered 562system.cpu.fetch.predictedBranches 6728378 # Number of branches that fetch has predicted taken 563system.cpu.fetch.Cycles 13263425 # Number of cycles fetch has run and was not squashing or blocked 564system.cpu.fetch.SquashCycles 1999195 # Number of cycles fetch has spent squashing 565system.cpu.fetch.BlockedCycles 38181411 # Number of cycles fetch has spent blocked 566system.cpu.fetch.MiscStallCycles 33091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 567system.cpu.fetch.PendingTrapStallCycles 255000 # Number of stall cycles due to pending traps 568system.cpu.fetch.PendingQuiesceStallCycles 364206 # Number of stall cycles due to pending quiesce instructions 569system.cpu.fetch.IcacheWaitRetryStallCycles 297 # Number of stall cycles due to full MSHR 570system.cpu.fetch.CacheLines 8556045 # Number of cache lines fetched 571system.cpu.fetch.IcacheSquashes 264477 # Number of outstanding Icache misses that were squashed 572system.cpu.fetch.rateDist::samples 81457086 # Number of instructions fetched each cycle (Total) 573system.cpu.fetch.rateDist::mean 0.869330 # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.rateDist::stdev 2.212823 # Number of instructions fetched each cycle (Total) |
| 571system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 575system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 572system.cpu.fetch.rateDist::0 68165198 83.71% 83.71% # Number of instructions fetched each cycle (Total) 573system.cpu.fetch.rateDist::1 850053 1.04% 84.75% # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.rateDist::2 1699284 2.09% 86.84% # Number of instructions fetched each cycle (Total) 575system.cpu.fetch.rateDist::3 821371 1.01% 87.85% # Number of instructions fetched each cycle (Total) 576system.cpu.fetch.rateDist::4 2763942 3.39% 91.24% # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::5 562061 0.69% 91.93% # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::6 645266 0.79% 92.72% # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.rateDist::7 1012758 1.24% 93.97% # Number of instructions fetched each cycle (Total) 580system.cpu.fetch.rateDist::8 4913453 6.03% 100.00% # Number of instructions fetched each cycle (Total) | 576system.cpu.fetch.rateDist::0 68193661 83.72% 83.72% # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::1 852857 1.05% 84.76% # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::2 1696439 2.08% 86.85% # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.rateDist::3 825181 1.01% 87.86% # Number of instructions fetched each cycle (Total) 580system.cpu.fetch.rateDist::4 2758325 3.39% 91.25% # Number of instructions fetched each cycle (Total) 581system.cpu.fetch.rateDist::5 561473 0.69% 91.94% # Number of instructions fetched each cycle (Total) 582system.cpu.fetch.rateDist::6 645881 0.79% 92.73% # Number of instructions fetched each cycle (Total) 583system.cpu.fetch.rateDist::7 1010308 1.24% 93.97% # Number of instructions fetched each cycle (Total) 584system.cpu.fetch.rateDist::8 4912961 6.03% 100.00% # Number of instructions fetched each cycle (Total) |
| 581system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 582system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 583system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 585system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 586system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 587system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 584system.cpu.fetch.rateDist::total 81433386 # Number of instructions fetched each cycle (Total) 585system.cpu.fetch.branchRate 0.113711 # Number of branch fetches per cycle 586system.cpu.fetch.rate 0.581061 # Number of inst fetches per cycle 587system.cpu.decode.IdleCycles 29221081 # Number of cycles decode is idle 588system.cpu.decode.BlockedCycles 37872240 # Number of cycles decode is blocked 589system.cpu.decode.RunCycles 12130703 # Number of cycles decode is running 590system.cpu.decode.UnblockCycles 959021 # Number of cycles decode is unblocking 591system.cpu.decode.SquashCycles 1250340 # Number of cycles decode is squashing 592system.cpu.decode.BranchResolved 583021 # Number of times decode resolved a branch 593system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction 594system.cpu.decode.DecodedInsts 69509272 # Number of instructions handled by decode 595system.cpu.decode.SquashedInsts 129850 # Number of squashed instructions handled by decode 596system.cpu.rename.SquashCycles 1250340 # Number of cycles rename is squashing 597system.cpu.rename.IdleCycles 30372674 # Number of cycles rename is idle 598system.cpu.rename.BlockCycles 14147971 # Number of cycles rename is blocking 599system.cpu.rename.serializeStallCycles 20014852 # count of cycles rename stalled for serializing inst 600system.cpu.rename.RunCycles 11335195 # Number of cycles rename is running 601system.cpu.rename.UnblockCycles 4312352 # Number of cycles rename is unblocking 602system.cpu.rename.RenamedInsts 65701425 # Number of instructions processed by rename 603system.cpu.rename.ROBFullEvents 7084 # Number of times rename has blocked due to ROB full 604system.cpu.rename.IQFullEvents 503729 # Number of times rename has blocked due to IQ full 605system.cpu.rename.LSQFullEvents 1544223 # Number of times rename has blocked due to LSQ full 606system.cpu.rename.RenamedOperands 43873094 # Number of destination operands rename has renamed 607system.cpu.rename.RenameLookups 79768312 # Number of register rename lookups that rename has made 608system.cpu.rename.int_rename_lookups 79589398 # Number of integer rename lookups 609system.cpu.rename.fp_rename_lookups 166462 # Number of floating rename lookups 610system.cpu.rename.CommittedMaps 38180112 # Number of HB maps that are committed 611system.cpu.rename.UndoneMaps 5692974 # Number of HB maps that are undone due to squashing 612system.cpu.rename.serializingInsts 1682864 # count of serializing insts renamed 613system.cpu.rename.tempSerializingInsts 240315 # count of temporary serializing insts renamed 614system.cpu.rename.skidInsts 12255388 # count of insts added to the skid buffer 615system.cpu.memDep0.insertedLoads 10448429 # Number of loads inserted to the mem dependence unit. 616system.cpu.memDep0.insertedStores 6906827 # Number of stores inserted to the mem dependence unit. 617system.cpu.memDep0.conflictingLoads 1318660 # Number of conflicting loads. 618system.cpu.memDep0.conflictingStores 851527 # Number of conflicting stores. 619system.cpu.iq.iqInstsAdded 58223534 # Number of instructions added to the IQ (excludes non-spec) 620system.cpu.iq.iqNonSpecInstsAdded 2050984 # Number of non-speculative instructions added to the IQ 621system.cpu.iq.iqInstsIssued 56812947 # Number of instructions issued 622system.cpu.iq.iqSquashedInstsIssued 113805 # Number of squashed instructions issued 623system.cpu.iq.iqSquashedInstsExamined 6931173 # Number of squashed instructions iterated over during squash; mainly for profiling 624system.cpu.iq.iqSquashedOperandsExamined 3605221 # Number of squashed operands that are examined and possibly removed from graph 625system.cpu.iq.iqSquashedNonSpecRemoved 1390018 # Number of squashed non-spec instructions that were removed 626system.cpu.iq.issued_per_cycle::samples 81433386 # Number of insts issued each cycle 627system.cpu.iq.issued_per_cycle::mean 0.697662 # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::stdev 1.359692 # Number of insts issued each cycle | 588system.cpu.fetch.rateDist::total 81457086 # Number of instructions fetched each cycle (Total) 589system.cpu.fetch.branchRate 0.113666 # Number of branch fetches per cycle 590system.cpu.fetch.rate 0.580592 # Number of inst fetches per cycle 591system.cpu.decode.IdleCycles 29256938 # Number of cycles decode is idle 592system.cpu.decode.BlockedCycles 37863691 # Number of cycles decode is blocked 593system.cpu.decode.RunCycles 12127839 # Number of cycles decode is running 594system.cpu.decode.UnblockCycles 959156 # Number of cycles decode is unblocking 595system.cpu.decode.SquashCycles 1249461 # Number of cycles decode is squashing 596system.cpu.decode.BranchResolved 584263 # Number of times decode resolved a branch 597system.cpu.decode.BranchMispred 42640 # Number of times decode detected a branch misprediction 598system.cpu.decode.DecodedInsts 69481989 # Number of instructions handled by decode 599system.cpu.decode.SquashedInsts 129319 # Number of squashed instructions handled by decode 600system.cpu.rename.SquashCycles 1249461 # Number of cycles rename is squashing 601system.cpu.rename.IdleCycles 30407522 # Number of cycles rename is idle 602system.cpu.rename.BlockCycles 14148846 # Number of cycles rename is blocking 603system.cpu.rename.serializeStallCycles 20005990 # count of cycles rename stalled for serializing inst 604system.cpu.rename.RunCycles 11332374 # Number of cycles rename is running 605system.cpu.rename.UnblockCycles 4312891 # Number of cycles rename is unblocking 606system.cpu.rename.RenamedInsts 65679549 # Number of instructions processed by rename 607system.cpu.rename.ROBFullEvents 7211 # Number of times rename has blocked due to ROB full 608system.cpu.rename.IQFullEvents 504797 # Number of times rename has blocked due to IQ full 609system.cpu.rename.LSQFullEvents 1541440 # Number of times rename has blocked due to LSQ full 610system.cpu.rename.RenamedOperands 43855166 # Number of destination operands rename has renamed 611system.cpu.rename.RenameLookups 79746051 # Number of register rename lookups that rename has made 612system.cpu.rename.int_rename_lookups 79567055 # Number of integer rename lookups 613system.cpu.rename.fp_rename_lookups 166544 # Number of floating rename lookups 614system.cpu.rename.CommittedMaps 38180329 # Number of HB maps that are committed 615system.cpu.rename.UndoneMaps 5674829 # Number of HB maps that are undone due to squashing 616system.cpu.rename.serializingInsts 1682909 # count of serializing insts renamed 617system.cpu.rename.tempSerializingInsts 240455 # count of temporary serializing insts renamed 618system.cpu.rename.skidInsts 12257327 # count of insts added to the skid buffer 619system.cpu.memDep0.insertedLoads 10441163 # Number of loads inserted to the mem dependence unit. 620system.cpu.memDep0.insertedStores 6908790 # Number of stores inserted to the mem dependence unit. 621system.cpu.memDep0.conflictingLoads 1318239 # Number of conflicting loads. 622system.cpu.memDep0.conflictingStores 851396 # Number of conflicting stores. 623system.cpu.iq.iqInstsAdded 58211664 # Number of instructions added to the IQ (excludes non-spec) 624system.cpu.iq.iqNonSpecInstsAdded 2050007 # Number of non-speculative instructions added to the IQ 625system.cpu.iq.iqInstsIssued 56814932 # Number of instructions issued 626system.cpu.iq.iqSquashedInstsIssued 114609 # Number of squashed instructions issued 627system.cpu.iq.iqSquashedInstsExamined 6922962 # Number of squashed instructions iterated over during squash; mainly for profiling 628system.cpu.iq.iqSquashedOperandsExamined 3587498 # Number of squashed operands that are examined and possibly removed from graph 629system.cpu.iq.iqSquashedNonSpecRemoved 1389025 # Number of squashed non-spec instructions that were removed 630system.cpu.iq.issued_per_cycle::samples 81457086 # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::mean 0.697483 # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::stdev 1.359485 # Number of insts issued each cycle |
| 629system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 633system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 630system.cpu.iq.issued_per_cycle::0 56726750 69.66% 69.66% # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::1 10882649 13.36% 83.02% # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::2 5163201 6.34% 89.36% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::3 3388782 4.16% 93.53% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::4 2628492 3.23% 96.75% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::5 1462722 1.80% 98.55% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::6 751690 0.92% 99.47% # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::7 332968 0.41% 99.88% # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::8 96132 0.12% 100.00% # Number of insts issued each cycle | 634system.cpu.iq.issued_per_cycle::0 56746030 69.66% 69.66% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::1 10887232 13.37% 83.03% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::2 5162469 6.34% 89.37% # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::3 3392471 4.16% 93.53% # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::4 2625915 3.22% 96.76% # Number of insts issued each cycle 639system.cpu.iq.issued_per_cycle::5 1461124 1.79% 98.55% # Number of insts issued each cycle 640system.cpu.iq.issued_per_cycle::6 753330 0.92% 99.47% # Number of insts issued each cycle 641system.cpu.iq.issued_per_cycle::7 332031 0.41% 99.88% # Number of insts issued each cycle 642system.cpu.iq.issued_per_cycle::8 96484 0.12% 100.00% # Number of insts issued each cycle |
| 639system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 640system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 641system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 643system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 644system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 645system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 642system.cpu.iq.issued_per_cycle::total 81433386 # Number of insts issued each cycle | 646system.cpu.iq.issued_per_cycle::total 81457086 # Number of insts issued each cycle |
| 643system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 647system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 644system.cpu.iq.fu_full::IntAlu 91250 11.56% 11.56% # attempts to use FU when none available 645system.cpu.iq.fu_full::IntMult 0 0.00% 11.56% # attempts to use FU when none available 646system.cpu.iq.fu_full::IntDiv 0 0.00% 11.56% # attempts to use FU when none available 647system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.56% # attempts to use FU when none available 648system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.56% # attempts to use FU when none available 649system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.56% # attempts to use FU when none available 650system.cpu.iq.fu_full::FloatMult 0 0.00% 11.56% # attempts to use FU when none available 651system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.56% # attempts to use FU when none available 652system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.56% # attempts to use FU when none available 653system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.56% # attempts to use FU when none available 654system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.56% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.56% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.56% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.56% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.56% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdMult 0 0.00% 11.56% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.56% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdShift 0 0.00% 11.56% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.56% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.56% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.56% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.56% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.56% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.56% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.56% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.56% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.56% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.56% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.56% # attempts to use FU when none available 673system.cpu.iq.fu_full::MemRead 372174 47.14% 58.70% # attempts to use FU when none available 674system.cpu.iq.fu_full::MemWrite 326051 41.30% 100.00% # attempts to use FU when none available | 648system.cpu.iq.fu_full::IntAlu 91940 11.62% 11.62% # attempts to use FU when none available 649system.cpu.iq.fu_full::IntMult 0 0.00% 11.62% # attempts to use FU when none available 650system.cpu.iq.fu_full::IntDiv 0 0.00% 11.62% # attempts to use FU when none available 651system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.62% # attempts to use FU when none available 652system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.62% # attempts to use FU when none available 653system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.62% # attempts to use FU when none available 654system.cpu.iq.fu_full::FloatMult 0 0.00% 11.62% # attempts to use FU when none available 655system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.62% # attempts to use FU when none available 656system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.62% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.62% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.62% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.62% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.62% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.62% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.62% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdMult 0 0.00% 11.62% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.62% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdShift 0 0.00% 11.62% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.62% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.62% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.62% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.62% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.62% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.62% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.62% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.62% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.62% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.62% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.62% # attempts to use FU when none available 677system.cpu.iq.fu_full::MemRead 373423 47.20% 58.82% # attempts to use FU when none available 678system.cpu.iq.fu_full::MemWrite 325849 41.18% 100.00% # attempts to use FU when none available |
| 675system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 676system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 677system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued | 679system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 680system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 681system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued |
| 678system.cpu.iq.FU_type_0::IntAlu 38733166 68.18% 68.19% # Type of FU issued 679system.cpu.iq.FU_type_0::IntMult 61715 0.11% 68.30% # Type of FU issued | 682system.cpu.iq.FU_type_0::IntAlu 38737583 68.18% 68.19% # Type of FU issued 683system.cpu.iq.FU_type_0::IntMult 61738 0.11% 68.30% # Type of FU issued |
| 680system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued | 684system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued |
| 681system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued 682system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued 683system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued 684system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued 685system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued 686system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued 687system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued 688system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued 689system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued 690system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued 691system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued 692system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued 693system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued 701system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued 702system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued 704system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued 705system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued 706system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued 707system.cpu.iq.FU_type_0::MemRead 10362094 18.24% 86.59% # Type of FU issued 708system.cpu.iq.FU_type_0::MemWrite 6670366 11.74% 98.33% # Type of FU issued | 685system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued 686system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued 687system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued 688system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued 689system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued 690system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued 691system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued 692system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued 693system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued 701system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued 702system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued 704system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued 705system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued 706system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued 711system.cpu.iq.FU_type_0::MemRead 10357242 18.23% 86.58% # Type of FU issued 712system.cpu.iq.FU_type_0::MemWrite 6672763 11.74% 98.33% # Type of FU issued |
| 709system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued 710system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 713system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued 714system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 711system.cpu.iq.FU_type_0::total 56812947 # Type of FU issued 712system.cpu.iq.rate 0.465957 # Inst issue rate 713system.cpu.iq.fu_busy_cnt 789475 # FU busy when requested 714system.cpu.iq.fu_busy_rate 0.013896 # FU busy rate (busy events/executed inst) 715system.cpu.iq.int_inst_queue_reads 195270080 # Number of integer instruction queue reads 716system.cpu.iq.int_inst_queue_writes 66882864 # Number of integer instruction queue writes 717system.cpu.iq.int_inst_queue_wakeup_accesses 55570085 # Number of integer instruction queue wakeup accesses 718system.cpu.iq.fp_inst_queue_reads 692479 # Number of floating instruction queue reads 719system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes 720system.cpu.iq.fp_inst_queue_wakeup_accesses 327821 # Number of floating instruction queue wakeup accesses 721system.cpu.iq.int_alu_accesses 57233809 # Number of integer alu accesses 722system.cpu.iq.fp_alu_accesses 361327 # Number of floating point alu accesses 723system.cpu.iew.lsq.thread0.forwLoads 596971 # Number of loads that had data forwarded from stores | 715system.cpu.iq.FU_type_0::total 56814932 # Type of FU issued 716system.cpu.iq.rate 0.465822 # Inst issue rate 717system.cpu.iq.fu_busy_cnt 791212 # FU busy when requested 718system.cpu.iq.fu_busy_rate 0.013926 # FU busy rate (busy events/executed inst) 719system.cpu.iq.int_inst_queue_reads 195300199 # Number of integer instruction queue reads 720system.cpu.iq.int_inst_queue_writes 66861892 # Number of integer instruction queue writes 721system.cpu.iq.int_inst_queue_wakeup_accesses 55573336 # Number of integer instruction queue wakeup accesses 722system.cpu.iq.fp_inst_queue_reads 692571 # Number of floating instruction queue reads 723system.cpu.iq.fp_inst_queue_writes 336551 # Number of floating instruction queue writes 724system.cpu.iq.fp_inst_queue_wakeup_accesses 327871 # Number of floating instruction queue wakeup accesses 725system.cpu.iq.int_alu_accesses 57237458 # Number of integer alu accesses 726system.cpu.iq.fp_alu_accesses 361400 # Number of floating point alu accesses 727system.cpu.iew.lsq.thread0.forwLoads 598272 # Number of loads that had data forwarded from stores |
| 724system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 728system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 725system.cpu.iew.lsq.thread0.squashedLoads 1356016 # Number of loads squashed 726system.cpu.iew.lsq.thread0.ignoredResponses 3236 # Number of memory responses ignored because the instruction is squashed 727system.cpu.iew.lsq.thread0.memOrderViolation 14012 # Number of memory ordering violations 728system.cpu.iew.lsq.thread0.squashedStores 528856 # Number of stores squashed | 729system.cpu.iew.lsq.thread0.squashedLoads 1348718 # Number of loads squashed 730system.cpu.iew.lsq.thread0.ignoredResponses 3201 # Number of memory responses ignored because the instruction is squashed 731system.cpu.iew.lsq.thread0.memOrderViolation 14139 # Number of memory ordering violations 732system.cpu.iew.lsq.thread0.squashedStores 530806 # Number of stores squashed |
| 729system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 730system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 733system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 734system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 731system.cpu.iew.lsq.thread0.rescheduledLoads 17919 # Number of loads that were rescheduled 732system.cpu.iew.lsq.thread0.cacheBlocked 183461 # Number of times an access to memory failed due to the cache being blocked | 735system.cpu.iew.lsq.thread0.rescheduledLoads 17937 # Number of loads that were rescheduled 736system.cpu.iew.lsq.thread0.cacheBlocked 182742 # Number of times an access to memory failed due to the cache being blocked |
| 733system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 737system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 734system.cpu.iew.iewSquashCycles 1250340 # Number of cycles IEW is squashing 735system.cpu.iew.iewBlockCycles 10233655 # Number of cycles IEW is blocking 736system.cpu.iew.iewUnblockCycles 702274 # Number of cycles IEW is unblocking 737system.cpu.iew.iewDispatchedInsts 63801966 # Number of instructions dispatched to IQ 738system.cpu.iew.iewDispSquashedInsts 688802 # Number of squashed instructions skipped by dispatch 739system.cpu.iew.iewDispLoadInsts 10448429 # Number of dispatched load instructions 740system.cpu.iew.iewDispStoreInsts 6906827 # Number of dispatched store instructions 741system.cpu.iew.iewDispNonSpecInsts 1805093 # Number of dispatched non-speculative instructions 742system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall 743system.cpu.iew.iewLSQFullEvents 17454 # Number of times the LSQ has become full, causing a stall 744system.cpu.iew.memOrderViolationEvents 14012 # Number of memory order violations 745system.cpu.iew.predictedTakenIncorrect 201109 # Number of branches that were predicted taken incorrectly 746system.cpu.iew.predictedNotTakenIncorrect 411560 # Number of branches that were predicted not taken incorrectly 747system.cpu.iew.branchMispredicts 612669 # Number of branch mispredicts detected at execute 748system.cpu.iew.iewExecutedInsts 56346471 # Number of executed instructions 749system.cpu.iew.iewExecLoadInsts 10001011 # Number of load instructions executed 750system.cpu.iew.iewExecSquashedInsts 466475 # Number of squashed instructions skipped in execute | 738system.cpu.iew.iewSquashCycles 1249461 # Number of cycles IEW is squashing 739system.cpu.iew.iewBlockCycles 10237116 # Number of cycles IEW is blocking 740system.cpu.iew.iewUnblockCycles 702035 # Number of cycles IEW is unblocking 741system.cpu.iew.iewDispatchedInsts 63785040 # Number of instructions dispatched to IQ 742system.cpu.iew.iewDispSquashedInsts 690324 # Number of squashed instructions skipped by dispatch 743system.cpu.iew.iewDispLoadInsts 10441163 # Number of dispatched load instructions 744system.cpu.iew.iewDispStoreInsts 6908790 # Number of dispatched store instructions 745system.cpu.iew.iewDispNonSpecInsts 1805677 # Number of dispatched non-speculative instructions 746system.cpu.iew.iewIQFullEvents 512237 # Number of times the IQ has become full, causing a stall 747system.cpu.iew.iewLSQFullEvents 17569 # Number of times the LSQ has become full, causing a stall 748system.cpu.iew.memOrderViolationEvents 14139 # Number of memory order violations 749system.cpu.iew.predictedTakenIncorrect 202047 # Number of branches that were predicted taken incorrectly 750system.cpu.iew.predictedNotTakenIncorrect 411314 # Number of branches that were predicted not taken incorrectly 751system.cpu.iew.branchMispredicts 613361 # Number of branch mispredicts detected at execute 752system.cpu.iew.iewExecutedInsts 56348369 # Number of executed instructions 753system.cpu.iew.iewExecLoadInsts 9996094 # Number of load instructions executed 754system.cpu.iew.iewExecSquashedInsts 466562 # Number of squashed instructions skipped in execute |
| 751system.cpu.iew.exec_swp 0 # number of swp insts executed | 755system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 752system.cpu.iew.exec_nop 3527448 # number of nop insts executed 753system.cpu.iew.exec_refs 16619020 # number of memory reference insts executed 754system.cpu.iew.exec_branches 8923746 # Number of branches executed 755system.cpu.iew.exec_stores 6618009 # Number of stores executed 756system.cpu.iew.exec_rate 0.462131 # Inst execution rate 757system.cpu.iew.wb_sent 56013491 # cumulative count of insts sent to commit 758system.cpu.iew.wb_count 55897906 # cumulative count of insts written-back 759system.cpu.iew.wb_producers 27708487 # num instructions producing a value 760system.cpu.iew.wb_consumers 37528450 # num instructions consuming a value | 756system.cpu.iew.exec_nop 3523369 # number of nop insts executed 757system.cpu.iew.exec_refs 16615920 # number of memory reference insts executed 758system.cpu.iew.exec_branches 8927027 # Number of branches executed 759system.cpu.iew.exec_stores 6619826 # Number of stores executed 760system.cpu.iew.exec_rate 0.461997 # Inst execution rate 761system.cpu.iew.wb_sent 56016387 # cumulative count of insts sent to commit 762system.cpu.iew.wb_count 55901207 # cumulative count of insts written-back 763system.cpu.iew.wb_producers 27709617 # num instructions producing a value 764system.cpu.iew.wb_consumers 37531222 # num instructions consuming a value |
| 761system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 765system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 762system.cpu.iew.wb_rate 0.458452 # insts written-back per cycle 763system.cpu.iew.wb_fanout 0.738333 # average fanout of values written-back | 766system.cpu.iew.wb_rate 0.458331 # insts written-back per cycle 767system.cpu.iew.wb_fanout 0.738308 # average fanout of values written-back |
| 764system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 768system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 765system.cpu.commit.commitSquashedInsts 7515002 # The number of squashed insts skipped by commit 766system.cpu.commit.commitNonSpecStalls 660966 # The number of times commit has been forced to stall to communicate backwards 767system.cpu.commit.branchMispredicts 566897 # The number of times a branch was mispredicted 768system.cpu.commit.committed_per_cycle::samples 80183046 # Number of insts commited each cycle 769system.cpu.commit.committed_per_cycle::mean 0.700527 # Number of insts commited each cycle 770system.cpu.commit.committed_per_cycle::stdev 1.629598 # Number of insts commited each cycle | 769system.cpu.commit.commitSquashedInsts 7496348 # The number of squashed insts skipped by commit 770system.cpu.commit.commitNonSpecStalls 660982 # The number of times commit has been forced to stall to communicate backwards 771system.cpu.commit.branchMispredicts 568504 # The number of times a branch was mispredicted 772system.cpu.commit.committed_per_cycle::samples 80207625 # Number of insts commited each cycle 773system.cpu.commit.committed_per_cycle::mean 0.700316 # Number of insts commited each cycle 774system.cpu.commit.committed_per_cycle::stdev 1.629380 # Number of insts commited each cycle |
| 771system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 775system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 772system.cpu.commit.committed_per_cycle::0 59370328 74.04% 74.04% # Number of insts commited each cycle 773system.cpu.commit.committed_per_cycle::1 8654728 10.79% 84.84% # Number of insts commited each cycle 774system.cpu.commit.committed_per_cycle::2 4617014 5.76% 90.60% # Number of insts commited each cycle 775system.cpu.commit.committed_per_cycle::3 2519187 3.14% 93.74% # Number of insts commited each cycle 776system.cpu.commit.committed_per_cycle::4 1509953 1.88% 95.62% # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::5 613300 0.76% 96.39% # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::6 523538 0.65% 97.04% # Number of insts commited each cycle 779system.cpu.commit.committed_per_cycle::7 523484 0.65% 97.69% # Number of insts commited each cycle 780system.cpu.commit.committed_per_cycle::8 1851514 2.31% 100.00% # Number of insts commited each cycle | 776system.cpu.commit.committed_per_cycle::0 59390670 74.05% 74.05% # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::1 8659340 10.80% 84.84% # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::2 4620197 5.76% 90.60% # Number of insts commited each cycle 779system.cpu.commit.committed_per_cycle::3 2517886 3.14% 93.74% # Number of insts commited each cycle 780system.cpu.commit.committed_per_cycle::4 1507376 1.88% 95.62% # Number of insts commited each cycle 781system.cpu.commit.committed_per_cycle::5 612052 0.76% 96.38% # Number of insts commited each cycle 782system.cpu.commit.committed_per_cycle::6 525608 0.66% 97.04% # Number of insts commited each cycle 783system.cpu.commit.committed_per_cycle::7 522089 0.65% 97.69% # Number of insts commited each cycle 784system.cpu.commit.committed_per_cycle::8 1852407 2.31% 100.00% # Number of insts commited each cycle |
| 781system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 782system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 783system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 785system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 786system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 784system.cpu.commit.committed_per_cycle::total 80183046 # Number of insts commited each cycle 785system.cpu.commit.committedInsts 56170357 # Number of instructions committed 786system.cpu.commit.committedOps 56170357 # Number of ops (including micro ops) committed | 788system.cpu.commit.committed_per_cycle::total 80207625 # Number of insts commited each cycle 789system.cpu.commit.committedInsts 56170683 # Number of instructions committed 790system.cpu.commit.committedOps 56170683 # Number of ops (including micro ops) committed |
| 787system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 791system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 788system.cpu.commit.refs 15470384 # Number of memory references committed 789system.cpu.commit.loads 9092413 # Number of loads committed 790system.cpu.commit.membars 226354 # Number of memory barriers committed 791system.cpu.commit.branches 8439829 # Number of branches committed | 792system.cpu.commit.refs 15470429 # Number of memory references committed 793system.cpu.commit.loads 9092445 # Number of loads committed 794system.cpu.commit.membars 226358 # Number of memory barriers committed 795system.cpu.commit.branches 8439899 # Number of branches committed |
| 792system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 796system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 793system.cpu.commit.int_insts 52019973 # Number of committed integer instructions. 794system.cpu.commit.function_calls 740579 # Number of function calls committed. 795system.cpu.commit.bw_lim_events 1851514 # number cycles where commit BW limit reached | 797system.cpu.commit.int_insts 52020266 # Number of committed integer instructions. 798system.cpu.commit.function_calls 740581 # Number of function calls committed. 799system.cpu.commit.bw_lim_events 1852407 # number cycles where commit BW limit reached |
| 796system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 800system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 797system.cpu.rob.rob_reads 141767299 # The number of ROB reads 798system.cpu.rob.rob_writes 128622610 # The number of ROB writes 799system.cpu.timesIdled 1192878 # Number of times that the entire CPU went into an idle state and unscheduled itself 800system.cpu.idleCycles 40494102 # Total number of cycles that the CPU has spent unscheduled due to idling 801system.cpu.quiesceCycles 3598461292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 802system.cpu.committedInsts 52979573 # Number of Instructions Simulated 803system.cpu.committedOps 52979573 # Number of Ops (including micro ops) Simulated 804system.cpu.committedInsts_total 52979573 # Number of Instructions Simulated 805system.cpu.cpi 2.301406 # CPI: Cycles Per Instruction 806system.cpu.cpi_total 2.301406 # CPI: Total CPI of All Threads 807system.cpu.ipc 0.434517 # IPC: Instructions Per Cycle 808system.cpu.ipc_total 0.434517 # IPC: Total IPC of All Threads 809system.cpu.int_regfile_reads 73879526 # number of integer regfile reads 810system.cpu.int_regfile_writes 40317649 # number of integer regfile writes 811system.cpu.fp_regfile_reads 165968 # number of floating regfile reads 812system.cpu.fp_regfile_writes 167427 # number of floating regfile writes 813system.cpu.misc_regfile_reads 1984782 # number of misc regfile reads 814system.cpu.misc_regfile_writes 938976 # number of misc regfile writes | 801system.cpu.rob.rob_reads 141772543 # The number of ROB reads 802system.cpu.rob.rob_writes 128585215 # The number of ROB writes 803system.cpu.timesIdled 1193212 # Number of times that the entire CPU went into an idle state and unscheduled itself 804system.cpu.idleCycles 40509912 # Total number of cycles that the CPU has spent unscheduled due to idling 805system.cpu.quiesceCycles 3598422122 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 806system.cpu.committedInsts 52979882 # Number of Instructions Simulated 807system.cpu.committedOps 52979882 # Number of Ops (including micro ops) Simulated 808system.cpu.committedInsts_total 52979882 # Number of Instructions Simulated 809system.cpu.cpi 2.302138 # CPI: Cycles Per Instruction 810system.cpu.cpi_total 2.302138 # CPI: Total CPI of All Threads 811system.cpu.ipc 0.434379 # IPC: Instructions Per Cycle 812system.cpu.ipc_total 0.434379 # IPC: Total IPC of All Threads 813system.cpu.int_regfile_reads 73881277 # number of integer regfile reads 814system.cpu.int_regfile_writes 40316653 # number of integer regfile writes 815system.cpu.fp_regfile_reads 166009 # number of floating regfile reads 816system.cpu.fp_regfile_writes 167434 # number of floating regfile writes 817system.cpu.misc_regfile_reads 1986207 # number of misc regfile reads 818system.cpu.misc_regfile_writes 938984 # number of misc regfile writes |
| 815system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 816system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 817system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 818system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 819system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 820system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 821system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 822system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 75 unchanged lines hidden (view full) --- 898system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 899system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 900system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 901system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 902system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 903system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 904system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 905system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 819system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 820system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 821system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 822system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 823system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 824system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 825system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 826system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 75 unchanged lines hidden (view full) --- 902system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 903system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 904system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 905system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 906system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 907system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 908system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 909system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 906system.iobus.reqLayer29.occupancy 377740446 # Layer occupancy (ticks) | 910system.iobus.reqLayer29.occupancy 377738948 # Layer occupancy (ticks) |
| 907system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 908system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 909system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 910system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 911system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 911system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 912system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 913system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 914system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 915system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 912system.iobus.respLayer1.occupancy 42670757 # Layer occupancy (ticks) | 916system.iobus.respLayer1.occupancy 42679505 # Layer occupancy (ticks) |
| 913system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 917system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 914system.cpu.toL2Bus.throughput 111891693 # Throughput (bytes/s) 915system.cpu.toL2Bus.trans_dist::ReadReq 2116597 # Transaction distribution 916system.cpu.toL2Bus.trans_dist::ReadResp 2116497 # Transaction distribution | 918system.cpu.toL2Bus.throughput 111941811 # Throughput (bytes/s) 919system.cpu.toL2Bus.trans_dist::ReadReq 2118263 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::ReadResp 2118167 # Transaction distribution |
| 917system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 918system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution | 921system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 922system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution |
| 919system.cpu.toL2Bus.trans_dist::Writeback 840887 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution | 923system.cpu.toL2Bus.trans_dist::Writeback 840743 # Transaction distribution 924system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution |
| 921system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 925system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 922system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution 923system.cpu.toL2Bus.trans_dist::ReadExReq 342605 # Transaction distribution 924system.cpu.toL2Bus.trans_dist::ReadExResp 301054 # Transaction distribution 925system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution 926system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2016984 # Packet count per connected master and slave (bytes) 927system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678218 # Packet count per connected master and slave (bytes) 928system.cpu.toL2Bus.pkt_count::total 5695202 # Packet count per connected master and slave (bytes) 929system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64539584 # Cumulative packet size per connected master and slave (bytes) 930system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143593268 # Cumulative packet size per connected master and slave (bytes) 931system.cpu.toL2Bus.tot_pkt_size::total 208132852 # Cumulative packet size per connected master and slave (bytes) 932system.cpu.toL2Bus.data_through_bus 208122804 # Total data (bytes) 933system.cpu.toL2Bus.snoop_data_through_bus 17856 # Total snoop data (bytes) 934system.cpu.toL2Bus.reqLayer0.occupancy 2479701498 # Layer occupancy (ticks) | 926system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution 927system.cpu.toL2Bus.trans_dist::ReadExReq 342536 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::ReadExResp 300985 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution 930system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020543 # Packet count per connected master and slave (bytes) 931system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677710 # Packet count per connected master and slave (bytes) 932system.cpu.toL2Bus.pkt_count::total 5698253 # Packet count per connected master and slave (bytes) 933system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64653440 # Cumulative packet size per connected master and slave (bytes) 934system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143572596 # Cumulative packet size per connected master and slave (bytes) 935system.cpu.toL2Bus.tot_pkt_size::total 208226036 # Cumulative packet size per connected master and slave (bytes) 936system.cpu.toL2Bus.data_through_bus 208215988 # Total data (bytes) 937system.cpu.toL2Bus.snoop_data_through_bus 17920 # Total snoop data (bytes) 938system.cpu.toL2Bus.reqLayer0.occupancy 2480284498 # Layer occupancy (ticks) |
| 935system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 936system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 937system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 939system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 940system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 941system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 938system.cpu.toL2Bus.respLayer0.occupancy 1516139861 # Layer occupancy (ticks) | 942system.cpu.toL2Bus.respLayer0.occupancy 1518802860 # Layer occupancy (ticks) |
| 939system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 943system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 940system.cpu.toL2Bus.respLayer1.occupancy 2192873665 # Layer occupancy (ticks) | 944system.cpu.toL2Bus.respLayer1.occupancy 2192631666 # Layer occupancy (ticks) |
| 941system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 945system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 942system.cpu.icache.tags.replacements 1007825 # number of replacements 943system.cpu.icache.tags.tagsinuse 509.660233 # Cycle average of tags in use 944system.cpu.icache.tags.total_refs 7491263 # Total number of references to valid blocks. 945system.cpu.icache.tags.sampled_refs 1008333 # Sample count of references to valid blocks. 946system.cpu.icache.tags.avg_refs 7.429354 # Average number of references to valid blocks. | 946system.cpu.icache.tags.replacements 1009602 # number of replacements 947system.cpu.icache.tags.tagsinuse 509.660060 # Cycle average of tags in use 948system.cpu.icache.tags.total_refs 7489391 # Total number of references to valid blocks. 949system.cpu.icache.tags.sampled_refs 1010110 # Sample count of references to valid blocks. 950system.cpu.icache.tags.avg_refs 7.414431 # Average number of references to valid blocks. |
| 947system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit. | 951system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit. |
| 948system.cpu.icache.tags.occ_blocks::cpu.inst 509.660233 # Average occupied blocks per requestor | 952system.cpu.icache.tags.occ_blocks::cpu.inst 509.660060 # Average occupied blocks per requestor |
| 949system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy 950system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy | 953system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy 954system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy |
| 951system.cpu.icache.ReadReq_hits::cpu.inst 7491264 # number of ReadReq hits 952system.cpu.icache.ReadReq_hits::total 7491264 # number of ReadReq hits 953system.cpu.icache.demand_hits::cpu.inst 7491264 # number of demand (read+write) hits 954system.cpu.icache.demand_hits::total 7491264 # number of demand (read+write) hits 955system.cpu.icache.overall_hits::cpu.inst 7491264 # number of overall hits 956system.cpu.icache.overall_hits::total 7491264 # number of overall hits 957system.cpu.icache.ReadReq_misses::cpu.inst 1064974 # number of ReadReq misses 958system.cpu.icache.ReadReq_misses::total 1064974 # number of ReadReq misses 959system.cpu.icache.demand_misses::cpu.inst 1064974 # number of demand (read+write) misses 960system.cpu.icache.demand_misses::total 1064974 # number of demand (read+write) misses 961system.cpu.icache.overall_misses::cpu.inst 1064974 # number of overall misses 962system.cpu.icache.overall_misses::total 1064974 # number of overall misses 963system.cpu.icache.ReadReq_miss_latency::cpu.inst 14872208186 # number of ReadReq miss cycles 964system.cpu.icache.ReadReq_miss_latency::total 14872208186 # number of ReadReq miss cycles 965system.cpu.icache.demand_miss_latency::cpu.inst 14872208186 # number of demand (read+write) miss cycles 966system.cpu.icache.demand_miss_latency::total 14872208186 # number of demand (read+write) miss cycles 967system.cpu.icache.overall_miss_latency::cpu.inst 14872208186 # number of overall miss cycles 968system.cpu.icache.overall_miss_latency::total 14872208186 # number of overall miss cycles 969system.cpu.icache.ReadReq_accesses::cpu.inst 8556238 # number of ReadReq accesses(hits+misses) 970system.cpu.icache.ReadReq_accesses::total 8556238 # number of ReadReq accesses(hits+misses) 971system.cpu.icache.demand_accesses::cpu.inst 8556238 # number of demand (read+write) accesses 972system.cpu.icache.demand_accesses::total 8556238 # number of demand (read+write) accesses 973system.cpu.icache.overall_accesses::cpu.inst 8556238 # number of overall (read+write) accesses 974system.cpu.icache.overall_accesses::total 8556238 # number of overall (read+write) accesses 975system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124468 # miss rate for ReadReq accesses 976system.cpu.icache.ReadReq_miss_rate::total 0.124468 # miss rate for ReadReq accesses 977system.cpu.icache.demand_miss_rate::cpu.inst 0.124468 # miss rate for demand accesses 978system.cpu.icache.demand_miss_rate::total 0.124468 # miss rate for demand accesses 979system.cpu.icache.overall_miss_rate::cpu.inst 0.124468 # miss rate for overall accesses 980system.cpu.icache.overall_miss_rate::total 0.124468 # miss rate for overall accesses 981system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13964.855655 # average ReadReq miss latency 982system.cpu.icache.ReadReq_avg_miss_latency::total 13964.855655 # average ReadReq miss latency 983system.cpu.icache.demand_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency 984system.cpu.icache.demand_avg_miss_latency::total 13964.855655 # average overall miss latency 985system.cpu.icache.overall_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency 986system.cpu.icache.overall_avg_miss_latency::total 13964.855655 # average overall miss latency 987system.cpu.icache.blocked_cycles::no_mshrs 5226 # number of cycles access was blocked | 955system.cpu.icache.ReadReq_hits::cpu.inst 7489392 # number of ReadReq hits 956system.cpu.icache.ReadReq_hits::total 7489392 # number of ReadReq hits 957system.cpu.icache.demand_hits::cpu.inst 7489392 # number of demand (read+write) hits 958system.cpu.icache.demand_hits::total 7489392 # number of demand (read+write) hits 959system.cpu.icache.overall_hits::cpu.inst 7489392 # number of overall hits 960system.cpu.icache.overall_hits::total 7489392 # number of overall hits 961system.cpu.icache.ReadReq_misses::cpu.inst 1066652 # number of ReadReq misses 962system.cpu.icache.ReadReq_misses::total 1066652 # number of ReadReq misses 963system.cpu.icache.demand_misses::cpu.inst 1066652 # number of demand (read+write) misses 964system.cpu.icache.demand_misses::total 1066652 # number of demand (read+write) misses 965system.cpu.icache.overall_misses::cpu.inst 1066652 # number of overall misses 966system.cpu.icache.overall_misses::total 1066652 # number of overall misses 967system.cpu.icache.ReadReq_miss_latency::cpu.inst 14896343949 # number of ReadReq miss cycles 968system.cpu.icache.ReadReq_miss_latency::total 14896343949 # number of ReadReq miss cycles 969system.cpu.icache.demand_miss_latency::cpu.inst 14896343949 # number of demand (read+write) miss cycles 970system.cpu.icache.demand_miss_latency::total 14896343949 # number of demand (read+write) miss cycles 971system.cpu.icache.overall_miss_latency::cpu.inst 14896343949 # number of overall miss cycles 972system.cpu.icache.overall_miss_latency::total 14896343949 # number of overall miss cycles 973system.cpu.icache.ReadReq_accesses::cpu.inst 8556044 # number of ReadReq accesses(hits+misses) 974system.cpu.icache.ReadReq_accesses::total 8556044 # number of ReadReq accesses(hits+misses) 975system.cpu.icache.demand_accesses::cpu.inst 8556044 # number of demand (read+write) accesses 976system.cpu.icache.demand_accesses::total 8556044 # number of demand (read+write) accesses 977system.cpu.icache.overall_accesses::cpu.inst 8556044 # number of overall (read+write) accesses 978system.cpu.icache.overall_accesses::total 8556044 # number of overall (read+write) accesses 979system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124666 # miss rate for ReadReq accesses 980system.cpu.icache.ReadReq_miss_rate::total 0.124666 # miss rate for ReadReq accesses 981system.cpu.icache.demand_miss_rate::cpu.inst 0.124666 # miss rate for demand accesses 982system.cpu.icache.demand_miss_rate::total 0.124666 # miss rate for demand accesses 983system.cpu.icache.overall_miss_rate::cpu.inst 0.124666 # miss rate for overall accesses 984system.cpu.icache.overall_miss_rate::total 0.124666 # miss rate for overall accesses 985system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13965.514478 # average ReadReq miss latency 986system.cpu.icache.ReadReq_avg_miss_latency::total 13965.514478 # average ReadReq miss latency 987system.cpu.icache.demand_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency 988system.cpu.icache.demand_avg_miss_latency::total 13965.514478 # average overall miss latency 989system.cpu.icache.overall_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency 990system.cpu.icache.overall_avg_miss_latency::total 13965.514478 # average overall miss latency 991system.cpu.icache.blocked_cycles::no_mshrs 4660 # number of cycles access was blocked |
| 988system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 992system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 989system.cpu.icache.blocked::no_mshrs 214 # number of cycles access was blocked | 993system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked |
| 990system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 994system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 991system.cpu.icache.avg_blocked_cycles::no_mshrs 24.420561 # average number of cycles each access was blocked | 995system.cpu.icache.avg_blocked_cycles::no_mshrs 23.417085 # average number of cycles each access was blocked |
| 992system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 993system.cpu.icache.fast_writes 0 # number of fast writes performed 994system.cpu.icache.cache_copies 0 # number of cache copies performed | 996system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 997system.cpu.icache.fast_writes 0 # number of fast writes performed 998system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 995system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56421 # number of ReadReq MSHR hits 996system.cpu.icache.ReadReq_mshr_hits::total 56421 # number of ReadReq MSHR hits 997system.cpu.icache.demand_mshr_hits::cpu.inst 56421 # number of demand (read+write) MSHR hits 998system.cpu.icache.demand_mshr_hits::total 56421 # number of demand (read+write) MSHR hits 999system.cpu.icache.overall_mshr_hits::cpu.inst 56421 # number of overall MSHR hits 1000system.cpu.icache.overall_mshr_hits::total 56421 # number of overall MSHR hits 1001system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008553 # number of ReadReq MSHR misses 1002system.cpu.icache.ReadReq_mshr_misses::total 1008553 # number of ReadReq MSHR misses 1003system.cpu.icache.demand_mshr_misses::cpu.inst 1008553 # number of demand (read+write) MSHR misses 1004system.cpu.icache.demand_mshr_misses::total 1008553 # number of demand (read+write) MSHR misses 1005system.cpu.icache.overall_mshr_misses::cpu.inst 1008553 # number of overall MSHR misses 1006system.cpu.icache.overall_mshr_misses::total 1008553 # number of overall MSHR misses 1007system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12184986133 # number of ReadReq MSHR miss cycles 1008system.cpu.icache.ReadReq_mshr_miss_latency::total 12184986133 # number of ReadReq MSHR miss cycles 1009system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12184986133 # number of demand (read+write) MSHR miss cycles 1010system.cpu.icache.demand_mshr_miss_latency::total 12184986133 # number of demand (read+write) MSHR miss cycles 1011system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12184986133 # number of overall MSHR miss cycles 1012system.cpu.icache.overall_mshr_miss_latency::total 12184986133 # number of overall MSHR miss cycles 1013system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for ReadReq accesses 1014system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117873 # mshr miss rate for ReadReq accesses 1015system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for demand accesses 1016system.cpu.icache.demand_mshr_miss_rate::total 0.117873 # mshr miss rate for demand accesses 1017system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for overall accesses 1018system.cpu.icache.overall_mshr_miss_rate::total 0.117873 # mshr miss rate for overall accesses 1019system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.651765 # average ReadReq mshr miss latency 1020system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.651765 # average ReadReq mshr miss latency 1021system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency 1022system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.651765 # average overall mshr miss latency 1023system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency 1024system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.651765 # average overall mshr miss latency | 999system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56319 # number of ReadReq MSHR hits 1000system.cpu.icache.ReadReq_mshr_hits::total 56319 # number of ReadReq MSHR hits 1001system.cpu.icache.demand_mshr_hits::cpu.inst 56319 # number of demand (read+write) MSHR hits 1002system.cpu.icache.demand_mshr_hits::total 56319 # number of demand (read+write) MSHR hits 1003system.cpu.icache.overall_mshr_hits::cpu.inst 56319 # number of overall MSHR hits 1004system.cpu.icache.overall_mshr_hits::total 56319 # number of overall MSHR hits 1005system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010333 # number of ReadReq MSHR misses 1006system.cpu.icache.ReadReq_mshr_misses::total 1010333 # number of ReadReq MSHR misses 1007system.cpu.icache.demand_mshr_misses::cpu.inst 1010333 # number of demand (read+write) MSHR misses 1008system.cpu.icache.demand_mshr_misses::total 1010333 # number of demand (read+write) MSHR misses 1009system.cpu.icache.overall_mshr_misses::cpu.inst 1010333 # number of overall MSHR misses 1010system.cpu.icache.overall_mshr_misses::total 1010333 # number of overall MSHR misses 1011system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12206065633 # number of ReadReq MSHR miss cycles 1012system.cpu.icache.ReadReq_mshr_miss_latency::total 12206065633 # number of ReadReq MSHR miss cycles 1013system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12206065633 # number of demand (read+write) MSHR miss cycles 1014system.cpu.icache.demand_mshr_miss_latency::total 12206065633 # number of demand (read+write) MSHR miss cycles 1015system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12206065633 # number of overall MSHR miss cycles 1016system.cpu.icache.overall_mshr_miss_latency::total 12206065633 # number of overall MSHR miss cycles 1017system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118084 # mshr miss rate for ReadReq accesses 1018system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118084 # mshr miss rate for ReadReq accesses 1019system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118084 # mshr miss rate for demand accesses 1020system.cpu.icache.demand_mshr_miss_rate::total 0.118084 # mshr miss rate for demand accesses 1021system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118084 # mshr miss rate for overall accesses 1022system.cpu.icache.overall_mshr_miss_rate::total 0.118084 # mshr miss rate for overall accesses 1023system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.230281 # average ReadReq mshr miss latency 1024system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.230281 # average ReadReq mshr miss latency 1025system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.230281 # average overall mshr miss latency 1026system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.230281 # average overall mshr miss latency 1027system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.230281 # average overall mshr miss latency 1028system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.230281 # average overall mshr miss latency |
| 1025system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1029system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1026system.cpu.l2cache.tags.replacements 338320 # number of replacements 1027system.cpu.l2cache.tags.tagsinuse 65339.826573 # Cycle average of tags in use 1028system.cpu.l2cache.tags.total_refs 2544675 # Total number of references to valid blocks. 1029system.cpu.l2cache.tags.sampled_refs 403486 # Sample count of references to valid blocks. 1030system.cpu.l2cache.tags.avg_refs 6.306724 # Average number of references to valid blocks. | 1030system.cpu.l2cache.tags.replacements 338298 # number of replacements 1031system.cpu.l2cache.tags.tagsinuse 65338.001327 # Cycle average of tags in use 1032system.cpu.l2cache.tags.total_refs 2546240 # Total number of references to valid blocks. 1033system.cpu.l2cache.tags.sampled_refs 403465 # Sample count of references to valid blocks. 1034system.cpu.l2cache.tags.avg_refs 6.310932 # Average number of references to valid blocks. |
| 1031system.cpu.l2cache.tags.warmup_cycle 5511908750 # Cycle when the warmup percentage was hit. | 1035system.cpu.l2cache.tags.warmup_cycle 5511908750 # Cycle when the warmup percentage was hit. |
| 1032system.cpu.l2cache.tags.occ_blocks::writebacks 53856.157750 # Average occupied blocks per requestor 1033system.cpu.l2cache.tags.occ_blocks::cpu.inst 5301.221918 # Average occupied blocks per requestor 1034system.cpu.l2cache.tags.occ_blocks::cpu.data 6182.446905 # Average occupied blocks per requestor 1035system.cpu.l2cache.tags.occ_percent::writebacks 0.821780 # Average percentage of cache occupancy 1036system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080890 # Average percentage of cache occupancy 1037system.cpu.l2cache.tags.occ_percent::cpu.data 0.094337 # Average percentage of cache occupancy 1038system.cpu.l2cache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy 1039system.cpu.l2cache.ReadReq_hits::cpu.inst 993358 # number of ReadReq hits 1040system.cpu.l2cache.ReadReq_hits::cpu.data 827156 # number of ReadReq hits 1041system.cpu.l2cache.ReadReq_hits::total 1820514 # number of ReadReq hits 1042system.cpu.l2cache.Writeback_hits::writebacks 840887 # number of Writeback hits 1043system.cpu.l2cache.Writeback_hits::total 840887 # number of Writeback hits 1044system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits 1045system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits 1046system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1047system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1048system.cpu.l2cache.ReadExReq_hits::cpu.data 185595 # number of ReadExReq hits 1049system.cpu.l2cache.ReadExReq_hits::total 185595 # number of ReadExReq hits 1050system.cpu.l2cache.demand_hits::cpu.inst 993358 # number of demand (read+write) hits 1051system.cpu.l2cache.demand_hits::cpu.data 1012751 # number of demand (read+write) hits 1052system.cpu.l2cache.demand_hits::total 2006109 # number of demand (read+write) hits 1053system.cpu.l2cache.overall_hits::cpu.inst 993358 # number of overall hits 1054system.cpu.l2cache.overall_hits::cpu.data 1012751 # number of overall hits 1055system.cpu.l2cache.overall_hits::total 2006109 # number of overall hits 1056system.cpu.l2cache.ReadReq_misses::cpu.inst 15073 # number of ReadReq misses 1057system.cpu.l2cache.ReadReq_misses::cpu.data 273785 # number of ReadReq misses 1058system.cpu.l2cache.ReadReq_misses::total 288858 # number of ReadReq misses 1059system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses 1060system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses 1061system.cpu.l2cache.ReadExReq_misses::cpu.data 115458 # number of ReadExReq misses 1062system.cpu.l2cache.ReadExReq_misses::total 115458 # number of ReadExReq misses 1063system.cpu.l2cache.demand_misses::cpu.inst 15073 # number of demand (read+write) misses 1064system.cpu.l2cache.demand_misses::cpu.data 389243 # number of demand (read+write) misses 1065system.cpu.l2cache.demand_misses::total 404316 # number of demand (read+write) misses 1066system.cpu.l2cache.overall_misses::cpu.inst 15073 # number of overall misses 1067system.cpu.l2cache.overall_misses::cpu.data 389243 # number of overall misses 1068system.cpu.l2cache.overall_misses::total 404316 # number of overall misses 1069system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1217060992 # number of ReadReq miss cycles 1070system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17822778727 # number of ReadReq miss cycles 1071system.cpu.l2cache.ReadReq_miss_latency::total 19039839719 # number of ReadReq miss cycles 1072system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 308496 # number of UpgradeReq miss cycles 1073system.cpu.l2cache.UpgradeReq_miss_latency::total 308496 # number of UpgradeReq miss cycles 1074system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9541842859 # number of ReadExReq miss cycles 1075system.cpu.l2cache.ReadExReq_miss_latency::total 9541842859 # number of ReadExReq miss cycles 1076system.cpu.l2cache.demand_miss_latency::cpu.inst 1217060992 # number of demand (read+write) miss cycles 1077system.cpu.l2cache.demand_miss_latency::cpu.data 27364621586 # number of demand (read+write) miss cycles 1078system.cpu.l2cache.demand_miss_latency::total 28581682578 # number of demand (read+write) miss cycles 1079system.cpu.l2cache.overall_miss_latency::cpu.inst 1217060992 # number of overall miss cycles 1080system.cpu.l2cache.overall_miss_latency::cpu.data 27364621586 # number of overall miss cycles 1081system.cpu.l2cache.overall_miss_latency::total 28581682578 # number of overall miss cycles 1082system.cpu.l2cache.ReadReq_accesses::cpu.inst 1008431 # number of ReadReq accesses(hits+misses) 1083system.cpu.l2cache.ReadReq_accesses::cpu.data 1100941 # number of ReadReq accesses(hits+misses) 1084system.cpu.l2cache.ReadReq_accesses::total 2109372 # number of ReadReq accesses(hits+misses) 1085system.cpu.l2cache.Writeback_accesses::writebacks 840887 # number of Writeback accesses(hits+misses) 1086system.cpu.l2cache.Writeback_accesses::total 840887 # number of Writeback accesses(hits+misses) 1087system.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses) 1088system.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses) | 1036system.cpu.l2cache.tags.occ_blocks::writebacks 53847.908430 # Average occupied blocks per requestor 1037system.cpu.l2cache.tags.occ_blocks::cpu.inst 5309.513440 # Average occupied blocks per requestor 1038system.cpu.l2cache.tags.occ_blocks::cpu.data 6180.579458 # Average occupied blocks per requestor 1039system.cpu.l2cache.tags.occ_percent::writebacks 0.821654 # Average percentage of cache occupancy 1040system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081017 # Average percentage of cache occupancy 1041system.cpu.l2cache.tags.occ_percent::cpu.data 0.094308 # Average percentage of cache occupancy 1042system.cpu.l2cache.tags.occ_percent::total 0.996979 # Average percentage of cache occupancy 1043system.cpu.l2cache.ReadReq_hits::cpu.inst 995146 # number of ReadReq hits 1044system.cpu.l2cache.ReadReq_hits::cpu.data 827013 # number of ReadReq hits 1045system.cpu.l2cache.ReadReq_hits::total 1822159 # number of ReadReq hits 1046system.cpu.l2cache.Writeback_hits::writebacks 840743 # number of Writeback hits 1047system.cpu.l2cache.Writeback_hits::total 840743 # number of Writeback hits 1048system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 1049system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 1050system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 1051system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 1052system.cpu.l2cache.ReadExReq_hits::cpu.data 185570 # number of ReadExReq hits 1053system.cpu.l2cache.ReadExReq_hits::total 185570 # number of ReadExReq hits 1054system.cpu.l2cache.demand_hits::cpu.inst 995146 # number of demand (read+write) hits 1055system.cpu.l2cache.demand_hits::cpu.data 1012583 # number of demand (read+write) hits 1056system.cpu.l2cache.demand_hits::total 2007729 # number of demand (read+write) hits 1057system.cpu.l2cache.overall_hits::cpu.inst 995146 # number of overall hits 1058system.cpu.l2cache.overall_hits::cpu.data 1012583 # number of overall hits 1059system.cpu.l2cache.overall_hits::total 2007729 # number of overall hits 1060system.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses 1061system.cpu.l2cache.ReadReq_misses::cpu.data 273814 # number of ReadReq misses 1062system.cpu.l2cache.ReadReq_misses::total 288878 # number of ReadReq misses 1063system.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses 1064system.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses 1065system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 1066system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 1067system.cpu.l2cache.ReadExReq_misses::cpu.data 115414 # number of ReadExReq misses 1068system.cpu.l2cache.ReadExReq_misses::total 115414 # number of ReadExReq misses 1069system.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses 1070system.cpu.l2cache.demand_misses::cpu.data 389228 # number of demand (read+write) misses 1071system.cpu.l2cache.demand_misses::total 404292 # number of demand (read+write) misses 1072system.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses 1073system.cpu.l2cache.overall_misses::cpu.data 389228 # number of overall misses 1074system.cpu.l2cache.overall_misses::total 404292 # number of overall misses 1075system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1218545993 # number of ReadReq miss cycles 1076system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17819527728 # number of ReadReq miss cycles 1077system.cpu.l2cache.ReadReq_miss_latency::total 19038073721 # number of ReadReq miss cycles 1078system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262498 # number of UpgradeReq miss cycles 1079system.cpu.l2cache.UpgradeReq_miss_latency::total 262498 # number of UpgradeReq miss cycles 1080system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 22999 # number of SCUpgradeReq miss cycles 1081system.cpu.l2cache.SCUpgradeReq_miss_latency::total 22999 # number of SCUpgradeReq miss cycles 1082system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9547009857 # number of ReadExReq miss cycles 1083system.cpu.l2cache.ReadExReq_miss_latency::total 9547009857 # number of ReadExReq miss cycles 1084system.cpu.l2cache.demand_miss_latency::cpu.inst 1218545993 # number of demand (read+write) miss cycles 1085system.cpu.l2cache.demand_miss_latency::cpu.data 27366537585 # number of demand (read+write) miss cycles 1086system.cpu.l2cache.demand_miss_latency::total 28585083578 # number of demand (read+write) miss cycles 1087system.cpu.l2cache.overall_miss_latency::cpu.inst 1218545993 # number of overall miss cycles 1088system.cpu.l2cache.overall_miss_latency::cpu.data 27366537585 # number of overall miss cycles 1089system.cpu.l2cache.overall_miss_latency::total 28585083578 # number of overall miss cycles 1090system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010210 # number of ReadReq accesses(hits+misses) 1091system.cpu.l2cache.ReadReq_accesses::cpu.data 1100827 # number of ReadReq accesses(hits+misses) 1092system.cpu.l2cache.ReadReq_accesses::total 2111037 # number of ReadReq accesses(hits+misses) 1093system.cpu.l2cache.Writeback_accesses::writebacks 840743 # number of Writeback accesses(hits+misses) 1094system.cpu.l2cache.Writeback_accesses::total 840743 # number of Writeback accesses(hits+misses) 1095system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses) 1096system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses) |
| 1089system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1090system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) | 1097system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1098system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) |
| 1091system.cpu.l2cache.ReadExReq_accesses::cpu.data 301053 # number of ReadExReq accesses(hits+misses) 1092system.cpu.l2cache.ReadExReq_accesses::total 301053 # number of ReadExReq accesses(hits+misses) 1093system.cpu.l2cache.demand_accesses::cpu.inst 1008431 # number of demand (read+write) accesses 1094system.cpu.l2cache.demand_accesses::cpu.data 1401994 # number of demand (read+write) accesses 1095system.cpu.l2cache.demand_accesses::total 2410425 # number of demand (read+write) accesses 1096system.cpu.l2cache.overall_accesses::cpu.inst 1008431 # number of overall (read+write) accesses 1097system.cpu.l2cache.overall_accesses::cpu.data 1401994 # number of overall (read+write) accesses 1098system.cpu.l2cache.overall_accesses::total 2410425 # number of overall (read+write) accesses 1099system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014947 # miss rate for ReadReq accesses 1100system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248683 # miss rate for ReadReq accesses 1101system.cpu.l2cache.ReadReq_miss_rate::total 0.136940 # miss rate for ReadReq accesses 1102system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.619048 # miss rate for UpgradeReq accesses 1103system.cpu.l2cache.UpgradeReq_miss_rate::total 0.619048 # miss rate for UpgradeReq accesses 1104system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383514 # miss rate for ReadExReq accesses 1105system.cpu.l2cache.ReadExReq_miss_rate::total 0.383514 # miss rate for ReadExReq accesses 1106system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014947 # miss rate for demand accesses 1107system.cpu.l2cache.demand_miss_rate::cpu.data 0.277635 # miss rate for demand accesses 1108system.cpu.l2cache.demand_miss_rate::total 0.167736 # miss rate for demand accesses 1109system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014947 # miss rate for overall accesses 1110system.cpu.l2cache.overall_miss_rate::cpu.data 0.277635 # miss rate for overall accesses 1111system.cpu.l2cache.overall_miss_rate::total 0.167736 # miss rate for overall accesses 1112system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80744.443177 # average ReadReq miss latency 1113system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65097.718016 # average ReadReq miss latency 1114system.cpu.l2cache.ReadReq_avg_miss_latency::total 65914.185236 # average ReadReq miss latency 1115system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7910.153846 # average UpgradeReq miss latency 1116system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7910.153846 # average UpgradeReq miss latency 1117system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82643.410236 # average ReadExReq miss latency 1118system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82643.410236 # average ReadExReq miss latency 1119system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80744.443177 # average overall miss latency 1120system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70302.154659 # average overall miss latency 1121system.cpu.l2cache.demand_avg_miss_latency::total 70691.445745 # average overall miss latency 1122system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80744.443177 # average overall miss latency 1123system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70302.154659 # average overall miss latency 1124system.cpu.l2cache.overall_avg_miss_latency::total 70691.445745 # average overall miss latency | 1099system.cpu.l2cache.ReadExReq_accesses::cpu.data 300984 # number of ReadExReq accesses(hits+misses) 1100system.cpu.l2cache.ReadExReq_accesses::total 300984 # number of ReadExReq accesses(hits+misses) 1101system.cpu.l2cache.demand_accesses::cpu.inst 1010210 # number of demand (read+write) accesses 1102system.cpu.l2cache.demand_accesses::cpu.data 1401811 # number of demand (read+write) accesses 1103system.cpu.l2cache.demand_accesses::total 2412021 # number of demand (read+write) accesses 1104system.cpu.l2cache.overall_accesses::cpu.inst 1010210 # number of overall (read+write) accesses 1105system.cpu.l2cache.overall_accesses::cpu.data 1401811 # number of overall (read+write) accesses 1106system.cpu.l2cache.overall_accesses::total 2412021 # number of overall (read+write) accesses 1107system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014912 # miss rate for ReadReq accesses 1108system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248735 # miss rate for ReadReq accesses 1109system.cpu.l2cache.ReadReq_miss_rate::total 0.136842 # miss rate for ReadReq accesses 1110system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses 1111system.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses 1112system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses 1113system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses 1114system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383456 # miss rate for ReadExReq accesses 1115system.cpu.l2cache.ReadExReq_miss_rate::total 0.383456 # miss rate for ReadExReq accesses 1116system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014912 # miss rate for demand accesses 1117system.cpu.l2cache.demand_miss_rate::cpu.data 0.277661 # miss rate for demand accesses 1118system.cpu.l2cache.demand_miss_rate::total 0.167615 # miss rate for demand accesses 1119system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014912 # miss rate for overall accesses 1120system.cpu.l2cache.overall_miss_rate::cpu.data 0.277661 # miss rate for overall accesses 1121system.cpu.l2cache.overall_miss_rate::total 0.167615 # miss rate for overall accesses 1122system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80891.263476 # average ReadReq miss latency 1123system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65078.950412 # average ReadReq miss latency 1124system.cpu.l2cache.ReadReq_avg_miss_latency::total 65903.508474 # average ReadReq miss latency 1125system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6907.842105 # average UpgradeReq miss latency 1126system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6907.842105 # average UpgradeReq miss latency 1127system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 22999 # average SCUpgradeReq miss latency 1128system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 22999 # average SCUpgradeReq miss latency 1129system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82719.686147 # average ReadExReq miss latency 1130system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82719.686147 # average ReadExReq miss latency 1131system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80891.263476 # average overall miss latency 1132system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70309.786513 # average overall miss latency 1133system.cpu.l2cache.demand_avg_miss_latency::total 70704.054441 # average overall miss latency 1134system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80891.263476 # average overall miss latency 1135system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70309.786513 # average overall miss latency 1136system.cpu.l2cache.overall_avg_miss_latency::total 70704.054441 # average overall miss latency |
| 1125system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1126system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1127system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1128system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1129system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1130system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1131system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1132system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1137system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1138system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1139system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1140system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1141system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1142system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1143system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1144system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1133system.cpu.l2cache.writebacks::writebacks 75936 # number of writebacks 1134system.cpu.l2cache.writebacks::total 75936 # number of writebacks | 1145system.cpu.l2cache.writebacks::writebacks 75917 # number of writebacks 1146system.cpu.l2cache.writebacks::total 75917 # number of writebacks |
| 1135system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1136system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1137system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1138system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1139system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1140system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 1147system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1148system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1149system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1150system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1151system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1152system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 1141system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15072 # number of ReadReq MSHR misses 1142system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273785 # number of ReadReq MSHR misses 1143system.cpu.l2cache.ReadReq_mshr_misses::total 288857 # number of ReadReq MSHR misses 1144system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses 1145system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses 1146system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115458 # number of ReadExReq MSHR misses 1147system.cpu.l2cache.ReadExReq_mshr_misses::total 115458 # number of ReadExReq MSHR misses 1148system.cpu.l2cache.demand_mshr_misses::cpu.inst 15072 # number of demand (read+write) MSHR misses 1149system.cpu.l2cache.demand_mshr_misses::cpu.data 389243 # number of demand (read+write) MSHR misses 1150system.cpu.l2cache.demand_mshr_misses::total 404315 # number of demand (read+write) MSHR misses 1151system.cpu.l2cache.overall_mshr_misses::cpu.inst 15072 # number of overall MSHR misses 1152system.cpu.l2cache.overall_mshr_misses::cpu.data 389243 # number of overall MSHR misses 1153system.cpu.l2cache.overall_mshr_misses::total 404315 # number of overall MSHR misses 1154system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1026861258 # number of ReadReq MSHR miss cycles 1155system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14410483773 # number of ReadReq MSHR miss cycles 1156system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15437345031 # number of ReadReq MSHR miss cycles 1157system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 542534 # number of UpgradeReq MSHR miss cycles 1158system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 542534 # number of UpgradeReq MSHR miss cycles 1159system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8118910641 # number of ReadExReq MSHR miss cycles 1160system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8118910641 # number of ReadExReq MSHR miss cycles 1161system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1026861258 # number of demand (read+write) MSHR miss cycles 1162system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22529394414 # number of demand (read+write) MSHR miss cycles 1163system.cpu.l2cache.demand_mshr_miss_latency::total 23556255672 # number of demand (read+write) MSHR miss cycles 1164system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1026861258 # number of overall MSHR miss cycles 1165system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22529394414 # number of overall MSHR miss cycles 1166system.cpu.l2cache.overall_mshr_miss_latency::total 23556255672 # number of overall MSHR miss cycles 1167system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334047500 # number of ReadReq MSHR uncacheable cycles 1168system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334047500 # number of ReadReq MSHR uncacheable cycles 1169system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882613000 # number of WriteReq MSHR uncacheable cycles 1170system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882613000 # number of WriteReq MSHR uncacheable cycles 1171system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216660500 # number of overall MSHR uncacheable cycles 1172system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216660500 # number of overall MSHR uncacheable cycles 1173system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for ReadReq accesses 1174system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248683 # mshr miss rate for ReadReq accesses 1175system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136940 # mshr miss rate for ReadReq accesses 1176system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses 1177system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses 1178system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383514 # mshr miss rate for ReadExReq accesses 1179system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383514 # mshr miss rate for ReadExReq accesses 1180system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for demand accesses 1181system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277635 # mshr miss rate for demand accesses 1182system.cpu.l2cache.demand_mshr_miss_rate::total 0.167736 # mshr miss rate for demand accesses 1183system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for overall accesses 1184system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277635 # mshr miss rate for overall accesses 1185system.cpu.l2cache.overall_mshr_miss_rate::total 0.167736 # mshr miss rate for overall accesses 1186system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68130.391322 # average ReadReq mshr miss latency 1187system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52634.307113 # average ReadReq mshr miss latency 1188system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53442.862839 # average ReadReq mshr miss latency 1189system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13911.128205 # average UpgradeReq mshr miss latency 1190system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13911.128205 # average UpgradeReq mshr miss latency 1191system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70319.169230 # average ReadExReq mshr miss latency 1192system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70319.169230 # average ReadExReq mshr miss latency 1193system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68130.391322 # average overall mshr miss latency 1194system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency 1195system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency 1196system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68130.391322 # average overall mshr miss latency 1197system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency 1198system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency | 1153system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses 1154system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273814 # number of ReadReq MSHR misses 1155system.cpu.l2cache.ReadReq_mshr_misses::total 288877 # number of ReadReq MSHR misses 1156system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses 1157system.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses 1158system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1159system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1160system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115414 # number of ReadExReq MSHR misses 1161system.cpu.l2cache.ReadExReq_mshr_misses::total 115414 # number of ReadExReq MSHR misses 1162system.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses 1163system.cpu.l2cache.demand_mshr_misses::cpu.data 389228 # number of demand (read+write) MSHR misses 1164system.cpu.l2cache.demand_mshr_misses::total 404291 # number of demand (read+write) MSHR misses 1165system.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses 1166system.cpu.l2cache.overall_mshr_misses::cpu.data 389228 # number of overall MSHR misses 1167system.cpu.l2cache.overall_mshr_misses::total 404291 # number of overall MSHR misses 1168system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1028470757 # number of ReadReq MSHR miss cycles 1169system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14406345772 # number of ReadReq MSHR miss cycles 1170system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15434816529 # number of ReadReq MSHR miss cycles 1171system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 532033 # number of UpgradeReq MSHR miss cycles 1172system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 532033 # number of UpgradeReq MSHR miss cycles 1173system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles 1174system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles 1175system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8124534143 # number of ReadExReq MSHR miss cycles 1176system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8124534143 # number of ReadExReq MSHR miss cycles 1177system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1028470757 # number of demand (read+write) MSHR miss cycles 1178system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22530879915 # number of demand (read+write) MSHR miss cycles 1179system.cpu.l2cache.demand_mshr_miss_latency::total 23559350672 # number of demand (read+write) MSHR miss cycles 1180system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1028470757 # number of overall MSHR miss cycles 1181system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22530879915 # number of overall MSHR miss cycles 1182system.cpu.l2cache.overall_mshr_miss_latency::total 23559350672 # number of overall MSHR miss cycles 1183system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333940000 # number of ReadReq MSHR uncacheable cycles 1184system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333940000 # number of ReadReq MSHR uncacheable cycles 1185system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882589500 # number of WriteReq MSHR uncacheable cycles 1186system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882589500 # number of WriteReq MSHR uncacheable cycles 1187system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216529500 # number of overall MSHR uncacheable cycles 1188system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216529500 # number of overall MSHR uncacheable cycles 1189system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for ReadReq accesses 1190system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248735 # mshr miss rate for ReadReq accesses 1191system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136841 # mshr miss rate for ReadReq accesses 1192system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses 1193system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses 1194system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 1195system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses 1196system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383456 # mshr miss rate for ReadExReq accesses 1197system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383456 # mshr miss rate for ReadExReq accesses 1198system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for demand accesses 1199system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277661 # mshr miss rate for demand accesses 1200system.cpu.l2cache.demand_mshr_miss_rate::total 0.167615 # mshr miss rate for demand accesses 1201system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for overall accesses 1202system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277661 # mshr miss rate for overall accesses 1203system.cpu.l2cache.overall_mshr_miss_rate::total 0.167615 # mshr miss rate for overall accesses 1204system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68277.949744 # average ReadReq mshr miss latency 1205system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52613.620092 # average ReadReq mshr miss latency 1206system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53430.409929 # average ReadReq mshr miss latency 1207system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14000.868421 # average UpgradeReq mshr miss latency 1208system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14000.868421 # average UpgradeReq mshr miss latency 1209system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1210system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1211system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70394.702055 # average ReadExReq mshr miss latency 1212system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70394.702055 # average ReadExReq mshr miss latency 1213system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68277.949744 # average overall mshr miss latency 1214system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57886.071698 # average overall mshr miss latency 1215system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58273.250386 # average overall mshr miss latency 1216system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68277.949744 # average overall mshr miss latency 1217system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57886.071698 # average overall mshr miss latency 1218system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58273.250386 # average overall mshr miss latency |
| 1199system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1200system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1201system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1202system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1203system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1204system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1205system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1219system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1220system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1221system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1222system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1223system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1224system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1225system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1206system.cpu.dcache.tags.replacements 1401398 # number of replacements 1207system.cpu.dcache.tags.tagsinuse 511.994568 # Cycle average of tags in use 1208system.cpu.dcache.tags.total_refs 11815525 # Total number of references to valid blocks. 1209system.cpu.dcache.tags.sampled_refs 1401910 # Sample count of references to valid blocks. 1210system.cpu.dcache.tags.avg_refs 8.428162 # Average number of references to valid blocks. | 1226system.cpu.dcache.tags.replacements 1401219 # number of replacements 1227system.cpu.dcache.tags.tagsinuse 511.994567 # Cycle average of tags in use 1228system.cpu.dcache.tags.total_refs 11810743 # Total number of references to valid blocks. 1229system.cpu.dcache.tags.sampled_refs 1401731 # Sample count of references to valid blocks. 1230system.cpu.dcache.tags.avg_refs 8.425827 # Average number of references to valid blocks. |
| 1211system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit. | 1231system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit. |
| 1212system.cpu.dcache.tags.occ_blocks::cpu.data 511.994568 # Average occupied blocks per requestor | 1232system.cpu.dcache.tags.occ_blocks::cpu.data 511.994567 # Average occupied blocks per requestor |
| 1213system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 1214system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy | 1233system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 1234system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy |
| 1215system.cpu.dcache.ReadReq_hits::cpu.data 7210216 # number of ReadReq hits 1216system.cpu.dcache.ReadReq_hits::total 7210216 # number of ReadReq hits 1217system.cpu.dcache.WriteReq_hits::cpu.data 4203313 # number of WriteReq hits 1218system.cpu.dcache.WriteReq_hits::total 4203313 # number of WriteReq hits 1219system.cpu.dcache.LoadLockedReq_hits::cpu.data 186240 # number of LoadLockedReq hits 1220system.cpu.dcache.LoadLockedReq_hits::total 186240 # number of LoadLockedReq hits 1221system.cpu.dcache.StoreCondReq_hits::cpu.data 215515 # number of StoreCondReq hits 1222system.cpu.dcache.StoreCondReq_hits::total 215515 # number of StoreCondReq hits 1223system.cpu.dcache.demand_hits::cpu.data 11413529 # number of demand (read+write) hits 1224system.cpu.dcache.demand_hits::total 11413529 # number of demand (read+write) hits 1225system.cpu.dcache.overall_hits::cpu.data 11413529 # number of overall hits 1226system.cpu.dcache.overall_hits::total 11413529 # number of overall hits 1227system.cpu.dcache.ReadReq_misses::cpu.data 1806580 # number of ReadReq misses 1228system.cpu.dcache.ReadReq_misses::total 1806580 # number of ReadReq misses 1229system.cpu.dcache.WriteReq_misses::cpu.data 1944438 # number of WriteReq misses 1230system.cpu.dcache.WriteReq_misses::total 1944438 # number of WriteReq misses 1231system.cpu.dcache.LoadLockedReq_misses::cpu.data 22731 # number of LoadLockedReq misses 1232system.cpu.dcache.LoadLockedReq_misses::total 22731 # number of LoadLockedReq misses | 1235system.cpu.dcache.ReadReq_hits::cpu.data 7205308 # number of ReadReq hits 1236system.cpu.dcache.ReadReq_hits::total 7205308 # number of ReadReq hits 1237system.cpu.dcache.WriteReq_hits::cpu.data 4203634 # number of WriteReq hits 1238system.cpu.dcache.WriteReq_hits::total 4203634 # number of WriteReq hits 1239system.cpu.dcache.LoadLockedReq_hits::cpu.data 186044 # number of LoadLockedReq hits 1240system.cpu.dcache.LoadLockedReq_hits::total 186044 # number of LoadLockedReq hits 1241system.cpu.dcache.StoreCondReq_hits::cpu.data 215517 # number of StoreCondReq hits 1242system.cpu.dcache.StoreCondReq_hits::total 215517 # number of StoreCondReq hits 1243system.cpu.dcache.demand_hits::cpu.data 11408942 # number of demand (read+write) hits 1244system.cpu.dcache.demand_hits::total 11408942 # number of demand (read+write) hits 1245system.cpu.dcache.overall_hits::cpu.data 11408942 # number of overall hits 1246system.cpu.dcache.overall_hits::total 11408942 # number of overall hits 1247system.cpu.dcache.ReadReq_misses::cpu.data 1806790 # number of ReadReq misses 1248system.cpu.dcache.ReadReq_misses::total 1806790 # number of ReadReq misses 1249system.cpu.dcache.WriteReq_misses::cpu.data 1944128 # number of WriteReq misses 1250system.cpu.dcache.WriteReq_misses::total 1944128 # number of WriteReq misses 1251system.cpu.dcache.LoadLockedReq_misses::cpu.data 22738 # number of LoadLockedReq misses 1252system.cpu.dcache.LoadLockedReq_misses::total 22738 # number of LoadLockedReq misses |
| 1233system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1234system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses | 1253system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1254system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses |
| 1235system.cpu.dcache.demand_misses::cpu.data 3751018 # number of demand (read+write) misses 1236system.cpu.dcache.demand_misses::total 3751018 # number of demand (read+write) misses 1237system.cpu.dcache.overall_misses::cpu.data 3751018 # number of overall misses 1238system.cpu.dcache.overall_misses::total 3751018 # number of overall misses 1239system.cpu.dcache.ReadReq_miss_latency::cpu.data 40329752439 # number of ReadReq miss cycles 1240system.cpu.dcache.ReadReq_miss_latency::total 40329752439 # number of ReadReq miss cycles 1241system.cpu.dcache.WriteReq_miss_latency::cpu.data 77181819403 # number of WriteReq miss cycles 1242system.cpu.dcache.WriteReq_miss_latency::total 77181819403 # number of WriteReq miss cycles 1243system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321716499 # number of LoadLockedReq miss cycles 1244system.cpu.dcache.LoadLockedReq_miss_latency::total 321716499 # number of LoadLockedReq miss cycles 1245system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles 1246system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles 1247system.cpu.dcache.demand_miss_latency::cpu.data 117511571842 # number of demand (read+write) miss cycles 1248system.cpu.dcache.demand_miss_latency::total 117511571842 # number of demand (read+write) miss cycles 1249system.cpu.dcache.overall_miss_latency::cpu.data 117511571842 # number of overall miss cycles 1250system.cpu.dcache.overall_miss_latency::total 117511571842 # number of overall miss cycles 1251system.cpu.dcache.ReadReq_accesses::cpu.data 9016796 # number of ReadReq accesses(hits+misses) 1252system.cpu.dcache.ReadReq_accesses::total 9016796 # number of ReadReq accesses(hits+misses) 1253system.cpu.dcache.WriteReq_accesses::cpu.data 6147751 # number of WriteReq accesses(hits+misses) 1254system.cpu.dcache.WriteReq_accesses::total 6147751 # number of WriteReq accesses(hits+misses) 1255system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208971 # number of LoadLockedReq accesses(hits+misses) 1256system.cpu.dcache.LoadLockedReq_accesses::total 208971 # number of LoadLockedReq accesses(hits+misses) 1257system.cpu.dcache.StoreCondReq_accesses::cpu.data 215517 # number of StoreCondReq accesses(hits+misses) 1258system.cpu.dcache.StoreCondReq_accesses::total 215517 # number of StoreCondReq accesses(hits+misses) 1259system.cpu.dcache.demand_accesses::cpu.data 15164547 # number of demand (read+write) accesses 1260system.cpu.dcache.demand_accesses::total 15164547 # number of demand (read+write) accesses 1261system.cpu.dcache.overall_accesses::cpu.data 15164547 # number of overall (read+write) accesses 1262system.cpu.dcache.overall_accesses::total 15164547 # number of overall (read+write) accesses 1263system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200357 # miss rate for ReadReq accesses 1264system.cpu.dcache.ReadReq_miss_rate::total 0.200357 # miss rate for ReadReq accesses 1265system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316284 # miss rate for WriteReq accesses 1266system.cpu.dcache.WriteReq_miss_rate::total 0.316284 # miss rate for WriteReq accesses 1267system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108776 # miss rate for LoadLockedReq accesses 1268system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108776 # miss rate for LoadLockedReq accesses | 1255system.cpu.dcache.demand_misses::cpu.data 3750918 # number of demand (read+write) misses 1256system.cpu.dcache.demand_misses::total 3750918 # number of demand (read+write) misses 1257system.cpu.dcache.overall_misses::cpu.data 3750918 # number of overall misses 1258system.cpu.dcache.overall_misses::total 3750918 # number of overall misses 1259system.cpu.dcache.ReadReq_miss_latency::cpu.data 40335866684 # number of ReadReq miss cycles 1260system.cpu.dcache.ReadReq_miss_latency::total 40335866684 # number of ReadReq miss cycles 1261system.cpu.dcache.WriteReq_miss_latency::cpu.data 77256495609 # number of WriteReq miss cycles 1262system.cpu.dcache.WriteReq_miss_latency::total 77256495609 # number of WriteReq miss cycles 1263system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322518001 # number of LoadLockedReq miss cycles 1264system.cpu.dcache.LoadLockedReq_miss_latency::total 322518001 # number of LoadLockedReq miss cycles 1265system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 39001 # number of StoreCondReq miss cycles 1266system.cpu.dcache.StoreCondReq_miss_latency::total 39001 # number of StoreCondReq miss cycles 1267system.cpu.dcache.demand_miss_latency::cpu.data 117592362293 # number of demand (read+write) miss cycles 1268system.cpu.dcache.demand_miss_latency::total 117592362293 # number of demand (read+write) miss cycles 1269system.cpu.dcache.overall_miss_latency::cpu.data 117592362293 # number of overall miss cycles 1270system.cpu.dcache.overall_miss_latency::total 117592362293 # number of overall miss cycles 1271system.cpu.dcache.ReadReq_accesses::cpu.data 9012098 # number of ReadReq accesses(hits+misses) 1272system.cpu.dcache.ReadReq_accesses::total 9012098 # number of ReadReq accesses(hits+misses) 1273system.cpu.dcache.WriteReq_accesses::cpu.data 6147762 # number of WriteReq accesses(hits+misses) 1274system.cpu.dcache.WriteReq_accesses::total 6147762 # number of WriteReq accesses(hits+misses) 1275system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208782 # number of LoadLockedReq accesses(hits+misses) 1276system.cpu.dcache.LoadLockedReq_accesses::total 208782 # number of LoadLockedReq accesses(hits+misses) 1277system.cpu.dcache.StoreCondReq_accesses::cpu.data 215519 # number of StoreCondReq accesses(hits+misses) 1278system.cpu.dcache.StoreCondReq_accesses::total 215519 # number of StoreCondReq accesses(hits+misses) 1279system.cpu.dcache.demand_accesses::cpu.data 15159860 # number of demand (read+write) accesses 1280system.cpu.dcache.demand_accesses::total 15159860 # number of demand (read+write) accesses 1281system.cpu.dcache.overall_accesses::cpu.data 15159860 # number of overall (read+write) accesses 1282system.cpu.dcache.overall_accesses::total 15159860 # number of overall (read+write) accesses 1283system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200485 # miss rate for ReadReq accesses 1284system.cpu.dcache.ReadReq_miss_rate::total 0.200485 # miss rate for ReadReq accesses 1285system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316233 # miss rate for WriteReq accesses 1286system.cpu.dcache.WriteReq_miss_rate::total 0.316233 # miss rate for WriteReq accesses 1287system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108908 # miss rate for LoadLockedReq accesses 1288system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108908 # miss rate for LoadLockedReq accesses |
| 1269system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 1270system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses | 1289system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 1290system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses |
| 1271system.cpu.dcache.demand_miss_rate::cpu.data 0.247354 # miss rate for demand accesses 1272system.cpu.dcache.demand_miss_rate::total 0.247354 # miss rate for demand accesses 1273system.cpu.dcache.overall_miss_rate::cpu.data 0.247354 # miss rate for overall accesses 1274system.cpu.dcache.overall_miss_rate::total 0.247354 # miss rate for overall accesses 1275system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22323.812086 # average ReadReq miss latency 1276system.cpu.dcache.ReadReq_avg_miss_latency::total 22323.812086 # average ReadReq miss latency 1277system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39693.638678 # average WriteReq miss latency 1278system.cpu.dcache.WriteReq_avg_miss_latency::total 39693.638678 # average WriteReq miss latency 1279system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14153.204830 # average LoadLockedReq miss latency 1280system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14153.204830 # average LoadLockedReq miss latency 1281system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 1282system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 1283system.cpu.dcache.demand_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency 1284system.cpu.dcache.demand_avg_miss_latency::total 31327.914673 # average overall miss latency 1285system.cpu.dcache.overall_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency 1286system.cpu.dcache.overall_avg_miss_latency::total 31327.914673 # average overall miss latency 1287system.cpu.dcache.blocked_cycles::no_mshrs 3032993 # number of cycles access was blocked | 1291system.cpu.dcache.demand_miss_rate::cpu.data 0.247424 # miss rate for demand accesses 1292system.cpu.dcache.demand_miss_rate::total 0.247424 # miss rate for demand accesses 1293system.cpu.dcache.overall_miss_rate::cpu.data 0.247424 # miss rate for overall accesses 1294system.cpu.dcache.overall_miss_rate::total 0.247424 # miss rate for overall accesses 1295system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22324.601467 # average ReadReq miss latency 1296system.cpu.dcache.ReadReq_avg_miss_latency::total 22324.601467 # average ReadReq miss latency 1297system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39738.379165 # average WriteReq miss latency 1298system.cpu.dcache.WriteReq_avg_miss_latency::total 39738.379165 # average WriteReq miss latency 1299system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14184.097150 # average LoadLockedReq miss latency 1300system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.097150 # average LoadLockedReq miss latency 1301system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency 1302system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency 1303system.cpu.dcache.demand_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency 1304system.cpu.dcache.demand_avg_miss_latency::total 31350.288727 # average overall miss latency 1305system.cpu.dcache.overall_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency 1306system.cpu.dcache.overall_avg_miss_latency::total 31350.288727 # average overall miss latency 1307system.cpu.dcache.blocked_cycles::no_mshrs 3041849 # number of cycles access was blocked |
| 1288system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked | 1308system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked |
| 1289system.cpu.dcache.blocked::no_mshrs 98350 # number of cycles access was blocked | 1309system.cpu.dcache.blocked::no_mshrs 98391 # number of cycles access was blocked |
| 1290system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked | 1310system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 1291system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.838770 # average number of cycles each access was blocked | 1311system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.915927 # average number of cycles each access was blocked |
| 1292system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked 1293system.cpu.dcache.fast_writes 0 # number of fast writes performed 1294system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1312system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked 1313system.cpu.dcache.fast_writes 0 # number of fast writes performed 1314system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1295system.cpu.dcache.writebacks::writebacks 840887 # number of writebacks 1296system.cpu.dcache.writebacks::total 840887 # number of writebacks 1297system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722519 # number of ReadReq MSHR hits 1298system.cpu.dcache.ReadReq_mshr_hits::total 722519 # number of ReadReq MSHR hits 1299system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643978 # number of WriteReq MSHR hits 1300system.cpu.dcache.WriteReq_mshr_hits::total 1643978 # number of WriteReq MSHR hits 1301system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5197 # number of LoadLockedReq MSHR hits 1302system.cpu.dcache.LoadLockedReq_mshr_hits::total 5197 # number of LoadLockedReq MSHR hits 1303system.cpu.dcache.demand_mshr_hits::cpu.data 2366497 # number of demand (read+write) MSHR hits 1304system.cpu.dcache.demand_mshr_hits::total 2366497 # number of demand (read+write) MSHR hits 1305system.cpu.dcache.overall_mshr_hits::cpu.data 2366497 # number of overall MSHR hits 1306system.cpu.dcache.overall_mshr_hits::total 2366497 # number of overall MSHR hits 1307system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084061 # number of ReadReq MSHR misses 1308system.cpu.dcache.ReadReq_mshr_misses::total 1084061 # number of ReadReq MSHR misses 1309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300460 # number of WriteReq MSHR misses 1310system.cpu.dcache.WriteReq_mshr_misses::total 300460 # number of WriteReq MSHR misses 1311system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17534 # number of LoadLockedReq MSHR misses 1312system.cpu.dcache.LoadLockedReq_mshr_misses::total 17534 # number of LoadLockedReq MSHR misses | 1315system.cpu.dcache.writebacks::writebacks 840743 # number of writebacks 1316system.cpu.dcache.writebacks::total 840743 # number of writebacks 1317system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722826 # number of ReadReq MSHR hits 1318system.cpu.dcache.ReadReq_mshr_hits::total 722826 # number of ReadReq MSHR hits 1319system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643736 # number of WriteReq MSHR hits 1320system.cpu.dcache.WriteReq_mshr_hits::total 1643736 # number of WriteReq MSHR hits 1321system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5220 # number of LoadLockedReq MSHR hits 1322system.cpu.dcache.LoadLockedReq_mshr_hits::total 5220 # number of LoadLockedReq MSHR hits 1323system.cpu.dcache.demand_mshr_hits::cpu.data 2366562 # number of demand (read+write) MSHR hits 1324system.cpu.dcache.demand_mshr_hits::total 2366562 # number of demand (read+write) MSHR hits 1325system.cpu.dcache.overall_mshr_hits::cpu.data 2366562 # number of overall MSHR hits 1326system.cpu.dcache.overall_mshr_hits::total 2366562 # number of overall MSHR hits 1327system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083964 # number of ReadReq MSHR misses 1328system.cpu.dcache.ReadReq_mshr_misses::total 1083964 # number of ReadReq MSHR misses 1329system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300392 # number of WriteReq MSHR misses 1330system.cpu.dcache.WriteReq_mshr_misses::total 300392 # number of WriteReq MSHR misses 1331system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17518 # number of LoadLockedReq MSHR misses 1332system.cpu.dcache.LoadLockedReq_mshr_misses::total 17518 # number of LoadLockedReq MSHR misses |
| 1313system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1314system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses | 1333system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1334system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses |
| 1315system.cpu.dcache.demand_mshr_misses::cpu.data 1384521 # number of demand (read+write) MSHR misses 1316system.cpu.dcache.demand_mshr_misses::total 1384521 # number of demand (read+write) MSHR misses 1317system.cpu.dcache.overall_mshr_misses::cpu.data 1384521 # number of overall MSHR misses 1318system.cpu.dcache.overall_mshr_misses::total 1384521 # number of overall MSHR misses 1319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27189046254 # number of ReadReq MSHR miss cycles 1320system.cpu.dcache.ReadReq_mshr_miss_latency::total 27189046254 # number of ReadReq MSHR miss cycles 1321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11757002855 # number of WriteReq MSHR miss cycles 1322system.cpu.dcache.WriteReq_mshr_miss_latency::total 11757002855 # number of WriteReq MSHR miss cycles 1323system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761751 # number of LoadLockedReq MSHR miss cycles 1324system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761751 # number of LoadLockedReq MSHR miss cycles 1325system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles 1326system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles 1327system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38946049109 # number of demand (read+write) MSHR miss cycles 1328system.cpu.dcache.demand_mshr_miss_latency::total 38946049109 # number of demand (read+write) MSHR miss cycles 1329system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38946049109 # number of overall MSHR miss cycles 1330system.cpu.dcache.overall_mshr_miss_latency::total 38946049109 # number of overall MSHR miss cycles 1331system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424137500 # number of ReadReq MSHR uncacheable cycles 1332system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424137500 # number of ReadReq MSHR uncacheable cycles 1333system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997802998 # number of WriteReq MSHR uncacheable cycles 1334system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997802998 # number of WriteReq MSHR uncacheable cycles 1335system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421940498 # number of overall MSHR uncacheable cycles 1336system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421940498 # number of overall MSHR uncacheable cycles 1337system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120227 # mshr miss rate for ReadReq accesses 1338system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120227 # mshr miss rate for ReadReq accesses 1339system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048873 # mshr miss rate for WriteReq accesses 1340system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048873 # mshr miss rate for WriteReq accesses | 1335system.cpu.dcache.demand_mshr_misses::cpu.data 1384356 # number of demand (read+write) MSHR misses 1336system.cpu.dcache.demand_mshr_misses::total 1384356 # number of demand (read+write) MSHR misses 1337system.cpu.dcache.overall_mshr_misses::cpu.data 1384356 # number of overall MSHR misses 1338system.cpu.dcache.overall_mshr_misses::total 1384356 # number of overall MSHR misses 1339system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27183263254 # number of ReadReq MSHR miss cycles 1340system.cpu.dcache.ReadReq_mshr_miss_latency::total 27183263254 # number of ReadReq MSHR miss cycles 1341system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11761438359 # number of WriteReq MSHR miss cycles 1342system.cpu.dcache.WriteReq_mshr_miss_latency::total 11761438359 # number of WriteReq MSHR miss cycles 1343system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200916999 # number of LoadLockedReq MSHR miss cycles 1344system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200916999 # number of LoadLockedReq MSHR miss cycles 1345system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34999 # number of StoreCondReq MSHR miss cycles 1346system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34999 # number of StoreCondReq MSHR miss cycles 1347system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38944701613 # number of demand (read+write) MSHR miss cycles 1348system.cpu.dcache.demand_mshr_miss_latency::total 38944701613 # number of demand (read+write) MSHR miss cycles 1349system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38944701613 # number of overall MSHR miss cycles 1350system.cpu.dcache.overall_mshr_miss_latency::total 38944701613 # number of overall MSHR miss cycles 1351system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424030000 # number of ReadReq MSHR uncacheable cycles 1352system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424030000 # number of ReadReq MSHR uncacheable cycles 1353system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997779498 # number of WriteReq MSHR uncacheable cycles 1354system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997779498 # number of WriteReq MSHR uncacheable cycles 1355system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421809498 # number of overall MSHR uncacheable cycles 1356system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421809498 # number of overall MSHR uncacheable cycles 1357system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120279 # mshr miss rate for ReadReq accesses 1358system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120279 # mshr miss rate for ReadReq accesses 1359system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048862 # mshr miss rate for WriteReq accesses 1360system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048862 # mshr miss rate for WriteReq accesses |
| 1341system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses 1342system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses 1343system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 1344system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses | 1361system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses 1362system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses 1363system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 1364system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses |
| 1345system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for demand accesses 1346system.cpu.dcache.demand_mshr_miss_rate::total 0.091300 # mshr miss rate for demand accesses 1347system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for overall accesses 1348system.cpu.dcache.overall_mshr_miss_rate::total 0.091300 # mshr miss rate for overall accesses 1349system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25080.734621 # average ReadReq mshr miss latency 1350system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25080.734621 # average ReadReq mshr miss latency 1351system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39130.010168 # average WriteReq mshr miss latency 1352system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39130.010168 # average WriteReq mshr miss latency 1353system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11449.854625 # average LoadLockedReq mshr miss latency 1354system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11449.854625 # average LoadLockedReq mshr miss latency 1355system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 1356system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 1357system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency 1358system.cpu.dcache.demand_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency 1359system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency 1360system.cpu.dcache.overall_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency | 1365system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for demand accesses 1366system.cpu.dcache.demand_mshr_miss_rate::total 0.091317 # mshr miss rate for demand accesses 1367system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for overall accesses 1368system.cpu.dcache.overall_mshr_miss_rate::total 0.091317 # mshr miss rate for overall accesses 1369system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25077.643957 # average ReadReq mshr miss latency 1370system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25077.643957 # average ReadReq mshr miss latency 1371system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39153.633782 # average WriteReq mshr miss latency 1372system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39153.633782 # average WriteReq mshr miss latency 1373system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11469.174506 # average LoadLockedReq mshr miss latency 1374system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11469.174506 # average LoadLockedReq mshr miss latency 1375system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency 1376system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency 1377system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency 1378system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency 1379system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency 1380system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency |
| 1361system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1362system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1363system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1364system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1365system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1366system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1367system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1368system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1381system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1382system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1383system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1384system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1385system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1386system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1387system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1388system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1369system.cpu.kern.inst.quiesce 6437 # number of quiesce instructions executed | 1389system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed |
| 1370system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed 1371system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl 1372system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1373system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1374system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl 1375system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl 1376system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1377system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1378system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1379system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1380system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl | 1390system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed 1391system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl 1392system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1393system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1394system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl 1395system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl 1396system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1397system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1398system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1399system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1400system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl |
| 1381system.cpu.kern.ipl_ticks::0 1818037303500 97.73% 97.73% # number of cycles we spent at this ipl 1382system.cpu.kern.ipl_ticks::21 64303500 0.00% 97.74% # number of cycles we spent at this ipl 1383system.cpu.kern.ipl_ticks::22 561270000 0.03% 97.77% # number of cycles we spent at this ipl 1384system.cpu.kern.ipl_ticks::31 41533903500 2.23% 100.00% # number of cycles we spent at this ipl 1385system.cpu.kern.ipl_ticks::total 1860196780500 # number of cycles we spent at this ipl | 1401system.cpu.kern.ipl_ticks::0 1818029044000 97.73% 97.73% # number of cycles we spent at this ipl 1402system.cpu.kern.ipl_ticks::21 64103000 0.00% 97.74% # number of cycles we spent at this ipl 1403system.cpu.kern.ipl_ticks::22 561251500 0.03% 97.77% # number of cycles we spent at this ipl 1404system.cpu.kern.ipl_ticks::31 41542545500 2.23% 100.00% # number of cycles we spent at this ipl 1405system.cpu.kern.ipl_ticks::total 1860196944000 # number of cycles we spent at this ipl |
| 1386system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl 1387system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1388system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1389system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl 1390system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl 1391system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1392system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1393system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed --- 47 unchanged lines hidden (view full) --- 1441system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches 1442system.cpu.kern.mode_good::kernel 1910 1443system.cpu.kern.mode_good::user 1740 1444system.cpu.kern.mode_good::idle 170 1445system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches 1446system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1447system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 1448system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches | 1406system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl 1407system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1408system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1409system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl 1410system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl 1411system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1412system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1413system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed --- 47 unchanged lines hidden (view full) --- 1461system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches 1462system.cpu.kern.mode_good::kernel 1910 1463system.cpu.kern.mode_good::user 1740 1464system.cpu.kern.mode_good::idle 170 1465system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches 1466system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1467system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 1468system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches |
| 1449system.cpu.kern.mode_ticks::kernel 29638597000 1.59% 1.59% # number of ticks spent at the given mode 1450system.cpu.kern.mode_ticks::user 2732860000 0.15% 1.74% # number of ticks spent at the given mode 1451system.cpu.kern.mode_ticks::idle 1827825315500 98.26% 100.00% # number of ticks spent at the given mode | 1469system.cpu.kern.mode_ticks::kernel 29636227500 1.59% 1.59% # number of ticks spent at the given mode 1470system.cpu.kern.mode_ticks::user 2736556500 0.15% 1.74% # number of ticks spent at the given mode 1471system.cpu.kern.mode_ticks::idle 1827824152000 98.26% 100.00% # number of ticks spent at the given mode |
| 1452system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1453 1454---------- End Simulation Statistics ---------- | 1472system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1473 1474---------- End Simulation Statistics ---------- |