| stats.txt (9312:e05e1b69ebf2) | stats.txt (9314:63e7cfff4188) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.854370 # Number of seconds simulated 4sim_ticks 1854370484500 # Number of ticks simulated 5final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.854370 # Number of seconds simulated 4sim_ticks 1854370484500 # Number of ticks simulated 5final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 94446 # Simulator instruction rate (inst/s) 8host_op_rate 94446 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3304859837 # Simulator tick rate (ticks/s) 10host_mem_usage 326668 # Number of bytes of host memory used 11host_seconds 561.10 # Real time elapsed on the host | 7host_inst_rate 120780 # Simulator instruction rate (inst/s) 8host_op_rate 120780 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4226353954 # Simulator tick rate (ticks/s) 10host_mem_usage 326684 # Number of bytes of host memory used 11host_seconds 438.76 # Real time elapsed on the host |
| 12sim_insts 52993965 # Number of instructions simulated 13sim_ops 52993965 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory --- 150 unchanged lines hidden (view full) --- 170system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 12sim_insts 52993965 # Number of instructions simulated 13sim_ops 52993965 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory --- 150 unchanged lines hidden (view full) --- 170system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 178system.physmem.totQLat 6175508423 # Total cycles spent in queuing delays 179system.physmem.totMemAccLat 13385774423 # Sum of mem lat for all requests | 178system.physmem.totQLat 6175504423 # Total cycles spent in queuing delays 179system.physmem.totMemAccLat 13385770423 # Sum of mem lat for all requests |
| 180system.physmem.totBusLat 1780884000 # Total cycles spent in databus access 181system.physmem.totBankLat 5429382000 # Total cycles spent in bank access | 180system.physmem.totBusLat 1780884000 # Total cycles spent in databus access 181system.physmem.totBankLat 5429382000 # Total cycles spent in bank access |
| 182system.physmem.avgQLat 13870.66 # Average queueing delay per request | 182system.physmem.avgQLat 13870.65 # Average queueing delay per request |
| 183system.physmem.avgBankLat 12194.80 # Average bank access latency per request 184system.physmem.avgBusLat 4000.00 # Average bus latency per request | 183system.physmem.avgBankLat 12194.80 # Average bank access latency per request 184system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 185system.physmem.avgMemAccLat 30065.46 # Average memory access latency | 185system.physmem.avgMemAccLat 30065.45 # Average memory access latency |
| 186system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s 187system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s 188system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s 189system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s 190system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 191system.physmem.busUtil 0.12 # Data bus utilization in percentage 192system.physmem.avgRdQLen 0.01 # Average read queue length over time 193system.physmem.avgWrQLen 10.01 # Average write queue length over time --- 150 unchanged lines hidden (view full) --- 344system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target. 345system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions. 346system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss 347system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed 348system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered 349system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken 350system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked 351system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing | 186system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s 187system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s 188system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s 189system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s 190system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 191system.physmem.busUtil 0.12 # Data bus utilization in percentage 192system.physmem.avgRdQLen 0.01 # Average read queue length over time 193system.physmem.avgWrQLen 10.01 # Average write queue length over time --- 150 unchanged lines hidden (view full) --- 344system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target. 345system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions. 346system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss 347system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed 348system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered 349system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken 350system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked 351system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing |
| 352system.cpu.fetch.BlockedCycles 37395096 # Number of cycles fetch has spent blocked | 352system.cpu.fetch.BlockedCycles 37395098 # Number of cycles fetch has spent blocked |
| 353system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 354system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps 355system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions 356system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR 357system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched 358system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed | 353system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 354system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps 355system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions 356system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR 357system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched 358system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed |
| 359system.cpu.fetch.rateDist::samples 81356871 # Number of instructions fetched each cycle (Total) | 359system.cpu.fetch.rateDist::samples 81356873 # Number of instructions fetched each cycle (Total) |
| 360system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 360system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 363system.cpu.fetch.rateDist::0 67855364 83.40% 83.40% # Number of instructions fetched each cycle (Total) | 363system.cpu.fetch.rateDist::0 67855366 83.40% 83.40% # Number of instructions fetched each cycle (Total) |
| 364system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 364system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 375system.cpu.fetch.rateDist::total 81356871 # Number of instructions fetched each cycle (Total) | 375system.cpu.fetch.rateDist::total 81356873 # Number of instructions fetched each cycle (Total) |
| 376system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle 377system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle 378system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle | 376system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle 377system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle 378system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle |
| 379system.cpu.decode.BlockedCycles 37116939 # Number of cycles decode is blocked | 379system.cpu.decode.BlockedCycles 37116941 # Number of cycles decode is blocked |
| 380system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running 381system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking 382system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing 383system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch 384system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction 385system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode 386system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode 387system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing 388system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle 389system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking | 380system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running 381system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking 382system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing 383system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch 384system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction 385system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode 386system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode 387system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing 388system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle 389system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking |
| 390system.cpu.rename.serializeStallCycles 19830183 # count of cycles rename stalled for serializing inst | 390system.cpu.rename.serializeStallCycles 19830185 # count of cycles rename stalled for serializing inst |
| 391system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running 392system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking 393system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename 394system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full 395system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full 396system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full 397system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed 398system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made --- 10 unchanged lines hidden (view full) --- 409system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores. 410system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec) 411system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ 412system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued 413system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued 414system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling 415system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph 416system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed | 391system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running 392system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking 393system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename 394system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full 395system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full 396system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full 397system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed 398system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made --- 10 unchanged lines hidden (view full) --- 409system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores. 410system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec) 411system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ 412system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued 413system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued 414system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling 415system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph 416system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed |
| 417system.cpu.iq.issued_per_cycle::samples 81356871 # Number of insts issued each cycle | 417system.cpu.iq.issued_per_cycle::samples 81356873 # Number of insts issued each cycle |
| 418system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 418system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 421system.cpu.iq.issued_per_cycle::0 56509821 69.46% 69.46% # Number of insts issued each cycle | 421system.cpu.iq.issued_per_cycle::0 56509823 69.46% 69.46% # Number of insts issued each cycle |
| 422system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 422system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 433system.cpu.iq.issued_per_cycle::total 81356871 # Number of insts issued each cycle | 433system.cpu.iq.issued_per_cycle::total 81356873 # Number of insts issued each cycle |
| 434system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available 436system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available 437system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 498system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued 499system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued 500system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued 501system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 502system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued 503system.cpu.iq.rate 0.522738 # Inst issue rate 504system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested 505system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) | 434system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available 436system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available 437system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 498system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued 499system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued 500system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued 501system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 502system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued 503system.cpu.iq.rate 0.522738 # Inst issue rate 504system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested 505system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) |
| 506system.cpu.iq.int_inst_queue_reads 195876832 # Number of integer instruction queue reads | 506system.cpu.iq.int_inst_queue_reads 195876834 # Number of integer instruction queue reads |
| 507system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes 508system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses 509system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads 510system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes 511system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses 512system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses 513system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses 514system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores --- 36 unchanged lines hidden (view full) --- 551system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value 552system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 553system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle 554system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back 555system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 556system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit 557system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards 558system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted | 507system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes 508system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses 509system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads 510system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes 511system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses 512system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses 513system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses 514system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores --- 36 unchanged lines hidden (view full) --- 551system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value 552system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 553system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle 554system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back 555system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 556system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit 557system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards 558system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted |
| 559system.cpu.commit.committed_per_cycle::samples 80002696 # Number of insts commited each cycle | 559system.cpu.commit.committed_per_cycle::samples 80002698 # Number of insts commited each cycle |
| 560system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 560system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 563system.cpu.commit.committed_per_cycle::0 59120918 73.90% 73.90% # Number of insts commited each cycle | 563system.cpu.commit.committed_per_cycle::0 59120920 73.90% 73.90% # Number of insts commited each cycle |
| 564system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 564system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 575system.cpu.commit.committed_per_cycle::total 80002696 # Number of insts commited each cycle | 575system.cpu.commit.committed_per_cycle::total 80002698 # Number of insts commited each cycle |
| 576system.cpu.commit.committedInsts 56184240 # Number of instructions committed 577system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed 578system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 579system.cpu.commit.refs 15475347 # Number of memory references committed 580system.cpu.commit.loads 9094466 # Number of loads committed 581system.cpu.commit.membars 226347 # Number of memory barriers committed 582system.cpu.commit.branches 8447798 # Number of branches committed 583system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 584system.cpu.commit.int_insts 52030338 # Number of committed integer instructions. 585system.cpu.commit.function_calls 740415 # Number of function calls committed. 586system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached 587system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 576system.cpu.commit.committedInsts 56184240 # Number of instructions committed 577system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed 578system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 579system.cpu.commit.refs 15475347 # Number of memory references committed 580system.cpu.commit.loads 9094466 # Number of loads committed 581system.cpu.commit.membars 226347 # Number of memory barriers committed 582system.cpu.commit.branches 8447798 # Number of branches committed 583system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 584system.cpu.commit.int_insts 52030338 # Number of committed integer instructions. 585system.cpu.commit.function_calls 740415 # Number of function calls committed. 586system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached 587system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 588system.cpu.rob.rob_reads 142220967 # The number of ROB reads | 588system.cpu.rob.rob_reads 142220969 # The number of ROB reads |
| 589system.cpu.rob.rob_writes 129940455 # The number of ROB writes 590system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself | 589system.cpu.rob.rob_writes 129940455 # The number of ROB writes 590system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 591system.cpu.idleCycles 27974649 # Total number of cycles that the CPU has spent unscheduled due to idling | 591system.cpu.idleCycles 27974647 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 592system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 593system.cpu.committedInsts 52993965 # Number of Instructions Simulated 594system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated 595system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated 596system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction 597system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads 598system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle 599system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads --- 148 unchanged lines hidden (view full) --- 748system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 749system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 750system.cpu.dcache.demand_misses::cpu.data 3743164 # number of demand (read+write) misses 751system.cpu.dcache.demand_misses::total 3743164 # number of demand (read+write) misses 752system.cpu.dcache.overall_misses::cpu.data 3743164 # number of overall misses 753system.cpu.dcache.overall_misses::total 3743164 # number of overall misses 754system.cpu.dcache.ReadReq_miss_latency::cpu.data 33852672500 # number of ReadReq miss cycles 755system.cpu.dcache.ReadReq_miss_latency::total 33852672500 # number of ReadReq miss cycles | 592system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 593system.cpu.committedInsts 52993965 # Number of Instructions Simulated 594system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated 595system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated 596system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction 597system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads 598system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle 599system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads --- 148 unchanged lines hidden (view full) --- 748system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 749system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 750system.cpu.dcache.demand_misses::cpu.data 3743164 # number of demand (read+write) misses 751system.cpu.dcache.demand_misses::total 3743164 # number of demand (read+write) misses 752system.cpu.dcache.overall_misses::cpu.data 3743164 # number of overall misses 753system.cpu.dcache.overall_misses::total 3743164 # number of overall misses 754system.cpu.dcache.ReadReq_miss_latency::cpu.data 33852672500 # number of ReadReq miss cycles 755system.cpu.dcache.ReadReq_miss_latency::total 33852672500 # number of ReadReq miss cycles |
| 756system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445086639 # number of WriteReq miss cycles 757system.cpu.dcache.WriteReq_miss_latency::total 70445086639 # number of WriteReq miss cycles | 756system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445061639 # number of WriteReq miss cycles 757system.cpu.dcache.WriteReq_miss_latency::total 70445061639 # number of WriteReq miss cycles |
| 758system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307962000 # number of LoadLockedReq miss cycles 759system.cpu.dcache.LoadLockedReq_miss_latency::total 307962000 # number of LoadLockedReq miss cycles 760system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38000 # number of StoreCondReq miss cycles 761system.cpu.dcache.StoreCondReq_miss_latency::total 38000 # number of StoreCondReq miss cycles | 758system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307962000 # number of LoadLockedReq miss cycles 759system.cpu.dcache.LoadLockedReq_miss_latency::total 307962000 # number of LoadLockedReq miss cycles 760system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38000 # number of StoreCondReq miss cycles 761system.cpu.dcache.StoreCondReq_miss_latency::total 38000 # number of StoreCondReq miss cycles |
| 762system.cpu.dcache.demand_miss_latency::cpu.data 104297759139 # number of demand (read+write) miss cycles 763system.cpu.dcache.demand_miss_latency::total 104297759139 # number of demand (read+write) miss cycles 764system.cpu.dcache.overall_miss_latency::cpu.data 104297759139 # number of overall miss cycles 765system.cpu.dcache.overall_miss_latency::total 104297759139 # number of overall miss cycles | 762system.cpu.dcache.demand_miss_latency::cpu.data 104297734139 # number of demand (read+write) miss cycles 763system.cpu.dcache.demand_miss_latency::total 104297734139 # number of demand (read+write) miss cycles 764system.cpu.dcache.overall_miss_latency::cpu.data 104297734139 # number of overall miss cycles 765system.cpu.dcache.overall_miss_latency::total 104297734139 # number of overall miss cycles |
| 766system.cpu.dcache.ReadReq_accesses::cpu.data 9066164 # number of ReadReq accesses(hits+misses) 767system.cpu.dcache.ReadReq_accesses::total 9066164 # number of ReadReq accesses(hits+misses) 768system.cpu.dcache.WriteReq_accesses::cpu.data 6146625 # number of WriteReq accesses(hits+misses) 769system.cpu.dcache.WriteReq_accesses::total 6146625 # number of WriteReq accesses(hits+misses) 770system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213241 # number of LoadLockedReq accesses(hits+misses) 771system.cpu.dcache.LoadLockedReq_accesses::total 213241 # number of LoadLockedReq accesses(hits+misses) 772system.cpu.dcache.StoreCondReq_accesses::cpu.data 219554 # number of StoreCondReq accesses(hits+misses) 773system.cpu.dcache.StoreCondReq_accesses::total 219554 # number of StoreCondReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 784system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 785system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 786system.cpu.dcache.demand_miss_rate::cpu.data 0.246054 # miss rate for demand accesses 787system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses 788system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses 789system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses 790system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency 791system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency | 766system.cpu.dcache.ReadReq_accesses::cpu.data 9066164 # number of ReadReq accesses(hits+misses) 767system.cpu.dcache.ReadReq_accesses::total 9066164 # number of ReadReq accesses(hits+misses) 768system.cpu.dcache.WriteReq_accesses::cpu.data 6146625 # number of WriteReq accesses(hits+misses) 769system.cpu.dcache.WriteReq_accesses::total 6146625 # number of WriteReq accesses(hits+misses) 770system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213241 # number of LoadLockedReq accesses(hits+misses) 771system.cpu.dcache.LoadLockedReq_accesses::total 213241 # number of LoadLockedReq accesses(hits+misses) 772system.cpu.dcache.StoreCondReq_accesses::cpu.data 219554 # number of StoreCondReq accesses(hits+misses) 773system.cpu.dcache.StoreCondReq_accesses::total 219554 # number of StoreCondReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 784system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 785system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 786system.cpu.dcache.demand_miss_rate::cpu.data 0.246054 # miss rate for demand accesses 787system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses 788system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses 789system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses 790system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency 791system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency |
| 792system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.547949 # average WriteReq miss latency 793system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.547949 # average WriteReq miss latency | 792system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.535074 # average WriteReq miss latency 793system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.535074 # average WriteReq miss latency |
| 794system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency 795system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency 796system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency 797system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency | 794system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency 795system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency 796system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency 797system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency |
| 798system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency 799system.cpu.dcache.demand_avg_miss_latency::total 27863.529126 # average overall miss latency 800system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency 801system.cpu.dcache.overall_avg_miss_latency::total 27863.529126 # average overall miss latency 802system.cpu.dcache.blocked_cycles::no_mshrs 2571682 # number of cycles access was blocked | 798system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency 799system.cpu.dcache.demand_avg_miss_latency::total 27863.522448 # average overall miss latency 800system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency 801system.cpu.dcache.overall_avg_miss_latency::total 27863.522448 # average overall miss latency 802system.cpu.dcache.blocked_cycles::no_mshrs 2571680 # number of cycles access was blocked |
| 803system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked 804system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked 805system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked | 803system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked 804system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked 805system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 806system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946948 # average number of cycles each access was blocked | 806system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946927 # average number of cycles each access was blocked |
| 807system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked 808system.cpu.dcache.fast_writes 0 # number of fast writes performed 809system.cpu.dcache.cache_copies 0 # number of cache copies performed 810system.cpu.dcache.writebacks::writebacks 841139 # number of writebacks 811system.cpu.dcache.writebacks::total 841139 # number of writebacks 812system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716695 # number of ReadReq MSHR hits 813system.cpu.dcache.ReadReq_mshr_hits::total 716695 # number of ReadReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1641513 # number of WriteReq MSHR hits --- 13 unchanged lines hidden (view full) --- 828system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 829system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 830system.cpu.dcache.demand_mshr_misses::cpu.data 1384956 # number of demand (read+write) MSHR misses 831system.cpu.dcache.demand_mshr_misses::total 1384956 # number of demand (read+write) MSHR misses 832system.cpu.dcache.overall_mshr_misses::cpu.data 1384956 # number of overall MSHR misses 833system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses 834system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles 835system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles | 807system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked 808system.cpu.dcache.fast_writes 0 # number of fast writes performed 809system.cpu.dcache.cache_copies 0 # number of cache copies performed 810system.cpu.dcache.writebacks::writebacks 841139 # number of writebacks 811system.cpu.dcache.writebacks::total 841139 # number of writebacks 812system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716695 # number of ReadReq MSHR hits 813system.cpu.dcache.ReadReq_mshr_hits::total 716695 # number of ReadReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1641513 # number of WriteReq MSHR hits --- 13 unchanged lines hidden (view full) --- 828system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 829system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 830system.cpu.dcache.demand_mshr_misses::cpu.data 1384956 # number of demand (read+write) MSHR misses 831system.cpu.dcache.demand_mshr_misses::total 1384956 # number of demand (read+write) MSHR misses 832system.cpu.dcache.overall_mshr_misses::cpu.data 1384956 # number of overall MSHR misses 833system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses 834system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles 835system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles |
| 836system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712390769 # number of WriteReq MSHR miss cycles 837system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712390769 # number of WriteReq MSHR miss cycles | 836system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712386769 # number of WriteReq MSHR miss cycles 837system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712386769 # number of WriteReq MSHR miss cycles |
| 838system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles 839system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles 840system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles 841system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles | 838system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles 839system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles 840system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles 841system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles |
| 842system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907863269 # number of demand (read+write) MSHR miss cycles 843system.cpu.dcache.demand_mshr_miss_latency::total 31907863269 # number of demand (read+write) MSHR miss cycles 844system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907863269 # number of overall MSHR miss cycles 845system.cpu.dcache.overall_mshr_miss_latency::total 31907863269 # number of overall MSHR miss cycles | 842system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907859269 # number of demand (read+write) MSHR miss cycles 843system.cpu.dcache.demand_mshr_miss_latency::total 31907859269 # number of demand (read+write) MSHR miss cycles 844system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907859269 # number of overall MSHR miss cycles 845system.cpu.dcache.overall_mshr_miss_latency::total 31907859269 # number of overall MSHR miss cycles |
| 846system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles 847system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles | 846system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles 847system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles |
| 848system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997718998 # number of WriteReq MSHR uncacheable cycles 849system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997718998 # number of WriteReq MSHR uncacheable cycles 850system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421626998 # number of overall MSHR uncacheable cycles 851system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421626998 # number of overall MSHR uncacheable cycles | 848system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997720998 # number of WriteReq MSHR uncacheable cycles 849system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997720998 # number of WriteReq MSHR uncacheable cycles 850system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421628998 # number of overall MSHR uncacheable cycles 851system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421628998 # number of overall MSHR uncacheable cycles |
| 852system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048843 # mshr miss rate for WriteReq accesses 856system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084177 # mshr miss rate for LoadLockedReq accesses 857system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084177 # mshr miss rate for LoadLockedReq accesses 858system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 859system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 860system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for demand accesses 861system.cpu.dcache.demand_mshr_miss_rate::total 0.091039 # mshr miss rate for demand accesses 862system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for overall accesses 863system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency 865system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency | 852system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048843 # mshr miss rate for WriteReq accesses 856system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084177 # mshr miss rate for LoadLockedReq accesses 857system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084177 # mshr miss rate for LoadLockedReq accesses 858system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 859system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 860system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for demand accesses 861system.cpu.dcache.demand_mshr_miss_rate::total 0.091039 # mshr miss rate for demand accesses 862system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for overall accesses 863system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency 865system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency |
| 866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.159135 # average WriteReq mshr miss latency 867system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.159135 # average WriteReq mshr miss latency | 866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.145811 # average WriteReq mshr miss latency 867system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.145811 # average WriteReq mshr miss latency |
| 868system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency 869system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency 870system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency 871system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency | 868system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency 869system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency 870system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency 871system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency |
| 872system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency 873system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency 874system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency 875system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency | 872system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency 873system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency 874system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency 875system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency |
| 876system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 877system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 878system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 879system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 880system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 881system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 882system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 883system.cpu.l2cache.replacements 338360 # number of replacements 884system.cpu.l2cache.tagsinuse 65364.997376 # Cycle average of tags in use 885system.cpu.l2cache.total_refs 2558215 # Total number of references to valid blocks. 886system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks. 887system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks. 888system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit. | 876system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 877system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 878system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 879system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 880system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 881system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 882system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 883system.cpu.l2cache.replacements 338360 # number of replacements 884system.cpu.l2cache.tagsinuse 65364.997376 # Cycle average of tags in use 885system.cpu.l2cache.total_refs 2558215 # Total number of references to valid blocks. 886system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks. 887system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks. 888system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit. |
| 889system.cpu.l2cache.occ_blocks::writebacks 53963.120653 # Average occupied blocks per requestor | 889system.cpu.l2cache.occ_blocks::writebacks 53963.120652 # Average occupied blocks per requestor |
| 890system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor 891system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor 892system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy 893system.cpu.l2cache.occ_percent::cpu.inst 0.081638 # Average percentage of cache occupancy 894system.cpu.l2cache.occ_percent::cpu.data 0.092341 # Average percentage of cache occupancy 895system.cpu.l2cache.occ_percent::total 0.997391 # Average percentage of cache occupancy 896system.cpu.l2cache.ReadReq_hits::cpu.inst 1005648 # number of ReadReq hits 897system.cpu.l2cache.ReadReq_hits::cpu.data 828171 # number of ReadReq hits --- 27 unchanged lines hidden (view full) --- 925system.cpu.l2cache.overall_misses::cpu.inst 15144 # number of overall misses 926system.cpu.l2cache.overall_misses::cpu.data 389186 # number of overall misses 927system.cpu.l2cache.overall_misses::total 404330 # number of overall misses 928system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 916217000 # number of ReadReq miss cycles 929system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11804091500 # number of ReadReq miss cycles 930system.cpu.l2cache.ReadReq_miss_latency::total 12720308500 # number of ReadReq miss cycles 931system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles 932system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles | 890system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor 891system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor 892system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy 893system.cpu.l2cache.occ_percent::cpu.inst 0.081638 # Average percentage of cache occupancy 894system.cpu.l2cache.occ_percent::cpu.data 0.092341 # Average percentage of cache occupancy 895system.cpu.l2cache.occ_percent::total 0.997391 # Average percentage of cache occupancy 896system.cpu.l2cache.ReadReq_hits::cpu.inst 1005648 # number of ReadReq hits 897system.cpu.l2cache.ReadReq_hits::cpu.data 828171 # number of ReadReq hits --- 27 unchanged lines hidden (view full) --- 925system.cpu.l2cache.overall_misses::cpu.inst 15144 # number of overall misses 926system.cpu.l2cache.overall_misses::cpu.data 389186 # number of overall misses 927system.cpu.l2cache.overall_misses::total 404330 # number of overall misses 928system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 916217000 # number of ReadReq miss cycles 929system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11804091500 # number of ReadReq miss cycles 930system.cpu.l2cache.ReadReq_miss_latency::total 12720308500 # number of ReadReq miss cycles 931system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles 932system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles |
| 933system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496192000 # number of ReadExReq miss cycles 934system.cpu.l2cache.ReadExReq_miss_latency::total 8496192000 # number of ReadExReq miss cycles | 933system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496188000 # number of ReadExReq miss cycles 934system.cpu.l2cache.ReadExReq_miss_latency::total 8496188000 # number of ReadExReq miss cycles |
| 935system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles | 935system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles |
| 936system.cpu.l2cache.demand_miss_latency::cpu.data 20300283500 # number of demand (read+write) miss cycles 937system.cpu.l2cache.demand_miss_latency::total 21216500500 # number of demand (read+write) miss cycles | 936system.cpu.l2cache.demand_miss_latency::cpu.data 20300279500 # number of demand (read+write) miss cycles 937system.cpu.l2cache.demand_miss_latency::total 21216496500 # number of demand (read+write) miss cycles |
| 938system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles | 938system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles |
| 939system.cpu.l2cache.overall_miss_latency::cpu.data 20300283500 # number of overall miss cycles 940system.cpu.l2cache.overall_miss_latency::total 21216500500 # number of overall miss cycles | 939system.cpu.l2cache.overall_miss_latency::cpu.data 20300279500 # number of overall miss cycles 940system.cpu.l2cache.overall_miss_latency::total 21216496500 # number of overall miss cycles |
| 941system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses) 942system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses) 943system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses) 944system.cpu.l2cache.Writeback_accesses::writebacks 841139 # number of Writeback accesses(hits+misses) 945system.cpu.l2cache.Writeback_accesses::total 841139 # number of Writeback accesses(hits+misses) 946system.cpu.l2cache.UpgradeReq_accesses::cpu.data 67 # number of UpgradeReq accesses(hits+misses) 947system.cpu.l2cache.UpgradeReq_accesses::total 67 # number of UpgradeReq accesses(hits+misses) 948system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) --- 21 unchanged lines hidden (view full) --- 970system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014836 # miss rate for overall accesses 971system.cpu.l2cache.overall_miss_rate::cpu.data 0.277427 # miss rate for overall accesses 972system.cpu.l2cache.overall_miss_rate::total 0.166828 # miss rate for overall accesses 973system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60500.330164 # average ReadReq miss latency 974system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43102.806554 # average ReadReq miss latency 975system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency 976system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency 977system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency | 941system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses) 942system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses) 943system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses) 944system.cpu.l2cache.Writeback_accesses::writebacks 841139 # number of Writeback accesses(hits+misses) 945system.cpu.l2cache.Writeback_accesses::total 841139 # number of Writeback accesses(hits+misses) 946system.cpu.l2cache.UpgradeReq_accesses::cpu.data 67 # number of UpgradeReq accesses(hits+misses) 947system.cpu.l2cache.UpgradeReq_accesses::total 67 # number of UpgradeReq accesses(hits+misses) 948system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) --- 21 unchanged lines hidden (view full) --- 970system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014836 # miss rate for overall accesses 971system.cpu.l2cache.overall_miss_rate::cpu.data 0.277427 # miss rate for overall accesses 972system.cpu.l2cache.overall_miss_rate::total 0.166828 # miss rate for overall accesses 973system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60500.330164 # average ReadReq miss latency 974system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43102.806554 # average ReadReq miss latency 975system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency 976system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency 977system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency |
| 978system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.450111 # average ReadExReq miss latency 979system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.450111 # average ReadExReq miss latency | 978system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.415427 # average ReadExReq miss latency 979system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.415427 # average ReadExReq miss latency |
| 980system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency | 980system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency |
| 981system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency 982system.cpu.l2cache.demand_avg_miss_latency::total 52473.228551 # average overall miss latency | 981system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency 982system.cpu.l2cache.demand_avg_miss_latency::total 52473.218658 # average overall miss latency |
| 983system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency | 983system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency |
| 984system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency 985system.cpu.l2cache.overall_avg_miss_latency::total 52473.228551 # average overall miss latency | 984system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency 985system.cpu.l2cache.overall_avg_miss_latency::total 52473.218658 # average overall miss latency |
| 986system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 987system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 988system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 989system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 990system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 991system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 992system.cpu.l2cache.fast_writes 0 # number of fast writes performed 993system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 22 unchanged lines hidden (view full) --- 1016system.cpu.l2cache.overall_mshr_misses::total 404329 # number of overall MSHR misses 1017system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles 1018system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles 1019system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles 1020system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles 1021system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles 1022system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles 1023system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles | 986system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 987system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 988system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 989system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 990system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 991system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 992system.cpu.l2cache.fast_writes 0 # number of fast writes performed 993system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 22 unchanged lines hidden (view full) --- 1016system.cpu.l2cache.overall_mshr_misses::total 404329 # number of overall MSHR misses 1017system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles 1018system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles 1019system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles 1020system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles 1021system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles 1022system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles 1023system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles |
| 1024system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067951103 # number of ReadExReq MSHR miss cycles 1025system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067951103 # number of ReadExReq MSHR miss cycles | 1024system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067947103 # number of ReadExReq MSHR miss cycles 1025system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067947103 # number of ReadExReq MSHR miss cycles |
| 1026system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles | 1026system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles |
| 1027system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327873464 # number of demand (read+write) MSHR miss cycles 1028system.cpu.l2cache.demand_mshr_miss_latency::total 16052895904 # number of demand (read+write) MSHR miss cycles | 1027system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327869464 # number of demand (read+write) MSHR miss cycles 1028system.cpu.l2cache.demand_mshr_miss_latency::total 16052891904 # number of demand (read+write) MSHR miss cycles |
| 1029system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles | 1029system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles |
| 1030system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327873464 # number of overall MSHR miss cycles 1031system.cpu.l2cache.overall_mshr_miss_latency::total 16052895904 # number of overall MSHR miss cycles 1032system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331389500 # number of ReadReq MSHR uncacheable cycles 1033system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331389500 # number of ReadReq MSHR uncacheable cycles 1034system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1881061000 # number of WriteReq MSHR uncacheable cycles 1035system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1881061000 # number of WriteReq MSHR uncacheable cycles 1036system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212450500 # number of overall MSHR uncacheable cycles 1037system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212450500 # number of overall MSHR uncacheable cycles | 1030system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327869464 # number of overall MSHR miss cycles 1031system.cpu.l2cache.overall_mshr_miss_latency::total 16052891904 # number of overall MSHR miss cycles 1032system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333831000 # number of ReadReq MSHR uncacheable cycles 1033system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333831000 # number of ReadReq MSHR uncacheable cycles 1034system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882540500 # number of WriteReq MSHR uncacheable cycles 1035system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882540500 # number of WriteReq MSHR uncacheable cycles 1036system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216371500 # number of overall MSHR uncacheable cycles 1037system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216371500 # number of overall MSHR uncacheable cycles |
| 1038system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses 1039system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses 1040system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses 1041system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses 1042system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses 1043system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 1044system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses 1045system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses --- 6 unchanged lines hidden (view full) --- 1052system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses 1053system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency 1054system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency 1055system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency 1056system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency 1057system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency 1058system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1059system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 1038system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses 1039system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses 1040system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses 1041system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses 1042system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses 1043system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 1044system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses 1045system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses --- 6 unchanged lines hidden (view full) --- 1052system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses 1053system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency 1054system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency 1055system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency 1056system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency 1057system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency 1058system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1059system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 1060system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.178458 # average ReadExReq mshr miss latency 1061system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.178458 # average ReadExReq mshr miss latency | 1060system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.143774 # average ReadExReq mshr miss latency 1061system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.143774 # average ReadExReq mshr miss latency |
| 1062system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency | 1062system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency |
| 1063system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency 1064system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency | 1063system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency 1064system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency |
| 1065system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency | 1065system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency |
| 1066system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency 1067system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency | 1066system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency 1067system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency |
| 1068system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1069system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1070system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1071system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1072system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1073system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1074system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1075system.cpu.kern.inst.arm 0 # number of arm instructions executed --- 86 unchanged lines hidden --- | 1068system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1069system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1070system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1071system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1072system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1073system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1074system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1075system.cpu.kern.inst.arm 0 # number of arm instructions executed --- 86 unchanged lines hidden --- |