| stats.txt (9289:a31a1243a3ed) | stats.txt (9312:e05e1b69ebf2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.855236 # Number of seconds simulated 4sim_ticks 1855236450500 # Number of ticks simulated 5final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.854370 # Number of seconds simulated 4sim_ticks 1854370484500 # Number of ticks simulated 5final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 182093 # Simulator instruction rate (inst/s) 8host_op_rate 182093 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6374280472 # Simulator tick rate (ticks/s) 10host_mem_usage 298212 # Number of bytes of host memory used 11host_seconds 291.05 # Real time elapsed on the host 12sim_insts 52998368 # Number of instructions simulated 13sim_ops 52998368 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7522688 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 445360 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117542 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 94446 # Simulator instruction rate (inst/s) 8host_op_rate 94446 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3304859837 # Simulator tick rate (ticks/s) 10host_mem_usage 326668 # Number of bytes of host memory used 11host_seconds 561.10 # Real time elapsed on the host 12sim_insts 52993965 # Number of instructions simulated 13sim_ops 52993965 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7507712 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7507712 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388692 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 445277 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117308 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117308 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 522597 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13414950 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1430325 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15367872 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 522597 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 522597 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4048658 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4048658 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4048658 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 522597 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13414950 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1430325 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19416530 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 445277 # Total number of read requests seen 42system.physmem.writeReqs 117308 # Total number of write requests seen 43system.physmem.cpureqs 564090 # Reqs generatd by CPU via cache - shady 44system.physmem.bytesRead 28497728 # Total number of bytes read from memory 45system.physmem.bytesWritten 7507712 # Total number of bytes written to memory 46system.physmem.bytesConsumedRd 28497728 # bytesRead derated as per pkt->getSize() 47system.physmem.bytesConsumedWr 7507712 # bytesWritten derated as per pkt->getSize() 48system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q 49system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed 50system.physmem.perBankRdReqs::0 28080 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::1 27611 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::2 27911 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::3 27629 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::4 28123 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::5 28001 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::6 27963 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::7 27770 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::8 27692 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::9 27278 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::10 27918 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::11 28145 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::13 27747 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::14 27834 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::15 27734 # Track reads on a per bank basis 66system.physmem.perBankWrReqs::0 7584 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::2 7291 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::3 7101 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::4 7583 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::5 7405 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::6 7380 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::7 7215 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::8 7260 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::9 6854 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::10 7428 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::11 7671 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::12 7427 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::13 7350 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::14 7315 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::15 7174 # Track writes on a per bank basis 82system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 83system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry 84system.physmem.totGap 1854365055000 # Total gap between requests 85system.physmem.readPktSize::0 0 # Categorize read packet sizes 86system.physmem.readPktSize::1 0 # Categorize read packet sizes 87system.physmem.readPktSize::2 0 # Categorize read packet sizes 88system.physmem.readPktSize::3 0 # Categorize read packet sizes 89system.physmem.readPktSize::4 0 # Categorize read packet sizes 90system.physmem.readPktSize::5 0 # Categorize read packet sizes 91system.physmem.readPktSize::6 445277 # Categorize read packet sizes 92system.physmem.readPktSize::7 0 # Categorize read packet sizes 93system.physmem.readPktSize::8 0 # Categorize read packet sizes 94system.physmem.writePktSize::0 0 # categorize write packet sizes 95system.physmem.writePktSize::1 0 # categorize write packet sizes 96system.physmem.writePktSize::2 0 # categorize write packet sizes 97system.physmem.writePktSize::3 0 # categorize write packet sizes 98system.physmem.writePktSize::4 0 # categorize write packet sizes 99system.physmem.writePktSize::5 0 # categorize write packet sizes 100system.physmem.writePktSize::6 118080 # categorize write packet sizes 101system.physmem.writePktSize::7 0 # categorize write packet sizes 102system.physmem.writePktSize::8 0 # categorize write packet sizes 103system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 106system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 108system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 109system.physmem.neitherpktsize::6 175 # categorize neither packet sizes 110system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 111system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 112system.physmem.rdQLenPdf::0 331917 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 65103 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 18248 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 6337 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 2872 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 2456 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 1809 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 2035 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 1684 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 1980 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 1575 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 1648 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 1261 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 1518 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 936 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 252 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 140 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 145system.physmem.wrQLenPdf::0 3912 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::1 4841 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::2 4917 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::3 4965 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::4 5049 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::5 5061 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::6 5094 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::7 5094 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::8 5093 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::9 5100 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::10 5100 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::11 5100 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::12 5100 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::13 5100 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::14 5100 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::15 5100 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::16 5100 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::17 5100 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::18 5100 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::19 5100 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::20 5100 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::23 1189 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::24 260 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 178system.physmem.totQLat 6175508423 # Total cycles spent in queuing delays 179system.physmem.totMemAccLat 13385774423 # Sum of mem lat for all requests 180system.physmem.totBusLat 1780884000 # Total cycles spent in databus access 181system.physmem.totBankLat 5429382000 # Total cycles spent in bank access 182system.physmem.avgQLat 13870.66 # Average queueing delay per request 183system.physmem.avgBankLat 12194.80 # Average bank access latency per request 184system.physmem.avgBusLat 4000.00 # Average bus latency per request 185system.physmem.avgMemAccLat 30065.46 # Average memory access latency 186system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s 187system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s 188system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s 189system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s 190system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 191system.physmem.busUtil 0.12 # Data bus utilization in percentage 192system.physmem.avgRdQLen 0.01 # Average read queue length over time 193system.physmem.avgWrQLen 10.01 # Average write queue length over time 194system.physmem.readRowHits 425232 # Number of row buffer hits during reads 195system.physmem.writeRowHits 76485 # Number of row buffer hits during writes 196system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads 197system.physmem.writeRowHitRate 65.20 # Row buffer hit rate for writes 198system.physmem.avgGap 3296150.90 # Average gap between requests |
| 41system.iocache.replacements 41685 # number of replacements | 199system.iocache.replacements 41685 # number of replacements |
| 42system.iocache.tagsinuse 1.255779 # Cycle average of tags in use | 200system.iocache.tagsinuse 1.265505 # Cycle average of tags in use |
| 43system.iocache.total_refs 0 # Total number of references to valid blocks. 44system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 45system.iocache.avg_refs 0 # Average number of references to valid blocks. | 201system.iocache.total_refs 0 # Total number of references to valid blocks. 202system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 203system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 46system.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit. 47system.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor 48system.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy 49system.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy | 204system.iocache.warmup_cycle 1704471567000 # Cycle when the warmup percentage was hit. 205system.iocache.occ_blocks::tsunami.ide 1.265505 # Average occupied blocks per requestor 206system.iocache.occ_percent::tsunami.ide 0.079094 # Average percentage of cache occupancy 207system.iocache.occ_percent::total 0.079094 # Average percentage of cache occupancy |
| 50system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 51system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 52system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 53system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 54system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 55system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 56system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 57system.iocache.overall_misses::total 41725 # number of overall misses | 208system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 209system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 210system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 211system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 212system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 213system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 214system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 215system.iocache.overall_misses::total 41725 # number of overall misses |
| 58system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 59system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles 60system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles 61system.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles 62system.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles 63system.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles 64system.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles 65system.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles | 216system.iocache.ReadReq_miss_latency::tsunami.ide 20930998 # number of ReadReq miss cycles 217system.iocache.ReadReq_miss_latency::total 20930998 # number of ReadReq miss cycles 218system.iocache.WriteReq_miss_latency::tsunami.ide 9501230806 # number of WriteReq miss cycles 219system.iocache.WriteReq_miss_latency::total 9501230806 # number of WriteReq miss cycles 220system.iocache.demand_miss_latency::tsunami.ide 9522161804 # number of demand (read+write) miss cycles 221system.iocache.demand_miss_latency::total 9522161804 # number of demand (read+write) miss cycles 222system.iocache.overall_miss_latency::tsunami.ide 9522161804 # number of overall miss cycles 223system.iocache.overall_miss_latency::total 9522161804 # number of overall miss cycles |
| 66system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 67system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 68system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 69system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 70system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 71system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 72system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 73system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 74system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 75system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 76system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 77system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 78system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 79system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 80system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 81system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 224system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 225system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 226system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 227system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 228system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 229system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 230system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 231system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 232system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 233system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 234system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 235system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 236system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 237system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 238system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 239system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 82system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 83system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency 84system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency 85system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency 86system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency 87system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency 88system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency 89system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency 90system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked | 240system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120988.427746 # average ReadReq miss latency 241system.iocache.ReadReq_avg_miss_latency::total 120988.427746 # average ReadReq miss latency 242system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228658.808385 # average WriteReq miss latency 243system.iocache.WriteReq_avg_miss_latency::total 228658.808385 # average WriteReq miss latency 244system.iocache.demand_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency 245system.iocache.demand_avg_miss_latency::total 228212.385956 # average overall miss latency 246system.iocache.overall_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency 247system.iocache.overall_avg_miss_latency::total 228212.385956 # average overall miss latency 248system.iocache.blocked_cycles::no_mshrs 190847 # number of cycles access was blocked |
| 91system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 249system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 92system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked | 250system.iocache.blocked::no_mshrs 22837 # number of cycles access was blocked |
| 93system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 251system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 94system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked | 252system.iocache.avg_blocked_cycles::no_mshrs 8.356921 # average number of cycles each access was blocked |
| 95system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96system.iocache.fast_writes 0 # number of fast writes performed 97system.iocache.cache_copies 0 # number of cache copies performed 98system.iocache.writebacks::writebacks 41512 # number of writebacks 99system.iocache.writebacks::total 41512 # number of writebacks 100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 102system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 103system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 104system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 105system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 106system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 107system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 253system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 254system.iocache.fast_writes 0 # number of fast writes performed 255system.iocache.cache_copies 0 # number of cache copies performed 256system.iocache.writebacks::writebacks 41512 # number of writebacks 257system.iocache.writebacks::total 41512 # number of writebacks 258system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 259system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 260system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 261system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 262system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 263system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 264system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 265system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles 109system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles 110system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles 111system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles 112system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles 113system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles 114system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles 115system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles | 266system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11934000 # number of ReadReq MSHR miss cycles 267system.iocache.ReadReq_mshr_miss_latency::total 11934000 # number of ReadReq MSHR miss cycles 268system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338470481 # number of WriteReq MSHR miss cycles 269system.iocache.WriteReq_mshr_miss_latency::total 7338470481 # number of WriteReq MSHR miss cycles 270system.iocache.demand_mshr_miss_latency::tsunami.ide 7350404481 # number of demand (read+write) MSHR miss cycles 271system.iocache.demand_mshr_miss_latency::total 7350404481 # number of demand (read+write) MSHR miss cycles 272system.iocache.overall_mshr_miss_latency::tsunami.ide 7350404481 # number of overall MSHR miss cycles 273system.iocache.overall_mshr_miss_latency::total 7350404481 # number of overall MSHR miss cycles |
| 116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 118system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 119system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 274system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 275system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 276system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 277system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 278system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 279system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 280system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 281system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency 125system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency 126system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency 127system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency 128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency 129system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency 130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency 131system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency | 282system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68982.658960 # average ReadReq mshr miss latency 283system.iocache.ReadReq_avg_mshr_miss_latency::total 68982.658960 # average ReadReq mshr miss latency 284system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176609.320394 # average WriteReq mshr miss latency 285system.iocache.WriteReq_avg_mshr_miss_latency::total 176609.320394 # average WriteReq mshr miss latency 286system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency 287system.iocache.demand_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency 288system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency 289system.iocache.overall_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency |
| 132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 133system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 134system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 135system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 136system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 137system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 138system.disk0.dma_write_txs 395 # Number of DMA write transactions. 139system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 140system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 141system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 142system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 143system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 144system.disk2.dma_write_txs 1 # Number of DMA write transactions. 145system.cpu.dtb.fetch_hits 0 # ITB hits 146system.cpu.dtb.fetch_misses 0 # ITB misses 147system.cpu.dtb.fetch_acv 0 # ITB acv 148system.cpu.dtb.fetch_accesses 0 # ITB accesses | 290system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 291system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 292system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 293system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 294system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 295system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 296system.disk0.dma_write_txs 395 # Number of DMA write transactions. 297system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 298system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 299system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 300system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 301system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 302system.disk2.dma_write_txs 1 # Number of DMA write transactions. 303system.cpu.dtb.fetch_hits 0 # ITB hits 304system.cpu.dtb.fetch_misses 0 # ITB misses 305system.cpu.dtb.fetch_acv 0 # ITB acv 306system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 149system.cpu.dtb.read_hits 9942716 # DTB read hits 150system.cpu.dtb.read_misses 44791 # DTB read misses 151system.cpu.dtb.read_acv 565 # DTB read access violations 152system.cpu.dtb.read_accesses 947396 # DTB read accesses 153system.cpu.dtb.write_hits 6623666 # DTB write hits 154system.cpu.dtb.write_misses 10259 # DTB write misses 155system.cpu.dtb.write_acv 393 # DTB write access violations 156system.cpu.dtb.write_accesses 338396 # DTB write accesses 157system.cpu.dtb.data_hits 16566382 # DTB hits 158system.cpu.dtb.data_misses 55050 # DTB misses 159system.cpu.dtb.data_acv 958 # DTB access violations 160system.cpu.dtb.data_accesses 1285792 # DTB accesses 161system.cpu.itb.fetch_hits 1328947 # ITB hits 162system.cpu.itb.fetch_misses 38142 # ITB misses 163system.cpu.itb.fetch_acv 1080 # ITB acv 164system.cpu.itb.fetch_accesses 1367089 # ITB accesses | 307system.cpu.dtb.read_hits 10013236 # DTB read hits 308system.cpu.dtb.read_misses 44959 # DTB read misses 309system.cpu.dtb.read_acv 558 # DTB read access violations 310system.cpu.dtb.read_accesses 947796 # DTB read accesses 311system.cpu.dtb.write_hits 6616814 # DTB write hits 312system.cpu.dtb.write_misses 10390 # DTB write misses 313system.cpu.dtb.write_acv 394 # DTB write access violations 314system.cpu.dtb.write_accesses 338465 # DTB write accesses 315system.cpu.dtb.data_hits 16630050 # DTB hits 316system.cpu.dtb.data_misses 55349 # DTB misses 317system.cpu.dtb.data_acv 952 # DTB access violations 318system.cpu.dtb.data_accesses 1286261 # DTB accesses 319system.cpu.itb.fetch_hits 1329992 # ITB hits 320system.cpu.itb.fetch_misses 37108 # ITB misses 321system.cpu.itb.fetch_acv 1110 # ITB acv 322system.cpu.itb.fetch_accesses 1367100 # ITB accesses |
| 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.read_acv 0 # DTB read access violations 168system.cpu.itb.read_accesses 0 # DTB read accesses 169system.cpu.itb.write_hits 0 # DTB write hits 170system.cpu.itb.write_misses 0 # DTB write misses 171system.cpu.itb.write_acv 0 # DTB write access violations 172system.cpu.itb.write_accesses 0 # DTB write accesses 173system.cpu.itb.data_hits 0 # DTB hits 174system.cpu.itb.data_misses 0 # DTB misses 175system.cpu.itb.data_acv 0 # DTB access violations 176system.cpu.itb.data_accesses 0 # DTB accesses | 323system.cpu.itb.read_hits 0 # DTB read hits 324system.cpu.itb.read_misses 0 # DTB read misses 325system.cpu.itb.read_acv 0 # DTB read access violations 326system.cpu.itb.read_accesses 0 # DTB read accesses 327system.cpu.itb.write_hits 0 # DTB write hits 328system.cpu.itb.write_misses 0 # DTB write misses 329system.cpu.itb.write_acv 0 # DTB write access violations 330system.cpu.itb.write_accesses 0 # DTB write accesses 331system.cpu.itb.data_hits 0 # DTB hits 332system.cpu.itb.data_misses 0 # DTB misses 333system.cpu.itb.data_acv 0 # DTB access violations 334system.cpu.itb.data_accesses 0 # DTB accesses |
| 177system.cpu.numCycles 112948398 # number of cpu cycles simulated | 335system.cpu.numCycles 109331520 # number of cpu cycles simulated |
| 178system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 179system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 336system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 337system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 180system.cpu.BPredUnit.lookups 13966796 # Number of BP lookups 181system.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted 182system.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect 183system.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups 184system.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits | 338system.cpu.BPredUnit.lookups 14034298 # Number of BP lookups 339system.cpu.BPredUnit.condPredicted 11727409 # Number of conditional branches predicted 340system.cpu.BPredUnit.condIncorrect 442398 # Number of conditional branches incorrect 341system.cpu.BPredUnit.BTBLookups 10070774 # Number of BTB lookups 342system.cpu.BPredUnit.BTBHits 5936443 # Number of BTB hits |
| 185system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 343system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 186system.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target. 187system.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions. 188system.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss 189system.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed 190system.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered 191system.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken 192system.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked 193system.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing 194system.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked 195system.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 196system.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps 197system.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions 198system.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR 199system.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched 200system.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed 201system.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total) 202system.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total) 203system.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total) | 344system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target. 345system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions. 346system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss 347system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed 348system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered 349system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken 350system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked 351system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing 352system.cpu.fetch.BlockedCycles 37395096 # Number of cycles fetch has spent blocked 353system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 354system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps 355system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions 356system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR 357system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched 358system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed 359system.cpu.fetch.rateDist::samples 81356871 # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) |
| 204system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 362system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 205system.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total) 208system.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total) | 363system.cpu.fetch.rateDist::0 67855364 83.40% 83.40% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total) |
| 214system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 372system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 217system.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle 219system.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle 220system.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle 221system.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked 222system.cpu.decode.RunCycles 12232048 # Number of cycles decode is running 223system.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking 224system.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing 225system.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch 226system.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction 227system.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode 228system.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode 229system.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing 230system.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle 231system.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking 232system.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst 233system.cpu.rename.RunCycles 11473805 # Number of cycles rename is running 234system.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking 235system.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename 236system.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full 237system.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full 238system.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full 239system.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed 240system.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made 241system.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups 242system.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups 243system.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed 244system.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing 245system.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed 246system.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed 247system.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer 248system.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit. 249system.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit. 250system.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads. 251system.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores. 252system.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec) 253system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ 254system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued 255system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued 256system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling 257system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph 258system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed 259system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle 260system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle | 375system.cpu.fetch.rateDist::total 81356871 # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle 377system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle 378system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle 379system.cpu.decode.BlockedCycles 37116939 # Number of cycles decode is blocked 380system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running 381system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking 382system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing 383system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch 384system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction 385system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode 386system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode 387system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing 388system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle 389system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking 390system.cpu.rename.serializeStallCycles 19830183 # count of cycles rename stalled for serializing inst 391system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running 392system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking 393system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename 394system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full 395system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full 396system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full 397system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed 398system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made 399system.cpu.rename.int_rename_lookups 80190207 # Number of integer rename lookups 400system.cpu.rename.fp_rename_lookups 479545 # Number of floating rename lookups 401system.cpu.rename.CommittedMaps 38187514 # Number of HB maps that are committed 402system.cpu.rename.UndoneMaps 6228893 # Number of HB maps that are undone due to squashing 403system.cpu.rename.serializingInsts 1695379 # count of serializing insts renamed 404system.cpu.rename.tempSerializingInsts 248206 # count of temporary serializing insts renamed 405system.cpu.rename.skidInsts 12171415 # count of insts added to the skid buffer 406system.cpu.memDep0.insertedLoads 10595299 # Number of loads inserted to the mem dependence unit. 407system.cpu.memDep0.insertedStores 6961029 # Number of stores inserted to the mem dependence unit. 408system.cpu.memDep0.conflictingLoads 1313529 # Number of conflicting loads. 409system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores. 410system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec) 411system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ 412system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued 413system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued 414system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling 415system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph 416system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed 417system.cpu.iq.issued_per_cycle::samples 81356871 # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle |
| 262system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 420system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 263system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle | 421system.cpu.iq.issued_per_cycle::0 56509821 69.46% 69.46% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle |
| 272system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 430system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 275system.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle | 433system.cpu.iq.issued_per_cycle::total 81356871 # Number of insts issued each cycle |
| 276system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 434system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 277system.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available 278system.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available 279system.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available 280system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available 281system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available 282system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available 283system.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available 284system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available 285system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available 286system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available 287system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available 306system.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available 307system.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available | 435system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available 436system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available 437system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.25% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.25% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.25% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.25% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.25% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.25% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.25% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.25% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdMult 0 0.00% 11.25% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.25% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdShift 0 0.00% 11.25% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.25% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.25% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.25% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.25% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.25% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.25% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.25% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.25% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.25% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.25% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.25% # attempts to use FU when none available 464system.cpu.iq.fu_full::MemRead 375615 47.50% 58.75% # attempts to use FU when none available 465system.cpu.iq.fu_full::MemWrite 326165 41.25% 100.00% # attempts to use FU when none available |
| 308system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 309system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 466system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 467system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 310system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 311system.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued 312system.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued 313system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued 314system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued 315system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued 316system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued 317system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued 318system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued 319system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued 320system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued 340system.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued 341system.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued 342system.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued | 468system.cpu.iq.FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued 469system.cpu.iq.FU_type_0::IntAlu 38947584 68.15% 68.16% # Type of FU issued 470system.cpu.iq.FU_type_0::IntMult 61688 0.11% 68.27% # Type of FU issued 471system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.32% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.32% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.32% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.32% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.32% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.32% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.32% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.32% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.32% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.32% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.32% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.32% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.32% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.32% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.32% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued 498system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued 499system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued 500system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued |
| 343system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 501system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 344system.cpu.iq.FU_type_0::total 57074473 # Type of FU issued 345system.cpu.iq.rate 0.505315 # Inst issue rate 346system.cpu.iq.fu_busy_cnt 789329 # FU busy when requested 347system.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst) 348system.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads 349system.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes 350system.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses 351system.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads 352system.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes 353system.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses 354system.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses 355system.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses 356system.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores | 502system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued 503system.cpu.iq.rate 0.522738 # Inst issue rate 504system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested 505system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) 506system.cpu.iq.int_inst_queue_reads 195876832 # Number of integer instruction queue reads 507system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes 508system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses 509system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads 510system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes 511system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses 512system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses 513system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses 514system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores |
| 357system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 515system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 358system.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed 359system.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed 360system.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations 361system.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed | 516system.cpu.iew.lsq.thread0.squashedLoads 1500833 # Number of loads squashed 517system.cpu.iew.lsq.thread0.ignoredResponses 3663 # Number of memory responses ignored because the instruction is squashed 518system.cpu.iew.lsq.thread0.memOrderViolation 13623 # Number of memory ordering violations 519system.cpu.iew.lsq.thread0.squashedStores 580148 # Number of stores squashed |
| 362system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 363system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 520system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 521system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 364system.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled 365system.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked | 522system.cpu.iew.lsq.thread0.rescheduledLoads 17973 # Number of loads that were rescheduled 523system.cpu.iew.lsq.thread0.cacheBlocked 208284 # Number of times an access to memory failed due to the cache being blocked |
| 366system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 524system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 367system.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing 368system.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking 369system.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking 370system.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ 371system.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch 372system.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions 373system.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions 374system.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions 375system.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall 376system.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall 377system.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations 378system.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly 379system.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly 380system.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute 381system.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions 382system.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed 383system.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute | 525system.cpu.iew.iewSquashCycles 1354175 # Number of cycles IEW is squashing 526system.cpu.iew.iewBlockCycles 9957840 # Number of cycles IEW is blocking 527system.cpu.iew.iewUnblockCycles 684465 # Number of cycles IEW is unblocking 528system.cpu.iew.iewDispatchedInsts 64406962 # Number of instructions dispatched to IQ 529system.cpu.iew.iewDispSquashedInsts 718774 # Number of squashed instructions skipped by dispatch 530system.cpu.iew.iewDispLoadInsts 10595299 # Number of dispatched load instructions 531system.cpu.iew.iewDispStoreInsts 6961029 # Number of dispatched store instructions 532system.cpu.iew.iewDispNonSpecInsts 1833098 # Number of dispatched non-speculative instructions 533system.cpu.iew.iewIQFullEvents 512595 # Number of times the IQ has become full, causing a stall 534system.cpu.iew.iewLSQFullEvents 19043 # Number of times the LSQ has become full, causing a stall 535system.cpu.iew.memOrderViolationEvents 13623 # Number of memory order violations 536system.cpu.iew.predictedTakenIncorrect 239398 # Number of branches that were predicted taken incorrectly 537system.cpu.iew.predictedNotTakenIncorrect 420347 # Number of branches that were predicted not taken incorrectly 538system.cpu.iew.branchMispredicts 659745 # Number of branch mispredicts detected at execute 539system.cpu.iew.iewExecutedInsts 56634449 # Number of executed instructions 540system.cpu.iew.iewExecLoadInsts 10087078 # Number of load instructions executed 541system.cpu.iew.iewExecSquashedInsts 517300 # Number of squashed instructions skipped in execute |
| 384system.cpu.iew.exec_swp 0 # number of swp insts executed | 542system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 385system.cpu.iew.exec_nop 3555305 # number of nop insts executed 386system.cpu.iew.exec_refs 16665522 # number of memory reference insts executed 387system.cpu.iew.exec_branches 8969939 # Number of branches executed 388system.cpu.iew.exec_stores 6649129 # Number of stores executed 389system.cpu.iew.exec_rate 0.500679 # Inst execution rate 390system.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit 391system.cpu.iew.wb_count 56121532 # cumulative count of insts written-back 392system.cpu.iew.wb_producers 27804186 # num instructions producing a value 393system.cpu.iew.wb_consumers 37617732 # num instructions consuming a value | 543system.cpu.iew.exec_nop 3558099 # number of nop insts executed 544system.cpu.iew.exec_refs 16729501 # number of memory reference insts executed 545system.cpu.iew.exec_branches 8966109 # Number of branches executed 546system.cpu.iew.exec_stores 6642423 # Number of stores executed 547system.cpu.iew.exec_rate 0.518007 # Inst execution rate 548system.cpu.iew.wb_sent 56249945 # cumulative count of insts sent to commit 549system.cpu.iew.wb_count 56126682 # cumulative count of insts written-back 550system.cpu.iew.wb_producers 27860065 # num instructions producing a value 551system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value |
| 394system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 552system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 395system.cpu.iew.wb_rate 0.496878 # insts written-back per cycle 396system.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back | 553system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle 554system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back |
| 397system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 555system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 398system.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit 399system.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards 400system.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted 401system.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle | 556system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit 557system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards 558system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted 559system.cpu.commit.committed_per_cycle::samples 80002696 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle |
| 404system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 562system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 405system.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle | 563system.cpu.commit.committed_per_cycle::0 59120918 73.90% 73.90% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle |
| 414system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 572system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 417system.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle 418system.cpu.commit.committedInsts 56188905 # Number of instructions committed 419system.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed | 575system.cpu.commit.committed_per_cycle::total 80002696 # Number of insts commited each cycle 576system.cpu.commit.committedInsts 56184240 # Number of instructions committed 577system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed |
| 420system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 578system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 421system.cpu.commit.refs 15476867 # Number of memory references committed 422system.cpu.commit.loads 9095415 # Number of loads committed 423system.cpu.commit.membars 226300 # Number of memory barriers committed 424system.cpu.commit.branches 8447820 # Number of branches committed | 579system.cpu.commit.refs 15475347 # Number of memory references committed 580system.cpu.commit.loads 9094466 # Number of loads committed 581system.cpu.commit.membars 226347 # Number of memory barriers committed 582system.cpu.commit.branches 8447798 # Number of branches committed |
| 425system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 583system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 426system.cpu.commit.int_insts 52034961 # Number of committed integer instructions. 427system.cpu.commit.function_calls 740468 # Number of function calls committed. 428system.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached | 584system.cpu.commit.int_insts 52030338 # Number of committed integer instructions. 585system.cpu.commit.function_calls 740415 # Number of function calls committed. 586system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached |
| 429system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 587system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 430system.cpu.rob.rob_reads 141682968 # The number of ROB reads 431system.cpu.rob.rob_writes 129465441 # The number of ROB writes 432system.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself 433system.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling 434system.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 435system.cpu.committedInsts 52998368 # Number of Instructions Simulated 436system.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated 437system.cpu.committedInsts_total 52998368 # Number of Instructions Simulated 438system.cpu.cpi 2.131167 # CPI: Cycles Per Instruction 439system.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads 440system.cpu.ipc 0.469226 # IPC: Instructions Per Cycle 441system.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads 442system.cpu.int_regfile_reads 74144483 # number of integer regfile reads 443system.cpu.int_regfile_writes 40484328 # number of integer regfile writes 444system.cpu.fp_regfile_reads 165992 # number of floating regfile reads 445system.cpu.fp_regfile_writes 167427 # number of floating regfile writes 446system.cpu.misc_regfile_reads 1993361 # number of misc regfile reads 447system.cpu.misc_regfile_writes 946826 # number of misc regfile writes | 588system.cpu.rob.rob_reads 142220967 # The number of ROB reads 589system.cpu.rob.rob_writes 129940455 # The number of ROB writes 590system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself 591system.cpu.idleCycles 27974649 # Total number of cycles that the CPU has spent unscheduled due to idling 592system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 593system.cpu.committedInsts 52993965 # Number of Instructions Simulated 594system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated 595system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated 596system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction 597system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads 598system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle 599system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads 600system.cpu.int_regfile_reads 74218754 # number of integer regfile reads 601system.cpu.int_regfile_writes 40498790 # number of integer regfile writes 602system.cpu.fp_regfile_reads 166070 # number of floating regfile reads 603system.cpu.fp_regfile_writes 167447 # number of floating regfile writes 604system.cpu.misc_regfile_reads 1994018 # number of misc regfile reads 605system.cpu.misc_regfile_writes 947042 # number of misc regfile writes |
| 448system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 449system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 450system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 451system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 452system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 453system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 454system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 455system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 471system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 472system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 473system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 474system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 475system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 476system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 477system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 478system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 606system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 607system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 608system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 609system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 610system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 611system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 612system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 613system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 629system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 630system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 631system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 632system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 633system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 634system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 635system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 636system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 479system.cpu.icache.replacements 1020348 # number of replacements 480system.cpu.icache.tagsinuse 510.019758 # Cycle average of tags in use 481system.cpu.icache.total_refs 7661720 # Total number of references to valid blocks. 482system.cpu.icache.sampled_refs 1020856 # Sample count of references to valid blocks. 483system.cpu.icache.avg_refs 7.505192 # Average number of references to valid blocks. 484system.cpu.icache.warmup_cycle 22969954000 # Cycle when the warmup percentage was hit. 485system.cpu.icache.occ_blocks::cpu.inst 510.019758 # Average occupied blocks per requestor 486system.cpu.icache.occ_percent::cpu.inst 0.996132 # Average percentage of cache occupancy 487system.cpu.icache.occ_percent::total 0.996132 # Average percentage of cache occupancy 488system.cpu.icache.ReadReq_hits::cpu.inst 7661721 # number of ReadReq hits 489system.cpu.icache.ReadReq_hits::total 7661721 # number of ReadReq hits 490system.cpu.icache.demand_hits::cpu.inst 7661721 # number of demand (read+write) hits 491system.cpu.icache.demand_hits::total 7661721 # number of demand (read+write) hits 492system.cpu.icache.overall_hits::cpu.inst 7661721 # number of overall hits 493system.cpu.icache.overall_hits::total 7661721 # number of overall hits 494system.cpu.icache.ReadReq_misses::cpu.inst 1079749 # number of ReadReq misses 495system.cpu.icache.ReadReq_misses::total 1079749 # number of ReadReq misses 496system.cpu.icache.demand_misses::cpu.inst 1079749 # number of demand (read+write) misses 497system.cpu.icache.demand_misses::total 1079749 # number of demand (read+write) misses 498system.cpu.icache.overall_misses::cpu.inst 1079749 # number of overall misses 499system.cpu.icache.overall_misses::total 1079749 # number of overall misses 500system.cpu.icache.ReadReq_miss_latency::cpu.inst 14523691994 # number of ReadReq miss cycles 501system.cpu.icache.ReadReq_miss_latency::total 14523691994 # number of ReadReq miss cycles 502system.cpu.icache.demand_miss_latency::cpu.inst 14523691994 # number of demand (read+write) miss cycles 503system.cpu.icache.demand_miss_latency::total 14523691994 # number of demand (read+write) miss cycles 504system.cpu.icache.overall_miss_latency::cpu.inst 14523691994 # number of overall miss cycles 505system.cpu.icache.overall_miss_latency::total 14523691994 # number of overall miss cycles 506system.cpu.icache.ReadReq_accesses::cpu.inst 8741470 # number of ReadReq accesses(hits+misses) 507system.cpu.icache.ReadReq_accesses::total 8741470 # number of ReadReq accesses(hits+misses) 508system.cpu.icache.demand_accesses::cpu.inst 8741470 # number of demand (read+write) accesses 509system.cpu.icache.demand_accesses::total 8741470 # number of demand (read+write) accesses 510system.cpu.icache.overall_accesses::cpu.inst 8741470 # number of overall (read+write) accesses 511system.cpu.icache.overall_accesses::total 8741470 # number of overall (read+write) accesses 512system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123520 # miss rate for ReadReq accesses 513system.cpu.icache.ReadReq_miss_rate::total 0.123520 # miss rate for ReadReq accesses 514system.cpu.icache.demand_miss_rate::cpu.inst 0.123520 # miss rate for demand accesses 515system.cpu.icache.demand_miss_rate::total 0.123520 # miss rate for demand accesses 516system.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses 517system.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses 518system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency 519system.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency 520system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency 521system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency 522system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency 523system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency 524system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked 525system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 526system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked 527system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 528system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked 529system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 637system.cpu.icache.replacements 1020188 # number of replacements 638system.cpu.icache.tagsinuse 510.304097 # Cycle average of tags in use 639system.cpu.icache.total_refs 7717774 # Total number of references to valid blocks. 640system.cpu.icache.sampled_refs 1020696 # Sample count of references to valid blocks. 641system.cpu.icache.avg_refs 7.561286 # Average number of references to valid blocks. 642system.cpu.icache.warmup_cycle 20124452000 # Cycle when the warmup percentage was hit. 643system.cpu.icache.occ_blocks::cpu.inst 510.304097 # Average occupied blocks per requestor 644system.cpu.icache.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy 645system.cpu.icache.occ_percent::total 0.996688 # Average percentage of cache occupancy 646system.cpu.icache.ReadReq_hits::cpu.inst 7717775 # number of ReadReq hits 647system.cpu.icache.ReadReq_hits::total 7717775 # number of ReadReq hits 648system.cpu.icache.demand_hits::cpu.inst 7717775 # number of demand (read+write) hits 649system.cpu.icache.demand_hits::total 7717775 # number of demand (read+write) hits 650system.cpu.icache.overall_hits::cpu.inst 7717775 # number of overall hits 651system.cpu.icache.overall_hits::total 7717775 # number of overall hits 652system.cpu.icache.ReadReq_misses::cpu.inst 1079494 # number of ReadReq misses 653system.cpu.icache.ReadReq_misses::total 1079494 # number of ReadReq misses 654system.cpu.icache.demand_misses::cpu.inst 1079494 # number of demand (read+write) misses 655system.cpu.icache.demand_misses::total 1079494 # number of demand (read+write) misses 656system.cpu.icache.overall_misses::cpu.inst 1079494 # number of overall misses 657system.cpu.icache.overall_misses::total 1079494 # number of overall misses 658system.cpu.icache.ReadReq_miss_latency::cpu.inst 14680685994 # number of ReadReq miss cycles 659system.cpu.icache.ReadReq_miss_latency::total 14680685994 # number of ReadReq miss cycles 660system.cpu.icache.demand_miss_latency::cpu.inst 14680685994 # number of demand (read+write) miss cycles 661system.cpu.icache.demand_miss_latency::total 14680685994 # number of demand (read+write) miss cycles 662system.cpu.icache.overall_miss_latency::cpu.inst 14680685994 # number of overall miss cycles 663system.cpu.icache.overall_miss_latency::total 14680685994 # number of overall miss cycles 664system.cpu.icache.ReadReq_accesses::cpu.inst 8797269 # number of ReadReq accesses(hits+misses) 665system.cpu.icache.ReadReq_accesses::total 8797269 # number of ReadReq accesses(hits+misses) 666system.cpu.icache.demand_accesses::cpu.inst 8797269 # number of demand (read+write) accesses 667system.cpu.icache.demand_accesses::total 8797269 # number of demand (read+write) accesses 668system.cpu.icache.overall_accesses::cpu.inst 8797269 # number of overall (read+write) accesses 669system.cpu.icache.overall_accesses::total 8797269 # number of overall (read+write) accesses 670system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122708 # miss rate for ReadReq accesses 671system.cpu.icache.ReadReq_miss_rate::total 0.122708 # miss rate for ReadReq accesses 672system.cpu.icache.demand_miss_rate::cpu.inst 0.122708 # miss rate for demand accesses 673system.cpu.icache.demand_miss_rate::total 0.122708 # miss rate for demand accesses 674system.cpu.icache.overall_miss_rate::cpu.inst 0.122708 # miss rate for overall accesses 675system.cpu.icache.overall_miss_rate::total 0.122708 # miss rate for overall accesses 676system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13599.599436 # average ReadReq miss latency 677system.cpu.icache.ReadReq_avg_miss_latency::total 13599.599436 # average ReadReq miss latency 678system.cpu.icache.demand_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency 679system.cpu.icache.demand_avg_miss_latency::total 13599.599436 # average overall miss latency 680system.cpu.icache.overall_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency 681system.cpu.icache.overall_avg_miss_latency::total 13599.599436 # average overall miss latency 682system.cpu.icache.blocked_cycles::no_mshrs 3410 # number of cycles access was blocked 683system.cpu.icache.blocked_cycles::no_targets 686 # number of cycles access was blocked 684system.cpu.icache.blocked::no_mshrs 137 # number of cycles access was blocked 685system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 686system.cpu.icache.avg_blocked_cycles::no_mshrs 24.890511 # average number of cycles each access was blocked 687system.cpu.icache.avg_blocked_cycles::no_targets 686 # average number of cycles each access was blocked |
| 530system.cpu.icache.fast_writes 0 # number of fast writes performed 531system.cpu.icache.cache_copies 0 # number of cache copies performed | 688system.cpu.icache.fast_writes 0 # number of fast writes performed 689system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 532system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58677 # number of ReadReq MSHR hits 533system.cpu.icache.ReadReq_mshr_hits::total 58677 # number of ReadReq MSHR hits 534system.cpu.icache.demand_mshr_hits::cpu.inst 58677 # number of demand (read+write) MSHR hits 535system.cpu.icache.demand_mshr_hits::total 58677 # number of demand (read+write) MSHR hits 536system.cpu.icache.overall_mshr_hits::cpu.inst 58677 # number of overall MSHR hits 537system.cpu.icache.overall_mshr_hits::total 58677 # number of overall MSHR hits 538system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021072 # number of ReadReq MSHR misses 539system.cpu.icache.ReadReq_mshr_misses::total 1021072 # number of ReadReq MSHR misses 540system.cpu.icache.demand_mshr_misses::cpu.inst 1021072 # number of demand (read+write) MSHR misses 541system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses 542system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses 543system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses 544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930955996 # number of ReadReq MSHR miss cycles 545system.cpu.icache.ReadReq_mshr_miss_latency::total 11930955996 # number of ReadReq MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930955996 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.demand_mshr_miss_latency::total 11930955996 # number of demand (read+write) MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930955996 # number of overall MSHR miss cycles 549system.cpu.icache.overall_mshr_miss_latency::total 11930955996 # number of overall MSHR miss cycles 550system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses 552system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses 553system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses 554system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses 555system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.735255 # average ReadReq mshr miss latency 557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.735255 # average ReadReq mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency 559system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency 561system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency | 690system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58579 # number of ReadReq MSHR hits 691system.cpu.icache.ReadReq_mshr_hits::total 58579 # number of ReadReq MSHR hits 692system.cpu.icache.demand_mshr_hits::cpu.inst 58579 # number of demand (read+write) MSHR hits 693system.cpu.icache.demand_mshr_hits::total 58579 # number of demand (read+write) MSHR hits 694system.cpu.icache.overall_mshr_hits::cpu.inst 58579 # number of overall MSHR hits 695system.cpu.icache.overall_mshr_hits::total 58579 # number of overall MSHR hits 696system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1020915 # number of ReadReq MSHR misses 697system.cpu.icache.ReadReq_mshr_misses::total 1020915 # number of ReadReq MSHR misses 698system.cpu.icache.demand_mshr_misses::cpu.inst 1020915 # number of demand (read+write) MSHR misses 699system.cpu.icache.demand_mshr_misses::total 1020915 # number of demand (read+write) MSHR misses 700system.cpu.icache.overall_mshr_misses::cpu.inst 1020915 # number of overall MSHR misses 701system.cpu.icache.overall_mshr_misses::total 1020915 # number of overall MSHR misses 702system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12036646497 # number of ReadReq MSHR miss cycles 703system.cpu.icache.ReadReq_mshr_miss_latency::total 12036646497 # number of ReadReq MSHR miss cycles 704system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12036646497 # number of demand (read+write) MSHR miss cycles 705system.cpu.icache.demand_mshr_miss_latency::total 12036646497 # number of demand (read+write) MSHR miss cycles 706system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12036646497 # number of overall MSHR miss cycles 707system.cpu.icache.overall_mshr_miss_latency::total 12036646497 # number of overall MSHR miss cycles 708system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for ReadReq accesses 709system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116049 # mshr miss rate for ReadReq accesses 710system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for demand accesses 711system.cpu.icache.demand_mshr_miss_rate::total 0.116049 # mshr miss rate for demand accesses 712system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for overall accesses 713system.cpu.icache.overall_mshr_miss_rate::total 0.116049 # mshr miss rate for overall accesses 714system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11790.057446 # average ReadReq mshr miss latency 715system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11790.057446 # average ReadReq mshr miss latency 716system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11790.057446 # average overall mshr miss latency 717system.cpu.icache.demand_avg_mshr_miss_latency::total 11790.057446 # average overall mshr miss latency 718system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11790.057446 # average overall mshr miss latency 719system.cpu.icache.overall_avg_mshr_miss_latency::total 11790.057446 # average overall mshr miss latency |
| 562system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 720system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 563system.cpu.dcache.replacements 1402622 # number of replacements 564system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use 565system.cpu.dcache.total_refs 11889704 # Total number of references to valid blocks. 566system.cpu.dcache.sampled_refs 1403134 # Sample count of references to valid blocks. 567system.cpu.dcache.avg_refs 8.473677 # Average number of references to valid blocks. 568system.cpu.dcache.warmup_cycle 23228000 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.occ_blocks::cpu.data 511.994917 # Average occupied blocks per requestor 570system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 571system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy 572system.cpu.dcache.ReadReq_hits::cpu.data 7274743 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 7274743 # number of ReadReq hits 574system.cpu.dcache.WriteReq_hits::cpu.data 4204816 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 4204816 # number of WriteReq hits 576system.cpu.dcache.LoadLockedReq_hits::cpu.data 190397 # number of LoadLockedReq hits 577system.cpu.dcache.LoadLockedReq_hits::total 190397 # number of LoadLockedReq hits 578system.cpu.dcache.StoreCondReq_hits::cpu.data 219522 # number of StoreCondReq hits 579system.cpu.dcache.StoreCondReq_hits::total 219522 # number of StoreCondReq hits 580system.cpu.dcache.demand_hits::cpu.data 11479559 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 11479559 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 11479559 # number of overall hits 583system.cpu.dcache.overall_hits::total 11479559 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 1797475 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 1797475 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 1942414 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 1942414 # number of WriteReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 23040 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 23040 # number of LoadLockedReq misses 590system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 591system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 592system.cpu.dcache.demand_misses::cpu.data 3739889 # number of demand (read+write) misses 593system.cpu.dcache.demand_misses::total 3739889 # number of demand (read+write) misses 594system.cpu.dcache.overall_misses::cpu.data 3739889 # number of overall misses 595system.cpu.dcache.overall_misses::total 3739889 # number of overall misses 596system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles 597system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles 598system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417909184 # number of WriteReq miss cycles 599system.cpu.dcache.WriteReq_miss_latency::total 56417909184 # number of WriteReq miss cycles 600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles 601system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles 602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles 603system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles 604system.cpu.dcache.demand_miss_latency::cpu.data 91795913684 # number of demand (read+write) miss cycles 605system.cpu.dcache.demand_miss_latency::total 91795913684 # number of demand (read+write) miss cycles 606system.cpu.dcache.overall_miss_latency::cpu.data 91795913684 # number of overall miss cycles 607system.cpu.dcache.overall_miss_latency::total 91795913684 # number of overall miss cycles 608system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses) 609system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses) 610system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses) 611system.cpu.dcache.WriteReq_accesses::total 6147230 # number of WriteReq accesses(hits+misses) 612system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213437 # number of LoadLockedReq accesses(hits+misses) 613system.cpu.dcache.LoadLockedReq_accesses::total 213437 # number of LoadLockedReq accesses(hits+misses) 614system.cpu.dcache.StoreCondReq_accesses::cpu.data 219523 # number of StoreCondReq accesses(hits+misses) 615system.cpu.dcache.StoreCondReq_accesses::total 219523 # number of StoreCondReq accesses(hits+misses) 616system.cpu.dcache.demand_accesses::cpu.data 15219448 # number of demand (read+write) accesses 617system.cpu.dcache.demand_accesses::total 15219448 # number of demand (read+write) accesses 618system.cpu.dcache.overall_accesses::cpu.data 15219448 # number of overall (read+write) accesses 619system.cpu.dcache.overall_accesses::total 15219448 # number of overall (read+write) accesses 620system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198130 # miss rate for ReadReq accesses 621system.cpu.dcache.ReadReq_miss_rate::total 0.198130 # miss rate for ReadReq accesses 622system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315982 # miss rate for WriteReq accesses 623system.cpu.dcache.WriteReq_miss_rate::total 0.315982 # miss rate for WriteReq accesses 624system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107948 # miss rate for LoadLockedReq accesses 625system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107948 # miss rate for LoadLockedReq accesses 626system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses 627system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses 628system.cpu.dcache.demand_miss_rate::cpu.data 0.245731 # miss rate for demand accesses 629system.cpu.dcache.demand_miss_rate::total 0.245731 # miss rate for demand accesses 630system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 # miss rate for overall accesses 631system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses 632system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency 633system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency 634system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.254608 # average WriteReq miss latency 635system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.254608 # average WriteReq miss latency 636system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency 637system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency 638system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 639system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 640system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency 641system.cpu.dcache.demand_avg_miss_latency::total 24545.090425 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency 643system.cpu.dcache.overall_avg_miss_latency::total 24545.090425 # average overall miss latency 644system.cpu.dcache.blocked_cycles::no_mshrs 1615102 # number of cycles access was blocked 645system.cpu.dcache.blocked_cycles::no_targets 442 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked 647system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 648system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.681144 # average number of cycles each access was blocked 649system.cpu.dcache.avg_blocked_cycles::no_targets 49.111111 # average number of cycles each access was blocked | 721system.cpu.dcache.replacements 1402245 # number of replacements 722system.cpu.dcache.tagsinuse 511.995160 # Cycle average of tags in use 723system.cpu.dcache.total_refs 11879672 # Total number of references to valid blocks. 724system.cpu.dcache.sampled_refs 1402757 # Sample count of references to valid blocks. 725system.cpu.dcache.avg_refs 8.468803 # Average number of references to valid blocks. 726system.cpu.dcache.warmup_cycle 21544000 # Cycle when the warmup percentage was hit. 727system.cpu.dcache.occ_blocks::cpu.data 511.995160 # Average occupied blocks per requestor 728system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 729system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy 730system.cpu.dcache.ReadReq_hits::cpu.data 7264730 # number of ReadReq hits 731system.cpu.dcache.ReadReq_hits::total 7264730 # number of ReadReq hits 732system.cpu.dcache.WriteReq_hits::cpu.data 4204895 # number of WriteReq hits 733system.cpu.dcache.WriteReq_hits::total 4204895 # number of WriteReq hits 734system.cpu.dcache.LoadLockedReq_hits::cpu.data 190246 # number of LoadLockedReq hits 735system.cpu.dcache.LoadLockedReq_hits::total 190246 # number of LoadLockedReq hits 736system.cpu.dcache.StoreCondReq_hits::cpu.data 219552 # number of StoreCondReq hits 737system.cpu.dcache.StoreCondReq_hits::total 219552 # number of StoreCondReq hits 738system.cpu.dcache.demand_hits::cpu.data 11469625 # number of demand (read+write) hits 739system.cpu.dcache.demand_hits::total 11469625 # number of demand (read+write) hits 740system.cpu.dcache.overall_hits::cpu.data 11469625 # number of overall hits 741system.cpu.dcache.overall_hits::total 11469625 # number of overall hits 742system.cpu.dcache.ReadReq_misses::cpu.data 1801434 # number of ReadReq misses 743system.cpu.dcache.ReadReq_misses::total 1801434 # number of ReadReq misses 744system.cpu.dcache.WriteReq_misses::cpu.data 1941730 # number of WriteReq misses 745system.cpu.dcache.WriteReq_misses::total 1941730 # number of WriteReq misses 746system.cpu.dcache.LoadLockedReq_misses::cpu.data 22995 # number of LoadLockedReq misses 747system.cpu.dcache.LoadLockedReq_misses::total 22995 # number of LoadLockedReq misses 748system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 749system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 750system.cpu.dcache.demand_misses::cpu.data 3743164 # number of demand (read+write) misses 751system.cpu.dcache.demand_misses::total 3743164 # number of demand (read+write) misses 752system.cpu.dcache.overall_misses::cpu.data 3743164 # number of overall misses 753system.cpu.dcache.overall_misses::total 3743164 # number of overall misses 754system.cpu.dcache.ReadReq_miss_latency::cpu.data 33852672500 # number of ReadReq miss cycles 755system.cpu.dcache.ReadReq_miss_latency::total 33852672500 # number of ReadReq miss cycles 756system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445086639 # number of WriteReq miss cycles 757system.cpu.dcache.WriteReq_miss_latency::total 70445086639 # number of WriteReq miss cycles 758system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307962000 # number of LoadLockedReq miss cycles 759system.cpu.dcache.LoadLockedReq_miss_latency::total 307962000 # number of LoadLockedReq miss cycles 760system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38000 # number of StoreCondReq miss cycles 761system.cpu.dcache.StoreCondReq_miss_latency::total 38000 # number of StoreCondReq miss cycles 762system.cpu.dcache.demand_miss_latency::cpu.data 104297759139 # number of demand (read+write) miss cycles 763system.cpu.dcache.demand_miss_latency::total 104297759139 # number of demand (read+write) miss cycles 764system.cpu.dcache.overall_miss_latency::cpu.data 104297759139 # number of overall miss cycles 765system.cpu.dcache.overall_miss_latency::total 104297759139 # number of overall miss cycles 766system.cpu.dcache.ReadReq_accesses::cpu.data 9066164 # number of ReadReq accesses(hits+misses) 767system.cpu.dcache.ReadReq_accesses::total 9066164 # number of ReadReq accesses(hits+misses) 768system.cpu.dcache.WriteReq_accesses::cpu.data 6146625 # number of WriteReq accesses(hits+misses) 769system.cpu.dcache.WriteReq_accesses::total 6146625 # number of WriteReq accesses(hits+misses) 770system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213241 # number of LoadLockedReq accesses(hits+misses) 771system.cpu.dcache.LoadLockedReq_accesses::total 213241 # number of LoadLockedReq accesses(hits+misses) 772system.cpu.dcache.StoreCondReq_accesses::cpu.data 219554 # number of StoreCondReq accesses(hits+misses) 773system.cpu.dcache.StoreCondReq_accesses::total 219554 # number of StoreCondReq accesses(hits+misses) 774system.cpu.dcache.demand_accesses::cpu.data 15212789 # number of demand (read+write) accesses 775system.cpu.dcache.demand_accesses::total 15212789 # number of demand (read+write) accesses 776system.cpu.dcache.overall_accesses::cpu.data 15212789 # number of overall (read+write) accesses 777system.cpu.dcache.overall_accesses::total 15212789 # number of overall (read+write) accesses 778system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198699 # miss rate for ReadReq accesses 779system.cpu.dcache.ReadReq_miss_rate::total 0.198699 # miss rate for ReadReq accesses 780system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315902 # miss rate for WriteReq accesses 781system.cpu.dcache.WriteReq_miss_rate::total 0.315902 # miss rate for WriteReq accesses 782system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107836 # miss rate for LoadLockedReq accesses 783system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107836 # miss rate for LoadLockedReq accesses 784system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 785system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 786system.cpu.dcache.demand_miss_rate::cpu.data 0.246054 # miss rate for demand accesses 787system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses 788system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses 789system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses 790system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency 791system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency 792system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.547949 # average WriteReq miss latency 793system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.547949 # average WriteReq miss latency 794system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency 795system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency 796system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency 797system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency 798system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency 799system.cpu.dcache.demand_avg_miss_latency::total 27863.529126 # average overall miss latency 800system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.529126 # average overall miss latency 801system.cpu.dcache.overall_avg_miss_latency::total 27863.529126 # average overall miss latency 802system.cpu.dcache.blocked_cycles::no_mshrs 2571682 # number of cycles access was blocked 803system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked 804system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked 805system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 806system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946948 # average number of cycles each access was blocked 807system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked |
| 650system.cpu.dcache.fast_writes 0 # number of fast writes performed 651system.cpu.dcache.cache_copies 0 # number of cache copies performed | 808system.cpu.dcache.fast_writes 0 # number of fast writes performed 809system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 652system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks 653system.cpu.dcache.writebacks::total 841878 # number of writebacks 654system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712313 # number of ReadReq MSHR hits 655system.cpu.dcache.ReadReq_mshr_hits::total 712313 # number of ReadReq MSHR hits 656system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642186 # number of WriteReq MSHR hits 657system.cpu.dcache.WriteReq_mshr_hits::total 1642186 # number of WriteReq MSHR hits 658system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5152 # number of LoadLockedReq MSHR hits 659system.cpu.dcache.LoadLockedReq_mshr_hits::total 5152 # number of LoadLockedReq MSHR hits 660system.cpu.dcache.demand_mshr_hits::cpu.data 2354499 # number of demand (read+write) MSHR hits 661system.cpu.dcache.demand_mshr_hits::total 2354499 # number of demand (read+write) MSHR hits 662system.cpu.dcache.overall_mshr_hits::cpu.data 2354499 # number of overall MSHR hits 663system.cpu.dcache.overall_mshr_hits::total 2354499 # number of overall MSHR hits 664system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085162 # number of ReadReq MSHR misses 665system.cpu.dcache.ReadReq_mshr_misses::total 1085162 # number of ReadReq MSHR misses 666system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300228 # number of WriteReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::total 300228 # number of WriteReq MSHR misses 668system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17888 # number of LoadLockedReq MSHR misses 669system.cpu.dcache.LoadLockedReq_mshr_misses::total 17888 # number of LoadLockedReq MSHR misses 670system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 671system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 672system.cpu.dcache.demand_mshr_misses::cpu.data 1385390 # number of demand (read+write) MSHR misses 673system.cpu.dcache.demand_mshr_misses::total 1385390 # number of demand (read+write) MSHR misses 674system.cpu.dcache.overall_mshr_misses::cpu.data 1385390 # number of overall MSHR misses 675system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses 676system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles 677system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles 678system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402034783 # number of WriteReq MSHR miss cycles 679system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402034783 # number of WriteReq MSHR miss cycles 680system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles 681system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles 682system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles 683system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles 684system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065701283 # number of demand (read+write) MSHR miss cycles 685system.cpu.dcache.demand_mshr_miss_latency::total 32065701283 # number of demand (read+write) MSHR miss cycles 686system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065701283 # number of overall MSHR miss cycles 687system.cpu.dcache.overall_mshr_miss_latency::total 32065701283 # number of overall MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles 689system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles 690system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles 691system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997524498 # number of WriteReq MSHR uncacheable cycles 692system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles 693system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles 694system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119614 # mshr miss rate for ReadReq accesses 695system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119614 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048840 # mshr miss rate for WriteReq accesses 697system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048840 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083809 # mshr miss rate for LoadLockedReq accesses 699system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083809 # mshr miss rate for LoadLockedReq accesses 700system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses 701system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses 702system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for demand accesses 703system.cpu.dcache.demand_mshr_miss_rate::total 0.091028 # mshr miss rate for demand accesses 704system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for overall accesses 705system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency 710system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency 711system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency 712system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 713system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 714system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency 715system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency 716system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency 717system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency | 810system.cpu.dcache.writebacks::writebacks 841139 # number of writebacks 811system.cpu.dcache.writebacks::total 841139 # number of writebacks 812system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716695 # number of ReadReq MSHR hits 813system.cpu.dcache.ReadReq_mshr_hits::total 716695 # number of ReadReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1641513 # number of WriteReq MSHR hits 815system.cpu.dcache.WriteReq_mshr_hits::total 1641513 # number of WriteReq MSHR hits 816system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5045 # number of LoadLockedReq MSHR hits 817system.cpu.dcache.LoadLockedReq_mshr_hits::total 5045 # number of LoadLockedReq MSHR hits 818system.cpu.dcache.demand_mshr_hits::cpu.data 2358208 # number of demand (read+write) MSHR hits 819system.cpu.dcache.demand_mshr_hits::total 2358208 # number of demand (read+write) MSHR hits 820system.cpu.dcache.overall_mshr_hits::cpu.data 2358208 # number of overall MSHR hits 821system.cpu.dcache.overall_mshr_hits::total 2358208 # number of overall MSHR hits 822system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084739 # number of ReadReq MSHR misses 823system.cpu.dcache.ReadReq_mshr_misses::total 1084739 # number of ReadReq MSHR misses 824system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300217 # number of WriteReq MSHR misses 825system.cpu.dcache.WriteReq_mshr_misses::total 300217 # number of WriteReq MSHR misses 826system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17950 # number of LoadLockedReq MSHR misses 827system.cpu.dcache.LoadLockedReq_mshr_misses::total 17950 # number of LoadLockedReq MSHR misses 828system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 829system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 830system.cpu.dcache.demand_mshr_misses::cpu.data 1384956 # number of demand (read+write) MSHR misses 831system.cpu.dcache.demand_mshr_misses::total 1384956 # number of demand (read+write) MSHR misses 832system.cpu.dcache.overall_mshr_misses::cpu.data 1384956 # number of overall MSHR misses 833system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses 834system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles 835system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles 836system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712390769 # number of WriteReq MSHR miss cycles 837system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712390769 # number of WriteReq MSHR miss cycles 838system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles 839system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles 840system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles 841system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles 842system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907863269 # number of demand (read+write) MSHR miss cycles 843system.cpu.dcache.demand_mshr_miss_latency::total 31907863269 # number of demand (read+write) MSHR miss cycles 844system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907863269 # number of overall MSHR miss cycles 845system.cpu.dcache.overall_mshr_miss_latency::total 31907863269 # number of overall MSHR miss cycles 846system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles 847system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles 848system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997718998 # number of WriteReq MSHR uncacheable cycles 849system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997718998 # number of WriteReq MSHR uncacheable cycles 850system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421626998 # number of overall MSHR uncacheable cycles 851system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421626998 # number of overall MSHR uncacheable cycles 852system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048843 # mshr miss rate for WriteReq accesses 856system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084177 # mshr miss rate for LoadLockedReq accesses 857system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084177 # mshr miss rate for LoadLockedReq accesses 858system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 859system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 860system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for demand accesses 861system.cpu.dcache.demand_mshr_miss_rate::total 0.091039 # mshr miss rate for demand accesses 862system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for overall accesses 863system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency 865system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency 866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.159135 # average WriteReq mshr miss latency 867system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.159135 # average WriteReq mshr miss latency 868system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency 869system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency 870system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency 871system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency 872system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency 873system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency 874system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.900347 # average overall mshr miss latency 875system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.900347 # average overall mshr miss latency |
| 718system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 719system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 720system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 721system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 722system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 723system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 724system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 876system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 877system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 878system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 879system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 880system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 881system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 882system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 725system.cpu.l2cache.replacements 338417 # number of replacements 726system.cpu.l2cache.tagsinuse 65352.111585 # Cycle average of tags in use 727system.cpu.l2cache.total_refs 2559541 # Total number of references to valid blocks. 728system.cpu.l2cache.sampled_refs 403585 # Sample count of references to valid blocks. 729system.cpu.l2cache.avg_refs 6.342012 # Average number of references to valid blocks. 730system.cpu.l2cache.warmup_cycle 4707423000 # Cycle when the warmup percentage was hit. 731system.cpu.l2cache.occ_blocks::writebacks 53923.419199 # Average occupied blocks per requestor 732system.cpu.l2cache.occ_blocks::cpu.inst 5354.651362 # Average occupied blocks per requestor 733system.cpu.l2cache.occ_blocks::cpu.data 6074.041024 # Average occupied blocks per requestor 734system.cpu.l2cache.occ_percent::writebacks 0.822806 # Average percentage of cache occupancy 735system.cpu.l2cache.occ_percent::cpu.inst 0.081705 # Average percentage of cache occupancy 736system.cpu.l2cache.occ_percent::cpu.data 0.092683 # Average percentage of cache occupancy 737system.cpu.l2cache.occ_percent::total 0.997194 # Average percentage of cache occupancy 738system.cpu.l2cache.ReadReq_hits::cpu.inst 1005811 # number of ReadReq hits 739system.cpu.l2cache.ReadReq_hits::cpu.data 828504 # number of ReadReq hits 740system.cpu.l2cache.ReadReq_hits::total 1834315 # number of ReadReq hits 741system.cpu.l2cache.Writeback_hits::writebacks 841878 # number of Writeback hits 742system.cpu.l2cache.Writeback_hits::total 841878 # number of Writeback hits 743system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 744system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits | 883system.cpu.l2cache.replacements 338360 # number of replacements 884system.cpu.l2cache.tagsinuse 65364.997376 # Cycle average of tags in use 885system.cpu.l2cache.total_refs 2558215 # Total number of references to valid blocks. 886system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks. 887system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks. 888system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit. 889system.cpu.l2cache.occ_blocks::writebacks 53963.120653 # Average occupied blocks per requestor 890system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor 891system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor 892system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy 893system.cpu.l2cache.occ_percent::cpu.inst 0.081638 # Average percentage of cache occupancy 894system.cpu.l2cache.occ_percent::cpu.data 0.092341 # Average percentage of cache occupancy 895system.cpu.l2cache.occ_percent::total 0.997391 # Average percentage of cache occupancy 896system.cpu.l2cache.ReadReq_hits::cpu.inst 1005648 # number of ReadReq hits 897system.cpu.l2cache.ReadReq_hits::cpu.data 828171 # number of ReadReq hits 898system.cpu.l2cache.ReadReq_hits::total 1833819 # number of ReadReq hits 899system.cpu.l2cache.Writeback_hits::writebacks 841139 # number of Writeback hits 900system.cpu.l2cache.Writeback_hits::total 841139 # number of Writeback hits 901system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 902system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits |
| 745system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 746system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits | 903system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 904system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits |
| 747system.cpu.l2cache.ReadExReq_hits::cpu.data 185452 # number of ReadExReq hits 748system.cpu.l2cache.ReadExReq_hits::total 185452 # number of ReadExReq hits 749system.cpu.l2cache.demand_hits::cpu.inst 1005811 # number of demand (read+write) hits 750system.cpu.l2cache.demand_hits::cpu.data 1013956 # number of demand (read+write) hits 751system.cpu.l2cache.demand_hits::total 2019767 # number of demand (read+write) hits 752system.cpu.l2cache.overall_hits::cpu.inst 1005811 # number of overall hits 753system.cpu.l2cache.overall_hits::cpu.data 1013956 # number of overall hits 754system.cpu.l2cache.overall_hits::total 2019767 # number of overall hits 755system.cpu.l2cache.ReadReq_misses::cpu.inst 15151 # number of ReadReq misses 756system.cpu.l2cache.ReadReq_misses::cpu.data 273885 # number of ReadReq misses 757system.cpu.l2cache.ReadReq_misses::total 289036 # number of ReadReq misses 758system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses 759system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses 760system.cpu.l2cache.ReadExReq_misses::cpu.data 115380 # number of ReadExReq misses 761system.cpu.l2cache.ReadExReq_misses::total 115380 # number of ReadExReq misses 762system.cpu.l2cache.demand_misses::cpu.inst 15151 # number of demand (read+write) misses 763system.cpu.l2cache.demand_misses::cpu.data 389265 # number of demand (read+write) misses 764system.cpu.l2cache.demand_misses::total 404416 # number of demand (read+write) misses 765system.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses 766system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses 767system.cpu.l2cache.overall_misses::total 404416 # number of overall misses 768system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808283500 # number of ReadReq miss cycles 769system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles 770system.cpu.l2cache.ReadReq_miss_latency::total 15073472500 # number of ReadReq miss cycles 771system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles 772system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles 773system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187369500 # number of ReadExReq miss cycles 774system.cpu.l2cache.ReadExReq_miss_latency::total 6187369500 # number of ReadExReq miss cycles 775system.cpu.l2cache.demand_miss_latency::cpu.inst 808283500 # number of demand (read+write) miss cycles 776system.cpu.l2cache.demand_miss_latency::cpu.data 20452558500 # number of demand (read+write) miss cycles 777system.cpu.l2cache.demand_miss_latency::total 21260842000 # number of demand (read+write) miss cycles 778system.cpu.l2cache.overall_miss_latency::cpu.inst 808283500 # number of overall miss cycles 779system.cpu.l2cache.overall_miss_latency::cpu.data 20452558500 # number of overall miss cycles 780system.cpu.l2cache.overall_miss_latency::total 21260842000 # number of overall miss cycles 781system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses) 782system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses) 783system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses) 784system.cpu.l2cache.Writeback_accesses::writebacks 841878 # number of Writeback accesses(hits+misses) 785system.cpu.l2cache.Writeback_accesses::total 841878 # number of Writeback accesses(hits+misses) 786system.cpu.l2cache.UpgradeReq_accesses::cpu.data 59 # number of UpgradeReq accesses(hits+misses) 787system.cpu.l2cache.UpgradeReq_accesses::total 59 # number of UpgradeReq accesses(hits+misses) 788system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 789system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 790system.cpu.l2cache.ReadExReq_accesses::cpu.data 300832 # number of ReadExReq accesses(hits+misses) 791system.cpu.l2cache.ReadExReq_accesses::total 300832 # number of ReadExReq accesses(hits+misses) 792system.cpu.l2cache.demand_accesses::cpu.inst 1020962 # number of demand (read+write) accesses 793system.cpu.l2cache.demand_accesses::cpu.data 1403221 # number of demand (read+write) accesses 794system.cpu.l2cache.demand_accesses::total 2424183 # number of demand (read+write) accesses 795system.cpu.l2cache.overall_accesses::cpu.inst 1020962 # number of overall (read+write) accesses 796system.cpu.l2cache.overall_accesses::cpu.data 1403221 # number of overall (read+write) accesses 797system.cpu.l2cache.overall_accesses::total 2424183 # number of overall (read+write) accesses 798system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014840 # miss rate for ReadReq accesses 799system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248447 # miss rate for ReadReq accesses 800system.cpu.l2cache.ReadReq_miss_rate::total 0.136123 # miss rate for ReadReq accesses 801system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.559322 # miss rate for UpgradeReq accesses 802system.cpu.l2cache.UpgradeReq_miss_rate::total 0.559322 # miss rate for UpgradeReq accesses 803system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383536 # miss rate for ReadExReq accesses 804system.cpu.l2cache.ReadExReq_miss_rate::total 0.383536 # miss rate for ReadExReq accesses 805system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014840 # miss rate for demand accesses 806system.cpu.l2cache.demand_miss_rate::cpu.data 0.277408 # miss rate for demand accesses 807system.cpu.l2cache.demand_miss_rate::total 0.166826 # miss rate for demand accesses 808system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses 810system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses 811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.524850 # average ReadReq miss latency 812system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency 813system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.847991 # average ReadReq miss latency 814system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency 815system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency 816system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.014041 # average ReadExReq miss latency 817system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.014041 # average ReadExReq miss latency 818system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency 819system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency 820system.cpu.l2cache.demand_avg_miss_latency::total 52571.713285 # average overall miss latency 821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency 822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency 823system.cpu.l2cache.overall_avg_miss_latency::total 52571.713285 # average overall miss latency | 905system.cpu.l2cache.ReadExReq_hits::cpu.data 185483 # number of ReadExReq hits 906system.cpu.l2cache.ReadExReq_hits::total 185483 # number of ReadExReq hits 907system.cpu.l2cache.demand_hits::cpu.inst 1005648 # number of demand (read+write) hits 908system.cpu.l2cache.demand_hits::cpu.data 1013654 # number of demand (read+write) hits 909system.cpu.l2cache.demand_hits::total 2019302 # number of demand (read+write) hits 910system.cpu.l2cache.overall_hits::cpu.inst 1005648 # number of overall hits 911system.cpu.l2cache.overall_hits::cpu.data 1013654 # number of overall hits 912system.cpu.l2cache.overall_hits::total 2019302 # number of overall hits 913system.cpu.l2cache.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses 914system.cpu.l2cache.ReadReq_misses::cpu.data 273859 # number of ReadReq misses 915system.cpu.l2cache.ReadReq_misses::total 289003 # number of ReadReq misses 916system.cpu.l2cache.UpgradeReq_misses::cpu.data 36 # number of UpgradeReq misses 917system.cpu.l2cache.UpgradeReq_misses::total 36 # number of UpgradeReq misses 918system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 919system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 920system.cpu.l2cache.ReadExReq_misses::cpu.data 115327 # number of ReadExReq misses 921system.cpu.l2cache.ReadExReq_misses::total 115327 # number of ReadExReq misses 922system.cpu.l2cache.demand_misses::cpu.inst 15144 # number of demand (read+write) misses 923system.cpu.l2cache.demand_misses::cpu.data 389186 # number of demand (read+write) misses 924system.cpu.l2cache.demand_misses::total 404330 # number of demand (read+write) misses 925system.cpu.l2cache.overall_misses::cpu.inst 15144 # number of overall misses 926system.cpu.l2cache.overall_misses::cpu.data 389186 # number of overall misses 927system.cpu.l2cache.overall_misses::total 404330 # number of overall misses 928system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 916217000 # number of ReadReq miss cycles 929system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11804091500 # number of ReadReq miss cycles 930system.cpu.l2cache.ReadReq_miss_latency::total 12720308500 # number of ReadReq miss cycles 931system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles 932system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles 933system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496192000 # number of ReadExReq miss cycles 934system.cpu.l2cache.ReadExReq_miss_latency::total 8496192000 # number of ReadExReq miss cycles 935system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles 936system.cpu.l2cache.demand_miss_latency::cpu.data 20300283500 # number of demand (read+write) miss cycles 937system.cpu.l2cache.demand_miss_latency::total 21216500500 # number of demand (read+write) miss cycles 938system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles 939system.cpu.l2cache.overall_miss_latency::cpu.data 20300283500 # number of overall miss cycles 940system.cpu.l2cache.overall_miss_latency::total 21216500500 # number of overall miss cycles 941system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses) 942system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses) 943system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses) 944system.cpu.l2cache.Writeback_accesses::writebacks 841139 # number of Writeback accesses(hits+misses) 945system.cpu.l2cache.Writeback_accesses::total 841139 # number of Writeback accesses(hits+misses) 946system.cpu.l2cache.UpgradeReq_accesses::cpu.data 67 # number of UpgradeReq accesses(hits+misses) 947system.cpu.l2cache.UpgradeReq_accesses::total 67 # number of UpgradeReq accesses(hits+misses) 948system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 949system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 950system.cpu.l2cache.ReadExReq_accesses::cpu.data 300810 # number of ReadExReq accesses(hits+misses) 951system.cpu.l2cache.ReadExReq_accesses::total 300810 # number of ReadExReq accesses(hits+misses) 952system.cpu.l2cache.demand_accesses::cpu.inst 1020792 # number of demand (read+write) accesses 953system.cpu.l2cache.demand_accesses::cpu.data 1402840 # number of demand (read+write) accesses 954system.cpu.l2cache.demand_accesses::total 2423632 # number of demand (read+write) accesses 955system.cpu.l2cache.overall_accesses::cpu.inst 1020792 # number of overall (read+write) accesses 956system.cpu.l2cache.overall_accesses::cpu.data 1402840 # number of overall (read+write) accesses 957system.cpu.l2cache.overall_accesses::total 2423632 # number of overall (read+write) accesses 958system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014836 # miss rate for ReadReq accesses 959system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248504 # miss rate for ReadReq accesses 960system.cpu.l2cache.ReadReq_miss_rate::total 0.136141 # miss rate for ReadReq accesses 961system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.537313 # miss rate for UpgradeReq accesses 962system.cpu.l2cache.UpgradeReq_miss_rate::total 0.537313 # miss rate for UpgradeReq accesses 963system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses 964system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses 965system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383388 # miss rate for ReadExReq accesses 966system.cpu.l2cache.ReadExReq_miss_rate::total 0.383388 # miss rate for ReadExReq accesses 967system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014836 # miss rate for demand accesses 968system.cpu.l2cache.demand_miss_rate::cpu.data 0.277427 # miss rate for demand accesses 969system.cpu.l2cache.demand_miss_rate::total 0.166828 # miss rate for demand accesses 970system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014836 # miss rate for overall accesses 971system.cpu.l2cache.overall_miss_rate::cpu.data 0.277427 # miss rate for overall accesses 972system.cpu.l2cache.overall_miss_rate::total 0.166828 # miss rate for overall accesses 973system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60500.330164 # average ReadReq miss latency 974system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43102.806554 # average ReadReq miss latency 975system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency 976system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency 977system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency 978system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.450111 # average ReadExReq miss latency 979system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.450111 # average ReadExReq miss latency 980system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency 981system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency 982system.cpu.l2cache.demand_avg_miss_latency::total 52473.228551 # average overall miss latency 983system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency 984system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.878089 # average overall miss latency 985system.cpu.l2cache.overall_avg_miss_latency::total 52473.228551 # average overall miss latency |
| 824system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 825system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 826system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 827system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 828system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 829system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 830system.cpu.l2cache.fast_writes 0 # number of fast writes performed 831system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 986system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 987system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 988system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 989system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 990system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 991system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 992system.cpu.l2cache.fast_writes 0 # number of fast writes performed 993system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 832system.cpu.l2cache.writebacks::writebacks 76030 # number of writebacks 833system.cpu.l2cache.writebacks::total 76030 # number of writebacks | 994system.cpu.l2cache.writebacks::writebacks 75796 # number of writebacks 995system.cpu.l2cache.writebacks::total 75796 # number of writebacks |
| 834system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 835system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 836system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 837system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 838system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 839system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 996system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 997system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 998system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 999system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1000system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1001system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 840system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15150 # number of ReadReq MSHR misses 841system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273885 # number of ReadReq MSHR misses 842system.cpu.l2cache.ReadReq_mshr_misses::total 289035 # number of ReadReq MSHR misses 843system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses 844system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses 845system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115380 # number of ReadExReq MSHR misses 846system.cpu.l2cache.ReadExReq_mshr_misses::total 115380 # number of ReadExReq MSHR misses 847system.cpu.l2cache.demand_mshr_misses::cpu.inst 15150 # number of demand (read+write) MSHR misses 848system.cpu.l2cache.demand_mshr_misses::cpu.data 389265 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.demand_mshr_misses::total 404415 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses 851system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses 852system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses 853system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919500 # number of ReadReq MSHR miss cycles 854system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986768000 # number of ReadReq MSHR miss cycles 855system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609687500 # number of ReadReq MSHR miss cycles 856system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles 857system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles 858system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791050000 # number of ReadExReq MSHR miss cycles 859system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791050000 # number of ReadExReq MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919500 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777818000 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.demand_mshr_miss_latency::total 16400737500 # number of demand (read+write) MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919500 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777818000 # number of overall MSHR miss cycles 865system.cpu.l2cache.overall_mshr_miss_latency::total 16400737500 # number of overall MSHR miss cycles 866system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles 867system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles 868system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939500 # number of WriteReq MSHR uncacheable cycles 869system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939500 # number of WriteReq MSHR uncacheable cycles 870system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539000 # number of overall MSHR uncacheable cycles 871system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539000 # number of overall MSHR uncacheable cycles 872system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses 873system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses 874system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses 875system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.559322 # mshr miss rate for UpgradeReq accesses 876system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.559322 # mshr miss rate for UpgradeReq accesses 877system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383536 # mshr miss rate for ReadExReq accesses 878system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383536 # mshr miss rate for ReadExReq accesses 879system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for demand accesses 880system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for demand accesses 881system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 # mshr miss rate for demand accesses 882system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses 883system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses 884system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses 885system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.798680 # average ReadReq mshr miss latency 886system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.529821 # average ReadReq mshr miss latency 887system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40167.064542 # average ReadReq mshr miss latency 888system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency 889system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency 890system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.094297 # average ReadExReq mshr miss latency 891system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.094297 # average ReadExReq mshr miss latency 892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency 893system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency 894system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency 895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency 896system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency 897system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency | 1002system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses 1003system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses 1004system.cpu.l2cache.ReadReq_mshr_misses::total 289002 # number of ReadReq MSHR misses 1005system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses 1006system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses 1007system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1008system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1009system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115327 # number of ReadExReq MSHR misses 1010system.cpu.l2cache.ReadExReq_mshr_misses::total 115327 # number of ReadExReq MSHR misses 1011system.cpu.l2cache.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses 1012system.cpu.l2cache.demand_mshr_misses::cpu.data 389186 # number of demand (read+write) MSHR misses 1013system.cpu.l2cache.demand_mshr_misses::total 404329 # number of demand (read+write) MSHR misses 1014system.cpu.l2cache.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses 1015system.cpu.l2cache.overall_mshr_misses::cpu.data 389186 # number of overall MSHR misses 1016system.cpu.l2cache.overall_mshr_misses::total 404329 # number of overall MSHR misses 1017system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles 1018system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles 1019system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles 1020system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles 1021system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles 1022system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles 1023system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles 1024system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067951103 # number of ReadExReq MSHR miss cycles 1025system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067951103 # number of ReadExReq MSHR miss cycles 1026system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles 1027system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327873464 # number of demand (read+write) MSHR miss cycles 1028system.cpu.l2cache.demand_mshr_miss_latency::total 16052895904 # number of demand (read+write) MSHR miss cycles 1029system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles 1030system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327873464 # number of overall MSHR miss cycles 1031system.cpu.l2cache.overall_mshr_miss_latency::total 16052895904 # number of overall MSHR miss cycles 1032system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331389500 # number of ReadReq MSHR uncacheable cycles 1033system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331389500 # number of ReadReq MSHR uncacheable cycles 1034system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1881061000 # number of WriteReq MSHR uncacheable cycles 1035system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1881061000 # number of WriteReq MSHR uncacheable cycles 1036system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212450500 # number of overall MSHR uncacheable cycles 1037system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212450500 # number of overall MSHR uncacheable cycles 1038system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses 1039system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses 1040system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses 1041system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses 1042system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses 1043system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 1044system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses 1045system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses 1046system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383388 # mshr miss rate for ReadExReq accesses 1047system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for demand accesses 1048system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for demand accesses 1049system.cpu.l2cache.demand_mshr_miss_rate::total 0.166828 # mshr miss rate for demand accesses 1050system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for overall accesses 1051system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for overall accesses 1052system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses 1053system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency 1054system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency 1055system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency 1056system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency 1057system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency 1058system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1059system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1060system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.178458 # average ReadExReq mshr miss latency 1061system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.178458 # average ReadExReq mshr miss latency 1062system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency 1063system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency 1064system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency 1065system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency 1066system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.442051 # average overall mshr miss latency 1067system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.558817 # average overall mshr miss latency |
| 898system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 899system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 900system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 901system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 902system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 903system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 904system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 905system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1068system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1069system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1070system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1071system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1072system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1073system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1074system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1075system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 906system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed 907system.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed 908system.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl | 1076system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed 1077system.cpu.kern.inst.hwrei 211013 # number of hwrei instructions executed 1078system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl |
| 909system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl | 1079system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl |
| 910system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl 911system.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl 912system.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl 913system.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 1080system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1081system.cpu.kern.ipl_count::31 105569 57.93% 100.00% # number of times we switched to this ipl 1082system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl 1083system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 914system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl | 1084system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl |
| 915system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl 916system.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl 917system.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl 918system.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl 919system.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl 920system.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl 921system.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl 922system.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl 923system.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl | 1085system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1086system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1087system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl 1088system.cpu.kern.ipl_ticks::0 1818451122500 98.06% 98.06% # number of cycles we spent at this ipl 1089system.cpu.kern.ipl_ticks::21 64044500 0.00% 98.07% # number of cycles we spent at this ipl 1090system.cpu.kern.ipl_ticks::22 561305000 0.03% 98.10% # number of cycles we spent at this ipl 1091system.cpu.kern.ipl_ticks::31 35293166500 1.90% 100.00% # number of cycles we spent at this ipl 1092system.cpu.kern.ipl_ticks::total 1854369638500 # number of cycles we spent at this ipl 1093system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl |
| 924system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 925system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 1094system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1095system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 926system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl 927system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl | 1096system.cpu.kern.ipl_used::31 0.694295 # fraction of swpipl calls that actually changed the ipl 1097system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl |
| 928system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 929system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 930system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 931system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 932system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 933system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 934system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 935system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 958system.cpu.kern.syscall::total 326 # number of syscalls executed 959system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 960system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 961system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 962system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 963system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 964system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 965system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed | 1098system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1099system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1100system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1101system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1102system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1103system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1104system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1105system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 1128system.cpu.kern.syscall::total 326 # number of syscalls executed 1129system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1130system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1131system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1132system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1133system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1134system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1135system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed |
| 966system.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed 967system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed | 1136system.cpu.kern.callpal::swpipl 175126 91.22% 93.43% # number of callpals executed 1137system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed |
| 968system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 969system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 970system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 971system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed | 1138system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1139system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1140system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1141system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed |
| 972system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed | 1142system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed |
| 973system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 974system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 1143system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1144system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 975system.cpu.kern.callpal::total 191902 # number of callpals executed 976system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches | 1145system.cpu.kern.callpal::total 191972 # number of callpals executed 1146system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches |
| 977system.cpu.kern.mode_switch::user 1739 # number of protection mode switches | 1147system.cpu.kern.mode_switch::user 1739 # number of protection mode switches |
| 978system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches | 1148system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches |
| 979system.cpu.kern.mode_good::kernel 1909 980system.cpu.kern.mode_good::user 1739 981system.cpu.kern.mode_good::idle 170 | 1149system.cpu.kern.mode_good::kernel 1909 1150system.cpu.kern.mode_good::user 1739 1151system.cpu.kern.mode_good::idle 170 |
| 982system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches | 1152system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches |
| 983system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1153system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 984system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 985system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches 986system.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode 987system.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode 988system.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode | 1154system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 1155system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches 1156system.cpu.kern.mode_ticks::kernel 29748704000 1.60% 1.60% # number of ticks spent at the given mode 1157system.cpu.kern.mode_ticks::user 2690261500 0.15% 1.75% # number of ticks spent at the given mode 1158system.cpu.kern.mode_ticks::idle 1821930665000 98.25% 100.00% # number of ticks spent at the given mode |
| 989system.cpu.kern.swap_context 4177 # number of times the context was actually changed 990 991---------- End Simulation Statistics ---------- | 1159system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1160 1161---------- End Simulation Statistics ---------- |