Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.855236 # Number of seconds simulated
4sim_ticks 1855236450500 # Number of ticks simulated
5final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 87142 # Simulator instruction rate (inst/s)
8host_op_rate 87142 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3050446700 # Simulator tick rate (ticks/s)
10host_mem_usage 299400 # Number of bytes of host memory used
11host_seconds 608.19 # Real time elapsed on the host

7host_inst_rate 182093 # Simulator instruction rate (inst/s)
8host_op_rate 182093 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 6374280472 # Simulator tick rate (ticks/s)
10host_mem_usage 298212 # Number of bytes of host memory used
11host_seconds 291.05 # Real time elapsed on the host

12sim_insts 52998368 # Number of instructions simulated
13sim_ops 52998368 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory
16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
17system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory

--- 62 unchanged lines hidden (view full) ---

82system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency
83system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency
84system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency
85system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency
86system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency
87system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency
88system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency
89system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency

90system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked

90system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked

91system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
92system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked
93system.iocache.blocked::no_targets 0 # number of cycles access was blocked

94system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked

94system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked

95system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
96system.iocache.fast_writes 0 # number of fast writes performed
97system.iocache.cache_copies 0 # number of cache copies performed
98system.iocache.writebacks::writebacks 41512 # number of writebacks
99system.iocache.writebacks::total 41512 # number of writebacks
100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
102system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
103system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
104system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
105system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
106system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
107system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses

108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles
109system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles
110system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles
111system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles
112system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles
113system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles
114system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles
115system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles

108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles
109system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles
110system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles
111system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles
112system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles
113system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles
114system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles
115system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles

116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
118system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
119system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses

124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency
125system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency
126system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency
127system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency
128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency
129system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency
130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency
131system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency

124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency
125system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency
126system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency
127system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency
128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
129system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency
130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
131system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency

132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
133system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
134system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
135system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
136system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
137system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
138system.disk0.dma_write_txs 395 # Number of DMA write transactions.
139system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).

--- 113 unchanged lines hidden (view full) ---

253system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ
254system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued
255system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued
256system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling
257system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph
258system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed
259system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle
260system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle

261system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle

261system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle

262system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

263system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle
264system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle
265system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle
266system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle

263system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle
264system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle
265system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle
266system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle

267system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle
268system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle
269system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle
270system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle
271system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle
272system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
273system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
274system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

--- 241 unchanged lines hidden (view full) ---

516system.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses
517system.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses
518system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency
519system.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency
520system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency
521system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency
522system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency
523system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency

524system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked

524system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked

525system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
526system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked
527system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

528system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked

528system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked

529system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
530system.cpu.icache.fast_writes 0 # number of fast writes performed
531system.cpu.icache.cache_copies 0 # number of cache copies performed
532system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58677 # number of ReadReq MSHR hits
533system.cpu.icache.ReadReq_mshr_hits::total 58677 # number of ReadReq MSHR hits
534system.cpu.icache.demand_mshr_hits::cpu.inst 58677 # number of demand (read+write) MSHR hits
535system.cpu.icache.demand_mshr_hits::total 58677 # number of demand (read+write) MSHR hits
536system.cpu.icache.overall_mshr_hits::cpu.inst 58677 # number of overall MSHR hits
537system.cpu.icache.overall_mshr_hits::total 58677 # number of overall MSHR hits
538system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021072 # number of ReadReq MSHR misses
539system.cpu.icache.ReadReq_mshr_misses::total 1021072 # number of ReadReq MSHR misses
540system.cpu.icache.demand_mshr_misses::cpu.inst 1021072 # number of demand (read+write) MSHR misses
541system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses
542system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses
543system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses

544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930954998 # number of ReadReq MSHR miss cycles
545system.cpu.icache.ReadReq_mshr_miss_latency::total 11930954998 # number of ReadReq MSHR miss cycles
546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930954998 # number of demand (read+write) MSHR miss cycles
547system.cpu.icache.demand_mshr_miss_latency::total 11930954998 # number of demand (read+write) MSHR miss cycles
548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles
549system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles

544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930955996 # number of ReadReq MSHR miss cycles
545system.cpu.icache.ReadReq_mshr_miss_latency::total 11930955996 # number of ReadReq MSHR miss cycles
546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930955996 # number of demand (read+write) MSHR miss cycles
547system.cpu.icache.demand_mshr_miss_latency::total 11930955996 # number of demand (read+write) MSHR miss cycles
548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930955996 # number of overall MSHR miss cycles
549system.cpu.icache.overall_mshr_miss_latency::total 11930955996 # number of overall MSHR miss cycles

550system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses
551system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses
552system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses
553system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses
554system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses
555system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses

556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency
557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # average ReadReq mshr miss latency
558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency
559system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency
560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency
561system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency

556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.735255 # average ReadReq mshr miss latency
557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.735255 # average ReadReq mshr miss latency
558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency
559system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency
560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency
561system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency

562system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
563system.cpu.dcache.replacements 1402622 # number of replacements
564system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use
565system.cpu.dcache.total_refs 11889704 # Total number of references to valid blocks.
566system.cpu.dcache.sampled_refs 1403134 # Sample count of references to valid blocks.
567system.cpu.dcache.avg_refs 8.473677 # Average number of references to valid blocks.
568system.cpu.dcache.warmup_cycle 23228000 # Cycle when the warmup percentage was hit.
569system.cpu.dcache.occ_blocks::cpu.data 511.994917 # Average occupied blocks per requestor

--- 20 unchanged lines hidden (view full) ---

590system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
591system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
592system.cpu.dcache.demand_misses::cpu.data 3739889 # number of demand (read+write) misses
593system.cpu.dcache.demand_misses::total 3739889 # number of demand (read+write) misses
594system.cpu.dcache.overall_misses::cpu.data 3739889 # number of overall misses
595system.cpu.dcache.overall_misses::total 3739889 # number of overall misses
596system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles
597system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles

598system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles
599system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles

598system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417909184 # number of WriteReq miss cycles
599system.cpu.dcache.WriteReq_miss_latency::total 56417909184 # number of WriteReq miss cycles

600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles
601system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles
602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles
603system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles

604system.cpu.dcache.demand_miss_latency::cpu.data 91795917177 # number of demand (read+write) miss cycles
605system.cpu.dcache.demand_miss_latency::total 91795917177 # number of demand (read+write) miss cycles
606system.cpu.dcache.overall_miss_latency::cpu.data 91795917177 # number of overall miss cycles
607system.cpu.dcache.overall_miss_latency::total 91795917177 # number of overall miss cycles

604system.cpu.dcache.demand_miss_latency::cpu.data 91795913684 # number of demand (read+write) miss cycles
605system.cpu.dcache.demand_miss_latency::total 91795913684 # number of demand (read+write) miss cycles
606system.cpu.dcache.overall_miss_latency::cpu.data 91795913684 # number of overall miss cycles
607system.cpu.dcache.overall_miss_latency::total 91795913684 # number of overall miss cycles

608system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses)
609system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses)
610system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses)
611system.cpu.dcache.WriteReq_accesses::total 6147230 # number of WriteReq accesses(hits+misses)
612system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213437 # number of LoadLockedReq accesses(hits+misses)
613system.cpu.dcache.LoadLockedReq_accesses::total 213437 # number of LoadLockedReq accesses(hits+misses)
614system.cpu.dcache.StoreCondReq_accesses::cpu.data 219523 # number of StoreCondReq accesses(hits+misses)
615system.cpu.dcache.StoreCondReq_accesses::total 219523 # number of StoreCondReq accesses(hits+misses)

--- 10 unchanged lines hidden (view full) ---

626system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses
627system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
628system.cpu.dcache.demand_miss_rate::cpu.data 0.245731 # miss rate for demand accesses
629system.cpu.dcache.demand_miss_rate::total 0.245731 # miss rate for demand accesses
630system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 # miss rate for overall accesses
631system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses
632system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency
633system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency

634system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency
635system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency

634system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.254608 # average WriteReq miss latency
635system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.254608 # average WriteReq miss latency

636system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency
637system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency
638system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
639system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency

640system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency
641system.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency
642system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency
643system.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency
644system.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked
645system.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked

640system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency
641system.cpu.dcache.demand_avg_miss_latency::total 24545.090425 # average overall miss latency
642system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.090425 # average overall miss latency
643system.cpu.dcache.overall_avg_miss_latency::total 24545.090425 # average overall miss latency
644system.cpu.dcache.blocked_cycles::no_mshrs 1615102 # number of cycles access was blocked
645system.cpu.dcache.blocked_cycles::no_targets 442 # number of cycles access was blocked

646system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked
647system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked

648system.cpu.dcache.avg_blocked_cycles::no_mshrs 7343.815084 # average number of cycles each access was blocked
649system.cpu.dcache.avg_blocked_cycles::no_targets 24555.555556 # average number of cycles each access was blocked

648system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.681144 # average number of cycles each access was blocked
649system.cpu.dcache.avg_blocked_cycles::no_targets 49.111111 # average number of cycles each access was blocked

650system.cpu.dcache.fast_writes 0 # number of fast writes performed
651system.cpu.dcache.cache_copies 0 # number of cache copies performed
652system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks
653system.cpu.dcache.writebacks::total 841878 # number of writebacks
654system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712313 # number of ReadReq MSHR hits
655system.cpu.dcache.ReadReq_mshr_hits::total 712313 # number of ReadReq MSHR hits
656system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642186 # number of WriteReq MSHR hits
657system.cpu.dcache.WriteReq_mshr_hits::total 1642186 # number of WriteReq MSHR hits

--- 12 unchanged lines hidden (view full) ---

670system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
671system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
672system.cpu.dcache.demand_mshr_misses::cpu.data 1385390 # number of demand (read+write) MSHR misses
673system.cpu.dcache.demand_mshr_misses::total 1385390 # number of demand (read+write) MSHR misses
674system.cpu.dcache.overall_mshr_misses::cpu.data 1385390 # number of overall MSHR misses
675system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses
676system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles
677system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles

678system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402021809 # number of WriteReq MSHR miss cycles
679system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402021809 # number of WriteReq MSHR miss cycles

678system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402034783 # number of WriteReq MSHR miss cycles
679system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402034783 # number of WriteReq MSHR miss cycles

680system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles
681system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles
682system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles
683system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles

684system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065688309 # number of demand (read+write) MSHR miss cycles
685system.cpu.dcache.demand_mshr_miss_latency::total 32065688309 # number of demand (read+write) MSHR miss cycles
686system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065688309 # number of overall MSHR miss cycles
687system.cpu.dcache.overall_mshr_miss_latency::total 32065688309 # number of overall MSHR miss cycles

684system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065701283 # number of demand (read+write) MSHR miss cycles
685system.cpu.dcache.demand_mshr_miss_latency::total 32065701283 # number of demand (read+write) MSHR miss cycles
686system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065701283 # number of overall MSHR miss cycles
687system.cpu.dcache.overall_mshr_miss_latency::total 32065701283 # number of overall MSHR miss cycles

688system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles
689system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles
690system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles
691system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997524498 # number of WriteReq MSHR uncacheable cycles
692system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles
693system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles
694system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119614 # mshr miss rate for ReadReq accesses
695system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119614 # mshr miss rate for ReadReq accesses

--- 4 unchanged lines hidden (view full) ---

700system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses
701system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
702system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for demand accesses
703system.cpu.dcache.demand_mshr_miss_rate::total 0.091028 # mshr miss rate for demand accesses
704system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for overall accesses
705system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses
706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency
707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency

708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.470406 # average WriteReq mshr miss latency
709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.470406 # average WriteReq mshr miss latency

708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.513620 # average WriteReq mshr miss latency
709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.513620 # average WriteReq mshr miss latency

710system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency
711system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency
712system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
713system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency

714system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency
715system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency
716system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency
717system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency

714system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency
715system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency
716system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.613353 # average overall mshr miss latency
717system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.613353 # average overall mshr miss latency

718system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
719system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
720system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
721system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
722system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
723system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
724system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
725system.cpu.l2cache.replacements 338417 # number of replacements

--- 34 unchanged lines hidden (view full) ---

760system.cpu.l2cache.ReadExReq_misses::cpu.data 115380 # number of ReadExReq misses
761system.cpu.l2cache.ReadExReq_misses::total 115380 # number of ReadExReq misses
762system.cpu.l2cache.demand_misses::cpu.inst 15151 # number of demand (read+write) misses
763system.cpu.l2cache.demand_misses::cpu.data 389265 # number of demand (read+write) misses
764system.cpu.l2cache.demand_misses::total 404416 # number of demand (read+write) misses
765system.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses
766system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses
767system.cpu.l2cache.overall_misses::total 404416 # number of overall misses

768system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808284498 # number of ReadReq miss cycles

768system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808283500 # number of ReadReq miss cycles

769system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles

770system.cpu.l2cache.ReadReq_miss_latency::total 15073473498 # number of ReadReq miss cycles

770system.cpu.l2cache.ReadReq_miss_latency::total 15073472500 # number of ReadReq miss cycles

771system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles
772system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles

773system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187378482 # number of ReadExReq miss cycles
774system.cpu.l2cache.ReadExReq_miss_latency::total 6187378482 # number of ReadExReq miss cycles
775system.cpu.l2cache.demand_miss_latency::cpu.inst 808284498 # number of demand (read+write) miss cycles
776system.cpu.l2cache.demand_miss_latency::cpu.data 20452567482 # number of demand (read+write) miss cycles
777system.cpu.l2cache.demand_miss_latency::total 21260851980 # number of demand (read+write) miss cycles
778system.cpu.l2cache.overall_miss_latency::cpu.inst 808284498 # number of overall miss cycles
779system.cpu.l2cache.overall_miss_latency::cpu.data 20452567482 # number of overall miss cycles
780system.cpu.l2cache.overall_miss_latency::total 21260851980 # number of overall miss cycles

773system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187369500 # number of ReadExReq miss cycles
774system.cpu.l2cache.ReadExReq_miss_latency::total 6187369500 # number of ReadExReq miss cycles
775system.cpu.l2cache.demand_miss_latency::cpu.inst 808283500 # number of demand (read+write) miss cycles
776system.cpu.l2cache.demand_miss_latency::cpu.data 20452558500 # number of demand (read+write) miss cycles
777system.cpu.l2cache.demand_miss_latency::total 21260842000 # number of demand (read+write) miss cycles
778system.cpu.l2cache.overall_miss_latency::cpu.inst 808283500 # number of overall miss cycles
779system.cpu.l2cache.overall_miss_latency::cpu.data 20452558500 # number of overall miss cycles
780system.cpu.l2cache.overall_miss_latency::total 21260842000 # number of overall miss cycles

781system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses)
782system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses)
783system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses)
784system.cpu.l2cache.Writeback_accesses::writebacks 841878 # number of Writeback accesses(hits+misses)
785system.cpu.l2cache.Writeback_accesses::total 841878 # number of Writeback accesses(hits+misses)
786system.cpu.l2cache.UpgradeReq_accesses::cpu.data 59 # number of UpgradeReq accesses(hits+misses)
787system.cpu.l2cache.UpgradeReq_accesses::total 59 # number of UpgradeReq accesses(hits+misses)
788system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)

--- 14 unchanged lines hidden (view full) ---

803system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383536 # miss rate for ReadExReq accesses
804system.cpu.l2cache.ReadExReq_miss_rate::total 0.383536 # miss rate for ReadExReq accesses
805system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014840 # miss rate for demand accesses
806system.cpu.l2cache.demand_miss_rate::cpu.data 0.277408 # miss rate for demand accesses
807system.cpu.l2cache.demand_miss_rate::total 0.166826 # miss rate for demand accesses
808system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses
809system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses
810system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses

811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.590720 # average ReadReq miss latency

811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.524850 # average ReadReq miss latency

812system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency

813system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.851444 # average ReadReq miss latency

813system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.847991 # average ReadReq miss latency

814system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency
815system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency

816system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.091888 # average ReadExReq miss latency
817system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.091888 # average ReadExReq miss latency
818system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency
819system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency
820system.cpu.l2cache.demand_avg_miss_latency::total 52571.737963 # average overall miss latency
821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency
822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency
823system.cpu.l2cache.overall_avg_miss_latency::total 52571.737963 # average overall miss latency

816system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.014041 # average ReadExReq miss latency
817system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.014041 # average ReadExReq miss latency
818system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency
819system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency
820system.cpu.l2cache.demand_avg_miss_latency::total 52571.713285 # average overall miss latency
821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.524850 # average overall miss latency
822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.478170 # average overall miss latency
823system.cpu.l2cache.overall_avg_miss_latency::total 52571.713285 # average overall miss latency

824system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
825system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
826system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
827system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
828system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
829system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
830system.cpu.l2cache.fast_writes 0 # number of fast writes performed
831system.cpu.l2cache.cache_copies 0 # number of cache copies performed

--- 13 unchanged lines hidden (view full) ---

845system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115380 # number of ReadExReq MSHR misses
846system.cpu.l2cache.ReadExReq_mshr_misses::total 115380 # number of ReadExReq MSHR misses
847system.cpu.l2cache.demand_mshr_misses::cpu.inst 15150 # number of demand (read+write) MSHR misses
848system.cpu.l2cache.demand_mshr_misses::cpu.data 389265 # number of demand (read+write) MSHR misses
849system.cpu.l2cache.demand_mshr_misses::total 404415 # number of demand (read+write) MSHR misses
850system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses
851system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses
852system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses

853system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles
854system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles
855system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles

853system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919500 # number of ReadReq MSHR miss cycles
854system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986768000 # number of ReadReq MSHR miss cycles
855system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609687500 # number of ReadReq MSHR miss cycles

856system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles
857system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles

858system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles
859system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles
860system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles
861system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles
862system.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles
863system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles
864system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles
865system.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles

858system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791050000 # number of ReadExReq MSHR miss cycles
859system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791050000 # number of ReadExReq MSHR miss cycles
860system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919500 # number of demand (read+write) MSHR miss cycles
861system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777818000 # number of demand (read+write) MSHR miss cycles
862system.cpu.l2cache.demand_mshr_miss_latency::total 16400737500 # number of demand (read+write) MSHR miss cycles
863system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919500 # number of overall MSHR miss cycles
864system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777818000 # number of overall MSHR miss cycles
865system.cpu.l2cache.overall_mshr_miss_latency::total 16400737500 # number of overall MSHR miss cycles

866system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles
867system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles

868system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles
869system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles
870system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles
871system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles

868system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939500 # number of WriteReq MSHR uncacheable cycles
869system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939500 # number of WriteReq MSHR uncacheable cycles
870system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539000 # number of overall MSHR uncacheable cycles
871system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539000 # number of overall MSHR uncacheable cycles

872system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses
873system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses
874system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses
875system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.559322 # mshr miss rate for UpgradeReq accesses
876system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.559322 # mshr miss rate for UpgradeReq accesses
877system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383536 # mshr miss rate for ReadExReq accesses
878system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383536 # mshr miss rate for ReadExReq accesses
879system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for demand accesses
880system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for demand accesses
881system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 # mshr miss rate for demand accesses
882system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses
883system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses
884system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses

885system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency
886system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency
887system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency

885system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.798680 # average ReadReq mshr miss latency
886system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.529821 # average ReadReq mshr miss latency
887system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40167.064542 # average ReadReq mshr miss latency

888system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency
889system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency

890system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency
891system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency
892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency
893system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency
894system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency
895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency
896system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency
897system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency

890system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.094297 # average ReadExReq mshr miss latency
891system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.094297 # average ReadExReq mshr miss latency
892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency
893system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency
894system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency
895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.798680 # average overall mshr miss latency
896system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.331445 # average overall mshr miss latency
897system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.226475 # average overall mshr miss latency