| stats.txt (9283:490958b032d6) | stats.txt (9285:9901180cd573) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.867374 # Number of seconds simulated 4sim_ticks 1867373908500 # Number of ticks simulated 5final_tick 1867373908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.855236 # Number of seconds simulated 4sim_ticks 1855236450500 # Number of ticks simulated 5final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 123272 # Simulator instruction rate (inst/s) 8host_op_rate 123272 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4349339718 # Simulator tick rate (ticks/s) 10host_mem_usage 299108 # Number of bytes of host memory used 11host_seconds 429.35 # Real time elapsed on the host 12sim_insts 52926469 # Number of instructions simulated 13sim_ops 52926469 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 969792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory | 7host_inst_rate 87142 # Simulator instruction rate (inst/s) 8host_op_rate 87142 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3050446700 # Simulator tick rate (ticks/s) 10host_mem_usage 299400 # Number of bytes of host memory used 11host_seconds 608.19 # Real time elapsed on the host 12sim_insts 52998368 # Number of instructions simulated 13sim_ops 52998368 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24881216 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::total 28501568 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 969792 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 969792 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7518720 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7518720 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15153 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::total 28503040 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 969536 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 969536 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7522688 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7522688 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15149 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388769 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory | 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::total 445337 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117480 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117480 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 519335 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13323249 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1420330 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15262914 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 519335 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 519335 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4026360 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4026360 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4026360 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 519335 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13323249 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1420330 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19289275 # Total bandwidth to/from this memory (bytes/s) 41system.cpu.l2cache.replacements 338398 # number of replacements 42system.cpu.l2cache.tagsinuse 65348.140689 # Cycle average of tags in use 43system.cpu.l2cache.total_refs 2559915 # Total number of references to valid blocks. 44system.cpu.l2cache.sampled_refs 403567 # Sample count of references to valid blocks. 45system.cpu.l2cache.avg_refs 6.343222 # Average number of references to valid blocks. 46system.cpu.l2cache.warmup_cycle 4870006000 # Cycle when the warmup percentage was hit. 47system.cpu.l2cache.occ_blocks::writebacks 53844.889123 # Average occupied blocks per requestor 48system.cpu.l2cache.occ_blocks::cpu.inst 5363.726417 # Average occupied blocks per requestor 49system.cpu.l2cache.occ_blocks::cpu.data 6139.525149 # Average occupied blocks per requestor 50system.cpu.l2cache.occ_percent::writebacks 0.821608 # Average percentage of cache occupancy 51system.cpu.l2cache.occ_percent::cpu.inst 0.081844 # Average percentage of cache occupancy 52system.cpu.l2cache.occ_percent::cpu.data 0.093682 # Average percentage of cache occupancy 53system.cpu.l2cache.occ_percent::total 0.997133 # Average percentage of cache occupancy 54system.cpu.l2cache.ReadReq_hits::cpu.inst 1007783 # number of ReadReq hits 55system.cpu.l2cache.ReadReq_hits::cpu.data 827771 # number of ReadReq hits 56system.cpu.l2cache.ReadReq_hits::total 1835554 # number of ReadReq hits 57system.cpu.l2cache.Writeback_hits::writebacks 841020 # number of Writeback hits 58system.cpu.l2cache.Writeback_hits::total 841020 # number of Writeback hits 59system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 60system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits 61system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 62system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 63system.cpu.l2cache.ReadExReq_hits::cpu.data 185546 # number of ReadExReq hits 64system.cpu.l2cache.ReadExReq_hits::total 185546 # number of ReadExReq hits 65system.cpu.l2cache.demand_hits::cpu.inst 1007783 # number of demand (read+write) hits 66system.cpu.l2cache.demand_hits::cpu.data 1013317 # number of demand (read+write) hits 67system.cpu.l2cache.demand_hits::total 2021100 # number of demand (read+write) hits 68system.cpu.l2cache.overall_hits::cpu.inst 1007783 # number of overall hits 69system.cpu.l2cache.overall_hits::cpu.data 1013317 # number of overall hits 70system.cpu.l2cache.overall_hits::total 2021100 # number of overall hits 71system.cpu.l2cache.ReadReq_misses::cpu.inst 15155 # number of ReadReq misses 72system.cpu.l2cache.ReadReq_misses::cpu.data 273854 # number of ReadReq misses 73system.cpu.l2cache.ReadReq_misses::total 289009 # number of ReadReq misses 74system.cpu.l2cache.UpgradeReq_misses::cpu.data 54 # number of UpgradeReq misses 75system.cpu.l2cache.UpgradeReq_misses::total 54 # number of UpgradeReq misses 76system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 77system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 78system.cpu.l2cache.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses 79system.cpu.l2cache.ReadExReq_misses::total 115395 # number of ReadExReq misses 80system.cpu.l2cache.demand_misses::cpu.inst 15155 # number of demand (read+write) misses 81system.cpu.l2cache.demand_misses::cpu.data 389249 # number of demand (read+write) misses 82system.cpu.l2cache.demand_misses::total 404404 # number of demand (read+write) misses 83system.cpu.l2cache.overall_misses::cpu.inst 15155 # number of overall misses 84system.cpu.l2cache.overall_misses::cpu.data 389249 # number of overall misses 85system.cpu.l2cache.overall_misses::total 404404 # number of overall misses 86system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 807128998 # number of ReadReq miss cycles 87system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14259763500 # number of ReadReq miss cycles 88system.cpu.l2cache.ReadReq_miss_latency::total 15066892498 # number of ReadReq miss cycles 89system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 376500 # number of UpgradeReq miss cycles 90system.cpu.l2cache.UpgradeReq_miss_latency::total 376500 # number of UpgradeReq miss cycles 91system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6225363497 # number of ReadExReq miss cycles 92system.cpu.l2cache.ReadExReq_miss_latency::total 6225363497 # number of ReadExReq miss cycles 93system.cpu.l2cache.demand_miss_latency::cpu.inst 807128998 # number of demand (read+write) miss cycles 94system.cpu.l2cache.demand_miss_latency::cpu.data 20485126997 # number of demand (read+write) miss cycles 95system.cpu.l2cache.demand_miss_latency::total 21292255995 # number of demand (read+write) miss cycles 96system.cpu.l2cache.overall_miss_latency::cpu.inst 807128998 # number of overall miss cycles 97system.cpu.l2cache.overall_miss_latency::cpu.data 20485126997 # number of overall miss cycles 98system.cpu.l2cache.overall_miss_latency::total 21292255995 # number of overall miss cycles 99system.cpu.l2cache.ReadReq_accesses::cpu.inst 1022938 # number of ReadReq accesses(hits+misses) 100system.cpu.l2cache.ReadReq_accesses::cpu.data 1101625 # number of ReadReq accesses(hits+misses) 101system.cpu.l2cache.ReadReq_accesses::total 2124563 # number of ReadReq accesses(hits+misses) 102system.cpu.l2cache.Writeback_accesses::writebacks 841020 # number of Writeback accesses(hits+misses) 103system.cpu.l2cache.Writeback_accesses::total 841020 # number of Writeback accesses(hits+misses) 104system.cpu.l2cache.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses) 105system.cpu.l2cache.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses) 106system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 107system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 108system.cpu.l2cache.ReadExReq_accesses::cpu.data 300941 # number of ReadExReq accesses(hits+misses) 109system.cpu.l2cache.ReadExReq_accesses::total 300941 # number of ReadExReq accesses(hits+misses) 110system.cpu.l2cache.demand_accesses::cpu.inst 1022938 # number of demand (read+write) accesses 111system.cpu.l2cache.demand_accesses::cpu.data 1402566 # number of demand (read+write) accesses 112system.cpu.l2cache.demand_accesses::total 2425504 # number of demand (read+write) accesses 113system.cpu.l2cache.overall_accesses::cpu.inst 1022938 # number of overall (read+write) accesses 114system.cpu.l2cache.overall_accesses::cpu.data 1402566 # number of overall (read+write) accesses 115system.cpu.l2cache.overall_accesses::total 2425504 # number of overall (read+write) accesses 116system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014815 # miss rate for ReadReq accesses 117system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248591 # miss rate for ReadReq accesses 118system.cpu.l2cache.ReadReq_miss_rate::total 0.136032 # miss rate for ReadReq accesses 119system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.635294 # miss rate for UpgradeReq accesses 120system.cpu.l2cache.UpgradeReq_miss_rate::total 0.635294 # miss rate for UpgradeReq accesses 121system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 122system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses 123system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383447 # miss rate for ReadExReq accesses 124system.cpu.l2cache.ReadExReq_miss_rate::total 0.383447 # miss rate for ReadExReq accesses 125system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014815 # miss rate for demand accesses 126system.cpu.l2cache.demand_miss_rate::cpu.data 0.277526 # miss rate for demand accesses 127system.cpu.l2cache.demand_miss_rate::total 0.166730 # miss rate for demand accesses 128system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014815 # miss rate for overall accesses 129system.cpu.l2cache.overall_miss_rate::cpu.data 0.277526 # miss rate for overall accesses 130system.cpu.l2cache.overall_miss_rate::total 0.166730 # miss rate for overall accesses 131system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.264467 # average ReadReq miss latency 132system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52070.678172 # average ReadReq miss latency 133system.cpu.l2cache.ReadReq_avg_miss_latency::total 52132.952600 # average ReadReq miss latency 134system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6972.222222 # average UpgradeReq miss latency 135system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6972.222222 # average UpgradeReq miss latency 136system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53948.294961 # average ReadExReq miss latency 137system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53948.294961 # average ReadExReq miss latency 138system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency 139system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency 140system.cpu.l2cache.demand_avg_miss_latency::total 52650.952995 # average overall miss latency 141system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency 142system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency 143system.cpu.l2cache.overall_avg_miss_latency::total 52650.952995 # average overall miss latency 144system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 145system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 146system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 147system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 148system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 149system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 150system.cpu.l2cache.fast_writes 0 # number of fast writes performed 151system.cpu.l2cache.cache_copies 0 # number of cache copies performed 152system.cpu.l2cache.writebacks::writebacks 75968 # number of writebacks 153system.cpu.l2cache.writebacks::total 75968 # number of writebacks 154system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 155system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 156system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 157system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 158system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 159system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 160system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15154 # number of ReadReq MSHR misses 161system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273854 # number of ReadReq MSHR misses 162system.cpu.l2cache.ReadReq_mshr_misses::total 289008 # number of ReadReq MSHR misses 163system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 54 # number of UpgradeReq MSHR misses 164system.cpu.l2cache.UpgradeReq_mshr_misses::total 54 # number of UpgradeReq MSHR misses 165system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 166system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 167system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses 168system.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses 169system.cpu.l2cache.demand_mshr_misses::cpu.inst 15154 # number of demand (read+write) MSHR misses 170system.cpu.l2cache.demand_mshr_misses::cpu.data 389249 # number of demand (read+write) MSHR misses 171system.cpu.l2cache.demand_mshr_misses::total 404403 # number of demand (read+write) MSHR misses 172system.cpu.l2cache.overall_mshr_misses::cpu.inst 15154 # number of overall MSHR misses 173system.cpu.l2cache.overall_mshr_misses::cpu.data 389249 # number of overall MSHR misses 174system.cpu.l2cache.overall_mshr_misses::total 404403 # number of overall MSHR misses 175system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 621904998 # number of ReadReq MSHR miss cycles 176system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10983272500 # number of ReadReq MSHR miss cycles 177system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11605177498 # number of ReadReq MSHR miss cycles 178system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2245000 # number of UpgradeReq MSHR miss cycles 179system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2245000 # number of UpgradeReq MSHR miss cycles 180system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles 181system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles 182system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4831334497 # number of ReadExReq MSHR miss cycles 183system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4831334497 # number of ReadExReq MSHR miss cycles 184system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 621904998 # number of demand (read+write) MSHR miss cycles 185system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15814606997 # number of demand (read+write) MSHR miss cycles 186system.cpu.l2cache.demand_mshr_miss_latency::total 16436511995 # number of demand (read+write) MSHR miss cycles 187system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 621904998 # number of overall MSHR miss cycles 188system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15814606997 # number of overall MSHR miss cycles 189system.cpu.l2cache.overall_mshr_miss_latency::total 16436511995 # number of overall MSHR miss cycles 190system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500 # number of ReadReq MSHR uncacheable cycles 191system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333882500 # number of ReadReq MSHR uncacheable cycles 192system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500 # number of WriteReq MSHR uncacheable cycles 193system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884635500 # number of WriteReq MSHR uncacheable cycles 194system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218518000 # number of overall MSHR uncacheable cycles 195system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218518000 # number of overall MSHR uncacheable cycles 196system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for ReadReq accesses 197system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248591 # mshr miss rate for ReadReq accesses 198system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136032 # mshr miss rate for ReadReq accesses 199system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.635294 # mshr miss rate for UpgradeReq accesses 200system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.635294 # mshr miss rate for UpgradeReq accesses 201system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 202system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses 203system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383447 # mshr miss rate for ReadExReq accesses 204system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383447 # mshr miss rate for ReadExReq accesses 205system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for demand accesses 206system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for demand accesses 207system.cpu.l2cache.demand_mshr_miss_rate::total 0.166729 # mshr miss rate for demand accesses 208system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for overall accesses 209system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for overall accesses 210system.cpu.l2cache.overall_mshr_miss_rate::total 0.166729 # mshr miss rate for overall accesses 211system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472 # average ReadReq mshr miss latency 212system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645 # average ReadReq mshr miss latency 213system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40155.211960 # average ReadReq mshr miss latency 214system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074 # average UpgradeReq mshr miss latency 215system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41574.074074 # average UpgradeReq mshr miss latency 216system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 217system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 218system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539 # average ReadExReq mshr miss latency 219system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41867.797539 # average ReadExReq mshr miss latency 220system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency 221system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency 222system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency 223system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency 224system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency 225system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency 226system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 227system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 228system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 229system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 230system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 231system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 232system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 25system.physmem.num_reads::total 445360 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117542 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117542 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 522594 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13411345 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1429623 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15363562 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 522594 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 522594 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4054841 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4054841 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4054841 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 522594 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13411345 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1429623 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19418402 # Total bandwidth to/from this memory (bytes/s) |
| 233system.iocache.replacements 41685 # number of replacements | 41system.iocache.replacements 41685 # number of replacements |
| 234system.iocache.tagsinuse 1.309507 # Cycle average of tags in use | 42system.iocache.tagsinuse 1.255779 # Cycle average of tags in use |
| 235system.iocache.total_refs 0 # Total number of references to valid blocks. 236system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 237system.iocache.avg_refs 0 # Average number of references to valid blocks. | 43system.iocache.total_refs 0 # Total number of references to valid blocks. 44system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 45system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 238system.iocache.warmup_cycle 1711308479000 # Cycle when the warmup percentage was hit. 239system.iocache.occ_blocks::tsunami.ide 1.309507 # Average occupied blocks per requestor 240system.iocache.occ_percent::tsunami.ide 0.081844 # Average percentage of cache occupancy 241system.iocache.occ_percent::total 0.081844 # Average percentage of cache occupancy | 46system.iocache.warmup_cycle 1706412007000 # Cycle when the warmup percentage was hit. 47system.iocache.occ_blocks::tsunami.ide 1.255779 # Average occupied blocks per requestor 48system.iocache.occ_percent::tsunami.ide 0.078486 # Average percentage of cache occupancy 49system.iocache.occ_percent::total 0.078486 # Average percentage of cache occupancy |
| 242system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 243system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 244system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 245system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 246system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 247system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 248system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 249system.iocache.overall_misses::total 41725 # number of overall misses 250system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 251system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles | 50system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 51system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 52system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 53system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 54system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 55system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 56system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 57system.iocache.overall_misses::total 41725 # number of overall misses 58system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 59system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles |
| 252system.iocache.WriteReq_miss_latency::tsunami.ide 11464497806 # number of WriteReq miss cycles 253system.iocache.WriteReq_miss_latency::total 11464497806 # number of WriteReq miss cycles 254system.iocache.demand_miss_latency::tsunami.ide 11485170804 # number of demand (read+write) miss cycles 255system.iocache.demand_miss_latency::total 11485170804 # number of demand (read+write) miss cycles 256system.iocache.overall_miss_latency::tsunami.ide 11485170804 # number of overall miss cycles 257system.iocache.overall_miss_latency::total 11485170804 # number of overall miss cycles | 60system.iocache.WriteReq_miss_latency::tsunami.ide 11469598806 # number of WriteReq miss cycles 61system.iocache.WriteReq_miss_latency::total 11469598806 # number of WriteReq miss cycles 62system.iocache.demand_miss_latency::tsunami.ide 11490271804 # number of demand (read+write) miss cycles 63system.iocache.demand_miss_latency::total 11490271804 # number of demand (read+write) miss cycles 64system.iocache.overall_miss_latency::tsunami.ide 11490271804 # number of overall miss cycles 65system.iocache.overall_miss_latency::total 11490271804 # number of overall miss cycles |
| 258system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 259system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 260system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 261system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 262system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 263system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 264system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 265system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 266system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 267system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 268system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 269system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 270system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 271system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 272system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 273system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 274system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 275system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency | 66system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 67system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 68system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 69system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 70system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 71system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 72system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 73system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 74system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 75system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 76system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 77system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 78system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 79system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 80system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 81system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 82system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 83system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency |
| 276system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275907.244080 # average WriteReq miss latency 277system.iocache.WriteReq_avg_miss_latency::total 275907.244080 # average WriteReq miss latency 278system.iocache.demand_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency 279system.iocache.demand_avg_miss_latency::total 275258.737064 # average overall miss latency 280system.iocache.overall_avg_miss_latency::tsunami.ide 275258.737064 # average overall miss latency 281system.iocache.overall_avg_miss_latency::total 275258.737064 # average overall miss latency 282system.iocache.blocked_cycles::no_mshrs 199587000 # number of cycles access was blocked | 84system.iocache.WriteReq_avg_miss_latency::tsunami.ide 276030.005920 # average WriteReq miss latency 85system.iocache.WriteReq_avg_miss_latency::total 276030.005920 # average WriteReq miss latency 86system.iocache.demand_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency 87system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency 88system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency 89system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency 90system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked |
| 283system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 91system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 284system.iocache.blocked::no_mshrs 24660 # number of cycles access was blocked | 92system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked |
| 285system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 93system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 286system.iocache.avg_blocked_cycles::no_mshrs 8093.552311 # average number of cycles each access was blocked | 94system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked |
| 287system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 288system.iocache.fast_writes 0 # number of fast writes performed 289system.iocache.cache_copies 0 # number of cache copies performed 290system.iocache.writebacks::writebacks 41512 # number of writebacks 291system.iocache.writebacks::total 41512 # number of writebacks 292system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 293system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 294system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 295system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 296system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 297system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 298system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 299system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 300system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 301system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles | 95system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96system.iocache.fast_writes 0 # number of fast writes performed 97system.iocache.cache_copies 0 # number of cache copies performed 98system.iocache.writebacks::writebacks 41512 # number of writebacks 99system.iocache.writebacks::total 41512 # number of writebacks 100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 102system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 103system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 104system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 105system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 106system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 107system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 109system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles |
| 302system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9303643992 # number of WriteReq MSHR miss cycles 303system.iocache.WriteReq_mshr_miss_latency::total 9303643992 # number of WriteReq MSHR miss cycles 304system.iocache.demand_mshr_miss_latency::tsunami.ide 9315319992 # number of demand (read+write) MSHR miss cycles 305system.iocache.demand_mshr_miss_latency::total 9315319992 # number of demand (read+write) MSHR miss cycles 306system.iocache.overall_mshr_miss_latency::tsunami.ide 9315319992 # number of overall MSHR miss cycles 307system.iocache.overall_mshr_miss_latency::total 9315319992 # number of overall MSHR miss cycles | 110system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles 111system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles 112system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles 113system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles 114system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles 115system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles |
| 308system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 309system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 310system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 311system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 312system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 313system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 314system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 315system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 316system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 317system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency | 116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 118system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 119system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 125system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency |
| 318system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223903.638621 # average WriteReq mshr miss latency 319system.iocache.WriteReq_avg_mshr_miss_latency::total 223903.638621 # average WriteReq mshr miss latency 320system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency 321system.iocache.demand_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency 322system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223255.122636 # average overall mshr miss latency 323system.iocache.overall_avg_mshr_miss_latency::total 223255.122636 # average overall mshr miss latency | 126system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency 127system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency 128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency 129system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency 130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency 131system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency |
| 324system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 325system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 326system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 327system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 328system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 329system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 330system.disk0.dma_write_txs 395 # Number of DMA write transactions. 331system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 332system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 333system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 334system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 335system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 336system.disk2.dma_write_txs 1 # Number of DMA write transactions. 337system.cpu.dtb.fetch_hits 0 # ITB hits 338system.cpu.dtb.fetch_misses 0 # ITB misses 339system.cpu.dtb.fetch_acv 0 # ITB acv 340system.cpu.dtb.fetch_accesses 0 # ITB accesses | 132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 133system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 134system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 135system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 136system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 137system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 138system.disk0.dma_write_txs 395 # Number of DMA write transactions. 139system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 140system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 141system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 142system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 143system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 144system.disk2.dma_write_txs 1 # Number of DMA write transactions. 145system.cpu.dtb.fetch_hits 0 # ITB hits 146system.cpu.dtb.fetch_misses 0 # ITB misses 147system.cpu.dtb.fetch_acv 0 # ITB acv 148system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 341system.cpu.dtb.read_hits 9950205 # DTB read hits 342system.cpu.dtb.read_misses 43861 # DTB read misses 343system.cpu.dtb.read_acv 493 # DTB read access violations 344system.cpu.dtb.read_accesses 957335 # DTB read accesses 345system.cpu.dtb.write_hits 6626699 # DTB write hits 346system.cpu.dtb.write_misses 9966 # DTB write misses 347system.cpu.dtb.write_acv 395 # DTB write access violations 348system.cpu.dtb.write_accesses 340478 # DTB write accesses 349system.cpu.dtb.data_hits 16576904 # DTB hits 350system.cpu.dtb.data_misses 53827 # DTB misses 351system.cpu.dtb.data_acv 888 # DTB access violations 352system.cpu.dtb.data_accesses 1297813 # DTB accesses 353system.cpu.itb.fetch_hits 1339762 # ITB hits 354system.cpu.itb.fetch_misses 37185 # ITB misses 355system.cpu.itb.fetch_acv 1122 # ITB acv 356system.cpu.itb.fetch_accesses 1376947 # ITB accesses | 149system.cpu.dtb.read_hits 9942716 # DTB read hits 150system.cpu.dtb.read_misses 44791 # DTB read misses 151system.cpu.dtb.read_acv 565 # DTB read access violations 152system.cpu.dtb.read_accesses 947396 # DTB read accesses 153system.cpu.dtb.write_hits 6623666 # DTB write hits 154system.cpu.dtb.write_misses 10259 # DTB write misses 155system.cpu.dtb.write_acv 393 # DTB write access violations 156system.cpu.dtb.write_accesses 338396 # DTB write accesses 157system.cpu.dtb.data_hits 16566382 # DTB hits 158system.cpu.dtb.data_misses 55050 # DTB misses 159system.cpu.dtb.data_acv 958 # DTB access violations 160system.cpu.dtb.data_accesses 1285792 # DTB accesses 161system.cpu.itb.fetch_hits 1328947 # ITB hits 162system.cpu.itb.fetch_misses 38142 # ITB misses 163system.cpu.itb.fetch_acv 1080 # ITB acv 164system.cpu.itb.fetch_accesses 1367089 # ITB accesses |
| 357system.cpu.itb.read_hits 0 # DTB read hits 358system.cpu.itb.read_misses 0 # DTB read misses 359system.cpu.itb.read_acv 0 # DTB read access violations 360system.cpu.itb.read_accesses 0 # DTB read accesses 361system.cpu.itb.write_hits 0 # DTB write hits 362system.cpu.itb.write_misses 0 # DTB write misses 363system.cpu.itb.write_acv 0 # DTB write access violations 364system.cpu.itb.write_accesses 0 # DTB write accesses 365system.cpu.itb.data_hits 0 # DTB hits 366system.cpu.itb.data_misses 0 # DTB misses 367system.cpu.itb.data_acv 0 # DTB access violations 368system.cpu.itb.data_accesses 0 # DTB accesses | 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.read_acv 0 # DTB read access violations 168system.cpu.itb.read_accesses 0 # DTB read accesses 169system.cpu.itb.write_hits 0 # DTB write hits 170system.cpu.itb.write_misses 0 # DTB write misses 171system.cpu.itb.write_acv 0 # DTB write access violations 172system.cpu.itb.write_accesses 0 # DTB write accesses 173system.cpu.itb.data_hits 0 # DTB hits 174system.cpu.itb.data_misses 0 # DTB misses 175system.cpu.itb.data_acv 0 # DTB access violations 176system.cpu.itb.data_accesses 0 # DTB accesses |
| 369system.cpu.numCycles 124800831 # number of cpu cycles simulated | 177system.cpu.numCycles 112948398 # number of cpu cycles simulated |
| 370system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 371system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 178system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 179system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 372system.cpu.BPredUnit.lookups 14048431 # Number of BP lookups 373system.cpu.BPredUnit.condPredicted 11726244 # Number of conditional branches predicted 374system.cpu.BPredUnit.condIncorrect 450741 # Number of conditional branches incorrect 375system.cpu.BPredUnit.BTBLookups 10120037 # Number of BTB lookups 376system.cpu.BPredUnit.BTBHits 5916610 # Number of BTB hits | 180system.cpu.BPredUnit.lookups 13966796 # Number of BP lookups 181system.cpu.BPredUnit.condPredicted 11655953 # Number of conditional branches predicted 182system.cpu.BPredUnit.condIncorrect 444631 # Number of conditional branches incorrect 183system.cpu.BPredUnit.BTBLookups 10036743 # Number of BTB lookups 184system.cpu.BPredUnit.BTBHits 5871104 # Number of BTB hits |
| 377system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 185system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 378system.cpu.BPredUnit.usedRAS 938783 # Number of times the RAS was used to get a target. 379system.cpu.BPredUnit.RASInCorrect 45408 # Number of incorrect RAS predictions. 380system.cpu.fetch.icacheStallCycles 31451408 # Number of cycles fetch is stalled on an Icache miss 381system.cpu.fetch.Insts 71430724 # Number of instructions fetch has processed 382system.cpu.fetch.Branches 14048431 # Number of branches that fetch encountered 383system.cpu.fetch.predictedBranches 6855393 # Number of branches that fetch has predicted taken 384system.cpu.fetch.Cycles 13459712 # Number of cycles fetch has run and was not squashing or blocked 385system.cpu.fetch.SquashCycles 2155244 # Number of cycles fetch has spent squashing 386system.cpu.fetch.BlockedCycles 43163669 # Number of cycles fetch has spent blocked 387system.cpu.fetch.MiscStallCycles 32124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 388system.cpu.fetch.PendingTrapStallCycles 276321 # Number of stall cycles due to pending traps 389system.cpu.fetch.PendingQuiesceStallCycles 306226 # Number of stall cycles due to pending quiesce instructions 390system.cpu.fetch.IcacheWaitRetryStallCycles 194 # Number of stall cycles due to full MSHR 391system.cpu.fetch.CacheLines 8835796 # Number of cache lines fetched 392system.cpu.fetch.IcacheSquashes 303984 # Number of outstanding Icache misses that were squashed 393system.cpu.fetch.rateDist::samples 90109445 # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::mean 0.792711 # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::stdev 2.123252 # Number of instructions fetched each cycle (Total) | 186system.cpu.BPredUnit.usedRAS 934424 # Number of times the RAS was used to get a target. 187system.cpu.BPredUnit.RASInCorrect 41946 # Number of incorrect RAS predictions. 188system.cpu.fetch.icacheStallCycles 28374488 # Number of cycles fetch is stalled on an Icache miss 189system.cpu.fetch.Insts 71061459 # Number of instructions fetch has processed 190system.cpu.fetch.Branches 13966796 # Number of branches that fetch encountered 191system.cpu.fetch.predictedBranches 6805528 # Number of branches that fetch has predicted taken 192system.cpu.fetch.Cycles 13370359 # Number of cycles fetch has run and was not squashing or blocked 193system.cpu.fetch.SquashCycles 2059258 # Number of cycles fetch has spent squashing 194system.cpu.fetch.BlockedCycles 37279668 # Number of cycles fetch has spent blocked 195system.cpu.fetch.MiscStallCycles 32466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 196system.cpu.fetch.PendingTrapStallCycles 255422 # Number of stall cycles due to pending traps 197system.cpu.fetch.PendingQuiesceStallCycles 316546 # Number of stall cycles due to pending quiesce instructions 198system.cpu.fetch.IcacheWaitRetryStallCycles 158 # Number of stall cycles due to full MSHR 199system.cpu.fetch.CacheLines 8741472 # Number of cache lines fetched 200system.cpu.fetch.IcacheSquashes 286615 # Number of outstanding Icache misses that were squashed 201system.cpu.fetch.rateDist::samples 80977441 # Number of instructions fetched each cycle (Total) 202system.cpu.fetch.rateDist::mean 0.877546 # Number of instructions fetched each cycle (Total) 203system.cpu.fetch.rateDist::stdev 2.218344 # Number of instructions fetched each cycle (Total) |
| 396system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 204system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 397system.cpu.fetch.rateDist::0 76649733 85.06% 85.06% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::1 882120 0.98% 86.04% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::2 1758761 1.95% 87.99% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::3 855148 0.95% 88.94% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::4 2774809 3.08% 92.02% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::5 597111 0.66% 92.68% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::6 671452 0.75% 93.43% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::7 1010353 1.12% 94.55% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::8 4909958 5.45% 100.00% # Number of instructions fetched each cycle (Total) | 205system.cpu.fetch.rateDist::0 67607082 83.49% 83.49% # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::1 875013 1.08% 84.57% # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::2 1738431 2.15% 86.72% # Number of instructions fetched each cycle (Total) 208system.cpu.fetch.rateDist::3 848390 1.05% 87.76% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::4 2741333 3.39% 91.15% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::5 593371 0.73% 91.88% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::6 672322 0.83% 92.71% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::7 1013697 1.25% 93.96% # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::8 4887802 6.04% 100.00% # Number of instructions fetched each cycle (Total) |
| 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 214system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 409system.cpu.fetch.rateDist::total 90109445 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.branchRate 0.112567 # Number of branch fetches per cycle 411system.cpu.fetch.rate 0.572358 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 32486072 # Number of cycles decode is idle 413system.cpu.decode.BlockedCycles 42966960 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 12232972 # Number of cycles decode is running 415system.cpu.decode.UnblockCycles 1046401 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 1377039 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 612715 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 43176 # Number of times decode detected a branch misprediction 419system.cpu.decode.DecodedInsts 70146735 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 131924 # Number of squashed instructions handled by decode 421system.cpu.rename.SquashCycles 1377039 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 33631618 # Number of cycles rename is idle 423system.cpu.rename.BlockCycles 17301504 # Number of cycles rename is blocking 424system.cpu.rename.serializeStallCycles 21458473 # count of cycles rename stalled for serializing inst 425system.cpu.rename.RunCycles 11517889 # Number of cycles rename is running 426system.cpu.rename.UnblockCycles 4822920 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 66414787 # Number of instructions processed by rename 428system.cpu.rename.ROBFullEvents 7289 # Number of times rename has blocked due to ROB full 429system.cpu.rename.IQFullEvents 750703 # Number of times rename has blocked due to IQ full 430system.cpu.rename.LSQFullEvents 1791896 # Number of times rename has blocked due to LSQ full 431system.cpu.rename.RenamedOperands 44375645 # Number of destination operands rename has renamed 432system.cpu.rename.RenameLookups 80516952 # Number of register rename lookups that rename has made 433system.cpu.rename.int_rename_lookups 80027527 # Number of integer rename lookups 434system.cpu.rename.fp_rename_lookups 489425 # Number of floating rename lookups 435system.cpu.rename.CommittedMaps 38131021 # Number of HB maps that are committed 436system.cpu.rename.UndoneMaps 6244616 # Number of HB maps that are undone due to squashing 437system.cpu.rename.serializingInsts 1698641 # count of serializing insts renamed 438system.cpu.rename.tempSerializingInsts 251106 # count of temporary serializing insts renamed 439system.cpu.rename.skidInsts 12735763 # count of insts added to the skid buffer 440system.cpu.memDep0.insertedLoads 10548926 # Number of loads inserted to the mem dependence unit. 441system.cpu.memDep0.insertedStores 6961519 # Number of stores inserted to the mem dependence unit. 442system.cpu.memDep0.conflictingLoads 1298320 # Number of conflicting loads. 443system.cpu.memDep0.conflictingStores 905557 # Number of conflicting stores. 444system.cpu.iq.iqInstsAdded 58829539 # Number of instructions added to the IQ (excludes non-spec) 445system.cpu.iq.iqNonSpecInstsAdded 2094293 # Number of non-speculative instructions added to the IQ 446system.cpu.iq.iqInstsIssued 57137234 # Number of instructions issued 447system.cpu.iq.iqSquashedInstsIssued 128634 # Number of squashed instructions issued 448system.cpu.iq.iqSquashedInstsExamined 7593303 # Number of squashed instructions iterated over during squash; mainly for profiling 449system.cpu.iq.iqSquashedOperandsExamined 3942261 # Number of squashed operands that are examined and possibly removed from graph 450system.cpu.iq.iqSquashedNonSpecRemoved 1428853 # Number of squashed non-spec instructions that were removed 451system.cpu.iq.issued_per_cycle::samples 90109445 # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::mean 0.634087 # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::stdev 1.284474 # Number of insts issued each cycle | 217system.cpu.fetch.rateDist::total 80977441 # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.branchRate 0.123656 # Number of branch fetches per cycle 219system.cpu.fetch.rate 0.629150 # Number of inst fetches per cycle 220system.cpu.decode.IdleCycles 29512235 # Number of cycles decode is idle 221system.cpu.decode.BlockedCycles 36965653 # Number of cycles decode is blocked 222system.cpu.decode.RunCycles 12232048 # Number of cycles decode is running 223system.cpu.decode.UnblockCycles 961909 # Number of cycles decode is unblocking 224system.cpu.decode.SquashCycles 1305595 # Number of cycles decode is squashing 225system.cpu.decode.BranchResolved 610411 # Number of times decode resolved a branch 226system.cpu.decode.BranchMispred 43204 # Number of times decode detected a branch misprediction 227system.cpu.decode.DecodedInsts 69782793 # Number of instructions handled by decode 228system.cpu.decode.SquashedInsts 129607 # Number of squashed instructions handled by decode 229system.cpu.rename.SquashCycles 1305595 # Number of cycles rename is squashing 230system.cpu.rename.IdleCycles 30617338 # Number of cycles rename is idle 231system.cpu.rename.BlockCycles 13493069 # Number of cycles rename is blocking 232system.cpu.rename.serializeStallCycles 19707624 # count of cycles rename stalled for serializing inst 233system.cpu.rename.RunCycles 11473805 # Number of cycles rename is running 234system.cpu.rename.UnblockCycles 4380008 # Number of cycles rename is unblocking 235system.cpu.rename.RenamedInsts 66097462 # Number of instructions processed by rename 236system.cpu.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full 237system.cpu.rename.IQFullEvents 499537 # Number of times rename has blocked due to IQ full 238system.cpu.rename.LSQFullEvents 1599586 # Number of times rename has blocked due to LSQ full 239system.cpu.rename.RenamedOperands 44156593 # Number of destination operands rename has renamed 240system.cpu.rename.RenameLookups 80173165 # Number of register rename lookups that rename has made 241system.cpu.rename.int_rename_lookups 79693699 # Number of integer rename lookups 242system.cpu.rename.fp_rename_lookups 479466 # Number of floating rename lookups 243system.cpu.rename.CommittedMaps 38191541 # Number of HB maps that are committed 244system.cpu.rename.UndoneMaps 5965044 # Number of HB maps that are undone due to squashing 245system.cpu.rename.serializingInsts 1694326 # count of serializing insts renamed 246system.cpu.rename.tempSerializingInsts 247806 # count of temporary serializing insts renamed 247system.cpu.rename.skidInsts 12010371 # count of insts added to the skid buffer 248system.cpu.memDep0.insertedLoads 10525116 # Number of loads inserted to the mem dependence unit. 249system.cpu.memDep0.insertedStores 6937010 # Number of stores inserted to the mem dependence unit. 250system.cpu.memDep0.conflictingLoads 1314782 # Number of conflicting loads. 251system.cpu.memDep0.conflictingStores 853291 # Number of conflicting stores. 252system.cpu.iq.iqInstsAdded 58559009 # Number of instructions added to the IQ (excludes non-spec) 253system.cpu.iq.iqNonSpecInstsAdded 2080853 # Number of non-speculative instructions added to the IQ 254system.cpu.iq.iqInstsIssued 57074473 # Number of instructions issued 255system.cpu.iq.iqSquashedInstsIssued 118261 # Number of squashed instructions issued 256system.cpu.iq.iqSquashedInstsExamined 7262069 # Number of squashed instructions iterated over during squash; mainly for profiling 257system.cpu.iq.iqSquashedOperandsExamined 3652702 # Number of squashed operands that are examined and possibly removed from graph 258system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed 259system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle 260system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle |
| 454system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 262system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 455system.cpu.iq.issued_per_cycle::0 64286768 71.34% 71.34% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::1 11995743 13.31% 84.66% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::2 5355125 5.94% 90.60% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::3 3438365 3.82% 94.41% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::4 2611846 2.90% 97.31% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::5 1326020 1.47% 98.78% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::6 685055 0.76% 99.54% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::7 355852 0.39% 99.94% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::8 54671 0.06% 100.00% # Number of insts issued each cycle | 263system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::7 333678 0.41% 99.88% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::8 95243 0.12% 100.00% # Number of insts issued each cycle |
| 464system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 272system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 467system.cpu.iq.issued_per_cycle::total 90109445 # Number of insts issued each cycle | 275system.cpu.iq.issued_per_cycle::total 80977441 # Number of insts issued each cycle |
| 468system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 276system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 469system.cpu.iq.fu_full::IntAlu 75508 9.96% 9.96% # attempts to use FU when none available 470system.cpu.iq.fu_full::IntMult 0 0.00% 9.96% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntDiv 0 0.00% 9.96% # attempts to use FU when none available 472system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.96% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.96% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.96% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatMult 0 0.00% 9.96% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.96% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.96% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.96% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.96% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.96% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.96% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.96% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.96% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdMult 0 0.00% 9.96% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.96% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdShift 0 0.00% 9.96% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.96% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.96% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.96% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.96% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.96% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.96% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.96% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.96% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.96% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.96% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.96% # attempts to use FU when none available 498system.cpu.iq.fu_full::MemRead 363265 47.93% 57.90% # attempts to use FU when none available 499system.cpu.iq.fu_full::MemWrite 319103 42.10% 100.00% # attempts to use FU when none available | 277system.cpu.iq.fu_full::IntAlu 88366 11.20% 11.20% # attempts to use FU when none available 278system.cpu.iq.fu_full::IntMult 0 0.00% 11.20% # attempts to use FU when none available 279system.cpu.iq.fu_full::IntDiv 0 0.00% 11.20% # attempts to use FU when none available 280system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.20% # attempts to use FU when none available 281system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.20% # attempts to use FU when none available 282system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.20% # attempts to use FU when none available 283system.cpu.iq.fu_full::FloatMult 0 0.00% 11.20% # attempts to use FU when none available 284system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.20% # attempts to use FU when none available 285system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.20% # attempts to use FU when none available 286system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.20% # attempts to use FU when none available 287system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.20% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.20% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.20% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.20% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.20% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdMult 0 0.00% 11.20% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.20% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdShift 0 0.00% 11.20% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.20% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.20% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.20% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.20% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.20% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.20% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.20% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.20% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.20% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.20% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.20% # attempts to use FU when none available 306system.cpu.iq.fu_full::MemRead 374779 47.48% 58.68% # attempts to use FU when none available 307system.cpu.iq.fu_full::MemWrite 326184 41.32% 100.00% # attempts to use FU when none available |
| 500system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 501system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 308system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 309system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 502system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued 503system.cpu.iq.FU_type_0::IntAlu 38991069 68.24% 68.25% # Type of FU issued 504system.cpu.iq.FU_type_0::IntMult 61859 0.11% 68.36% # Type of FU issued 505system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.36% # Type of FU issued 506system.cpu.iq.FU_type_0::FloatAdd 25608 0.04% 68.41% # Type of FU issued 507system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.41% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.41% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.41% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.41% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.41% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.41% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.41% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.41% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.41% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.41% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.41% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.41% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.41% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.41% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.41% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.41% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.41% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.41% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.41% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.41% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.41% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.41% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued 532system.cpu.iq.FU_type_0::MemRead 10392240 18.19% 86.60% # Type of FU issued 533system.cpu.iq.FU_type_0::MemWrite 6705676 11.74% 98.34% # Type of FU issued 534system.cpu.iq.FU_type_0::IprAccess 949855 1.66% 100.00% # Type of FU issued | 310system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 311system.cpu.iq.FU_type_0::IntAlu 38932323 68.21% 68.23% # Type of FU issued 312system.cpu.iq.FU_type_0::IntMult 61748 0.11% 68.33% # Type of FU issued 313system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.33% # Type of FU issued 314system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.38% # Type of FU issued 315system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.38% # Type of FU issued 316system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.38% # Type of FU issued 317system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.38% # Type of FU issued 318system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued 319system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued 320system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.39% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.39% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.39% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.39% # Type of FU issued 340system.cpu.iq.FU_type_0::MemRead 10391482 18.21% 86.59% # Type of FU issued 341system.cpu.iq.FU_type_0::MemWrite 6703636 11.75% 98.34% # Type of FU issued 342system.cpu.iq.FU_type_0::IprAccess 948755 1.66% 100.00% # Type of FU issued |
| 535system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 343system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 536system.cpu.iq.FU_type_0::total 57137234 # Type of FU issued 537system.cpu.iq.rate 0.457827 # Inst issue rate 538system.cpu.iq.fu_busy_cnt 757876 # FU busy when requested 539system.cpu.iq.fu_busy_rate 0.013264 # FU busy rate (busy events/executed inst) 540system.cpu.iq.int_inst_queue_reads 204573341 # Number of integer instruction queue reads 541system.cpu.iq.int_inst_queue_writes 68190814 # Number of integer instruction queue writes 542system.cpu.iq.int_inst_queue_wakeup_accesses 55847999 # Number of integer instruction queue wakeup accesses 543system.cpu.iq.fp_inst_queue_reads 697081 # Number of floating instruction queue reads 544system.cpu.iq.fp_inst_queue_writes 339930 # Number of floating instruction queue writes 545system.cpu.iq.fp_inst_queue_wakeup_accesses 327759 # Number of floating instruction queue wakeup accesses 546system.cpu.iq.int_alu_accesses 57523312 # Number of integer alu accesses 547system.cpu.iq.fp_alu_accesses 364507 # Number of floating point alu accesses 548system.cpu.iew.lsq.thread0.forwLoads 597966 # Number of loads that had data forwarded from stores | 344system.cpu.iq.FU_type_0::total 57074473 # Type of FU issued 345system.cpu.iq.rate 0.505315 # Inst issue rate 346system.cpu.iq.fu_busy_cnt 789329 # FU busy when requested 347system.cpu.iq.fu_busy_rate 0.013830 # FU busy rate (busy events/executed inst) 348system.cpu.iq.int_inst_queue_reads 195341432 # Number of integer instruction queue reads 349system.cpu.iq.int_inst_queue_writes 67578548 # Number of integer instruction queue writes 350system.cpu.iq.int_inst_queue_wakeup_accesses 55793685 # Number of integer instruction queue wakeup accesses 351system.cpu.iq.fp_inst_queue_reads 692544 # Number of floating instruction queue reads 352system.cpu.iq.fp_inst_queue_writes 336641 # Number of floating instruction queue writes 353system.cpu.iq.fp_inst_queue_wakeup_accesses 327847 # Number of floating instruction queue wakeup accesses 354system.cpu.iq.int_alu_accesses 57495160 # Number of integer alu accesses 355system.cpu.iq.fp_alu_accesses 361356 # Number of floating point alu accesses 356system.cpu.iew.lsq.thread0.forwLoads 596122 # Number of loads that had data forwarded from stores |
| 549system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 357system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 550system.cpu.iew.lsq.thread0.squashedLoads 1464590 # Number of loads squashed 551system.cpu.iew.lsq.thread0.ignoredResponses 2710 # Number of memory responses ignored because the instruction is squashed 552system.cpu.iew.lsq.thread0.memOrderViolation 13959 # Number of memory ordering violations 553system.cpu.iew.lsq.thread0.squashedStores 585881 # Number of stores squashed | 358system.cpu.iew.lsq.thread0.squashedLoads 1429701 # Number of loads squashed 359system.cpu.iew.lsq.thread0.ignoredResponses 3754 # Number of memory responses ignored because the instruction is squashed 360system.cpu.iew.lsq.thread0.memOrderViolation 13594 # Number of memory ordering violations 361system.cpu.iew.lsq.thread0.squashedStores 555558 # Number of stores squashed |
| 554system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 555system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 362system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 363system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 556system.cpu.iew.lsq.thread0.rescheduledLoads 18028 # Number of loads that were rescheduled 557system.cpu.iew.lsq.thread0.cacheBlocked 111488 # Number of times an access to memory failed due to the cache being blocked | 364system.cpu.iew.lsq.thread0.rescheduledLoads 17950 # Number of loads that were rescheduled 365system.cpu.iew.lsq.thread0.cacheBlocked 159161 # Number of times an access to memory failed due to the cache being blocked |
| 558system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 366system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 559system.cpu.iew.iewSquashCycles 1377039 # Number of cycles IEW is squashing 560system.cpu.iew.iewBlockCycles 12355921 # Number of cycles IEW is blocking 561system.cpu.iew.iewUnblockCycles 868580 # Number of cycles IEW is unblocking 562system.cpu.iew.iewDispatchedInsts 64490760 # Number of instructions dispatched to IQ 563system.cpu.iew.iewDispSquashedInsts 689025 # Number of squashed instructions skipped by dispatch 564system.cpu.iew.iewDispLoadInsts 10548926 # Number of dispatched load instructions 565system.cpu.iew.iewDispStoreInsts 6961519 # Number of dispatched store instructions 566system.cpu.iew.iewDispNonSpecInsts 1842879 # Number of dispatched non-speculative instructions 567system.cpu.iew.iewIQFullEvents 620807 # Number of times the IQ has become full, causing a stall 568system.cpu.iew.iewLSQFullEvents 12564 # Number of times the LSQ has become full, causing a stall 569system.cpu.iew.memOrderViolationEvents 13959 # Number of memory order violations 570system.cpu.iew.predictedTakenIncorrect 241262 # Number of branches that were predicted taken incorrectly 571system.cpu.iew.predictedNotTakenIncorrect 422502 # Number of branches that were predicted not taken incorrectly 572system.cpu.iew.branchMispredicts 663764 # Number of branch mispredicts detected at execute 573system.cpu.iew.iewExecutedInsts 56606739 # Number of executed instructions 574system.cpu.iew.iewExecLoadInsts 10022317 # Number of load instructions executed 575system.cpu.iew.iewExecSquashedInsts 530494 # Number of squashed instructions skipped in execute | 367system.cpu.iew.iewSquashCycles 1305595 # Number of cycles IEW is squashing 368system.cpu.iew.iewBlockCycles 9769239 # Number of cycles IEW is blocking 369system.cpu.iew.iewUnblockCycles 682868 # Number of cycles IEW is unblocking 370system.cpu.iew.iewDispatchedInsts 64195167 # Number of instructions dispatched to IQ 371system.cpu.iew.iewDispSquashedInsts 659293 # Number of squashed instructions skipped by dispatch 372system.cpu.iew.iewDispLoadInsts 10525116 # Number of dispatched load instructions 373system.cpu.iew.iewDispStoreInsts 6937010 # Number of dispatched store instructions 374system.cpu.iew.iewDispNonSpecInsts 1832536 # Number of dispatched non-speculative instructions 375system.cpu.iew.iewIQFullEvents 511952 # Number of times the IQ has become full, causing a stall 376system.cpu.iew.iewLSQFullEvents 18439 # Number of times the LSQ has become full, causing a stall 377system.cpu.iew.memOrderViolationEvents 13594 # Number of memory order violations 378system.cpu.iew.predictedTakenIncorrect 242380 # Number of branches that were predicted taken incorrectly 379system.cpu.iew.predictedNotTakenIncorrect 420357 # Number of branches that were predicted not taken incorrectly 380system.cpu.iew.branchMispredicts 662737 # Number of branch mispredicts detected at execute 381system.cpu.iew.iewExecutedInsts 56550869 # Number of executed instructions 382system.cpu.iew.iewExecLoadInsts 10016393 # Number of load instructions executed 383system.cpu.iew.iewExecSquashedInsts 523603 # Number of squashed instructions skipped in execute |
| 576system.cpu.iew.exec_swp 0 # number of swp insts executed | 384system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 577system.cpu.iew.exec_nop 3566928 # number of nop insts executed 578system.cpu.iew.exec_refs 16674247 # number of memory reference insts executed 579system.cpu.iew.exec_branches 8979744 # Number of branches executed 580system.cpu.iew.exec_stores 6651930 # Number of stores executed 581system.cpu.iew.exec_rate 0.453577 # Inst execution rate 582system.cpu.iew.wb_sent 56287349 # cumulative count of insts sent to commit 583system.cpu.iew.wb_count 56175758 # cumulative count of insts written-back 584system.cpu.iew.wb_producers 27690548 # num instructions producing a value 585system.cpu.iew.wb_consumers 37534692 # num instructions consuming a value | 385system.cpu.iew.exec_nop 3555305 # number of nop insts executed 386system.cpu.iew.exec_refs 16665522 # number of memory reference insts executed 387system.cpu.iew.exec_branches 8969939 # Number of branches executed 388system.cpu.iew.exec_stores 6649129 # Number of stores executed 389system.cpu.iew.exec_rate 0.500679 # Inst execution rate 390system.cpu.iew.wb_sent 56244022 # cumulative count of insts sent to commit 391system.cpu.iew.wb_count 56121532 # cumulative count of insts written-back 392system.cpu.iew.wb_producers 27804186 # num instructions producing a value 393system.cpu.iew.wb_consumers 37617732 # num instructions consuming a value |
| 586system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 394system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 587system.cpu.iew.wb_rate 0.450123 # insts written-back per cycle 588system.cpu.iew.wb_fanout 0.737732 # average fanout of values written-back | 395system.cpu.iew.wb_rate 0.496878 # insts written-back per cycle 396system.cpu.iew.wb_fanout 0.739124 # average fanout of values written-back |
| 589system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 397system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 590system.cpu.commit.commitSquashedInsts 8267625 # The number of squashed insts skipped by commit 591system.cpu.commit.commitNonSpecStalls 665440 # The number of times commit has been forced to stall to communicate backwards 592system.cpu.commit.branchMispredicts 619184 # The number of times a branch was mispredicted 593system.cpu.commit.committed_per_cycle::samples 88732406 # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::mean 0.632394 # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::stdev 1.547937 # Number of insts commited each cycle | 398system.cpu.commit.commitSquashedInsts 7890216 # The number of squashed insts skipped by commit 399system.cpu.commit.commitNonSpecStalls 664845 # The number of times commit has been forced to stall to communicate backwards 400system.cpu.commit.branchMispredicts 612833 # The number of times a branch was mispredicted 401system.cpu.commit.committed_per_cycle::samples 79671846 # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::mean 0.705254 # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::stdev 1.627009 # Number of insts commited each cycle |
| 596system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 404system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 597system.cpu.commit.committed_per_cycle::0 67542246 76.12% 76.12% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::1 8923750 10.06% 86.18% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::2 4811841 5.42% 91.60% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::3 2594320 2.92% 94.52% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::4 1447946 1.63% 96.15% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::5 597901 0.67% 96.83% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::6 519027 0.58% 97.41% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::7 475014 0.54% 97.95% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::8 1820361 2.05% 100.00% # Number of insts commited each cycle | 405system.cpu.commit.committed_per_cycle::0 58664724 73.63% 73.63% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::1 8821985 11.07% 84.71% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::2 4676702 5.87% 90.58% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::3 2526569 3.17% 93.75% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::4 1499177 1.88% 95.63% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::5 615140 0.77% 96.40% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::6 529950 0.67% 97.07% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::7 519091 0.65% 97.72% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::8 1818508 2.28% 100.00% # Number of insts commited each cycle |
| 606system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 414system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 609system.cpu.commit.committed_per_cycle::total 88732406 # Number of insts commited each cycle 610system.cpu.commit.committedInsts 56113829 # Number of instructions committed 611system.cpu.commit.committedOps 56113829 # Number of ops (including micro ops) committed | 417system.cpu.commit.committed_per_cycle::total 79671846 # Number of insts commited each cycle 418system.cpu.commit.committedInsts 56188905 # Number of instructions committed 419system.cpu.commit.committedOps 56188905 # Number of ops (including micro ops) committed |
| 612system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 420system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 613system.cpu.commit.refs 15459974 # Number of memory references committed 614system.cpu.commit.loads 9084336 # Number of loads committed 615system.cpu.commit.membars 226495 # Number of memory barriers committed 616system.cpu.commit.branches 8440914 # Number of branches committed | 421system.cpu.commit.refs 15476867 # Number of memory references committed 422system.cpu.commit.loads 9095415 # Number of loads committed 423system.cpu.commit.membars 226300 # Number of memory barriers committed 424system.cpu.commit.branches 8447820 # Number of branches committed |
| 617system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 425system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 618system.cpu.commit.int_insts 51962143 # Number of committed integer instructions. 619system.cpu.commit.function_calls 739769 # Number of function calls committed. 620system.cpu.commit.bw_lim_events 1820361 # number cycles where commit BW limit reached | 426system.cpu.commit.int_insts 52034961 # Number of committed integer instructions. 427system.cpu.commit.function_calls 740468 # Number of function calls committed. 428system.cpu.commit.bw_lim_events 1818508 # number cycles where commit BW limit reached |
| 621system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 429system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 622system.cpu.rob.rob_reads 151043798 # The number of ROB reads 623system.cpu.rob.rob_writes 130140767 # The number of ROB writes 624system.cpu.timesIdled 1385278 # Number of times that the entire CPU went into an idle state and unscheduled itself 625system.cpu.idleCycles 34691386 # Total number of cycles that the CPU has spent unscheduled due to idling 626system.cpu.quiesceCycles 3609940555 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 627system.cpu.committedInsts 52926469 # Number of Instructions Simulated 628system.cpu.committedOps 52926469 # Number of Ops (including micro ops) Simulated 629system.cpu.committedInsts_total 52926469 # Number of Instructions Simulated 630system.cpu.cpi 2.358004 # CPI: Cycles Per Instruction 631system.cpu.cpi_total 2.358004 # CPI: Total CPI of All Threads 632system.cpu.ipc 0.424087 # IPC: Instructions Per Cycle 633system.cpu.ipc_total 0.424087 # IPC: Total IPC of All Threads 634system.cpu.int_regfile_reads 74197467 # number of integer regfile reads 635system.cpu.int_regfile_writes 40518410 # number of integer regfile writes 636system.cpu.fp_regfile_reads 166390 # number of floating regfile reads 637system.cpu.fp_regfile_writes 166940 # number of floating regfile writes 638system.cpu.misc_regfile_reads 1995246 # number of misc regfile reads 639system.cpu.misc_regfile_writes 947641 # number of misc regfile writes | 430system.cpu.rob.rob_reads 141682968 # The number of ROB reads 431system.cpu.rob.rob_writes 129465441 # The number of ROB writes 432system.cpu.timesIdled 1179964 # Number of times that the entire CPU went into an idle state and unscheduled itself 433system.cpu.idleCycles 31970957 # Total number of cycles that the CPU has spent unscheduled due to idling 434system.cpu.quiesceCycles 3597518061 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 435system.cpu.committedInsts 52998368 # Number of Instructions Simulated 436system.cpu.committedOps 52998368 # Number of Ops (including micro ops) Simulated 437system.cpu.committedInsts_total 52998368 # Number of Instructions Simulated 438system.cpu.cpi 2.131167 # CPI: Cycles Per Instruction 439system.cpu.cpi_total 2.131167 # CPI: Total CPI of All Threads 440system.cpu.ipc 0.469226 # IPC: Instructions Per Cycle 441system.cpu.ipc_total 0.469226 # IPC: Total IPC of All Threads 442system.cpu.int_regfile_reads 74144483 # number of integer regfile reads 443system.cpu.int_regfile_writes 40484328 # number of integer regfile writes 444system.cpu.fp_regfile_reads 165992 # number of floating regfile reads 445system.cpu.fp_regfile_writes 167427 # number of floating regfile writes 446system.cpu.misc_regfile_reads 1993361 # number of misc regfile reads 447system.cpu.misc_regfile_writes 946826 # number of misc regfile writes |
| 640system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 641system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 642system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 643system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 644system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 645system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 646system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 647system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 663system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 664system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 665system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 666system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 667system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 668system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 669system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 670system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 448system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 449system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 450system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 451system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 452system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 453system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 454system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 455system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 471system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 472system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 473system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 474system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 475system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 476system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 477system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 478system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 671system.cpu.icache.replacements 1022327 # number of replacements 672system.cpu.icache.tagsinuse 509.956829 # Cycle average of tags in use 673system.cpu.icache.total_refs 7752117 # Total number of references to valid blocks. 674system.cpu.icache.sampled_refs 1022838 # Sample count of references to valid blocks. 675system.cpu.icache.avg_refs 7.579027 # Average number of references to valid blocks. 676system.cpu.icache.warmup_cycle 23896694000 # Cycle when the warmup percentage was hit. 677system.cpu.icache.occ_blocks::cpu.inst 509.956829 # Average occupied blocks per requestor 678system.cpu.icache.occ_percent::cpu.inst 0.996009 # Average percentage of cache occupancy 679system.cpu.icache.occ_percent::total 0.996009 # Average percentage of cache occupancy 680system.cpu.icache.ReadReq_hits::cpu.inst 7752118 # number of ReadReq hits 681system.cpu.icache.ReadReq_hits::total 7752118 # number of ReadReq hits 682system.cpu.icache.demand_hits::cpu.inst 7752118 # number of demand (read+write) hits 683system.cpu.icache.demand_hits::total 7752118 # number of demand (read+write) hits 684system.cpu.icache.overall_hits::cpu.inst 7752118 # number of overall hits 685system.cpu.icache.overall_hits::total 7752118 # number of overall hits 686system.cpu.icache.ReadReq_misses::cpu.inst 1083676 # number of ReadReq misses 687system.cpu.icache.ReadReq_misses::total 1083676 # number of ReadReq misses 688system.cpu.icache.demand_misses::cpu.inst 1083676 # number of demand (read+write) misses 689system.cpu.icache.demand_misses::total 1083676 # number of demand (read+write) misses 690system.cpu.icache.overall_misses::cpu.inst 1083676 # number of overall misses 691system.cpu.icache.overall_misses::total 1083676 # number of overall misses 692system.cpu.icache.ReadReq_miss_latency::cpu.inst 17473525489 # number of ReadReq miss cycles 693system.cpu.icache.ReadReq_miss_latency::total 17473525489 # number of ReadReq miss cycles 694system.cpu.icache.demand_miss_latency::cpu.inst 17473525489 # number of demand (read+write) miss cycles 695system.cpu.icache.demand_miss_latency::total 17473525489 # number of demand (read+write) miss cycles 696system.cpu.icache.overall_miss_latency::cpu.inst 17473525489 # number of overall miss cycles 697system.cpu.icache.overall_miss_latency::total 17473525489 # number of overall miss cycles 698system.cpu.icache.ReadReq_accesses::cpu.inst 8835794 # number of ReadReq accesses(hits+misses) 699system.cpu.icache.ReadReq_accesses::total 8835794 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.demand_accesses::cpu.inst 8835794 # number of demand (read+write) accesses 701system.cpu.icache.demand_accesses::total 8835794 # number of demand (read+write) accesses 702system.cpu.icache.overall_accesses::cpu.inst 8835794 # number of overall (read+write) accesses 703system.cpu.icache.overall_accesses::total 8835794 # number of overall (read+write) accesses 704system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122646 # miss rate for ReadReq accesses 705system.cpu.icache.ReadReq_miss_rate::total 0.122646 # miss rate for ReadReq accesses 706system.cpu.icache.demand_miss_rate::cpu.inst 0.122646 # miss rate for demand accesses 707system.cpu.icache.demand_miss_rate::total 0.122646 # miss rate for demand accesses 708system.cpu.icache.overall_miss_rate::cpu.inst 0.122646 # miss rate for overall accesses 709system.cpu.icache.overall_miss_rate::total 0.122646 # miss rate for overall accesses 710system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16124.307901 # average ReadReq miss latency 711system.cpu.icache.ReadReq_avg_miss_latency::total 16124.307901 # average ReadReq miss latency 712system.cpu.icache.demand_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency 713system.cpu.icache.demand_avg_miss_latency::total 16124.307901 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::cpu.inst 16124.307901 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::total 16124.307901 # average overall miss latency 716system.cpu.icache.blocked_cycles::no_mshrs 1701496 # number of cycles access was blocked | 479system.cpu.icache.replacements 1020348 # number of replacements 480system.cpu.icache.tagsinuse 510.019758 # Cycle average of tags in use 481system.cpu.icache.total_refs 7661720 # Total number of references to valid blocks. 482system.cpu.icache.sampled_refs 1020856 # Sample count of references to valid blocks. 483system.cpu.icache.avg_refs 7.505192 # Average number of references to valid blocks. 484system.cpu.icache.warmup_cycle 22969954000 # Cycle when the warmup percentage was hit. 485system.cpu.icache.occ_blocks::cpu.inst 510.019758 # Average occupied blocks per requestor 486system.cpu.icache.occ_percent::cpu.inst 0.996132 # Average percentage of cache occupancy 487system.cpu.icache.occ_percent::total 0.996132 # Average percentage of cache occupancy 488system.cpu.icache.ReadReq_hits::cpu.inst 7661721 # number of ReadReq hits 489system.cpu.icache.ReadReq_hits::total 7661721 # number of ReadReq hits 490system.cpu.icache.demand_hits::cpu.inst 7661721 # number of demand (read+write) hits 491system.cpu.icache.demand_hits::total 7661721 # number of demand (read+write) hits 492system.cpu.icache.overall_hits::cpu.inst 7661721 # number of overall hits 493system.cpu.icache.overall_hits::total 7661721 # number of overall hits 494system.cpu.icache.ReadReq_misses::cpu.inst 1079749 # number of ReadReq misses 495system.cpu.icache.ReadReq_misses::total 1079749 # number of ReadReq misses 496system.cpu.icache.demand_misses::cpu.inst 1079749 # number of demand (read+write) misses 497system.cpu.icache.demand_misses::total 1079749 # number of demand (read+write) misses 498system.cpu.icache.overall_misses::cpu.inst 1079749 # number of overall misses 499system.cpu.icache.overall_misses::total 1079749 # number of overall misses 500system.cpu.icache.ReadReq_miss_latency::cpu.inst 14523691994 # number of ReadReq miss cycles 501system.cpu.icache.ReadReq_miss_latency::total 14523691994 # number of ReadReq miss cycles 502system.cpu.icache.demand_miss_latency::cpu.inst 14523691994 # number of demand (read+write) miss cycles 503system.cpu.icache.demand_miss_latency::total 14523691994 # number of demand (read+write) miss cycles 504system.cpu.icache.overall_miss_latency::cpu.inst 14523691994 # number of overall miss cycles 505system.cpu.icache.overall_miss_latency::total 14523691994 # number of overall miss cycles 506system.cpu.icache.ReadReq_accesses::cpu.inst 8741470 # number of ReadReq accesses(hits+misses) 507system.cpu.icache.ReadReq_accesses::total 8741470 # number of ReadReq accesses(hits+misses) 508system.cpu.icache.demand_accesses::cpu.inst 8741470 # number of demand (read+write) accesses 509system.cpu.icache.demand_accesses::total 8741470 # number of demand (read+write) accesses 510system.cpu.icache.overall_accesses::cpu.inst 8741470 # number of overall (read+write) accesses 511system.cpu.icache.overall_accesses::total 8741470 # number of overall (read+write) accesses 512system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123520 # miss rate for ReadReq accesses 513system.cpu.icache.ReadReq_miss_rate::total 0.123520 # miss rate for ReadReq accesses 514system.cpu.icache.demand_miss_rate::cpu.inst 0.123520 # miss rate for demand accesses 515system.cpu.icache.demand_miss_rate::total 0.123520 # miss rate for demand accesses 516system.cpu.icache.overall_miss_rate::cpu.inst 0.123520 # miss rate for overall accesses 517system.cpu.icache.overall_miss_rate::total 0.123520 # miss rate for overall accesses 518system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13450.989067 # average ReadReq miss latency 519system.cpu.icache.ReadReq_avg_miss_latency::total 13450.989067 # average ReadReq miss latency 520system.cpu.icache.demand_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency 521system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency 522system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency 523system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency 524system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked |
| 717system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 525system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 718system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked | 526system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked |
| 719system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 527system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 720system.cpu.icache.avg_blocked_cycles::no_mshrs 9098.909091 # average number of cycles each access was blocked | 528system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked |
| 721system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 722system.cpu.icache.fast_writes 0 # number of fast writes performed 723system.cpu.icache.cache_copies 0 # number of cache copies performed | 529system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 530system.cpu.icache.fast_writes 0 # number of fast writes performed 531system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 724system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60589 # number of ReadReq MSHR hits 725system.cpu.icache.ReadReq_mshr_hits::total 60589 # number of ReadReq MSHR hits 726system.cpu.icache.demand_mshr_hits::cpu.inst 60589 # number of demand (read+write) MSHR hits 727system.cpu.icache.demand_mshr_hits::total 60589 # number of demand (read+write) MSHR hits 728system.cpu.icache.overall_mshr_hits::cpu.inst 60589 # number of overall MSHR hits 729system.cpu.icache.overall_mshr_hits::total 60589 # number of overall MSHR hits 730system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1023087 # number of ReadReq MSHR misses 731system.cpu.icache.ReadReq_mshr_misses::total 1023087 # number of ReadReq MSHR misses 732system.cpu.icache.demand_mshr_misses::cpu.inst 1023087 # number of demand (read+write) MSHR misses 733system.cpu.icache.demand_mshr_misses::total 1023087 # number of demand (read+write) MSHR misses 734system.cpu.icache.overall_mshr_misses::cpu.inst 1023087 # number of overall MSHR misses 735system.cpu.icache.overall_mshr_misses::total 1023087 # number of overall MSHR misses 736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13469506496 # number of ReadReq MSHR miss cycles 737system.cpu.icache.ReadReq_mshr_miss_latency::total 13469506496 # number of ReadReq MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13469506496 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::total 13469506496 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13469506496 # number of overall MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::total 13469506496 # number of overall MSHR miss cycles 742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115789 # mshr miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115789 # mshr miss rate for ReadReq accesses 744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115789 # mshr miss rate for demand accesses 745system.cpu.icache.demand_mshr_miss_rate::total 0.115789 # mshr miss rate for demand accesses 746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115789 # mshr miss rate for overall accesses 747system.cpu.icache.overall_mshr_miss_rate::total 0.115789 # mshr miss rate for overall accesses 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13165.553365 # average ReadReq mshr miss latency 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13165.553365 # average ReadReq mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13165.553365 # average overall mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::total 13165.553365 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13165.553365 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::total 13165.553365 # average overall mshr miss latency | 532system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58677 # number of ReadReq MSHR hits 533system.cpu.icache.ReadReq_mshr_hits::total 58677 # number of ReadReq MSHR hits 534system.cpu.icache.demand_mshr_hits::cpu.inst 58677 # number of demand (read+write) MSHR hits 535system.cpu.icache.demand_mshr_hits::total 58677 # number of demand (read+write) MSHR hits 536system.cpu.icache.overall_mshr_hits::cpu.inst 58677 # number of overall MSHR hits 537system.cpu.icache.overall_mshr_hits::total 58677 # number of overall MSHR hits 538system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021072 # number of ReadReq MSHR misses 539system.cpu.icache.ReadReq_mshr_misses::total 1021072 # number of ReadReq MSHR misses 540system.cpu.icache.demand_mshr_misses::cpu.inst 1021072 # number of demand (read+write) MSHR misses 541system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses 542system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses 543system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses 544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930954998 # number of ReadReq MSHR miss cycles 545system.cpu.icache.ReadReq_mshr_miss_latency::total 11930954998 # number of ReadReq MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930954998 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.demand_mshr_miss_latency::total 11930954998 # number of demand (read+write) MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles 549system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles 550system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses 552system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses 553system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses 554system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses 555system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency 557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # average ReadReq mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency 559system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency 561system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency |
| 754system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 562system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 755system.cpu.dcache.replacements 1401959 # number of replacements 756system.cpu.dcache.tagsinuse 511.994863 # Cycle average of tags in use 757system.cpu.dcache.total_refs 11836105 # Total number of references to valid blocks. 758system.cpu.dcache.sampled_refs 1402471 # Sample count of references to valid blocks. 759system.cpu.dcache.avg_refs 8.439465 # Average number of references to valid blocks. 760system.cpu.dcache.warmup_cycle 23767000 # Cycle when the warmup percentage was hit. 761system.cpu.dcache.occ_blocks::cpu.data 511.994863 # Average occupied blocks per requestor | 563system.cpu.dcache.replacements 1402622 # number of replacements 564system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use 565system.cpu.dcache.total_refs 11889704 # Total number of references to valid blocks. 566system.cpu.dcache.sampled_refs 1403134 # Sample count of references to valid blocks. 567system.cpu.dcache.avg_refs 8.473677 # Average number of references to valid blocks. 568system.cpu.dcache.warmup_cycle 23228000 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.occ_blocks::cpu.data 511.994917 # Average occupied blocks per requestor |
| 762system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 763system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy | 570system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 571system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy |
| 764system.cpu.dcache.ReadReq_hits::cpu.data 7252868 # number of ReadReq hits 765system.cpu.dcache.ReadReq_hits::total 7252868 # number of ReadReq hits 766system.cpu.dcache.WriteReq_hits::cpu.data 4173229 # number of WriteReq hits 767system.cpu.dcache.WriteReq_hits::total 4173229 # number of WriteReq hits 768system.cpu.dcache.LoadLockedReq_hits::cpu.data 190095 # number of LoadLockedReq hits 769system.cpu.dcache.LoadLockedReq_hits::total 190095 # number of LoadLockedReq hits 770system.cpu.dcache.StoreCondReq_hits::cpu.data 219635 # number of StoreCondReq hits 771system.cpu.dcache.StoreCondReq_hits::total 219635 # number of StoreCondReq hits 772system.cpu.dcache.demand_hits::cpu.data 11426097 # number of demand (read+write) hits 773system.cpu.dcache.demand_hits::total 11426097 # number of demand (read+write) hits 774system.cpu.dcache.overall_hits::cpu.data 11426097 # number of overall hits 775system.cpu.dcache.overall_hits::total 11426097 # number of overall hits 776system.cpu.dcache.ReadReq_misses::cpu.data 1829534 # number of ReadReq misses 777system.cpu.dcache.ReadReq_misses::total 1829534 # number of ReadReq misses 778system.cpu.dcache.WriteReq_misses::cpu.data 1968037 # number of WriteReq misses 779system.cpu.dcache.WriteReq_misses::total 1968037 # number of WriteReq misses 780system.cpu.dcache.LoadLockedReq_misses::cpu.data 23402 # number of LoadLockedReq misses 781system.cpu.dcache.LoadLockedReq_misses::total 23402 # number of LoadLockedReq misses 782system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 783system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 784system.cpu.dcache.demand_misses::cpu.data 3797571 # number of demand (read+write) misses 785system.cpu.dcache.demand_misses::total 3797571 # number of demand (read+write) misses 786system.cpu.dcache.overall_misses::cpu.data 3797571 # number of overall misses 787system.cpu.dcache.overall_misses::total 3797571 # number of overall misses 788system.cpu.dcache.ReadReq_miss_latency::cpu.data 48866941000 # number of ReadReq miss cycles 789system.cpu.dcache.ReadReq_miss_latency::total 48866941000 # number of ReadReq miss cycles 790system.cpu.dcache.WriteReq_miss_latency::cpu.data 75341328877 # number of WriteReq miss cycles 791system.cpu.dcache.WriteReq_miss_latency::total 75341328877 # number of WriteReq miss cycles 792system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 430627500 # number of LoadLockedReq miss cycles 793system.cpu.dcache.LoadLockedReq_miss_latency::total 430627500 # number of LoadLockedReq miss cycles 794system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 153500 # number of StoreCondReq miss cycles 795system.cpu.dcache.StoreCondReq_miss_latency::total 153500 # number of StoreCondReq miss cycles 796system.cpu.dcache.demand_miss_latency::cpu.data 124208269877 # number of demand (read+write) miss cycles 797system.cpu.dcache.demand_miss_latency::total 124208269877 # number of demand (read+write) miss cycles 798system.cpu.dcache.overall_miss_latency::cpu.data 124208269877 # number of overall miss cycles 799system.cpu.dcache.overall_miss_latency::total 124208269877 # number of overall miss cycles 800system.cpu.dcache.ReadReq_accesses::cpu.data 9082402 # number of ReadReq accesses(hits+misses) 801system.cpu.dcache.ReadReq_accesses::total 9082402 # number of ReadReq accesses(hits+misses) 802system.cpu.dcache.WriteReq_accesses::cpu.data 6141266 # number of WriteReq accesses(hits+misses) 803system.cpu.dcache.WriteReq_accesses::total 6141266 # number of WriteReq accesses(hits+misses) 804system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213497 # number of LoadLockedReq accesses(hits+misses) 805system.cpu.dcache.LoadLockedReq_accesses::total 213497 # number of LoadLockedReq accesses(hits+misses) 806system.cpu.dcache.StoreCondReq_accesses::cpu.data 219640 # number of StoreCondReq accesses(hits+misses) 807system.cpu.dcache.StoreCondReq_accesses::total 219640 # number of StoreCondReq accesses(hits+misses) 808system.cpu.dcache.demand_accesses::cpu.data 15223668 # number of demand (read+write) accesses 809system.cpu.dcache.demand_accesses::total 15223668 # number of demand (read+write) accesses 810system.cpu.dcache.overall_accesses::cpu.data 15223668 # number of overall (read+write) accesses 811system.cpu.dcache.overall_accesses::total 15223668 # number of overall (read+write) accesses 812system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.201437 # miss rate for ReadReq accesses 813system.cpu.dcache.ReadReq_miss_rate::total 0.201437 # miss rate for ReadReq accesses 814system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320461 # miss rate for WriteReq accesses 815system.cpu.dcache.WriteReq_miss_rate::total 0.320461 # miss rate for WriteReq accesses 816system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109613 # miss rate for LoadLockedReq accesses 817system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109613 # miss rate for LoadLockedReq accesses 818system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000023 # miss rate for StoreCondReq accesses 819system.cpu.dcache.StoreCondReq_miss_rate::total 0.000023 # miss rate for StoreCondReq accesses 820system.cpu.dcache.demand_miss_rate::cpu.data 0.249452 # miss rate for demand accesses 821system.cpu.dcache.demand_miss_rate::total 0.249452 # miss rate for demand accesses 822system.cpu.dcache.overall_miss_rate::cpu.data 0.249452 # miss rate for overall accesses 823system.cpu.dcache.overall_miss_rate::total 0.249452 # miss rate for overall accesses 824system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26710.048023 # average ReadReq miss latency 825system.cpu.dcache.ReadReq_avg_miss_latency::total 26710.048023 # average ReadReq miss latency 826system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38282.475826 # average WriteReq miss latency 827system.cpu.dcache.WriteReq_avg_miss_latency::total 38282.475826 # average WriteReq miss latency 828system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18401.311854 # average LoadLockedReq miss latency 829system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18401.311854 # average LoadLockedReq miss latency 830system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30700 # average StoreCondReq miss latency 831system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30700 # average StoreCondReq miss latency 832system.cpu.dcache.demand_avg_miss_latency::cpu.data 32707.293656 # average overall miss latency 833system.cpu.dcache.demand_avg_miss_latency::total 32707.293656 # average overall miss latency 834system.cpu.dcache.overall_avg_miss_latency::cpu.data 32707.293656 # average overall miss latency 835system.cpu.dcache.overall_avg_miss_latency::total 32707.293656 # average overall miss latency 836system.cpu.dcache.blocked_cycles::no_mshrs 749837529 # number of cycles access was blocked 837system.cpu.dcache.blocked_cycles::no_targets 205000 # number of cycles access was blocked 838system.cpu.dcache.blocked::no_mshrs 72763 # number of cycles access was blocked 839system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked 840system.cpu.dcache.avg_blocked_cycles::no_mshrs 10305.203592 # average number of cycles each access was blocked 841system.cpu.dcache.avg_blocked_cycles::no_targets 25625 # average number of cycles each access was blocked | 572system.cpu.dcache.ReadReq_hits::cpu.data 7274743 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 7274743 # number of ReadReq hits 574system.cpu.dcache.WriteReq_hits::cpu.data 4204816 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 4204816 # number of WriteReq hits 576system.cpu.dcache.LoadLockedReq_hits::cpu.data 190397 # number of LoadLockedReq hits 577system.cpu.dcache.LoadLockedReq_hits::total 190397 # number of LoadLockedReq hits 578system.cpu.dcache.StoreCondReq_hits::cpu.data 219522 # number of StoreCondReq hits 579system.cpu.dcache.StoreCondReq_hits::total 219522 # number of StoreCondReq hits 580system.cpu.dcache.demand_hits::cpu.data 11479559 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 11479559 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 11479559 # number of overall hits 583system.cpu.dcache.overall_hits::total 11479559 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 1797475 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 1797475 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 1942414 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 1942414 # number of WriteReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 23040 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 23040 # number of LoadLockedReq misses 590system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 591system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 592system.cpu.dcache.demand_misses::cpu.data 3739889 # number of demand (read+write) misses 593system.cpu.dcache.demand_misses::total 3739889 # number of demand (read+write) misses 594system.cpu.dcache.overall_misses::cpu.data 3739889 # number of overall misses 595system.cpu.dcache.overall_misses::total 3739889 # number of overall misses 596system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles 597system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles 598system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles 599system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles 600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles 601system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles 602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles 603system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles 604system.cpu.dcache.demand_miss_latency::cpu.data 91795917177 # number of demand (read+write) miss cycles 605system.cpu.dcache.demand_miss_latency::total 91795917177 # number of demand (read+write) miss cycles 606system.cpu.dcache.overall_miss_latency::cpu.data 91795917177 # number of overall miss cycles 607system.cpu.dcache.overall_miss_latency::total 91795917177 # number of overall miss cycles 608system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses) 609system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses) 610system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses) 611system.cpu.dcache.WriteReq_accesses::total 6147230 # number of WriteReq accesses(hits+misses) 612system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213437 # number of LoadLockedReq accesses(hits+misses) 613system.cpu.dcache.LoadLockedReq_accesses::total 213437 # number of LoadLockedReq accesses(hits+misses) 614system.cpu.dcache.StoreCondReq_accesses::cpu.data 219523 # number of StoreCondReq accesses(hits+misses) 615system.cpu.dcache.StoreCondReq_accesses::total 219523 # number of StoreCondReq accesses(hits+misses) 616system.cpu.dcache.demand_accesses::cpu.data 15219448 # number of demand (read+write) accesses 617system.cpu.dcache.demand_accesses::total 15219448 # number of demand (read+write) accesses 618system.cpu.dcache.overall_accesses::cpu.data 15219448 # number of overall (read+write) accesses 619system.cpu.dcache.overall_accesses::total 15219448 # number of overall (read+write) accesses 620system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198130 # miss rate for ReadReq accesses 621system.cpu.dcache.ReadReq_miss_rate::total 0.198130 # miss rate for ReadReq accesses 622system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315982 # miss rate for WriteReq accesses 623system.cpu.dcache.WriteReq_miss_rate::total 0.315982 # miss rate for WriteReq accesses 624system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107948 # miss rate for LoadLockedReq accesses 625system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107948 # miss rate for LoadLockedReq accesses 626system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses 627system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses 628system.cpu.dcache.demand_miss_rate::cpu.data 0.245731 # miss rate for demand accesses 629system.cpu.dcache.demand_miss_rate::total 0.245731 # miss rate for demand accesses 630system.cpu.dcache.overall_miss_rate::cpu.data 0.245731 # miss rate for overall accesses 631system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses 632system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19682.056496 # average ReadReq miss latency 633system.cpu.dcache.ReadReq_avg_miss_latency::total 19682.056496 # average ReadReq miss latency 634system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29045.256406 # average WriteReq miss latency 635system.cpu.dcache.WriteReq_avg_miss_latency::total 29045.256406 # average WriteReq miss latency 636system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13215.277778 # average LoadLockedReq miss latency 637system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13215.277778 # average LoadLockedReq miss latency 638system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 639system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 640system.cpu.dcache.demand_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency 641system.cpu.dcache.demand_avg_miss_latency::total 24545.091359 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::cpu.data 24545.091359 # average overall miss latency 643system.cpu.dcache.overall_avg_miss_latency::total 24545.091359 # average overall miss latency 644system.cpu.dcache.blocked_cycles::no_mshrs 807907785 # number of cycles access was blocked 645system.cpu.dcache.blocked_cycles::no_targets 221000 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_mshrs 110012 # number of cycles access was blocked 647system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 648system.cpu.dcache.avg_blocked_cycles::no_mshrs 7343.815084 # average number of cycles each access was blocked 649system.cpu.dcache.avg_blocked_cycles::no_targets 24555.555556 # average number of cycles each access was blocked |
| 842system.cpu.dcache.fast_writes 0 # number of fast writes performed 843system.cpu.dcache.cache_copies 0 # number of cache copies performed | 650system.cpu.dcache.fast_writes 0 # number of fast writes performed 651system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 844system.cpu.dcache.writebacks::writebacks 841020 # number of writebacks 845system.cpu.dcache.writebacks::total 841020 # number of writebacks 846system.cpu.dcache.ReadReq_mshr_hits::cpu.data 745266 # number of ReadReq MSHR hits 847system.cpu.dcache.ReadReq_mshr_hits::total 745266 # number of ReadReq MSHR hits 848system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667773 # number of WriteReq MSHR hits 849system.cpu.dcache.WriteReq_mshr_hits::total 1667773 # number of WriteReq MSHR hits 850system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5284 # number of LoadLockedReq MSHR hits 851system.cpu.dcache.LoadLockedReq_mshr_hits::total 5284 # number of LoadLockedReq MSHR hits 852system.cpu.dcache.demand_mshr_hits::cpu.data 2413039 # number of demand (read+write) MSHR hits 853system.cpu.dcache.demand_mshr_hits::total 2413039 # number of demand (read+write) MSHR hits 854system.cpu.dcache.overall_mshr_hits::cpu.data 2413039 # number of overall MSHR hits 855system.cpu.dcache.overall_mshr_hits::total 2413039 # number of overall MSHR hits 856system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084268 # number of ReadReq MSHR misses 857system.cpu.dcache.ReadReq_mshr_misses::total 1084268 # number of ReadReq MSHR misses 858system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300264 # number of WriteReq MSHR misses 859system.cpu.dcache.WriteReq_mshr_misses::total 300264 # number of WriteReq MSHR misses 860system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18118 # number of LoadLockedReq MSHR misses 861system.cpu.dcache.LoadLockedReq_mshr_misses::total 18118 # number of LoadLockedReq MSHR misses 862system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 863system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 864system.cpu.dcache.demand_mshr_misses::cpu.data 1384532 # number of demand (read+write) MSHR misses 865system.cpu.dcache.demand_mshr_misses::total 1384532 # number of demand (read+write) MSHR misses 866system.cpu.dcache.overall_mshr_misses::cpu.data 1384532 # number of overall MSHR misses 867system.cpu.dcache.overall_mshr_misses::total 1384532 # number of overall MSHR misses 868system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28231218500 # number of ReadReq MSHR miss cycles 869system.cpu.dcache.ReadReq_mshr_miss_latency::total 28231218500 # number of ReadReq MSHR miss cycles 870system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9703849435 # number of WriteReq MSHR miss cycles 871system.cpu.dcache.WriteReq_mshr_miss_latency::total 9703849435 # number of WriteReq MSHR miss cycles 872system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 271481500 # number of LoadLockedReq MSHR miss cycles 873system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 271481500 # number of LoadLockedReq MSHR miss cycles 874system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 138000 # number of StoreCondReq MSHR miss cycles 875system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 138000 # number of StoreCondReq MSHR miss cycles 876system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37935067935 # number of demand (read+write) MSHR miss cycles 877system.cpu.dcache.demand_mshr_miss_latency::total 37935067935 # number of demand (read+write) MSHR miss cycles 878system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37935067935 # number of overall MSHR miss cycles 879system.cpu.dcache.overall_mshr_miss_latency::total 37935067935 # number of overall MSHR miss cycles 880system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1425162500 # number of ReadReq MSHR uncacheable cycles 881system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1425162500 # number of ReadReq MSHR uncacheable cycles 882system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2002731998 # number of WriteReq MSHR uncacheable cycles 883system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002731998 # number of WriteReq MSHR uncacheable cycles 884system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3427894498 # number of overall MSHR uncacheable cycles 885system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427894498 # number of overall MSHR uncacheable cycles 886system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119381 # mshr miss rate for ReadReq accesses 887system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119381 # mshr miss rate for ReadReq accesses 888system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048893 # mshr miss rate for WriteReq accesses 889system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048893 # mshr miss rate for WriteReq accesses 890system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084863 # mshr miss rate for LoadLockedReq accesses 891system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084863 # mshr miss rate for LoadLockedReq accesses 892system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses 893system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses 894system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090946 # mshr miss rate for demand accesses 895system.cpu.dcache.demand_mshr_miss_rate::total 0.090946 # mshr miss rate for demand accesses 896system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090946 # mshr miss rate for overall accesses 897system.cpu.dcache.overall_mshr_miss_rate::total 0.090946 # mshr miss rate for overall accesses 898system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26037.122280 # average ReadReq mshr miss latency 899system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26037.122280 # average ReadReq mshr miss latency 900system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32317.725185 # average WriteReq mshr miss latency 901system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32317.725185 # average WriteReq mshr miss latency 902system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14984.076609 # average LoadLockedReq mshr miss latency 903system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.076609 # average LoadLockedReq mshr miss latency 904system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27600 # average StoreCondReq mshr miss latency 905system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27600 # average StoreCondReq mshr miss latency 906system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27399.199105 # average overall mshr miss latency 907system.cpu.dcache.demand_avg_mshr_miss_latency::total 27399.199105 # average overall mshr miss latency 908system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27399.199105 # average overall mshr miss latency 909system.cpu.dcache.overall_avg_mshr_miss_latency::total 27399.199105 # average overall mshr miss latency | 652system.cpu.dcache.writebacks::writebacks 841878 # number of writebacks 653system.cpu.dcache.writebacks::total 841878 # number of writebacks 654system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712313 # number of ReadReq MSHR hits 655system.cpu.dcache.ReadReq_mshr_hits::total 712313 # number of ReadReq MSHR hits 656system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642186 # number of WriteReq MSHR hits 657system.cpu.dcache.WriteReq_mshr_hits::total 1642186 # number of WriteReq MSHR hits 658system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5152 # number of LoadLockedReq MSHR hits 659system.cpu.dcache.LoadLockedReq_mshr_hits::total 5152 # number of LoadLockedReq MSHR hits 660system.cpu.dcache.demand_mshr_hits::cpu.data 2354499 # number of demand (read+write) MSHR hits 661system.cpu.dcache.demand_mshr_hits::total 2354499 # number of demand (read+write) MSHR hits 662system.cpu.dcache.overall_mshr_hits::cpu.data 2354499 # number of overall MSHR hits 663system.cpu.dcache.overall_mshr_hits::total 2354499 # number of overall MSHR hits 664system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085162 # number of ReadReq MSHR misses 665system.cpu.dcache.ReadReq_mshr_misses::total 1085162 # number of ReadReq MSHR misses 666system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300228 # number of WriteReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::total 300228 # number of WriteReq MSHR misses 668system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17888 # number of LoadLockedReq MSHR misses 669system.cpu.dcache.LoadLockedReq_mshr_misses::total 17888 # number of LoadLockedReq MSHR misses 670system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 671system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 672system.cpu.dcache.demand_mshr_misses::cpu.data 1385390 # number of demand (read+write) MSHR misses 673system.cpu.dcache.demand_mshr_misses::total 1385390 # number of demand (read+write) MSHR misses 674system.cpu.dcache.overall_mshr_misses::cpu.data 1385390 # number of overall MSHR misses 675system.cpu.dcache.overall_mshr_misses::total 1385390 # number of overall MSHR misses 676system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23663666500 # number of ReadReq MSHR miss cycles 677system.cpu.dcache.ReadReq_mshr_miss_latency::total 23663666500 # number of ReadReq MSHR miss cycles 678system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402021809 # number of WriteReq MSHR miss cycles 679system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402021809 # number of WriteReq MSHR miss cycles 680system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201708000 # number of LoadLockedReq MSHR miss cycles 681system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201708000 # number of LoadLockedReq MSHR miss cycles 682system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles 683system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles 684system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32065688309 # number of demand (read+write) MSHR miss cycles 685system.cpu.dcache.demand_mshr_miss_latency::total 32065688309 # number of demand (read+write) MSHR miss cycles 686system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32065688309 # number of overall MSHR miss cycles 687system.cpu.dcache.overall_mshr_miss_latency::total 32065688309 # number of overall MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424101000 # number of ReadReq MSHR uncacheable cycles 689system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424101000 # number of ReadReq MSHR uncacheable cycles 690system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997524498 # number of WriteReq MSHR uncacheable cycles 691system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997524498 # number of WriteReq MSHR uncacheable cycles 692system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles 693system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles 694system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119614 # mshr miss rate for ReadReq accesses 695system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119614 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048840 # mshr miss rate for WriteReq accesses 697system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048840 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083809 # mshr miss rate for LoadLockedReq accesses 699system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083809 # mshr miss rate for LoadLockedReq accesses 700system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses 701system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses 702system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for demand accesses 703system.cpu.dcache.demand_mshr_miss_rate::total 0.091028 # mshr miss rate for demand accesses 704system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091028 # mshr miss rate for overall accesses 705system.cpu.dcache.overall_mshr_miss_rate::total 0.091028 # mshr miss rate for overall accesses 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21806.574963 # average ReadReq mshr miss latency 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21806.574963 # average ReadReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27985.470406 # average WriteReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27985.470406 # average WriteReq mshr miss latency 710system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11276.162791 # average LoadLockedReq mshr miss latency 711system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11276.162791 # average LoadLockedReq mshr miss latency 712system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 713system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 714system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency 715system.cpu.dcache.demand_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency 716system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23145.603988 # average overall mshr miss latency 717system.cpu.dcache.overall_avg_mshr_miss_latency::total 23145.603988 # average overall mshr miss latency |
| 910system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 911system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 912system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 913system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 914system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 915system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 916system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 718system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 719system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 720system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 721system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 722system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 723system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 724system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 725system.cpu.l2cache.replacements 338417 # number of replacements 726system.cpu.l2cache.tagsinuse 65352.111585 # Cycle average of tags in use 727system.cpu.l2cache.total_refs 2559541 # Total number of references to valid blocks. 728system.cpu.l2cache.sampled_refs 403585 # Sample count of references to valid blocks. 729system.cpu.l2cache.avg_refs 6.342012 # Average number of references to valid blocks. 730system.cpu.l2cache.warmup_cycle 4707423000 # Cycle when the warmup percentage was hit. 731system.cpu.l2cache.occ_blocks::writebacks 53923.419199 # Average occupied blocks per requestor 732system.cpu.l2cache.occ_blocks::cpu.inst 5354.651362 # Average occupied blocks per requestor 733system.cpu.l2cache.occ_blocks::cpu.data 6074.041024 # Average occupied blocks per requestor 734system.cpu.l2cache.occ_percent::writebacks 0.822806 # Average percentage of cache occupancy 735system.cpu.l2cache.occ_percent::cpu.inst 0.081705 # Average percentage of cache occupancy 736system.cpu.l2cache.occ_percent::cpu.data 0.092683 # Average percentage of cache occupancy 737system.cpu.l2cache.occ_percent::total 0.997194 # Average percentage of cache occupancy 738system.cpu.l2cache.ReadReq_hits::cpu.inst 1005811 # number of ReadReq hits 739system.cpu.l2cache.ReadReq_hits::cpu.data 828504 # number of ReadReq hits 740system.cpu.l2cache.ReadReq_hits::total 1834315 # number of ReadReq hits 741system.cpu.l2cache.Writeback_hits::writebacks 841878 # number of Writeback hits 742system.cpu.l2cache.Writeback_hits::total 841878 # number of Writeback hits 743system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 744system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 745system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 746system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 747system.cpu.l2cache.ReadExReq_hits::cpu.data 185452 # number of ReadExReq hits 748system.cpu.l2cache.ReadExReq_hits::total 185452 # number of ReadExReq hits 749system.cpu.l2cache.demand_hits::cpu.inst 1005811 # number of demand (read+write) hits 750system.cpu.l2cache.demand_hits::cpu.data 1013956 # number of demand (read+write) hits 751system.cpu.l2cache.demand_hits::total 2019767 # number of demand (read+write) hits 752system.cpu.l2cache.overall_hits::cpu.inst 1005811 # number of overall hits 753system.cpu.l2cache.overall_hits::cpu.data 1013956 # number of overall hits 754system.cpu.l2cache.overall_hits::total 2019767 # number of overall hits 755system.cpu.l2cache.ReadReq_misses::cpu.inst 15151 # number of ReadReq misses 756system.cpu.l2cache.ReadReq_misses::cpu.data 273885 # number of ReadReq misses 757system.cpu.l2cache.ReadReq_misses::total 289036 # number of ReadReq misses 758system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses 759system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses 760system.cpu.l2cache.ReadExReq_misses::cpu.data 115380 # number of ReadExReq misses 761system.cpu.l2cache.ReadExReq_misses::total 115380 # number of ReadExReq misses 762system.cpu.l2cache.demand_misses::cpu.inst 15151 # number of demand (read+write) misses 763system.cpu.l2cache.demand_misses::cpu.data 389265 # number of demand (read+write) misses 764system.cpu.l2cache.demand_misses::total 404416 # number of demand (read+write) misses 765system.cpu.l2cache.overall_misses::cpu.inst 15151 # number of overall misses 766system.cpu.l2cache.overall_misses::cpu.data 389265 # number of overall misses 767system.cpu.l2cache.overall_misses::total 404416 # number of overall misses 768system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 808284498 # number of ReadReq miss cycles 769system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14265189000 # number of ReadReq miss cycles 770system.cpu.l2cache.ReadReq_miss_latency::total 15073473498 # number of ReadReq miss cycles 771system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 384500 # number of UpgradeReq miss cycles 772system.cpu.l2cache.UpgradeReq_miss_latency::total 384500 # number of UpgradeReq miss cycles 773system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6187378482 # number of ReadExReq miss cycles 774system.cpu.l2cache.ReadExReq_miss_latency::total 6187378482 # number of ReadExReq miss cycles 775system.cpu.l2cache.demand_miss_latency::cpu.inst 808284498 # number of demand (read+write) miss cycles 776system.cpu.l2cache.demand_miss_latency::cpu.data 20452567482 # number of demand (read+write) miss cycles 777system.cpu.l2cache.demand_miss_latency::total 21260851980 # number of demand (read+write) miss cycles 778system.cpu.l2cache.overall_miss_latency::cpu.inst 808284498 # number of overall miss cycles 779system.cpu.l2cache.overall_miss_latency::cpu.data 20452567482 # number of overall miss cycles 780system.cpu.l2cache.overall_miss_latency::total 21260851980 # number of overall miss cycles 781system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020962 # number of ReadReq accesses(hits+misses) 782system.cpu.l2cache.ReadReq_accesses::cpu.data 1102389 # number of ReadReq accesses(hits+misses) 783system.cpu.l2cache.ReadReq_accesses::total 2123351 # number of ReadReq accesses(hits+misses) 784system.cpu.l2cache.Writeback_accesses::writebacks 841878 # number of Writeback accesses(hits+misses) 785system.cpu.l2cache.Writeback_accesses::total 841878 # number of Writeback accesses(hits+misses) 786system.cpu.l2cache.UpgradeReq_accesses::cpu.data 59 # number of UpgradeReq accesses(hits+misses) 787system.cpu.l2cache.UpgradeReq_accesses::total 59 # number of UpgradeReq accesses(hits+misses) 788system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 789system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 790system.cpu.l2cache.ReadExReq_accesses::cpu.data 300832 # number of ReadExReq accesses(hits+misses) 791system.cpu.l2cache.ReadExReq_accesses::total 300832 # number of ReadExReq accesses(hits+misses) 792system.cpu.l2cache.demand_accesses::cpu.inst 1020962 # number of demand (read+write) accesses 793system.cpu.l2cache.demand_accesses::cpu.data 1403221 # number of demand (read+write) accesses 794system.cpu.l2cache.demand_accesses::total 2424183 # number of demand (read+write) accesses 795system.cpu.l2cache.overall_accesses::cpu.inst 1020962 # number of overall (read+write) accesses 796system.cpu.l2cache.overall_accesses::cpu.data 1403221 # number of overall (read+write) accesses 797system.cpu.l2cache.overall_accesses::total 2424183 # number of overall (read+write) accesses 798system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014840 # miss rate for ReadReq accesses 799system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248447 # miss rate for ReadReq accesses 800system.cpu.l2cache.ReadReq_miss_rate::total 0.136123 # miss rate for ReadReq accesses 801system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.559322 # miss rate for UpgradeReq accesses 802system.cpu.l2cache.UpgradeReq_miss_rate::total 0.559322 # miss rate for UpgradeReq accesses 803system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383536 # miss rate for ReadExReq accesses 804system.cpu.l2cache.ReadExReq_miss_rate::total 0.383536 # miss rate for ReadExReq accesses 805system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014840 # miss rate for demand accesses 806system.cpu.l2cache.demand_miss_rate::cpu.data 0.277408 # miss rate for demand accesses 807system.cpu.l2cache.demand_miss_rate::total 0.166826 # miss rate for demand accesses 808system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014840 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::cpu.data 0.277408 # miss rate for overall accesses 810system.cpu.l2cache.overall_miss_rate::total 0.166826 # miss rate for overall accesses 811system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53348.590720 # average ReadReq miss latency 812system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52084.593899 # average ReadReq miss latency 813system.cpu.l2cache.ReadReq_avg_miss_latency::total 52150.851444 # average ReadReq miss latency 814system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.515152 # average UpgradeReq miss latency 815system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.515152 # average UpgradeReq miss latency 816system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53626.091888 # average ReadExReq miss latency 817system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53626.091888 # average ReadExReq miss latency 818system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency 819system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency 820system.cpu.l2cache.demand_avg_miss_latency::total 52571.737963 # average overall miss latency 821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53348.590720 # average overall miss latency 822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52541.501245 # average overall miss latency 823system.cpu.l2cache.overall_avg_miss_latency::total 52571.737963 # average overall miss latency 824system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 825system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 826system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 827system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 828system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 829system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 830system.cpu.l2cache.fast_writes 0 # number of fast writes performed 831system.cpu.l2cache.cache_copies 0 # number of cache copies performed 832system.cpu.l2cache.writebacks::writebacks 76030 # number of writebacks 833system.cpu.l2cache.writebacks::total 76030 # number of writebacks 834system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 835system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 836system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 837system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 838system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 839system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 840system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15150 # number of ReadReq MSHR misses 841system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273885 # number of ReadReq MSHR misses 842system.cpu.l2cache.ReadReq_mshr_misses::total 289035 # number of ReadReq MSHR misses 843system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses 844system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses 845system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115380 # number of ReadExReq MSHR misses 846system.cpu.l2cache.ReadExReq_mshr_misses::total 115380 # number of ReadExReq MSHR misses 847system.cpu.l2cache.demand_mshr_misses::cpu.inst 15150 # number of demand (read+write) MSHR misses 848system.cpu.l2cache.demand_mshr_misses::cpu.data 389265 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.demand_mshr_misses::total 404415 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.overall_mshr_misses::cpu.inst 15150 # number of overall MSHR misses 851system.cpu.l2cache.overall_mshr_misses::cpu.data 389265 # number of overall MSHR misses 852system.cpu.l2cache.overall_mshr_misses::total 404415 # number of overall MSHR misses 853system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 622919998 # number of ReadReq MSHR miss cycles 854system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986726000 # number of ReadReq MSHR miss cycles 855system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11609645998 # number of ReadReq MSHR miss cycles 856system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1412500 # number of UpgradeReq MSHR miss cycles 857system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1412500 # number of UpgradeReq MSHR miss cycles 858system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4791053982 # number of ReadExReq MSHR miss cycles 859system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4791053982 # number of ReadExReq MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 622919998 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15777779982 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.demand_mshr_miss_latency::total 16400699980 # number of demand (read+write) MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 622919998 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15777779982 # number of overall MSHR miss cycles 865system.cpu.l2cache.overall_mshr_miss_latency::total 16400699980 # number of overall MSHR miss cycles 866system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331599500 # number of ReadReq MSHR uncacheable cycles 867system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331599500 # number of ReadReq MSHR uncacheable cycles 868system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1880939999 # number of WriteReq MSHR uncacheable cycles 869system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1880939999 # number of WriteReq MSHR uncacheable cycles 870system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3212539499 # number of overall MSHR uncacheable cycles 871system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3212539499 # number of overall MSHR uncacheable cycles 872system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for ReadReq accesses 873system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248447 # mshr miss rate for ReadReq accesses 874system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136122 # mshr miss rate for ReadReq accesses 875system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.559322 # mshr miss rate for UpgradeReq accesses 876system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.559322 # mshr miss rate for UpgradeReq accesses 877system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383536 # mshr miss rate for ReadExReq accesses 878system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383536 # mshr miss rate for ReadExReq accesses 879system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for demand accesses 880system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for demand accesses 881system.cpu.l2cache.demand_mshr_miss_rate::total 0.166825 # mshr miss rate for demand accesses 882system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014839 # mshr miss rate for overall accesses 883system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277408 # mshr miss rate for overall accesses 884system.cpu.l2cache.overall_mshr_miss_rate::total 0.166825 # mshr miss rate for overall accesses 885system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41116.831551 # average ReadReq mshr miss latency 886system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40114.376472 # average ReadReq mshr miss latency 887system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40166.920954 # average ReadReq mshr miss latency 888system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 42803.030303 # average UpgradeReq mshr miss latency 889system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 42803.030303 # average UpgradeReq mshr miss latency 890system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41524.128809 # average ReadExReq mshr miss latency 891system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41524.128809 # average ReadExReq mshr miss latency 892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency 893system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency 894system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency 895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41116.831551 # average overall mshr miss latency 896system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40532.233779 # average overall mshr miss latency 897system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40554.133699 # average overall mshr miss latency 898system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 899system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 900system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 901system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 902system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 903system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 904system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 917system.cpu.kern.inst.arm 0 # number of arm instructions executed | 905system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 918system.cpu.kern.inst.quiesce 6432 # number of quiesce instructions executed 919system.cpu.kern.inst.hwrei 211195 # number of hwrei instructions executed 920system.cpu.kern.ipl_count::0 74695 40.95% 40.95% # number of times we switched to this ipl 921system.cpu.kern.ipl_count::21 137 0.08% 41.02% # number of times we switched to this ipl 922system.cpu.kern.ipl_count::22 1890 1.04% 42.06% # number of times we switched to this ipl 923system.cpu.kern.ipl_count::31 105693 57.94% 100.00% # number of times we switched to this ipl 924system.cpu.kern.ipl_count::total 182415 # number of times we switched to this ipl 925system.cpu.kern.ipl_good::0 73328 49.32% 49.32% # number of times we switched to this ipl from a different ipl 926system.cpu.kern.ipl_good::21 137 0.09% 49.41% # number of times we switched to this ipl from a different ipl 927system.cpu.kern.ipl_good::22 1890 1.27% 50.68% # number of times we switched to this ipl from a different ipl 928system.cpu.kern.ipl_good::31 73331 49.32% 100.00% # number of times we switched to this ipl from a different ipl 929system.cpu.kern.ipl_good::total 148686 # number of times we switched to this ipl from a different ipl 930system.cpu.kern.ipl_ticks::0 1826702082500 97.82% 97.82% # number of cycles we spent at this ipl 931system.cpu.kern.ipl_ticks::21 72077500 0.00% 97.83% # number of cycles we spent at this ipl 932system.cpu.kern.ipl_ticks::22 572984500 0.03% 97.86% # number of cycles we spent at this ipl 933system.cpu.kern.ipl_ticks::31 40025844000 2.14% 100.00% # number of cycles we spent at this ipl 934system.cpu.kern.ipl_ticks::total 1867372988500 # number of cycles we spent at this ipl 935system.cpu.kern.ipl_used::0 0.981699 # fraction of swpipl calls that actually changed the ipl | 906system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed 907system.cpu.kern.inst.hwrei 210941 # number of hwrei instructions executed 908system.cpu.kern.ipl_count::0 74638 40.97% 40.97% # number of times we switched to this ipl 909system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 910system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl 911system.cpu.kern.ipl_count::31 105526 57.93% 100.00% # number of times we switched to this ipl 912system.cpu.kern.ipl_count::total 182173 # number of times we switched to this ipl 913system.cpu.kern.ipl_good::0 73271 49.32% 49.32% # number of times we switched to this ipl from a different ipl 914system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 915system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl 916system.cpu.kern.ipl_good::31 73271 49.32% 100.00% # number of times we switched to this ipl from a different ipl 917system.cpu.kern.ipl_good::total 148551 # number of times we switched to this ipl from a different ipl 918system.cpu.kern.ipl_ticks::0 1816492246000 97.91% 97.91% # number of cycles we spent at this ipl 919system.cpu.kern.ipl_ticks::21 64137000 0.00% 97.92% # number of cycles we spent at this ipl 920system.cpu.kern.ipl_ticks::22 560297500 0.03% 97.95% # number of cycles we spent at this ipl 921system.cpu.kern.ipl_ticks::31 38118929000 2.05% 100.00% # number of cycles we spent at this ipl 922system.cpu.kern.ipl_ticks::total 1855235609500 # number of cycles we spent at this ipl 923system.cpu.kern.ipl_used::0 0.981685 # fraction of swpipl calls that actually changed the ipl |
| 936system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 937system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 924system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 925system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 938system.cpu.kern.ipl_used::31 0.693811 # fraction of swpipl calls that actually changed the ipl 939system.cpu.kern.ipl_used::total 0.815097 # fraction of swpipl calls that actually changed the ipl | 926system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl 927system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl |
| 940system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 941system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 942system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 943system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 944system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 945system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 946system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 947system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 967system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 968system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 969system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 970system.cpu.kern.syscall::total 326 # number of syscalls executed 971system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 972system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 973system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 974system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 928system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 929system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 930system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 931system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 932system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 933system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 934system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 935system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 955system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 956system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 957system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 958system.cpu.kern.syscall::total 326 # number of syscalls executed 959system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 960system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 961system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 962system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 975system.cpu.kern.callpal::swpctx 4176 2.17% 2.18% # number of callpals executed 976system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed | 963system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 964system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed |
| 977system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed | 965system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed |
| 978system.cpu.kern.callpal::swpipl 175272 91.22% 93.43% # number of callpals executed 979system.cpu.kern.callpal::rdps 6795 3.54% 96.96% # number of callpals executed 980system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed | 966system.cpu.kern.callpal::swpipl 175060 91.22% 93.43% # number of callpals executed 967system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 968system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed |
| 981system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed | 969system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed |
| 982system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 983system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 984system.cpu.kern.callpal::rti 5118 2.66% 99.64% # number of callpals executed | 970system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 971system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 972system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed |
| 985system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 986system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 973system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 974system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 987system.cpu.kern.callpal::total 192141 # number of callpals executed 988system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches 989system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 990system.cpu.kern.mode_switch::idle 2108 # number of protection mode switches 991system.cpu.kern.mode_good::kernel 1908 992system.cpu.kern.mode_good::user 1738 | 975system.cpu.kern.callpal::total 191902 # number of callpals executed 976system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches 977system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 978system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 979system.cpu.kern.mode_good::kernel 1909 980system.cpu.kern.mode_good::user 1739 |
| 993system.cpu.kern.mode_good::idle 170 | 981system.cpu.kern.mode_good::idle 170 |
| 994system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches | 982system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches |
| 995system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 983system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 996system.cpu.kern.mode_switch_good::idle 0.080645 # fraction of useful protection mode switches 997system.cpu.kern.mode_switch_good::total 0.393483 # fraction of useful protection mode switches 998system.cpu.kern.mode_ticks::kernel 29935560000 1.60% 1.60% # number of ticks spent at the given mode 999system.cpu.kern.mode_ticks::user 2782423500 0.15% 1.75% # number of ticks spent at the given mode 1000system.cpu.kern.mode_ticks::idle 1834654997000 98.25% 100.00% # number of ticks spent at the given mode | 984system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 985system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches 986system.cpu.kern.mode_ticks::kernel 28997338000 1.56% 1.56% # number of ticks spent at the given mode 987system.cpu.kern.mode_ticks::user 2608198500 0.14% 1.70% # number of ticks spent at the given mode 988system.cpu.kern.mode_ticks::idle 1823630065000 98.30% 100.00% # number of ticks spent at the given mode |
| 1001system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1002 1003---------- End Simulation Statistics ---------- | 989system.cpu.kern.swap_context 4177 # number of times the context was actually changed 990 991---------- End Simulation Statistics ---------- |