| stats.txt (9229:65f927bda74d) | stats.txt (9283:490958b032d6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.867374 # Number of seconds simulated 4sim_ticks 1867373908500 # Number of ticks simulated 5final_tick 1867373908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 123272 # Simulator instruction rate (inst/s) 8host_op_rate 123272 # Simulator op (including micro ops) rate (op/s) --- 24 unchanged lines hidden (view full) --- 33system.physmem.bw_inst_read::total 519335 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4026360 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4026360 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4026360 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 519335 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13323249 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1420330 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19289275 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.867374 # Number of seconds simulated 4sim_ticks 1867373908500 # Number of ticks simulated 5final_tick 1867373908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 123272 # Simulator instruction rate (inst/s) 8host_op_rate 123272 # Simulator op (including micro ops) rate (op/s) --- 24 unchanged lines hidden (view full) --- 33system.physmem.bw_inst_read::total 519335 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4026360 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4026360 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4026360 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 519335 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13323249 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1420330 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19289275 # Total bandwidth to/from this memory (bytes/s) |
| 41system.l2c.replacements 338398 # number of replacements 42system.l2c.tagsinuse 65348.140689 # Cycle average of tags in use 43system.l2c.total_refs 2559915 # Total number of references to valid blocks. 44system.l2c.sampled_refs 403567 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.343222 # Average number of references to valid blocks. 46system.l2c.warmup_cycle 4870006000 # Cycle when the warmup percentage was hit. 47system.l2c.occ_blocks::writebacks 53844.889123 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 5363.726417 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 6139.525149 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.821608 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.081844 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.093682 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.997133 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 1007783 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 827771 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1835554 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 841020 # number of Writeback hits 58system.l2c.Writeback_hits::total 841020 # number of Writeback hits 59system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits 61system.l2c.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 62system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 63system.l2c.ReadExReq_hits::cpu.data 185546 # number of ReadExReq hits 64system.l2c.ReadExReq_hits::total 185546 # number of ReadExReq hits 65system.l2c.demand_hits::cpu.inst 1007783 # number of demand (read+write) hits 66system.l2c.demand_hits::cpu.data 1013317 # number of demand (read+write) hits 67system.l2c.demand_hits::total 2021100 # number of demand (read+write) hits 68system.l2c.overall_hits::cpu.inst 1007783 # number of overall hits 69system.l2c.overall_hits::cpu.data 1013317 # number of overall hits 70system.l2c.overall_hits::total 2021100 # number of overall hits 71system.l2c.ReadReq_misses::cpu.inst 15155 # number of ReadReq misses 72system.l2c.ReadReq_misses::cpu.data 273854 # number of ReadReq misses 73system.l2c.ReadReq_misses::total 289009 # number of ReadReq misses 74system.l2c.UpgradeReq_misses::cpu.data 54 # number of UpgradeReq misses 75system.l2c.UpgradeReq_misses::total 54 # number of UpgradeReq misses 76system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 77system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 78system.l2c.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses 79system.l2c.ReadExReq_misses::total 115395 # number of ReadExReq misses 80system.l2c.demand_misses::cpu.inst 15155 # number of demand (read+write) misses 81system.l2c.demand_misses::cpu.data 389249 # number of demand (read+write) misses 82system.l2c.demand_misses::total 404404 # number of demand (read+write) misses 83system.l2c.overall_misses::cpu.inst 15155 # number of overall misses 84system.l2c.overall_misses::cpu.data 389249 # number of overall misses 85system.l2c.overall_misses::total 404404 # number of overall misses 86system.l2c.ReadReq_miss_latency::cpu.inst 807128998 # number of ReadReq miss cycles 87system.l2c.ReadReq_miss_latency::cpu.data 14259763500 # number of ReadReq miss cycles 88system.l2c.ReadReq_miss_latency::total 15066892498 # number of ReadReq miss cycles 89system.l2c.UpgradeReq_miss_latency::cpu.data 376500 # number of UpgradeReq miss cycles 90system.l2c.UpgradeReq_miss_latency::total 376500 # number of UpgradeReq miss cycles 91system.l2c.ReadExReq_miss_latency::cpu.data 6225363497 # number of ReadExReq miss cycles 92system.l2c.ReadExReq_miss_latency::total 6225363497 # number of ReadExReq miss cycles 93system.l2c.demand_miss_latency::cpu.inst 807128998 # number of demand (read+write) miss cycles 94system.l2c.demand_miss_latency::cpu.data 20485126997 # number of demand (read+write) miss cycles 95system.l2c.demand_miss_latency::total 21292255995 # number of demand (read+write) miss cycles 96system.l2c.overall_miss_latency::cpu.inst 807128998 # number of overall miss cycles 97system.l2c.overall_miss_latency::cpu.data 20485126997 # number of overall miss cycles 98system.l2c.overall_miss_latency::total 21292255995 # number of overall miss cycles 99system.l2c.ReadReq_accesses::cpu.inst 1022938 # number of ReadReq accesses(hits+misses) 100system.l2c.ReadReq_accesses::cpu.data 1101625 # number of ReadReq accesses(hits+misses) 101system.l2c.ReadReq_accesses::total 2124563 # number of ReadReq accesses(hits+misses) 102system.l2c.Writeback_accesses::writebacks 841020 # number of Writeback accesses(hits+misses) 103system.l2c.Writeback_accesses::total 841020 # number of Writeback accesses(hits+misses) 104system.l2c.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses) 105system.l2c.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses) 106system.l2c.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 107system.l2c.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 108system.l2c.ReadExReq_accesses::cpu.data 300941 # number of ReadExReq accesses(hits+misses) 109system.l2c.ReadExReq_accesses::total 300941 # number of ReadExReq accesses(hits+misses) 110system.l2c.demand_accesses::cpu.inst 1022938 # number of demand (read+write) accesses 111system.l2c.demand_accesses::cpu.data 1402566 # number of demand (read+write) accesses 112system.l2c.demand_accesses::total 2425504 # number of demand (read+write) accesses 113system.l2c.overall_accesses::cpu.inst 1022938 # number of overall (read+write) accesses 114system.l2c.overall_accesses::cpu.data 1402566 # number of overall (read+write) accesses 115system.l2c.overall_accesses::total 2425504 # number of overall (read+write) accesses 116system.l2c.ReadReq_miss_rate::cpu.inst 0.014815 # miss rate for ReadReq accesses 117system.l2c.ReadReq_miss_rate::cpu.data 0.248591 # miss rate for ReadReq accesses 118system.l2c.ReadReq_miss_rate::total 0.136032 # miss rate for ReadReq accesses 119system.l2c.UpgradeReq_miss_rate::cpu.data 0.635294 # miss rate for UpgradeReq accesses 120system.l2c.UpgradeReq_miss_rate::total 0.635294 # miss rate for UpgradeReq accesses 121system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 122system.l2c.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses 123system.l2c.ReadExReq_miss_rate::cpu.data 0.383447 # miss rate for ReadExReq accesses 124system.l2c.ReadExReq_miss_rate::total 0.383447 # miss rate for ReadExReq accesses 125system.l2c.demand_miss_rate::cpu.inst 0.014815 # miss rate for demand accesses 126system.l2c.demand_miss_rate::cpu.data 0.277526 # miss rate for demand accesses 127system.l2c.demand_miss_rate::total 0.166730 # miss rate for demand accesses 128system.l2c.overall_miss_rate::cpu.inst 0.014815 # miss rate for overall accesses 129system.l2c.overall_miss_rate::cpu.data 0.277526 # miss rate for overall accesses 130system.l2c.overall_miss_rate::total 0.166730 # miss rate for overall accesses 131system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.264467 # average ReadReq miss latency 132system.l2c.ReadReq_avg_miss_latency::cpu.data 52070.678172 # average ReadReq miss latency 133system.l2c.ReadReq_avg_miss_latency::total 52132.952600 # average ReadReq miss latency 134system.l2c.UpgradeReq_avg_miss_latency::cpu.data 6972.222222 # average UpgradeReq miss latency 135system.l2c.UpgradeReq_avg_miss_latency::total 6972.222222 # average UpgradeReq miss latency 136system.l2c.ReadExReq_avg_miss_latency::cpu.data 53948.294961 # average ReadExReq miss latency 137system.l2c.ReadExReq_avg_miss_latency::total 53948.294961 # average ReadExReq miss latency 138system.l2c.demand_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency 139system.l2c.demand_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency 140system.l2c.demand_avg_miss_latency::total 52650.952995 # average overall miss latency 141system.l2c.overall_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency 142system.l2c.overall_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency 143system.l2c.overall_avg_miss_latency::total 52650.952995 # average overall miss latency 144system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 145system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 146system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 147system.l2c.blocked::no_targets 0 # number of cycles access was blocked 148system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 149system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 150system.l2c.fast_writes 0 # number of fast writes performed 151system.l2c.cache_copies 0 # number of cache copies performed 152system.l2c.writebacks::writebacks 75968 # number of writebacks 153system.l2c.writebacks::total 75968 # number of writebacks 154system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 155system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 156system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 157system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 158system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 159system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 160system.l2c.ReadReq_mshr_misses::cpu.inst 15154 # number of ReadReq MSHR misses 161system.l2c.ReadReq_mshr_misses::cpu.data 273854 # number of ReadReq MSHR misses 162system.l2c.ReadReq_mshr_misses::total 289008 # number of ReadReq MSHR misses 163system.l2c.UpgradeReq_mshr_misses::cpu.data 54 # number of UpgradeReq MSHR misses 164system.l2c.UpgradeReq_mshr_misses::total 54 # number of UpgradeReq MSHR misses 165system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 166system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 167system.l2c.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses 168system.l2c.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses 169system.l2c.demand_mshr_misses::cpu.inst 15154 # number of demand (read+write) MSHR misses 170system.l2c.demand_mshr_misses::cpu.data 389249 # number of demand (read+write) MSHR misses 171system.l2c.demand_mshr_misses::total 404403 # number of demand (read+write) MSHR misses 172system.l2c.overall_mshr_misses::cpu.inst 15154 # number of overall MSHR misses 173system.l2c.overall_mshr_misses::cpu.data 389249 # number of overall MSHR misses 174system.l2c.overall_mshr_misses::total 404403 # number of overall MSHR misses 175system.l2c.ReadReq_mshr_miss_latency::cpu.inst 621904998 # number of ReadReq MSHR miss cycles 176system.l2c.ReadReq_mshr_miss_latency::cpu.data 10983272500 # number of ReadReq MSHR miss cycles 177system.l2c.ReadReq_mshr_miss_latency::total 11605177498 # number of ReadReq MSHR miss cycles 178system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2245000 # number of UpgradeReq MSHR miss cycles 179system.l2c.UpgradeReq_mshr_miss_latency::total 2245000 # number of UpgradeReq MSHR miss cycles 180system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles 181system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles 182system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4831334497 # number of ReadExReq MSHR miss cycles 183system.l2c.ReadExReq_mshr_miss_latency::total 4831334497 # number of ReadExReq MSHR miss cycles 184system.l2c.demand_mshr_miss_latency::cpu.inst 621904998 # number of demand (read+write) MSHR miss cycles 185system.l2c.demand_mshr_miss_latency::cpu.data 15814606997 # number of demand (read+write) MSHR miss cycles 186system.l2c.demand_mshr_miss_latency::total 16436511995 # number of demand (read+write) MSHR miss cycles 187system.l2c.overall_mshr_miss_latency::cpu.inst 621904998 # number of overall MSHR miss cycles 188system.l2c.overall_mshr_miss_latency::cpu.data 15814606997 # number of overall MSHR miss cycles 189system.l2c.overall_mshr_miss_latency::total 16436511995 # number of overall MSHR miss cycles 190system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500 # number of ReadReq MSHR uncacheable cycles 191system.l2c.ReadReq_mshr_uncacheable_latency::total 1333882500 # number of ReadReq MSHR uncacheable cycles 192system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500 # number of WriteReq MSHR uncacheable cycles 193system.l2c.WriteReq_mshr_uncacheable_latency::total 1884635500 # number of WriteReq MSHR uncacheable cycles 194system.l2c.overall_mshr_uncacheable_latency::cpu.data 3218518000 # number of overall MSHR uncacheable cycles 195system.l2c.overall_mshr_uncacheable_latency::total 3218518000 # number of overall MSHR uncacheable cycles 196system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for ReadReq accesses 197system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248591 # mshr miss rate for ReadReq accesses 198system.l2c.ReadReq_mshr_miss_rate::total 0.136032 # mshr miss rate for ReadReq accesses 199system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.635294 # mshr miss rate for UpgradeReq accesses 200system.l2c.UpgradeReq_mshr_miss_rate::total 0.635294 # mshr miss rate for UpgradeReq accesses 201system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 202system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses 203system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383447 # mshr miss rate for ReadExReq accesses 204system.l2c.ReadExReq_mshr_miss_rate::total 0.383447 # mshr miss rate for ReadExReq accesses 205system.l2c.demand_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for demand accesses 206system.l2c.demand_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for demand accesses 207system.l2c.demand_mshr_miss_rate::total 0.166729 # mshr miss rate for demand accesses 208system.l2c.overall_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for overall accesses 209system.l2c.overall_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for overall accesses 210system.l2c.overall_mshr_miss_rate::total 0.166729 # mshr miss rate for overall accesses 211system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472 # average ReadReq mshr miss latency 212system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645 # average ReadReq mshr miss latency 213system.l2c.ReadReq_avg_mshr_miss_latency::total 40155.211960 # average ReadReq mshr miss latency 214system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074 # average UpgradeReq mshr miss latency 215system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41574.074074 # average UpgradeReq mshr miss latency 216system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 217system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 218system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539 # average ReadExReq mshr miss latency 219system.l2c.ReadExReq_avg_mshr_miss_latency::total 41867.797539 # average ReadExReq mshr miss latency 220system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency 221system.l2c.demand_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency 222system.l2c.demand_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency 223system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency 224system.l2c.overall_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency 225system.l2c.overall_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency 226system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 227system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 228system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 229system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 230system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 231system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 232system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 41system.cpu.l2cache.replacements 338398 # number of replacements 42system.cpu.l2cache.tagsinuse 65348.140689 # Cycle average of tags in use 43system.cpu.l2cache.total_refs 2559915 # Total number of references to valid blocks. 44system.cpu.l2cache.sampled_refs 403567 # Sample count of references to valid blocks. 45system.cpu.l2cache.avg_refs 6.343222 # Average number of references to valid blocks. 46system.cpu.l2cache.warmup_cycle 4870006000 # Cycle when the warmup percentage was hit. 47system.cpu.l2cache.occ_blocks::writebacks 53844.889123 # Average occupied blocks per requestor 48system.cpu.l2cache.occ_blocks::cpu.inst 5363.726417 # Average occupied blocks per requestor 49system.cpu.l2cache.occ_blocks::cpu.data 6139.525149 # Average occupied blocks per requestor 50system.cpu.l2cache.occ_percent::writebacks 0.821608 # Average percentage of cache occupancy 51system.cpu.l2cache.occ_percent::cpu.inst 0.081844 # Average percentage of cache occupancy 52system.cpu.l2cache.occ_percent::cpu.data 0.093682 # Average percentage of cache occupancy 53system.cpu.l2cache.occ_percent::total 0.997133 # Average percentage of cache occupancy 54system.cpu.l2cache.ReadReq_hits::cpu.inst 1007783 # number of ReadReq hits 55system.cpu.l2cache.ReadReq_hits::cpu.data 827771 # number of ReadReq hits 56system.cpu.l2cache.ReadReq_hits::total 1835554 # number of ReadReq hits 57system.cpu.l2cache.Writeback_hits::writebacks 841020 # number of Writeback hits 58system.cpu.l2cache.Writeback_hits::total 841020 # number of Writeback hits 59system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 60system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits 61system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 62system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 63system.cpu.l2cache.ReadExReq_hits::cpu.data 185546 # number of ReadExReq hits 64system.cpu.l2cache.ReadExReq_hits::total 185546 # number of ReadExReq hits 65system.cpu.l2cache.demand_hits::cpu.inst 1007783 # number of demand (read+write) hits 66system.cpu.l2cache.demand_hits::cpu.data 1013317 # number of demand (read+write) hits 67system.cpu.l2cache.demand_hits::total 2021100 # number of demand (read+write) hits 68system.cpu.l2cache.overall_hits::cpu.inst 1007783 # number of overall hits 69system.cpu.l2cache.overall_hits::cpu.data 1013317 # number of overall hits 70system.cpu.l2cache.overall_hits::total 2021100 # number of overall hits 71system.cpu.l2cache.ReadReq_misses::cpu.inst 15155 # number of ReadReq misses 72system.cpu.l2cache.ReadReq_misses::cpu.data 273854 # number of ReadReq misses 73system.cpu.l2cache.ReadReq_misses::total 289009 # number of ReadReq misses 74system.cpu.l2cache.UpgradeReq_misses::cpu.data 54 # number of UpgradeReq misses 75system.cpu.l2cache.UpgradeReq_misses::total 54 # number of UpgradeReq misses 76system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 77system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 78system.cpu.l2cache.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses 79system.cpu.l2cache.ReadExReq_misses::total 115395 # number of ReadExReq misses 80system.cpu.l2cache.demand_misses::cpu.inst 15155 # number of demand (read+write) misses 81system.cpu.l2cache.demand_misses::cpu.data 389249 # number of demand (read+write) misses 82system.cpu.l2cache.demand_misses::total 404404 # number of demand (read+write) misses 83system.cpu.l2cache.overall_misses::cpu.inst 15155 # number of overall misses 84system.cpu.l2cache.overall_misses::cpu.data 389249 # number of overall misses 85system.cpu.l2cache.overall_misses::total 404404 # number of overall misses 86system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 807128998 # number of ReadReq miss cycles 87system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14259763500 # number of ReadReq miss cycles 88system.cpu.l2cache.ReadReq_miss_latency::total 15066892498 # number of ReadReq miss cycles 89system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 376500 # number of UpgradeReq miss cycles 90system.cpu.l2cache.UpgradeReq_miss_latency::total 376500 # number of UpgradeReq miss cycles 91system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6225363497 # number of ReadExReq miss cycles 92system.cpu.l2cache.ReadExReq_miss_latency::total 6225363497 # number of ReadExReq miss cycles 93system.cpu.l2cache.demand_miss_latency::cpu.inst 807128998 # number of demand (read+write) miss cycles 94system.cpu.l2cache.demand_miss_latency::cpu.data 20485126997 # number of demand (read+write) miss cycles 95system.cpu.l2cache.demand_miss_latency::total 21292255995 # number of demand (read+write) miss cycles 96system.cpu.l2cache.overall_miss_latency::cpu.inst 807128998 # number of overall miss cycles 97system.cpu.l2cache.overall_miss_latency::cpu.data 20485126997 # number of overall miss cycles 98system.cpu.l2cache.overall_miss_latency::total 21292255995 # number of overall miss cycles 99system.cpu.l2cache.ReadReq_accesses::cpu.inst 1022938 # number of ReadReq accesses(hits+misses) 100system.cpu.l2cache.ReadReq_accesses::cpu.data 1101625 # number of ReadReq accesses(hits+misses) 101system.cpu.l2cache.ReadReq_accesses::total 2124563 # number of ReadReq accesses(hits+misses) 102system.cpu.l2cache.Writeback_accesses::writebacks 841020 # number of Writeback accesses(hits+misses) 103system.cpu.l2cache.Writeback_accesses::total 841020 # number of Writeback accesses(hits+misses) 104system.cpu.l2cache.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses) 105system.cpu.l2cache.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses) 106system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 107system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 108system.cpu.l2cache.ReadExReq_accesses::cpu.data 300941 # number of ReadExReq accesses(hits+misses) 109system.cpu.l2cache.ReadExReq_accesses::total 300941 # number of ReadExReq accesses(hits+misses) 110system.cpu.l2cache.demand_accesses::cpu.inst 1022938 # number of demand (read+write) accesses 111system.cpu.l2cache.demand_accesses::cpu.data 1402566 # number of demand (read+write) accesses 112system.cpu.l2cache.demand_accesses::total 2425504 # number of demand (read+write) accesses 113system.cpu.l2cache.overall_accesses::cpu.inst 1022938 # number of overall (read+write) accesses 114system.cpu.l2cache.overall_accesses::cpu.data 1402566 # number of overall (read+write) accesses 115system.cpu.l2cache.overall_accesses::total 2425504 # number of overall (read+write) accesses 116system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014815 # miss rate for ReadReq accesses 117system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248591 # miss rate for ReadReq accesses 118system.cpu.l2cache.ReadReq_miss_rate::total 0.136032 # miss rate for ReadReq accesses 119system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.635294 # miss rate for UpgradeReq accesses 120system.cpu.l2cache.UpgradeReq_miss_rate::total 0.635294 # miss rate for UpgradeReq accesses 121system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 122system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses 123system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383447 # miss rate for ReadExReq accesses 124system.cpu.l2cache.ReadExReq_miss_rate::total 0.383447 # miss rate for ReadExReq accesses 125system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014815 # miss rate for demand accesses 126system.cpu.l2cache.demand_miss_rate::cpu.data 0.277526 # miss rate for demand accesses 127system.cpu.l2cache.demand_miss_rate::total 0.166730 # miss rate for demand accesses 128system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014815 # miss rate for overall accesses 129system.cpu.l2cache.overall_miss_rate::cpu.data 0.277526 # miss rate for overall accesses 130system.cpu.l2cache.overall_miss_rate::total 0.166730 # miss rate for overall accesses 131system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.264467 # average ReadReq miss latency 132system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52070.678172 # average ReadReq miss latency 133system.cpu.l2cache.ReadReq_avg_miss_latency::total 52132.952600 # average ReadReq miss latency 134system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6972.222222 # average UpgradeReq miss latency 135system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6972.222222 # average UpgradeReq miss latency 136system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53948.294961 # average ReadExReq miss latency 137system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53948.294961 # average ReadExReq miss latency 138system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency 139system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency 140system.cpu.l2cache.demand_avg_miss_latency::total 52650.952995 # average overall miss latency 141system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.264467 # average overall miss latency 142system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52627.307962 # average overall miss latency 143system.cpu.l2cache.overall_avg_miss_latency::total 52650.952995 # average overall miss latency 144system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 145system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 146system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 147system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 148system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 149system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 150system.cpu.l2cache.fast_writes 0 # number of fast writes performed 151system.cpu.l2cache.cache_copies 0 # number of cache copies performed 152system.cpu.l2cache.writebacks::writebacks 75968 # number of writebacks 153system.cpu.l2cache.writebacks::total 75968 # number of writebacks 154system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 155system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 156system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 157system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 158system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 159system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 160system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15154 # number of ReadReq MSHR misses 161system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273854 # number of ReadReq MSHR misses 162system.cpu.l2cache.ReadReq_mshr_misses::total 289008 # number of ReadReq MSHR misses 163system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 54 # number of UpgradeReq MSHR misses 164system.cpu.l2cache.UpgradeReq_mshr_misses::total 54 # number of UpgradeReq MSHR misses 165system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 166system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 167system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses 168system.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses 169system.cpu.l2cache.demand_mshr_misses::cpu.inst 15154 # number of demand (read+write) MSHR misses 170system.cpu.l2cache.demand_mshr_misses::cpu.data 389249 # number of demand (read+write) MSHR misses 171system.cpu.l2cache.demand_mshr_misses::total 404403 # number of demand (read+write) MSHR misses 172system.cpu.l2cache.overall_mshr_misses::cpu.inst 15154 # number of overall MSHR misses 173system.cpu.l2cache.overall_mshr_misses::cpu.data 389249 # number of overall MSHR misses 174system.cpu.l2cache.overall_mshr_misses::total 404403 # number of overall MSHR misses 175system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 621904998 # number of ReadReq MSHR miss cycles 176system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10983272500 # number of ReadReq MSHR miss cycles 177system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11605177498 # number of ReadReq MSHR miss cycles 178system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2245000 # number of UpgradeReq MSHR miss cycles 179system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2245000 # number of UpgradeReq MSHR miss cycles 180system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles 181system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles 182system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4831334497 # number of ReadExReq MSHR miss cycles 183system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4831334497 # number of ReadExReq MSHR miss cycles 184system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 621904998 # number of demand (read+write) MSHR miss cycles 185system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15814606997 # number of demand (read+write) MSHR miss cycles 186system.cpu.l2cache.demand_mshr_miss_latency::total 16436511995 # number of demand (read+write) MSHR miss cycles 187system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 621904998 # number of overall MSHR miss cycles 188system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15814606997 # number of overall MSHR miss cycles 189system.cpu.l2cache.overall_mshr_miss_latency::total 16436511995 # number of overall MSHR miss cycles 190system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333882500 # number of ReadReq MSHR uncacheable cycles 191system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333882500 # number of ReadReq MSHR uncacheable cycles 192system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884635500 # number of WriteReq MSHR uncacheable cycles 193system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884635500 # number of WriteReq MSHR uncacheable cycles 194system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218518000 # number of overall MSHR uncacheable cycles 195system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218518000 # number of overall MSHR uncacheable cycles 196system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for ReadReq accesses 197system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248591 # mshr miss rate for ReadReq accesses 198system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136032 # mshr miss rate for ReadReq accesses 199system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.635294 # mshr miss rate for UpgradeReq accesses 200system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.635294 # mshr miss rate for UpgradeReq accesses 201system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 202system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses 203system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383447 # mshr miss rate for ReadExReq accesses 204system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383447 # mshr miss rate for ReadExReq accesses 205system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for demand accesses 206system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for demand accesses 207system.cpu.l2cache.demand_mshr_miss_rate::total 0.166729 # mshr miss rate for demand accesses 208system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014814 # mshr miss rate for overall accesses 209system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277526 # mshr miss rate for overall accesses 210system.cpu.l2cache.overall_mshr_miss_rate::total 0.166729 # mshr miss rate for overall accesses 211system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41038.999472 # average ReadReq mshr miss latency 212system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40106.306645 # average ReadReq mshr miss latency 213system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40155.211960 # average ReadReq mshr miss latency 214system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41574.074074 # average UpgradeReq mshr miss latency 215system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41574.074074 # average UpgradeReq mshr miss latency 216system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 217system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 218system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41867.797539 # average ReadExReq mshr miss latency 219system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41867.797539 # average ReadExReq mshr miss latency 220system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency 221system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency 222system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency 223system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41038.999472 # average overall mshr miss latency 224system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40628.510277 # average overall mshr miss latency 225system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40643.892343 # average overall mshr miss latency 226system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 227system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 228system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 229system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 230system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 231system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 232system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 233system.iocache.replacements 41685 # number of replacements 234system.iocache.tagsinuse 1.309507 # Cycle average of tags in use 235system.iocache.total_refs 0 # Total number of references to valid blocks. 236system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 237system.iocache.avg_refs 0 # Average number of references to valid blocks. 238system.iocache.warmup_cycle 1711308479000 # Cycle when the warmup percentage was hit. 239system.iocache.occ_blocks::tsunami.ide 1.309507 # Average occupied blocks per requestor 240system.iocache.occ_percent::tsunami.ide 0.081844 # Average percentage of cache occupancy --- 763 unchanged lines hidden --- | 233system.iocache.replacements 41685 # number of replacements 234system.iocache.tagsinuse 1.309507 # Cycle average of tags in use 235system.iocache.total_refs 0 # Total number of references to valid blocks. 236system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 237system.iocache.avg_refs 0 # Average number of references to valid blocks. 238system.iocache.warmup_cycle 1711308479000 # Cycle when the warmup percentage was hit. 239system.iocache.occ_blocks::tsunami.ide 1.309507 # Average occupied blocks per requestor 240system.iocache.occ_percent::tsunami.ide 0.081844 # Average percentage of cache occupancy --- 763 unchanged lines hidden --- |