| stats.txt (9096:8971a998190a) | stats.txt (9134:275232ad377d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.865402 # Number of seconds simulated 4sim_ticks 1865402113500 # Number of ticks simulated 5final_tick 1865402113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.864424 # Number of seconds simulated 4sim_ticks 1864423957500 # Number of ticks simulated 5final_tick 1864423957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 131129 # Simulator instruction rate (inst/s) 8host_op_rate 131129 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4607058697 # Simulator tick rate (ticks/s) 10host_mem_usage 298956 # Number of bytes of host memory used 11host_seconds 404.90 # Real time elapsed on the host 12sim_insts 53094243 # Number of instructions simulated 13sim_ops 53094243 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 967424 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24877312 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28497024 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 967424 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 967424 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7516928 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7516928 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15116 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388708 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 445266 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117452 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117452 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 518614 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13336166 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1421832 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15276612 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 518614 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 518614 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4029656 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4029656 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4029656 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 518614 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13336166 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1421832 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19306267 # Total bandwidth to/from this memory (bytes/s) 41system.l2c.replacements 338323 # number of replacements 42system.l2c.tagsinuse 65346.781313 # Cycle average of tags in use 43system.l2c.total_refs 2566599 # Total number of references to valid blocks. 44system.l2c.sampled_refs 403491 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.360982 # Average number of references to valid blocks. | 7host_inst_rate 128916 # Simulator instruction rate (inst/s) 8host_op_rate 128916 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4527170908 # Simulator tick rate (ticks/s) 10host_mem_usage 303408 # Number of bytes of host memory used 11host_seconds 411.83 # Real time elapsed on the host 12sim_insts 53091408 # Number of instructions simulated 13sim_ops 53091408 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 967616 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24878144 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652032 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28497792 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 967616 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 967616 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7517760 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7517760 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15119 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388721 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41438 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 445278 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117465 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117465 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 518989 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13343609 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1422440 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15285039 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 518989 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 518989 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4032216 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4032216 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4032216 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 518989 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13343609 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1422440 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19317254 # Total bandwidth to/from this memory (bytes/s) 41system.l2c.replacements 338334 # number of replacements 42system.l2c.tagsinuse 65348.280232 # Cycle average of tags in use 43system.l2c.total_refs 2564971 # Total number of references to valid blocks. 44system.l2c.sampled_refs 403499 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.356821 # Average number of references to valid blocks. |
| 46system.l2c.warmup_cycle 4861120000 # Cycle when the warmup percentage was hit. | 46system.l2c.warmup_cycle 4861120000 # Cycle when the warmup percentage was hit. |
| 47system.l2c.occ_blocks::writebacks 53937.288272 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 5357.413768 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 6052.079273 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.823018 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.081748 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.092347 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.997113 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 1010692 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 829338 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1840030 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 843192 # number of Writeback hits 58system.l2c.Writeback_hits::total 843192 # number of Writeback hits | 47system.l2c.occ_blocks::writebacks 53937.270475 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 5353.133006 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 6057.876752 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.823017 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.081682 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.092436 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.997136 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 1009873 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 829098 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1838971 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 842689 # number of Writeback hits 58system.l2c.Writeback_hits::total 842689 # number of Writeback hits |
| 59system.l2c.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 35 # number of UpgradeReq hits | 59system.l2c.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 35 # number of UpgradeReq hits |
| 61system.l2c.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits 62system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits 63system.l2c.ReadExReq_hits::cpu.data 185767 # number of ReadExReq hits 64system.l2c.ReadExReq_hits::total 185767 # number of ReadExReq hits 65system.l2c.demand_hits::cpu.inst 1010692 # number of demand (read+write) hits 66system.l2c.demand_hits::cpu.data 1015105 # number of demand (read+write) hits 67system.l2c.demand_hits::total 2025797 # number of demand (read+write) hits 68system.l2c.overall_hits::cpu.inst 1010692 # number of overall hits 69system.l2c.overall_hits::cpu.data 1015105 # number of overall hits 70system.l2c.overall_hits::total 2025797 # number of overall hits 71system.l2c.ReadReq_misses::cpu.inst 15118 # number of ReadReq misses 72system.l2c.ReadReq_misses::cpu.data 273845 # number of ReadReq misses 73system.l2c.ReadReq_misses::total 288963 # number of ReadReq misses 74system.l2c.UpgradeReq_misses::cpu.data 49 # number of UpgradeReq misses 75system.l2c.UpgradeReq_misses::total 49 # number of UpgradeReq misses 76system.l2c.ReadExReq_misses::cpu.data 115352 # number of ReadExReq misses 77system.l2c.ReadExReq_misses::total 115352 # number of ReadExReq misses 78system.l2c.demand_misses::cpu.inst 15118 # number of demand (read+write) misses 79system.l2c.demand_misses::cpu.data 389197 # number of demand (read+write) misses 80system.l2c.demand_misses::total 404315 # number of demand (read+write) misses 81system.l2c.overall_misses::cpu.inst 15118 # number of overall misses 82system.l2c.overall_misses::cpu.data 389197 # number of overall misses 83system.l2c.overall_misses::total 404315 # number of overall misses 84system.l2c.ReadReq_miss_latency::cpu.inst 805739998 # number of ReadReq miss cycles 85system.l2c.ReadReq_miss_latency::cpu.data 14260725000 # number of ReadReq miss cycles 86system.l2c.ReadReq_miss_latency::total 15066464998 # number of ReadReq miss cycles 87system.l2c.UpgradeReq_miss_latency::cpu.data 501500 # number of UpgradeReq miss cycles 88system.l2c.UpgradeReq_miss_latency::total 501500 # number of UpgradeReq miss cycles 89system.l2c.ReadExReq_miss_latency::cpu.data 6190534997 # number of ReadExReq miss cycles 90system.l2c.ReadExReq_miss_latency::total 6190534997 # number of ReadExReq miss cycles 91system.l2c.demand_miss_latency::cpu.inst 805739998 # number of demand (read+write) miss cycles 92system.l2c.demand_miss_latency::cpu.data 20451259997 # number of demand (read+write) miss cycles 93system.l2c.demand_miss_latency::total 21256999995 # number of demand (read+write) miss cycles 94system.l2c.overall_miss_latency::cpu.inst 805739998 # number of overall miss cycles 95system.l2c.overall_miss_latency::cpu.data 20451259997 # number of overall miss cycles 96system.l2c.overall_miss_latency::total 21256999995 # number of overall miss cycles 97system.l2c.ReadReq_accesses::cpu.inst 1025810 # number of ReadReq accesses(hits+misses) 98system.l2c.ReadReq_accesses::cpu.data 1103183 # number of ReadReq accesses(hits+misses) 99system.l2c.ReadReq_accesses::total 2128993 # number of ReadReq accesses(hits+misses) 100system.l2c.Writeback_accesses::writebacks 843192 # number of Writeback accesses(hits+misses) 101system.l2c.Writeback_accesses::total 843192 # number of Writeback accesses(hits+misses) 102system.l2c.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) 103system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) | 61system.l2c.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 62system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 63system.l2c.ReadExReq_hits::cpu.data 185872 # number of ReadExReq hits 64system.l2c.ReadExReq_hits::total 185872 # number of ReadExReq hits 65system.l2c.demand_hits::cpu.inst 1009873 # number of demand (read+write) hits 66system.l2c.demand_hits::cpu.data 1014970 # number of demand (read+write) hits 67system.l2c.demand_hits::total 2024843 # number of demand (read+write) hits 68system.l2c.overall_hits::cpu.inst 1009873 # number of overall hits 69system.l2c.overall_hits::cpu.data 1014970 # number of overall hits 70system.l2c.overall_hits::total 2024843 # number of overall hits 71system.l2c.ReadReq_misses::cpu.inst 15121 # number of ReadReq misses 72system.l2c.ReadReq_misses::cpu.data 273859 # number of ReadReq misses 73system.l2c.ReadReq_misses::total 288980 # number of ReadReq misses 74system.l2c.UpgradeReq_misses::cpu.data 50 # number of UpgradeReq misses 75system.l2c.UpgradeReq_misses::total 50 # number of UpgradeReq misses 76system.l2c.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 77system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 78system.l2c.ReadExReq_misses::cpu.data 115376 # number of ReadExReq misses 79system.l2c.ReadExReq_misses::total 115376 # number of ReadExReq misses 80system.l2c.demand_misses::cpu.inst 15121 # number of demand (read+write) misses 81system.l2c.demand_misses::cpu.data 389235 # number of demand (read+write) misses 82system.l2c.demand_misses::total 404356 # number of demand (read+write) misses 83system.l2c.overall_misses::cpu.inst 15121 # number of overall misses 84system.l2c.overall_misses::cpu.data 389235 # number of overall misses 85system.l2c.overall_misses::total 404356 # number of overall misses 86system.l2c.ReadReq_miss_latency::cpu.inst 805852997 # number of ReadReq miss cycles 87system.l2c.ReadReq_miss_latency::cpu.data 14261584000 # number of ReadReq miss cycles 88system.l2c.ReadReq_miss_latency::total 15067436997 # number of ReadReq miss cycles 89system.l2c.UpgradeReq_miss_latency::cpu.data 397000 # number of UpgradeReq miss cycles 90system.l2c.UpgradeReq_miss_latency::total 397000 # number of UpgradeReq miss cycles 91system.l2c.ReadExReq_miss_latency::cpu.data 6192128996 # number of ReadExReq miss cycles 92system.l2c.ReadExReq_miss_latency::total 6192128996 # number of ReadExReq miss cycles 93system.l2c.demand_miss_latency::cpu.inst 805852997 # number of demand (read+write) miss cycles 94system.l2c.demand_miss_latency::cpu.data 20453712996 # number of demand (read+write) miss cycles 95system.l2c.demand_miss_latency::total 21259565993 # number of demand (read+write) miss cycles 96system.l2c.overall_miss_latency::cpu.inst 805852997 # number of overall miss cycles 97system.l2c.overall_miss_latency::cpu.data 20453712996 # number of overall miss cycles 98system.l2c.overall_miss_latency::total 21259565993 # number of overall miss cycles 99system.l2c.ReadReq_accesses::cpu.inst 1024994 # number of ReadReq accesses(hits+misses) 100system.l2c.ReadReq_accesses::cpu.data 1102957 # number of ReadReq accesses(hits+misses) 101system.l2c.ReadReq_accesses::total 2127951 # number of ReadReq accesses(hits+misses) 102system.l2c.Writeback_accesses::writebacks 842689 # number of Writeback accesses(hits+misses) 103system.l2c.Writeback_accesses::total 842689 # number of Writeback accesses(hits+misses) 104system.l2c.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses) 105system.l2c.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses) |
| 104system.l2c.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) 105system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) | 106system.l2c.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) 107system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) |
| 106system.l2c.ReadExReq_accesses::cpu.data 301119 # number of ReadExReq accesses(hits+misses) 107system.l2c.ReadExReq_accesses::total 301119 # number of ReadExReq accesses(hits+misses) 108system.l2c.demand_accesses::cpu.inst 1025810 # number of demand (read+write) accesses 109system.l2c.demand_accesses::cpu.data 1404302 # number of demand (read+write) accesses 110system.l2c.demand_accesses::total 2430112 # number of demand (read+write) accesses 111system.l2c.overall_accesses::cpu.inst 1025810 # number of overall (read+write) accesses 112system.l2c.overall_accesses::cpu.data 1404302 # number of overall (read+write) accesses 113system.l2c.overall_accesses::total 2430112 # number of overall (read+write) accesses 114system.l2c.ReadReq_miss_rate::cpu.inst 0.014738 # miss rate for ReadReq accesses 115system.l2c.ReadReq_miss_rate::cpu.data 0.248232 # miss rate for ReadReq accesses 116system.l2c.ReadReq_miss_rate::total 0.135728 # miss rate for ReadReq accesses 117system.l2c.UpgradeReq_miss_rate::cpu.data 0.583333 # miss rate for UpgradeReq accesses 118system.l2c.UpgradeReq_miss_rate::total 0.583333 # miss rate for UpgradeReq accesses 119system.l2c.ReadExReq_miss_rate::cpu.data 0.383078 # miss rate for ReadExReq accesses 120system.l2c.ReadExReq_miss_rate::total 0.383078 # miss rate for ReadExReq accesses 121system.l2c.demand_miss_rate::cpu.inst 0.014738 # miss rate for demand accesses 122system.l2c.demand_miss_rate::cpu.data 0.277146 # miss rate for demand accesses 123system.l2c.demand_miss_rate::total 0.166377 # miss rate for demand accesses 124system.l2c.overall_miss_rate::cpu.inst 0.014738 # miss rate for overall accesses 125system.l2c.overall_miss_rate::cpu.data 0.277146 # miss rate for overall accesses 126system.l2c.overall_miss_rate::total 0.166377 # miss rate for overall accesses 127system.l2c.ReadReq_avg_miss_latency::cpu.inst 53296.732240 # average ReadReq miss latency 128system.l2c.ReadReq_avg_miss_latency::cpu.data 52075.900601 # average ReadReq miss latency 129system.l2c.ReadReq_avg_miss_latency::total 52139.772213 # average ReadReq miss latency 130system.l2c.UpgradeReq_avg_miss_latency::cpu.data 10234.693878 # average UpgradeReq miss latency 131system.l2c.UpgradeReq_avg_miss_latency::total 10234.693878 # average UpgradeReq miss latency 132system.l2c.ReadExReq_avg_miss_latency::cpu.data 53666.473030 # average ReadExReq miss latency 133system.l2c.ReadExReq_avg_miss_latency::total 53666.473030 # average ReadExReq miss latency 134system.l2c.demand_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency 135system.l2c.demand_avg_miss_latency::cpu.data 52547.321786 # average overall miss latency 136system.l2c.demand_avg_miss_latency::total 52575.343470 # average overall miss latency 137system.l2c.overall_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency 138system.l2c.overall_avg_miss_latency::cpu.data 52547.321786 # average overall miss latency 139system.l2c.overall_avg_miss_latency::total 52575.343470 # average overall miss latency | 108system.l2c.ReadExReq_accesses::cpu.data 301248 # number of ReadExReq accesses(hits+misses) 109system.l2c.ReadExReq_accesses::total 301248 # number of ReadExReq accesses(hits+misses) 110system.l2c.demand_accesses::cpu.inst 1024994 # number of demand (read+write) accesses 111system.l2c.demand_accesses::cpu.data 1404205 # number of demand (read+write) accesses 112system.l2c.demand_accesses::total 2429199 # number of demand (read+write) accesses 113system.l2c.overall_accesses::cpu.inst 1024994 # number of overall (read+write) accesses 114system.l2c.overall_accesses::cpu.data 1404205 # number of overall (read+write) accesses 115system.l2c.overall_accesses::total 2429199 # number of overall (read+write) accesses 116system.l2c.ReadReq_miss_rate::cpu.inst 0.014752 # miss rate for ReadReq accesses 117system.l2c.ReadReq_miss_rate::cpu.data 0.248295 # miss rate for ReadReq accesses 118system.l2c.ReadReq_miss_rate::total 0.135802 # miss rate for ReadReq accesses 119system.l2c.UpgradeReq_miss_rate::cpu.data 0.588235 # miss rate for UpgradeReq accesses 120system.l2c.UpgradeReq_miss_rate::total 0.588235 # miss rate for UpgradeReq accesses 121system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses 122system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses 123system.l2c.ReadExReq_miss_rate::cpu.data 0.382993 # miss rate for ReadExReq accesses 124system.l2c.ReadExReq_miss_rate::total 0.382993 # miss rate for ReadExReq accesses 125system.l2c.demand_miss_rate::cpu.inst 0.014752 # miss rate for demand accesses 126system.l2c.demand_miss_rate::cpu.data 0.277192 # miss rate for demand accesses 127system.l2c.demand_miss_rate::total 0.166457 # miss rate for demand accesses 128system.l2c.overall_miss_rate::cpu.inst 0.014752 # miss rate for overall accesses 129system.l2c.overall_miss_rate::cpu.data 0.277192 # miss rate for overall accesses 130system.l2c.overall_miss_rate::total 0.166457 # miss rate for overall accesses 131system.l2c.ReadReq_avg_miss_latency::cpu.inst 53293.631175 # average ReadReq miss latency 132system.l2c.ReadReq_avg_miss_latency::cpu.data 52076.375069 # average ReadReq miss latency 133system.l2c.ReadReq_avg_miss_latency::total 52140.068506 # average ReadReq miss latency 134system.l2c.UpgradeReq_avg_miss_latency::cpu.data 7940 # average UpgradeReq miss latency 135system.l2c.UpgradeReq_avg_miss_latency::total 7940 # average UpgradeReq miss latency 136system.l2c.ReadExReq_avg_miss_latency::cpu.data 53669.125260 # average ReadExReq miss latency 137system.l2c.ReadExReq_avg_miss_latency::total 53669.125260 # average ReadExReq miss latency 138system.l2c.demand_avg_miss_latency::cpu.inst 53293.631175 # average overall miss latency 139system.l2c.demand_avg_miss_latency::cpu.data 52548.493830 # average overall miss latency 140system.l2c.demand_avg_miss_latency::total 52576.358439 # average overall miss latency 141system.l2c.overall_avg_miss_latency::cpu.inst 53293.631175 # average overall miss latency 142system.l2c.overall_avg_miss_latency::cpu.data 52548.493830 # average overall miss latency 143system.l2c.overall_avg_miss_latency::total 52576.358439 # average overall miss latency |
| 140system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 141system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 142system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 143system.l2c.blocked::no_targets 0 # number of cycles access was blocked 144system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 145system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146system.l2c.fast_writes 0 # number of fast writes performed 147system.l2c.cache_copies 0 # number of cache copies performed | 144system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 145system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 146system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 147system.l2c.blocked::no_targets 0 # number of cycles access was blocked 148system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 149system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 150system.l2c.fast_writes 0 # number of fast writes performed 151system.l2c.cache_copies 0 # number of cache copies performed |
| 148system.l2c.writebacks::writebacks 75940 # number of writebacks 149system.l2c.writebacks::total 75940 # number of writebacks | 152system.l2c.writebacks::writebacks 75953 # number of writebacks 153system.l2c.writebacks::total 75953 # number of writebacks |
| 150system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 151system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 152system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 153system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 154system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 155system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits | 154system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 155system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 156system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 157system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 158system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 159system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 156system.l2c.ReadReq_mshr_misses::cpu.inst 15117 # number of ReadReq MSHR misses 157system.l2c.ReadReq_mshr_misses::cpu.data 273845 # number of ReadReq MSHR misses 158system.l2c.ReadReq_mshr_misses::total 288962 # number of ReadReq MSHR misses 159system.l2c.UpgradeReq_mshr_misses::cpu.data 49 # number of UpgradeReq MSHR misses 160system.l2c.UpgradeReq_mshr_misses::total 49 # number of UpgradeReq MSHR misses 161system.l2c.ReadExReq_mshr_misses::cpu.data 115352 # number of ReadExReq MSHR misses 162system.l2c.ReadExReq_mshr_misses::total 115352 # number of ReadExReq MSHR misses 163system.l2c.demand_mshr_misses::cpu.inst 15117 # number of demand (read+write) MSHR misses 164system.l2c.demand_mshr_misses::cpu.data 389197 # number of demand (read+write) MSHR misses 165system.l2c.demand_mshr_misses::total 404314 # number of demand (read+write) MSHR misses 166system.l2c.overall_mshr_misses::cpu.inst 15117 # number of overall MSHR misses 167system.l2c.overall_mshr_misses::cpu.data 389197 # number of overall MSHR misses 168system.l2c.overall_mshr_misses::total 404314 # number of overall MSHR misses 169system.l2c.ReadReq_mshr_miss_latency::cpu.inst 620965998 # number of ReadReq MSHR miss cycles 170system.l2c.ReadReq_mshr_miss_latency::cpu.data 10975082500 # number of ReadReq MSHR miss cycles 171system.l2c.ReadReq_mshr_miss_latency::total 11596048498 # number of ReadReq MSHR miss cycles 172system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2065000 # number of UpgradeReq MSHR miss cycles 173system.l2c.UpgradeReq_mshr_miss_latency::total 2065000 # number of UpgradeReq MSHR miss cycles 174system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4796966997 # number of ReadExReq MSHR miss cycles 175system.l2c.ReadExReq_mshr_miss_latency::total 4796966997 # number of ReadExReq MSHR miss cycles 176system.l2c.demand_mshr_miss_latency::cpu.inst 620965998 # number of demand (read+write) MSHR miss cycles 177system.l2c.demand_mshr_miss_latency::cpu.data 15772049497 # number of demand (read+write) MSHR miss cycles 178system.l2c.demand_mshr_miss_latency::total 16393015495 # number of demand (read+write) MSHR miss cycles 179system.l2c.overall_mshr_miss_latency::cpu.inst 620965998 # number of overall MSHR miss cycles 180system.l2c.overall_mshr_miss_latency::cpu.data 15772049497 # number of overall MSHR miss cycles 181system.l2c.overall_mshr_miss_latency::total 16393015495 # number of overall MSHR miss cycles 182system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810224030 # number of ReadReq MSHR uncacheable cycles 183system.l2c.ReadReq_mshr_uncacheable_latency::total 810224030 # number of ReadReq MSHR uncacheable cycles 184system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1103797000 # number of WriteReq MSHR uncacheable cycles 185system.l2c.WriteReq_mshr_uncacheable_latency::total 1103797000 # number of WriteReq MSHR uncacheable cycles 186system.l2c.overall_mshr_uncacheable_latency::cpu.data 1914021030 # number of overall MSHR uncacheable cycles 187system.l2c.overall_mshr_uncacheable_latency::total 1914021030 # number of overall MSHR uncacheable cycles 188system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for ReadReq accesses 189system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248232 # mshr miss rate for ReadReq accesses 190system.l2c.ReadReq_mshr_miss_rate::total 0.135727 # mshr miss rate for ReadReq accesses 191system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.583333 # mshr miss rate for UpgradeReq accesses 192system.l2c.UpgradeReq_mshr_miss_rate::total 0.583333 # mshr miss rate for UpgradeReq accesses 193system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383078 # mshr miss rate for ReadExReq accesses 194system.l2c.ReadExReq_mshr_miss_rate::total 0.383078 # mshr miss rate for ReadExReq accesses 195system.l2c.demand_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for demand accesses 196system.l2c.demand_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for demand accesses 197system.l2c.demand_mshr_miss_rate::total 0.166377 # mshr miss rate for demand accesses 198system.l2c.overall_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for overall accesses 199system.l2c.overall_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for overall accesses 200system.l2c.overall_mshr_miss_rate::total 0.166377 # mshr miss rate for overall accesses 201system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41077.330026 # average ReadReq mshr miss latency 202system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40077.717322 # average ReadReq mshr miss latency 203system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.011898 # average ReadReq mshr miss latency 204system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average UpgradeReq mshr miss latency 205system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42142.857143 # average UpgradeReq mshr miss latency 206system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.468800 # average ReadExReq mshr miss latency 207system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.468800 # average ReadExReq mshr miss latency 208system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency 209system.l2c.demand_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency 210system.l2c.demand_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency 211system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency 212system.l2c.overall_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency 213system.l2c.overall_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency | 160system.l2c.ReadReq_mshr_misses::cpu.inst 15120 # number of ReadReq MSHR misses 161system.l2c.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses 162system.l2c.ReadReq_mshr_misses::total 288979 # number of ReadReq MSHR misses 163system.l2c.UpgradeReq_mshr_misses::cpu.data 50 # number of UpgradeReq MSHR misses 164system.l2c.UpgradeReq_mshr_misses::total 50 # number of UpgradeReq MSHR misses 165system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 166system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 167system.l2c.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses 168system.l2c.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses 169system.l2c.demand_mshr_misses::cpu.inst 15120 # number of demand (read+write) MSHR misses 170system.l2c.demand_mshr_misses::cpu.data 389235 # number of demand (read+write) MSHR misses 171system.l2c.demand_mshr_misses::total 404355 # number of demand (read+write) MSHR misses 172system.l2c.overall_mshr_misses::cpu.inst 15120 # number of overall MSHR misses 173system.l2c.overall_mshr_misses::cpu.data 389235 # number of overall MSHR misses 174system.l2c.overall_mshr_misses::total 404355 # number of overall MSHR misses 175system.l2c.ReadReq_mshr_miss_latency::cpu.inst 621011997 # number of ReadReq MSHR miss cycles 176system.l2c.ReadReq_mshr_miss_latency::cpu.data 10975832000 # number of ReadReq MSHR miss cycles 177system.l2c.ReadReq_mshr_miss_latency::total 11596843997 # number of ReadReq MSHR miss cycles 178system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2105000 # number of UpgradeReq MSHR miss cycles 179system.l2c.UpgradeReq_mshr_miss_latency::total 2105000 # number of UpgradeReq MSHR miss cycles 180system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 40000 # number of SCUpgradeReq MSHR miss cycles 181system.l2c.SCUpgradeReq_mshr_miss_latency::total 40000 # number of SCUpgradeReq MSHR miss cycles 182system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4797954496 # number of ReadExReq MSHR miss cycles 183system.l2c.ReadExReq_mshr_miss_latency::total 4797954496 # number of ReadExReq MSHR miss cycles 184system.l2c.demand_mshr_miss_latency::cpu.inst 621011997 # number of demand (read+write) MSHR miss cycles 185system.l2c.demand_mshr_miss_latency::cpu.data 15773786496 # number of demand (read+write) MSHR miss cycles 186system.l2c.demand_mshr_miss_latency::total 16394798493 # number of demand (read+write) MSHR miss cycles 187system.l2c.overall_mshr_miss_latency::cpu.inst 621011997 # number of overall MSHR miss cycles 188system.l2c.overall_mshr_miss_latency::cpu.data 15773786496 # number of overall MSHR miss cycles 189system.l2c.overall_mshr_miss_latency::total 16394798493 # number of overall MSHR miss cycles 190system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809342530 # number of ReadReq MSHR uncacheable cycles 191system.l2c.ReadReq_mshr_uncacheable_latency::total 809342530 # number of ReadReq MSHR uncacheable cycles 192system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1103231500 # number of WriteReq MSHR uncacheable cycles 193system.l2c.WriteReq_mshr_uncacheable_latency::total 1103231500 # number of WriteReq MSHR uncacheable cycles 194system.l2c.overall_mshr_uncacheable_latency::cpu.data 1912574030 # number of overall MSHR uncacheable cycles 195system.l2c.overall_mshr_uncacheable_latency::total 1912574030 # number of overall MSHR uncacheable cycles 196system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for ReadReq accesses 197system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248295 # mshr miss rate for ReadReq accesses 198system.l2c.ReadReq_mshr_miss_rate::total 0.135802 # mshr miss rate for ReadReq accesses 199system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.588235 # mshr miss rate for UpgradeReq accesses 200system.l2c.UpgradeReq_mshr_miss_rate::total 0.588235 # mshr miss rate for UpgradeReq accesses 201system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses 202system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses 203system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.382993 # mshr miss rate for ReadExReq accesses 204system.l2c.ReadExReq_mshr_miss_rate::total 0.382993 # mshr miss rate for ReadExReq accesses 205system.l2c.demand_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for demand accesses 206system.l2c.demand_mshr_miss_rate::cpu.data 0.277192 # mshr miss rate for demand accesses 207system.l2c.demand_mshr_miss_rate::total 0.166456 # mshr miss rate for demand accesses 208system.l2c.overall_mshr_miss_rate::cpu.inst 0.014751 # mshr miss rate for overall accesses 209system.l2c.overall_mshr_miss_rate::cpu.data 0.277192 # mshr miss rate for overall accesses 210system.l2c.overall_mshr_miss_rate::total 0.166456 # mshr miss rate for overall accesses 211system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41072.222024 # average ReadReq mshr miss latency 212system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40078.405311 # average ReadReq mshr miss latency 213system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.403929 # average ReadReq mshr miss latency 214system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42100 # average UpgradeReq mshr miss latency 215system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42100 # average UpgradeReq mshr miss latency 216system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 217system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 218system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.377340 # average ReadExReq mshr miss latency 219system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.377340 # average ReadExReq mshr miss latency 220system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41072.222024 # average overall mshr miss latency 221system.l2c.demand_avg_mshr_miss_latency::cpu.data 40525.097938 # average overall mshr miss latency 222system.l2c.demand_avg_mshr_miss_latency::total 40545.556486 # average overall mshr miss latency 223system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41072.222024 # average overall mshr miss latency 224system.l2c.overall_avg_mshr_miss_latency::cpu.data 40525.097938 # average overall mshr miss latency 225system.l2c.overall_avg_mshr_miss_latency::total 40545.556486 # average overall mshr miss latency |
| 214system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 215system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 216system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 217system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 218system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 219system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 220system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 221system.iocache.replacements 41685 # number of replacements | 226system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 227system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 228system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 229system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 230system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 231system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 232system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 233system.iocache.replacements 41685 # number of replacements |
| 222system.iocache.tagsinuse 1.294799 # Cycle average of tags in use | 234system.iocache.tagsinuse 1.287077 # Cycle average of tags in use |
| 223system.iocache.total_refs 0 # Total number of references to valid blocks. 224system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 225system.iocache.avg_refs 0 # Average number of references to valid blocks. | 235system.iocache.total_refs 0 # Total number of references to valid blocks. 236system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 237system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 226system.iocache.warmup_cycle 1711277767000 # Cycle when the warmup percentage was hit. 227system.iocache.occ_blocks::tsunami.ide 1.294799 # Average occupied blocks per requestor 228system.iocache.occ_percent::tsunami.ide 0.080925 # Average percentage of cache occupancy 229system.iocache.occ_percent::total 0.080925 # Average percentage of cache occupancy | 238system.iocache.warmup_cycle 1711278506000 # Cycle when the warmup percentage was hit. 239system.iocache.occ_blocks::tsunami.ide 1.287077 # Average occupied blocks per requestor 240system.iocache.occ_percent::tsunami.ide 0.080442 # Average percentage of cache occupancy 241system.iocache.occ_percent::total 0.080442 # Average percentage of cache occupancy |
| 230system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 231system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 232system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 233system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 234system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 235system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 236system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 237system.iocache.overall_misses::total 41725 # number of overall misses 238system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 239system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles | 242system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 243system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 244system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 245system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 246system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 247system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 248system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 249system.iocache.overall_misses::total 41725 # number of overall misses 250system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 251system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles |
| 240system.iocache.WriteReq_miss_latency::tsunami.ide 7641897806 # number of WriteReq miss cycles 241system.iocache.WriteReq_miss_latency::total 7641897806 # number of WriteReq miss cycles 242system.iocache.demand_miss_latency::tsunami.ide 7662570804 # number of demand (read+write) miss cycles 243system.iocache.demand_miss_latency::total 7662570804 # number of demand (read+write) miss cycles 244system.iocache.overall_miss_latency::tsunami.ide 7662570804 # number of overall miss cycles 245system.iocache.overall_miss_latency::total 7662570804 # number of overall miss cycles | 252system.iocache.WriteReq_miss_latency::tsunami.ide 7639838806 # number of WriteReq miss cycles 253system.iocache.WriteReq_miss_latency::total 7639838806 # number of WriteReq miss cycles 254system.iocache.demand_miss_latency::tsunami.ide 7660511804 # number of demand (read+write) miss cycles 255system.iocache.demand_miss_latency::total 7660511804 # number of demand (read+write) miss cycles 256system.iocache.overall_miss_latency::tsunami.ide 7660511804 # number of overall miss cycles 257system.iocache.overall_miss_latency::total 7660511804 # number of overall miss cycles |
| 246system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 247system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 248system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 249system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 250system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 251system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 252system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 253system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 254system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 255system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 256system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 257system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 258system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 259system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 260system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 261system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 262system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 263system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency | 258system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 259system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 260system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 261system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 262system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 263system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 264system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 265system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 266system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 267system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 268system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 269system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 270system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 271system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 272system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 273system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 274system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 275system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency |
| 264system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183911.672266 # average WriteReq miss latency 265system.iocache.WriteReq_avg_miss_latency::total 183911.672266 # average WriteReq miss latency 266system.iocache.demand_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency 267system.iocache.demand_avg_miss_latency::total 183644.596860 # average overall miss latency 268system.iocache.overall_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency 269system.iocache.overall_avg_miss_latency::total 183644.596860 # average overall miss latency 270system.iocache.blocked_cycles::no_mshrs 7656000 # number of cycles access was blocked | 276system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183862.119898 # average WriteReq miss latency 277system.iocache.WriteReq_avg_miss_latency::total 183862.119898 # average WriteReq miss latency 278system.iocache.demand_avg_miss_latency::tsunami.ide 183595.249946 # average overall miss latency 279system.iocache.demand_avg_miss_latency::total 183595.249946 # average overall miss latency 280system.iocache.overall_avg_miss_latency::tsunami.ide 183595.249946 # average overall miss latency 281system.iocache.overall_avg_miss_latency::total 183595.249946 # average overall miss latency 282system.iocache.blocked_cycles::no_mshrs 7420000 # number of cycles access was blocked |
| 271system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 283system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 272system.iocache.blocked::no_mshrs 7143 # number of cycles access was blocked | 284system.iocache.blocked::no_mshrs 7102 # number of cycles access was blocked |
| 273system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 285system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 274system.iocache.avg_blocked_cycles::no_mshrs 1071.818564 # average number of cycles each access was blocked | 286system.iocache.avg_blocked_cycles::no_mshrs 1044.776119 # average number of cycles each access was blocked |
| 275system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 276system.iocache.fast_writes 0 # number of fast writes performed 277system.iocache.cache_copies 0 # number of cache copies performed 278system.iocache.writebacks::writebacks 41512 # number of writebacks 279system.iocache.writebacks::total 41512 # number of writebacks 280system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 281system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 282system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 283system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 284system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 285system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 286system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 287system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 288system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 289system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles | 287system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 288system.iocache.fast_writes 0 # number of fast writes performed 289system.iocache.cache_copies 0 # number of cache copies performed 290system.iocache.writebacks::writebacks 41512 # number of writebacks 291system.iocache.writebacks::total 41512 # number of writebacks 292system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 293system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 294system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 295system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 296system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 297system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 298system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 299system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 300system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 301system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles |
| 290system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5481043992 # number of WriteReq MSHR miss cycles 291system.iocache.WriteReq_mshr_miss_latency::total 5481043992 # number of WriteReq MSHR miss cycles 292system.iocache.demand_mshr_miss_latency::tsunami.ide 5492719992 # number of demand (read+write) MSHR miss cycles 293system.iocache.demand_mshr_miss_latency::total 5492719992 # number of demand (read+write) MSHR miss cycles 294system.iocache.overall_mshr_miss_latency::tsunami.ide 5492719992 # number of overall MSHR miss cycles 295system.iocache.overall_mshr_miss_latency::total 5492719992 # number of overall MSHR miss cycles | 302system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5478984000 # number of WriteReq MSHR miss cycles 303system.iocache.WriteReq_mshr_miss_latency::total 5478984000 # number of WriteReq MSHR miss cycles 304system.iocache.demand_mshr_miss_latency::tsunami.ide 5490660000 # number of demand (read+write) MSHR miss cycles 305system.iocache.demand_mshr_miss_latency::total 5490660000 # number of demand (read+write) MSHR miss cycles 306system.iocache.overall_mshr_miss_latency::tsunami.ide 5490660000 # number of overall MSHR miss cycles 307system.iocache.overall_mshr_miss_latency::total 5490660000 # number of overall MSHR miss cycles |
| 296system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 297system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 298system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 299system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 300system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 301system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 302system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 303system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 304system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 305system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency | 308system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 309system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 310system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 311system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 312system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 313system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 314system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 315system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 316system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 317system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency |
| 306system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131908.066808 # average WriteReq mshr miss latency 307system.iocache.WriteReq_avg_mshr_miss_latency::total 131908.066808 # average WriteReq mshr miss latency 308system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency 309system.iocache.demand_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency 310system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency 311system.iocache.overall_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency | 318system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131858.490566 # average WriteReq mshr miss latency 319system.iocache.WriteReq_avg_mshr_miss_latency::total 131858.490566 # average WriteReq mshr miss latency 320system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131591.611744 # average overall mshr miss latency 321system.iocache.demand_avg_mshr_miss_latency::total 131591.611744 # average overall mshr miss latency 322system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131591.611744 # average overall mshr miss latency 323system.iocache.overall_avg_mshr_miss_latency::total 131591.611744 # average overall mshr miss latency |
| 312system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 313system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 314system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 315system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 316system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 317system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 318system.disk0.dma_write_txs 395 # Number of DMA write transactions. 319system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 320system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 321system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 322system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 323system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 324system.disk2.dma_write_txs 1 # Number of DMA write transactions. 325system.cpu.dtb.fetch_hits 0 # ITB hits 326system.cpu.dtb.fetch_misses 0 # ITB misses 327system.cpu.dtb.fetch_acv 0 # ITB acv 328system.cpu.dtb.fetch_accesses 0 # ITB accesses | 324system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 325system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 326system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 327system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 328system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 329system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 330system.disk0.dma_write_txs 395 # Number of DMA write transactions. 331system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 332system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 333system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 334system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 335system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 336system.disk2.dma_write_txs 1 # Number of DMA write transactions. 337system.cpu.dtb.fetch_hits 0 # ITB hits 338system.cpu.dtb.fetch_misses 0 # ITB misses 339system.cpu.dtb.fetch_acv 0 # ITB acv 340system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 329system.cpu.dtb.read_hits 9972402 # DTB read hits 330system.cpu.dtb.read_misses 43929 # DTB read misses 331system.cpu.dtb.read_acv 494 # DTB read access violations 332system.cpu.dtb.read_accesses 957886 # DTB read accesses 333system.cpu.dtb.write_hits 6649938 # DTB write hits 334system.cpu.dtb.write_misses 10071 # DTB write misses 335system.cpu.dtb.write_acv 391 # DTB write access violations 336system.cpu.dtb.write_accesses 340693 # DTB write accesses 337system.cpu.dtb.data_hits 16622340 # DTB hits 338system.cpu.dtb.data_misses 54000 # DTB misses 339system.cpu.dtb.data_acv 885 # DTB access violations 340system.cpu.dtb.data_accesses 1298579 # DTB accesses 341system.cpu.itb.fetch_hits 1343669 # ITB hits 342system.cpu.itb.fetch_misses 37345 # ITB misses 343system.cpu.itb.fetch_acv 1146 # ITB acv 344system.cpu.itb.fetch_accesses 1381014 # ITB accesses | 341system.cpu.dtb.read_hits 9968108 # DTB read hits 342system.cpu.dtb.read_misses 43556 # DTB read misses 343system.cpu.dtb.read_acv 496 # DTB read access violations 344system.cpu.dtb.read_accesses 957960 # DTB read accesses 345system.cpu.dtb.write_hits 6640476 # DTB write hits 346system.cpu.dtb.write_misses 10042 # DTB write misses 347system.cpu.dtb.write_acv 402 # DTB write access violations 348system.cpu.dtb.write_accesses 340316 # DTB write accesses 349system.cpu.dtb.data_hits 16608584 # DTB hits 350system.cpu.dtb.data_misses 53598 # DTB misses 351system.cpu.dtb.data_acv 898 # DTB access violations 352system.cpu.dtb.data_accesses 1298276 # DTB accesses 353system.cpu.itb.fetch_hits 1341124 # ITB hits 354system.cpu.itb.fetch_misses 40235 # ITB misses 355system.cpu.itb.fetch_acv 1160 # ITB acv 356system.cpu.itb.fetch_accesses 1381359 # ITB accesses |
| 345system.cpu.itb.read_hits 0 # DTB read hits 346system.cpu.itb.read_misses 0 # DTB read misses 347system.cpu.itb.read_acv 0 # DTB read access violations 348system.cpu.itb.read_accesses 0 # DTB read accesses 349system.cpu.itb.write_hits 0 # DTB write hits 350system.cpu.itb.write_misses 0 # DTB write misses 351system.cpu.itb.write_acv 0 # DTB write access violations 352system.cpu.itb.write_accesses 0 # DTB write accesses 353system.cpu.itb.data_hits 0 # DTB hits 354system.cpu.itb.data_misses 0 # DTB misses 355system.cpu.itb.data_acv 0 # DTB access violations 356system.cpu.itb.data_accesses 0 # DTB accesses | 357system.cpu.itb.read_hits 0 # DTB read hits 358system.cpu.itb.read_misses 0 # DTB read misses 359system.cpu.itb.read_acv 0 # DTB read access violations 360system.cpu.itb.read_accesses 0 # DTB read accesses 361system.cpu.itb.write_hits 0 # DTB write hits 362system.cpu.itb.write_misses 0 # DTB write misses 363system.cpu.itb.write_acv 0 # DTB write access violations 364system.cpu.itb.write_accesses 0 # DTB write accesses 365system.cpu.itb.data_hits 0 # DTB hits 366system.cpu.itb.data_misses 0 # DTB misses 367system.cpu.itb.data_acv 0 # DTB access violations 368system.cpu.itb.data_accesses 0 # DTB accesses |
| 357system.cpu.numCycles 122571263 # number of cpu cycles simulated | 369system.cpu.numCycles 122531860 # number of cpu cycles simulated |
| 358system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 359system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 370system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 371system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 360system.cpu.BPredUnit.lookups 14075987 # Number of BP lookups 361system.cpu.BPredUnit.condPredicted 11741614 # Number of conditional branches predicted 362system.cpu.BPredUnit.condIncorrect 452517 # Number of conditional branches incorrect 363system.cpu.BPredUnit.BTBLookups 10126525 # Number of BTB lookups 364system.cpu.BPredUnit.BTBHits 5926302 # Number of BTB hits | 372system.cpu.BPredUnit.lookups 14045558 # Number of BP lookups 373system.cpu.BPredUnit.condPredicted 11719354 # Number of conditional branches predicted 374system.cpu.BPredUnit.condIncorrect 447776 # Number of conditional branches incorrect 375system.cpu.BPredUnit.BTBLookups 10129156 # Number of BTB lookups 376system.cpu.BPredUnit.BTBHits 5920510 # Number of BTB hits |
| 365system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 377system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 366system.cpu.BPredUnit.usedRAS 942334 # Number of times the RAS was used to get a target. 367system.cpu.BPredUnit.RASInCorrect 45003 # Number of incorrect RAS predictions. 368system.cpu.fetch.icacheStallCycles 31564050 # Number of cycles fetch is stalled on an Icache miss 369system.cpu.fetch.Insts 71567580 # Number of instructions fetch has processed 370system.cpu.fetch.Branches 14075987 # Number of branches that fetch encountered 371system.cpu.fetch.predictedBranches 6868636 # Number of branches that fetch has predicted taken 372system.cpu.fetch.Cycles 13486844 # Number of cycles fetch has run and was not squashing or blocked 373system.cpu.fetch.SquashCycles 2151091 # Number of cycles fetch has spent squashing 374system.cpu.fetch.BlockedCycles 41804632 # Number of cycles fetch has spent blocked 375system.cpu.fetch.MiscStallCycles 33708 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 376system.cpu.fetch.PendingTrapStallCycles 276041 # Number of stall cycles due to pending traps 377system.cpu.fetch.PendingQuiesceStallCycles 314295 # Number of stall cycles due to pending quiesce instructions 378system.cpu.fetch.IcacheWaitRetryStallCycles 187 # Number of stall cycles due to full MSHR 379system.cpu.fetch.CacheLines 8859322 # Number of cache lines fetched 380system.cpu.fetch.IcacheSquashes 305645 # Number of outstanding Icache misses that were squashed 381system.cpu.fetch.rateDist::samples 88896899 # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::mean 0.805063 # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::stdev 2.137281 # Number of instructions fetched each cycle (Total) | 378system.cpu.BPredUnit.usedRAS 939631 # Number of times the RAS was used to get a target. 379system.cpu.BPredUnit.RASInCorrect 44501 # Number of incorrect RAS predictions. 380system.cpu.fetch.icacheStallCycles 31544288 # Number of cycles fetch is stalled on an Icache miss 381system.cpu.fetch.Insts 71453130 # Number of instructions fetch has processed 382system.cpu.fetch.Branches 14045558 # Number of branches that fetch encountered 383system.cpu.fetch.predictedBranches 6860141 # Number of branches that fetch has predicted taken 384system.cpu.fetch.Cycles 13465921 # Number of cycles fetch has run and was not squashing or blocked 385system.cpu.fetch.SquashCycles 2135846 # Number of cycles fetch has spent squashing 386system.cpu.fetch.BlockedCycles 41803348 # Number of cycles fetch has spent blocked 387system.cpu.fetch.MiscStallCycles 34171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 388system.cpu.fetch.PendingTrapStallCycles 276891 # Number of stall cycles due to pending traps 389system.cpu.fetch.PendingQuiesceStallCycles 309124 # Number of stall cycles due to pending quiesce instructions 390system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR 391system.cpu.fetch.CacheLines 8845261 # Number of cache lines fetched 392system.cpu.fetch.IcacheSquashes 302298 # Number of outstanding Icache misses that were squashed 393system.cpu.fetch.rateDist::samples 88840406 # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::mean 0.804286 # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::stdev 2.136255 # Number of instructions fetched each cycle (Total) |
| 384system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 396system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 385system.cpu.fetch.rateDist::0 75410055 84.83% 84.83% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::1 885656 1.00% 85.82% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::2 1762066 1.98% 87.81% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::3 856601 0.96% 88.77% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::4 2772547 3.12% 91.89% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::5 605003 0.68% 92.57% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::6 676052 0.76% 93.33% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::7 1014878 1.14% 94.47% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::8 4914041 5.53% 100.00% # Number of instructions fetched each cycle (Total) | 397system.cpu.fetch.rateDist::0 75374485 84.84% 84.84% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::1 882693 0.99% 85.84% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::2 1758870 1.98% 87.82% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::3 855110 0.96% 88.78% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::4 2773745 3.12% 91.90% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::5 603499 0.68% 92.58% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::6 673337 0.76% 93.34% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::7 1014466 1.14% 94.48% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::8 4904201 5.52% 100.00% # Number of instructions fetched each cycle (Total) |
| 394system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 397system.cpu.fetch.rateDist::total 88896899 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.branchRate 0.114839 # Number of branch fetches per cycle 399system.cpu.fetch.rate 0.583885 # Number of inst fetches per cycle 400system.cpu.decode.IdleCycles 32604567 # Number of cycles decode is idle 401system.cpu.decode.BlockedCycles 41610698 # Number of cycles decode is blocked 402system.cpu.decode.RunCycles 12250426 # Number of cycles decode is running 403system.cpu.decode.UnblockCycles 1057078 # Number of cycles decode is unblocking 404system.cpu.decode.SquashCycles 1374129 # Number of cycles decode is squashing 405system.cpu.decode.BranchResolved 617310 # Number of times decode resolved a branch 406system.cpu.decode.BranchMispred 43428 # Number of times decode detected a branch misprediction 407system.cpu.decode.DecodedInsts 70293890 # Number of instructions handled by decode 408system.cpu.decode.SquashedInsts 133239 # Number of squashed instructions handled by decode 409system.cpu.rename.SquashCycles 1374129 # Number of cycles rename is squashing 410system.cpu.rename.IdleCycles 33752767 # Number of cycles rename is idle 411system.cpu.rename.BlockCycles 16324711 # Number of cycles rename is blocking 412system.cpu.rename.serializeStallCycles 21058224 # count of cycles rename stalled for serializing inst 413system.cpu.rename.RunCycles 11548980 # Number of cycles rename is running 414system.cpu.rename.UnblockCycles 4838086 # Number of cycles rename is unblocking 415system.cpu.rename.RenamedInsts 66572257 # Number of instructions processed by rename 416system.cpu.rename.ROBFullEvents 7187 # Number of times rename has blocked due to ROB full 417system.cpu.rename.IQFullEvents 753146 # Number of times rename has blocked due to IQ full 418system.cpu.rename.LSQFullEvents 1801877 # Number of times rename has blocked due to LSQ full 419system.cpu.rename.RenamedOperands 44498273 # Number of destination operands rename has renamed 420system.cpu.rename.RenameLookups 80714962 # Number of register rename lookups that rename has made 421system.cpu.rename.int_rename_lookups 80226097 # Number of integer rename lookups 422system.cpu.rename.fp_rename_lookups 488865 # Number of floating rename lookups 423system.cpu.rename.CommittedMaps 38261328 # Number of HB maps that are committed 424system.cpu.rename.UndoneMaps 6236937 # Number of HB maps that are undone due to squashing 425system.cpu.rename.serializingInsts 1703640 # count of serializing insts renamed 426system.cpu.rename.tempSerializingInsts 251709 # count of temporary serializing insts renamed 427system.cpu.rename.skidInsts 12757763 # count of insts added to the skid buffer 428system.cpu.memDep0.insertedLoads 10570492 # Number of loads inserted to the mem dependence unit. 429system.cpu.memDep0.insertedStores 6981683 # Number of stores inserted to the mem dependence unit. 430system.cpu.memDep0.conflictingLoads 1316603 # Number of conflicting loads. 431system.cpu.memDep0.conflictingStores 922104 # Number of conflicting stores. 432system.cpu.iq.iqInstsAdded 58981346 # Number of instructions added to the IQ (excludes non-spec) 433system.cpu.iq.iqNonSpecInstsAdded 2097651 # Number of non-speculative instructions added to the IQ 434system.cpu.iq.iqInstsIssued 57326676 # Number of instructions issued 435system.cpu.iq.iqSquashedInstsIssued 120953 # Number of squashed instructions issued 436system.cpu.iq.iqSquashedInstsExamined 7579711 # Number of squashed instructions iterated over during squash; mainly for profiling 437system.cpu.iq.iqSquashedOperandsExamined 3887654 # Number of squashed operands that are examined and possibly removed from graph 438system.cpu.iq.iqSquashedNonSpecRemoved 1429592 # Number of squashed non-spec instructions that were removed 439system.cpu.iq.issued_per_cycle::samples 88896899 # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::mean 0.644867 # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::stdev 1.291957 # Number of insts issued each cycle | 409system.cpu.fetch.rateDist::total 88840406 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.branchRate 0.114628 # Number of branch fetches per cycle 411system.cpu.fetch.rate 0.583139 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 32595578 # Number of cycles decode is idle 413system.cpu.decode.BlockedCycles 41593167 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 12233698 # Number of cycles decode is running 415system.cpu.decode.UnblockCycles 1054489 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 1363473 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 614789 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 43441 # Number of times decode detected a branch misprediction 419system.cpu.decode.DecodedInsts 70185288 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 133206 # Number of squashed instructions handled by decode 421system.cpu.rename.SquashCycles 1363473 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 33740803 # Number of cycles rename is idle 423system.cpu.rename.BlockCycles 16340010 # Number of cycles rename is blocking 424system.cpu.rename.serializeStallCycles 21029757 # count of cycles rename stalled for serializing inst 425system.cpu.rename.RunCycles 11532133 # Number of cycles rename is running 426system.cpu.rename.UnblockCycles 4834228 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 66486071 # Number of instructions processed by rename 428system.cpu.rename.ROBFullEvents 7165 # Number of times rename has blocked due to ROB full 429system.cpu.rename.IQFullEvents 750706 # Number of times rename has blocked due to IQ full 430system.cpu.rename.LSQFullEvents 1800875 # Number of times rename has blocked due to LSQ full 431system.cpu.rename.RenamedOperands 44431145 # Number of destination operands rename has renamed 432system.cpu.rename.RenameLookups 80611615 # Number of register rename lookups that rename has made 433system.cpu.rename.int_rename_lookups 80123142 # Number of integer rename lookups 434system.cpu.rename.fp_rename_lookups 488473 # Number of floating rename lookups 435system.cpu.rename.CommittedMaps 38259358 # Number of HB maps that are committed 436system.cpu.rename.UndoneMaps 6171779 # Number of HB maps that are undone due to squashing 437system.cpu.rename.serializingInsts 1702958 # count of serializing insts renamed 438system.cpu.rename.tempSerializingInsts 251555 # count of temporary serializing insts renamed 439system.cpu.rename.skidInsts 12743501 # count of insts added to the skid buffer 440system.cpu.memDep0.insertedLoads 10564267 # Number of loads inserted to the mem dependence unit. 441system.cpu.memDep0.insertedStores 6974375 # Number of stores inserted to the mem dependence unit. 442system.cpu.memDep0.conflictingLoads 1310956 # Number of conflicting loads. 443system.cpu.memDep0.conflictingStores 921637 # Number of conflicting stores. 444system.cpu.iq.iqInstsAdded 58920823 # Number of instructions added to the IQ (excludes non-spec) 445system.cpu.iq.iqNonSpecInstsAdded 2093860 # Number of non-speculative instructions added to the IQ 446system.cpu.iq.iqInstsIssued 57272597 # Number of instructions issued 447system.cpu.iq.iqSquashedInstsIssued 128544 # Number of squashed instructions issued 448system.cpu.iq.iqSquashedInstsExamined 7527772 # Number of squashed instructions iterated over during squash; mainly for profiling 449system.cpu.iq.iqSquashedOperandsExamined 3875760 # Number of squashed operands that are examined and possibly removed from graph 450system.cpu.iq.iqSquashedNonSpecRemoved 1425872 # Number of squashed non-spec instructions that were removed 451system.cpu.iq.issued_per_cycle::samples 88840406 # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::mean 0.644668 # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::stdev 1.291770 # Number of insts issued each cycle |
| 442system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 454system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 443system.cpu.iq.issued_per_cycle::0 62967728 70.83% 70.83% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::1 12048856 13.55% 84.39% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::2 5390899 6.06% 90.45% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::3 3449544 3.88% 94.33% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::4 2613461 2.94% 97.27% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::5 1329807 1.50% 98.77% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::6 686975 0.77% 99.54% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::7 354371 0.40% 99.94% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::8 55258 0.06% 100.00% # Number of insts issued each cycle | 455system.cpu.iq.issued_per_cycle::0 62934632 70.84% 70.84% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::1 12040664 13.55% 84.39% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::2 5383860 6.06% 90.45% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::3 3443587 3.88% 94.33% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::4 2613267 2.94% 97.27% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::5 1328836 1.50% 98.77% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::6 686879 0.77% 99.54% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::7 354518 0.40% 99.94% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::8 54163 0.06% 100.00% # Number of insts issued each cycle |
| 452system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 464system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 455system.cpu.iq.issued_per_cycle::total 88896899 # Number of insts issued each cycle | 467system.cpu.iq.issued_per_cycle::total 88840406 # Number of insts issued each cycle |
| 456system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 468system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 457system.cpu.iq.fu_full::IntAlu 75491 10.00% 10.00% # attempts to use FU when none available 458system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available 459system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available 460system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available 461system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available 462system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available 463system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available 464system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available 486system.cpu.iq.fu_full::MemRead 363771 48.19% 58.19% # attempts to use FU when none available 487system.cpu.iq.fu_full::MemWrite 315594 41.81% 100.00% # attempts to use FU when none available | 469system.cpu.iq.fu_full::IntAlu 73519 9.73% 9.73% # attempts to use FU when none available 470system.cpu.iq.fu_full::IntMult 0 0.00% 9.73% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntDiv 0 0.00% 9.73% # attempts to use FU when none available 472system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.73% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.73% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.73% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatMult 0 0.00% 9.73% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.73% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.73% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.73% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.73% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.73% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.73% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.73% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.73% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdMult 0 0.00% 9.73% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.73% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdShift 0 0.00% 9.73% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.73% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.73% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.73% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.73% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.73% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.73% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.73% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.73% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.73% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.73% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.73% # attempts to use FU when none available 498system.cpu.iq.fu_full::MemRead 364094 48.19% 57.91% # attempts to use FU when none available 499system.cpu.iq.fu_full::MemWrite 318003 42.09% 100.00% # attempts to use FU when none available |
| 488system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 489system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 490system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued | 500system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 501system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 502system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued |
| 491system.cpu.iq.FU_type_0::IntAlu 39127581 68.25% 68.27% # Type of FU issued 492system.cpu.iq.FU_type_0::IntMult 61956 0.11% 68.37% # Type of FU issued 493system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.37% # Type of FU issued | 503system.cpu.iq.FU_type_0::IntAlu 39090989 68.25% 68.27% # Type of FU issued 504system.cpu.iq.FU_type_0::IntMult 61973 0.11% 68.38% # Type of FU issued 505system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.38% # Type of FU issued |
| 494system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued 495system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued 496system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued 497system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued 498system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.43% # Type of FU issued 499system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 512system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued | 506system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued 507system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.43% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 524system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued |
| 520system.cpu.iq.FU_type_0::MemRead 10418296 18.17% 86.60% # Type of FU issued 521system.cpu.iq.FU_type_0::MemWrite 6729507 11.74% 98.34% # Type of FU issued 522system.cpu.iq.FU_type_0::IprAccess 952802 1.66% 100.00% # Type of FU issued | 532system.cpu.iq.FU_type_0::MemRead 10411715 18.18% 86.61% # Type of FU issued 533system.cpu.iq.FU_type_0::MemWrite 6718707 11.73% 98.34% # Type of FU issued 534system.cpu.iq.FU_type_0::IprAccess 952679 1.66% 100.00% # Type of FU issued |
| 523system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 535system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 524system.cpu.iq.FU_type_0::total 57326676 # Type of FU issued 525system.cpu.iq.rate 0.467701 # Inst issue rate 526system.cpu.iq.fu_busy_cnt 754856 # FU busy when requested 527system.cpu.iq.fu_busy_rate 0.013168 # FU busy rate (busy events/executed inst) 528system.cpu.iq.int_inst_queue_reads 203729346 # Number of integer instruction queue reads 529system.cpu.iq.int_inst_queue_writes 68333375 # Number of integer instruction queue writes 530system.cpu.iq.int_inst_queue_wakeup_accesses 56036726 # Number of integer instruction queue wakeup accesses 531system.cpu.iq.fp_inst_queue_reads 696713 # Number of floating instruction queue reads 532system.cpu.iq.fp_inst_queue_writes 339202 # Number of floating instruction queue writes 533system.cpu.iq.fp_inst_queue_wakeup_accesses 327718 # Number of floating instruction queue wakeup accesses 534system.cpu.iq.int_alu_accesses 57709702 # Number of integer alu accesses 535system.cpu.iq.fp_alu_accesses 364539 # Number of floating point alu accesses 536system.cpu.iew.lsq.thread0.forwLoads 594776 # Number of loads that had data forwarded from stores | 536system.cpu.iq.FU_type_0::total 57272597 # Type of FU issued 537system.cpu.iq.rate 0.467410 # Inst issue rate 538system.cpu.iq.fu_busy_cnt 755616 # FU busy when requested 539system.cpu.iq.fu_busy_rate 0.013193 # FU busy rate (busy events/executed inst) 540system.cpu.iq.int_inst_queue_reads 203573547 # Number of integer instruction queue reads 541system.cpu.iq.int_inst_queue_writes 68217667 # Number of integer instruction queue writes 542system.cpu.iq.int_inst_queue_wakeup_accesses 55990659 # Number of integer instruction queue wakeup accesses 543system.cpu.iq.fp_inst_queue_reads 696212 # Number of floating instruction queue reads 544system.cpu.iq.fp_inst_queue_writes 338599 # Number of floating instruction queue writes 545system.cpu.iq.fp_inst_queue_wakeup_accesses 327577 # Number of floating instruction queue wakeup accesses 546system.cpu.iq.int_alu_accesses 57656594 # Number of integer alu accesses 547system.cpu.iq.fp_alu_accesses 364328 # Number of floating point alu accesses 548system.cpu.iew.lsq.thread0.forwLoads 594908 # Number of loads that had data forwarded from stores |
| 537system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 549system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 538system.cpu.iew.lsq.thread0.squashedLoads 1456655 # Number of loads squashed 539system.cpu.iew.lsq.thread0.ignoredResponses 2870 # Number of memory responses ignored because the instruction is squashed 540system.cpu.iew.lsq.thread0.memOrderViolation 14252 # Number of memory ordering violations 541system.cpu.iew.lsq.thread0.squashedStores 588832 # Number of stores squashed | 550system.cpu.iew.lsq.thread0.squashedLoads 1450991 # Number of loads squashed 551system.cpu.iew.lsq.thread0.ignoredResponses 2769 # Number of memory responses ignored because the instruction is squashed 552system.cpu.iew.lsq.thread0.memOrderViolation 14176 # Number of memory ordering violations 553system.cpu.iew.lsq.thread0.squashedStores 581838 # Number of stores squashed |
| 542system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 543system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 554system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 555system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 544system.cpu.iew.lsq.thread0.rescheduledLoads 18348 # Number of loads that were rescheduled 545system.cpu.iew.lsq.thread0.cacheBlocked 104302 # Number of times an access to memory failed due to the cache being blocked | 556system.cpu.iew.lsq.thread0.rescheduledLoads 18337 # Number of loads that were rescheduled 557system.cpu.iew.lsq.thread0.cacheBlocked 105015 # Number of times an access to memory failed due to the cache being blocked |
| 546system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 558system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 547system.cpu.iew.iewSquashCycles 1374129 # Number of cycles IEW is squashing 548system.cpu.iew.iewBlockCycles 11393417 # Number of cycles IEW is blocking 549system.cpu.iew.iewUnblockCycles 869281 # Number of cycles IEW is unblocking 550system.cpu.iew.iewDispatchedInsts 64652535 # Number of instructions dispatched to IQ 551system.cpu.iew.iewDispSquashedInsts 684492 # Number of squashed instructions skipped by dispatch 552system.cpu.iew.iewDispLoadInsts 10570492 # Number of dispatched load instructions 553system.cpu.iew.iewDispStoreInsts 6981683 # Number of dispatched store instructions 554system.cpu.iew.iewDispNonSpecInsts 1845589 # Number of dispatched non-speculative instructions 555system.cpu.iew.iewIQFullEvents 621506 # Number of times the IQ has become full, causing a stall 556system.cpu.iew.iewLSQFullEvents 12714 # Number of times the LSQ has become full, causing a stall 557system.cpu.iew.memOrderViolationEvents 14252 # Number of memory order violations 558system.cpu.iew.predictedTakenIncorrect 241539 # Number of branches that were predicted taken incorrectly 559system.cpu.iew.predictedNotTakenIncorrect 423865 # Number of branches that were predicted not taken incorrectly 560system.cpu.iew.branchMispredicts 665404 # Number of branch mispredicts detected at execute 561system.cpu.iew.iewExecutedInsts 56791406 # Number of executed instructions 562system.cpu.iew.iewExecLoadInsts 10044983 # Number of load instructions executed 563system.cpu.iew.iewExecSquashedInsts 535269 # Number of squashed instructions skipped in execute | 559system.cpu.iew.iewSquashCycles 1363473 # Number of cycles IEW is squashing 560system.cpu.iew.iewBlockCycles 11404151 # Number of cycles IEW is blocking 561system.cpu.iew.iewUnblockCycles 871964 # Number of cycles IEW is unblocking 562system.cpu.iew.iewDispatchedInsts 64586243 # Number of instructions dispatched to IQ 563system.cpu.iew.iewDispSquashedInsts 684405 # Number of squashed instructions skipped by dispatch 564system.cpu.iew.iewDispLoadInsts 10564267 # Number of dispatched load instructions 565system.cpu.iew.iewDispStoreInsts 6974375 # Number of dispatched store instructions 566system.cpu.iew.iewDispNonSpecInsts 1841535 # Number of dispatched non-speculative instructions 567system.cpu.iew.iewIQFullEvents 624319 # Number of times the IQ has become full, causing a stall 568system.cpu.iew.iewLSQFullEvents 12765 # Number of times the LSQ has become full, causing a stall 569system.cpu.iew.memOrderViolationEvents 14176 # Number of memory order violations 570system.cpu.iew.predictedTakenIncorrect 237440 # Number of branches that were predicted taken incorrectly 571system.cpu.iew.predictedNotTakenIncorrect 422569 # Number of branches that were predicted not taken incorrectly 572system.cpu.iew.branchMispredicts 660009 # Number of branch mispredicts detected at execute 573system.cpu.iew.iewExecutedInsts 56745623 # Number of executed instructions 574system.cpu.iew.iewExecLoadInsts 10040371 # Number of load instructions executed 575system.cpu.iew.iewExecSquashedInsts 526973 # Number of squashed instructions skipped in execute |
| 564system.cpu.iew.exec_swp 0 # number of swp insts executed | 576system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 565system.cpu.iew.exec_nop 3573538 # number of nop insts executed 566system.cpu.iew.exec_refs 16720258 # number of memory reference insts executed 567system.cpu.iew.exec_branches 9005988 # Number of branches executed 568system.cpu.iew.exec_stores 6675275 # Number of stores executed 569system.cpu.iew.exec_rate 0.463334 # Inst execution rate 570system.cpu.iew.wb_sent 56476627 # cumulative count of insts sent to commit 571system.cpu.iew.wb_count 56364444 # cumulative count of insts written-back 572system.cpu.iew.wb_producers 27797872 # num instructions producing a value 573system.cpu.iew.wb_consumers 37663953 # num instructions consuming a value | 577system.cpu.iew.exec_nop 3571560 # number of nop insts executed 578system.cpu.iew.exec_refs 16706164 # number of memory reference insts executed 579system.cpu.iew.exec_branches 8999941 # Number of branches executed 580system.cpu.iew.exec_stores 6665793 # Number of stores executed 581system.cpu.iew.exec_rate 0.463109 # Inst execution rate 582system.cpu.iew.wb_sent 56430087 # cumulative count of insts sent to commit 583system.cpu.iew.wb_count 56318236 # cumulative count of insts written-back 584system.cpu.iew.wb_producers 27772479 # num instructions producing a value 585system.cpu.iew.wb_consumers 37631426 # num instructions consuming a value |
| 574system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 586system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 575system.cpu.iew.wb_rate 0.459850 # insts written-back per cycle 576system.cpu.iew.wb_fanout 0.738050 # average fanout of values written-back | 587system.cpu.iew.wb_rate 0.459621 # insts written-back per cycle 588system.cpu.iew.wb_fanout 0.738013 # average fanout of values written-back |
| 577system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 589system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 578system.cpu.commit.commitCommittedInsts 56288834 # The number of committed instructions 579system.cpu.commit.commitCommittedOps 56288834 # The number of committed instructions 580system.cpu.commit.commitSquashedInsts 8251602 # The number of squashed insts skipped by commit 581system.cpu.commit.commitNonSpecStalls 668059 # The number of times commit has been forced to stall to communicate backwards 582system.cpu.commit.branchMispredicts 621198 # The number of times a branch was mispredicted 583system.cpu.commit.committed_per_cycle::samples 87522770 # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::mean 0.643134 # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::stdev 1.558246 # Number of insts commited each cycle | 590system.cpu.commit.commitCommittedInsts 56285915 # The number of committed instructions 591system.cpu.commit.commitCommittedOps 56285915 # The number of committed instructions 592system.cpu.commit.commitSquashedInsts 8189376 # The number of squashed insts skipped by commit 593system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards 594system.cpu.commit.branchMispredicts 616441 # The number of times a branch was mispredicted 595system.cpu.commit.committed_per_cycle::samples 87476933 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 0.643437 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 1.558745 # Number of insts commited each cycle |
| 586system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 587system.cpu.commit.committed_per_cycle::0 66254825 75.70% 75.70% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::1 8962066 10.24% 85.94% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::2 4828588 5.52% 91.46% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::3 2603942 2.98% 94.43% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::4 1449491 1.66% 96.09% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::5 603705 0.69% 96.78% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::6 515511 0.59% 97.37% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::7 488925 0.56% 97.93% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::8 1815717 2.07% 100.00% # Number of insts commited each cycle | 599system.cpu.commit.committed_per_cycle::0 66214375 75.69% 75.69% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 8956758 10.24% 85.93% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 4831410 5.52% 91.46% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 2600718 2.97% 94.43% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 1447358 1.65% 96.08% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 605400 0.69% 96.78% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 515608 0.59% 97.36% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 488345 0.56% 97.92% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 1816961 2.08% 100.00% # Number of insts commited each cycle |
| 596system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 599system.cpu.commit.committed_per_cycle::total 87522770 # Number of insts commited each cycle 600system.cpu.commit.committedInsts 56288834 # Number of instructions committed 601system.cpu.commit.committedOps 56288834 # Number of ops (including micro ops) committed | 611system.cpu.commit.committed_per_cycle::total 87476933 # Number of insts commited each cycle 612system.cpu.commit.committedInsts 56285915 # Number of instructions committed 613system.cpu.commit.committedOps 56285915 # Number of ops (including micro ops) committed |
| 602system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 603system.cpu.commit.refs 15506688 # Number of memory references committed 604system.cpu.commit.loads 9113837 # Number of loads committed 605system.cpu.commit.membars 227975 # Number of memory barriers committed 606system.cpu.commit.branches 8463674 # Number of branches committed | 615system.cpu.commit.refs 15505813 # Number of memory references committed 616system.cpu.commit.loads 9113276 # Number of loads committed 617system.cpu.commit.membars 227944 # Number of memory barriers committed 618system.cpu.commit.branches 8463135 # Number of branches committed |
| 607system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 619system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 608system.cpu.commit.int_insts 52126817 # Number of committed integer instructions. 609system.cpu.commit.function_calls 744625 # Number of function calls committed. 610system.cpu.commit.bw_lim_events 1815717 # number cycles where commit BW limit reached | 620system.cpu.commit.int_insts 52124087 # Number of committed integer instructions. 621system.cpu.commit.function_calls 744545 # Number of function calls committed. 622system.cpu.commit.bw_lim_events 1816961 # number cycles where commit BW limit reached |
| 611system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 623system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 612system.cpu.rob.rob_reads 149996318 # The number of ROB reads 613system.cpu.rob.rob_writes 130455868 # The number of ROB writes 614system.cpu.timesIdled 1387986 # Number of times that the entire CPU went into an idle state and unscheduled itself 615system.cpu.idleCycles 33674364 # Total number of cycles that the CPU has spent unscheduled due to idling 616system.cpu.quiesceCycles 3608226532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 617system.cpu.committedInsts 53094243 # Number of Instructions Simulated 618system.cpu.committedOps 53094243 # Number of Ops (including micro ops) Simulated 619system.cpu.committedInsts_total 53094243 # Number of Instructions Simulated 620system.cpu.cpi 2.308560 # CPI: Cycles Per Instruction 621system.cpu.cpi_total 2.308560 # CPI: Total CPI of All Threads 622system.cpu.ipc 0.433170 # IPC: Instructions Per Cycle 623system.cpu.ipc_total 0.433170 # IPC: Total IPC of All Threads 624system.cpu.int_regfile_reads 74446052 # number of integer regfile reads 625system.cpu.int_regfile_writes 40661007 # number of integer regfile writes 626system.cpu.fp_regfile_reads 166346 # number of floating regfile reads 627system.cpu.fp_regfile_writes 166939 # number of floating regfile writes 628system.cpu.misc_regfile_reads 1998850 # number of misc regfile reads 629system.cpu.misc_regfile_writes 950370 # number of misc regfile writes | 624system.cpu.rob.rob_reads 149884134 # The number of ROB reads 625system.cpu.rob.rob_writes 130314855 # The number of ROB writes 626system.cpu.timesIdled 1389359 # Number of times that the entire CPU went into an idle state and unscheduled itself 627system.cpu.idleCycles 33691454 # Total number of cycles that the CPU has spent unscheduled due to idling 628system.cpu.quiesceCycles 3606309626 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 629system.cpu.committedInsts 53091408 # Number of Instructions Simulated 630system.cpu.committedOps 53091408 # Number of Ops (including micro ops) Simulated 631system.cpu.committedInsts_total 53091408 # Number of Instructions Simulated 632system.cpu.cpi 2.307941 # CPI: Cycles Per Instruction 633system.cpu.cpi_total 2.307941 # CPI: Total CPI of All Threads 634system.cpu.ipc 0.433287 # IPC: Instructions Per Cycle 635system.cpu.ipc_total 0.433287 # IPC: Total IPC of All Threads 636system.cpu.int_regfile_reads 74386687 # number of integer regfile reads 637system.cpu.int_regfile_writes 40627933 # number of integer regfile writes 638system.cpu.fp_regfile_reads 166209 # number of floating regfile reads 639system.cpu.fp_regfile_writes 166935 # number of floating regfile writes 640system.cpu.misc_regfile_reads 1998011 # number of misc regfile reads 641system.cpu.misc_regfile_writes 950291 # number of misc regfile writes |
| 630system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 631system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 632system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 633system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 634system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 635system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 636system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 637system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 653system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 654system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 655system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 656system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 657system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 658system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 659system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 660system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 642system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 643system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 644system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 645system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 646system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 647system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 648system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 649system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 665system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 666system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 667system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 668system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 669system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 670system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 671system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 672system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 661system.cpu.icache.replacements 1025209 # number of replacements 662system.cpu.icache.tagsinuse 509.960172 # Cycle average of tags in use 663system.cpu.icache.total_refs 7772148 # Total number of references to valid blocks. 664system.cpu.icache.sampled_refs 1025718 # Sample count of references to valid blocks. 665system.cpu.icache.avg_refs 7.577276 # Average number of references to valid blocks. | 673system.cpu.icache.replacements 1024388 # number of replacements 674system.cpu.icache.tagsinuse 509.959478 # Cycle average of tags in use 675system.cpu.icache.total_refs 7759501 # Total number of references to valid blocks. 676system.cpu.icache.sampled_refs 1024896 # Sample count of references to valid blocks. 677system.cpu.icache.avg_refs 7.571013 # Average number of references to valid blocks. |
| 666system.cpu.icache.warmup_cycle 23722278000 # Cycle when the warmup percentage was hit. | 678system.cpu.icache.warmup_cycle 23722278000 # Cycle when the warmup percentage was hit. |
| 667system.cpu.icache.occ_blocks::cpu.inst 509.960172 # Average occupied blocks per requestor 668system.cpu.icache.occ_percent::cpu.inst 0.996016 # Average percentage of cache occupancy 669system.cpu.icache.occ_percent::total 0.996016 # Average percentage of cache occupancy 670system.cpu.icache.ReadReq_hits::cpu.inst 7772149 # number of ReadReq hits 671system.cpu.icache.ReadReq_hits::total 7772149 # number of ReadReq hits 672system.cpu.icache.demand_hits::cpu.inst 7772149 # number of demand (read+write) hits 673system.cpu.icache.demand_hits::total 7772149 # number of demand (read+write) hits 674system.cpu.icache.overall_hits::cpu.inst 7772149 # number of overall hits 675system.cpu.icache.overall_hits::total 7772149 # number of overall hits 676system.cpu.icache.ReadReq_misses::cpu.inst 1087170 # number of ReadReq misses 677system.cpu.icache.ReadReq_misses::total 1087170 # number of ReadReq misses 678system.cpu.icache.demand_misses::cpu.inst 1087170 # number of demand (read+write) misses 679system.cpu.icache.demand_misses::total 1087170 # number of demand (read+write) misses 680system.cpu.icache.overall_misses::cpu.inst 1087170 # number of overall misses 681system.cpu.icache.overall_misses::total 1087170 # number of overall misses 682system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528418489 # number of ReadReq miss cycles 683system.cpu.icache.ReadReq_miss_latency::total 17528418489 # number of ReadReq miss cycles 684system.cpu.icache.demand_miss_latency::cpu.inst 17528418489 # number of demand (read+write) miss cycles 685system.cpu.icache.demand_miss_latency::total 17528418489 # number of demand (read+write) miss cycles 686system.cpu.icache.overall_miss_latency::cpu.inst 17528418489 # number of overall miss cycles 687system.cpu.icache.overall_miss_latency::total 17528418489 # number of overall miss cycles 688system.cpu.icache.ReadReq_accesses::cpu.inst 8859319 # number of ReadReq accesses(hits+misses) 689system.cpu.icache.ReadReq_accesses::total 8859319 # number of ReadReq accesses(hits+misses) 690system.cpu.icache.demand_accesses::cpu.inst 8859319 # number of demand (read+write) accesses 691system.cpu.icache.demand_accesses::total 8859319 # number of demand (read+write) accesses 692system.cpu.icache.overall_accesses::cpu.inst 8859319 # number of overall (read+write) accesses 693system.cpu.icache.overall_accesses::total 8859319 # number of overall (read+write) accesses 694system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122715 # miss rate for ReadReq accesses 695system.cpu.icache.ReadReq_miss_rate::total 0.122715 # miss rate for ReadReq accesses 696system.cpu.icache.demand_miss_rate::cpu.inst 0.122715 # miss rate for demand accesses 697system.cpu.icache.demand_miss_rate::total 0.122715 # miss rate for demand accesses 698system.cpu.icache.overall_miss_rate::cpu.inst 0.122715 # miss rate for overall accesses 699system.cpu.icache.overall_miss_rate::total 0.122715 # miss rate for overall accesses 700system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16122.978457 # average ReadReq miss latency 701system.cpu.icache.ReadReq_avg_miss_latency::total 16122.978457 # average ReadReq miss latency 702system.cpu.icache.demand_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency 703system.cpu.icache.demand_avg_miss_latency::total 16122.978457 # average overall miss latency 704system.cpu.icache.overall_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency 705system.cpu.icache.overall_avg_miss_latency::total 16122.978457 # average overall miss latency 706system.cpu.icache.blocked_cycles::no_mshrs 1581994 # number of cycles access was blocked | 679system.cpu.icache.occ_blocks::cpu.inst 509.959478 # Average occupied blocks per requestor 680system.cpu.icache.occ_percent::cpu.inst 0.996015 # Average percentage of cache occupancy 681system.cpu.icache.occ_percent::total 0.996015 # Average percentage of cache occupancy 682system.cpu.icache.ReadReq_hits::cpu.inst 7759502 # number of ReadReq hits 683system.cpu.icache.ReadReq_hits::total 7759502 # number of ReadReq hits 684system.cpu.icache.demand_hits::cpu.inst 7759502 # number of demand (read+write) hits 685system.cpu.icache.demand_hits::total 7759502 # number of demand (read+write) hits 686system.cpu.icache.overall_hits::cpu.inst 7759502 # number of overall hits 687system.cpu.icache.overall_hits::total 7759502 # number of overall hits 688system.cpu.icache.ReadReq_misses::cpu.inst 1085755 # number of ReadReq misses 689system.cpu.icache.ReadReq_misses::total 1085755 # number of ReadReq misses 690system.cpu.icache.demand_misses::cpu.inst 1085755 # number of demand (read+write) misses 691system.cpu.icache.demand_misses::total 1085755 # number of demand (read+write) misses 692system.cpu.icache.overall_misses::cpu.inst 1085755 # number of overall misses 693system.cpu.icache.overall_misses::total 1085755 # number of overall misses 694system.cpu.icache.ReadReq_miss_latency::cpu.inst 17501015990 # number of ReadReq miss cycles 695system.cpu.icache.ReadReq_miss_latency::total 17501015990 # number of ReadReq miss cycles 696system.cpu.icache.demand_miss_latency::cpu.inst 17501015990 # number of demand (read+write) miss cycles 697system.cpu.icache.demand_miss_latency::total 17501015990 # number of demand (read+write) miss cycles 698system.cpu.icache.overall_miss_latency::cpu.inst 17501015990 # number of overall miss cycles 699system.cpu.icache.overall_miss_latency::total 17501015990 # number of overall miss cycles 700system.cpu.icache.ReadReq_accesses::cpu.inst 8845257 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.ReadReq_accesses::total 8845257 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.demand_accesses::cpu.inst 8845257 # number of demand (read+write) accesses 703system.cpu.icache.demand_accesses::total 8845257 # number of demand (read+write) accesses 704system.cpu.icache.overall_accesses::cpu.inst 8845257 # number of overall (read+write) accesses 705system.cpu.icache.overall_accesses::total 8845257 # number of overall (read+write) accesses 706system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122750 # miss rate for ReadReq accesses 707system.cpu.icache.ReadReq_miss_rate::total 0.122750 # miss rate for ReadReq accesses 708system.cpu.icache.demand_miss_rate::cpu.inst 0.122750 # miss rate for demand accesses 709system.cpu.icache.demand_miss_rate::total 0.122750 # miss rate for demand accesses 710system.cpu.icache.overall_miss_rate::cpu.inst 0.122750 # miss rate for overall accesses 711system.cpu.icache.overall_miss_rate::total 0.122750 # miss rate for overall accesses 712system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16118.752380 # average ReadReq miss latency 713system.cpu.icache.ReadReq_avg_miss_latency::total 16118.752380 # average ReadReq miss latency 714system.cpu.icache.demand_avg_miss_latency::cpu.inst 16118.752380 # average overall miss latency 715system.cpu.icache.demand_avg_miss_latency::total 16118.752380 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::cpu.inst 16118.752380 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::total 16118.752380 # average overall miss latency 718system.cpu.icache.blocked_cycles::no_mshrs 1777494 # number of cycles access was blocked |
| 707system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 719system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 708system.cpu.icache.blocked::no_mshrs 196 # number of cycles access was blocked | 720system.cpu.icache.blocked::no_mshrs 208 # number of cycles access was blocked |
| 709system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 721system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 710system.cpu.icache.avg_blocked_cycles::no_mshrs 8071.397959 # average number of cycles each access was blocked | 722system.cpu.icache.avg_blocked_cycles::no_mshrs 8545.644231 # average number of cycles each access was blocked |
| 711system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu.icache.fast_writes 0 # number of fast writes performed 713system.cpu.icache.cache_copies 0 # number of cache copies performed | 723system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu.icache.fast_writes 0 # number of fast writes performed 725system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 714system.cpu.icache.writebacks::writebacks 238 # number of writebacks 715system.cpu.icache.writebacks::total 238 # number of writebacks 716system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61204 # number of ReadReq MSHR hits 717system.cpu.icache.ReadReq_mshr_hits::total 61204 # number of ReadReq MSHR hits 718system.cpu.icache.demand_mshr_hits::cpu.inst 61204 # number of demand (read+write) MSHR hits 719system.cpu.icache.demand_mshr_hits::total 61204 # number of demand (read+write) MSHR hits 720system.cpu.icache.overall_mshr_hits::cpu.inst 61204 # number of overall MSHR hits 721system.cpu.icache.overall_mshr_hits::total 61204 # number of overall MSHR hits 722system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025966 # number of ReadReq MSHR misses 723system.cpu.icache.ReadReq_mshr_misses::total 1025966 # number of ReadReq MSHR misses 724system.cpu.icache.demand_mshr_misses::cpu.inst 1025966 # number of demand (read+write) MSHR misses 725system.cpu.icache.demand_mshr_misses::total 1025966 # number of demand (read+write) MSHR misses 726system.cpu.icache.overall_mshr_misses::cpu.inst 1025966 # number of overall MSHR misses 727system.cpu.icache.overall_mshr_misses::total 1025966 # number of overall MSHR misses 728system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13510508994 # number of ReadReq MSHR miss cycles 729system.cpu.icache.ReadReq_mshr_miss_latency::total 13510508994 # number of ReadReq MSHR miss cycles 730system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13510508994 # number of demand (read+write) MSHR miss cycles 731system.cpu.icache.demand_mshr_miss_latency::total 13510508994 # number of demand (read+write) MSHR miss cycles 732system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13510508994 # number of overall MSHR miss cycles 733system.cpu.icache.overall_mshr_miss_latency::total 13510508994 # number of overall MSHR miss cycles 734system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for ReadReq accesses 735system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115806 # mshr miss rate for ReadReq accesses 736system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for demand accesses 737system.cpu.icache.demand_mshr_miss_rate::total 0.115806 # mshr miss rate for demand accesses 738system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for overall accesses 739system.cpu.icache.overall_mshr_miss_rate::total 0.115806 # mshr miss rate for overall accesses 740system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13168.573807 # average ReadReq mshr miss latency 741system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13168.573807 # average ReadReq mshr miss latency 742system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency 743system.cpu.icache.demand_avg_mshr_miss_latency::total 13168.573807 # average overall mshr miss latency 744system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency 745system.cpu.icache.overall_avg_mshr_miss_latency::total 13168.573807 # average overall mshr miss latency | 726system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60612 # number of ReadReq MSHR hits 727system.cpu.icache.ReadReq_mshr_hits::total 60612 # number of ReadReq MSHR hits 728system.cpu.icache.demand_mshr_hits::cpu.inst 60612 # number of demand (read+write) MSHR hits 729system.cpu.icache.demand_mshr_hits::total 60612 # number of demand (read+write) MSHR hits 730system.cpu.icache.overall_mshr_hits::cpu.inst 60612 # number of overall MSHR hits 731system.cpu.icache.overall_mshr_hits::total 60612 # number of overall MSHR hits 732system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025143 # number of ReadReq MSHR misses 733system.cpu.icache.ReadReq_mshr_misses::total 1025143 # number of ReadReq MSHR misses 734system.cpu.icache.demand_mshr_misses::cpu.inst 1025143 # number of demand (read+write) MSHR misses 735system.cpu.icache.demand_mshr_misses::total 1025143 # number of demand (read+write) MSHR misses 736system.cpu.icache.overall_mshr_misses::cpu.inst 1025143 # number of overall MSHR misses 737system.cpu.icache.overall_mshr_misses::total 1025143 # number of overall MSHR misses 738system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13492714994 # number of ReadReq MSHR miss cycles 739system.cpu.icache.ReadReq_mshr_miss_latency::total 13492714994 # number of ReadReq MSHR miss cycles 740system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13492714994 # number of demand (read+write) MSHR miss cycles 741system.cpu.icache.demand_mshr_miss_latency::total 13492714994 # number of demand (read+write) MSHR miss cycles 742system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13492714994 # number of overall MSHR miss cycles 743system.cpu.icache.overall_mshr_miss_latency::total 13492714994 # number of overall MSHR miss cycles 744system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115897 # mshr miss rate for ReadReq accesses 745system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115897 # mshr miss rate for ReadReq accesses 746system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115897 # mshr miss rate for demand accesses 747system.cpu.icache.demand_mshr_miss_rate::total 0.115897 # mshr miss rate for demand accesses 748system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115897 # mshr miss rate for overall accesses 749system.cpu.icache.overall_mshr_miss_rate::total 0.115897 # mshr miss rate for overall accesses 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13161.788154 # average ReadReq mshr miss latency 751system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13161.788154 # average ReadReq mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13161.788154 # average overall mshr miss latency 753system.cpu.icache.demand_avg_mshr_miss_latency::total 13161.788154 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13161.788154 # average overall mshr miss latency 755system.cpu.icache.overall_avg_mshr_miss_latency::total 13161.788154 # average overall mshr miss latency |
| 746system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 756system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 747system.cpu.dcache.replacements 1403926 # number of replacements 748system.cpu.dcache.tagsinuse 511.995922 # Cycle average of tags in use 749system.cpu.dcache.total_refs 11884045 # Total number of references to valid blocks. 750system.cpu.dcache.sampled_refs 1404438 # Sample count of references to valid blocks. 751system.cpu.dcache.avg_refs 8.461780 # Average number of references to valid blocks. | 757system.cpu.dcache.replacements 1403592 # number of replacements 758system.cpu.dcache.tagsinuse 511.995920 # Cycle average of tags in use 759system.cpu.dcache.total_refs 11877954 # Total number of references to valid blocks. 760system.cpu.dcache.sampled_refs 1404104 # Sample count of references to valid blocks. 761system.cpu.dcache.avg_refs 8.459455 # Average number of references to valid blocks. |
| 752system.cpu.dcache.warmup_cycle 19693000 # Cycle when the warmup percentage was hit. | 762system.cpu.dcache.warmup_cycle 19693000 # Cycle when the warmup percentage was hit. |
| 753system.cpu.dcache.occ_blocks::cpu.data 511.995922 # Average occupied blocks per requestor | 763system.cpu.dcache.occ_blocks::cpu.data 511.995920 # Average occupied blocks per requestor |
| 754system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy 755system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy | 764system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy 765system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy |
| 756system.cpu.dcache.ReadReq_hits::cpu.data 7283526 # number of ReadReq hits 757system.cpu.dcache.ReadReq_hits::total 7283526 # number of ReadReq hits 758system.cpu.dcache.WriteReq_hits::cpu.data 4189382 # number of WriteReq hits 759system.cpu.dcache.WriteReq_hits::total 4189382 # number of WriteReq hits 760system.cpu.dcache.LoadLockedReq_hits::cpu.data 190687 # number of LoadLockedReq hits 761system.cpu.dcache.LoadLockedReq_hits::total 190687 # number of LoadLockedReq hits 762system.cpu.dcache.StoreCondReq_hits::cpu.data 220149 # number of StoreCondReq hits 763system.cpu.dcache.StoreCondReq_hits::total 220149 # number of StoreCondReq hits 764system.cpu.dcache.demand_hits::cpu.data 11472908 # number of demand (read+write) hits 765system.cpu.dcache.demand_hits::total 11472908 # number of demand (read+write) hits 766system.cpu.dcache.overall_hits::cpu.data 11472908 # number of overall hits 767system.cpu.dcache.overall_hits::total 11472908 # number of overall hits 768system.cpu.dcache.ReadReq_misses::cpu.data 1829585 # number of ReadReq misses 769system.cpu.dcache.ReadReq_misses::total 1829585 # number of ReadReq misses 770system.cpu.dcache.WriteReq_misses::cpu.data 1968134 # number of WriteReq misses 771system.cpu.dcache.WriteReq_misses::total 1968134 # number of WriteReq misses 772system.cpu.dcache.LoadLockedReq_misses::cpu.data 23417 # number of LoadLockedReq misses 773system.cpu.dcache.LoadLockedReq_misses::total 23417 # number of LoadLockedReq misses | 766system.cpu.dcache.ReadReq_hits::cpu.data 7277634 # number of ReadReq hits 767system.cpu.dcache.ReadReq_hits::total 7277634 # number of ReadReq hits 768system.cpu.dcache.WriteReq_hits::cpu.data 4189219 # number of WriteReq hits 769system.cpu.dcache.WriteReq_hits::total 4189219 # number of WriteReq hits 770system.cpu.dcache.LoadLockedReq_hits::cpu.data 190679 # number of LoadLockedReq hits 771system.cpu.dcache.LoadLockedReq_hits::total 190679 # number of LoadLockedReq hits 772system.cpu.dcache.StoreCondReq_hits::cpu.data 220144 # number of StoreCondReq hits 773system.cpu.dcache.StoreCondReq_hits::total 220144 # number of StoreCondReq hits 774system.cpu.dcache.demand_hits::cpu.data 11466853 # number of demand (read+write) hits 775system.cpu.dcache.demand_hits::total 11466853 # number of demand (read+write) hits 776system.cpu.dcache.overall_hits::cpu.data 11466853 # number of overall hits 777system.cpu.dcache.overall_hits::total 11466853 # number of overall hits 778system.cpu.dcache.ReadReq_misses::cpu.data 1830581 # number of ReadReq misses 779system.cpu.dcache.ReadReq_misses::total 1830581 # number of ReadReq misses 780system.cpu.dcache.WriteReq_misses::cpu.data 1967996 # number of WriteReq misses 781system.cpu.dcache.WriteReq_misses::total 1967996 # number of WriteReq misses 782system.cpu.dcache.LoadLockedReq_misses::cpu.data 23423 # number of LoadLockedReq misses 783system.cpu.dcache.LoadLockedReq_misses::total 23423 # number of LoadLockedReq misses |
| 774system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 775system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses | 784system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 785system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses |
| 776system.cpu.dcache.demand_misses::cpu.data 3797719 # number of demand (read+write) misses 777system.cpu.dcache.demand_misses::total 3797719 # number of demand (read+write) misses 778system.cpu.dcache.overall_misses::cpu.data 3797719 # number of overall misses 779system.cpu.dcache.overall_misses::total 3797719 # number of overall misses 780system.cpu.dcache.ReadReq_miss_latency::cpu.data 48849966500 # number of ReadReq miss cycles 781system.cpu.dcache.ReadReq_miss_latency::total 48849966500 # number of ReadReq miss cycles 782system.cpu.dcache.WriteReq_miss_latency::cpu.data 74989002011 # number of WriteReq miss cycles 783system.cpu.dcache.WriteReq_miss_latency::total 74989002011 # number of WriteReq miss cycles 784system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 432032000 # number of LoadLockedReq miss cycles 785system.cpu.dcache.LoadLockedReq_miss_latency::total 432032000 # number of LoadLockedReq miss cycles 786system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 56500 # number of StoreCondReq miss cycles 787system.cpu.dcache.StoreCondReq_miss_latency::total 56500 # number of StoreCondReq miss cycles 788system.cpu.dcache.demand_miss_latency::cpu.data 123838968511 # number of demand (read+write) miss cycles 789system.cpu.dcache.demand_miss_latency::total 123838968511 # number of demand (read+write) miss cycles 790system.cpu.dcache.overall_miss_latency::cpu.data 123838968511 # number of overall miss cycles 791system.cpu.dcache.overall_miss_latency::total 123838968511 # number of overall miss cycles 792system.cpu.dcache.ReadReq_accesses::cpu.data 9113111 # number of ReadReq accesses(hits+misses) 793system.cpu.dcache.ReadReq_accesses::total 9113111 # number of ReadReq accesses(hits+misses) 794system.cpu.dcache.WriteReq_accesses::cpu.data 6157516 # number of WriteReq accesses(hits+misses) 795system.cpu.dcache.WriteReq_accesses::total 6157516 # number of WriteReq accesses(hits+misses) 796system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214104 # number of LoadLockedReq accesses(hits+misses) 797system.cpu.dcache.LoadLockedReq_accesses::total 214104 # number of LoadLockedReq accesses(hits+misses) 798system.cpu.dcache.StoreCondReq_accesses::cpu.data 220153 # number of StoreCondReq accesses(hits+misses) 799system.cpu.dcache.StoreCondReq_accesses::total 220153 # number of StoreCondReq accesses(hits+misses) 800system.cpu.dcache.demand_accesses::cpu.data 15270627 # number of demand (read+write) accesses 801system.cpu.dcache.demand_accesses::total 15270627 # number of demand (read+write) accesses 802system.cpu.dcache.overall_accesses::cpu.data 15270627 # number of overall (read+write) accesses 803system.cpu.dcache.overall_accesses::total 15270627 # number of overall (read+write) accesses 804system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200764 # miss rate for ReadReq accesses 805system.cpu.dcache.ReadReq_miss_rate::total 0.200764 # miss rate for ReadReq accesses 806system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319631 # miss rate for WriteReq accesses 807system.cpu.dcache.WriteReq_miss_rate::total 0.319631 # miss rate for WriteReq accesses 808system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109372 # miss rate for LoadLockedReq accesses 809system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109372 # miss rate for LoadLockedReq accesses | 786system.cpu.dcache.demand_misses::cpu.data 3798577 # number of demand (read+write) misses 787system.cpu.dcache.demand_misses::total 3798577 # number of demand (read+write) misses 788system.cpu.dcache.overall_misses::cpu.data 3798577 # number of overall misses 789system.cpu.dcache.overall_misses::total 3798577 # number of overall misses 790system.cpu.dcache.ReadReq_miss_latency::cpu.data 48883672000 # number of ReadReq miss cycles 791system.cpu.dcache.ReadReq_miss_latency::total 48883672000 # number of ReadReq miss cycles 792system.cpu.dcache.WriteReq_miss_latency::cpu.data 74930562797 # number of WriteReq miss cycles 793system.cpu.dcache.WriteReq_miss_latency::total 74930562797 # number of WriteReq miss cycles 794system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 428682000 # number of LoadLockedReq miss cycles 795system.cpu.dcache.LoadLockedReq_miss_latency::total 428682000 # number of LoadLockedReq miss cycles 796system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 98000 # number of StoreCondReq miss cycles 797system.cpu.dcache.StoreCondReq_miss_latency::total 98000 # number of StoreCondReq miss cycles 798system.cpu.dcache.demand_miss_latency::cpu.data 123814234797 # number of demand (read+write) miss cycles 799system.cpu.dcache.demand_miss_latency::total 123814234797 # number of demand (read+write) miss cycles 800system.cpu.dcache.overall_miss_latency::cpu.data 123814234797 # number of overall miss cycles 801system.cpu.dcache.overall_miss_latency::total 123814234797 # number of overall miss cycles 802system.cpu.dcache.ReadReq_accesses::cpu.data 9108215 # number of ReadReq accesses(hits+misses) 803system.cpu.dcache.ReadReq_accesses::total 9108215 # number of ReadReq accesses(hits+misses) 804system.cpu.dcache.WriteReq_accesses::cpu.data 6157215 # number of WriteReq accesses(hits+misses) 805system.cpu.dcache.WriteReq_accesses::total 6157215 # number of WriteReq accesses(hits+misses) 806system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214102 # number of LoadLockedReq accesses(hits+misses) 807system.cpu.dcache.LoadLockedReq_accesses::total 214102 # number of LoadLockedReq accesses(hits+misses) 808system.cpu.dcache.StoreCondReq_accesses::cpu.data 220148 # number of StoreCondReq accesses(hits+misses) 809system.cpu.dcache.StoreCondReq_accesses::total 220148 # number of StoreCondReq accesses(hits+misses) 810system.cpu.dcache.demand_accesses::cpu.data 15265430 # number of demand (read+write) accesses 811system.cpu.dcache.demand_accesses::total 15265430 # number of demand (read+write) accesses 812system.cpu.dcache.overall_accesses::cpu.data 15265430 # number of overall (read+write) accesses 813system.cpu.dcache.overall_accesses::total 15265430 # number of overall (read+write) accesses 814system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200981 # miss rate for ReadReq accesses 815system.cpu.dcache.ReadReq_miss_rate::total 0.200981 # miss rate for ReadReq accesses 816system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319624 # miss rate for WriteReq accesses 817system.cpu.dcache.WriteReq_miss_rate::total 0.319624 # miss rate for WriteReq accesses 818system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109401 # miss rate for LoadLockedReq accesses 819system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109401 # miss rate for LoadLockedReq accesses |
| 810system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000018 # miss rate for StoreCondReq accesses 811system.cpu.dcache.StoreCondReq_miss_rate::total 0.000018 # miss rate for StoreCondReq accesses | 820system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000018 # miss rate for StoreCondReq accesses 821system.cpu.dcache.StoreCondReq_miss_rate::total 0.000018 # miss rate for StoreCondReq accesses |
| 812system.cpu.dcache.demand_miss_rate::cpu.data 0.248694 # miss rate for demand accesses 813system.cpu.dcache.demand_miss_rate::total 0.248694 # miss rate for demand accesses 814system.cpu.dcache.overall_miss_rate::cpu.data 0.248694 # miss rate for overall accesses 815system.cpu.dcache.overall_miss_rate::total 0.248694 # miss rate for overall accesses 816system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26700.025689 # average ReadReq miss latency 817system.cpu.dcache.ReadReq_avg_miss_latency::total 26700.025689 # average ReadReq miss latency 818system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38101.573374 # average WriteReq miss latency 819system.cpu.dcache.WriteReq_avg_miss_latency::total 38101.573374 # average WriteReq miss latency 820system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18449.502498 # average LoadLockedReq miss latency 821system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18449.502498 # average LoadLockedReq miss latency 822system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14125 # average StoreCondReq miss latency 823system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14125 # average StoreCondReq miss latency 824system.cpu.dcache.demand_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency 825system.cpu.dcache.demand_avg_miss_latency::total 32608.776087 # average overall miss latency 826system.cpu.dcache.overall_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency 827system.cpu.dcache.overall_avg_miss_latency::total 32608.776087 # average overall miss latency 828system.cpu.dcache.blocked_cycles::no_mshrs 732928021 # number of cycles access was blocked | 822system.cpu.dcache.demand_miss_rate::cpu.data 0.248835 # miss rate for demand accesses 823system.cpu.dcache.demand_miss_rate::total 0.248835 # miss rate for demand accesses 824system.cpu.dcache.overall_miss_rate::cpu.data 0.248835 # miss rate for overall accesses 825system.cpu.dcache.overall_miss_rate::total 0.248835 # miss rate for overall accesses 826system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26703.910944 # average ReadReq miss latency 827system.cpu.dcache.ReadReq_avg_miss_latency::total 26703.910944 # average ReadReq miss latency 828system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38074.550353 # average WriteReq miss latency 829system.cpu.dcache.WriteReq_avg_miss_latency::total 38074.550353 # average WriteReq miss latency 830system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18301.754686 # average LoadLockedReq miss latency 831system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18301.754686 # average LoadLockedReq miss latency 832system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24500 # average StoreCondReq miss latency 833system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24500 # average StoreCondReq miss latency 834system.cpu.dcache.demand_avg_miss_latency::cpu.data 32594.899300 # average overall miss latency 835system.cpu.dcache.demand_avg_miss_latency::total 32594.899300 # average overall miss latency 836system.cpu.dcache.overall_avg_miss_latency::cpu.data 32594.899300 # average overall miss latency 837system.cpu.dcache.overall_avg_miss_latency::total 32594.899300 # average overall miss latency 838system.cpu.dcache.blocked_cycles::no_mshrs 731758024 # number of cycles access was blocked |
| 829system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked | 839system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked |
| 830system.cpu.dcache.blocked::no_mshrs 72145 # number of cycles access was blocked | 840system.cpu.dcache.blocked::no_mshrs 72544 # number of cycles access was blocked |
| 831system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked | 841system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 832system.cpu.dcache.avg_blocked_cycles::no_mshrs 10159.096556 # average number of cycles each access was blocked | 842system.cpu.dcache.avg_blocked_cycles::no_mshrs 10087.092303 # average number of cycles each access was blocked |
| 833system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked 834system.cpu.dcache.fast_writes 0 # number of fast writes performed 835system.cpu.dcache.cache_copies 0 # number of cache copies performed | 843system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked 844system.cpu.dcache.fast_writes 0 # number of fast writes performed 845system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 836system.cpu.dcache.writebacks::writebacks 842954 # number of writebacks 837system.cpu.dcache.writebacks::total 842954 # number of writebacks 838system.cpu.dcache.ReadReq_mshr_hits::cpu.data 743747 # number of ReadReq MSHR hits 839system.cpu.dcache.ReadReq_mshr_hits::total 743747 # number of ReadReq MSHR hits 840system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667534 # number of WriteReq MSHR hits 841system.cpu.dcache.WriteReq_mshr_hits::total 1667534 # number of WriteReq MSHR hits 842system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5230 # number of LoadLockedReq MSHR hits 843system.cpu.dcache.LoadLockedReq_mshr_hits::total 5230 # number of LoadLockedReq MSHR hits 844system.cpu.dcache.demand_mshr_hits::cpu.data 2411281 # number of demand (read+write) MSHR hits 845system.cpu.dcache.demand_mshr_hits::total 2411281 # number of demand (read+write) MSHR hits 846system.cpu.dcache.overall_mshr_hits::cpu.data 2411281 # number of overall MSHR hits 847system.cpu.dcache.overall_mshr_hits::total 2411281 # number of overall MSHR hits 848system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085838 # number of ReadReq MSHR misses 849system.cpu.dcache.ReadReq_mshr_misses::total 1085838 # number of ReadReq MSHR misses 850system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300600 # number of WriteReq MSHR misses 851system.cpu.dcache.WriteReq_mshr_misses::total 300600 # number of WriteReq MSHR misses 852system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18187 # number of LoadLockedReq MSHR misses 853system.cpu.dcache.LoadLockedReq_mshr_misses::total 18187 # number of LoadLockedReq MSHR misses | 846system.cpu.dcache.writebacks::writebacks 842689 # number of writebacks 847system.cpu.dcache.writebacks::total 842689 # number of writebacks 848system.cpu.dcache.ReadReq_mshr_hits::cpu.data 745053 # number of ReadReq MSHR hits 849system.cpu.dcache.ReadReq_mshr_hits::total 745053 # number of ReadReq MSHR hits 850system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667452 # number of WriteReq MSHR hits 851system.cpu.dcache.WriteReq_mshr_hits::total 1667452 # number of WriteReq MSHR hits 852system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits 853system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits 854system.cpu.dcache.demand_mshr_hits::cpu.data 2412505 # number of demand (read+write) MSHR hits 855system.cpu.dcache.demand_mshr_hits::total 2412505 # number of demand (read+write) MSHR hits 856system.cpu.dcache.overall_mshr_hits::cpu.data 2412505 # number of overall MSHR hits 857system.cpu.dcache.overall_mshr_hits::total 2412505 # number of overall MSHR hits 858system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085528 # number of ReadReq MSHR misses 859system.cpu.dcache.ReadReq_mshr_misses::total 1085528 # number of ReadReq MSHR misses 860system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300544 # number of WriteReq MSHR misses 861system.cpu.dcache.WriteReq_mshr_misses::total 300544 # number of WriteReq MSHR misses 862system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18217 # number of LoadLockedReq MSHR misses 863system.cpu.dcache.LoadLockedReq_mshr_misses::total 18217 # number of LoadLockedReq MSHR misses |
| 854system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses 855system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses | 864system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses 865system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses |
| 856system.cpu.dcache.demand_mshr_misses::cpu.data 1386438 # number of demand (read+write) MSHR misses 857system.cpu.dcache.demand_mshr_misses::total 1386438 # number of demand (read+write) MSHR misses 858system.cpu.dcache.overall_mshr_misses::cpu.data 1386438 # number of overall MSHR misses 859system.cpu.dcache.overall_mshr_misses::total 1386438 # number of overall MSHR misses 860system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28239740000 # number of ReadReq MSHR miss cycles 861system.cpu.dcache.ReadReq_mshr_miss_latency::total 28239740000 # number of ReadReq MSHR miss cycles 862system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9650792448 # number of WriteReq MSHR miss cycles 863system.cpu.dcache.WriteReq_mshr_miss_latency::total 9650792448 # number of WriteReq MSHR miss cycles 864system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 273508500 # number of LoadLockedReq MSHR miss cycles 865system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 273508500 # number of LoadLockedReq MSHR miss cycles 866system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 44000 # number of StoreCondReq MSHR miss cycles 867system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles 868system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37890532448 # number of demand (read+write) MSHR miss cycles 869system.cpu.dcache.demand_mshr_miss_latency::total 37890532448 # number of demand (read+write) MSHR miss cycles 870system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37890532448 # number of overall MSHR miss cycles 871system.cpu.dcache.overall_mshr_miss_latency::total 37890532448 # number of overall MSHR miss cycles 872system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 905949500 # number of ReadReq MSHR uncacheable cycles 873system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 905949500 # number of ReadReq MSHR uncacheable cycles 874system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1225663998 # number of WriteReq MSHR uncacheable cycles 875system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1225663998 # number of WriteReq MSHR uncacheable cycles 876system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2131613498 # number of overall MSHR uncacheable cycles 877system.cpu.dcache.overall_mshr_uncacheable_latency::total 2131613498 # number of overall MSHR uncacheable cycles 878system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119151 # mshr miss rate for ReadReq accesses 879system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119151 # mshr miss rate for ReadReq accesses 880system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048818 # mshr miss rate for WriteReq accesses 881system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048818 # mshr miss rate for WriteReq accesses 882system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084945 # mshr miss rate for LoadLockedReq accesses 883system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084945 # mshr miss rate for LoadLockedReq accesses | 866system.cpu.dcache.demand_mshr_misses::cpu.data 1386072 # number of demand (read+write) MSHR misses 867system.cpu.dcache.demand_mshr_misses::total 1386072 # number of demand (read+write) MSHR misses 868system.cpu.dcache.overall_mshr_misses::cpu.data 1386072 # number of overall MSHR misses 869system.cpu.dcache.overall_mshr_misses::total 1386072 # number of overall MSHR misses 870system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28234901500 # number of ReadReq MSHR miss cycles 871system.cpu.dcache.ReadReq_mshr_miss_latency::total 28234901500 # number of ReadReq MSHR miss cycles 872system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9648960448 # number of WriteReq MSHR miss cycles 873system.cpu.dcache.WriteReq_mshr_miss_latency::total 9648960448 # number of WriteReq MSHR miss cycles 874system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 269943500 # number of LoadLockedReq MSHR miss cycles 875system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 269943500 # number of LoadLockedReq MSHR miss cycles 876system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 85500 # number of StoreCondReq MSHR miss cycles 877system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 85500 # number of StoreCondReq MSHR miss cycles 878system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37883861948 # number of demand (read+write) MSHR miss cycles 879system.cpu.dcache.demand_mshr_miss_latency::total 37883861948 # number of demand (read+write) MSHR miss cycles 880system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37883861948 # number of overall MSHR miss cycles 881system.cpu.dcache.overall_mshr_miss_latency::total 37883861948 # number of overall MSHR miss cycles 882system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904971500 # number of ReadReq MSHR uncacheable cycles 883system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904971500 # number of ReadReq MSHR uncacheable cycles 884system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1224983998 # number of WriteReq MSHR uncacheable cycles 885system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1224983998 # number of WriteReq MSHR uncacheable cycles 886system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2129955498 # number of overall MSHR uncacheable cycles 887system.cpu.dcache.overall_mshr_uncacheable_latency::total 2129955498 # number of overall MSHR uncacheable cycles 888system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119181 # mshr miss rate for ReadReq accesses 889system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119181 # mshr miss rate for ReadReq accesses 890system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048812 # mshr miss rate for WriteReq accesses 891system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048812 # mshr miss rate for WriteReq accesses 892system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085086 # mshr miss rate for LoadLockedReq accesses 893system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085086 # mshr miss rate for LoadLockedReq accesses |
| 884system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000018 # mshr miss rate for StoreCondReq accesses 885system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000018 # mshr miss rate for StoreCondReq accesses | 894system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000018 # mshr miss rate for StoreCondReq accesses 895system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000018 # mshr miss rate for StoreCondReq accesses |
| 886system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for demand accesses 887system.cpu.dcache.demand_mshr_miss_rate::total 0.090791 # mshr miss rate for demand accesses 888system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for overall accesses 889system.cpu.dcache.overall_mshr_miss_rate::total 0.090791 # mshr miss rate for overall accesses 890system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26007.323376 # average ReadReq mshr miss latency 891system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26007.323376 # average ReadReq mshr miss latency 892system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32105.097964 # average WriteReq mshr miss latency 893system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32105.097964 # average WriteReq mshr miss latency 894system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15038.681476 # average LoadLockedReq mshr miss latency 895system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15038.681476 # average LoadLockedReq mshr miss latency 896system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 897system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 898system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency 899system.cpu.dcache.demand_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency 900system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency 901system.cpu.dcache.overall_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency | 896system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090798 # mshr miss rate for demand accesses 897system.cpu.dcache.demand_mshr_miss_rate::total 0.090798 # mshr miss rate for demand accesses 898system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090798 # mshr miss rate for overall accesses 899system.cpu.dcache.overall_mshr_miss_rate::total 0.090798 # mshr miss rate for overall accesses 900system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26010.293148 # average ReadReq mshr miss latency 901system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26010.293148 # average ReadReq mshr miss latency 902system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32104.984455 # average WriteReq mshr miss latency 903system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32104.984455 # average WriteReq mshr miss latency 904system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14818.219246 # average LoadLockedReq mshr miss latency 905system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14818.219246 # average LoadLockedReq mshr miss latency 906system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 21375 # average StoreCondReq mshr miss latency 907system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 21375 # average StoreCondReq mshr miss latency 908system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27331.813894 # average overall mshr miss latency 909system.cpu.dcache.demand_avg_mshr_miss_latency::total 27331.813894 # average overall mshr miss latency 910system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27331.813894 # average overall mshr miss latency 911system.cpu.dcache.overall_avg_mshr_miss_latency::total 27331.813894 # average overall mshr miss latency |
| 902system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 903system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 904system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 905system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 906system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 907system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 908system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 909system.cpu.kern.inst.arm 0 # number of arm instructions executed | 912system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 913system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 914system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 915system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 916system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 917system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 918system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 919system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 910system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed 911system.cpu.kern.inst.hwrei 211694 # number of hwrei instructions executed 912system.cpu.kern.ipl_count::0 74899 40.95% 40.95% # number of times we switched to this ipl 913system.cpu.kern.ipl_count::21 247 0.14% 41.08% # number of times we switched to this ipl 914system.cpu.kern.ipl_count::22 1887 1.03% 42.11% # number of times we switched to this ipl 915system.cpu.kern.ipl_count::31 105884 57.89% 100.00% # number of times we switched to this ipl 916system.cpu.kern.ipl_count::total 182917 # number of times we switched to this ipl 917system.cpu.kern.ipl_good::0 73532 49.28% 49.28% # number of times we switched to this ipl from a different ipl 918system.cpu.kern.ipl_good::21 247 0.17% 49.45% # number of times we switched to this ipl from a different ipl 919system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl 920system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl 921system.cpu.kern.ipl_good::total 149203 # number of times we switched to this ipl from a different ipl 922system.cpu.kern.ipl_ticks::0 1825754390000 97.87% 97.87% # number of cycles we spent at this ipl 923system.cpu.kern.ipl_ticks::21 99081000 0.01% 97.88% # number of cycles we spent at this ipl 924system.cpu.kern.ipl_ticks::22 381309500 0.02% 97.90% # number of cycles we spent at this ipl 925system.cpu.kern.ipl_ticks::31 39166410000 2.10% 100.00% # number of cycles we spent at this ipl 926system.cpu.kern.ipl_ticks::total 1865401190500 # number of cycles we spent at this ipl 927system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl | 920system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed 921system.cpu.kern.inst.hwrei 211669 # number of hwrei instructions executed 922system.cpu.kern.ipl_count::0 74897 40.95% 40.95% # number of times we switched to this ipl 923system.cpu.kern.ipl_count::21 243 0.13% 41.08% # number of times we switched to this ipl 924system.cpu.kern.ipl_count::22 1886 1.03% 42.12% # number of times we switched to this ipl 925system.cpu.kern.ipl_count::31 105867 57.88% 100.00% # number of times we switched to this ipl 926system.cpu.kern.ipl_count::total 182893 # number of times we switched to this ipl 927system.cpu.kern.ipl_good::0 73530 49.29% 49.29% # number of times we switched to this ipl from a different ipl 928system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl 929system.cpu.kern.ipl_good::22 1886 1.26% 50.71% # number of times we switched to this ipl from a different ipl 930system.cpu.kern.ipl_good::31 73533 49.29% 100.00% # number of times we switched to this ipl from a different ipl 931system.cpu.kern.ipl_good::total 149192 # number of times we switched to this ipl from a different ipl 932system.cpu.kern.ipl_ticks::0 1824783514500 97.87% 97.87% # number of cycles we spent at this ipl 933system.cpu.kern.ipl_ticks::21 98568000 0.01% 97.88% # number of cycles we spent at this ipl 934system.cpu.kern.ipl_ticks::22 384878500 0.02% 97.90% # number of cycles we spent at this ipl 935system.cpu.kern.ipl_ticks::31 39156084500 2.10% 100.00% # number of cycles we spent at this ipl 936system.cpu.kern.ipl_ticks::total 1864423045500 # number of cycles we spent at this ipl 937system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl |
| 928system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 929system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 938system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 939system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 930system.cpu.kern.ipl_used::31 0.694505 # fraction of swpipl calls that actually changed the ipl 931system.cpu.kern.ipl_used::total 0.815687 # fraction of swpipl calls that actually changed the ipl | 940system.cpu.kern.ipl_used::31 0.694579 # fraction of swpipl calls that actually changed the ipl 941system.cpu.kern.ipl_used::total 0.815734 # fraction of swpipl calls that actually changed the ipl |
| 932system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 933system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 934system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 935system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 936system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 937system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 938system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 939system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 962system.cpu.kern.syscall::total 326 # number of syscalls executed 963system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 964system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 965system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 966system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 967system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 968system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 969system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 942system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 943system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 944system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 945system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 946system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 947system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 948system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 949system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 972system.cpu.kern.syscall::total 326 # number of syscalls executed 973system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 974system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 975system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 976system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 977system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 978system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 979system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 970system.cpu.kern.callpal::swpipl 175564 91.19% 93.39% # number of callpals executed 971system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed | 980system.cpu.kern.callpal::swpipl 175546 91.19% 93.39% # number of callpals executed 981system.cpu.kern.callpal::rdps 6791 3.53% 96.92% # number of callpals executed |
| 972system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 973system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed | 982system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 983system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed |
| 974system.cpu.kern.callpal::rdusp 9 0.00% 96.92% # number of callpals executed | 984system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed |
| 975system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed | 985system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed |
| 976system.cpu.kern.callpal::rti 5223 2.71% 99.64% # number of callpals executed | 986system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed |
| 977system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 978system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 987system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 988system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 979system.cpu.kern.callpal::total 192535 # number of callpals executed 980system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches | 989system.cpu.kern.callpal::total 192513 # number of callpals executed 990system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches |
| 981system.cpu.kern.mode_switch::user 1736 # number of protection mode switches | 991system.cpu.kern.mode_switch::user 1736 # number of protection mode switches |
| 982system.cpu.kern.mode_switch::idle 2110 # number of protection mode switches | 992system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches |
| 983system.cpu.kern.mode_good::kernel 1906 984system.cpu.kern.mode_good::user 1736 985system.cpu.kern.mode_good::idle 170 | 993system.cpu.kern.mode_good::kernel 1906 994system.cpu.kern.mode_good::user 1736 995system.cpu.kern.mode_good::idle 170 |
| 986system.cpu.kern.mode_switch_good::kernel 0.320067 # fraction of useful protection mode switches | 996system.cpu.kern.mode_switch_good::kernel 0.320013 # fraction of useful protection mode switches |
| 987system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 997system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 988system.cpu.kern.mode_switch_good::idle 0.080569 # fraction of useful protection mode switches 989system.cpu.kern.mode_switch_good::total 0.388940 # fraction of useful protection mode switches 990system.cpu.kern.mode_ticks::kernel 29632954500 1.59% 1.59% # number of ticks spent at the given mode 991system.cpu.kern.mode_ticks::user 2782152500 0.15% 1.74% # number of ticks spent at the given mode 992system.cpu.kern.mode_ticks::idle 1832986075500 98.26% 100.00% # number of ticks spent at the given mode | 998system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches 999system.cpu.kern.mode_switch_good::total 0.389059 # fraction of useful protection mode switches 1000system.cpu.kern.mode_ticks::kernel 29626491000 1.59% 1.59% # number of ticks spent at the given mode 1001system.cpu.kern.mode_ticks::user 2782272500 0.15% 1.74% # number of ticks spent at the given mode 1002system.cpu.kern.mode_ticks::idle 1832014274000 98.26% 100.00% # number of ticks spent at the given mode |
| 993system.cpu.kern.swap_context 4177 # number of times the context was actually changed 994 995---------- End Simulation Statistics ---------- | 1003system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1004 1005---------- End Simulation Statistics ---------- |