| stats.txt (9079:9a244ebdc3c9) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.858880 # Number of seconds simulated 4sim_ticks 1858879782500 # Number of ticks simulated 5final_tick 1858879782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.865402 # Number of seconds simulated 4sim_ticks 1865402113500 # Number of ticks simulated 5final_tick 1865402113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 196297 # Simulator instruction rate (inst/s) 8host_op_rate 196297 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6876664069 # Simulator tick rate (ticks/s) 10host_mem_usage 298988 # Number of bytes of host memory used 11host_seconds 270.32 # Real time elapsed on the host 12sim_insts 53062487 # Number of instructions simulated 13sim_ops 53062487 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24884032 # Number of bytes read from this memory | 7host_inst_rate 131129 # Simulator instruction rate (inst/s) 8host_op_rate 131129 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4607058697 # Simulator tick rate (ticks/s) 10host_mem_usage 298956 # Number of bytes of host memory used 11host_seconds 404.90 # Real time elapsed on the host 12sim_insts 53094243 # Number of instructions simulated 13sim_ops 53094243 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 967424 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24877312 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::total 28505408 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388813 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::total 28497024 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 967424 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 967424 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7516928 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7516928 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15116 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388708 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory | 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::total 445397 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 521329 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13386574 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1426821 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15334724 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 521329 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 521329 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4048064 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4048064 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4048064 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 521329 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13386574 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1426821 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19382788 # Total bandwidth to/from this memory (bytes/s) 41system.l2c.replacements 338457 # number of replacements 42system.l2c.tagsinuse 65351.732427 # Cycle average of tags in use 43system.l2c.total_refs 2557615 # Total number of references to valid blocks. 44system.l2c.sampled_refs 403631 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.336518 # Average number of references to valid blocks. 46system.l2c.warmup_cycle 4816079000 # Cycle when the warmup percentage was hit. 47system.l2c.occ_blocks::writebacks 53832.150010 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 5352.172668 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 6167.409749 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.821413 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.081668 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.094107 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.997188 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 1006386 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 826813 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1833199 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 841169 # number of Writeback hits 58system.l2c.Writeback_hits::total 841169 # number of Writeback hits 59system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits 61system.l2c.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 62system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 63system.l2c.ReadExReq_hits::cpu.data 185491 # number of ReadExReq hits 64system.l2c.ReadExReq_hits::total 185491 # number of ReadExReq hits 65system.l2c.demand_hits::cpu.inst 1006386 # number of demand (read+write) hits 66system.l2c.demand_hits::cpu.data 1012304 # number of demand (read+write) hits 67system.l2c.demand_hits::total 2018690 # number of demand (read+write) hits 68system.l2c.overall_hits::cpu.inst 1006386 # number of overall hits 69system.l2c.overall_hits::cpu.data 1012304 # number of overall hits 70system.l2c.overall_hits::total 2018690 # number of overall hits 71system.l2c.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses 72system.l2c.ReadReq_misses::cpu.data 273879 # number of ReadReq misses 73system.l2c.ReadReq_misses::total 289023 # number of ReadReq misses 74system.l2c.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses 75system.l2c.UpgradeReq_misses::total 27 # number of UpgradeReq misses 76system.l2c.ReadExReq_misses::cpu.data 115423 # number of ReadExReq misses 77system.l2c.ReadExReq_misses::total 115423 # number of ReadExReq misses 78system.l2c.demand_misses::cpu.inst 15144 # number of demand (read+write) misses 79system.l2c.demand_misses::cpu.data 389302 # number of demand (read+write) misses 80system.l2c.demand_misses::total 404446 # number of demand (read+write) misses 81system.l2c.overall_misses::cpu.inst 15144 # number of overall misses 82system.l2c.overall_misses::cpu.data 389302 # number of overall misses 83system.l2c.overall_misses::total 404446 # number of overall misses 84system.l2c.ReadReq_miss_latency::cpu.inst 792218000 # number of ReadReq miss cycles 85system.l2c.ReadReq_miss_latency::cpu.data 14246173000 # number of ReadReq miss cycles 86system.l2c.ReadReq_miss_latency::total 15038391000 # number of ReadReq miss cycles 87system.l2c.UpgradeReq_miss_latency::cpu.data 322000 # number of UpgradeReq miss cycles 88system.l2c.UpgradeReq_miss_latency::total 322000 # number of UpgradeReq miss cycles 89system.l2c.ReadExReq_miss_latency::cpu.data 6056487000 # number of ReadExReq miss cycles 90system.l2c.ReadExReq_miss_latency::total 6056487000 # number of ReadExReq miss cycles 91system.l2c.demand_miss_latency::cpu.inst 792218000 # number of demand (read+write) miss cycles 92system.l2c.demand_miss_latency::cpu.data 20302660000 # number of demand (read+write) miss cycles 93system.l2c.demand_miss_latency::total 21094878000 # number of demand (read+write) miss cycles 94system.l2c.overall_miss_latency::cpu.inst 792218000 # number of overall miss cycles 95system.l2c.overall_miss_latency::cpu.data 20302660000 # number of overall miss cycles 96system.l2c.overall_miss_latency::total 21094878000 # number of overall miss cycles 97system.l2c.ReadReq_accesses::cpu.inst 1021530 # number of ReadReq accesses(hits+misses) 98system.l2c.ReadReq_accesses::cpu.data 1100692 # number of ReadReq accesses(hits+misses) 99system.l2c.ReadReq_accesses::total 2122222 # number of ReadReq accesses(hits+misses) 100system.l2c.Writeback_accesses::writebacks 841169 # number of Writeback accesses(hits+misses) 101system.l2c.Writeback_accesses::total 841169 # number of Writeback accesses(hits+misses) 102system.l2c.UpgradeReq_accesses::cpu.data 42 # number of UpgradeReq accesses(hits+misses) 103system.l2c.UpgradeReq_accesses::total 42 # number of UpgradeReq accesses(hits+misses) 104system.l2c.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 105system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 106system.l2c.ReadExReq_accesses::cpu.data 300914 # number of ReadExReq accesses(hits+misses) 107system.l2c.ReadExReq_accesses::total 300914 # number of ReadExReq accesses(hits+misses) 108system.l2c.demand_accesses::cpu.inst 1021530 # number of demand (read+write) accesses 109system.l2c.demand_accesses::cpu.data 1401606 # number of demand (read+write) accesses 110system.l2c.demand_accesses::total 2423136 # number of demand (read+write) accesses 111system.l2c.overall_accesses::cpu.inst 1021530 # number of overall (read+write) accesses 112system.l2c.overall_accesses::cpu.data 1401606 # number of overall (read+write) accesses 113system.l2c.overall_accesses::total 2423136 # number of overall (read+write) accesses 114system.l2c.ReadReq_miss_rate::cpu.inst 0.014825 # miss rate for ReadReq accesses 115system.l2c.ReadReq_miss_rate::cpu.data 0.248824 # miss rate for ReadReq accesses 116system.l2c.ReadReq_miss_rate::total 0.136189 # miss rate for ReadReq accesses 117system.l2c.UpgradeReq_miss_rate::cpu.data 0.642857 # miss rate for UpgradeReq accesses 118system.l2c.UpgradeReq_miss_rate::total 0.642857 # miss rate for UpgradeReq accesses 119system.l2c.ReadExReq_miss_rate::cpu.data 0.383575 # miss rate for ReadExReq accesses 120system.l2c.ReadExReq_miss_rate::total 0.383575 # miss rate for ReadExReq accesses 121system.l2c.demand_miss_rate::cpu.inst 0.014825 # miss rate for demand accesses 122system.l2c.demand_miss_rate::cpu.data 0.277754 # miss rate for demand accesses 123system.l2c.demand_miss_rate::total 0.166910 # miss rate for demand accesses 124system.l2c.overall_miss_rate::cpu.inst 0.014825 # miss rate for overall accesses 125system.l2c.overall_miss_rate::cpu.data 0.277754 # miss rate for overall accesses 126system.l2c.overall_miss_rate::total 0.166910 # miss rate for overall accesses 127system.l2c.ReadReq_avg_miss_latency::cpu.inst 52312.334918 # average ReadReq miss latency 128system.l2c.ReadReq_avg_miss_latency::cpu.data 52016.302820 # average ReadReq miss latency 129system.l2c.ReadReq_avg_miss_latency::total 52031.814077 # average ReadReq miss latency 130system.l2c.UpgradeReq_avg_miss_latency::cpu.data 11925.925926 # average UpgradeReq miss latency 131system.l2c.UpgradeReq_avg_miss_latency::total 11925.925926 # average UpgradeReq miss latency 132system.l2c.ReadExReq_avg_miss_latency::cpu.data 52472.098282 # average ReadExReq miss latency 133system.l2c.ReadExReq_avg_miss_latency::total 52472.098282 # average ReadExReq miss latency 134system.l2c.demand_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency 135system.l2c.demand_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency 136system.l2c.demand_avg_miss_latency::total 52157.464779 # average overall miss latency 137system.l2c.overall_avg_miss_latency::cpu.inst 52312.334918 # average overall miss latency 138system.l2c.overall_avg_miss_latency::cpu.data 52151.440270 # average overall miss latency 139system.l2c.overall_avg_miss_latency::total 52157.464779 # average overall miss latency | 25system.physmem.num_reads::total 445266 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117452 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117452 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 518614 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13336166 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1421832 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15276612 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 518614 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 518614 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4029656 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4029656 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4029656 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 518614 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13336166 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1421832 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19306267 # Total bandwidth to/from this memory (bytes/s) 41system.l2c.replacements 338323 # number of replacements 42system.l2c.tagsinuse 65346.781313 # Cycle average of tags in use 43system.l2c.total_refs 2566599 # Total number of references to valid blocks. 44system.l2c.sampled_refs 403491 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.360982 # Average number of references to valid blocks. 46system.l2c.warmup_cycle 4861120000 # Cycle when the warmup percentage was hit. 47system.l2c.occ_blocks::writebacks 53937.288272 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 5357.413768 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 6052.079273 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.823018 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.081748 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.092347 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.997113 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 1010692 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 829338 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1840030 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 843192 # number of Writeback hits 58system.l2c.Writeback_hits::total 843192 # number of Writeback hits 59system.l2c.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 35 # number of UpgradeReq hits 61system.l2c.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits 62system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits 63system.l2c.ReadExReq_hits::cpu.data 185767 # number of ReadExReq hits 64system.l2c.ReadExReq_hits::total 185767 # number of ReadExReq hits 65system.l2c.demand_hits::cpu.inst 1010692 # number of demand (read+write) hits 66system.l2c.demand_hits::cpu.data 1015105 # number of demand (read+write) hits 67system.l2c.demand_hits::total 2025797 # number of demand (read+write) hits 68system.l2c.overall_hits::cpu.inst 1010692 # number of overall hits 69system.l2c.overall_hits::cpu.data 1015105 # number of overall hits 70system.l2c.overall_hits::total 2025797 # number of overall hits 71system.l2c.ReadReq_misses::cpu.inst 15118 # number of ReadReq misses 72system.l2c.ReadReq_misses::cpu.data 273845 # number of ReadReq misses 73system.l2c.ReadReq_misses::total 288963 # number of ReadReq misses 74system.l2c.UpgradeReq_misses::cpu.data 49 # number of UpgradeReq misses 75system.l2c.UpgradeReq_misses::total 49 # number of UpgradeReq misses 76system.l2c.ReadExReq_misses::cpu.data 115352 # number of ReadExReq misses 77system.l2c.ReadExReq_misses::total 115352 # number of ReadExReq misses 78system.l2c.demand_misses::cpu.inst 15118 # number of demand (read+write) misses 79system.l2c.demand_misses::cpu.data 389197 # number of demand (read+write) misses 80system.l2c.demand_misses::total 404315 # number of demand (read+write) misses 81system.l2c.overall_misses::cpu.inst 15118 # number of overall misses 82system.l2c.overall_misses::cpu.data 389197 # number of overall misses 83system.l2c.overall_misses::total 404315 # number of overall misses 84system.l2c.ReadReq_miss_latency::cpu.inst 805739998 # number of ReadReq miss cycles 85system.l2c.ReadReq_miss_latency::cpu.data 14260725000 # number of ReadReq miss cycles 86system.l2c.ReadReq_miss_latency::total 15066464998 # number of ReadReq miss cycles 87system.l2c.UpgradeReq_miss_latency::cpu.data 501500 # number of UpgradeReq miss cycles 88system.l2c.UpgradeReq_miss_latency::total 501500 # number of UpgradeReq miss cycles 89system.l2c.ReadExReq_miss_latency::cpu.data 6190534997 # number of ReadExReq miss cycles 90system.l2c.ReadExReq_miss_latency::total 6190534997 # number of ReadExReq miss cycles 91system.l2c.demand_miss_latency::cpu.inst 805739998 # number of demand (read+write) miss cycles 92system.l2c.demand_miss_latency::cpu.data 20451259997 # number of demand (read+write) miss cycles 93system.l2c.demand_miss_latency::total 21256999995 # number of demand (read+write) miss cycles 94system.l2c.overall_miss_latency::cpu.inst 805739998 # number of overall miss cycles 95system.l2c.overall_miss_latency::cpu.data 20451259997 # number of overall miss cycles 96system.l2c.overall_miss_latency::total 21256999995 # number of overall miss cycles 97system.l2c.ReadReq_accesses::cpu.inst 1025810 # number of ReadReq accesses(hits+misses) 98system.l2c.ReadReq_accesses::cpu.data 1103183 # number of ReadReq accesses(hits+misses) 99system.l2c.ReadReq_accesses::total 2128993 # number of ReadReq accesses(hits+misses) 100system.l2c.Writeback_accesses::writebacks 843192 # number of Writeback accesses(hits+misses) 101system.l2c.Writeback_accesses::total 843192 # number of Writeback accesses(hits+misses) 102system.l2c.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) 103system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) 104system.l2c.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) 105system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) 106system.l2c.ReadExReq_accesses::cpu.data 301119 # number of ReadExReq accesses(hits+misses) 107system.l2c.ReadExReq_accesses::total 301119 # number of ReadExReq accesses(hits+misses) 108system.l2c.demand_accesses::cpu.inst 1025810 # number of demand (read+write) accesses 109system.l2c.demand_accesses::cpu.data 1404302 # number of demand (read+write) accesses 110system.l2c.demand_accesses::total 2430112 # number of demand (read+write) accesses 111system.l2c.overall_accesses::cpu.inst 1025810 # number of overall (read+write) accesses 112system.l2c.overall_accesses::cpu.data 1404302 # number of overall (read+write) accesses 113system.l2c.overall_accesses::total 2430112 # number of overall (read+write) accesses 114system.l2c.ReadReq_miss_rate::cpu.inst 0.014738 # miss rate for ReadReq accesses 115system.l2c.ReadReq_miss_rate::cpu.data 0.248232 # miss rate for ReadReq accesses 116system.l2c.ReadReq_miss_rate::total 0.135728 # miss rate for ReadReq accesses 117system.l2c.UpgradeReq_miss_rate::cpu.data 0.583333 # miss rate for UpgradeReq accesses 118system.l2c.UpgradeReq_miss_rate::total 0.583333 # miss rate for UpgradeReq accesses 119system.l2c.ReadExReq_miss_rate::cpu.data 0.383078 # miss rate for ReadExReq accesses 120system.l2c.ReadExReq_miss_rate::total 0.383078 # miss rate for ReadExReq accesses 121system.l2c.demand_miss_rate::cpu.inst 0.014738 # miss rate for demand accesses 122system.l2c.demand_miss_rate::cpu.data 0.277146 # miss rate for demand accesses 123system.l2c.demand_miss_rate::total 0.166377 # miss rate for demand accesses 124system.l2c.overall_miss_rate::cpu.inst 0.014738 # miss rate for overall accesses 125system.l2c.overall_miss_rate::cpu.data 0.277146 # miss rate for overall accesses 126system.l2c.overall_miss_rate::total 0.166377 # miss rate for overall accesses 127system.l2c.ReadReq_avg_miss_latency::cpu.inst 53296.732240 # average ReadReq miss latency 128system.l2c.ReadReq_avg_miss_latency::cpu.data 52075.900601 # average ReadReq miss latency 129system.l2c.ReadReq_avg_miss_latency::total 52139.772213 # average ReadReq miss latency 130system.l2c.UpgradeReq_avg_miss_latency::cpu.data 10234.693878 # average UpgradeReq miss latency 131system.l2c.UpgradeReq_avg_miss_latency::total 10234.693878 # average UpgradeReq miss latency 132system.l2c.ReadExReq_avg_miss_latency::cpu.data 53666.473030 # average ReadExReq miss latency 133system.l2c.ReadExReq_avg_miss_latency::total 53666.473030 # average ReadExReq miss latency 134system.l2c.demand_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency 135system.l2c.demand_avg_miss_latency::cpu.data 52547.321786 # average overall miss latency 136system.l2c.demand_avg_miss_latency::total 52575.343470 # average overall miss latency 137system.l2c.overall_avg_miss_latency::cpu.inst 53296.732240 # average overall miss latency 138system.l2c.overall_avg_miss_latency::cpu.data 52547.321786 # average overall miss latency 139system.l2c.overall_avg_miss_latency::total 52575.343470 # average overall miss latency |
| 140system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 141system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 142system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 143system.l2c.blocked::no_targets 0 # number of cycles access was blocked 144system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 145system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146system.l2c.fast_writes 0 # number of fast writes performed 147system.l2c.cache_copies 0 # number of cache copies performed | 140system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 141system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 142system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 143system.l2c.blocked::no_targets 0 # number of cycles access was blocked 144system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 145system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146system.l2c.fast_writes 0 # number of fast writes performed 147system.l2c.cache_copies 0 # number of cache copies performed |
| 148system.l2c.writebacks::writebacks 76064 # number of writebacks 149system.l2c.writebacks::total 76064 # number of writebacks | 148system.l2c.writebacks::writebacks 75940 # number of writebacks 149system.l2c.writebacks::total 75940 # number of writebacks |
| 150system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 151system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 152system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 153system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 154system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 155system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits | 150system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 151system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 152system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 153system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 154system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 155system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 156system.l2c.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses 157system.l2c.ReadReq_mshr_misses::cpu.data 273879 # number of ReadReq MSHR misses 158system.l2c.ReadReq_mshr_misses::total 289022 # number of ReadReq MSHR misses 159system.l2c.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses 160system.l2c.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses 161system.l2c.ReadExReq_mshr_misses::cpu.data 115423 # number of ReadExReq MSHR misses 162system.l2c.ReadExReq_mshr_misses::total 115423 # number of ReadExReq MSHR misses 163system.l2c.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses 164system.l2c.demand_mshr_misses::cpu.data 389302 # number of demand (read+write) MSHR misses 165system.l2c.demand_mshr_misses::total 404445 # number of demand (read+write) MSHR misses 166system.l2c.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses 167system.l2c.overall_mshr_misses::cpu.data 389302 # number of overall MSHR misses 168system.l2c.overall_mshr_misses::total 404445 # number of overall MSHR misses 169system.l2c.ReadReq_mshr_miss_latency::cpu.inst 606782500 # number of ReadReq MSHR miss cycles 170system.l2c.ReadReq_mshr_miss_latency::cpu.data 10958767000 # number of ReadReq MSHR miss cycles 171system.l2c.ReadReq_mshr_miss_latency::total 11565549500 # number of ReadReq MSHR miss cycles 172system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1142000 # number of UpgradeReq MSHR miss cycles 173system.l2c.UpgradeReq_mshr_miss_latency::total 1142000 # number of UpgradeReq MSHR miss cycles 174system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4653345000 # number of ReadExReq MSHR miss cycles 175system.l2c.ReadExReq_mshr_miss_latency::total 4653345000 # number of ReadExReq MSHR miss cycles 176system.l2c.demand_mshr_miss_latency::cpu.inst 606782500 # number of demand (read+write) MSHR miss cycles 177system.l2c.demand_mshr_miss_latency::cpu.data 15612112000 # number of demand (read+write) MSHR miss cycles 178system.l2c.demand_mshr_miss_latency::total 16218894500 # number of demand (read+write) MSHR miss cycles 179system.l2c.overall_mshr_miss_latency::cpu.inst 606782500 # number of overall MSHR miss cycles 180system.l2c.overall_mshr_miss_latency::cpu.data 15612112000 # number of overall MSHR miss cycles 181system.l2c.overall_mshr_miss_latency::total 16218894500 # number of overall MSHR miss cycles 182system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810071000 # number of ReadReq MSHR uncacheable cycles 183system.l2c.ReadReq_mshr_uncacheable_latency::total 810071000 # number of ReadReq MSHR uncacheable cycles 184system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114787998 # number of WriteReq MSHR uncacheable cycles 185system.l2c.WriteReq_mshr_uncacheable_latency::total 1114787998 # number of WriteReq MSHR uncacheable cycles 186system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924858998 # number of overall MSHR uncacheable cycles 187system.l2c.overall_mshr_uncacheable_latency::total 1924858998 # number of overall MSHR uncacheable cycles 188system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for ReadReq accesses 189system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248824 # mshr miss rate for ReadReq accesses 190system.l2c.ReadReq_mshr_miss_rate::total 0.136188 # mshr miss rate for ReadReq accesses 191system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.642857 # mshr miss rate for UpgradeReq accesses 192system.l2c.UpgradeReq_mshr_miss_rate::total 0.642857 # mshr miss rate for UpgradeReq accesses 193system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383575 # mshr miss rate for ReadExReq accesses 194system.l2c.ReadExReq_mshr_miss_rate::total 0.383575 # mshr miss rate for ReadExReq accesses 195system.l2c.demand_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for demand accesses 196system.l2c.demand_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for demand accesses 197system.l2c.demand_mshr_miss_rate::total 0.166910 # mshr miss rate for demand accesses 198system.l2c.overall_mshr_miss_rate::cpu.inst 0.014824 # mshr miss rate for overall accesses 199system.l2c.overall_mshr_miss_rate::cpu.data 0.277754 # mshr miss rate for overall accesses 200system.l2c.overall_mshr_miss_rate::total 0.166910 # mshr miss rate for overall accesses 201system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40070.164432 # average ReadReq mshr miss latency 202system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40013.170050 # average ReadReq mshr miss latency 203system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.156210 # average ReadReq mshr miss latency 204system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42296.296296 # average UpgradeReq mshr miss latency 205system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42296.296296 # average UpgradeReq mshr miss latency 206system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40315.578351 # average ReadExReq mshr miss latency 207system.l2c.ReadExReq_avg_mshr_miss_latency::total 40315.578351 # average ReadExReq mshr miss latency 208system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency 209system.l2c.demand_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency 210system.l2c.demand_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency 211system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40070.164432 # average overall mshr miss latency 212system.l2c.overall_avg_mshr_miss_latency::cpu.data 40102.830194 # average overall mshr miss latency 213system.l2c.overall_avg_mshr_miss_latency::total 40101.607141 # average overall mshr miss latency | 156system.l2c.ReadReq_mshr_misses::cpu.inst 15117 # number of ReadReq MSHR misses 157system.l2c.ReadReq_mshr_misses::cpu.data 273845 # number of ReadReq MSHR misses 158system.l2c.ReadReq_mshr_misses::total 288962 # number of ReadReq MSHR misses 159system.l2c.UpgradeReq_mshr_misses::cpu.data 49 # number of UpgradeReq MSHR misses 160system.l2c.UpgradeReq_mshr_misses::total 49 # number of UpgradeReq MSHR misses 161system.l2c.ReadExReq_mshr_misses::cpu.data 115352 # number of ReadExReq MSHR misses 162system.l2c.ReadExReq_mshr_misses::total 115352 # number of ReadExReq MSHR misses 163system.l2c.demand_mshr_misses::cpu.inst 15117 # number of demand (read+write) MSHR misses 164system.l2c.demand_mshr_misses::cpu.data 389197 # number of demand (read+write) MSHR misses 165system.l2c.demand_mshr_misses::total 404314 # number of demand (read+write) MSHR misses 166system.l2c.overall_mshr_misses::cpu.inst 15117 # number of overall MSHR misses 167system.l2c.overall_mshr_misses::cpu.data 389197 # number of overall MSHR misses 168system.l2c.overall_mshr_misses::total 404314 # number of overall MSHR misses 169system.l2c.ReadReq_mshr_miss_latency::cpu.inst 620965998 # number of ReadReq MSHR miss cycles 170system.l2c.ReadReq_mshr_miss_latency::cpu.data 10975082500 # number of ReadReq MSHR miss cycles 171system.l2c.ReadReq_mshr_miss_latency::total 11596048498 # number of ReadReq MSHR miss cycles 172system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 2065000 # number of UpgradeReq MSHR miss cycles 173system.l2c.UpgradeReq_mshr_miss_latency::total 2065000 # number of UpgradeReq MSHR miss cycles 174system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4796966997 # number of ReadExReq MSHR miss cycles 175system.l2c.ReadExReq_mshr_miss_latency::total 4796966997 # number of ReadExReq MSHR miss cycles 176system.l2c.demand_mshr_miss_latency::cpu.inst 620965998 # number of demand (read+write) MSHR miss cycles 177system.l2c.demand_mshr_miss_latency::cpu.data 15772049497 # number of demand (read+write) MSHR miss cycles 178system.l2c.demand_mshr_miss_latency::total 16393015495 # number of demand (read+write) MSHR miss cycles 179system.l2c.overall_mshr_miss_latency::cpu.inst 620965998 # number of overall MSHR miss cycles 180system.l2c.overall_mshr_miss_latency::cpu.data 15772049497 # number of overall MSHR miss cycles 181system.l2c.overall_mshr_miss_latency::total 16393015495 # number of overall MSHR miss cycles 182system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 810224030 # number of ReadReq MSHR uncacheable cycles 183system.l2c.ReadReq_mshr_uncacheable_latency::total 810224030 # number of ReadReq MSHR uncacheable cycles 184system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1103797000 # number of WriteReq MSHR uncacheable cycles 185system.l2c.WriteReq_mshr_uncacheable_latency::total 1103797000 # number of WriteReq MSHR uncacheable cycles 186system.l2c.overall_mshr_uncacheable_latency::cpu.data 1914021030 # number of overall MSHR uncacheable cycles 187system.l2c.overall_mshr_uncacheable_latency::total 1914021030 # number of overall MSHR uncacheable cycles 188system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for ReadReq accesses 189system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.248232 # mshr miss rate for ReadReq accesses 190system.l2c.ReadReq_mshr_miss_rate::total 0.135727 # mshr miss rate for ReadReq accesses 191system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.583333 # mshr miss rate for UpgradeReq accesses 192system.l2c.UpgradeReq_mshr_miss_rate::total 0.583333 # mshr miss rate for UpgradeReq accesses 193system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383078 # mshr miss rate for ReadExReq accesses 194system.l2c.ReadExReq_mshr_miss_rate::total 0.383078 # mshr miss rate for ReadExReq accesses 195system.l2c.demand_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for demand accesses 196system.l2c.demand_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for demand accesses 197system.l2c.demand_mshr_miss_rate::total 0.166377 # mshr miss rate for demand accesses 198system.l2c.overall_mshr_miss_rate::cpu.inst 0.014737 # mshr miss rate for overall accesses 199system.l2c.overall_mshr_miss_rate::cpu.data 0.277146 # mshr miss rate for overall accesses 200system.l2c.overall_mshr_miss_rate::total 0.166377 # mshr miss rate for overall accesses 201system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41077.330026 # average ReadReq mshr miss latency 202system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40077.717322 # average ReadReq mshr miss latency 203system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.011898 # average ReadReq mshr miss latency 204system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average UpgradeReq mshr miss latency 205system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42142.857143 # average UpgradeReq mshr miss latency 206system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.468800 # average ReadExReq mshr miss latency 207system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.468800 # average ReadExReq mshr miss latency 208system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency 209system.l2c.demand_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency 210system.l2c.demand_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency 211system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41077.330026 # average overall mshr miss latency 212system.l2c.overall_avg_mshr_miss_latency::cpu.data 40524.591652 # average overall mshr miss latency 213system.l2c.overall_avg_mshr_miss_latency::total 40545.258129 # average overall mshr miss latency |
| 214system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 215system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 216system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 217system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 218system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 219system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 220system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 221system.iocache.replacements 41685 # number of replacements | 214system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 215system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 216system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 217system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 218system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 219system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 220system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 221system.iocache.replacements 41685 # number of replacements |
| 222system.iocache.tagsinuse 1.268378 # Cycle average of tags in use | 222system.iocache.tagsinuse 1.294799 # Cycle average of tags in use |
| 223system.iocache.total_refs 0 # Total number of references to valid blocks. 224system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 225system.iocache.avg_refs 0 # Average number of references to valid blocks. | 223system.iocache.total_refs 0 # Total number of references to valid blocks. 224system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 225system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 226system.iocache.warmup_cycle 1708338896000 # Cycle when the warmup percentage was hit. 227system.iocache.occ_blocks::tsunami.ide 1.268378 # Average occupied blocks per requestor 228system.iocache.occ_percent::tsunami.ide 0.079274 # Average percentage of cache occupancy 229system.iocache.occ_percent::total 0.079274 # Average percentage of cache occupancy | 226system.iocache.warmup_cycle 1711277767000 # Cycle when the warmup percentage was hit. 227system.iocache.occ_blocks::tsunami.ide 1.294799 # Average occupied blocks per requestor 228system.iocache.occ_percent::tsunami.ide 0.080925 # Average percentage of cache occupancy 229system.iocache.occ_percent::total 0.080925 # Average percentage of cache occupancy |
| 230system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 231system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 232system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 233system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 234system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 235system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 236system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 237system.iocache.overall_misses::total 41725 # number of overall misses | 230system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 231system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 232system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 233system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 234system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 235system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 236system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 237system.iocache.overall_misses::total 41725 # number of overall misses |
| 238system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles 239system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles 240system.iocache.WriteReq_miss_latency::tsunami.ide 5721900806 # number of WriteReq miss cycles 241system.iocache.WriteReq_miss_latency::total 5721900806 # number of WriteReq miss cycles 242system.iocache.demand_miss_latency::tsunami.ide 5741838804 # number of demand (read+write) miss cycles 243system.iocache.demand_miss_latency::total 5741838804 # number of demand (read+write) miss cycles 244system.iocache.overall_miss_latency::tsunami.ide 5741838804 # number of overall miss cycles 245system.iocache.overall_miss_latency::total 5741838804 # number of overall miss cycles | 238system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 239system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles 240system.iocache.WriteReq_miss_latency::tsunami.ide 7641897806 # number of WriteReq miss cycles 241system.iocache.WriteReq_miss_latency::total 7641897806 # number of WriteReq miss cycles 242system.iocache.demand_miss_latency::tsunami.ide 7662570804 # number of demand (read+write) miss cycles 243system.iocache.demand_miss_latency::total 7662570804 # number of demand (read+write) miss cycles 244system.iocache.overall_miss_latency::tsunami.ide 7662570804 # number of overall miss cycles 245system.iocache.overall_miss_latency::total 7662570804 # number of overall miss cycles |
| 246system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 247system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 248system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 249system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 250system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 251system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 252system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 253system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 254system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 255system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 256system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 257system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 258system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 259system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 260system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 261system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 246system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 247system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 248system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 249system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 250system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 251system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 252system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 253system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 254system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 255system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 256system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 257system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 258system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 259system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 260system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 261system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 262system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency 263system.iocache.ReadReq_avg_miss_latency::total 115248.543353 # average ReadReq miss latency 264system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.582355 # average WriteReq miss latency 265system.iocache.WriteReq_avg_miss_latency::total 137704.582355 # average WriteReq miss latency 266system.iocache.demand_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency 267system.iocache.demand_avg_miss_latency::total 137611.475231 # average overall miss latency 268system.iocache.overall_avg_miss_latency::tsunami.ide 137611.475231 # average overall miss latency 269system.iocache.overall_avg_miss_latency::total 137611.475231 # average overall miss latency 270system.iocache.blocked_cycles::no_mshrs 64649068 # number of cycles access was blocked | 262system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 263system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency 264system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183911.672266 # average WriteReq miss latency 265system.iocache.WriteReq_avg_miss_latency::total 183911.672266 # average WriteReq miss latency 266system.iocache.demand_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency 267system.iocache.demand_avg_miss_latency::total 183644.596860 # average overall miss latency 268system.iocache.overall_avg_miss_latency::tsunami.ide 183644.596860 # average overall miss latency 269system.iocache.overall_avg_miss_latency::total 183644.596860 # average overall miss latency 270system.iocache.blocked_cycles::no_mshrs 7656000 # number of cycles access was blocked |
| 271system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 271system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 272system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked | 272system.iocache.blocked::no_mshrs 7143 # number of cycles access was blocked |
| 273system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 273system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 274system.iocache.avg_blocked_cycles::no_mshrs 6171.159603 # average number of cycles each access was blocked | 274system.iocache.avg_blocked_cycles::no_mshrs 1071.818564 # average number of cycles each access was blocked |
| 275system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 276system.iocache.fast_writes 0 # number of fast writes performed 277system.iocache.cache_copies 0 # number of cache copies performed 278system.iocache.writebacks::writebacks 41512 # number of writebacks 279system.iocache.writebacks::total 41512 # number of writebacks 280system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 281system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 282system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 283system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 284system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 285system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 286system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 287system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 275system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 276system.iocache.fast_writes 0 # number of fast writes performed 277system.iocache.cache_copies 0 # number of cache copies performed 278system.iocache.writebacks::writebacks 41512 # number of writebacks 279system.iocache.writebacks::total 41512 # number of writebacks 280system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 281system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 282system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 283system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 284system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 285system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 286system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 287system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 288system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles 289system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles 290system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561047996 # number of WriteReq MSHR miss cycles 291system.iocache.WriteReq_mshr_miss_latency::total 3561047996 # number of WriteReq MSHR miss cycles 292system.iocache.demand_mshr_miss_latency::tsunami.ide 3571989994 # number of demand (read+write) MSHR miss cycles 293system.iocache.demand_mshr_miss_latency::total 3571989994 # number of demand (read+write) MSHR miss cycles 294system.iocache.overall_mshr_miss_latency::tsunami.ide 3571989994 # number of overall MSHR miss cycles 295system.iocache.overall_mshr_miss_latency::total 3571989994 # number of overall MSHR miss cycles | 288system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 289system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles 290system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5481043992 # number of WriteReq MSHR miss cycles 291system.iocache.WriteReq_mshr_miss_latency::total 5481043992 # number of WriteReq MSHR miss cycles 292system.iocache.demand_mshr_miss_latency::tsunami.ide 5492719992 # number of demand (read+write) MSHR miss cycles 293system.iocache.demand_mshr_miss_latency::total 5492719992 # number of demand (read+write) MSHR miss cycles 294system.iocache.overall_mshr_miss_latency::tsunami.ide 5492719992 # number of overall MSHR miss cycles 295system.iocache.overall_mshr_miss_latency::total 5492719992 # number of overall MSHR miss cycles |
| 296system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 297system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 298system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 299system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 300system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 301system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 302system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 303system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 296system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 297system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 298system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 299system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 300system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 301system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 302system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 303system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 304system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency 305system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353 # average ReadReq mshr miss latency 306system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85701.001059 # average WriteReq mshr miss latency 307system.iocache.WriteReq_avg_mshr_miss_latency::total 85701.001059 # average WriteReq mshr miss latency 308system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency 309system.iocache.demand_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency 310system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.908784 # average overall mshr miss latency 311system.iocache.overall_avg_mshr_miss_latency::total 85607.908784 # average overall mshr miss latency | 304system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 305system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency 306system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131908.066808 # average WriteReq mshr miss latency 307system.iocache.WriteReq_avg_mshr_miss_latency::total 131908.066808 # average WriteReq mshr miss latency 308system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency 309system.iocache.demand_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency 310system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131640.982433 # average overall mshr miss latency 311system.iocache.overall_avg_mshr_miss_latency::total 131640.982433 # average overall mshr miss latency |
| 312system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 313system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 314system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 315system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 316system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 317system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 318system.disk0.dma_write_txs 395 # Number of DMA write transactions. 319system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 320system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 321system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 322system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 323system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 324system.disk2.dma_write_txs 1 # Number of DMA write transactions. 325system.cpu.dtb.fetch_hits 0 # ITB hits 326system.cpu.dtb.fetch_misses 0 # ITB misses 327system.cpu.dtb.fetch_acv 0 # ITB acv 328system.cpu.dtb.fetch_accesses 0 # ITB accesses | 312system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 313system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 314system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 315system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 316system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 317system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 318system.disk0.dma_write_txs 395 # Number of DMA write transactions. 319system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 320system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 321system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 322system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 323system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 324system.disk2.dma_write_txs 1 # Number of DMA write transactions. 325system.cpu.dtb.fetch_hits 0 # ITB hits 326system.cpu.dtb.fetch_misses 0 # ITB misses 327system.cpu.dtb.fetch_acv 0 # ITB acv 328system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 329system.cpu.dtb.read_hits 9957395 # DTB read hits 330system.cpu.dtb.read_misses 44300 # DTB read misses 331system.cpu.dtb.read_acv 564 # DTB read access violations 332system.cpu.dtb.read_accesses 948872 # DTB read accesses 333system.cpu.dtb.write_hits 6634412 # DTB write hits 334system.cpu.dtb.write_misses 10394 # DTB write misses 335system.cpu.dtb.write_acv 384 # DTB write access violations 336system.cpu.dtb.write_accesses 338929 # DTB write accesses 337system.cpu.dtb.data_hits 16591807 # DTB hits 338system.cpu.dtb.data_misses 54694 # DTB misses 339system.cpu.dtb.data_acv 948 # DTB access violations 340system.cpu.dtb.data_accesses 1287801 # DTB accesses 341system.cpu.itb.fetch_hits 1332166 # ITB hits 342system.cpu.itb.fetch_misses 40283 # ITB misses 343system.cpu.itb.fetch_acv 1114 # ITB acv 344system.cpu.itb.fetch_accesses 1372449 # ITB accesses | 329system.cpu.dtb.read_hits 9972402 # DTB read hits 330system.cpu.dtb.read_misses 43929 # DTB read misses 331system.cpu.dtb.read_acv 494 # DTB read access violations 332system.cpu.dtb.read_accesses 957886 # DTB read accesses 333system.cpu.dtb.write_hits 6649938 # DTB write hits 334system.cpu.dtb.write_misses 10071 # DTB write misses 335system.cpu.dtb.write_acv 391 # DTB write access violations 336system.cpu.dtb.write_accesses 340693 # DTB write accesses 337system.cpu.dtb.data_hits 16622340 # DTB hits 338system.cpu.dtb.data_misses 54000 # DTB misses 339system.cpu.dtb.data_acv 885 # DTB access violations 340system.cpu.dtb.data_accesses 1298579 # DTB accesses 341system.cpu.itb.fetch_hits 1343669 # ITB hits 342system.cpu.itb.fetch_misses 37345 # ITB misses 343system.cpu.itb.fetch_acv 1146 # ITB acv 344system.cpu.itb.fetch_accesses 1381014 # ITB accesses |
| 345system.cpu.itb.read_hits 0 # DTB read hits 346system.cpu.itb.read_misses 0 # DTB read misses 347system.cpu.itb.read_acv 0 # DTB read access violations 348system.cpu.itb.read_accesses 0 # DTB read accesses 349system.cpu.itb.write_hits 0 # DTB write hits 350system.cpu.itb.write_misses 0 # DTB write misses 351system.cpu.itb.write_acv 0 # DTB write access violations 352system.cpu.itb.write_accesses 0 # DTB write accesses 353system.cpu.itb.data_hits 0 # DTB hits 354system.cpu.itb.data_misses 0 # DTB misses 355system.cpu.itb.data_acv 0 # DTB access violations 356system.cpu.itb.data_accesses 0 # DTB accesses | 345system.cpu.itb.read_hits 0 # DTB read hits 346system.cpu.itb.read_misses 0 # DTB read misses 347system.cpu.itb.read_acv 0 # DTB read access violations 348system.cpu.itb.read_accesses 0 # DTB read accesses 349system.cpu.itb.write_hits 0 # DTB write hits 350system.cpu.itb.write_misses 0 # DTB write misses 351system.cpu.itb.write_acv 0 # DTB write access violations 352system.cpu.itb.write_accesses 0 # DTB write accesses 353system.cpu.itb.data_hits 0 # DTB hits 354system.cpu.itb.data_misses 0 # DTB misses 355system.cpu.itb.data_acv 0 # DTB access violations 356system.cpu.itb.data_accesses 0 # DTB accesses |
| 357system.cpu.numCycles 114963877 # number of cpu cycles simulated | 357system.cpu.numCycles 122571263 # number of cpu cycles simulated |
| 358system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 359system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 358system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 359system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 360system.cpu.BPredUnit.lookups 13985774 # Number of BP lookups 361system.cpu.BPredUnit.condPredicted 11671873 # Number of conditional branches predicted 362system.cpu.BPredUnit.condIncorrect 444413 # Number of conditional branches incorrect 363system.cpu.BPredUnit.BTBLookups 10112209 # Number of BTB lookups 364system.cpu.BPredUnit.BTBHits 5892039 # Number of BTB hits | 360system.cpu.BPredUnit.lookups 14075987 # Number of BP lookups 361system.cpu.BPredUnit.condPredicted 11741614 # Number of conditional branches predicted 362system.cpu.BPredUnit.condIncorrect 452517 # Number of conditional branches incorrect 363system.cpu.BPredUnit.BTBLookups 10126525 # Number of BTB lookups 364system.cpu.BPredUnit.BTBHits 5926302 # Number of BTB hits |
| 365system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 365system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 366system.cpu.BPredUnit.usedRAS 933191 # Number of times the RAS was used to get a target. 367system.cpu.BPredUnit.RASInCorrect 42453 # Number of incorrect RAS predictions. 368system.cpu.fetch.icacheStallCycles 29251616 # Number of cycles fetch is stalled on an Icache miss 369system.cpu.fetch.Insts 71181997 # Number of instructions fetch has processed 370system.cpu.fetch.Branches 13985774 # Number of branches that fetch encountered 371system.cpu.fetch.predictedBranches 6825230 # Number of branches that fetch has predicted taken 372system.cpu.fetch.Cycles 13396576 # Number of cycles fetch has run and was not squashing or blocked 373system.cpu.fetch.SquashCycles 2069716 # Number of cycles fetch has spent squashing 374system.cpu.fetch.BlockedCycles 36268090 # Number of cycles fetch has spent blocked 375system.cpu.fetch.MiscStallCycles 34293 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 376system.cpu.fetch.PendingTrapStallCycles 258776 # Number of stall cycles due to pending traps 377system.cpu.fetch.PendingQuiesceStallCycles 311439 # Number of stall cycles due to pending quiesce instructions 378system.cpu.fetch.IcacheWaitRetryStallCycles 136 # Number of stall cycles due to full MSHR 379system.cpu.fetch.CacheLines 8761444 # Number of cache lines fetched 380system.cpu.fetch.IcacheSquashes 288106 # Number of outstanding Icache misses that were squashed 381system.cpu.fetch.rateDist::samples 80878220 # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::mean 0.880113 # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::stdev 2.220739 # Number of instructions fetched each cycle (Total) | 366system.cpu.BPredUnit.usedRAS 942334 # Number of times the RAS was used to get a target. 367system.cpu.BPredUnit.RASInCorrect 45003 # Number of incorrect RAS predictions. 368system.cpu.fetch.icacheStallCycles 31564050 # Number of cycles fetch is stalled on an Icache miss 369system.cpu.fetch.Insts 71567580 # Number of instructions fetch has processed 370system.cpu.fetch.Branches 14075987 # Number of branches that fetch encountered 371system.cpu.fetch.predictedBranches 6868636 # Number of branches that fetch has predicted taken 372system.cpu.fetch.Cycles 13486844 # Number of cycles fetch has run and was not squashing or blocked 373system.cpu.fetch.SquashCycles 2151091 # Number of cycles fetch has spent squashing 374system.cpu.fetch.BlockedCycles 41804632 # Number of cycles fetch has spent blocked 375system.cpu.fetch.MiscStallCycles 33708 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 376system.cpu.fetch.PendingTrapStallCycles 276041 # Number of stall cycles due to pending traps 377system.cpu.fetch.PendingQuiesceStallCycles 314295 # Number of stall cycles due to pending quiesce instructions 378system.cpu.fetch.IcacheWaitRetryStallCycles 187 # Number of stall cycles due to full MSHR 379system.cpu.fetch.CacheLines 8859322 # Number of cache lines fetched 380system.cpu.fetch.IcacheSquashes 305645 # Number of outstanding Icache misses that were squashed 381system.cpu.fetch.rateDist::samples 88896899 # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::mean 0.805063 # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::stdev 2.137281 # Number of instructions fetched each cycle (Total) |
| 384system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 384system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 385system.cpu.fetch.rateDist::0 67481644 83.44% 83.44% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::1 875531 1.08% 84.52% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::2 1743396 2.16% 86.67% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::3 848384 1.05% 87.72% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::4 2751006 3.40% 91.12% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::5 598052 0.74% 91.86% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::6 674963 0.83% 92.70% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::7 1011492 1.25% 93.95% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::8 4893752 6.05% 100.00% # Number of instructions fetched each cycle (Total) | 385system.cpu.fetch.rateDist::0 75410055 84.83% 84.83% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::1 885656 1.00% 85.82% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::2 1762066 1.98% 87.81% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::3 856601 0.96% 88.77% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::4 2772547 3.12% 91.89% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::5 605003 0.68% 92.57% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::6 676052 0.76% 93.33% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::7 1014878 1.14% 94.47% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::8 4914041 5.53% 100.00% # Number of instructions fetched each cycle (Total) |
| 394system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 394system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 397system.cpu.fetch.rateDist::total 80878220 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.branchRate 0.121654 # Number of branch fetches per cycle 399system.cpu.fetch.rate 0.619168 # Number of inst fetches per cycle 400system.cpu.decode.IdleCycles 30302953 # Number of cycles decode is idle 401system.cpu.decode.BlockedCycles 36036206 # Number of cycles decode is blocked 402system.cpu.decode.RunCycles 12267887 # Number of cycles decode is running 403system.cpu.decode.UnblockCycles 956730 # Number of cycles decode is unblocking 404system.cpu.decode.SquashCycles 1314443 # Number of cycles decode is squashing 405system.cpu.decode.BranchResolved 612620 # Number of times decode resolved a branch 406system.cpu.decode.BranchMispred 43298 # Number of times decode detected a branch misprediction 407system.cpu.decode.DecodedInsts 69919175 # Number of instructions handled by decode 408system.cpu.decode.SquashedInsts 129721 # Number of squashed instructions handled by decode 409system.cpu.rename.SquashCycles 1314443 # Number of cycles rename is squashing 410system.cpu.rename.IdleCycles 31429322 # Number of cycles rename is idle 411system.cpu.rename.BlockCycles 12715444 # Number of cycles rename is blocking 412system.cpu.rename.serializeStallCycles 19630106 # count of cycles rename stalled for serializing inst 413system.cpu.rename.RunCycles 11479703 # Number of cycles rename is running 414system.cpu.rename.UnblockCycles 4309200 # Number of cycles rename is unblocking 415system.cpu.rename.RenamedInsts 66239771 # Number of instructions processed by rename 416system.cpu.rename.ROBFullEvents 6813 # Number of times rename has blocked due to ROB full 417system.cpu.rename.IQFullEvents 505927 # Number of times rename has blocked due to IQ full 418system.cpu.rename.LSQFullEvents 1528052 # Number of times rename has blocked due to LSQ full 419system.cpu.rename.RenamedOperands 44253229 # Number of destination operands rename has renamed 420system.cpu.rename.RenameLookups 80320067 # Number of register rename lookups that rename has made 421system.cpu.rename.int_rename_lookups 79838854 # Number of integer rename lookups 422system.cpu.rename.fp_rename_lookups 481213 # Number of floating rename lookups 423system.cpu.rename.CommittedMaps 38235996 # Number of HB maps that are committed 424system.cpu.rename.UndoneMaps 6017225 # Number of HB maps that are undone due to squashing 425system.cpu.rename.serializingInsts 1699905 # count of serializing insts renamed 426system.cpu.rename.tempSerializingInsts 247549 # count of temporary serializing insts renamed 427system.cpu.rename.skidInsts 12108783 # count of insts added to the skid buffer 428system.cpu.memDep0.insertedLoads 10535735 # Number of loads inserted to the mem dependence unit. 429system.cpu.memDep0.insertedStores 6944708 # Number of stores inserted to the mem dependence unit. 430system.cpu.memDep0.conflictingLoads 1299665 # Number of conflicting loads. 431system.cpu.memDep0.conflictingStores 826518 # Number of conflicting stores. 432system.cpu.iq.iqInstsAdded 58678192 # Number of instructions added to the IQ (excludes non-spec) 433system.cpu.iq.iqNonSpecInstsAdded 2085341 # Number of non-speculative instructions added to the IQ 434system.cpu.iq.iqInstsIssued 57178934 # Number of instructions issued 435system.cpu.iq.iqSquashedInstsIssued 114167 # Number of squashed instructions issued 436system.cpu.iq.iqSquashedInstsExamined 7323387 # Number of squashed instructions iterated over during squash; mainly for profiling 437system.cpu.iq.iqSquashedOperandsExamined 3670404 # Number of squashed operands that are examined and possibly removed from graph 438system.cpu.iq.iqSquashedNonSpecRemoved 1417353 # Number of squashed non-spec instructions that were removed 439system.cpu.iq.issued_per_cycle::samples 80878220 # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::mean 0.706976 # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::stdev 1.364710 # Number of insts issued each cycle | 397system.cpu.fetch.rateDist::total 88896899 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.branchRate 0.114839 # Number of branch fetches per cycle 399system.cpu.fetch.rate 0.583885 # Number of inst fetches per cycle 400system.cpu.decode.IdleCycles 32604567 # Number of cycles decode is idle 401system.cpu.decode.BlockedCycles 41610698 # Number of cycles decode is blocked 402system.cpu.decode.RunCycles 12250426 # Number of cycles decode is running 403system.cpu.decode.UnblockCycles 1057078 # Number of cycles decode is unblocking 404system.cpu.decode.SquashCycles 1374129 # Number of cycles decode is squashing 405system.cpu.decode.BranchResolved 617310 # Number of times decode resolved a branch 406system.cpu.decode.BranchMispred 43428 # Number of times decode detected a branch misprediction 407system.cpu.decode.DecodedInsts 70293890 # Number of instructions handled by decode 408system.cpu.decode.SquashedInsts 133239 # Number of squashed instructions handled by decode 409system.cpu.rename.SquashCycles 1374129 # Number of cycles rename is squashing 410system.cpu.rename.IdleCycles 33752767 # Number of cycles rename is idle 411system.cpu.rename.BlockCycles 16324711 # Number of cycles rename is blocking 412system.cpu.rename.serializeStallCycles 21058224 # count of cycles rename stalled for serializing inst 413system.cpu.rename.RunCycles 11548980 # Number of cycles rename is running 414system.cpu.rename.UnblockCycles 4838086 # Number of cycles rename is unblocking 415system.cpu.rename.RenamedInsts 66572257 # Number of instructions processed by rename 416system.cpu.rename.ROBFullEvents 7187 # Number of times rename has blocked due to ROB full 417system.cpu.rename.IQFullEvents 753146 # Number of times rename has blocked due to IQ full 418system.cpu.rename.LSQFullEvents 1801877 # Number of times rename has blocked due to LSQ full 419system.cpu.rename.RenamedOperands 44498273 # Number of destination operands rename has renamed 420system.cpu.rename.RenameLookups 80714962 # Number of register rename lookups that rename has made 421system.cpu.rename.int_rename_lookups 80226097 # Number of integer rename lookups 422system.cpu.rename.fp_rename_lookups 488865 # Number of floating rename lookups 423system.cpu.rename.CommittedMaps 38261328 # Number of HB maps that are committed 424system.cpu.rename.UndoneMaps 6236937 # Number of HB maps that are undone due to squashing 425system.cpu.rename.serializingInsts 1703640 # count of serializing insts renamed 426system.cpu.rename.tempSerializingInsts 251709 # count of temporary serializing insts renamed 427system.cpu.rename.skidInsts 12757763 # count of insts added to the skid buffer 428system.cpu.memDep0.insertedLoads 10570492 # Number of loads inserted to the mem dependence unit. 429system.cpu.memDep0.insertedStores 6981683 # Number of stores inserted to the mem dependence unit. 430system.cpu.memDep0.conflictingLoads 1316603 # Number of conflicting loads. 431system.cpu.memDep0.conflictingStores 922104 # Number of conflicting stores. 432system.cpu.iq.iqInstsAdded 58981346 # Number of instructions added to the IQ (excludes non-spec) 433system.cpu.iq.iqNonSpecInstsAdded 2097651 # Number of non-speculative instructions added to the IQ 434system.cpu.iq.iqInstsIssued 57326676 # Number of instructions issued 435system.cpu.iq.iqSquashedInstsIssued 120953 # Number of squashed instructions issued 436system.cpu.iq.iqSquashedInstsExamined 7579711 # Number of squashed instructions iterated over during squash; mainly for profiling 437system.cpu.iq.iqSquashedOperandsExamined 3887654 # Number of squashed operands that are examined and possibly removed from graph 438system.cpu.iq.iqSquashedNonSpecRemoved 1429592 # Number of squashed non-spec instructions that were removed 439system.cpu.iq.issued_per_cycle::samples 88896899 # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::mean 0.644867 # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::stdev 1.291957 # Number of insts issued each cycle |
| 442system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 442system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 443system.cpu.iq.issued_per_cycle::0 55943146 69.17% 69.17% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::1 11029219 13.64% 82.81% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::2 5183069 6.41% 89.21% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::3 3467547 4.29% 93.50% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::4 2613614 3.23% 96.73% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::5 1475312 1.82% 98.56% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::6 724581 0.90% 99.45% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::7 331422 0.41% 99.86% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::8 110310 0.14% 100.00% # Number of insts issued each cycle | 443system.cpu.iq.issued_per_cycle::0 62967728 70.83% 70.83% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::1 12048856 13.55% 84.39% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::2 5390899 6.06% 90.45% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::3 3449544 3.88% 94.33% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::4 2613461 2.94% 97.27% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::5 1329807 1.50% 98.77% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::6 686975 0.77% 99.54% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::7 354371 0.40% 99.94% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::8 55258 0.06% 100.00% # Number of insts issued each cycle |
| 452system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 452system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 455system.cpu.iq.issued_per_cycle::total 80878220 # Number of insts issued each cycle | 455system.cpu.iq.issued_per_cycle::total 88896899 # Number of insts issued each cycle |
| 456system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 456system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 457system.cpu.iq.fu_full::IntAlu 90406 11.39% 11.39% # attempts to use FU when none available 458system.cpu.iq.fu_full::IntMult 0 0.00% 11.39% # attempts to use FU when none available 459system.cpu.iq.fu_full::IntDiv 0 0.00% 11.39% # attempts to use FU when none available 460system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.39% # attempts to use FU when none available 461system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.39% # attempts to use FU when none available 462system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.39% # attempts to use FU when none available 463system.cpu.iq.fu_full::FloatMult 0 0.00% 11.39% # attempts to use FU when none available 464system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.39% # attempts to use FU when none available 465system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.39% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.39% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.39% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.39% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.39% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.39% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.39% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdMult 0 0.00% 11.39% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.39% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdShift 0 0.00% 11.39% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.39% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.39% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.39% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.39% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.39% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.39% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.39% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.39% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.39% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.39% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.39% # attempts to use FU when none available 486system.cpu.iq.fu_full::MemRead 375907 47.36% 58.75% # attempts to use FU when none available 487system.cpu.iq.fu_full::MemWrite 327352 41.25% 100.00% # attempts to use FU when none available | 457system.cpu.iq.fu_full::IntAlu 75491 10.00% 10.00% # attempts to use FU when none available 458system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available 459system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available 460system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available 461system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available 462system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available 463system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available 464system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available 486system.cpu.iq.fu_full::MemRead 363771 48.19% 58.19% # attempts to use FU when none available 487system.cpu.iq.fu_full::MemWrite 315594 41.81% 100.00% # attempts to use FU when none available |
| 488system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 489system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 488system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 489system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 490system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued 491system.cpu.iq.FU_type_0::IntAlu 39009688 68.22% 68.24% # Type of FU issued 492system.cpu.iq.FU_type_0::IntMult 61923 0.11% 68.34% # Type of FU issued 493system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued 494system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.39% # Type of FU issued 495system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued 496system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued 497system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued 498system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued 499system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued 520system.cpu.iq.FU_type_0::MemRead 10404436 18.20% 86.59% # Type of FU issued 521system.cpu.iq.FU_type_0::MemWrite 6713568 11.74% 98.33% # Type of FU issued 522system.cpu.iq.FU_type_0::IprAccess 952795 1.67% 100.00% # Type of FU issued | 490system.cpu.iq.FU_type_0::No_OpClass 7291 0.01% 0.01% # Type of FU issued 491system.cpu.iq.FU_type_0::IntAlu 39127581 68.25% 68.27% # Type of FU issued 492system.cpu.iq.FU_type_0::IntMult 61956 0.11% 68.37% # Type of FU issued 493system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.37% # Type of FU issued 494system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.42% # Type of FU issued 495system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued 496system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued 497system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued 498system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.43% # Type of FU issued 499system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued 520system.cpu.iq.FU_type_0::MemRead 10418296 18.17% 86.60% # Type of FU issued 521system.cpu.iq.FU_type_0::MemWrite 6729507 11.74% 98.34% # Type of FU issued 522system.cpu.iq.FU_type_0::IprAccess 952802 1.66% 100.00% # Type of FU issued |
| 523system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 523system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 524system.cpu.iq.FU_type_0::total 57178934 # Type of FU issued 525system.cpu.iq.rate 0.497364 # Inst issue rate 526system.cpu.iq.fu_busy_cnt 793665 # FU busy when requested 527system.cpu.iq.fu_busy_rate 0.013880 # FU busy rate (busy events/executed inst) 528system.cpu.iq.int_inst_queue_reads 195448703 # Number of integer instruction queue reads 529system.cpu.iq.int_inst_queue_writes 67761433 # Number of integer instruction queue writes 530system.cpu.iq.int_inst_queue_wakeup_accesses 55894957 # Number of integer instruction queue wakeup accesses 531system.cpu.iq.fp_inst_queue_reads 695216 # Number of floating instruction queue reads 532system.cpu.iq.fp_inst_queue_writes 339032 # Number of floating instruction queue writes 533system.cpu.iq.fp_inst_queue_wakeup_accesses 327938 # Number of floating instruction queue wakeup accesses 534system.cpu.iq.int_alu_accesses 57602239 # Number of integer alu accesses 535system.cpu.iq.fp_alu_accesses 363079 # Number of floating point alu accesses 536system.cpu.iew.lsq.thread0.forwLoads 589978 # Number of loads that had data forwarded from stores | 524system.cpu.iq.FU_type_0::total 57326676 # Type of FU issued 525system.cpu.iq.rate 0.467701 # Inst issue rate 526system.cpu.iq.fu_busy_cnt 754856 # FU busy when requested 527system.cpu.iq.fu_busy_rate 0.013168 # FU busy rate (busy events/executed inst) 528system.cpu.iq.int_inst_queue_reads 203729346 # Number of integer instruction queue reads 529system.cpu.iq.int_inst_queue_writes 68333375 # Number of integer instruction queue writes 530system.cpu.iq.int_inst_queue_wakeup_accesses 56036726 # Number of integer instruction queue wakeup accesses 531system.cpu.iq.fp_inst_queue_reads 696713 # Number of floating instruction queue reads 532system.cpu.iq.fp_inst_queue_writes 339202 # Number of floating instruction queue writes 533system.cpu.iq.fp_inst_queue_wakeup_accesses 327718 # Number of floating instruction queue wakeup accesses 534system.cpu.iq.int_alu_accesses 57709702 # Number of integer alu accesses 535system.cpu.iq.fp_alu_accesses 364539 # Number of floating point alu accesses 536system.cpu.iew.lsq.thread0.forwLoads 594776 # Number of loads that had data forwarded from stores |
| 537system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 537system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 538system.cpu.iew.lsq.thread0.squashedLoads 1427299 # Number of loads squashed 539system.cpu.iew.lsq.thread0.ignoredResponses 3440 # Number of memory responses ignored because the instruction is squashed 540system.cpu.iew.lsq.thread0.memOrderViolation 13878 # Number of memory ordering violations 541system.cpu.iew.lsq.thread0.squashedStores 554882 # Number of stores squashed | 538system.cpu.iew.lsq.thread0.squashedLoads 1456655 # Number of loads squashed 539system.cpu.iew.lsq.thread0.ignoredResponses 2870 # Number of memory responses ignored because the instruction is squashed 540system.cpu.iew.lsq.thread0.memOrderViolation 14252 # Number of memory ordering violations 541system.cpu.iew.lsq.thread0.squashedStores 588832 # Number of stores squashed |
| 542system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 543system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 542system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 543system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 544system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled 545system.cpu.iew.lsq.thread0.cacheBlocked 151980 # Number of times an access to memory failed due to the cache being blocked | 544system.cpu.iew.lsq.thread0.rescheduledLoads 18348 # Number of loads that were rescheduled 545system.cpu.iew.lsq.thread0.cacheBlocked 104302 # Number of times an access to memory failed due to the cache being blocked |
| 546system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 546system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 547system.cpu.iew.iewSquashCycles 1314443 # Number of cycles IEW is squashing 548system.cpu.iew.iewBlockCycles 8887747 # Number of cycles IEW is blocking 549system.cpu.iew.iewUnblockCycles 615033 # Number of cycles IEW is unblocking 550system.cpu.iew.iewDispatchedInsts 64324837 # Number of instructions dispatched to IQ 551system.cpu.iew.iewDispSquashedInsts 661005 # Number of squashed instructions skipped by dispatch 552system.cpu.iew.iewDispLoadInsts 10535735 # Number of dispatched load instructions 553system.cpu.iew.iewDispStoreInsts 6944708 # Number of dispatched store instructions 554system.cpu.iew.iewDispNonSpecInsts 1835122 # Number of dispatched non-speculative instructions 555system.cpu.iew.iewIQFullEvents 481853 # Number of times the IQ has become full, causing a stall 556system.cpu.iew.iewLSQFullEvents 16088 # Number of times the LSQ has become full, causing a stall 557system.cpu.iew.memOrderViolationEvents 13878 # Number of memory order violations 558system.cpu.iew.predictedTakenIncorrect 240769 # Number of branches that were predicted taken incorrectly 559system.cpu.iew.predictedNotTakenIncorrect 420658 # Number of branches that were predicted not taken incorrectly 560system.cpu.iew.branchMispredicts 661427 # Number of branch mispredicts detected at execute 561system.cpu.iew.iewExecutedInsts 56655096 # Number of executed instructions 562system.cpu.iew.iewExecLoadInsts 10030988 # Number of load instructions executed 563system.cpu.iew.iewExecSquashedInsts 523837 # Number of squashed instructions skipped in execute | 547system.cpu.iew.iewSquashCycles 1374129 # Number of cycles IEW is squashing 548system.cpu.iew.iewBlockCycles 11393417 # Number of cycles IEW is blocking 549system.cpu.iew.iewUnblockCycles 869281 # Number of cycles IEW is unblocking 550system.cpu.iew.iewDispatchedInsts 64652535 # Number of instructions dispatched to IQ 551system.cpu.iew.iewDispSquashedInsts 684492 # Number of squashed instructions skipped by dispatch 552system.cpu.iew.iewDispLoadInsts 10570492 # Number of dispatched load instructions 553system.cpu.iew.iewDispStoreInsts 6981683 # Number of dispatched store instructions 554system.cpu.iew.iewDispNonSpecInsts 1845589 # Number of dispatched non-speculative instructions 555system.cpu.iew.iewIQFullEvents 621506 # Number of times the IQ has become full, causing a stall 556system.cpu.iew.iewLSQFullEvents 12714 # Number of times the LSQ has become full, causing a stall 557system.cpu.iew.memOrderViolationEvents 14252 # Number of memory order violations 558system.cpu.iew.predictedTakenIncorrect 241539 # Number of branches that were predicted taken incorrectly 559system.cpu.iew.predictedNotTakenIncorrect 423865 # Number of branches that were predicted not taken incorrectly 560system.cpu.iew.branchMispredicts 665404 # Number of branch mispredicts detected at execute 561system.cpu.iew.iewExecutedInsts 56791406 # Number of executed instructions 562system.cpu.iew.iewExecLoadInsts 10044983 # Number of load instructions executed 563system.cpu.iew.iewExecSquashedInsts 535269 # Number of squashed instructions skipped in execute |
| 564system.cpu.iew.exec_swp 0 # number of swp insts executed | 564system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 565system.cpu.iew.exec_nop 3561304 # number of nop insts executed 566system.cpu.iew.exec_refs 16691010 # number of memory reference insts executed 567system.cpu.iew.exec_branches 8986521 # Number of branches executed 568system.cpu.iew.exec_stores 6660022 # Number of stores executed 569system.cpu.iew.exec_rate 0.492808 # Inst execution rate 570system.cpu.iew.wb_sent 56341255 # cumulative count of insts sent to commit 571system.cpu.iew.wb_count 56222895 # cumulative count of insts written-back 572system.cpu.iew.wb_producers 27828941 # num instructions producing a value 573system.cpu.iew.wb_consumers 37695611 # num instructions consuming a value | 565system.cpu.iew.exec_nop 3573538 # number of nop insts executed 566system.cpu.iew.exec_refs 16720258 # number of memory reference insts executed 567system.cpu.iew.exec_branches 9005988 # Number of branches executed 568system.cpu.iew.exec_stores 6675275 # Number of stores executed 569system.cpu.iew.exec_rate 0.463334 # Inst execution rate 570system.cpu.iew.wb_sent 56476627 # cumulative count of insts sent to commit 571system.cpu.iew.wb_count 56364444 # cumulative count of insts written-back 572system.cpu.iew.wb_producers 27797872 # num instructions producing a value 573system.cpu.iew.wb_consumers 37663953 # num instructions consuming a value |
| 574system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 574system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 575system.cpu.iew.wb_rate 0.489048 # insts written-back per cycle 576system.cpu.iew.wb_fanout 0.738254 # average fanout of values written-back | 575system.cpu.iew.wb_rate 0.459850 # insts written-back per cycle 576system.cpu.iew.wb_fanout 0.738050 # average fanout of values written-back |
| 577system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 577system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 578system.cpu.commit.commitCommittedInsts 56255888 # The number of committed instructions 579system.cpu.commit.commitCommittedOps 56255888 # The number of committed instructions 580system.cpu.commit.commitSquashedInsts 7955379 # The number of squashed insts skipped by commit 581system.cpu.commit.commitNonSpecStalls 667988 # The number of times commit has been forced to stall to communicate backwards 582system.cpu.commit.branchMispredicts 613263 # The number of times a branch was mispredicted 583system.cpu.commit.committed_per_cycle::samples 79563777 # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::mean 0.707054 # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::stdev 1.631051 # Number of insts commited each cycle | 578system.cpu.commit.commitCommittedInsts 56288834 # The number of committed instructions 579system.cpu.commit.commitCommittedOps 56288834 # The number of committed instructions 580system.cpu.commit.commitSquashedInsts 8251602 # The number of squashed insts skipped by commit 581system.cpu.commit.commitNonSpecStalls 668059 # The number of times commit has been forced to stall to communicate backwards 582system.cpu.commit.branchMispredicts 621198 # The number of times a branch was mispredicted 583system.cpu.commit.committed_per_cycle::samples 87522770 # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::mean 0.643134 # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::stdev 1.558246 # Number of insts commited each cycle |
| 586system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 586system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 587system.cpu.commit.committed_per_cycle::0 58612311 73.67% 73.67% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::1 8734565 10.98% 84.65% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::2 4655391 5.85% 90.50% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::3 2574186 3.24% 93.73% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::4 1496332 1.88% 95.61% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::5 659939 0.83% 96.44% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::6 486345 0.61% 97.05% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::7 472774 0.59% 97.65% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::8 1871934 2.35% 100.00% # Number of insts commited each cycle | 587system.cpu.commit.committed_per_cycle::0 66254825 75.70% 75.70% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::1 8962066 10.24% 85.94% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::2 4828588 5.52% 91.46% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::3 2603942 2.98% 94.43% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::4 1449491 1.66% 96.09% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::5 603705 0.69% 96.78% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::6 515511 0.59% 97.37% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::7 488925 0.56% 97.93% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::8 1815717 2.07% 100.00% # Number of insts commited each cycle |
| 596system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 596system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 599system.cpu.commit.committed_per_cycle::total 79563777 # Number of insts commited each cycle 600system.cpu.commit.committedInsts 56255888 # Number of instructions committed 601system.cpu.commit.committedOps 56255888 # Number of ops (including micro ops) committed | 599system.cpu.commit.committed_per_cycle::total 87522770 # Number of insts commited each cycle 600system.cpu.commit.committedInsts 56288834 # Number of instructions committed 601system.cpu.commit.committedOps 56288834 # Number of ops (including micro ops) committed |
| 602system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 602system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 603system.cpu.commit.refs 15498262 # Number of memory references committed 604system.cpu.commit.loads 9108436 # Number of loads committed 605system.cpu.commit.membars 227920 # Number of memory barriers committed 606system.cpu.commit.branches 8459857 # Number of branches committed | 603system.cpu.commit.refs 15506688 # Number of memory references committed 604system.cpu.commit.loads 9113837 # Number of loads committed 605system.cpu.commit.membars 227975 # Number of memory barriers committed 606system.cpu.commit.branches 8463674 # Number of branches committed |
| 607system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 607system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 608system.cpu.commit.int_insts 52095164 # Number of committed integer instructions. 609system.cpu.commit.function_calls 744157 # Number of function calls committed. 610system.cpu.commit.bw_lim_events 1871934 # number cycles where commit BW limit reached | 608system.cpu.commit.int_insts 52126817 # Number of committed integer instructions. 609system.cpu.commit.function_calls 744625 # Number of function calls committed. 610system.cpu.commit.bw_lim_events 1815717 # number cycles where commit BW limit reached |
| 611system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 611system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 612system.cpu.rob.rob_reads 141652037 # The number of ROB reads 613system.cpu.rob.rob_writes 129738562 # The number of ROB writes 614system.cpu.timesIdled 1269768 # Number of times that the entire CPU went into an idle state and unscheduled itself 615system.cpu.idleCycles 34085657 # Total number of cycles that the CPU has spent unscheduled due to idling 616system.cpu.quiesceCycles 3602789251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 617system.cpu.committedInsts 53062487 # Number of Instructions Simulated 618system.cpu.committedOps 53062487 # Number of Ops (including micro ops) Simulated 619system.cpu.committedInsts_total 53062487 # Number of Instructions Simulated 620system.cpu.cpi 2.166575 # CPI: Cycles Per Instruction 621system.cpu.cpi_total 2.166575 # CPI: Total CPI of All Threads 622system.cpu.ipc 0.461558 # IPC: Instructions Per Cycle 623system.cpu.ipc_total 0.461558 # IPC: Total IPC of All Threads 624system.cpu.int_regfile_reads 74266984 # number of integer regfile reads 625system.cpu.int_regfile_writes 40553865 # number of integer regfile writes 626system.cpu.fp_regfile_reads 166054 # number of floating regfile reads 627system.cpu.fp_regfile_writes 167450 # number of floating regfile writes 628system.cpu.misc_regfile_reads 1999349 # number of misc regfile reads 629system.cpu.misc_regfile_writes 950331 # number of misc regfile writes | 612system.cpu.rob.rob_reads 149996318 # The number of ROB reads 613system.cpu.rob.rob_writes 130455868 # The number of ROB writes 614system.cpu.timesIdled 1387986 # Number of times that the entire CPU went into an idle state and unscheduled itself 615system.cpu.idleCycles 33674364 # Total number of cycles that the CPU has spent unscheduled due to idling 616system.cpu.quiesceCycles 3608226532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 617system.cpu.committedInsts 53094243 # Number of Instructions Simulated 618system.cpu.committedOps 53094243 # Number of Ops (including micro ops) Simulated 619system.cpu.committedInsts_total 53094243 # Number of Instructions Simulated 620system.cpu.cpi 2.308560 # CPI: Cycles Per Instruction 621system.cpu.cpi_total 2.308560 # CPI: Total CPI of All Threads 622system.cpu.ipc 0.433170 # IPC: Instructions Per Cycle 623system.cpu.ipc_total 0.433170 # IPC: Total IPC of All Threads 624system.cpu.int_regfile_reads 74446052 # number of integer regfile reads 625system.cpu.int_regfile_writes 40661007 # number of integer regfile writes 626system.cpu.fp_regfile_reads 166346 # number of floating regfile reads 627system.cpu.fp_regfile_writes 166939 # number of floating regfile writes 628system.cpu.misc_regfile_reads 1998850 # number of misc regfile reads 629system.cpu.misc_regfile_writes 950370 # number of misc regfile writes |
| 630system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 631system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 632system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 633system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 634system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 635system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 636system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 637system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 653system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 654system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 655system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 656system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 657system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 658system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 659system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 660system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 630system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 631system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 632system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 633system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 634system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 635system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 636system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 637system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 653system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 654system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 655system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 656system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 657system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 658system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 659system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 660system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 661system.cpu.icache.replacements 1020915 # number of replacements 662system.cpu.icache.tagsinuse 509.977219 # Cycle average of tags in use 663system.cpu.icache.total_refs 7681837 # Total number of references to valid blocks. 664system.cpu.icache.sampled_refs 1021424 # Sample count of references to valid blocks. 665system.cpu.icache.avg_refs 7.520713 # Average number of references to valid blocks. 666system.cpu.icache.warmup_cycle 23212946000 # Cycle when the warmup percentage was hit. 667system.cpu.icache.occ_blocks::cpu.inst 509.977219 # Average occupied blocks per requestor 668system.cpu.icache.occ_percent::cpu.inst 0.996049 # Average percentage of cache occupancy 669system.cpu.icache.occ_percent::total 0.996049 # Average percentage of cache occupancy 670system.cpu.icache.ReadReq_hits::cpu.inst 7681838 # number of ReadReq hits 671system.cpu.icache.ReadReq_hits::total 7681838 # number of ReadReq hits 672system.cpu.icache.demand_hits::cpu.inst 7681838 # number of demand (read+write) hits 673system.cpu.icache.demand_hits::total 7681838 # number of demand (read+write) hits 674system.cpu.icache.overall_hits::cpu.inst 7681838 # number of overall hits 675system.cpu.icache.overall_hits::total 7681838 # number of overall hits 676system.cpu.icache.ReadReq_misses::cpu.inst 1079605 # number of ReadReq misses 677system.cpu.icache.ReadReq_misses::total 1079605 # number of ReadReq misses 678system.cpu.icache.demand_misses::cpu.inst 1079605 # number of demand (read+write) misses 679system.cpu.icache.demand_misses::total 1079605 # number of demand (read+write) misses 680system.cpu.icache.overall_misses::cpu.inst 1079605 # number of overall misses 681system.cpu.icache.overall_misses::total 1079605 # number of overall misses 682system.cpu.icache.ReadReq_miss_latency::cpu.inst 16072965497 # number of ReadReq miss cycles 683system.cpu.icache.ReadReq_miss_latency::total 16072965497 # number of ReadReq miss cycles 684system.cpu.icache.demand_miss_latency::cpu.inst 16072965497 # number of demand (read+write) miss cycles 685system.cpu.icache.demand_miss_latency::total 16072965497 # number of demand (read+write) miss cycles 686system.cpu.icache.overall_miss_latency::cpu.inst 16072965497 # number of overall miss cycles 687system.cpu.icache.overall_miss_latency::total 16072965497 # number of overall miss cycles 688system.cpu.icache.ReadReq_accesses::cpu.inst 8761443 # number of ReadReq accesses(hits+misses) 689system.cpu.icache.ReadReq_accesses::total 8761443 # number of ReadReq accesses(hits+misses) 690system.cpu.icache.demand_accesses::cpu.inst 8761443 # number of demand (read+write) accesses 691system.cpu.icache.demand_accesses::total 8761443 # number of demand (read+write) accesses 692system.cpu.icache.overall_accesses::cpu.inst 8761443 # number of overall (read+write) accesses 693system.cpu.icache.overall_accesses::total 8761443 # number of overall (read+write) accesses 694system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123222 # miss rate for ReadReq accesses 695system.cpu.icache.ReadReq_miss_rate::total 0.123222 # miss rate for ReadReq accesses 696system.cpu.icache.demand_miss_rate::cpu.inst 0.123222 # miss rate for demand accesses 697system.cpu.icache.demand_miss_rate::total 0.123222 # miss rate for demand accesses 698system.cpu.icache.overall_miss_rate::cpu.inst 0.123222 # miss rate for overall accesses 699system.cpu.icache.overall_miss_rate::total 0.123222 # miss rate for overall accesses 700system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14887.820543 # average ReadReq miss latency 701system.cpu.icache.ReadReq_avg_miss_latency::total 14887.820543 # average ReadReq miss latency 702system.cpu.icache.demand_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency 703system.cpu.icache.demand_avg_miss_latency::total 14887.820543 # average overall miss latency 704system.cpu.icache.overall_avg_miss_latency::cpu.inst 14887.820543 # average overall miss latency 705system.cpu.icache.overall_avg_miss_latency::total 14887.820543 # average overall miss latency 706system.cpu.icache.blocked_cycles::no_mshrs 1368497 # number of cycles access was blocked | 661system.cpu.icache.replacements 1025209 # number of replacements 662system.cpu.icache.tagsinuse 509.960172 # Cycle average of tags in use 663system.cpu.icache.total_refs 7772148 # Total number of references to valid blocks. 664system.cpu.icache.sampled_refs 1025718 # Sample count of references to valid blocks. 665system.cpu.icache.avg_refs 7.577276 # Average number of references to valid blocks. 666system.cpu.icache.warmup_cycle 23722278000 # Cycle when the warmup percentage was hit. 667system.cpu.icache.occ_blocks::cpu.inst 509.960172 # Average occupied blocks per requestor 668system.cpu.icache.occ_percent::cpu.inst 0.996016 # Average percentage of cache occupancy 669system.cpu.icache.occ_percent::total 0.996016 # Average percentage of cache occupancy 670system.cpu.icache.ReadReq_hits::cpu.inst 7772149 # number of ReadReq hits 671system.cpu.icache.ReadReq_hits::total 7772149 # number of ReadReq hits 672system.cpu.icache.demand_hits::cpu.inst 7772149 # number of demand (read+write) hits 673system.cpu.icache.demand_hits::total 7772149 # number of demand (read+write) hits 674system.cpu.icache.overall_hits::cpu.inst 7772149 # number of overall hits 675system.cpu.icache.overall_hits::total 7772149 # number of overall hits 676system.cpu.icache.ReadReq_misses::cpu.inst 1087170 # number of ReadReq misses 677system.cpu.icache.ReadReq_misses::total 1087170 # number of ReadReq misses 678system.cpu.icache.demand_misses::cpu.inst 1087170 # number of demand (read+write) misses 679system.cpu.icache.demand_misses::total 1087170 # number of demand (read+write) misses 680system.cpu.icache.overall_misses::cpu.inst 1087170 # number of overall misses 681system.cpu.icache.overall_misses::total 1087170 # number of overall misses 682system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528418489 # number of ReadReq miss cycles 683system.cpu.icache.ReadReq_miss_latency::total 17528418489 # number of ReadReq miss cycles 684system.cpu.icache.demand_miss_latency::cpu.inst 17528418489 # number of demand (read+write) miss cycles 685system.cpu.icache.demand_miss_latency::total 17528418489 # number of demand (read+write) miss cycles 686system.cpu.icache.overall_miss_latency::cpu.inst 17528418489 # number of overall miss cycles 687system.cpu.icache.overall_miss_latency::total 17528418489 # number of overall miss cycles 688system.cpu.icache.ReadReq_accesses::cpu.inst 8859319 # number of ReadReq accesses(hits+misses) 689system.cpu.icache.ReadReq_accesses::total 8859319 # number of ReadReq accesses(hits+misses) 690system.cpu.icache.demand_accesses::cpu.inst 8859319 # number of demand (read+write) accesses 691system.cpu.icache.demand_accesses::total 8859319 # number of demand (read+write) accesses 692system.cpu.icache.overall_accesses::cpu.inst 8859319 # number of overall (read+write) accesses 693system.cpu.icache.overall_accesses::total 8859319 # number of overall (read+write) accesses 694system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122715 # miss rate for ReadReq accesses 695system.cpu.icache.ReadReq_miss_rate::total 0.122715 # miss rate for ReadReq accesses 696system.cpu.icache.demand_miss_rate::cpu.inst 0.122715 # miss rate for demand accesses 697system.cpu.icache.demand_miss_rate::total 0.122715 # miss rate for demand accesses 698system.cpu.icache.overall_miss_rate::cpu.inst 0.122715 # miss rate for overall accesses 699system.cpu.icache.overall_miss_rate::total 0.122715 # miss rate for overall accesses 700system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16122.978457 # average ReadReq miss latency 701system.cpu.icache.ReadReq_avg_miss_latency::total 16122.978457 # average ReadReq miss latency 702system.cpu.icache.demand_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency 703system.cpu.icache.demand_avg_miss_latency::total 16122.978457 # average overall miss latency 704system.cpu.icache.overall_avg_miss_latency::cpu.inst 16122.978457 # average overall miss latency 705system.cpu.icache.overall_avg_miss_latency::total 16122.978457 # average overall miss latency 706system.cpu.icache.blocked_cycles::no_mshrs 1581994 # number of cycles access was blocked |
| 707system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 707system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 708system.cpu.icache.blocked::no_mshrs 139 # number of cycles access was blocked | 708system.cpu.icache.blocked::no_mshrs 196 # number of cycles access was blocked |
| 709system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 709system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 710system.cpu.icache.avg_blocked_cycles::no_mshrs 9845.302158 # average number of cycles each access was blocked | 710system.cpu.icache.avg_blocked_cycles::no_mshrs 8071.397959 # average number of cycles each access was blocked |
| 711system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu.icache.fast_writes 0 # number of fast writes performed 713system.cpu.icache.cache_copies 0 # number of cache copies performed | 711system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu.icache.fast_writes 0 # number of fast writes performed 713system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 714system.cpu.icache.writebacks::writebacks 236 # number of writebacks 715system.cpu.icache.writebacks::total 236 # number of writebacks 716system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57973 # number of ReadReq MSHR hits 717system.cpu.icache.ReadReq_mshr_hits::total 57973 # number of ReadReq MSHR hits 718system.cpu.icache.demand_mshr_hits::cpu.inst 57973 # number of demand (read+write) MSHR hits 719system.cpu.icache.demand_mshr_hits::total 57973 # number of demand (read+write) MSHR hits 720system.cpu.icache.overall_mshr_hits::cpu.inst 57973 # number of overall MSHR hits 721system.cpu.icache.overall_mshr_hits::total 57973 # number of overall MSHR hits 722system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1021632 # number of ReadReq MSHR misses 723system.cpu.icache.ReadReq_mshr_misses::total 1021632 # number of ReadReq MSHR misses 724system.cpu.icache.demand_mshr_misses::cpu.inst 1021632 # number of demand (read+write) MSHR misses 725system.cpu.icache.demand_mshr_misses::total 1021632 # number of demand (read+write) MSHR misses 726system.cpu.icache.overall_mshr_misses::cpu.inst 1021632 # number of overall MSHR misses 727system.cpu.icache.overall_mshr_misses::total 1021632 # number of overall MSHR misses 728system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12173342997 # number of ReadReq MSHR miss cycles 729system.cpu.icache.ReadReq_mshr_miss_latency::total 12173342997 # number of ReadReq MSHR miss cycles 730system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12173342997 # number of demand (read+write) MSHR miss cycles 731system.cpu.icache.demand_mshr_miss_latency::total 12173342997 # number of demand (read+write) MSHR miss cycles 732system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12173342997 # number of overall MSHR miss cycles 733system.cpu.icache.overall_mshr_miss_latency::total 12173342997 # number of overall MSHR miss cycles 734system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for ReadReq accesses 735system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116605 # mshr miss rate for ReadReq accesses 736system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for demand accesses 737system.cpu.icache.demand_mshr_miss_rate::total 0.116605 # mshr miss rate for demand accesses 738system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116605 # mshr miss rate for overall accesses 739system.cpu.icache.overall_mshr_miss_rate::total 0.116605 # mshr miss rate for overall accesses 740system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11915.585061 # average ReadReq mshr miss latency 741system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11915.585061 # average ReadReq mshr miss latency 742system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency 743system.cpu.icache.demand_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency 744system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11915.585061 # average overall mshr miss latency 745system.cpu.icache.overall_avg_mshr_miss_latency::total 11915.585061 # average overall mshr miss latency | 714system.cpu.icache.writebacks::writebacks 238 # number of writebacks 715system.cpu.icache.writebacks::total 238 # number of writebacks 716system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61204 # number of ReadReq MSHR hits 717system.cpu.icache.ReadReq_mshr_hits::total 61204 # number of ReadReq MSHR hits 718system.cpu.icache.demand_mshr_hits::cpu.inst 61204 # number of demand (read+write) MSHR hits 719system.cpu.icache.demand_mshr_hits::total 61204 # number of demand (read+write) MSHR hits 720system.cpu.icache.overall_mshr_hits::cpu.inst 61204 # number of overall MSHR hits 721system.cpu.icache.overall_mshr_hits::total 61204 # number of overall MSHR hits 722system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025966 # number of ReadReq MSHR misses 723system.cpu.icache.ReadReq_mshr_misses::total 1025966 # number of ReadReq MSHR misses 724system.cpu.icache.demand_mshr_misses::cpu.inst 1025966 # number of demand (read+write) MSHR misses 725system.cpu.icache.demand_mshr_misses::total 1025966 # number of demand (read+write) MSHR misses 726system.cpu.icache.overall_mshr_misses::cpu.inst 1025966 # number of overall MSHR misses 727system.cpu.icache.overall_mshr_misses::total 1025966 # number of overall MSHR misses 728system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13510508994 # number of ReadReq MSHR miss cycles 729system.cpu.icache.ReadReq_mshr_miss_latency::total 13510508994 # number of ReadReq MSHR miss cycles 730system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13510508994 # number of demand (read+write) MSHR miss cycles 731system.cpu.icache.demand_mshr_miss_latency::total 13510508994 # number of demand (read+write) MSHR miss cycles 732system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13510508994 # number of overall MSHR miss cycles 733system.cpu.icache.overall_mshr_miss_latency::total 13510508994 # number of overall MSHR miss cycles 734system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for ReadReq accesses 735system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115806 # mshr miss rate for ReadReq accesses 736system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for demand accesses 737system.cpu.icache.demand_mshr_miss_rate::total 0.115806 # mshr miss rate for demand accesses 738system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115806 # mshr miss rate for overall accesses 739system.cpu.icache.overall_mshr_miss_rate::total 0.115806 # mshr miss rate for overall accesses 740system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13168.573807 # average ReadReq mshr miss latency 741system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13168.573807 # average ReadReq mshr miss latency 742system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency 743system.cpu.icache.demand_avg_mshr_miss_latency::total 13168.573807 # average overall mshr miss latency 744system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13168.573807 # average overall mshr miss latency 745system.cpu.icache.overall_avg_mshr_miss_latency::total 13168.573807 # average overall mshr miss latency |
| 746system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 746system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 747system.cpu.dcache.replacements 1401226 # number of replacements 748system.cpu.dcache.tagsinuse 511.995976 # Cycle average of tags in use 749system.cpu.dcache.total_refs 11915698 # Total number of references to valid blocks. 750system.cpu.dcache.sampled_refs 1401738 # Sample count of references to valid blocks. 751system.cpu.dcache.avg_refs 8.500660 # Average number of references to valid blocks. 752system.cpu.dcache.warmup_cycle 19319000 # Cycle when the warmup percentage was hit. 753system.cpu.dcache.occ_blocks::cpu.data 511.995976 # Average occupied blocks per requestor | 747system.cpu.dcache.replacements 1403926 # number of replacements 748system.cpu.dcache.tagsinuse 511.995922 # Cycle average of tags in use 749system.cpu.dcache.total_refs 11884045 # Total number of references to valid blocks. 750system.cpu.dcache.sampled_refs 1404438 # Sample count of references to valid blocks. 751system.cpu.dcache.avg_refs 8.461780 # Average number of references to valid blocks. 752system.cpu.dcache.warmup_cycle 19693000 # Cycle when the warmup percentage was hit. 753system.cpu.dcache.occ_blocks::cpu.data 511.995922 # Average occupied blocks per requestor |
| 754system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy 755system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy | 754system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy 755system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy |
| 756system.cpu.dcache.ReadReq_hits::cpu.data 7290659 # number of ReadReq hits 757system.cpu.dcache.ReadReq_hits::total 7290659 # number of ReadReq hits 758system.cpu.dcache.WriteReq_hits::cpu.data 4213930 # number of WriteReq hits 759system.cpu.dcache.WriteReq_hits::total 4213930 # number of WriteReq hits 760system.cpu.dcache.LoadLockedReq_hits::cpu.data 190794 # number of LoadLockedReq hits 761system.cpu.dcache.LoadLockedReq_hits::total 190794 # number of LoadLockedReq hits 762system.cpu.dcache.StoreCondReq_hits::cpu.data 220142 # number of StoreCondReq hits 763system.cpu.dcache.StoreCondReq_hits::total 220142 # number of StoreCondReq hits 764system.cpu.dcache.demand_hits::cpu.data 11504589 # number of demand (read+write) hits 765system.cpu.dcache.demand_hits::total 11504589 # number of demand (read+write) hits 766system.cpu.dcache.overall_hits::cpu.data 11504589 # number of overall hits 767system.cpu.dcache.overall_hits::total 11504589 # number of overall hits 768system.cpu.dcache.ReadReq_misses::cpu.data 1799381 # number of ReadReq misses 769system.cpu.dcache.ReadReq_misses::total 1799381 # number of ReadReq misses 770system.cpu.dcache.WriteReq_misses::cpu.data 1940587 # number of WriteReq misses 771system.cpu.dcache.WriteReq_misses::total 1940587 # number of WriteReq misses 772system.cpu.dcache.LoadLockedReq_misses::cpu.data 23075 # number of LoadLockedReq misses 773system.cpu.dcache.LoadLockedReq_misses::total 23075 # number of LoadLockedReq misses 774system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 775system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 776system.cpu.dcache.demand_misses::cpu.data 3739968 # number of demand (read+write) misses 777system.cpu.dcache.demand_misses::total 3739968 # number of demand (read+write) misses 778system.cpu.dcache.overall_misses::cpu.data 3739968 # number of overall misses 779system.cpu.dcache.overall_misses::total 3739968 # number of overall misses 780system.cpu.dcache.ReadReq_miss_latency::cpu.data 37711411500 # number of ReadReq miss cycles 781system.cpu.dcache.ReadReq_miss_latency::total 37711411500 # number of ReadReq miss cycles 782system.cpu.dcache.WriteReq_miss_latency::cpu.data 57880522429 # number of WriteReq miss cycles 783system.cpu.dcache.WriteReq_miss_latency::total 57880522429 # number of WriteReq miss cycles 784system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 335593000 # number of LoadLockedReq miss cycles 785system.cpu.dcache.LoadLockedReq_miss_latency::total 335593000 # number of LoadLockedReq miss cycles 786system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 14000 # number of StoreCondReq miss cycles 787system.cpu.dcache.StoreCondReq_miss_latency::total 14000 # number of StoreCondReq miss cycles 788system.cpu.dcache.demand_miss_latency::cpu.data 95591933929 # number of demand (read+write) miss cycles 789system.cpu.dcache.demand_miss_latency::total 95591933929 # number of demand (read+write) miss cycles 790system.cpu.dcache.overall_miss_latency::cpu.data 95591933929 # number of overall miss cycles 791system.cpu.dcache.overall_miss_latency::total 95591933929 # number of overall miss cycles 792system.cpu.dcache.ReadReq_accesses::cpu.data 9090040 # number of ReadReq accesses(hits+misses) 793system.cpu.dcache.ReadReq_accesses::total 9090040 # number of ReadReq accesses(hits+misses) 794system.cpu.dcache.WriteReq_accesses::cpu.data 6154517 # number of WriteReq accesses(hits+misses) 795system.cpu.dcache.WriteReq_accesses::total 6154517 # number of WriteReq accesses(hits+misses) 796system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213869 # number of LoadLockedReq accesses(hits+misses) 797system.cpu.dcache.LoadLockedReq_accesses::total 213869 # number of LoadLockedReq accesses(hits+misses) 798system.cpu.dcache.StoreCondReq_accesses::cpu.data 220143 # number of StoreCondReq accesses(hits+misses) 799system.cpu.dcache.StoreCondReq_accesses::total 220143 # number of StoreCondReq accesses(hits+misses) 800system.cpu.dcache.demand_accesses::cpu.data 15244557 # number of demand (read+write) accesses 801system.cpu.dcache.demand_accesses::total 15244557 # number of demand (read+write) accesses 802system.cpu.dcache.overall_accesses::cpu.data 15244557 # number of overall (read+write) accesses 803system.cpu.dcache.overall_accesses::total 15244557 # number of overall (read+write) accesses 804system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197951 # miss rate for ReadReq accesses 805system.cpu.dcache.ReadReq_miss_rate::total 0.197951 # miss rate for ReadReq accesses 806system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315311 # miss rate for WriteReq accesses 807system.cpu.dcache.WriteReq_miss_rate::total 0.315311 # miss rate for WriteReq accesses 808system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107893 # miss rate for LoadLockedReq accesses 809system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107893 # miss rate for LoadLockedReq accesses 810system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses 811system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses 812system.cpu.dcache.demand_miss_rate::cpu.data 0.245331 # miss rate for demand accesses 813system.cpu.dcache.demand_miss_rate::total 0.245331 # miss rate for demand accesses 814system.cpu.dcache.overall_miss_rate::cpu.data 0.245331 # miss rate for overall accesses 815system.cpu.dcache.overall_miss_rate::total 0.245331 # miss rate for overall accesses 816system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20957.991387 # average ReadReq miss latency 817system.cpu.dcache.ReadReq_avg_miss_latency::total 20957.991387 # average ReadReq miss latency 818system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29826.296079 # average WriteReq miss latency 819system.cpu.dcache.WriteReq_avg_miss_latency::total 29826.296079 # average WriteReq miss latency 820system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14543.575298 # average LoadLockedReq miss latency 821system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14543.575298 # average LoadLockedReq miss latency 822system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14000 # average StoreCondReq miss latency 823system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14000 # average StoreCondReq miss latency 824system.cpu.dcache.demand_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency 825system.cpu.dcache.demand_avg_miss_latency::total 25559.559314 # average overall miss latency 826system.cpu.dcache.overall_avg_miss_latency::cpu.data 25559.559314 # average overall miss latency 827system.cpu.dcache.overall_avg_miss_latency::total 25559.559314 # average overall miss latency 828system.cpu.dcache.blocked_cycles::no_mshrs 805076325 # number of cycles access was blocked 829system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked 830system.cpu.dcache.blocked::no_mshrs 99334 # number of cycles access was blocked | 756system.cpu.dcache.ReadReq_hits::cpu.data 7283526 # number of ReadReq hits 757system.cpu.dcache.ReadReq_hits::total 7283526 # number of ReadReq hits 758system.cpu.dcache.WriteReq_hits::cpu.data 4189382 # number of WriteReq hits 759system.cpu.dcache.WriteReq_hits::total 4189382 # number of WriteReq hits 760system.cpu.dcache.LoadLockedReq_hits::cpu.data 190687 # number of LoadLockedReq hits 761system.cpu.dcache.LoadLockedReq_hits::total 190687 # number of LoadLockedReq hits 762system.cpu.dcache.StoreCondReq_hits::cpu.data 220149 # number of StoreCondReq hits 763system.cpu.dcache.StoreCondReq_hits::total 220149 # number of StoreCondReq hits 764system.cpu.dcache.demand_hits::cpu.data 11472908 # number of demand (read+write) hits 765system.cpu.dcache.demand_hits::total 11472908 # number of demand (read+write) hits 766system.cpu.dcache.overall_hits::cpu.data 11472908 # number of overall hits 767system.cpu.dcache.overall_hits::total 11472908 # number of overall hits 768system.cpu.dcache.ReadReq_misses::cpu.data 1829585 # number of ReadReq misses 769system.cpu.dcache.ReadReq_misses::total 1829585 # number of ReadReq misses 770system.cpu.dcache.WriteReq_misses::cpu.data 1968134 # number of WriteReq misses 771system.cpu.dcache.WriteReq_misses::total 1968134 # number of WriteReq misses 772system.cpu.dcache.LoadLockedReq_misses::cpu.data 23417 # number of LoadLockedReq misses 773system.cpu.dcache.LoadLockedReq_misses::total 23417 # number of LoadLockedReq misses 774system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 775system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses 776system.cpu.dcache.demand_misses::cpu.data 3797719 # number of demand (read+write) misses 777system.cpu.dcache.demand_misses::total 3797719 # number of demand (read+write) misses 778system.cpu.dcache.overall_misses::cpu.data 3797719 # number of overall misses 779system.cpu.dcache.overall_misses::total 3797719 # number of overall misses 780system.cpu.dcache.ReadReq_miss_latency::cpu.data 48849966500 # number of ReadReq miss cycles 781system.cpu.dcache.ReadReq_miss_latency::total 48849966500 # number of ReadReq miss cycles 782system.cpu.dcache.WriteReq_miss_latency::cpu.data 74989002011 # number of WriteReq miss cycles 783system.cpu.dcache.WriteReq_miss_latency::total 74989002011 # number of WriteReq miss cycles 784system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 432032000 # number of LoadLockedReq miss cycles 785system.cpu.dcache.LoadLockedReq_miss_latency::total 432032000 # number of LoadLockedReq miss cycles 786system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 56500 # number of StoreCondReq miss cycles 787system.cpu.dcache.StoreCondReq_miss_latency::total 56500 # number of StoreCondReq miss cycles 788system.cpu.dcache.demand_miss_latency::cpu.data 123838968511 # number of demand (read+write) miss cycles 789system.cpu.dcache.demand_miss_latency::total 123838968511 # number of demand (read+write) miss cycles 790system.cpu.dcache.overall_miss_latency::cpu.data 123838968511 # number of overall miss cycles 791system.cpu.dcache.overall_miss_latency::total 123838968511 # number of overall miss cycles 792system.cpu.dcache.ReadReq_accesses::cpu.data 9113111 # number of ReadReq accesses(hits+misses) 793system.cpu.dcache.ReadReq_accesses::total 9113111 # number of ReadReq accesses(hits+misses) 794system.cpu.dcache.WriteReq_accesses::cpu.data 6157516 # number of WriteReq accesses(hits+misses) 795system.cpu.dcache.WriteReq_accesses::total 6157516 # number of WriteReq accesses(hits+misses) 796system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214104 # number of LoadLockedReq accesses(hits+misses) 797system.cpu.dcache.LoadLockedReq_accesses::total 214104 # number of LoadLockedReq accesses(hits+misses) 798system.cpu.dcache.StoreCondReq_accesses::cpu.data 220153 # number of StoreCondReq accesses(hits+misses) 799system.cpu.dcache.StoreCondReq_accesses::total 220153 # number of StoreCondReq accesses(hits+misses) 800system.cpu.dcache.demand_accesses::cpu.data 15270627 # number of demand (read+write) accesses 801system.cpu.dcache.demand_accesses::total 15270627 # number of demand (read+write) accesses 802system.cpu.dcache.overall_accesses::cpu.data 15270627 # number of overall (read+write) accesses 803system.cpu.dcache.overall_accesses::total 15270627 # number of overall (read+write) accesses 804system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200764 # miss rate for ReadReq accesses 805system.cpu.dcache.ReadReq_miss_rate::total 0.200764 # miss rate for ReadReq accesses 806system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319631 # miss rate for WriteReq accesses 807system.cpu.dcache.WriteReq_miss_rate::total 0.319631 # miss rate for WriteReq accesses 808system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.109372 # miss rate for LoadLockedReq accesses 809system.cpu.dcache.LoadLockedReq_miss_rate::total 0.109372 # miss rate for LoadLockedReq accesses 810system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000018 # miss rate for StoreCondReq accesses 811system.cpu.dcache.StoreCondReq_miss_rate::total 0.000018 # miss rate for StoreCondReq accesses 812system.cpu.dcache.demand_miss_rate::cpu.data 0.248694 # miss rate for demand accesses 813system.cpu.dcache.demand_miss_rate::total 0.248694 # miss rate for demand accesses 814system.cpu.dcache.overall_miss_rate::cpu.data 0.248694 # miss rate for overall accesses 815system.cpu.dcache.overall_miss_rate::total 0.248694 # miss rate for overall accesses 816system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26700.025689 # average ReadReq miss latency 817system.cpu.dcache.ReadReq_avg_miss_latency::total 26700.025689 # average ReadReq miss latency 818system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38101.573374 # average WriteReq miss latency 819system.cpu.dcache.WriteReq_avg_miss_latency::total 38101.573374 # average WriteReq miss latency 820system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18449.502498 # average LoadLockedReq miss latency 821system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18449.502498 # average LoadLockedReq miss latency 822system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14125 # average StoreCondReq miss latency 823system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14125 # average StoreCondReq miss latency 824system.cpu.dcache.demand_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency 825system.cpu.dcache.demand_avg_miss_latency::total 32608.776087 # average overall miss latency 826system.cpu.dcache.overall_avg_miss_latency::cpu.data 32608.776087 # average overall miss latency 827system.cpu.dcache.overall_avg_miss_latency::total 32608.776087 # average overall miss latency 828system.cpu.dcache.blocked_cycles::no_mshrs 732928021 # number of cycles access was blocked 829system.cpu.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked 830system.cpu.dcache.blocked::no_mshrs 72145 # number of cycles access was blocked |
| 831system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked | 831system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 832system.cpu.dcache.avg_blocked_cycles::no_mshrs 8104.740824 # average number of cycles each access was blocked 833system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked | 832system.cpu.dcache.avg_blocked_cycles::no_mshrs 10159.096556 # average number of cycles each access was blocked 833system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked |
| 834system.cpu.dcache.fast_writes 0 # number of fast writes performed 835system.cpu.dcache.cache_copies 0 # number of cache copies performed | 834system.cpu.dcache.fast_writes 0 # number of fast writes performed 835system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 836system.cpu.dcache.writebacks::writebacks 840933 # number of writebacks 837system.cpu.dcache.writebacks::total 840933 # number of writebacks 838system.cpu.dcache.ReadReq_mshr_hits::cpu.data 715397 # number of ReadReq MSHR hits 839system.cpu.dcache.ReadReq_mshr_hits::total 715397 # number of ReadReq MSHR hits 840system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640618 # number of WriteReq MSHR hits 841system.cpu.dcache.WriteReq_mshr_hits::total 1640618 # number of WriteReq MSHR hits 842system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5145 # number of LoadLockedReq MSHR hits 843system.cpu.dcache.LoadLockedReq_mshr_hits::total 5145 # number of LoadLockedReq MSHR hits 844system.cpu.dcache.demand_mshr_hits::cpu.data 2356015 # number of demand (read+write) MSHR hits 845system.cpu.dcache.demand_mshr_hits::total 2356015 # number of demand (read+write) MSHR hits 846system.cpu.dcache.overall_mshr_hits::cpu.data 2356015 # number of overall MSHR hits 847system.cpu.dcache.overall_mshr_hits::total 2356015 # number of overall MSHR hits 848system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083984 # number of ReadReq MSHR misses 849system.cpu.dcache.ReadReq_mshr_misses::total 1083984 # number of ReadReq MSHR misses 850system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299969 # number of WriteReq MSHR misses 851system.cpu.dcache.WriteReq_mshr_misses::total 299969 # number of WriteReq MSHR misses 852system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17930 # number of LoadLockedReq MSHR misses 853system.cpu.dcache.LoadLockedReq_mshr_misses::total 17930 # number of LoadLockedReq MSHR misses 854system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 855system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 856system.cpu.dcache.demand_mshr_misses::cpu.data 1383953 # number of demand (read+write) MSHR misses 857system.cpu.dcache.demand_mshr_misses::total 1383953 # number of demand (read+write) MSHR misses 858system.cpu.dcache.overall_mshr_misses::cpu.data 1383953 # number of overall MSHR misses 859system.cpu.dcache.overall_mshr_misses::total 1383953 # number of overall MSHR misses 860system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24067895500 # number of ReadReq MSHR miss cycles 861system.cpu.dcache.ReadReq_mshr_miss_latency::total 24067895500 # number of ReadReq MSHR miss cycles 862system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8474806325 # number of WriteReq MSHR miss cycles 863system.cpu.dcache.WriteReq_mshr_miss_latency::total 8474806325 # number of WriteReq MSHR miss cycles 864system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206484500 # number of LoadLockedReq MSHR miss cycles 865system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206484500 # number of LoadLockedReq MSHR miss cycles 866system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles 867system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles 868system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32542701825 # number of demand (read+write) MSHR miss cycles 869system.cpu.dcache.demand_mshr_miss_latency::total 32542701825 # number of demand (read+write) MSHR miss cycles 870system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32542701825 # number of overall MSHR miss cycles 871system.cpu.dcache.overall_mshr_miss_latency::total 32542701825 # number of overall MSHR miss cycles 872system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904540000 # number of ReadReq MSHR uncacheable cycles 873system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904540000 # number of ReadReq MSHR uncacheable cycles 874system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234101998 # number of WriteReq MSHR uncacheable cycles 875system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234101998 # number of WriteReq MSHR uncacheable cycles 876system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138641998 # number of overall MSHR uncacheable cycles 877system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138641998 # number of overall MSHR uncacheable cycles 878system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119250 # mshr miss rate for ReadReq accesses 879system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119250 # mshr miss rate for ReadReq accesses 880system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048740 # mshr miss rate for WriteReq accesses 881system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048740 # mshr miss rate for WriteReq accesses 882system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083836 # mshr miss rate for LoadLockedReq accesses 883system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083836 # mshr miss rate for LoadLockedReq accesses 884system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses 885system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses 886system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for demand accesses 887system.cpu.dcache.demand_mshr_miss_rate::total 0.090783 # mshr miss rate for demand accesses 888system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090783 # mshr miss rate for overall accesses 889system.cpu.dcache.overall_mshr_miss_rate::total 0.090783 # mshr miss rate for overall accesses 890system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22203.183350 # average ReadReq mshr miss latency 891system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22203.183350 # average ReadReq mshr miss latency 892system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28252.273818 # average WriteReq mshr miss latency 893system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28252.273818 # average WriteReq mshr miss latency 894system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11516.146124 # average LoadLockedReq mshr miss latency 895system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11516.146124 # average LoadLockedReq mshr miss latency | 836system.cpu.dcache.writebacks::writebacks 842954 # number of writebacks 837system.cpu.dcache.writebacks::total 842954 # number of writebacks 838system.cpu.dcache.ReadReq_mshr_hits::cpu.data 743747 # number of ReadReq MSHR hits 839system.cpu.dcache.ReadReq_mshr_hits::total 743747 # number of ReadReq MSHR hits 840system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1667534 # number of WriteReq MSHR hits 841system.cpu.dcache.WriteReq_mshr_hits::total 1667534 # number of WriteReq MSHR hits 842system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5230 # number of LoadLockedReq MSHR hits 843system.cpu.dcache.LoadLockedReq_mshr_hits::total 5230 # number of LoadLockedReq MSHR hits 844system.cpu.dcache.demand_mshr_hits::cpu.data 2411281 # number of demand (read+write) MSHR hits 845system.cpu.dcache.demand_mshr_hits::total 2411281 # number of demand (read+write) MSHR hits 846system.cpu.dcache.overall_mshr_hits::cpu.data 2411281 # number of overall MSHR hits 847system.cpu.dcache.overall_mshr_hits::total 2411281 # number of overall MSHR hits 848system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085838 # number of ReadReq MSHR misses 849system.cpu.dcache.ReadReq_mshr_misses::total 1085838 # number of ReadReq MSHR misses 850system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300600 # number of WriteReq MSHR misses 851system.cpu.dcache.WriteReq_mshr_misses::total 300600 # number of WriteReq MSHR misses 852system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18187 # number of LoadLockedReq MSHR misses 853system.cpu.dcache.LoadLockedReq_mshr_misses::total 18187 # number of LoadLockedReq MSHR misses 854system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses 855system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses 856system.cpu.dcache.demand_mshr_misses::cpu.data 1386438 # number of demand (read+write) MSHR misses 857system.cpu.dcache.demand_mshr_misses::total 1386438 # number of demand (read+write) MSHR misses 858system.cpu.dcache.overall_mshr_misses::cpu.data 1386438 # number of overall MSHR misses 859system.cpu.dcache.overall_mshr_misses::total 1386438 # number of overall MSHR misses 860system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28239740000 # number of ReadReq MSHR miss cycles 861system.cpu.dcache.ReadReq_mshr_miss_latency::total 28239740000 # number of ReadReq MSHR miss cycles 862system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9650792448 # number of WriteReq MSHR miss cycles 863system.cpu.dcache.WriteReq_mshr_miss_latency::total 9650792448 # number of WriteReq MSHR miss cycles 864system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 273508500 # number of LoadLockedReq MSHR miss cycles 865system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 273508500 # number of LoadLockedReq MSHR miss cycles 866system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 44000 # number of StoreCondReq MSHR miss cycles 867system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles 868system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37890532448 # number of demand (read+write) MSHR miss cycles 869system.cpu.dcache.demand_mshr_miss_latency::total 37890532448 # number of demand (read+write) MSHR miss cycles 870system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37890532448 # number of overall MSHR miss cycles 871system.cpu.dcache.overall_mshr_miss_latency::total 37890532448 # number of overall MSHR miss cycles 872system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 905949500 # number of ReadReq MSHR uncacheable cycles 873system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 905949500 # number of ReadReq MSHR uncacheable cycles 874system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1225663998 # number of WriteReq MSHR uncacheable cycles 875system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1225663998 # number of WriteReq MSHR uncacheable cycles 876system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2131613498 # number of overall MSHR uncacheable cycles 877system.cpu.dcache.overall_mshr_uncacheable_latency::total 2131613498 # number of overall MSHR uncacheable cycles 878system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119151 # mshr miss rate for ReadReq accesses 879system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119151 # mshr miss rate for ReadReq accesses 880system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048818 # mshr miss rate for WriteReq accesses 881system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048818 # mshr miss rate for WriteReq accesses 882system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084945 # mshr miss rate for LoadLockedReq accesses 883system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084945 # mshr miss rate for LoadLockedReq accesses 884system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000018 # mshr miss rate for StoreCondReq accesses 885system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000018 # mshr miss rate for StoreCondReq accesses 886system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for demand accesses 887system.cpu.dcache.demand_mshr_miss_rate::total 0.090791 # mshr miss rate for demand accesses 888system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090791 # mshr miss rate for overall accesses 889system.cpu.dcache.overall_mshr_miss_rate::total 0.090791 # mshr miss rate for overall accesses 890system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26007.323376 # average ReadReq mshr miss latency 891system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26007.323376 # average ReadReq mshr miss latency 892system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32105.097964 # average WriteReq mshr miss latency 893system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32105.097964 # average WriteReq mshr miss latency 894system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15038.681476 # average LoadLockedReq mshr miss latency 895system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15038.681476 # average LoadLockedReq mshr miss latency |
| 896system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 897system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency | 896system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 897system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency |
| 898system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency 899system.cpu.dcache.demand_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency 900system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23514.311414 # average overall mshr miss latency 901system.cpu.dcache.overall_avg_mshr_miss_latency::total 23514.311414 # average overall mshr miss latency | 898system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency 899system.cpu.dcache.demand_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency 900system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27329.409933 # average overall mshr miss latency 901system.cpu.dcache.overall_avg_mshr_miss_latency::total 27329.409933 # average overall mshr miss latency |
| 902system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 903system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 904system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 905system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 906system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 907system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 908system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 909system.cpu.kern.inst.arm 0 # number of arm instructions executed | 902system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 903system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 904system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 905system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 906system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 907system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 908system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 909system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 910system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed 911system.cpu.kern.inst.hwrei 211701 # number of hwrei instructions executed 912system.cpu.kern.ipl_count::0 74930 40.96% 40.96% # number of times we switched to this ipl 913system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl 914system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl 915system.cpu.kern.ipl_count::31 105874 57.88% 100.00% # number of times we switched to this ipl 916system.cpu.kern.ipl_count::total 182929 # number of times we switched to this ipl 917system.cpu.kern.ipl_good::0 73563 49.29% 49.29% # number of times we switched to this ipl from a different ipl 918system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl 919system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl 920system.cpu.kern.ipl_good::31 73566 49.29% 100.00% # number of times we switched to this ipl from a different ipl 921system.cpu.kern.ipl_good::total 149254 # number of times we switched to this ipl from a different ipl 922system.cpu.kern.ipl_ticks::0 1820291216500 97.92% 97.92% # number of cycles we spent at this ipl 923system.cpu.kern.ipl_ticks::21 94615000 0.01% 97.93% # number of cycles we spent at this ipl 924system.cpu.kern.ipl_ticks::22 380636500 0.02% 97.95% # number of cycles we spent at this ipl 925system.cpu.kern.ipl_ticks::31 38112442500 2.05% 100.00% # number of cycles we spent at this ipl 926system.cpu.kern.ipl_ticks::total 1858878910500 # number of cycles we spent at this ipl 927system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl | 910system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed 911system.cpu.kern.inst.hwrei 211694 # number of hwrei instructions executed 912system.cpu.kern.ipl_count::0 74899 40.95% 40.95% # number of times we switched to this ipl 913system.cpu.kern.ipl_count::21 247 0.14% 41.08% # number of times we switched to this ipl 914system.cpu.kern.ipl_count::22 1887 1.03% 42.11% # number of times we switched to this ipl 915system.cpu.kern.ipl_count::31 105884 57.89% 100.00% # number of times we switched to this ipl 916system.cpu.kern.ipl_count::total 182917 # number of times we switched to this ipl 917system.cpu.kern.ipl_good::0 73532 49.28% 49.28% # number of times we switched to this ipl from a different ipl 918system.cpu.kern.ipl_good::21 247 0.17% 49.45% # number of times we switched to this ipl from a different ipl 919system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl 920system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl 921system.cpu.kern.ipl_good::total 149203 # number of times we switched to this ipl from a different ipl 922system.cpu.kern.ipl_ticks::0 1825754390000 97.87% 97.87% # number of cycles we spent at this ipl 923system.cpu.kern.ipl_ticks::21 99081000 0.01% 97.88% # number of cycles we spent at this ipl 924system.cpu.kern.ipl_ticks::22 381309500 0.02% 97.90% # number of cycles we spent at this ipl 925system.cpu.kern.ipl_ticks::31 39166410000 2.10% 100.00% # number of cycles we spent at this ipl 926system.cpu.kern.ipl_ticks::total 1865401190500 # number of cycles we spent at this ipl 927system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl |
| 928system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 929system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 928system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 929system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 930system.cpu.kern.ipl_used::31 0.694845 # fraction of swpipl calls that actually changed the ipl 931system.cpu.kern.ipl_used::total 0.815912 # fraction of swpipl calls that actually changed the ipl | 930system.cpu.kern.ipl_used::31 0.694505 # fraction of swpipl calls that actually changed the ipl 931system.cpu.kern.ipl_used::total 0.815687 # fraction of swpipl calls that actually changed the ipl |
| 932system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 933system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 934system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 935system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 936system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 937system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 938system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 939system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 962system.cpu.kern.syscall::total 326 # number of syscalls executed 963system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 964system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 965system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 966system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 967system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 968system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 969system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 932system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 933system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 934system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 935system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 936system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 937system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 938system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 939system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 962system.cpu.kern.syscall::total 326 # number of syscalls executed 963system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 964system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 965system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 966system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 967system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 968system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 969system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 970system.cpu.kern.callpal::swpipl 175590 91.19% 93.39% # number of callpals executed 971system.cpu.kern.callpal::rdps 6787 3.52% 96.92% # number of callpals executed | 970system.cpu.kern.callpal::swpipl 175564 91.19% 93.39% # number of callpals executed 971system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed |
| 972system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 973system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed | 972system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 973system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed |
| 974system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed | 974system.cpu.kern.callpal::rdusp 9 0.00% 96.92% # number of callpals executed |
| 975system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed | 975system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed |
| 976system.cpu.kern.callpal::rti 5216 2.71% 99.64% # number of callpals executed | 976system.cpu.kern.callpal::rti 5223 2.71% 99.64% # number of callpals executed |
| 977system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 978system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 977system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 978system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 979system.cpu.kern.callpal::total 192549 # number of callpals executed | 979system.cpu.kern.callpal::total 192535 # number of callpals executed |
| 980system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches | 980system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches |
| 981system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 982system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches 983system.cpu.kern.mode_good::kernel 1908 984system.cpu.kern.mode_good::user 1738 | 981system.cpu.kern.mode_switch::user 1736 # number of protection mode switches 982system.cpu.kern.mode_switch::idle 2110 # number of protection mode switches 983system.cpu.kern.mode_good::kernel 1906 984system.cpu.kern.mode_good::user 1736 |
| 985system.cpu.kern.mode_good::idle 170 | 985system.cpu.kern.mode_good::idle 170 |
| 986system.cpu.kern.mode_switch_good::kernel 0.320403 # fraction of useful protection mode switches | 986system.cpu.kern.mode_switch_good::kernel 0.320067 # fraction of useful protection mode switches |
| 987system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 987system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 988system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches 989system.cpu.kern.mode_switch_good::total 0.389547 # fraction of useful protection mode switches 990system.cpu.kern.mode_ticks::kernel 29004913500 1.56% 1.56% # number of ticks spent at the given mode 991system.cpu.kern.mode_ticks::user 2663331000 0.14% 1.70% # number of ticks spent at the given mode 992system.cpu.kern.mode_ticks::idle 1827210658000 98.30% 100.00% # number of ticks spent at the given mode | 988system.cpu.kern.mode_switch_good::idle 0.080569 # fraction of useful protection mode switches 989system.cpu.kern.mode_switch_good::total 0.388940 # fraction of useful protection mode switches 990system.cpu.kern.mode_ticks::kernel 29632954500 1.59% 1.59% # number of ticks spent at the given mode 991system.cpu.kern.mode_ticks::user 2782152500 0.15% 1.74% # number of ticks spent at the given mode 992system.cpu.kern.mode_ticks::idle 1832986075500 98.26% 100.00% # number of ticks spent at the given mode |
| 993system.cpu.kern.swap_context 4177 # number of times the context was actually changed 994 995---------- End Simulation Statistics ---------- | 993system.cpu.kern.swap_context 4177 # number of times the context was actually changed 994 995---------- End Simulation Statistics ---------- |