| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.858684 # Number of seconds simulated 4sim_ticks 1858684403000 # Number of ticks simulated 5final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.858684 # Number of seconds simulated 4sim_ticks 1858684403000 # Number of ticks simulated 5final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 192280 # Simulator instruction rate (inst/s) 8host_op_rate 192280 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6731751609 # Simulator tick rate (ticks/s) 10host_mem_usage 292636 # Number of bytes of host memory used 11host_seconds 276.11 # Real time elapsed on the host | 7host_inst_rate 73473 # Simulator instruction rate (inst/s) 8host_op_rate 73473 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2572309842 # Simulator tick rate (ticks/s) 10host_mem_usage 296656 # Number of bytes of host memory used 11host_seconds 722.57 # Real time elapsed on the host |
| 12sim_insts 53089851 # Number of instructions simulated 13sim_ops 53089851 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 29847552 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1082432 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10195968 # Number of bytes written to this memory 17system.physmem.num_reads 466368 # Number of read requests responded to by this memory 18system.physmem.num_writes 159312 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 92 unchanged lines hidden (view full) --- 112system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency 113system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency 114system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency 115system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency 116system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 119system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 53089851 # Number of instructions simulated 13sim_ops 53089851 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 29847552 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1082432 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10195968 # Number of bytes written to this memory 17system.physmem.num_reads 466368 # Number of read requests responded to by this memory 18system.physmem.num_writes 159312 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 92 unchanged lines hidden (view full) --- 112system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency 113system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency 114system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency 115system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency 116system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 119system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 120system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 121system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 120system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 121system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 122system.l2c.fast_writes 0 # number of fast writes performed 123system.l2c.cache_copies 0 # number of cache copies performed 124system.l2c.writebacks::writebacks 117800 # number of writebacks 125system.l2c.writebacks::total 117800 # number of writebacks 126system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 127system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 128system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 129system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits --- 98 unchanged lines hidden (view full) --- 228system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency 229system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency 230system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency 231system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked 232system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 233system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked 234system.iocache.blocked::no_targets 0 # number of cycles access was blocked 235system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked | 122system.l2c.fast_writes 0 # number of fast writes performed 123system.l2c.cache_copies 0 # number of cache copies performed 124system.l2c.writebacks::writebacks 117800 # number of writebacks 125system.l2c.writebacks::total 117800 # number of writebacks 126system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 127system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 128system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 129system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits --- 98 unchanged lines hidden (view full) --- 228system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency 229system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency 230system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency 231system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked 232system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 233system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked 234system.iocache.blocked::no_targets 0 # number of cycles access was blocked 235system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked |
| 236system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 236system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 237system.iocache.fast_writes 0 # number of fast writes performed 238system.iocache.cache_copies 0 # number of cache copies performed 239system.iocache.writebacks::writebacks 41512 # number of writebacks 240system.iocache.writebacks::total 41512 # number of writebacks 241system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 242system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 243system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 244system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses --- 335 unchanged lines hidden (view full) --- 580system.cpu.fp_regfile_writes 167434 # number of floating regfile writes 581system.cpu.misc_regfile_reads 1998995 # number of misc regfile reads 582system.cpu.misc_regfile_writes 949957 # number of misc regfile writes 583system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 584system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 585system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 586system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 587system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU | 237system.iocache.fast_writes 0 # number of fast writes performed 238system.iocache.cache_copies 0 # number of cache copies performed 239system.iocache.writebacks::writebacks 41512 # number of writebacks 240system.iocache.writebacks::total 41512 # number of writebacks 241system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 242system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 243system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 244system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses --- 335 unchanged lines hidden (view full) --- 580system.cpu.fp_regfile_writes 167434 # number of floating regfile writes 581system.cpu.misc_regfile_reads 1998995 # number of misc regfile reads 582system.cpu.misc_regfile_writes 949957 # number of misc regfile writes 583system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 584system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 585system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 586system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 587system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU |
| 588system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post | 588system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post |
| 589system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 590system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU | 589system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 590system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU |
| 591system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post | 591system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post |
| 592system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 593system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU | 592system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 593system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU |
| 594system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post | 594system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post |
| 595system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 596system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU | 595system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 596system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU |
| 597system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post | 597system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post |
| 598system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 599system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU | 598system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 599system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU |
| 600system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post | 600system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post |
| 601system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 602system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU | 601system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 602system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU |
| 603system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post | 603system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post |
| 604system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 605system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU | 604system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 605system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU |
| 606system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post | 606system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post |
| 607system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 608system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU | 607system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 608system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU |
| 609system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post | 609system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post |
| 610system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR | 610system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR |
| 611system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post | 611system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post |
| 612system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 613system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 614system.cpu.icache.replacements 1025621 # number of replacements 615system.cpu.icache.tagsinuse 509.964536 # Cycle average of tags in use 616system.cpu.icache.total_refs 7915589 # Total number of references to valid blocks. 617system.cpu.icache.sampled_refs 1026130 # Sample count of references to valid blocks. 618system.cpu.icache.avg_refs 7.714022 # Average number of references to valid blocks. 619system.cpu.icache.warmup_cycle 23323095000 # Cycle when the warmup percentage was hit. --- 30 unchanged lines hidden (view full) --- 650system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency 651system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency 653system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667 # average number of cycles each access was blocked | 612system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 613system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 614system.cpu.icache.replacements 1025621 # number of replacements 615system.cpu.icache.tagsinuse 509.964536 # Cycle average of tags in use 616system.cpu.icache.total_refs 7915589 # Total number of references to valid blocks. 617system.cpu.icache.sampled_refs 1026130 # Sample count of references to valid blocks. 618system.cpu.icache.avg_refs 7.714022 # Average number of references to valid blocks. 619system.cpu.icache.warmup_cycle 23323095000 # Cycle when the warmup percentage was hit. --- 30 unchanged lines hidden (view full) --- 650system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency 651system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency 653system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667 # average number of cycles each access was blocked |
| 658system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 658system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 659system.cpu.icache.fast_writes 0 # number of fast writes performed 660system.cpu.icache.cache_copies 0 # number of cache copies performed 661system.cpu.icache.writebacks::writebacks 238 # number of writebacks 662system.cpu.icache.writebacks::total 238 # number of writebacks 663system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59750 # number of ReadReq MSHR hits 664system.cpu.icache.ReadReq_mshr_hits::total 59750 # number of ReadReq MSHR hits 665system.cpu.icache.demand_mshr_hits::cpu.inst 59750 # number of demand (read+write) MSHR hits 666system.cpu.icache.demand_mshr_hits::total 59750 # number of demand (read+write) MSHR hits --- 242 unchanged lines hidden --- | 659system.cpu.icache.fast_writes 0 # number of fast writes performed 660system.cpu.icache.cache_copies 0 # number of cache copies performed 661system.cpu.icache.writebacks::writebacks 238 # number of writebacks 662system.cpu.icache.writebacks::total 238 # number of writebacks 663system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59750 # number of ReadReq MSHR hits 664system.cpu.icache.ReadReq_mshr_hits::total 59750 # number of ReadReq MSHR hits 665system.cpu.icache.demand_mshr_hits::cpu.inst 59750 # number of demand (read+write) MSHR hits 666system.cpu.icache.demand_mshr_hits::total 59750 # number of demand (read+write) MSHR hits --- 242 unchanged lines hidden --- |