| stats.txt (8835:7c68f84d7c4e) | stats.txt (8844:a451e4eda591) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.859851 # Number of seconds simulated 4sim_ticks 1859850554500 # Number of ticks simulated 5final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.858684 # Number of seconds simulated 4sim_ticks 1858684403000 # Number of ticks simulated 5final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 188989 # Simulator instruction rate (inst/s) 8host_op_rate 188989 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6621174751 # Simulator tick rate (ticks/s) 10host_mem_usage 292896 # Number of bytes of host memory used 11host_seconds 280.89 # Real time elapsed on the host 12sim_insts 53085804 # Number of instructions simulated 13sim_ops 53085804 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 29820864 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10193536 # Number of bytes written to this memory 17system.physmem.num_reads 465951 # Number of read requests responded to by this memory 18system.physmem.num_writes 159274 # Number of write requests responded to by this memory | 7host_inst_rate 192280 # Simulator instruction rate (inst/s) 8host_op_rate 192280 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6731751609 # Simulator tick rate (ticks/s) 10host_mem_usage 292636 # Number of bytes of host memory used 11host_seconds 276.11 # Real time elapsed on the host 12sim_insts 53089851 # Number of instructions simulated 13sim_ops 53089851 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 29847552 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1082432 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10195968 # Number of bytes written to this memory 17system.physmem.num_reads 466368 # Number of read requests responded to by this memory 18system.physmem.num_writes 159312 # Number of write requests responded to by this memory |
| 19system.physmem.num_other 0 # Number of other requests responded to by this memory | 19system.physmem.num_other 0 # Number of other requests responded to by this memory |
| 20system.physmem.bw_read 16034011 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 572089 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 5480836 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 21514847 # Total bandwidth to/from this memory (bytes/s) 24system.l2c.replacements 391353 # number of replacements 25system.l2c.tagsinuse 34925.820021 # Cycle average of tags in use 26system.l2c.total_refs 2406767 # Total number of references to valid blocks. 27system.l2c.sampled_refs 424249 # Sample count of references to valid blocks. 28system.l2c.avg_refs 5.673006 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 22620.354669 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu.inst 4081.669847 # Average occupied blocks per requestor 32system.l2c.occ_blocks::cpu.data 8223.795506 # Average occupied blocks per requestor 33system.l2c.occ_percent::writebacks 0.345159 # Average percentage of cache occupancy 34system.l2c.occ_percent::cpu.inst 0.062281 # Average percentage of cache occupancy 35system.l2c.occ_percent::cpu.data 0.125485 # Average percentage of cache occupancy 36system.l2c.occ_percent::total 0.532926 # Average percentage of cache occupancy 37system.l2c.ReadReq_hits::cpu.inst 988583 # number of ReadReq hits 38system.l2c.ReadReq_hits::cpu.data 812181 # number of ReadReq hits 39system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits 40system.l2c.Writeback_hits::writebacks 835189 # number of Writeback hits 41system.l2c.Writeback_hits::total 835189 # number of Writeback hits 42system.l2c.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits 43system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits | 20system.physmem.bw_read 16058429 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 582365 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 5485583 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 21544012 # Total bandwidth to/from this memory (bytes/s) 24system.l2c.replacements 391653 # number of replacements 25system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use 26system.l2c.total_refs 2427420 # Total number of references to valid blocks. 27system.l2c.sampled_refs 424662 # Sample count of references to valid blocks. 28system.l2c.avg_refs 5.716122 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 5620155000 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 22664.143946 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu.inst 4133.885317 # Average occupied blocks per requestor 32system.l2c.occ_blocks::cpu.data 8135.052193 # Average occupied blocks per requestor 33system.l2c.occ_percent::writebacks 0.345827 # Average percentage of cache occupancy 34system.l2c.occ_percent::cpu.inst 0.063078 # Average percentage of cache occupancy 35system.l2c.occ_percent::cpu.data 0.124131 # Average percentage of cache occupancy 36system.l2c.occ_percent::total 0.533037 # Average percentage of cache occupancy 37system.l2c.ReadReq_hits::cpu.inst 1009333 # number of ReadReq hits 38system.l2c.ReadReq_hits::cpu.data 810762 # number of ReadReq hits 39system.l2c.ReadReq_hits::total 1820095 # number of ReadReq hits 40system.l2c.Writeback_hits::writebacks 834721 # number of Writeback hits 41system.l2c.Writeback_hits::total 834721 # number of Writeback hits 42system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits 43system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits |
| 44system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 45system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits | 44system.l2c.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 45system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits |
| 46system.l2c.ReadExReq_hits::cpu.data 183241 # number of ReadExReq hits 47system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits 48system.l2c.demand_hits::cpu.inst 988583 # number of demand (read+write) hits 49system.l2c.demand_hits::cpu.data 995422 # number of demand (read+write) hits 50system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits 51system.l2c.overall_hits::cpu.inst 988583 # number of overall hits 52system.l2c.overall_hits::cpu.data 995422 # number of overall hits 53system.l2c.overall_hits::total 1984005 # number of overall hits 54system.l2c.ReadReq_misses::cpu.inst 16626 # number of ReadReq misses 55system.l2c.ReadReq_misses::cpu.data 291511 # number of ReadReq misses 56system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses 57system.l2c.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses 58system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses 59system.l2c.ReadExReq_misses::cpu.data 116889 # number of ReadExReq misses 60system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses 61system.l2c.demand_misses::cpu.inst 16626 # number of demand (read+write) misses 62system.l2c.demand_misses::cpu.data 408400 # number of demand (read+write) misses 63system.l2c.demand_misses::total 425026 # number of demand (read+write) misses 64system.l2c.overall_misses::cpu.inst 16626 # number of overall misses 65system.l2c.overall_misses::cpu.data 408400 # number of overall misses 66system.l2c.overall_misses::total 425026 # number of overall misses 67system.l2c.ReadReq_miss_latency::cpu.inst 869674000 # number of ReadReq miss cycles 68system.l2c.ReadReq_miss_latency::cpu.data 15168138500 # number of ReadReq miss cycles 69system.l2c.ReadReq_miss_latency::total 16037812500 # number of ReadReq miss cycles 70system.l2c.UpgradeReq_miss_latency::cpu.data 424500 # number of UpgradeReq miss cycles 71system.l2c.UpgradeReq_miss_latency::total 424500 # number of UpgradeReq miss cycles 72system.l2c.ReadExReq_miss_latency::cpu.data 6132457500 # number of ReadExReq miss cycles 73system.l2c.ReadExReq_miss_latency::total 6132457500 # number of ReadExReq miss cycles 74system.l2c.demand_miss_latency::cpu.inst 869674000 # number of demand (read+write) miss cycles 75system.l2c.demand_miss_latency::cpu.data 21300596000 # number of demand (read+write) miss cycles 76system.l2c.demand_miss_latency::total 22170270000 # number of demand (read+write) miss cycles 77system.l2c.overall_miss_latency::cpu.inst 869674000 # number of overall miss cycles 78system.l2c.overall_miss_latency::cpu.data 21300596000 # number of overall miss cycles 79system.l2c.overall_miss_latency::total 22170270000 # number of overall miss cycles 80system.l2c.ReadReq_accesses::cpu.inst 1005209 # number of ReadReq accesses(hits+misses) 81system.l2c.ReadReq_accesses::cpu.data 1103692 # number of ReadReq accesses(hits+misses) 82system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses) 83system.l2c.Writeback_accesses::writebacks 835189 # number of Writeback accesses(hits+misses) 84system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses) 85system.l2c.UpgradeReq_accesses::cpu.data 51 # number of UpgradeReq accesses(hits+misses) 86system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses) 87system.l2c.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 88system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 89system.l2c.ReadExReq_accesses::cpu.data 300130 # number of ReadExReq accesses(hits+misses) 90system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses) 91system.l2c.demand_accesses::cpu.inst 1005209 # number of demand (read+write) accesses 92system.l2c.demand_accesses::cpu.data 1403822 # number of demand (read+write) accesses 93system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses 94system.l2c.overall_accesses::cpu.inst 1005209 # number of overall (read+write) accesses 95system.l2c.overall_accesses::cpu.data 1403822 # number of overall (read+write) accesses 96system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses 97system.l2c.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses 98system.l2c.ReadReq_miss_rate::cpu.data 0.264124 # miss rate for ReadReq accesses 99system.l2c.UpgradeReq_miss_rate::cpu.data 0.686275 # miss rate for UpgradeReq accesses 100system.l2c.ReadExReq_miss_rate::cpu.data 0.389461 # miss rate for ReadExReq accesses 101system.l2c.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses 102system.l2c.demand_miss_rate::cpu.data 0.290920 # miss rate for demand accesses 103system.l2c.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses 104system.l2c.overall_miss_rate::cpu.data 0.290920 # miss rate for overall accesses 105system.l2c.ReadReq_avg_miss_latency::cpu.inst 52308.071695 # average ReadReq miss latency 106system.l2c.ReadReq_avg_miss_latency::cpu.data 52032.816943 # average ReadReq miss latency 107system.l2c.UpgradeReq_avg_miss_latency::cpu.data 12128.571429 # average UpgradeReq miss latency 108system.l2c.ReadExReq_avg_miss_latency::cpu.data 52463.940148 # average ReadExReq miss latency 109system.l2c.demand_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency 110system.l2c.demand_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency 111system.l2c.overall_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency 112system.l2c.overall_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency | 46system.l2c.ReadExReq_hits::cpu.data 183748 # number of ReadExReq hits 47system.l2c.ReadExReq_hits::total 183748 # number of ReadExReq hits 48system.l2c.demand_hits::cpu.inst 1009333 # number of demand (read+write) hits 49system.l2c.demand_hits::cpu.data 994510 # number of demand (read+write) hits 50system.l2c.demand_hits::total 2003843 # number of demand (read+write) hits 51system.l2c.overall_hits::cpu.inst 1009333 # number of overall hits 52system.l2c.overall_hits::cpu.data 994510 # number of overall hits 53system.l2c.overall_hits::total 2003843 # number of overall hits 54system.l2c.ReadReq_misses::cpu.inst 16915 # number of ReadReq misses 55system.l2c.ReadReq_misses::cpu.data 291468 # number of ReadReq misses 56system.l2c.ReadReq_misses::total 308383 # number of ReadReq misses 57system.l2c.UpgradeReq_misses::cpu.data 32 # number of UpgradeReq misses 58system.l2c.UpgradeReq_misses::total 32 # number of UpgradeReq misses 59system.l2c.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 60system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 61system.l2c.ReadExReq_misses::cpu.data 117029 # number of ReadExReq misses 62system.l2c.ReadExReq_misses::total 117029 # number of ReadExReq misses 63system.l2c.demand_misses::cpu.inst 16915 # number of demand (read+write) misses 64system.l2c.demand_misses::cpu.data 408497 # number of demand (read+write) misses 65system.l2c.demand_misses::total 425412 # number of demand (read+write) misses 66system.l2c.overall_misses::cpu.inst 16915 # number of overall misses 67system.l2c.overall_misses::cpu.data 408497 # number of overall misses 68system.l2c.overall_misses::total 425412 # number of overall misses 69system.l2c.ReadReq_miss_latency::cpu.inst 884741000 # number of ReadReq miss cycles 70system.l2c.ReadReq_miss_latency::cpu.data 15168191000 # number of ReadReq miss cycles 71system.l2c.ReadReq_miss_latency::total 16052932000 # number of ReadReq miss cycles 72system.l2c.UpgradeReq_miss_latency::cpu.data 425500 # number of UpgradeReq miss cycles 73system.l2c.UpgradeReq_miss_latency::total 425500 # number of UpgradeReq miss cycles 74system.l2c.ReadExReq_miss_latency::cpu.data 6138440500 # number of ReadExReq miss cycles 75system.l2c.ReadExReq_miss_latency::total 6138440500 # number of ReadExReq miss cycles 76system.l2c.demand_miss_latency::cpu.inst 884741000 # number of demand (read+write) miss cycles 77system.l2c.demand_miss_latency::cpu.data 21306631500 # number of demand (read+write) miss cycles 78system.l2c.demand_miss_latency::total 22191372500 # number of demand (read+write) miss cycles 79system.l2c.overall_miss_latency::cpu.inst 884741000 # number of overall miss cycles 80system.l2c.overall_miss_latency::cpu.data 21306631500 # number of overall miss cycles 81system.l2c.overall_miss_latency::total 22191372500 # number of overall miss cycles 82system.l2c.ReadReq_accesses::cpu.inst 1026248 # number of ReadReq accesses(hits+misses) 83system.l2c.ReadReq_accesses::cpu.data 1102230 # number of ReadReq accesses(hits+misses) 84system.l2c.ReadReq_accesses::total 2128478 # number of ReadReq accesses(hits+misses) 85system.l2c.Writeback_accesses::writebacks 834721 # number of Writeback accesses(hits+misses) 86system.l2c.Writeback_accesses::total 834721 # number of Writeback accesses(hits+misses) 87system.l2c.UpgradeReq_accesses::cpu.data 47 # number of UpgradeReq accesses(hits+misses) 88system.l2c.UpgradeReq_accesses::total 47 # number of UpgradeReq accesses(hits+misses) 89system.l2c.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) 90system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) 91system.l2c.ReadExReq_accesses::cpu.data 300777 # number of ReadExReq accesses(hits+misses) 92system.l2c.ReadExReq_accesses::total 300777 # number of ReadExReq accesses(hits+misses) 93system.l2c.demand_accesses::cpu.inst 1026248 # number of demand (read+write) accesses 94system.l2c.demand_accesses::cpu.data 1403007 # number of demand (read+write) accesses 95system.l2c.demand_accesses::total 2429255 # number of demand (read+write) accesses 96system.l2c.overall_accesses::cpu.inst 1026248 # number of overall (read+write) accesses 97system.l2c.overall_accesses::cpu.data 1403007 # number of overall (read+write) accesses 98system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses 99system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses 100system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses 101system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses 102system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses 103system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses 104system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses 105system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses 106system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses 107system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses 108system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency 109system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency 110system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency 111system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency 112system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency 113system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency 114system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency 115system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency |
| 113system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 114system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 115system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 116system.l2c.blocked::no_targets 0 # number of cycles access was blocked 117system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 118system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 119system.l2c.fast_writes 0 # number of fast writes performed 120system.l2c.cache_copies 0 # number of cache copies performed | 116system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 119system.l2c.blocked::no_targets 0 # number of cycles access was blocked 120system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 121system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 122system.l2c.fast_writes 0 # number of fast writes performed 123system.l2c.cache_copies 0 # number of cache copies performed |
| 121system.l2c.writebacks::writebacks 117762 # number of writebacks 122system.l2c.writebacks::total 117762 # number of writebacks 123system.l2c.ReadReq_mshr_misses::cpu.inst 16626 # number of ReadReq MSHR misses 124system.l2c.ReadReq_mshr_misses::cpu.data 291511 # number of ReadReq MSHR misses 125system.l2c.ReadReq_mshr_misses::total 308137 # number of ReadReq MSHR misses 126system.l2c.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses 127system.l2c.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses 128system.l2c.ReadExReq_mshr_misses::cpu.data 116889 # number of ReadExReq MSHR misses 129system.l2c.ReadExReq_mshr_misses::total 116889 # number of ReadExReq MSHR misses 130system.l2c.demand_mshr_misses::cpu.inst 16626 # number of demand (read+write) MSHR misses 131system.l2c.demand_mshr_misses::cpu.data 408400 # number of demand (read+write) MSHR misses 132system.l2c.demand_mshr_misses::total 425026 # number of demand (read+write) MSHR misses 133system.l2c.overall_mshr_misses::cpu.inst 16626 # number of overall MSHR misses 134system.l2c.overall_mshr_misses::cpu.data 408400 # number of overall MSHR misses 135system.l2c.overall_mshr_misses::total 425026 # number of overall MSHR misses 136system.l2c.ReadReq_mshr_miss_latency::cpu.inst 666148500 # number of ReadReq MSHR miss cycles 137system.l2c.ReadReq_mshr_miss_latency::cpu.data 11667923000 # number of ReadReq MSHR miss cycles 138system.l2c.ReadReq_mshr_miss_latency::total 12334071500 # number of ReadReq MSHR miss cycles 139system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1460000 # number of UpgradeReq MSHR miss cycles 140system.l2c.UpgradeReq_mshr_miss_latency::total 1460000 # number of UpgradeReq MSHR miss cycles 141system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4711233500 # number of ReadExReq MSHR miss cycles 142system.l2c.ReadExReq_mshr_miss_latency::total 4711233500 # number of ReadExReq MSHR miss cycles 143system.l2c.demand_mshr_miss_latency::cpu.inst 666148500 # number of demand (read+write) MSHR miss cycles 144system.l2c.demand_mshr_miss_latency::cpu.data 16379156500 # number of demand (read+write) MSHR miss cycles 145system.l2c.demand_mshr_miss_latency::total 17045305000 # number of demand (read+write) MSHR miss cycles 146system.l2c.overall_mshr_miss_latency::cpu.inst 666148500 # number of overall MSHR miss cycles 147system.l2c.overall_mshr_miss_latency::cpu.data 16379156500 # number of overall MSHR miss cycles 148system.l2c.overall_mshr_miss_latency::total 17045305000 # number of overall MSHR miss cycles 149system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809589500 # number of ReadReq MSHR uncacheable cycles 150system.l2c.ReadReq_mshr_uncacheable_latency::total 809589500 # number of ReadReq MSHR uncacheable cycles 151system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114928998 # number of WriteReq MSHR uncacheable cycles 152system.l2c.WriteReq_mshr_uncacheable_latency::total 1114928998 # number of WriteReq MSHR uncacheable cycles 153system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924518498 # number of overall MSHR uncacheable cycles 154system.l2c.overall_mshr_uncacheable_latency::total 1924518498 # number of overall MSHR uncacheable cycles 155system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses 156system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264124 # mshr miss rate for ReadReq accesses 157system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.686275 # mshr miss rate for UpgradeReq accesses 158system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389461 # mshr miss rate for ReadExReq accesses 159system.l2c.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses 160system.l2c.demand_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for demand accesses 161system.l2c.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses 162system.l2c.overall_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for overall accesses 163system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.672681 # average ReadReq mshr miss latency 164system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40025.669700 # average ReadReq mshr miss latency 165system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41714.285714 # average UpgradeReq mshr miss latency 166system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40305.191250 # average ReadExReq mshr miss latency 167system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency 168system.l2c.demand_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency 169system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency 170system.l2c.overall_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency | 124system.l2c.writebacks::writebacks 117800 # number of writebacks 125system.l2c.writebacks::total 117800 # number of writebacks 126system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 127system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 128system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 129system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 130system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 131system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 132system.l2c.ReadReq_mshr_misses::cpu.inst 16914 # number of ReadReq MSHR misses 133system.l2c.ReadReq_mshr_misses::cpu.data 291468 # number of ReadReq MSHR misses 134system.l2c.ReadReq_mshr_misses::total 308382 # number of ReadReq MSHR misses 135system.l2c.UpgradeReq_mshr_misses::cpu.data 32 # number of UpgradeReq MSHR misses 136system.l2c.UpgradeReq_mshr_misses::total 32 # number of UpgradeReq MSHR misses 137system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 138system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 139system.l2c.ReadExReq_mshr_misses::cpu.data 117029 # number of ReadExReq MSHR misses 140system.l2c.ReadExReq_mshr_misses::total 117029 # number of ReadExReq MSHR misses 141system.l2c.demand_mshr_misses::cpu.inst 16914 # number of demand (read+write) MSHR misses 142system.l2c.demand_mshr_misses::cpu.data 408497 # number of demand (read+write) MSHR misses 143system.l2c.demand_mshr_misses::total 425411 # number of demand (read+write) MSHR misses 144system.l2c.overall_mshr_misses::cpu.inst 16914 # number of overall MSHR misses 145system.l2c.overall_mshr_misses::cpu.data 408497 # number of overall MSHR misses 146system.l2c.overall_mshr_misses::total 425411 # number of overall MSHR misses 147system.l2c.ReadReq_mshr_miss_latency::cpu.inst 677644000 # number of ReadReq MSHR miss cycles 148system.l2c.ReadReq_mshr_miss_latency::cpu.data 11668187500 # number of ReadReq MSHR miss cycles 149system.l2c.ReadReq_mshr_miss_latency::total 12345831500 # number of ReadReq MSHR miss cycles 150system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1343000 # number of UpgradeReq MSHR miss cycles 151system.l2c.UpgradeReq_mshr_miss_latency::total 1343000 # number of UpgradeReq MSHR miss cycles 152system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 40000 # number of SCUpgradeReq MSHR miss cycles 153system.l2c.SCUpgradeReq_mshr_miss_latency::total 40000 # number of SCUpgradeReq MSHR miss cycles 154system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4714582500 # number of ReadExReq MSHR miss cycles 155system.l2c.ReadExReq_mshr_miss_latency::total 4714582500 # number of ReadExReq MSHR miss cycles 156system.l2c.demand_mshr_miss_latency::cpu.inst 677644000 # number of demand (read+write) MSHR miss cycles 157system.l2c.demand_mshr_miss_latency::cpu.data 16382770000 # number of demand (read+write) MSHR miss cycles 158system.l2c.demand_mshr_miss_latency::total 17060414000 # number of demand (read+write) MSHR miss cycles 159system.l2c.overall_mshr_miss_latency::cpu.inst 677644000 # number of overall MSHR miss cycles 160system.l2c.overall_mshr_miss_latency::cpu.data 16382770000 # number of overall MSHR miss cycles 161system.l2c.overall_mshr_miss_latency::total 17060414000 # number of overall MSHR miss cycles 162system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809666500 # number of ReadReq MSHR uncacheable cycles 163system.l2c.ReadReq_mshr_uncacheable_latency::total 809666500 # number of ReadReq MSHR uncacheable cycles 164system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114488498 # number of WriteReq MSHR uncacheable cycles 165system.l2c.WriteReq_mshr_uncacheable_latency::total 1114488498 # number of WriteReq MSHR uncacheable cycles 166system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998 # number of overall MSHR uncacheable cycles 167system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles 168system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses 169system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses 170system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses 171system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses 172system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses 173system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses 174system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses 175system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses 176system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses 177system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency 178system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency 179system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency 180system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 181system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency 182system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency 183system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency 184system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency 185system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency |
| 171system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 172system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 173system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 174system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 175system.iocache.replacements 41685 # number of replacements | 186system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 187system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 188system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 189system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 190system.iocache.replacements 41685 # number of replacements |
| 176system.iocache.tagsinuse 1.276011 # Cycle average of tags in use | 191system.iocache.tagsinuse 1.266745 # Cycle average of tags in use |
| 177system.iocache.total_refs 0 # Total number of references to valid blocks. 178system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 179system.iocache.avg_refs 0 # Average number of references to valid blocks. | 192system.iocache.total_refs 0 # Total number of references to valid blocks. 193system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 194system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 180system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit. 181system.iocache.occ_blocks::tsunami.ide 1.276011 # Average occupied blocks per requestor 182system.iocache.occ_percent::tsunami.ide 0.079751 # Average percentage of cache occupancy 183system.iocache.occ_percent::total 0.079751 # Average percentage of cache occupancy | 195system.iocache.warmup_cycle 1708341003000 # Cycle when the warmup percentage was hit. 196system.iocache.occ_blocks::tsunami.ide 1.266745 # Average occupied blocks per requestor 197system.iocache.occ_percent::tsunami.ide 0.079172 # Average percentage of cache occupancy 198system.iocache.occ_percent::total 0.079172 # Average percentage of cache occupancy |
| 184system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 185system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 186system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 187system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 188system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 189system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 190system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 191system.iocache.overall_misses::total 41725 # number of overall misses 192system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles 193system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles | 199system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 200system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 201system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 202system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 203system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 204system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 205system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 206system.iocache.overall_misses::total 41725 # number of overall misses 207system.iocache.ReadReq_miss_latency::tsunami.ide 19937998 # number of ReadReq miss cycles 208system.iocache.ReadReq_miss_latency::total 19937998 # number of ReadReq miss cycles |
| 194system.iocache.WriteReq_miss_latency::tsunami.ide 5721891806 # number of WriteReq miss cycles 195system.iocache.WriteReq_miss_latency::total 5721891806 # number of WriteReq miss cycles 196system.iocache.demand_miss_latency::tsunami.ide 5741829804 # number of demand (read+write) miss cycles 197system.iocache.demand_miss_latency::total 5741829804 # number of demand (read+write) miss cycles 198system.iocache.overall_miss_latency::tsunami.ide 5741829804 # number of overall miss cycles 199system.iocache.overall_miss_latency::total 5741829804 # number of overall miss cycles | 209system.iocache.WriteReq_miss_latency::tsunami.ide 5721838806 # number of WriteReq miss cycles 210system.iocache.WriteReq_miss_latency::total 5721838806 # number of WriteReq miss cycles 211system.iocache.demand_miss_latency::tsunami.ide 5741776804 # number of demand (read+write) miss cycles 212system.iocache.demand_miss_latency::total 5741776804 # number of demand (read+write) miss cycles 213system.iocache.overall_miss_latency::tsunami.ide 5741776804 # number of overall miss cycles 214system.iocache.overall_miss_latency::total 5741776804 # number of overall miss cycles |
| 200system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 201system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 202system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 203system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 204system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 205system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 206system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 207system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 208system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 209system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 210system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 211system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 212system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency | 215system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 216system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 217system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 218system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 219system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 220system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 221system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 222system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 223system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 224system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 225system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 226system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 227system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353 # average ReadReq miss latency |
| 213system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.365759 # average WriteReq miss latency 214system.iocache.demand_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency 215system.iocache.overall_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency 216system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked | 228system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency 229system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency 230system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency 231system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked |
| 217system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 232system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 218system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked | 233system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked |
| 219system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 234system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 220system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # average number of cycles each access was blocked | 235system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked |
| 221system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 222system.iocache.fast_writes 0 # number of fast writes performed 223system.iocache.cache_copies 0 # number of cache copies performed 224system.iocache.writebacks::writebacks 41512 # number of writebacks 225system.iocache.writebacks::total 41512 # number of writebacks 226system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 227system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 228system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 229system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 230system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 231system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 232system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 233system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 234system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles 235system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles | 236system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 237system.iocache.fast_writes 0 # number of fast writes performed 238system.iocache.cache_copies 0 # number of cache copies performed 239system.iocache.writebacks::writebacks 41512 # number of writebacks 240system.iocache.writebacks::total 41512 # number of writebacks 241system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 242system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 243system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 244system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 245system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 246system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 247system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 248system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 249system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10941998 # number of ReadReq MSHR miss cycles 250system.iocache.ReadReq_mshr_miss_latency::total 10941998 # number of ReadReq MSHR miss cycles |
| 236system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561041984 # number of WriteReq MSHR miss cycles 237system.iocache.WriteReq_mshr_miss_latency::total 3561041984 # number of WriteReq MSHR miss cycles 238system.iocache.demand_mshr_miss_latency::tsunami.ide 3571983982 # number of demand (read+write) MSHR miss cycles 239system.iocache.demand_mshr_miss_latency::total 3571983982 # number of demand (read+write) MSHR miss cycles 240system.iocache.overall_mshr_miss_latency::tsunami.ide 3571983982 # number of overall MSHR miss cycles 241system.iocache.overall_mshr_miss_latency::total 3571983982 # number of overall MSHR miss cycles | 251system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560986994 # number of WriteReq MSHR miss cycles 252system.iocache.WriteReq_mshr_miss_latency::total 3560986994 # number of WriteReq MSHR miss cycles 253system.iocache.demand_mshr_miss_latency::tsunami.ide 3571928992 # number of demand (read+write) MSHR miss cycles 254system.iocache.demand_mshr_miss_latency::total 3571928992 # number of demand (read+write) MSHR miss cycles 255system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles 256system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles |
| 242system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 243system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 244system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 245system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 246system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency | 257system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 258system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 259system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 260system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 261system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353 # average ReadReq mshr miss latency |
| 247system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85700.856373 # average WriteReq mshr miss latency 248system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency 249system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency | 262system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency 263system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency 264system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency |
| 250system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 251system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 252system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 253system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 254system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 255system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 256system.disk0.dma_write_txs 395 # Number of DMA write transactions. 257system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 258system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 259system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 260system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 261system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 262system.disk2.dma_write_txs 1 # Number of DMA write transactions. 263system.cpu.dtb.fetch_hits 0 # ITB hits 264system.cpu.dtb.fetch_misses 0 # ITB misses 265system.cpu.dtb.fetch_acv 0 # ITB acv 266system.cpu.dtb.fetch_accesses 0 # ITB accesses | 265system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 266system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 267system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 268system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 269system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 270system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 271system.disk0.dma_write_txs 395 # Number of DMA write transactions. 272system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 273system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 274system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 275system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 276system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 277system.disk2.dma_write_txs 1 # Number of DMA write transactions. 278system.cpu.dtb.fetch_hits 0 # ITB hits 279system.cpu.dtb.fetch_misses 0 # ITB misses 280system.cpu.dtb.fetch_acv 0 # ITB acv 281system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 267system.cpu.dtb.read_hits 10136178 # DTB read hits 268system.cpu.dtb.read_misses 46729 # DTB read misses 269system.cpu.dtb.read_acv 584 # DTB read access violations 270system.cpu.dtb.read_accesses 970980 # DTB read accesses 271system.cpu.dtb.write_hits 6626287 # DTB write hits 272system.cpu.dtb.write_misses 12218 # DTB write misses 273system.cpu.dtb.write_acv 419 # DTB write access violations 274system.cpu.dtb.write_accesses 347267 # DTB write accesses 275system.cpu.dtb.data_hits 16762465 # DTB hits 276system.cpu.dtb.data_misses 58947 # DTB misses 277system.cpu.dtb.data_acv 1003 # DTB access violations 278system.cpu.dtb.data_accesses 1318247 # DTB accesses 279system.cpu.itb.fetch_hits 1326719 # ITB hits 280system.cpu.itb.fetch_misses 39613 # ITB misses 281system.cpu.itb.fetch_acv 1063 # ITB acv 282system.cpu.itb.fetch_accesses 1366332 # ITB accesses | 282system.cpu.dtb.read_hits 10017178 # DTB read hits 283system.cpu.dtb.read_misses 45828 # DTB read misses 284system.cpu.dtb.read_acv 561 # DTB read access violations 285system.cpu.dtb.read_accesses 954843 # DTB read accesses 286system.cpu.dtb.write_hits 6639084 # DTB write hits 287system.cpu.dtb.write_misses 10800 # DTB write misses 288system.cpu.dtb.write_acv 415 # DTB write access violations 289system.cpu.dtb.write_accesses 340295 # DTB write accesses 290system.cpu.dtb.data_hits 16656262 # DTB hits 291system.cpu.dtb.data_misses 56628 # DTB misses 292system.cpu.dtb.data_acv 976 # DTB access violations 293system.cpu.dtb.data_accesses 1295138 # DTB accesses 294system.cpu.itb.fetch_hits 1345400 # ITB hits 295system.cpu.itb.fetch_misses 36691 # ITB misses 296system.cpu.itb.fetch_acv 1385 # ITB acv 297system.cpu.itb.fetch_accesses 1382091 # ITB accesses |
| 283system.cpu.itb.read_hits 0 # DTB read hits 284system.cpu.itb.read_misses 0 # DTB read misses 285system.cpu.itb.read_acv 0 # DTB read access violations 286system.cpu.itb.read_accesses 0 # DTB read accesses 287system.cpu.itb.write_hits 0 # DTB write hits 288system.cpu.itb.write_misses 0 # DTB write misses 289system.cpu.itb.write_acv 0 # DTB write access violations 290system.cpu.itb.write_accesses 0 # DTB write accesses 291system.cpu.itb.data_hits 0 # DTB hits 292system.cpu.itb.data_misses 0 # DTB misses 293system.cpu.itb.data_acv 0 # DTB access violations 294system.cpu.itb.data_accesses 0 # DTB accesses | 298system.cpu.itb.read_hits 0 # DTB read hits 299system.cpu.itb.read_misses 0 # DTB read misses 300system.cpu.itb.read_acv 0 # DTB read access violations 301system.cpu.itb.read_accesses 0 # DTB read accesses 302system.cpu.itb.write_hits 0 # DTB write hits 303system.cpu.itb.write_misses 0 # DTB write misses 304system.cpu.itb.write_acv 0 # DTB write access violations 305system.cpu.itb.write_accesses 0 # DTB write accesses 306system.cpu.itb.data_hits 0 # DTB hits 307system.cpu.itb.data_misses 0 # DTB misses 308system.cpu.itb.data_acv 0 # DTB access violations 309system.cpu.itb.data_accesses 0 # DTB accesses |
| 295system.cpu.numCycles 116271514 # number of cpu cycles simulated | 310system.cpu.numCycles 115937106 # number of cpu cycles simulated |
| 296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 311system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 312system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 298system.cpu.BPredUnit.lookups 14404381 # Number of BP lookups 299system.cpu.BPredUnit.condPredicted 12049368 # Number of conditional branches predicted 300system.cpu.BPredUnit.condIncorrect 531407 # Number of conditional branches incorrect 301system.cpu.BPredUnit.BTBLookups 13004312 # Number of BTB lookups 302system.cpu.BPredUnit.BTBHits 6709840 # Number of BTB hits | 313system.cpu.BPredUnit.lookups 14171679 # Number of BP lookups 314system.cpu.BPredUnit.condPredicted 11793956 # Number of conditional branches predicted 315system.cpu.BPredUnit.condIncorrect 477051 # Number of conditional branches incorrect 316system.cpu.BPredUnit.BTBLookups 10388735 # Number of BTB lookups 317system.cpu.BPredUnit.BTBHits 5970315 # Number of BTB hits |
| 303system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 318system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 304system.cpu.BPredUnit.usedRAS 971693 # Number of times the RAS was used to get a target. 305system.cpu.BPredUnit.RASInCorrect 45037 # Number of incorrect RAS predictions. 306system.cpu.fetch.icacheStallCycles 29087793 # Number of cycles fetch is stalled on an Icache miss 307system.cpu.fetch.Insts 73522129 # Number of instructions fetch has processed 308system.cpu.fetch.Branches 14404381 # Number of branches that fetch encountered 309system.cpu.fetch.predictedBranches 7681533 # Number of branches that fetch has predicted taken 310system.cpu.fetch.Cycles 14275065 # Number of cycles fetch has run and was not squashing or blocked 311system.cpu.fetch.SquashCycles 2363223 # Number of cycles fetch has spent squashing 312system.cpu.fetch.BlockedCycles 36625670 # Number of cycles fetch has spent blocked 313system.cpu.fetch.MiscStallCycles 33401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 314system.cpu.fetch.PendingTrapStallCycles 258943 # Number of stall cycles due to pending traps 315system.cpu.fetch.PendingQuiesceStallCycles 335385 # Number of stall cycles due to pending quiesce instructions 316system.cpu.fetch.IcacheWaitRetryStallCycles 155 # Number of stall cycles due to full MSHR 317system.cpu.fetch.CacheLines 9051216 # Number of cache lines fetched 318system.cpu.fetch.IcacheSquashes 322280 # Number of outstanding Icache misses that were squashed 319system.cpu.fetch.rateDist::samples 82158877 # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::mean 0.894877 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::stdev 2.211744 # Number of instructions fetched each cycle (Total) | 319system.cpu.BPredUnit.usedRAS 956584 # Number of times the RAS was used to get a target. 320system.cpu.BPredUnit.RASInCorrect 68437 # Number of incorrect RAS predictions. 321system.cpu.fetch.icacheStallCycles 29509897 # Number of cycles fetch is stalled on an Icache miss 322system.cpu.fetch.Insts 72276663 # Number of instructions fetch has processed 323system.cpu.fetch.Branches 14171679 # Number of branches that fetch encountered 324system.cpu.fetch.predictedBranches 6926899 # Number of branches that fetch has predicted taken 325system.cpu.fetch.Cycles 13625760 # Number of cycles fetch has run and was not squashing or blocked 326system.cpu.fetch.SquashCycles 2211095 # Number of cycles fetch has spent squashing 327system.cpu.fetch.BlockedCycles 36451359 # Number of cycles fetch has spent blocked 328system.cpu.fetch.MiscStallCycles 33988 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 329system.cpu.fetch.PendingTrapStallCycles 254368 # Number of stall cycles due to pending traps 330system.cpu.fetch.PendingQuiesceStallCycles 318126 # Number of stall cycles due to pending quiesce instructions 331system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR 332system.cpu.fetch.CacheLines 9001683 # Number of cache lines fetched 333system.cpu.fetch.IcacheSquashes 320234 # Number of outstanding Icache misses that were squashed 334system.cpu.fetch.rateDist::samples 81638301 # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::mean 0.885328 # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::stdev 2.224856 # Number of instructions fetched each cycle (Total) |
| 322system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 337system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 323system.cpu.fetch.rateDist::0 67883812 82.63% 82.63% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::1 1025449 1.25% 83.87% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::2 2024221 2.46% 86.34% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::3 965546 1.18% 87.51% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::4 2955118 3.60% 91.11% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::5 688428 0.84% 91.95% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::6 786197 0.96% 92.90% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::7 1069042 1.30% 94.21% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::8 4761064 5.79% 100.00% # Number of instructions fetched each cycle (Total) | 338system.cpu.fetch.rateDist::0 68012541 83.31% 83.31% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::1 890285 1.09% 84.40% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::2 1788287 2.19% 86.59% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::3 860446 1.05% 87.64% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::4 2806697 3.44% 91.08% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::5 613121 0.75% 91.83% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::6 690439 0.85% 92.68% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::7 1018441 1.25% 93.93% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::8 4958044 6.07% 100.00% # Number of instructions fetched each cycle (Total) |
| 332system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 347system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 335system.cpu.fetch.rateDist::total 82158877 # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.branchRate 0.123886 # Number of branch fetches per cycle 337system.cpu.fetch.rate 0.632331 # Number of inst fetches per cycle 338system.cpu.decode.IdleCycles 30342810 # Number of cycles decode is idle 339system.cpu.decode.BlockedCycles 36285765 # Number of cycles decode is blocked 340system.cpu.decode.RunCycles 13055396 # Number of cycles decode is running 341system.cpu.decode.UnblockCycles 974232 # Number of cycles decode is unblocking 342system.cpu.decode.SquashCycles 1500673 # Number of cycles decode is squashing 343system.cpu.decode.BranchResolved 609120 # Number of times decode resolved a branch 344system.cpu.decode.BranchMispred 42110 # Number of times decode detected a branch misprediction 345system.cpu.decode.DecodedInsts 71910719 # Number of instructions handled by decode 346system.cpu.decode.SquashedInsts 128198 # Number of squashed instructions handled by decode 347system.cpu.rename.SquashCycles 1500673 # Number of cycles rename is squashing 348system.cpu.rename.IdleCycles 31545269 # Number of cycles rename is idle 349system.cpu.rename.BlockCycles 12820046 # Number of cycles rename is blocking 350system.cpu.rename.serializeStallCycles 19759905 # count of cycles rename stalled for serializing inst 351system.cpu.rename.RunCycles 12205401 # Number of cycles rename is running 352system.cpu.rename.UnblockCycles 4327581 # Number of cycles rename is unblocking 353system.cpu.rename.RenamedInsts 67985937 # Number of instructions processed by rename 354system.cpu.rename.ROBFullEvents 6903 # Number of times rename has blocked due to ROB full 355system.cpu.rename.IQFullEvents 504868 # Number of times rename has blocked due to IQ full 356system.cpu.rename.LSQFullEvents 1537776 # Number of times rename has blocked due to LSQ full 357system.cpu.rename.RenamedOperands 45488593 # Number of destination operands rename has renamed 358system.cpu.rename.RenameLookups 82604485 # Number of register rename lookups that rename has made 359system.cpu.rename.int_rename_lookups 82125154 # Number of integer rename lookups 360system.cpu.rename.fp_rename_lookups 479331 # Number of floating rename lookups 361system.cpu.rename.CommittedMaps 38256265 # Number of HB maps that are committed 362system.cpu.rename.UndoneMaps 7232320 # Number of HB maps that are undone due to squashing 363system.cpu.rename.serializingInsts 1700161 # count of serializing insts renamed 364system.cpu.rename.tempSerializingInsts 251408 # count of temporary serializing insts renamed 365system.cpu.rename.skidInsts 12102195 # count of insts added to the skid buffer 366system.cpu.memDep0.insertedLoads 10719689 # Number of loads inserted to the mem dependence unit. 367system.cpu.memDep0.insertedStores 6992362 # Number of stores inserted to the mem dependence unit. 368system.cpu.memDep0.conflictingLoads 1255856 # Number of conflicting loads. 369system.cpu.memDep0.conflictingStores 835149 # Number of conflicting stores. 370system.cpu.iq.iqInstsAdded 59697251 # Number of instructions added to the IQ (excludes non-spec) 371system.cpu.iq.iqNonSpecInstsAdded 2115237 # Number of non-speculative instructions added to the IQ 372system.cpu.iq.iqInstsIssued 57966423 # Number of instructions issued 373system.cpu.iq.iqSquashedInstsIssued 118182 # Number of squashed instructions issued 374system.cpu.iq.iqSquashedInstsExamined 8327603 # Number of squashed instructions iterated over during squash; mainly for profiling 375system.cpu.iq.iqSquashedOperandsExamined 4293139 # Number of squashed operands that are examined and possibly removed from graph 376system.cpu.iq.iqSquashedNonSpecRemoved 1447692 # Number of squashed non-spec instructions that were removed 377system.cpu.iq.issued_per_cycle::samples 82158877 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::mean 0.705541 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::stdev 1.352283 # Number of insts issued each cycle | 350system.cpu.fetch.rateDist::total 81638301 # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.branchRate 0.122236 # Number of branch fetches per cycle 352system.cpu.fetch.rate 0.623413 # Number of inst fetches per cycle 353system.cpu.decode.IdleCycles 30605398 # Number of cycles decode is idle 354system.cpu.decode.BlockedCycles 36211579 # Number of cycles decode is blocked 355system.cpu.decode.RunCycles 12459009 # Number of cycles decode is running 356system.cpu.decode.UnblockCycles 962410 # Number of cycles decode is unblocking 357system.cpu.decode.SquashCycles 1399904 # Number of cycles decode is squashing 358system.cpu.decode.BranchResolved 626907 # Number of times decode resolved a branch 359system.cpu.decode.BranchMispred 46406 # Number of times decode detected a branch misprediction 360system.cpu.decode.DecodedInsts 70869283 # Number of instructions handled by decode 361system.cpu.decode.SquashedInsts 128122 # Number of squashed instructions handled by decode 362system.cpu.rename.SquashCycles 1399904 # Number of cycles rename is squashing 363system.cpu.rename.IdleCycles 31751021 # Number of cycles rename is idle 364system.cpu.rename.BlockCycles 12870145 # Number of cycles rename is blocking 365system.cpu.rename.serializeStallCycles 19629693 # count of cycles rename stalled for serializing inst 366system.cpu.rename.RunCycles 11657858 # Number of cycles rename is running 367system.cpu.rename.UnblockCycles 4329678 # Number of cycles rename is unblocking 368system.cpu.rename.RenamedInsts 67084686 # Number of instructions processed by rename 369system.cpu.rename.ROBFullEvents 6936 # Number of times rename has blocked due to ROB full 370system.cpu.rename.IQFullEvents 509202 # Number of times rename has blocked due to IQ full 371system.cpu.rename.LSQFullEvents 1545669 # Number of times rename has blocked due to LSQ full 372system.cpu.rename.RenamedOperands 44883895 # Number of destination operands rename has renamed 373system.cpu.rename.RenameLookups 81279618 # Number of register rename lookups that rename has made 374system.cpu.rename.int_rename_lookups 80782275 # Number of integer rename lookups 375system.cpu.rename.fp_rename_lookups 497343 # Number of floating rename lookups 376system.cpu.rename.CommittedMaps 38259023 # Number of HB maps that are committed 377system.cpu.rename.UndoneMaps 6624872 # Number of HB maps that are undone due to squashing 378system.cpu.rename.serializingInsts 1702108 # count of serializing insts renamed 379system.cpu.rename.tempSerializingInsts 250876 # count of temporary serializing insts renamed 380system.cpu.rename.skidInsts 12154886 # count of insts added to the skid buffer 381system.cpu.memDep0.insertedLoads 10647937 # Number of loads inserted to the mem dependence unit. 382system.cpu.memDep0.insertedStores 6996260 # Number of stores inserted to the mem dependence unit. 383system.cpu.memDep0.conflictingLoads 1317222 # Number of conflicting loads. 384system.cpu.memDep0.conflictingStores 890257 # Number of conflicting stores. 385system.cpu.iq.iqInstsAdded 59186479 # Number of instructions added to the IQ (excludes non-spec) 386system.cpu.iq.iqNonSpecInstsAdded 2094113 # Number of non-speculative instructions added to the IQ 387system.cpu.iq.iqInstsIssued 57496699 # Number of instructions issued 388system.cpu.iq.iqSquashedInstsIssued 116770 # Number of squashed instructions issued 389system.cpu.iq.iqSquashedInstsExamined 7805626 # Number of squashed instructions iterated over during squash; mainly for profiling 390system.cpu.iq.iqSquashedOperandsExamined 4020701 # Number of squashed operands that are examined and possibly removed from graph 391system.cpu.iq.iqSquashedNonSpecRemoved 1426389 # Number of squashed non-spec instructions that were removed 392system.cpu.iq.issued_per_cycle::samples 81638301 # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::mean 0.704286 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::stdev 1.361652 # Number of insts issued each cycle |
| 380system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 395system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 381system.cpu.iq.issued_per_cycle::0 56706238 69.02% 69.02% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::1 11186331 13.62% 82.64% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::2 5491014 6.68% 89.32% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::3 3497852 4.26% 93.58% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::4 2643618 3.22% 96.79% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::5 1562284 1.90% 98.70% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::6 690020 0.84% 99.54% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::7 273664 0.33% 99.87% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::8 107856 0.13% 100.00% # Number of insts issued each cycle | 396system.cpu.iq.issued_per_cycle::0 56549177 69.27% 69.27% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::1 11085908 13.58% 82.85% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::2 5246792 6.43% 89.27% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::3 3470006 4.25% 93.52% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::4 2637448 3.23% 96.76% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::5 1477237 1.81% 98.56% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::6 737523 0.90% 99.47% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::7 327606 0.40% 99.87% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::8 106604 0.13% 100.00% # Number of insts issued each cycle |
| 390system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 405system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 393system.cpu.iq.issued_per_cycle::total 82158877 # Number of insts issued each cycle | 408system.cpu.iq.issued_per_cycle::total 81638301 # Number of insts issued each cycle |
| 394system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 409system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 395system.cpu.iq.fu_full::IntAlu 66675 8.67% 8.67% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntMult 0 0.00% 8.67% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntDiv 0 0.00% 8.67% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.67% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.67% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.67% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatMult 0 0.00% 8.67% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.67% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.67% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.67% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.67% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.67% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.67% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.67% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.67% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMult 0 0.00% 8.67% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.67% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdShift 0 0.00% 8.67% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.67% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.67% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.67% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.67% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.67% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.67% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.67% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.67% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.67% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.67% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.67% # attempts to use FU when none available 424system.cpu.iq.fu_full::MemRead 379311 49.30% 57.96% # attempts to use FU when none available 425system.cpu.iq.fu_full::MemWrite 323479 42.04% 100.00% # attempts to use FU when none available | 410system.cpu.iq.fu_full::IntAlu 90136 11.38% 11.38% # attempts to use FU when none available 411system.cpu.iq.fu_full::IntMult 0 0.00% 11.38% # attempts to use FU when none available 412system.cpu.iq.fu_full::IntDiv 0 0.00% 11.38% # attempts to use FU when none available 413system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.38% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.38% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.38% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatMult 0 0.00% 11.38% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.38% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.38% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.38% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.38% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.38% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.38% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.38% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.38% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdMult 0 0.00% 11.38% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.38% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdShift 0 0.00% 11.38% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.38% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.38% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.38% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.38% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.38% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.38% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.38% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.38% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.38% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.38% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.38% # attempts to use FU when none available 439system.cpu.iq.fu_full::MemRead 378271 47.76% 59.14% # attempts to use FU when none available 440system.cpu.iq.fu_full::MemWrite 323650 40.86% 100.00% # attempts to use FU when none available |
| 426system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 427system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 428system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued | 441system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 442system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 443system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued |
| 429system.cpu.iq.FU_type_0::IntAlu 39589342 68.30% 68.31% # Type of FU issued 430system.cpu.iq.FU_type_0::IntMult 62143 0.11% 68.42% # Type of FU issued 431system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.42% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.47% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.47% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.47% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.47% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.47% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.47% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.47% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.47% # Type of FU issued 458system.cpu.iq.FU_type_0::MemRead 10612322 18.31% 86.77% # Type of FU issued 459system.cpu.iq.FU_type_0::MemWrite 6714161 11.58% 98.36% # Type of FU issued 460system.cpu.iq.FU_type_0::IprAccess 951931 1.64% 100.00% # Type of FU issued | 444system.cpu.iq.FU_type_0::IntAlu 39231645 68.23% 68.25% # Type of FU issued 445system.cpu.iq.FU_type_0::IntMult 61830 0.11% 68.35% # Type of FU issued 446system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.35% # Type of FU issued 447system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.40% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued 473system.cpu.iq.FU_type_0::MemRead 10492080 18.25% 86.65% # Type of FU issued 474system.cpu.iq.FU_type_0::MemWrite 6722416 11.69% 98.34% # Type of FU issued 475system.cpu.iq.FU_type_0::IprAccess 952204 1.66% 100.00% # Type of FU issued |
| 461system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 476system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 462system.cpu.iq.FU_type_0::total 57966423 # Type of FU issued 463system.cpu.iq.rate 0.498544 # Inst issue rate 464system.cpu.iq.fu_busy_cnt 769465 # FU busy when requested 465system.cpu.iq.fu_busy_rate 0.013274 # FU busy rate (busy events/executed inst) 466system.cpu.iq.int_inst_queue_reads 198287117 # Number of integer instruction queue reads 467system.cpu.iq.int_inst_queue_writes 69820873 # Number of integer instruction queue writes 468system.cpu.iq.int_inst_queue_wakeup_accesses 56409682 # Number of integer instruction queue wakeup accesses 469system.cpu.iq.fp_inst_queue_reads 692252 # Number of floating instruction queue reads 470system.cpu.iq.fp_inst_queue_writes 333301 # Number of floating instruction queue writes 471system.cpu.iq.fp_inst_queue_wakeup_accesses 328338 # Number of floating instruction queue wakeup accesses 472system.cpu.iq.int_alu_accesses 58365379 # Number of integer alu accesses 473system.cpu.iq.fp_alu_accesses 363228 # Number of floating point alu accesses 474system.cpu.iew.lsq.thread0.forwLoads 574200 # Number of loads that had data forwarded from stores | 477system.cpu.iq.FU_type_0::total 57496699 # Type of FU issued 478system.cpu.iq.rate 0.495930 # Inst issue rate 479system.cpu.iq.fu_busy_cnt 792057 # FU busy when requested 480system.cpu.iq.fu_busy_rate 0.013776 # FU busy rate (busy events/executed inst) 481system.cpu.iq.int_inst_queue_reads 196846794 # Number of integer instruction queue reads 482system.cpu.iq.int_inst_queue_writes 68765054 # Number of integer instruction queue writes 483system.cpu.iq.int_inst_queue_wakeup_accesses 56061076 # Number of integer instruction queue wakeup accesses 484system.cpu.iq.fp_inst_queue_reads 693732 # Number of floating instruction queue reads 485system.cpu.iq.fp_inst_queue_writes 333965 # Number of floating instruction queue writes 486system.cpu.iq.fp_inst_queue_wakeup_accesses 328206 # Number of floating instruction queue wakeup accesses 487system.cpu.iq.int_alu_accesses 57917538 # Number of integer alu accesses 488system.cpu.iq.fp_alu_accesses 363937 # Number of floating point alu accesses 489system.cpu.iew.lsq.thread0.forwLoads 590984 # Number of loads that had data forwarded from stores |
| 475system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 490system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 476system.cpu.iew.lsq.thread0.squashedLoads 1607370 # Number of loads squashed 477system.cpu.iew.lsq.thread0.ignoredResponses 13516 # Number of memory responses ignored because the instruction is squashed 478system.cpu.iew.lsq.thread0.memOrderViolation 14481 # Number of memory ordering violations 479system.cpu.iew.lsq.thread0.squashedStores 600235 # Number of stores squashed | 491system.cpu.iew.lsq.thread0.squashedLoads 1535089 # Number of loads squashed 492system.cpu.iew.lsq.thread0.ignoredResponses 3470 # Number of memory responses ignored because the instruction is squashed 493system.cpu.iew.lsq.thread0.memOrderViolation 13124 # Number of memory ordering violations 494system.cpu.iew.lsq.thread0.squashedStores 604028 # Number of stores squashed |
| 480system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 481system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 495system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 496system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 482system.cpu.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled 483system.cpu.iew.lsq.thread0.cacheBlocked 173076 # Number of times an access to memory failed due to the cache being blocked | 497system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled 498system.cpu.iew.lsq.thread0.cacheBlocked 170629 # Number of times an access to memory failed due to the cache being blocked |
| 484system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 499system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 485system.cpu.iew.iewSquashCycles 1500673 # Number of cycles IEW is squashing 486system.cpu.iew.iewBlockCycles 8975371 # Number of cycles IEW is blocking 487system.cpu.iew.iewUnblockCycles 617328 # Number of cycles IEW is unblocking 488system.cpu.iew.iewDispatchedInsts 65437961 # Number of instructions dispatched to IQ 489system.cpu.iew.iewDispSquashedInsts 865160 # Number of squashed instructions skipped by dispatch 490system.cpu.iew.iewDispLoadInsts 10719689 # Number of dispatched load instructions 491system.cpu.iew.iewDispStoreInsts 6992362 # Number of dispatched store instructions 492system.cpu.iew.iewDispNonSpecInsts 1868933 # Number of dispatched non-speculative instructions 493system.cpu.iew.iewIQFullEvents 485175 # Number of times the IQ has become full, causing a stall 494system.cpu.iew.iewLSQFullEvents 15743 # Number of times the LSQ has become full, causing a stall 495system.cpu.iew.memOrderViolationEvents 14481 # Number of memory order violations 496system.cpu.iew.predictedTakenIncorrect 386643 # Number of branches that were predicted taken incorrectly 497system.cpu.iew.predictedNotTakenIncorrect 382870 # Number of branches that were predicted not taken incorrectly 498system.cpu.iew.branchMispredicts 769513 # Number of branch mispredicts detected at execute 499system.cpu.iew.iewExecutedInsts 57271021 # Number of executed instructions 500system.cpu.iew.iewExecLoadInsts 10213321 # Number of load instructions executed 501system.cpu.iew.iewExecSquashedInsts 695401 # Number of squashed instructions skipped in execute | 500system.cpu.iew.iewSquashCycles 1399904 # Number of cycles IEW is squashing 501system.cpu.iew.iewBlockCycles 9017933 # Number of cycles IEW is blocking 502system.cpu.iew.iewUnblockCycles 616152 # Number of cycles IEW is unblocking 503system.cpu.iew.iewDispatchedInsts 64867759 # Number of instructions dispatched to IQ 504system.cpu.iew.iewDispSquashedInsts 849536 # Number of squashed instructions skipped by dispatch 505system.cpu.iew.iewDispLoadInsts 10647937 # Number of dispatched load instructions 506system.cpu.iew.iewDispStoreInsts 6996260 # Number of dispatched store instructions 507system.cpu.iew.iewDispNonSpecInsts 1840231 # Number of dispatched non-speculative instructions 508system.cpu.iew.iewIQFullEvents 482623 # Number of times the IQ has become full, causing a stall 509system.cpu.iew.iewLSQFullEvents 15971 # Number of times the LSQ has become full, causing a stall 510system.cpu.iew.memOrderViolationEvents 13124 # Number of memory order violations 511system.cpu.iew.predictedTakenIncorrect 267386 # Number of branches that were predicted taken incorrectly 512system.cpu.iew.predictedNotTakenIncorrect 425155 # Number of branches that were predicted not taken incorrectly 513system.cpu.iew.branchMispredicts 692541 # Number of branch mispredicts detected at execute 514system.cpu.iew.iewExecutedInsts 56871146 # Number of executed instructions 515system.cpu.iew.iewExecLoadInsts 10095387 # Number of load instructions executed 516system.cpu.iew.iewExecSquashedInsts 625553 # Number of squashed instructions skipped in execute |
| 502system.cpu.iew.exec_swp 0 # number of swp insts executed | 517system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 503system.cpu.iew.exec_nop 3625473 # number of nop insts executed 504system.cpu.iew.exec_refs 16867223 # number of memory reference insts executed 505system.cpu.iew.exec_branches 9097936 # Number of branches executed 506system.cpu.iew.exec_stores 6653902 # Number of stores executed 507system.cpu.iew.exec_rate 0.492563 # Inst execution rate 508system.cpu.iew.wb_sent 56871872 # cumulative count of insts sent to commit 509system.cpu.iew.wb_count 56738020 # cumulative count of insts written-back 510system.cpu.iew.wb_producers 28030988 # num instructions producing a value 511system.cpu.iew.wb_consumers 37770905 # num instructions consuming a value | 518system.cpu.iew.exec_nop 3587167 # number of nop insts executed 519system.cpu.iew.exec_refs 16760622 # number of memory reference insts executed 520system.cpu.iew.exec_branches 9006504 # Number of branches executed 521system.cpu.iew.exec_stores 6665235 # Number of stores executed 522system.cpu.iew.exec_rate 0.490534 # Inst execution rate 523system.cpu.iew.wb_sent 56517124 # cumulative count of insts sent to commit 524system.cpu.iew.wb_count 56389282 # cumulative count of insts written-back 525system.cpu.iew.wb_producers 27888094 # num instructions producing a value 526system.cpu.iew.wb_consumers 37753450 # num instructions consuming a value |
| 512system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 527system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 513system.cpu.iew.wb_rate 0.487979 # insts written-back per cycle 514system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back | 528system.cpu.iew.wb_rate 0.486378 # insts written-back per cycle 529system.cpu.iew.wb_fanout 0.738690 # average fanout of values written-back |
| 515system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 530system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 516system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions 517system.cpu.commit.commitCommittedOps 56280196 # The number of committed instructions 518system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit 519system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards 520system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted 521system.cpu.commit.committed_per_cycle::samples 80658204 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::mean 0.697762 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::stdev 1.611283 # Number of insts commited each cycle | 531system.cpu.commit.commitCommittedInsts 56284358 # The number of committed instructions 532system.cpu.commit.commitCommittedOps 56284358 # The number of committed instructions 533system.cpu.commit.commitSquashedInsts 8468547 # The number of squashed insts skipped by commit 534system.cpu.commit.commitNonSpecStalls 667724 # The number of times commit has been forced to stall to communicate backwards 535system.cpu.commit.branchMispredicts 643899 # The number of times a branch was mispredicted 536system.cpu.commit.committed_per_cycle::samples 80238397 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::mean 0.701464 # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::stdev 1.625122 # Number of insts commited each cycle |
| 524system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 539system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 525system.cpu.commit.committed_per_cycle::0 59481462 73.75% 73.75% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::1 8887876 11.02% 84.76% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::2 4721135 5.85% 90.62% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::3 2612091 3.24% 93.86% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::4 1531941 1.90% 95.76% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::5 645193 0.80% 96.56% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::6 475603 0.59% 97.14% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::7 516794 0.64% 97.79% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::8 1786109 2.21% 100.00% # Number of insts commited each cycle | 540system.cpu.commit.committed_per_cycle::0 59258262 73.85% 73.85% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::1 8767408 10.93% 84.78% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::2 4647312 5.79% 90.57% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::3 2573487 3.21% 93.78% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::4 1500960 1.87% 95.65% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::5 651575 0.81% 96.46% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::6 486922 0.61% 97.07% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::7 501150 0.62% 97.69% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::8 1851321 2.31% 100.00% # Number of insts commited each cycle |
| 534system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 549system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 537system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle 538system.cpu.commit.committedInsts 56280196 # Number of instructions committed 539system.cpu.commit.committedOps 56280196 # Number of ops (including micro ops) committed | 552system.cpu.commit.committed_per_cycle::total 80238397 # Number of insts commited each cycle 553system.cpu.commit.committedInsts 56284358 # Number of instructions committed 554system.cpu.commit.committedOps 56284358 # Number of ops (including micro ops) committed |
| 540system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 555system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 541system.cpu.commit.refs 15504446 # Number of memory references committed 542system.cpu.commit.loads 9112319 # Number of loads committed 543system.cpu.commit.membars 227818 # Number of memory barriers committed 544system.cpu.commit.branches 8461284 # Number of branches committed | 556system.cpu.commit.refs 15505080 # Number of memory references committed 557system.cpu.commit.loads 9112848 # Number of loads committed 558system.cpu.commit.membars 227858 # Number of memory barriers committed 559system.cpu.commit.branches 8462387 # Number of branches committed |
| 545system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 560system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 546system.cpu.commit.int_insts 52119152 # Number of committed integer instructions. 547system.cpu.commit.function_calls 744404 # Number of function calls committed. 548system.cpu.commit.bw_lim_events 1786109 # number cycles where commit BW limit reached | 561system.cpu.commit.int_insts 52122951 # Number of committed integer instructions. 562system.cpu.commit.function_calls 744427 # Number of function calls committed. 563system.cpu.commit.bw_lim_events 1851321 # number cycles where commit BW limit reached |
| 549system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 564system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 550system.cpu.rob.rob_reads 143937484 # The number of ROB reads 551system.cpu.rob.rob_writes 132136289 # The number of ROB writes 552system.cpu.timesIdled 1255783 # Number of times that the entire CPU went into an idle state and unscheduled itself 553system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling 554system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 555system.cpu.committedInsts 53085804 # Number of Instructions Simulated 556system.cpu.committedOps 53085804 # Number of Ops (including micro ops) Simulated 557system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated 558system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction 559system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads 560system.cpu.ipc 0.456568 # IPC: Instructions Per Cycle 561system.cpu.ipc_total 0.456568 # IPC: Total IPC of All Threads 562system.cpu.int_regfile_reads 75080091 # number of integer regfile reads 563system.cpu.int_regfile_writes 40965330 # number of integer regfile writes 564system.cpu.fp_regfile_reads 166532 # number of floating regfile reads 565system.cpu.fp_regfile_writes 167403 # number of floating regfile writes 566system.cpu.misc_regfile_reads 1996306 # number of misc regfile reads 567system.cpu.misc_regfile_writes 949674 # number of misc regfile writes | 565system.cpu.rob.rob_reads 142888950 # The number of ROB reads 566system.cpu.rob.rob_writes 130907900 # The number of ROB writes 567system.cpu.timesIdled 1275123 # Number of times that the entire CPU went into an idle state and unscheduled itself 568system.cpu.idleCycles 34298805 # Total number of cycles that the CPU has spent unscheduled due to idling 569system.cpu.quiesceCycles 3601425271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 570system.cpu.committedInsts 53089851 # Number of Instructions Simulated 571system.cpu.committedOps 53089851 # Number of Ops (including micro ops) Simulated 572system.cpu.committedInsts_total 53089851 # Number of Instructions Simulated 573system.cpu.cpi 2.183790 # CPI: Cycles Per Instruction 574system.cpu.cpi_total 2.183790 # CPI: Total CPI of All Threads 575system.cpu.ipc 0.457919 # IPC: Instructions Per Cycle 576system.cpu.ipc_total 0.457919 # IPC: Total IPC of All Threads 577system.cpu.int_regfile_reads 74514493 # number of integer regfile reads 578system.cpu.int_regfile_writes 40703979 # number of integer regfile writes 579system.cpu.fp_regfile_reads 166152 # number of floating regfile reads 580system.cpu.fp_regfile_writes 167434 # number of floating regfile writes 581system.cpu.misc_regfile_reads 1998995 # number of misc regfile reads 582system.cpu.misc_regfile_writes 949957 # number of misc regfile writes |
| 568system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 569system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 570system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 571system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 572system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 573system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 574system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 575system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 591system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 592system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 593system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 594system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 595system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 596system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 597system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 598system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 583system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 584system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 585system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 586system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 587system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 588system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 589system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 590system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 606system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 607system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 608system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 609system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 610system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 611system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 612system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 613system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 599system.cpu.icache.replacements 1004588 # number of replacements 600system.cpu.icache.tagsinuse 509.963959 # Cycle average of tags in use 601system.cpu.icache.total_refs 7985769 # Total number of references to valid blocks. 602system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks. 603system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks. 604system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit. 605system.cpu.icache.occ_blocks::cpu.inst 509.963959 # Average occupied blocks per requestor 606system.cpu.icache.occ_percent::cpu.inst 0.996023 # Average percentage of cache occupancy 607system.cpu.icache.occ_percent::total 0.996023 # Average percentage of cache occupancy 608system.cpu.icache.ReadReq_hits::cpu.inst 7985770 # number of ReadReq hits 609system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits 610system.cpu.icache.demand_hits::cpu.inst 7985770 # number of demand (read+write) hits 611system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits 612system.cpu.icache.overall_hits::cpu.inst 7985770 # number of overall hits 613system.cpu.icache.overall_hits::total 7985770 # number of overall hits 614system.cpu.icache.ReadReq_misses::cpu.inst 1065446 # number of ReadReq misses 615system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses 616system.cpu.icache.demand_misses::cpu.inst 1065446 # number of demand (read+write) misses 617system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses 618system.cpu.icache.overall_misses::cpu.inst 1065446 # number of overall misses 619system.cpu.icache.overall_misses::total 1065446 # number of overall misses 620system.cpu.icache.ReadReq_miss_latency::cpu.inst 15927822494 # number of ReadReq miss cycles 621system.cpu.icache.ReadReq_miss_latency::total 15927822494 # number of ReadReq miss cycles 622system.cpu.icache.demand_miss_latency::cpu.inst 15927822494 # number of demand (read+write) miss cycles 623system.cpu.icache.demand_miss_latency::total 15927822494 # number of demand (read+write) miss cycles 624system.cpu.icache.overall_miss_latency::cpu.inst 15927822494 # number of overall miss cycles 625system.cpu.icache.overall_miss_latency::total 15927822494 # number of overall miss cycles 626system.cpu.icache.ReadReq_accesses::cpu.inst 9051216 # number of ReadReq accesses(hits+misses) 627system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses) 628system.cpu.icache.demand_accesses::cpu.inst 9051216 # number of demand (read+write) accesses 629system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses 630system.cpu.icache.overall_accesses::cpu.inst 9051216 # number of overall (read+write) accesses 631system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses 632system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117713 # miss rate for ReadReq accesses 633system.cpu.icache.demand_miss_rate::cpu.inst 0.117713 # miss rate for demand accesses 634system.cpu.icache.overall_miss_rate::cpu.inst 0.117713 # miss rate for overall accesses 635system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14949.441355 # average ReadReq miss latency 636system.cpu.icache.demand_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency 637system.cpu.icache.overall_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency 638system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked | 614system.cpu.icache.replacements 1025621 # number of replacements 615system.cpu.icache.tagsinuse 509.964536 # Cycle average of tags in use 616system.cpu.icache.total_refs 7915589 # Total number of references to valid blocks. 617system.cpu.icache.sampled_refs 1026130 # Sample count of references to valid blocks. 618system.cpu.icache.avg_refs 7.714022 # Average number of references to valid blocks. 619system.cpu.icache.warmup_cycle 23323095000 # Cycle when the warmup percentage was hit. 620system.cpu.icache.occ_blocks::cpu.inst 509.964536 # Average occupied blocks per requestor 621system.cpu.icache.occ_percent::cpu.inst 0.996024 # Average percentage of cache occupancy 622system.cpu.icache.occ_percent::total 0.996024 # Average percentage of cache occupancy 623system.cpu.icache.ReadReq_hits::cpu.inst 7915590 # number of ReadReq hits 624system.cpu.icache.ReadReq_hits::total 7915590 # number of ReadReq hits 625system.cpu.icache.demand_hits::cpu.inst 7915590 # number of demand (read+write) hits 626system.cpu.icache.demand_hits::total 7915590 # number of demand (read+write) hits 627system.cpu.icache.overall_hits::cpu.inst 7915590 # number of overall hits 628system.cpu.icache.overall_hits::total 7915590 # number of overall hits 629system.cpu.icache.ReadReq_misses::cpu.inst 1086093 # number of ReadReq misses 630system.cpu.icache.ReadReq_misses::total 1086093 # number of ReadReq misses 631system.cpu.icache.demand_misses::cpu.inst 1086093 # number of demand (read+write) misses 632system.cpu.icache.demand_misses::total 1086093 # number of demand (read+write) misses 633system.cpu.icache.overall_misses::cpu.inst 1086093 # number of overall misses 634system.cpu.icache.overall_misses::total 1086093 # number of overall misses 635system.cpu.icache.ReadReq_miss_latency::cpu.inst 16268467995 # number of ReadReq miss cycles 636system.cpu.icache.ReadReq_miss_latency::total 16268467995 # number of ReadReq miss cycles 637system.cpu.icache.demand_miss_latency::cpu.inst 16268467995 # number of demand (read+write) miss cycles 638system.cpu.icache.demand_miss_latency::total 16268467995 # number of demand (read+write) miss cycles 639system.cpu.icache.overall_miss_latency::cpu.inst 16268467995 # number of overall miss cycles 640system.cpu.icache.overall_miss_latency::total 16268467995 # number of overall miss cycles 641system.cpu.icache.ReadReq_accesses::cpu.inst 9001683 # number of ReadReq accesses(hits+misses) 642system.cpu.icache.ReadReq_accesses::total 9001683 # number of ReadReq accesses(hits+misses) 643system.cpu.icache.demand_accesses::cpu.inst 9001683 # number of demand (read+write) accesses 644system.cpu.icache.demand_accesses::total 9001683 # number of demand (read+write) accesses 645system.cpu.icache.overall_accesses::cpu.inst 9001683 # number of overall (read+write) accesses 646system.cpu.icache.overall_accesses::total 9001683 # number of overall (read+write) accesses 647system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120654 # miss rate for ReadReq accesses 648system.cpu.icache.demand_miss_rate::cpu.inst 0.120654 # miss rate for demand accesses 649system.cpu.icache.overall_miss_rate::cpu.inst 0.120654 # miss rate for overall accesses 650system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency 651system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency 653system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked |
| 639system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 640system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked | 655system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked |
| 641system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 642system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 # average number of cycles each access was blocked | 657system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667 # average number of cycles each access was blocked |
| 643system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 644system.cpu.icache.fast_writes 0 # number of fast writes performed 645system.cpu.icache.cache_copies 0 # number of cache copies performed | 658system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 659system.cpu.icache.fast_writes 0 # number of fast writes performed 660system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 646system.cpu.icache.writebacks::writebacks 234 # number of writebacks 647system.cpu.icache.writebacks::total 234 # number of writebacks 648system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60134 # number of ReadReq MSHR hits 649system.cpu.icache.ReadReq_mshr_hits::total 60134 # number of ReadReq MSHR hits 650system.cpu.icache.demand_mshr_hits::cpu.inst 60134 # number of demand (read+write) MSHR hits 651system.cpu.icache.demand_mshr_hits::total 60134 # number of demand (read+write) MSHR hits 652system.cpu.icache.overall_mshr_hits::cpu.inst 60134 # number of overall MSHR hits 653system.cpu.icache.overall_mshr_hits::total 60134 # number of overall MSHR hits 654system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1005312 # number of ReadReq MSHR misses 655system.cpu.icache.ReadReq_mshr_misses::total 1005312 # number of ReadReq MSHR misses 656system.cpu.icache.demand_mshr_misses::cpu.inst 1005312 # number of demand (read+write) MSHR misses 657system.cpu.icache.demand_mshr_misses::total 1005312 # number of demand (read+write) MSHR misses 658system.cpu.icache.overall_mshr_misses::cpu.inst 1005312 # number of overall MSHR misses 659system.cpu.icache.overall_mshr_misses::total 1005312 # number of overall MSHR misses 660system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12047333996 # number of ReadReq MSHR miss cycles 661system.cpu.icache.ReadReq_mshr_miss_latency::total 12047333996 # number of ReadReq MSHR miss cycles 662system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12047333996 # number of demand (read+write) MSHR miss cycles 663system.cpu.icache.demand_mshr_miss_latency::total 12047333996 # number of demand (read+write) MSHR miss cycles 664system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12047333996 # number of overall MSHR miss cycles 665system.cpu.icache.overall_mshr_miss_latency::total 12047333996 # number of overall MSHR miss cycles 666system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for ReadReq accesses 667system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for demand accesses 668system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for overall accesses 669system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.676705 # average ReadReq mshr miss latency 670system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency 671system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency | 661system.cpu.icache.writebacks::writebacks 238 # number of writebacks 662system.cpu.icache.writebacks::total 238 # number of writebacks 663system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59750 # number of ReadReq MSHR hits 664system.cpu.icache.ReadReq_mshr_hits::total 59750 # number of ReadReq MSHR hits 665system.cpu.icache.demand_mshr_hits::cpu.inst 59750 # number of demand (read+write) MSHR hits 666system.cpu.icache.demand_mshr_hits::total 59750 # number of demand (read+write) MSHR hits 667system.cpu.icache.overall_mshr_hits::cpu.inst 59750 # number of overall MSHR hits 668system.cpu.icache.overall_mshr_hits::total 59750 # number of overall MSHR hits 669system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026343 # number of ReadReq MSHR misses 670system.cpu.icache.ReadReq_mshr_misses::total 1026343 # number of ReadReq MSHR misses 671system.cpu.icache.demand_mshr_misses::cpu.inst 1026343 # number of demand (read+write) MSHR misses 672system.cpu.icache.demand_mshr_misses::total 1026343 # number of demand (read+write) MSHR misses 673system.cpu.icache.overall_mshr_misses::cpu.inst 1026343 # number of overall MSHR misses 674system.cpu.icache.overall_mshr_misses::total 1026343 # number of overall MSHR misses 675system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12299507497 # number of ReadReq MSHR miss cycles 676system.cpu.icache.ReadReq_mshr_miss_latency::total 12299507497 # number of ReadReq MSHR miss cycles 677system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12299507497 # number of demand (read+write) MSHR miss cycles 678system.cpu.icache.demand_mshr_miss_latency::total 12299507497 # number of demand (read+write) MSHR miss cycles 679system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12299507497 # number of overall MSHR miss cycles 680system.cpu.icache.overall_mshr_miss_latency::total 12299507497 # number of overall MSHR miss cycles 681system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for ReadReq accesses 682system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for demand accesses 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for overall accesses 684system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.817785 # average ReadReq mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency |
| 672system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 687system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 673system.cpu.dcache.replacements 1403406 # number of replacements 674system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use 675system.cpu.dcache.total_refs 12086534 # Total number of references to valid blocks. 676system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks. 677system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks. 678system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. 679system.cpu.dcache.occ_blocks::cpu.data 511.996008 # Average occupied blocks per requestor | 688system.cpu.dcache.replacements 1402627 # number of replacements 689system.cpu.dcache.tagsinuse 511.995944 # Cycle average of tags in use 690system.cpu.dcache.total_refs 11951343 # Total number of references to valid blocks. 691system.cpu.dcache.sampled_refs 1403139 # Sample count of references to valid blocks. 692system.cpu.dcache.avg_refs 8.517576 # Average number of references to valid blocks. 693system.cpu.dcache.warmup_cycle 19459000 # Cycle when the warmup percentage was hit. 694system.cpu.dcache.occ_blocks::cpu.data 511.995944 # Average occupied blocks per requestor |
| 680system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy 681system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy | 695system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy 696system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy |
| 682system.cpu.dcache.ReadReq_hits::cpu.data 7453772 # number of ReadReq hits 683system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits 684system.cpu.dcache.WriteReq_hits::cpu.data 4220462 # number of WriteReq hits 685system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits 686system.cpu.dcache.LoadLockedReq_hits::cpu.data 192050 # number of LoadLockedReq hits 687system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits 688system.cpu.dcache.StoreCondReq_hits::cpu.data 220033 # number of StoreCondReq hits 689system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits 690system.cpu.dcache.demand_hits::cpu.data 11674234 # number of demand (read+write) hits 691system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits 692system.cpu.dcache.overall_hits::cpu.data 11674234 # number of overall hits 693system.cpu.dcache.overall_hits::total 11674234 # number of overall hits 694system.cpu.dcache.ReadReq_misses::cpu.data 1809182 # number of ReadReq misses 695system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses 696system.cpu.dcache.WriteReq_misses::cpu.data 1936475 # number of WriteReq misses 697system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses 698system.cpu.dcache.LoadLockedReq_misses::cpu.data 22599 # number of LoadLockedReq misses 699system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses 700system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 701system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 702system.cpu.dcache.demand_misses::cpu.data 3745657 # number of demand (read+write) misses 703system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses 704system.cpu.dcache.overall_misses::cpu.data 3745657 # number of overall misses 705system.cpu.dcache.overall_misses::total 3745657 # number of overall misses 706system.cpu.dcache.ReadReq_miss_latency::cpu.data 38930236000 # number of ReadReq miss cycles 707system.cpu.dcache.ReadReq_miss_latency::total 38930236000 # number of ReadReq miss cycles 708system.cpu.dcache.WriteReq_miss_latency::cpu.data 57815325976 # number of WriteReq miss cycles 709system.cpu.dcache.WriteReq_miss_latency::total 57815325976 # number of WriteReq miss cycles 710system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338636000 # number of LoadLockedReq miss cycles 711system.cpu.dcache.LoadLockedReq_miss_latency::total 338636000 # number of LoadLockedReq miss cycles 712system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 28500 # number of StoreCondReq miss cycles 713system.cpu.dcache.StoreCondReq_miss_latency::total 28500 # number of StoreCondReq miss cycles 714system.cpu.dcache.demand_miss_latency::cpu.data 96745561976 # number of demand (read+write) miss cycles 715system.cpu.dcache.demand_miss_latency::total 96745561976 # number of demand (read+write) miss cycles 716system.cpu.dcache.overall_miss_latency::cpu.data 96745561976 # number of overall miss cycles 717system.cpu.dcache.overall_miss_latency::total 96745561976 # number of overall miss cycles 718system.cpu.dcache.ReadReq_accesses::cpu.data 9262954 # number of ReadReq accesses(hits+misses) 719system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses) 720system.cpu.dcache.WriteReq_accesses::cpu.data 6156937 # number of WriteReq accesses(hits+misses) 721system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses) 722system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214649 # number of LoadLockedReq accesses(hits+misses) 723system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses) 724system.cpu.dcache.StoreCondReq_accesses::cpu.data 220035 # number of StoreCondReq accesses(hits+misses) 725system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses) 726system.cpu.dcache.demand_accesses::cpu.data 15419891 # number of demand (read+write) accesses 727system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses 728system.cpu.dcache.overall_accesses::cpu.data 15419891 # number of overall (read+write) accesses 729system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses 730system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195314 # miss rate for ReadReq accesses 731system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314519 # miss rate for WriteReq accesses 732system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.105284 # miss rate for LoadLockedReq accesses 733system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 734system.cpu.dcache.demand_miss_rate::cpu.data 0.242911 # miss rate for demand accesses 735system.cpu.dcache.overall_miss_rate::cpu.data 0.242911 # miss rate for overall accesses 736system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21518.142453 # average ReadReq miss latency 737system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29855.963013 # average WriteReq miss latency 738system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14984.556839 # average LoadLockedReq miss latency 739system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14250 # average StoreCondReq miss latency 740system.cpu.dcache.demand_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency 741system.cpu.dcache.overall_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency 742system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked 743system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked 744system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked 745system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 746system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 # average number of cycles each access was blocked 747system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked | 697system.cpu.dcache.ReadReq_hits::cpu.data 7323424 # number of ReadReq hits 698system.cpu.dcache.ReadReq_hits::total 7323424 # number of ReadReq hits 699system.cpu.dcache.WriteReq_hits::cpu.data 4214108 # number of WriteReq hits 700system.cpu.dcache.WriteReq_hits::total 4214108 # number of WriteReq hits 701system.cpu.dcache.LoadLockedReq_hits::cpu.data 193501 # number of LoadLockedReq hits 702system.cpu.dcache.LoadLockedReq_hits::total 193501 # number of LoadLockedReq hits 703system.cpu.dcache.StoreCondReq_hits::cpu.data 220102 # number of StoreCondReq hits 704system.cpu.dcache.StoreCondReq_hits::total 220102 # number of StoreCondReq hits 705system.cpu.dcache.demand_hits::cpu.data 11537532 # number of demand (read+write) hits 706system.cpu.dcache.demand_hits::total 11537532 # number of demand (read+write) hits 707system.cpu.dcache.overall_hits::cpu.data 11537532 # number of overall hits 708system.cpu.dcache.overall_hits::total 11537532 # number of overall hits 709system.cpu.dcache.ReadReq_misses::cpu.data 1804216 # number of ReadReq misses 710system.cpu.dcache.ReadReq_misses::total 1804216 # number of ReadReq misses 711system.cpu.dcache.WriteReq_misses::cpu.data 1942860 # number of WriteReq misses 712system.cpu.dcache.WriteReq_misses::total 1942860 # number of WriteReq misses 713system.cpu.dcache.LoadLockedReq_misses::cpu.data 23377 # number of LoadLockedReq misses 714system.cpu.dcache.LoadLockedReq_misses::total 23377 # number of LoadLockedReq misses 715system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses 716system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses 717system.cpu.dcache.demand_misses::cpu.data 3747076 # number of demand (read+write) misses 718system.cpu.dcache.demand_misses::total 3747076 # number of demand (read+write) misses 719system.cpu.dcache.overall_misses::cpu.data 3747076 # number of overall misses 720system.cpu.dcache.overall_misses::total 3747076 # number of overall misses 721system.cpu.dcache.ReadReq_miss_latency::cpu.data 38906858000 # number of ReadReq miss cycles 722system.cpu.dcache.ReadReq_miss_latency::total 38906858000 # number of ReadReq miss cycles 723system.cpu.dcache.WriteReq_miss_latency::cpu.data 58108807026 # number of WriteReq miss cycles 724system.cpu.dcache.WriteReq_miss_latency::total 58108807026 # number of WriteReq miss cycles 725system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 346630500 # number of LoadLockedReq miss cycles 726system.cpu.dcache.LoadLockedReq_miss_latency::total 346630500 # number of LoadLockedReq miss cycles 727system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83500 # number of StoreCondReq miss cycles 728system.cpu.dcache.StoreCondReq_miss_latency::total 83500 # number of StoreCondReq miss cycles 729system.cpu.dcache.demand_miss_latency::cpu.data 97015665026 # number of demand (read+write) miss cycles 730system.cpu.dcache.demand_miss_latency::total 97015665026 # number of demand (read+write) miss cycles 731system.cpu.dcache.overall_miss_latency::cpu.data 97015665026 # number of overall miss cycles 732system.cpu.dcache.overall_miss_latency::total 97015665026 # number of overall miss cycles 733system.cpu.dcache.ReadReq_accesses::cpu.data 9127640 # number of ReadReq accesses(hits+misses) 734system.cpu.dcache.ReadReq_accesses::total 9127640 # number of ReadReq accesses(hits+misses) 735system.cpu.dcache.WriteReq_accesses::cpu.data 6156968 # number of WriteReq accesses(hits+misses) 736system.cpu.dcache.WriteReq_accesses::total 6156968 # number of WriteReq accesses(hits+misses) 737system.cpu.dcache.LoadLockedReq_accesses::cpu.data 216878 # number of LoadLockedReq accesses(hits+misses) 738system.cpu.dcache.LoadLockedReq_accesses::total 216878 # number of LoadLockedReq accesses(hits+misses) 739system.cpu.dcache.StoreCondReq_accesses::cpu.data 220105 # number of StoreCondReq accesses(hits+misses) 740system.cpu.dcache.StoreCondReq_accesses::total 220105 # number of StoreCondReq accesses(hits+misses) 741system.cpu.dcache.demand_accesses::cpu.data 15284608 # number of demand (read+write) accesses 742system.cpu.dcache.demand_accesses::total 15284608 # number of demand (read+write) accesses 743system.cpu.dcache.overall_accesses::cpu.data 15284608 # number of overall (read+write) accesses 744system.cpu.dcache.overall_accesses::total 15284608 # number of overall (read+write) accesses 745system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197665 # miss rate for ReadReq accesses 746system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315555 # miss rate for WriteReq accesses 747system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107789 # miss rate for LoadLockedReq accesses 748system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000014 # miss rate for StoreCondReq accesses 749system.cpu.dcache.demand_miss_rate::cpu.data 0.245154 # miss rate for demand accesses 750system.cpu.dcache.overall_miss_rate::cpu.data 0.245154 # miss rate for overall accesses 751system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21564.412465 # average ReadReq miss latency 752system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29908.900809 # average WriteReq miss latency 753system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14827.843607 # average LoadLockedReq miss latency 754system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27833.333333 # average StoreCondReq miss latency 755system.cpu.dcache.demand_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency 756system.cpu.dcache.overall_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency 757system.cpu.dcache.blocked_cycles::no_mshrs 927127320 # number of cycles access was blocked 758system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked 759system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked 760system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 761system.cpu.dcache.avg_blocked_cycles::no_mshrs 9123.293381 # average number of cycles each access was blocked 762system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked |
| 748system.cpu.dcache.fast_writes 0 # number of fast writes performed 749system.cpu.dcache.cache_copies 0 # number of cache copies performed | 763system.cpu.dcache.fast_writes 0 # number of fast writes performed 764system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 750system.cpu.dcache.writebacks::writebacks 834955 # number of writebacks 751system.cpu.dcache.writebacks::total 834955 # number of writebacks 752system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721461 # number of ReadReq MSHR hits 753system.cpu.dcache.ReadReq_mshr_hits::total 721461 # number of ReadReq MSHR hits 754system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1637588 # number of WriteReq MSHR hits 755system.cpu.dcache.WriteReq_mshr_hits::total 1637588 # number of WriteReq MSHR hits 756system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5103 # number of LoadLockedReq MSHR hits 757system.cpu.dcache.LoadLockedReq_mshr_hits::total 5103 # number of LoadLockedReq MSHR hits 758system.cpu.dcache.demand_mshr_hits::cpu.data 2359049 # number of demand (read+write) MSHR hits 759system.cpu.dcache.demand_mshr_hits::total 2359049 # number of demand (read+write) MSHR hits 760system.cpu.dcache.overall_mshr_hits::cpu.data 2359049 # number of overall MSHR hits 761system.cpu.dcache.overall_mshr_hits::total 2359049 # number of overall MSHR hits 762system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1087721 # number of ReadReq MSHR misses 763system.cpu.dcache.ReadReq_mshr_misses::total 1087721 # number of ReadReq MSHR misses 764system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298887 # number of WriteReq MSHR misses 765system.cpu.dcache.WriteReq_mshr_misses::total 298887 # number of WriteReq MSHR misses 766system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17496 # number of LoadLockedReq MSHR misses 767system.cpu.dcache.LoadLockedReq_mshr_misses::total 17496 # number of LoadLockedReq MSHR misses 768system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 769system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 770system.cpu.dcache.demand_mshr_misses::cpu.data 1386608 # number of demand (read+write) MSHR misses 771system.cpu.dcache.demand_mshr_misses::total 1386608 # number of demand (read+write) MSHR misses 772system.cpu.dcache.overall_mshr_misses::cpu.data 1386608 # number of overall MSHR misses 773system.cpu.dcache.overall_mshr_misses::total 1386608 # number of overall MSHR misses 774system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24804888500 # number of ReadReq MSHR miss cycles 775system.cpu.dcache.ReadReq_mshr_miss_latency::total 24804888500 # number of ReadReq MSHR miss cycles 776system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509686826 # number of WriteReq MSHR miss cycles 777system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509686826 # number of WriteReq MSHR miss cycles 778system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206420500 # number of LoadLockedReq MSHR miss cycles 779system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206420500 # number of LoadLockedReq MSHR miss cycles 780system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles 781system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles 782system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33314575326 # number of demand (read+write) MSHR miss cycles 783system.cpu.dcache.demand_mshr_miss_latency::total 33314575326 # number of demand (read+write) MSHR miss cycles 784system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33314575326 # number of overall MSHR miss cycles 785system.cpu.dcache.overall_mshr_miss_latency::total 33314575326 # number of overall MSHR miss cycles 786system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904009500 # number of ReadReq MSHR uncacheable cycles 787system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904009500 # number of ReadReq MSHR uncacheable cycles 788system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234178998 # number of WriteReq MSHR uncacheable cycles 789system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234178998 # number of WriteReq MSHR uncacheable cycles 790system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138188498 # number of overall MSHR uncacheable cycles 791system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138188498 # number of overall MSHR uncacheable cycles 792system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.117427 # mshr miss rate for ReadReq accesses 793system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048545 # mshr miss rate for WriteReq accesses 794system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.081510 # mshr miss rate for LoadLockedReq accesses 795system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 796system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for demand accesses 797system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for overall accesses 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588 # average ReadReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095 # average WriteReq mshr miss latency 800system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864 # average LoadLockedReq mshr miss latency 801system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency 803system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency | 765system.cpu.dcache.writebacks::writebacks 834483 # number of writebacks 766system.cpu.dcache.writebacks::total 834483 # number of writebacks 767system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718769 # number of ReadReq MSHR hits 768system.cpu.dcache.ReadReq_mshr_hits::total 718769 # number of ReadReq MSHR hits 769system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643008 # number of WriteReq MSHR hits 770system.cpu.dcache.WriteReq_mshr_hits::total 1643008 # number of WriteReq MSHR hits 771system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5385 # number of LoadLockedReq MSHR hits 772system.cpu.dcache.LoadLockedReq_mshr_hits::total 5385 # number of LoadLockedReq MSHR hits 773system.cpu.dcache.demand_mshr_hits::cpu.data 2361777 # number of demand (read+write) MSHR hits 774system.cpu.dcache.demand_mshr_hits::total 2361777 # number of demand (read+write) MSHR hits 775system.cpu.dcache.overall_mshr_hits::cpu.data 2361777 # number of overall MSHR hits 776system.cpu.dcache.overall_mshr_hits::total 2361777 # number of overall MSHR hits 777system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085447 # number of ReadReq MSHR misses 778system.cpu.dcache.ReadReq_mshr_misses::total 1085447 # number of ReadReq MSHR misses 779system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299852 # number of WriteReq MSHR misses 780system.cpu.dcache.WriteReq_mshr_misses::total 299852 # number of WriteReq MSHR misses 781system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17992 # number of LoadLockedReq MSHR misses 782system.cpu.dcache.LoadLockedReq_mshr_misses::total 17992 # number of LoadLockedReq MSHR misses 783system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses 784system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses 785system.cpu.dcache.demand_mshr_misses::cpu.data 1385299 # number of demand (read+write) MSHR misses 786system.cpu.dcache.demand_mshr_misses::total 1385299 # number of demand (read+write) MSHR misses 787system.cpu.dcache.overall_mshr_misses::cpu.data 1385299 # number of overall MSHR misses 788system.cpu.dcache.overall_mshr_misses::total 1385299 # number of overall MSHR misses 789system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24777383500 # number of ReadReq MSHR miss cycles 790system.cpu.dcache.ReadReq_mshr_miss_latency::total 24777383500 # number of ReadReq MSHR miss cycles 791system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8529644820 # number of WriteReq MSHR miss cycles 792system.cpu.dcache.WriteReq_mshr_miss_latency::total 8529644820 # number of WriteReq MSHR miss cycles 793system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212567500 # number of LoadLockedReq MSHR miss cycles 794system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212567500 # number of LoadLockedReq MSHR miss cycles 795system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 74000 # number of StoreCondReq MSHR miss cycles 796system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 74000 # number of StoreCondReq MSHR miss cycles 797system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307028320 # number of demand (read+write) MSHR miss cycles 798system.cpu.dcache.demand_mshr_miss_latency::total 33307028320 # number of demand (read+write) MSHR miss cycles 799system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33307028320 # number of overall MSHR miss cycles 800system.cpu.dcache.overall_mshr_miss_latency::total 33307028320 # number of overall MSHR miss cycles 801system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904080500 # number of ReadReq MSHR uncacheable cycles 802system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904080500 # number of ReadReq MSHR uncacheable cycles 803system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1233731998 # number of WriteReq MSHR uncacheable cycles 804system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1233731998 # number of WriteReq MSHR uncacheable cycles 805system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2137812498 # number of overall MSHR uncacheable cycles 806system.cpu.dcache.overall_mshr_uncacheable_latency::total 2137812498 # number of overall MSHR uncacheable cycles 807system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118919 # mshr miss rate for ReadReq accesses 808system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048701 # mshr miss rate for WriteReq accesses 809system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082959 # mshr miss rate for LoadLockedReq accesses 810system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000014 # mshr miss rate for StoreCondReq accesses 811system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for demand accesses 812system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for overall accesses 813system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22826.893897 # average ReadReq mshr miss latency 814system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28446.182850 # average WriteReq mshr miss latency 815system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11814.556470 # average LoadLockedReq mshr miss latency 816system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24666.666667 # average StoreCondReq mshr miss latency 817system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency 818system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency |
| 804system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 805system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 806system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 807system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 808system.cpu.kern.inst.arm 0 # number of arm instructions executed | 819system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 820system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 821system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 822system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 823system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 809system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed 810system.cpu.kern.inst.hwrei 211491 # number of hwrei instructions executed 811system.cpu.kern.ipl_count::0 74854 40.97% 40.97% # number of times we switched to this ipl | 824system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed 825system.cpu.kern.inst.hwrei 211556 # number of hwrei instructions executed 826system.cpu.kern.ipl_count::0 74875 40.96% 40.96% # number of times we switched to this ipl |
| 812system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl | 827system.cpu.kern.ipl_count::21 241 0.13% 41.10% # number of times we switched to this ipl |
| 813system.cpu.kern.ipl_count::22 1878 1.03% 42.13% # number of times we switched to this ipl 814system.cpu.kern.ipl_count::31 105750 57.87% 100.00% # number of times we switched to this ipl 815system.cpu.kern.ipl_count::total 182723 # number of times we switched to this ipl 816system.cpu.kern.ipl_good::0 73487 49.29% 49.29% # number of times we switched to this ipl from a different ipl | 828system.cpu.kern.ipl_count::22 1880 1.03% 42.12% # number of times we switched to this ipl 829system.cpu.kern.ipl_count::31 105790 57.88% 100.00% # number of times we switched to this ipl 830system.cpu.kern.ipl_count::total 182786 # number of times we switched to this ipl 831system.cpu.kern.ipl_good::0 73508 49.29% 49.29% # number of times we switched to this ipl from a different ipl |
| 817system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl | 832system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl |
| 818system.cpu.kern.ipl_good::22 1878 1.26% 50.71% # number of times we switched to this ipl from a different ipl 819system.cpu.kern.ipl_good::31 73489 49.29% 100.00% # number of times we switched to this ipl from a different ipl 820system.cpu.kern.ipl_good::total 149095 # number of times we switched to this ipl from a different ipl 821system.cpu.kern.ipl_ticks::0 1821211214000 97.92% 97.92% # number of cycles we spent at this ipl 822system.cpu.kern.ipl_ticks::21 93652500 0.01% 97.93% # number of cycles we spent at this ipl 823system.cpu.kern.ipl_ticks::22 383616500 0.02% 97.95% # number of cycles we spent at this ipl 824system.cpu.kern.ipl_ticks::31 38161211000 2.05% 100.00% # number of cycles we spent at this ipl 825system.cpu.kern.ipl_ticks::total 1859849694000 # number of cycles we spent at this ipl 826system.cpu.kern.ipl_used::0 0.981738 # fraction of swpipl calls that actually changed the ipl | 833system.cpu.kern.ipl_good::22 1880 1.26% 50.71% # number of times we switched to this ipl from a different ipl 834system.cpu.kern.ipl_good::31 73510 49.29% 100.00% # number of times we switched to this ipl from a different ipl 835system.cpu.kern.ipl_good::total 149139 # number of times we switched to this ipl from a different ipl 836system.cpu.kern.ipl_ticks::0 1820018970500 97.92% 97.92% # number of cycles we spent at this ipl 837system.cpu.kern.ipl_ticks::21 94294500 0.01% 97.92% # number of cycles we spent at this ipl 838system.cpu.kern.ipl_ticks::22 380287500 0.02% 97.95% # number of cycles we spent at this ipl 839system.cpu.kern.ipl_ticks::31 38189985000 2.05% 100.00% # number of cycles we spent at this ipl 840system.cpu.kern.ipl_ticks::total 1858683537500 # number of cycles we spent at this ipl 841system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl |
| 827system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 828system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 842system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 843system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 829system.cpu.kern.ipl_used::31 0.694931 # fraction of swpipl calls that actually changed the ipl | 844system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl |
| 830system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 831system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 832system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 833system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 834system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 835system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 836system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 837system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 860system.cpu.kern.syscall::total 326 # number of syscalls executed 861system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 862system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 863system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 864system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 865system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 866system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 867system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 845system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 846system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 847system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 848system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 849system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 850system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 851system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 852system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 875system.cpu.kern.syscall::total 326 # number of syscalls executed 876system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 877system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 878system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 879system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 880system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 881system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 882system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 868system.cpu.kern.callpal::swpipl 175394 91.19% 93.39% # number of callpals executed 869system.cpu.kern.callpal::rdps 6783 3.53% 96.92% # number of callpals executed | 883system.cpu.kern.callpal::swpipl 175453 91.19% 93.39% # number of callpals executed 884system.cpu.kern.callpal::rdps 6785 3.53% 96.92% # number of callpals executed |
| 870system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 871system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 872system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 873system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed | 885system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 886system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 887system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 888system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed |
| 874system.cpu.kern.callpal::rti 5211 2.71% 99.64% # number of callpals executed | 889system.cpu.kern.callpal::rti 5213 2.71% 99.64% # number of callpals executed |
| 875system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 876system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 890system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 891system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 877system.cpu.kern.callpal::total 192344 # number of callpals executed 878system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches 879system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 880system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches 881system.cpu.kern.mode_good::kernel 1909 882system.cpu.kern.mode_good::user 1739 | 892system.cpu.kern.callpal::total 192407 # number of callpals executed 893system.cpu.kern.mode_switch::kernel 5952 # number of protection mode switches 894system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 895system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches 896system.cpu.kern.mode_good::kernel 1910 897system.cpu.kern.mode_good::user 1740 |
| 883system.cpu.kern.mode_good::idle 170 | 898system.cpu.kern.mode_good::idle 170 |
| 884system.cpu.kern.mode_switch_good::kernel 0.320948 # fraction of useful protection mode switches | 899system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches |
| 885system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 900system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 886system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches 887system.cpu.kern.mode_switch_good::total 1.401708 # fraction of useful protection mode switches 888system.cpu.kern.mode_ticks::kernel 29148036500 1.57% 1.57% # number of ticks spent at the given mode 889system.cpu.kern.mode_ticks::user 2681917500 0.14% 1.71% # number of ticks spent at the given mode 890system.cpu.kern.mode_ticks::idle 1828019732000 98.29% 100.00% # number of ticks spent at the given mode | 901system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches 902system.cpu.kern.mode_switch_good::total 1.401737 # fraction of useful protection mode switches 903system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode 904system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode 905system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode |
| 891system.cpu.kern.swap_context 4177 # number of times the context was actually changed 892 893---------- End Simulation Statistics ---------- | 906system.cpu.kern.swap_context 4177 # number of times the context was actually changed 907 908---------- End Simulation Statistics ---------- |