| stats.txt (11707:1d085f66c4ca) | stats.txt (11754:c209cb86278a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.865012 # Number of seconds simulated 4sim_ticks 1865011607500 # Number of ticks simulated 5final_tick 1865011607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.865010 # Number of seconds simulated 4sim_ticks 1865009748000 # Number of ticks simulated 5final_tick 1865009748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 239114 # Simulator instruction rate (inst/s) 8host_op_rate 239113 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8418978943 # Simulator tick rate (ticks/s) 10host_mem_usage 338260 # Number of bytes of host memory used 11host_seconds 221.52 # Real time elapsed on the host 12sim_insts 52969539 # Number of instructions simulated 13sim_ops 52969539 # Number of ops (including micro ops) simulated | 7host_inst_rate 235871 # Simulator instruction rate (inst/s) 8host_op_rate 235870 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8303287371 # Simulator tick rate (ticks/s) 10host_mem_usage 337912 # Number of bytes of host memory used 11host_seconds 224.61 # Real time elapsed on the host 12sim_insts 52979108 # Number of instructions simulated 13sim_ops 52979108 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 962688 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24879872 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 962240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24880192 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::total 25843520 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 962688 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 962688 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7514368 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7514368 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 15042 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388748 # Number of read requests responded to by this memory | 20system.physmem.bytes_read::total 25843392 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 962240 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 15035 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388753 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::total 403805 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 117412 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 117412 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 516183 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 13340331 # Total read bandwidth from this memory (bytes/s) | 28system.physmem.num_reads::total 403803 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 515944 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 13340516 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::total 13857029 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 516183 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 516183 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 4029127 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 4029127 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 4029127 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 516183 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 13340331 # Total bandwidth to/from this memory (bytes/s) | 34system.physmem.bw_read::total 13856974 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 515944 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 515944 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 4030126 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 4030126 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 4030126 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 515944 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 13340516 # Total bandwidth to/from this memory (bytes/s) |
| 42system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) |
| 43system.physmem.bw_total::total 17886156 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 403805 # Number of read requests accepted 45system.physmem.writeReqs 117412 # Number of write requests accepted 46system.physmem.readBursts 403805 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 117412 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25836672 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7513280 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25843520 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7514368 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue | 43system.physmem.bw_total::total 17887100 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 403803 # Number of read requests accepted 45system.physmem.writeReqs 117441 # Number of write requests accepted 46system.physmem.readBursts 403803 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 117441 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25835712 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7515136 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25843392 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7516224 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue |
| 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 25445 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25617 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25496 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25620 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25117 # Per bank write bursts 61system.physmem.perBankRdBursts::5 25178 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24740 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24558 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25032 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25302 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25290 # Per bank write bursts 67system.physmem.perBankRdBursts::11 25006 # Per bank write bursts 68system.physmem.perBankRdBursts::12 24377 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25425 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25800 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25695 # Per bank write bursts 72system.physmem.perBankWrBursts::0 7802 # Per bank write bursts 73system.physmem.perBankWrBursts::1 7592 # Per bank write bursts 74system.physmem.perBankWrBursts::2 7774 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7602 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7239 # Per bank write bursts 77system.physmem.perBankWrBursts::5 7182 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6741 # Per bank write bursts 79system.physmem.perBankWrBursts::7 6416 # Per bank write bursts 80system.physmem.perBankWrBursts::8 7149 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6926 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7200 # Per bank write bursts 83system.physmem.perBankWrBursts::11 7003 # Per bank write bursts 84system.physmem.perBankWrBursts::12 6957 # Per bank write bursts 85system.physmem.perBankWrBursts::13 7880 # Per bank write bursts 86system.physmem.perBankWrBursts::14 8017 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 25444 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25611 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25628 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25719 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25100 # Per bank write bursts 61system.physmem.perBankRdBursts::5 25088 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24758 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24649 # Per bank write bursts 64system.physmem.perBankRdBursts::8 24903 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25188 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25284 # Per bank write bursts 67system.physmem.perBankRdBursts::11 25005 # Per bank write bursts 68system.physmem.perBankRdBursts::12 24375 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25430 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25804 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25697 # Per bank write bursts 72system.physmem.perBankWrBursts::0 7804 # Per bank write bursts 73system.physmem.perBankWrBursts::1 7583 # Per bank write bursts 74system.physmem.perBankWrBursts::2 7900 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7698 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7224 # Per bank write bursts 77system.physmem.perBankWrBursts::5 7092 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6759 # Per bank write bursts 79system.physmem.perBankWrBursts::7 6515 # Per bank write bursts 80system.physmem.perBankWrBursts::8 7053 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6824 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7197 # Per bank write bursts 83system.physmem.perBankWrBursts::11 7005 # Per bank write bursts 84system.physmem.perBankWrBursts::12 6955 # Per bank write bursts 85system.physmem.perBankWrBursts::13 7882 # Per bank write bursts 86system.physmem.perBankWrBursts::14 8018 # Per bank write bursts |
| 87system.physmem.perBankWrBursts::15 7915 # Per bank write bursts 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.perBankWrBursts::15 7915 # Per bank write bursts 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 89system.physmem.numWrRetry 50 # Number of times write queue was full causing retry 90system.physmem.totGap 1865006319500 # Total gap between requests | 89system.physmem.numWrRetry 65 # Number of times write queue was full causing retry 90system.physmem.totGap 1865004470500 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 403805 # Read request sizes (log2) | 97system.physmem.readPktSize::6 403803 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 117412 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 314207 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 36490 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 28744 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 24151 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 117441 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 314056 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 36501 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 28766 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 24237 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 106 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see |
| 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 1450 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 3214 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 4203 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 5585 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6297 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 7150 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 8264 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6799 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 7310 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 7943 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7596 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 6918 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6963 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 7091 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 5971 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 6192 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 746 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 330 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 325 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 1442 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 2555 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 3197 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6335 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 7132 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 8220 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6784 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 7296 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 7880 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7649 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 6878 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6959 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6763 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 6050 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 763 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 457 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see |
| 175system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see | 175system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see |
| 176system.physmem.wrQLenPdf::39 287 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 308 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 376 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 400 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 341 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 298 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 305 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 305 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 312 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 254 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 168 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 103 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 61234 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 544.625012 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 334.721385 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 417.137572 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 13321 21.75% 21.75% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 10685 17.45% 39.20% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4509 7.36% 46.57% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 2718 4.44% 51.01% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2169 3.54% 54.55% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 1832 2.99% 57.54% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1887 3.08% 60.62% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1551 2.53% 63.15% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 22562 36.85% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 61234 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 78.280396 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2939.585639 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5154 99.94% 99.94% # Reads before turning the bus around for writes | 176system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 257 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 275 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 349 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 350 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 345 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 206 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 315 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 191 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 206 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 373 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 288 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 129 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 61362 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 543.503536 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 333.365701 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 417.323842 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 13476 21.96% 21.96% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 10707 17.45% 39.41% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4479 7.30% 46.71% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 2678 4.36% 51.07% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2195 3.58% 54.65% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 1843 3.00% 57.65% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1874 3.05% 60.71% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1552 2.53% 63.24% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 22558 36.76% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 61362 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 78.231977 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2938.731055 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5157 99.94% 99.94% # Reads before turning the bus around for writes |
| 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 222system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.764204 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 18.942160 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 24.363230 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4631 89.80% 89.80% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 32 0.62% 90.42% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 183 3.55% 93.97% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 6 0.12% 94.09% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 4 0.08% 94.16% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 9 0.17% 94.34% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 9 0.17% 94.51% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 4 0.08% 94.59% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 32 0.62% 95.21% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 5 0.10% 95.31% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 155 3.01% 98.31% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 14 0.27% 98.58% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::112-119 9 0.17% 98.76% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-127 2 0.04% 98.80% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 9 0.17% 98.97% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::136-143 4 0.08% 99.05% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::152-159 1 0.02% 99.07% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 2 0.04% 99.11% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::168-175 8 0.16% 99.26% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 6 0.12% 99.38% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 10 0.19% 99.57% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::192-199 10 0.19% 99.77% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::208-215 1 0.02% 99.81% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::216-223 4 0.08% 99.88% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::248-255 1 0.02% 99.94% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads 257system.physmem.totQLat 7801574500 # Total ticks spent queuing 258system.physmem.totMemAccLat 15370912000 # Total ticks spent from burst creation until serviced by the DRAM 259system.physmem.totBusLat 2018490000 # Total ticks spent in databus transfers 260system.physmem.avgQLat 19325.27 # Average queueing delay per DRAM burst | 222system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.756589 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 18.921420 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 24.589297 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4641 89.94% 89.94% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 34 0.66% 90.60% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 173 3.35% 93.95% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 9 0.17% 94.13% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 2 0.04% 94.17% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 16 0.31% 94.48% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 8 0.16% 94.63% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 3 0.06% 94.69% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 29 0.56% 95.25% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 4 0.08% 95.33% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 150 2.91% 98.24% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 19 0.37% 98.60% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::112-119 6 0.12% 98.72% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-127 5 0.10% 98.82% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 7 0.14% 98.95% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::136-143 2 0.04% 98.99% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::144-151 1 0.02% 99.01% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 3 0.06% 99.07% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::168-175 7 0.14% 99.21% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 5 0.10% 99.30% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 10 0.19% 99.50% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::192-199 13 0.25% 99.75% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 1 0.02% 99.77% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::216-223 4 0.08% 99.84% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::224-231 4 0.08% 99.92% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads 255system.physmem.totQLat 7817102750 # Total ticks spent queuing 256system.physmem.totMemAccLat 15386159000 # Total ticks spent from burst creation until serviced by the DRAM 257system.physmem.totBusLat 2018415000 # Total ticks spent in databus transfers 258system.physmem.avgQLat 19364.46 # Average queueing delay per DRAM burst |
| 261system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 262system.physmem.avgMemAccLat 38075.27 # Average memory access latency per DRAM burst | 260system.physmem.avgMemAccLat 38114.46 # Average memory access latency per DRAM burst |
| 263system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s 264system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s 265system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s 266system.physmem.avgWrBWSys 4.03 # Average system write bandwidth in MiByte/s 267system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 268system.physmem.busUtil 0.14 # Data bus utilization in percentage 269system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 270system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 261system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s 263system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s 264system.physmem.avgWrBWSys 4.03 # Average system write bandwidth in MiByte/s 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 266system.physmem.busUtil 0.14 # Data bus utilization in percentage 267system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 268system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 271system.physmem.avgRdQLen 1.96 # Average read queue length when enqueuing 272system.physmem.avgWrQLen 25.64 # Average write queue length when enqueuing 273system.physmem.readRowHits 364428 # Number of row buffer hits during reads 274system.physmem.writeRowHits 95430 # Number of row buffer hits during writes 275system.physmem.readRowHitRate 90.27 # Row buffer hit rate for reads 276system.physmem.writeRowHitRate 81.28 # Row buffer hit rate for writes 277system.physmem.avgGap 3578176.31 # Average gap between requests 278system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined 279system.physmem_0.actEnergy 214821180 # Energy for activate commands per rank (pJ) 280system.physmem_0.preEnergy 114180165 # Energy for precharge commands per rank (pJ) 281system.physmem_0.readEnergy 1440644940 # Energy for read commands per rank (pJ) 282system.physmem_0.writeEnergy 304576560 # Energy for write commands per rank (pJ) 283system.physmem_0.refreshEnergy 3637439520.000001 # Energy for refresh commands per rank (pJ) 284system.physmem_0.actBackEnergy 4203799590 # Energy for active background per rank (pJ) 285system.physmem_0.preBackEnergy 238276320 # Energy for precharge background per rank (pJ) 286system.physmem_0.actPowerDownEnergy 7970182890 # Energy for active power-down per rank (pJ) 287system.physmem_0.prePowerDownEnergy 4260887040 # Energy for precharge power-down per rank (pJ) 288system.physmem_0.selfRefreshEnergy 438967517640 # Energy for self refresh per rank (pJ) 289system.physmem_0.totalEnergy 461353182075 # Total energy per rank (pJ) 290system.physmem_0.averagePower 247.372821 # Core power per rank (mW) 291system.physmem_0.totalIdleTime 1855132089750 # Total Idle time Per DRAM Rank 292system.physmem_0.memoryStateTime::IDLE 377139000 # Time in different power states 293system.physmem_0.memoryStateTime::REF 1545232000 # Time in different power states 294system.physmem_0.memoryStateTime::SREF 1826595828250 # Time in different power states 295system.physmem_0.memoryStateTime::PRE_PDN 11096155750 # Time in different power states 296system.physmem_0.memoryStateTime::ACT 7918821750 # Time in different power states 297system.physmem_0.memoryStateTime::ACT_PDN 17478430750 # Time in different power states 298system.physmem_1.actEnergy 222396720 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 118202865 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 1441758780 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 308225340 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 3641127360.000001 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 4165097730 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 227687040 # Energy for precharge background per rank (pJ) 305system.physmem_1.actPowerDownEnergy 8135120370 # Energy for active power-down per rank (pJ) 306system.physmem_1.prePowerDownEnergy 4246672320 # Energy for precharge power-down per rank (pJ) 307system.physmem_1.selfRefreshEnergy 438904577085 # Energy for self refresh per rank (pJ) 308system.physmem_1.totalEnergy 461412058890 # Total energy per rank (pJ) 309system.physmem_1.averagePower 247.404390 # Core power per rank (mW) 310system.physmem_1.totalIdleTime 1855277049250 # Total Idle time Per DRAM Rank 311system.physmem_1.memoryStateTime::IDLE 349511250 # Time in different power states 312system.physmem_1.memoryStateTime::REF 1546624000 # Time in different power states 313system.physmem_1.memoryStateTime::SREF 1826382821500 # Time in different power states 314system.physmem_1.memoryStateTime::PRE_PDN 11059060000 # Time in different power states 315system.physmem_1.memoryStateTime::ACT 7833171250 # Time in different power states 316system.physmem_1.memoryStateTime::ACT_PDN 17840419500 # Time in different power states 317system.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 318system.bridge.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 319system.cpu.branchPred.lookups 19540652 # Number of BP lookups 320system.cpu.branchPred.condPredicted 16609155 # Number of conditional branches predicted 321system.cpu.branchPred.condIncorrect 593501 # Number of conditional branches incorrect 322system.cpu.branchPred.BTBLookups 12781935 # Number of BTB lookups 323system.cpu.branchPred.BTBHits 5419166 # Number of BTB hits | 269system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing 270system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing 271system.physmem.readRowHits 364427 # Number of row buffer hits during reads 272system.physmem.writeRowHits 95317 # Number of row buffer hits during writes 273system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads 274system.physmem.writeRowHitRate 81.16 # Row buffer hit rate for writes 275system.physmem.avgGap 3577987.41 # Average gap between requests 276system.physmem.pageHitRate 88.22 # Row buffer hit rate, read and write combined 277system.physmem_0.actEnergy 216106380 # Energy for activate commands per rank (pJ) 278system.physmem_0.preEnergy 114863265 # Energy for precharge commands per rank (pJ) 279system.physmem_0.readEnergy 1442258580 # Energy for read commands per rank (pJ) 280system.physmem_0.writeEnergy 305761500 # Energy for write commands per rank (pJ) 281system.physmem_0.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) 282system.physmem_0.actBackEnergy 4158564390 # Energy for active background per rank (pJ) 283system.physmem_0.preBackEnergy 232346880 # Energy for precharge background per rank (pJ) 284system.physmem_0.actPowerDownEnergy 8004158310 # Energy for active power-down per rank (pJ) 285system.physmem_0.prePowerDownEnergy 4220231520 # Energy for precharge power-down per rank (pJ) 286system.physmem_0.selfRefreshEnergy 438996708360 # Energy for self refresh per rank (pJ) 287system.physmem_0.totalEnergy 461312299845 # Total energy per rank (pJ) 288system.physmem_0.averagePower 247.351146 # Core power per rank (mW) 289system.physmem_0.totalIdleTime 1855244620250 # Total Idle time Per DRAM Rank 290system.physmem_0.memoryStateTime::IDLE 361602000 # Time in different power states 291system.physmem_0.memoryStateTime::REF 1537874000 # Time in different power states 292system.physmem_0.memoryStateTime::SREF 1826739481250 # Time in different power states 293system.physmem_0.memoryStateTime::PRE_PDN 10990187750 # Time in different power states 294system.physmem_0.memoryStateTime::ACT 7827619250 # Time in different power states 295system.physmem_0.memoryStateTime::ACT_PDN 17552983750 # Time in different power states 296system.physmem_1.actEnergy 222025440 # Energy for activate commands per rank (pJ) 297system.physmem_1.preEnergy 118005525 # Energy for precharge commands per rank (pJ) 298system.physmem_1.readEnergy 1440038040 # Energy for read commands per rank (pJ) 299system.physmem_1.writeEnergy 307191780 # Energy for write commands per rank (pJ) 300system.physmem_1.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) 301system.physmem_1.actBackEnergy 4104344850 # Energy for active background per rank (pJ) 302system.physmem_1.preBackEnergy 228211680 # Energy for precharge background per rank (pJ) 303system.physmem_1.actPowerDownEnergy 8096599200 # Energy for active power-down per rank (pJ) 304system.physmem_1.prePowerDownEnergy 4247999520 # Energy for precharge power-down per rank (pJ) 305system.physmem_1.selfRefreshEnergy 438951182175 # Energy for self refresh per rank (pJ) 306system.physmem_1.totalEnergy 461336536560 # Total energy per rank (pJ) 307system.physmem_1.averagePower 247.364142 # Core power per rank (mW) 308system.physmem_1.totalIdleTime 1855407985250 # Total Idle time Per DRAM Rank 309system.physmem_1.memoryStateTime::IDLE 350582750 # Time in different power states 310system.physmem_1.memoryStateTime::REF 1537736000 # Time in different power states 311system.physmem_1.memoryStateTime::SREF 1826594899250 # Time in different power states 312system.physmem_1.memoryStateTime::PRE_PDN 11062498750 # Time in different power states 313system.physmem_1.memoryStateTime::ACT 7708202750 # Time in different power states 314system.physmem_1.memoryStateTime::ACT_PDN 17755828500 # Time in different power states 315system.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 316system.bridge.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 317system.cpu.branchPred.lookups 19556212 # Number of BP lookups 318system.cpu.branchPred.condPredicted 16618547 # Number of conditional branches predicted 319system.cpu.branchPred.condIncorrect 593854 # Number of conditional branches incorrect 320system.cpu.branchPred.BTBLookups 12802975 # Number of BTB lookups 321system.cpu.branchPred.BTBHits 5420040 # Number of BTB hits |
| 324system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 322system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 325system.cpu.branchPred.BTBHitPct 42.397071 # BTB Hit Percentage 326system.cpu.branchPred.usedRAS 1123794 # Number of times the RAS was used to get a target. 327system.cpu.branchPred.RASInCorrect 42287 # Number of incorrect RAS predictions. 328system.cpu.branchPred.indirectLookups 6265125 # Number of indirect predictor lookups. 329system.cpu.branchPred.indirectHits 563559 # Number of indirect target hits. 330system.cpu.branchPred.indirectMisses 5701566 # Number of indirect misses. 331system.cpu.branchPredindirectMispredicted 264926 # Number of mispredicted indirect branches. | 323system.cpu.branchPred.BTBHitPct 42.334223 # BTB Hit Percentage 324system.cpu.branchPred.usedRAS 1126473 # Number of times the RAS was used to get a target. 325system.cpu.branchPred.RASInCorrect 42524 # Number of incorrect RAS predictions. 326system.cpu.branchPred.indirectLookups 6261380 # Number of indirect predictor lookups. 327system.cpu.branchPred.indirectHits 563797 # Number of indirect target hits. 328system.cpu.branchPred.indirectMisses 5697583 # Number of indirect misses. 329system.cpu.branchPredindirectMispredicted 265016 # Number of mispredicted indirect branches. |
| 332system.cpu_clk_domain.clock 500 # Clock period in ticks 333system.cpu.dtb.fetch_hits 0 # ITB hits 334system.cpu.dtb.fetch_misses 0 # ITB misses 335system.cpu.dtb.fetch_acv 0 # ITB acv 336system.cpu.dtb.fetch_accesses 0 # ITB accesses | 330system.cpu_clk_domain.clock 500 # Clock period in ticks 331system.cpu.dtb.fetch_hits 0 # ITB hits 332system.cpu.dtb.fetch_misses 0 # ITB misses 333system.cpu.dtb.fetch_acv 0 # ITB acv 334system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 337system.cpu.dtb.read_hits 11133148 # DTB read hits 338system.cpu.dtb.read_misses 49550 # DTB read misses 339system.cpu.dtb.read_acv 604 # DTB read access violations 340system.cpu.dtb.read_accesses 995639 # DTB read accesses 341system.cpu.dtb.write_hits 6779390 # DTB write hits 342system.cpu.dtb.write_misses 12217 # DTB write misses 343system.cpu.dtb.write_acv 419 # DTB write access violations 344system.cpu.dtb.write_accesses 345330 # DTB write accesses 345system.cpu.dtb.data_hits 17912538 # DTB hits 346system.cpu.dtb.data_misses 61767 # DTB misses 347system.cpu.dtb.data_acv 1023 # DTB access violations 348system.cpu.dtb.data_accesses 1340969 # DTB accesses 349system.cpu.itb.fetch_hits 1814760 # ITB hits 350system.cpu.itb.fetch_misses 10379 # ITB misses 351system.cpu.itb.fetch_acv 753 # ITB acv 352system.cpu.itb.fetch_accesses 1825139 # ITB accesses | 335system.cpu.dtb.read_hits 11131129 # DTB read hits 336system.cpu.dtb.read_misses 49734 # DTB read misses 337system.cpu.dtb.read_acv 613 # DTB read access violations 338system.cpu.dtb.read_accesses 995788 # DTB read accesses 339system.cpu.dtb.write_hits 6783534 # DTB write hits 340system.cpu.dtb.write_misses 12230 # DTB write misses 341system.cpu.dtb.write_acv 435 # DTB write access violations 342system.cpu.dtb.write_accesses 345368 # DTB write accesses 343system.cpu.dtb.data_hits 17914663 # DTB hits 344system.cpu.dtb.data_misses 61964 # DTB misses 345system.cpu.dtb.data_acv 1048 # DTB access violations 346system.cpu.dtb.data_accesses 1341156 # DTB accesses 347system.cpu.itb.fetch_hits 1815343 # ITB hits 348system.cpu.itb.fetch_misses 10369 # ITB misses 349system.cpu.itb.fetch_acv 759 # ITB acv 350system.cpu.itb.fetch_accesses 1825712 # ITB accesses |
| 353system.cpu.itb.read_hits 0 # DTB read hits 354system.cpu.itb.read_misses 0 # DTB read misses 355system.cpu.itb.read_acv 0 # DTB read access violations 356system.cpu.itb.read_accesses 0 # DTB read accesses 357system.cpu.itb.write_hits 0 # DTB write hits 358system.cpu.itb.write_misses 0 # DTB write misses 359system.cpu.itb.write_acv 0 # DTB write access violations 360system.cpu.itb.write_accesses 0 # DTB write accesses 361system.cpu.itb.data_hits 0 # DTB hits 362system.cpu.itb.data_misses 0 # DTB misses 363system.cpu.itb.data_acv 0 # DTB access violations 364system.cpu.itb.data_accesses 0 # DTB accesses 365system.cpu.numPwrStateTransitions 12878 # Number of power state transitions 366system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state | 351system.cpu.itb.read_hits 0 # DTB read hits 352system.cpu.itb.read_misses 0 # DTB read misses 353system.cpu.itb.read_acv 0 # DTB read access violations 354system.cpu.itb.read_accesses 0 # DTB read accesses 355system.cpu.itb.write_hits 0 # DTB write hits 356system.cpu.itb.write_misses 0 # DTB write misses 357system.cpu.itb.write_acv 0 # DTB write access violations 358system.cpu.itb.write_accesses 0 # DTB write accesses 359system.cpu.itb.data_hits 0 # DTB hits 360system.cpu.itb.data_misses 0 # DTB misses 361system.cpu.itb.data_acv 0 # DTB access violations 362system.cpu.itb.data_accesses 0 # DTB accesses 363system.cpu.numPwrStateTransitions 12878 # Number of power state transitions 364system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state |
| 367system.cpu.pwrStateClkGateDist::mean 279577818.217114 # Distribution of time spent in the clock gated state 368system.cpu.pwrStateClkGateDist::stdev 438970116.286468 # Distribution of time spent in the clock gated state | 365system.cpu.pwrStateClkGateDist::mean 279575452.943004 # Distribution of time spent in the clock gated state 366system.cpu.pwrStateClkGateDist::stdev 438968142.754116 # Distribution of time spent in the clock gated state |
| 369system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state | 367system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state |
| 370system.cpu.pwrStateClkGateDist::min_value 62000 # Distribution of time spent in the clock gated state | 368system.cpu.pwrStateClkGateDist::min_value 71000 # Distribution of time spent in the clock gated state |
| 371system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 372system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state | 369system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 370system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state |
| 373system.cpu.pwrStateResidencyTicks::ON 64810036000 # Cumulative time (in ticks) in various power states 374system.cpu.pwrStateResidencyTicks::CLK_GATED 1800201571500 # Cumulative time (in ticks) in various power states 375system.cpu.numCycles 129626512 # number of cpu cycles simulated | 371system.cpu.pwrStateResidencyTicks::ON 64823406500 # Cumulative time (in ticks) in various power states 372system.cpu.pwrStateResidencyTicks::CLK_GATED 1800186341500 # Cumulative time (in ticks) in various power states 373system.cpu.numCycles 129653253 # number of cpu cycles simulated |
| 376system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 377system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 374system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 375system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 378system.cpu.fetch.icacheStallCycles 30190363 # Number of cycles fetch is stalled on an Icache miss 379system.cpu.fetch.Insts 85695972 # Number of instructions fetch has processed 380system.cpu.fetch.Branches 19540652 # Number of branches that fetch encountered 381system.cpu.fetch.predictedBranches 7106519 # Number of branches that fetch has predicted taken 382system.cpu.fetch.Cycles 91835709 # Number of cycles fetch has run and was not squashing or blocked 383system.cpu.fetch.SquashCycles 1682318 # Number of cycles fetch has spent squashing 384system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb 385system.cpu.fetch.MiscStallCycles 29737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 386system.cpu.fetch.PendingTrapStallCycles 207098 # Number of stall cycles due to pending traps 387system.cpu.fetch.PendingQuiesceStallCycles 428060 # Number of stall cycles due to pending quiesce instructions 388system.cpu.fetch.IcacheWaitRetryStallCycles 576 # Number of stall cycles due to full MSHR 389system.cpu.fetch.CacheLines 9928105 # Number of cache lines fetched 390system.cpu.fetch.IcacheSquashes 408572 # Number of outstanding Icache misses that were squashed 391system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 392system.cpu.fetch.rateDist::samples 123532763 # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::mean 0.693710 # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::stdev 2.023135 # Number of instructions fetched each cycle (Total) | 376system.cpu.fetch.icacheStallCycles 30226306 # Number of cycles fetch is stalled on an Icache miss 377system.cpu.fetch.Insts 85761758 # Number of instructions fetch has processed 378system.cpu.fetch.Branches 19556212 # Number of branches that fetch encountered 379system.cpu.fetch.predictedBranches 7110310 # Number of branches that fetch has predicted taken 380system.cpu.fetch.Cycles 91828962 # Number of cycles fetch has run and was not squashing or blocked 381system.cpu.fetch.SquashCycles 1682802 # Number of cycles fetch has spent squashing 382system.cpu.fetch.TlbCycles 214 # Number of cycles fetch has spent waiting for tlb 383system.cpu.fetch.MiscStallCycles 31116 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 384system.cpu.fetch.PendingTrapStallCycles 206972 # Number of stall cycles due to pending traps 385system.cpu.fetch.PendingQuiesceStallCycles 428466 # Number of stall cycles due to pending quiesce instructions 386system.cpu.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR 387system.cpu.fetch.CacheLines 9929941 # Number of cache lines fetched 388system.cpu.fetch.IcacheSquashes 408418 # Number of outstanding Icache misses that were squashed 389system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed 390system.cpu.fetch.rateDist::samples 123563934 # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::mean 0.694068 # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::stdev 2.023639 # Number of instructions fetched each cycle (Total) |
| 395system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 393system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 396system.cpu.fetch.rateDist::0 107696719 87.18% 87.18% # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::1 1032377 0.84% 88.02% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::2 2107068 1.71% 89.72% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::3 968796 0.78% 90.51% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::4 2908740 2.35% 92.86% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::5 664008 0.54% 93.40% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::6 809572 0.66% 94.05% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::7 1033225 0.84% 94.89% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::8 6312258 5.11% 100.00% # Number of instructions fetched each cycle (Total) | 394system.cpu.fetch.rateDist::0 107716203 87.17% 87.17% # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::1 1033964 0.84% 88.01% # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::2 2108086 1.71% 89.72% # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::3 968916 0.78% 90.50% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::4 2910075 2.36% 92.86% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::5 665807 0.54% 93.40% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::6 808204 0.65% 94.05% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::7 1035117 0.84% 94.89% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::8 6317562 5.11% 100.00% # Number of instructions fetched each cycle (Total) |
| 405system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 403system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 408system.cpu.fetch.rateDist::total 123532763 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.branchRate 0.150746 # Number of branch fetches per cycle 410system.cpu.fetch.rate 0.661099 # Number of inst fetches per cycle 411system.cpu.decode.IdleCycles 24222797 # Number of cycles decode is idle 412system.cpu.decode.BlockedCycles 86210181 # Number of cycles decode is blocked 413system.cpu.decode.RunCycles 10254650 # Number of cycles decode is running 414system.cpu.decode.UnblockCycles 2038697 # Number of cycles decode is unblocking 415system.cpu.decode.SquashCycles 806437 # Number of cycles decode is squashing 416system.cpu.decode.BranchResolved 738100 # Number of times decode resolved a branch 417system.cpu.decode.BranchMispred 35530 # Number of times decode detected a branch misprediction 418system.cpu.decode.DecodedInsts 74041720 # Number of instructions handled by decode 419system.cpu.decode.SquashedInsts 113425 # Number of squashed instructions handled by decode 420system.cpu.rename.SquashCycles 806437 # Number of cycles rename is squashing 421system.cpu.rename.IdleCycles 25231796 # Number of cycles rename is idle 422system.cpu.rename.BlockCycles 56630169 # Number of cycles rename is blocking 423system.cpu.rename.serializeStallCycles 20045874 # count of cycles rename stalled for serializing inst 424system.cpu.rename.RunCycles 11215615 # Number of cycles rename is running 425system.cpu.rename.UnblockCycles 9602870 # Number of cycles rename is unblocking 426system.cpu.rename.RenamedInsts 71021126 # Number of instructions processed by rename 427system.cpu.rename.ROBFullEvents 199714 # Number of times rename has blocked due to ROB full 428system.cpu.rename.IQFullEvents 2114917 # Number of times rename has blocked due to IQ full 429system.cpu.rename.LQFullEvents 266619 # Number of times rename has blocked due to LQ full 430system.cpu.rename.SQFullEvents 5298821 # Number of times rename has blocked due to SQ full 431system.cpu.rename.RenamedOperands 47846131 # Number of destination operands rename has renamed 432system.cpu.rename.RenameLookups 85558708 # Number of register rename lookups that rename has made 433system.cpu.rename.int_rename_lookups 85377795 # Number of integer rename lookups 434system.cpu.rename.fp_rename_lookups 168460 # Number of floating rename lookups 435system.cpu.rename.CommittedMaps 38170817 # Number of HB maps that are committed 436system.cpu.rename.UndoneMaps 9675306 # Number of HB maps that are undone due to squashing 437system.cpu.rename.serializingInsts 1730146 # count of serializing insts renamed 438system.cpu.rename.tempSerializingInsts 277278 # count of temporary serializing insts renamed 439system.cpu.rename.skidInsts 13907871 # count of insts added to the skid buffer 440system.cpu.memDep0.insertedLoads 11664536 # Number of loads inserted to the mem dependence unit. 441system.cpu.memDep0.insertedStores 7226725 # Number of stores inserted to the mem dependence unit. 442system.cpu.memDep0.conflictingLoads 1727084 # Number of conflicting loads. 443system.cpu.memDep0.conflictingStores 1123210 # Number of conflicting stores. 444system.cpu.iq.iqInstsAdded 62712842 # Number of instructions added to the IQ (excludes non-spec) 445system.cpu.iq.iqNonSpecInstsAdded 2208202 # Number of non-speculative instructions added to the IQ 446system.cpu.iq.iqInstsIssued 60540114 # Number of instructions issued 447system.cpu.iq.iqSquashedInstsIssued 93631 # Number of squashed instructions issued 448system.cpu.iq.iqSquashedInstsExamined 11951500 # Number of squashed instructions iterated over during squash; mainly for profiling 449system.cpu.iq.iqSquashedOperandsExamined 5299174 # Number of squashed operands that are examined and possibly removed from graph 450system.cpu.iq.iqSquashedNonSpecRemoved 1546957 # Number of squashed non-spec instructions that were removed 451system.cpu.iq.issued_per_cycle::samples 123532763 # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::mean 0.490073 # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::stdev 1.235792 # Number of insts issued each cycle | 406system.cpu.fetch.rateDist::total 123563934 # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.branchRate 0.150835 # Number of branch fetches per cycle 408system.cpu.fetch.rate 0.661470 # Number of inst fetches per cycle 409system.cpu.decode.IdleCycles 24256271 # Number of cycles decode is idle 410system.cpu.decode.BlockedCycles 86199481 # Number of cycles decode is blocked 411system.cpu.decode.RunCycles 10262767 # Number of cycles decode is running 412system.cpu.decode.UnblockCycles 2038754 # Number of cycles decode is unblocking 413system.cpu.decode.SquashCycles 806660 # Number of cycles decode is squashing 414system.cpu.decode.BranchResolved 739137 # Number of times decode resolved a branch 415system.cpu.decode.BranchMispred 35567 # Number of times decode detected a branch misprediction 416system.cpu.decode.DecodedInsts 74091152 # Number of instructions handled by decode 417system.cpu.decode.SquashedInsts 113387 # Number of squashed instructions handled by decode 418system.cpu.rename.SquashCycles 806660 # Number of cycles rename is squashing 419system.cpu.rename.IdleCycles 25262123 # Number of cycles rename is idle 420system.cpu.rename.BlockCycles 56608165 # Number of cycles rename is blocking 421system.cpu.rename.serializeStallCycles 20046193 # count of cycles rename stalled for serializing inst 422system.cpu.rename.RunCycles 11227977 # Number of cycles rename is running 423system.cpu.rename.UnblockCycles 9612814 # Number of cycles rename is unblocking 424system.cpu.rename.RenamedInsts 71075345 # Number of instructions processed by rename 425system.cpu.rename.ROBFullEvents 200089 # Number of times rename has blocked due to ROB full 426system.cpu.rename.IQFullEvents 2115758 # Number of times rename has blocked due to IQ full 427system.cpu.rename.LQFullEvents 264182 # Number of times rename has blocked due to LQ full 428system.cpu.rename.SQFullEvents 5312560 # Number of times rename has blocked due to SQ full 429system.cpu.rename.RenamedOperands 47887128 # Number of destination operands rename has renamed 430system.cpu.rename.RenameLookups 85631010 # Number of register rename lookups that rename has made 431system.cpu.rename.int_rename_lookups 85450068 # Number of integer rename lookups 432system.cpu.rename.fp_rename_lookups 168489 # Number of floating rename lookups 433system.cpu.rename.CommittedMaps 38179018 # Number of HB maps that are committed 434system.cpu.rename.UndoneMaps 9708102 # Number of HB maps that are undone due to squashing 435system.cpu.rename.serializingInsts 1730208 # count of serializing insts renamed 436system.cpu.rename.tempSerializingInsts 277739 # count of temporary serializing insts renamed 437system.cpu.rename.skidInsts 13892500 # count of insts added to the skid buffer 438system.cpu.memDep0.insertedLoads 11673351 # Number of loads inserted to the mem dependence unit. 439system.cpu.memDep0.insertedStores 7232744 # Number of stores inserted to the mem dependence unit. 440system.cpu.memDep0.conflictingLoads 1724750 # Number of conflicting loads. 441system.cpu.memDep0.conflictingStores 1099672 # Number of conflicting stores. 442system.cpu.iq.iqInstsAdded 62753291 # Number of instructions added to the IQ (excludes non-spec) 443system.cpu.iq.iqNonSpecInstsAdded 2208700 # Number of non-speculative instructions added to the IQ 444system.cpu.iq.iqInstsIssued 60568136 # Number of instructions issued 445system.cpu.iq.iqSquashedInstsIssued 94532 # Number of squashed instructions issued 446system.cpu.iq.iqSquashedInstsExamined 11982878 # Number of squashed instructions iterated over during squash; mainly for profiling 447system.cpu.iq.iqSquashedOperandsExamined 5316307 # Number of squashed operands that are examined and possibly removed from graph 448system.cpu.iq.iqSquashedNonSpecRemoved 1547451 # Number of squashed non-spec instructions that were removed 449system.cpu.iq.issued_per_cycle::samples 123563934 # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::mean 0.490176 # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::stdev 1.236204 # Number of insts issued each cycle |
| 454system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 452system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 455system.cpu.iq.issued_per_cycle::0 98992964 80.13% 80.13% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::1 10407106 8.42% 88.56% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::2 4428528 3.58% 92.14% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::3 3186499 2.58% 94.72% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::4 3245157 2.63% 97.35% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::5 1605158 1.30% 98.65% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::6 1098083 0.89% 99.54% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::7 432605 0.35% 99.89% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::8 136663 0.11% 100.00% # Number of insts issued each cycle | 453system.cpu.iq.issued_per_cycle::0 99014105 80.13% 80.13% # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::1 10422330 8.43% 88.57% # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::2 4419921 3.58% 92.14% # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::3 3179961 2.57% 94.72% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::4 3252538 2.63% 97.35% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::5 1603803 1.30% 98.65% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::6 1099991 0.89% 99.54% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::7 433312 0.35% 99.89% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::8 137973 0.11% 100.00% # Number of insts issued each cycle |
| 464system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 462system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 467system.cpu.iq.issued_per_cycle::total 123532763 # Number of insts issued each cycle | 465system.cpu.iq.issued_per_cycle::total 123563934 # Number of insts issued each cycle |
| 468system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 466system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 469system.cpu.iq.fu_full::IntAlu 207032 16.63% 16.63% # attempts to use FU when none available 470system.cpu.iq.fu_full::IntMult 1 0.00% 16.63% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available 472system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.63% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemRead 606591 48.74% 65.37% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 372500 29.93% 95.30% # attempts to use FU when none available 502system.cpu.iq.fu_full::FloatMemRead 31949 2.57% 97.87% # attempts to use FU when none available 503system.cpu.iq.fu_full::FloatMemWrite 26498 2.13% 100.00% # attempts to use FU when none available | 467system.cpu.iq.fu_full::IntAlu 206621 16.55% 16.55% # attempts to use FU when none available 468system.cpu.iq.fu_full::IntMult 0 0.00% 16.55% # attempts to use FU when none available 469system.cpu.iq.fu_full::IntDiv 0 0.00% 16.55% # attempts to use FU when none available 470system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.55% # attempts to use FU when none available 471system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.55% # attempts to use FU when none available 472system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.55% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatMult 0 0.00% 16.55% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.55% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.55% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.55% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.55% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.55% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.55% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.55% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.55% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.55% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdMult 0 0.00% 16.55% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.55% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdShift 0 0.00% 16.55% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.55% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.55% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.55% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.55% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.55% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.55% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.55% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.55% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.55% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.55% # attempts to use FU when none available 498system.cpu.iq.fu_full::MemRead 610635 48.92% 65.47% # attempts to use FU when none available 499system.cpu.iq.fu_full::MemWrite 372589 29.85% 95.32% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatMemRead 31948 2.56% 97.88% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatMemWrite 26502 2.12% 100.00% # attempts to use FU when none available |
| 504system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 505system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 506system.cpu.iq.FU_type_0::No_OpClass 7276 0.01% 0.01% # Type of FU issued 507system.cpu.iq.FU_type_0::IntAlu 40915146 67.58% 67.60% # Type of FU issued 508system.cpu.iq.FU_type_0::IntMult 62152 0.10% 67.70% # Type of FU issued | 504system.cpu.iq.FU_type_0::No_OpClass 7279 0.01% 0.01% # Type of FU issued 505system.cpu.iq.FU_type_0::IntAlu 40937281 67.59% 67.60% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 62136 0.10% 67.70% # Type of FU issued |
| 509system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued | 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued |
| 510system.cpu.iq.FU_type_0::FloatAdd 38560 0.06% 67.76% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued | 508system.cpu.iq.FU_type_0::FloatAdd 38562 0.06% 67.77% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.77% # Type of FU issued |
| 515system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued 516system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 530system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued | 513system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 528system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued |
| 538system.cpu.iq.FU_type_0::MemRead 11521390 19.03% 86.80% # Type of FU issued 539system.cpu.iq.FU_type_0::MemWrite 6745321 11.14% 97.94% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatMemRead 156180 0.26% 98.20% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatMemWrite 141327 0.23% 98.43% # Type of FU issued | 536system.cpu.iq.FU_type_0::MemRead 11522525 19.02% 86.80% # Type of FU issued 537system.cpu.iq.FU_type_0::MemWrite 6750152 11.14% 97.94% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatMemRead 156092 0.26% 98.20% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatMemWrite 141347 0.23% 98.43% # Type of FU issued |
| 542system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued 543system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 540system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued 541system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 544system.cpu.iq.FU_type_0::total 60540114 # Type of FU issued 545system.cpu.iq.rate 0.467035 # Inst issue rate 546system.cpu.iq.fu_busy_cnt 1244571 # FU busy when requested 547system.cpu.iq.fu_busy_rate 0.020558 # FU busy rate (busy events/executed inst) 548system.cpu.iq.int_inst_queue_reads 245211528 # Number of integer instruction queue reads 549system.cpu.iq.int_inst_queue_writes 76534751 # Number of integer instruction queue writes 550system.cpu.iq.int_inst_queue_wakeup_accesses 58316055 # Number of integer instruction queue wakeup accesses 551system.cpu.iq.fp_inst_queue_reads 739664 # Number of floating instruction queue reads 552system.cpu.iq.fp_inst_queue_writes 359442 # Number of floating instruction queue writes 553system.cpu.iq.fp_inst_queue_wakeup_accesses 336937 # Number of floating instruction queue wakeup accesses 554system.cpu.iq.int_alu_accesses 61379259 # Number of integer alu accesses 555system.cpu.iq.fp_alu_accesses 398150 # Number of floating point alu accesses 556system.cpu.iew.lsq.thread0.forwLoads 691177 # Number of loads that had data forwarded from stores | 542system.cpu.iq.FU_type_0::total 60568136 # Type of FU issued 543system.cpu.iq.rate 0.467155 # Inst issue rate 544system.cpu.iq.fu_busy_cnt 1248295 # FU busy when requested 545system.cpu.iq.fu_busy_rate 0.020610 # FU busy rate (busy events/executed inst) 546system.cpu.iq.int_inst_queue_reads 245303428 # Number of integer instruction queue reads 547system.cpu.iq.int_inst_queue_writes 76606948 # Number of integer instruction queue writes 548system.cpu.iq.int_inst_queue_wakeup_accesses 58345447 # Number of integer instruction queue wakeup accesses 549system.cpu.iq.fp_inst_queue_reads 739604 # Number of floating instruction queue reads 550system.cpu.iq.fp_inst_queue_writes 359470 # Number of floating instruction queue writes 551system.cpu.iq.fp_inst_queue_wakeup_accesses 336798 # Number of floating instruction queue wakeup accesses 552system.cpu.iq.int_alu_accesses 61411065 # Number of integer alu accesses 553system.cpu.iq.fp_alu_accesses 398087 # Number of floating point alu accesses 554system.cpu.iew.lsq.thread0.forwLoads 692317 # Number of loads that had data forwarded from stores |
| 557system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 555system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 558system.cpu.iew.lsq.thread0.squashedLoads 2573780 # Number of loads squashed 559system.cpu.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed 560system.cpu.iew.lsq.thread0.memOrderViolation 22128 # Number of memory ordering violations 561system.cpu.iew.lsq.thread0.squashedStores 849514 # Number of stores squashed | 556system.cpu.iew.lsq.thread0.squashedLoads 2580830 # Number of loads squashed 557system.cpu.iew.lsq.thread0.ignoredResponses 3930 # Number of memory responses ignored because the instruction is squashed 558system.cpu.iew.lsq.thread0.memOrderViolation 22198 # Number of memory ordering violations 559system.cpu.iew.lsq.thread0.squashedStores 854795 # Number of stores squashed |
| 562system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 563system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 560system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 561system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 564system.cpu.iew.lsq.thread0.rescheduledLoads 18020 # Number of loads that were rescheduled 565system.cpu.iew.lsq.thread0.cacheBlocked 462679 # Number of times an access to memory failed due to the cache being blocked | 562system.cpu.iew.lsq.thread0.rescheduledLoads 17998 # Number of loads that were rescheduled 563system.cpu.iew.lsq.thread0.cacheBlocked 456632 # Number of times an access to memory failed due to the cache being blocked |
| 566system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 564system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 567system.cpu.iew.iewSquashCycles 806437 # Number of cycles IEW is squashing 568system.cpu.iew.iewBlockCycles 52697038 # Number of cycles IEW is blocking 569system.cpu.iew.iewUnblockCycles 1357053 # Number of cycles IEW is unblocking 570system.cpu.iew.iewDispatchedInsts 68903527 # Number of instructions dispatched to IQ 571system.cpu.iew.iewDispSquashedInsts 198807 # Number of squashed instructions skipped by dispatch 572system.cpu.iew.iewDispLoadInsts 11664536 # Number of dispatched load instructions 573system.cpu.iew.iewDispStoreInsts 7226725 # Number of dispatched store instructions 574system.cpu.iew.iewDispNonSpecInsts 1959166 # Number of dispatched non-speculative instructions 575system.cpu.iew.iewIQFullEvents 45872 # Number of times the IQ has become full, causing a stall 576system.cpu.iew.iewLSQFullEvents 1108146 # Number of times the LSQ has become full, causing a stall 577system.cpu.iew.memOrderViolationEvents 22128 # Number of memory order violations 578system.cpu.iew.predictedTakenIncorrect 230653 # Number of branches that were predicted taken incorrectly 579system.cpu.iew.predictedNotTakenIncorrect 630212 # Number of branches that were predicted not taken incorrectly 580system.cpu.iew.branchMispredicts 860865 # Number of branch mispredicts detected at execute 581system.cpu.iew.iewExecutedInsts 59685899 # Number of executed instructions 582system.cpu.iew.iewExecLoadInsts 11215511 # Number of load instructions executed 583system.cpu.iew.iewExecSquashedInsts 854214 # Number of squashed instructions skipped in execute | 565system.cpu.iew.iewSquashCycles 806660 # Number of cycles IEW is squashing 566system.cpu.iew.iewBlockCycles 52694504 # Number of cycles IEW is blocking 567system.cpu.iew.iewUnblockCycles 1340713 # Number of cycles IEW is unblocking 568system.cpu.iew.iewDispatchedInsts 68945664 # Number of instructions dispatched to IQ 569system.cpu.iew.iewDispSquashedInsts 202125 # Number of squashed instructions skipped by dispatch 570system.cpu.iew.iewDispLoadInsts 11673351 # Number of dispatched load instructions 571system.cpu.iew.iewDispStoreInsts 7232744 # Number of dispatched store instructions 572system.cpu.iew.iewDispNonSpecInsts 1959731 # Number of dispatched non-speculative instructions 573system.cpu.iew.iewIQFullEvents 45749 # Number of times the IQ has become full, causing a stall 574system.cpu.iew.iewLSQFullEvents 1091638 # Number of times the LSQ has become full, causing a stall 575system.cpu.iew.memOrderViolationEvents 22198 # Number of memory order violations 576system.cpu.iew.predictedTakenIncorrect 229988 # Number of branches that were predicted taken incorrectly 577system.cpu.iew.predictedNotTakenIncorrect 630611 # Number of branches that were predicted not taken incorrectly 578system.cpu.iew.branchMispredicts 860599 # Number of branch mispredicts detected at execute 579system.cpu.iew.iewExecutedInsts 59710531 # Number of executed instructions 580system.cpu.iew.iewExecLoadInsts 11213503 # Number of load instructions executed 581system.cpu.iew.iewExecSquashedInsts 857604 # Number of squashed instructions skipped in execute |
| 584system.cpu.iew.exec_swp 0 # number of swp insts executed | 582system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 585system.cpu.iew.exec_nop 3982483 # number of nop insts executed 586system.cpu.iew.exec_refs 18027322 # number of memory reference insts executed 587system.cpu.iew.exec_branches 9384105 # Number of branches executed 588system.cpu.iew.exec_stores 6811811 # Number of stores executed 589system.cpu.iew.exec_rate 0.460445 # Inst execution rate 590system.cpu.iew.wb_sent 58897557 # cumulative count of insts sent to commit 591system.cpu.iew.wb_count 58652992 # cumulative count of insts written-back 592system.cpu.iew.wb_producers 29769052 # num instructions producing a value 593system.cpu.iew.wb_consumers 41264413 # num instructions consuming a value 594system.cpu.iew.wb_rate 0.452477 # insts written-back per cycle 595system.cpu.iew.wb_fanout 0.721422 # average fanout of values written-back 596system.cpu.commit.commitSquashedInsts 12552458 # The number of squashed insts skipped by commit 597system.cpu.commit.commitNonSpecStalls 661245 # The number of times commit has been forced to stall to communicate backwards 598system.cpu.commit.branchMispredicts 769809 # The number of times a branch was mispredicted 599system.cpu.commit.committed_per_cycle::samples 121361631 # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::mean 0.462746 # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::stdev 1.395074 # Number of insts commited each cycle | 583system.cpu.iew.exec_nop 3983673 # number of nop insts executed 584system.cpu.iew.exec_refs 18029484 # number of memory reference insts executed 585system.cpu.iew.exec_branches 9387402 # Number of branches executed 586system.cpu.iew.exec_stores 6815981 # Number of stores executed 587system.cpu.iew.exec_rate 0.460540 # Inst execution rate 588system.cpu.iew.wb_sent 58927059 # cumulative count of insts sent to commit 589system.cpu.iew.wb_count 58682245 # cumulative count of insts written-back 590system.cpu.iew.wb_producers 29779151 # num instructions producing a value 591system.cpu.iew.wb_consumers 41279871 # num instructions consuming a value 592system.cpu.iew.wb_rate 0.452609 # insts written-back per cycle 593system.cpu.iew.wb_fanout 0.721396 # average fanout of values written-back 594system.cpu.commit.commitSquashedInsts 12584544 # The number of squashed insts skipped by commit 595system.cpu.commit.commitNonSpecStalls 661249 # The number of times commit has been forced to stall to communicate backwards 596system.cpu.commit.branchMispredicts 770143 # The number of times a branch was mispredicted 597system.cpu.commit.committed_per_cycle::samples 121389515 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::mean 0.462724 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::stdev 1.395132 # Number of insts commited each cycle |
| 602system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 600system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 603system.cpu.commit.committed_per_cycle::0 101505032 83.64% 83.64% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::1 7973925 6.57% 90.21% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::2 4190958 3.45% 93.66% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::3 2263923 1.87% 95.53% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::4 1758393 1.45% 96.98% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::5 630847 0.52% 97.50% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::6 481222 0.40% 97.89% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::7 521755 0.43% 98.32% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::8 2035576 1.68% 100.00% # Number of insts commited each cycle | 601system.cpu.commit.committed_per_cycle::0 101523124 83.63% 83.63% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::1 7984339 6.58% 90.21% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::2 4194668 3.46% 93.67% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::3 2261790 1.86% 95.53% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::4 1754136 1.45% 96.98% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::5 633873 0.52% 97.50% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::6 481376 0.40% 97.89% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::7 513083 0.42% 98.32% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::8 2043126 1.68% 100.00% # Number of insts commited each cycle |
| 612system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 610system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 615system.cpu.commit.committed_per_cycle::total 121361631 # Number of insts commited each cycle 616system.cpu.commit.committedInsts 56159642 # Number of instructions committed 617system.cpu.commit.committedOps 56159642 # Number of ops (including micro ops) committed | 613system.cpu.commit.committed_per_cycle::total 121389515 # Number of insts commited each cycle 614system.cpu.commit.committedInsts 56169799 # Number of instructions committed 615system.cpu.commit.committedOps 56169799 # Number of ops (including micro ops) committed |
| 618system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 616system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 619system.cpu.commit.refs 15467967 # Number of memory references committed 620system.cpu.commit.loads 9090756 # Number of loads committed 621system.cpu.commit.membars 226364 # Number of memory barriers committed 622system.cpu.commit.branches 8439956 # Number of branches committed | 617system.cpu.commit.refs 15470470 # Number of memory references committed 618system.cpu.commit.loads 9092521 # Number of loads committed 619system.cpu.commit.membars 226360 # Number of memory barriers committed 620system.cpu.commit.branches 8440690 # Number of branches committed |
| 623system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 621system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 624system.cpu.commit.int_insts 52009640 # Number of committed integer instructions. 625system.cpu.commit.function_calls 740476 # Number of function calls committed. 626system.cpu.commit.op_class_0::No_OpClass 3197376 5.69% 5.69% # Class of committed instruction 627system.cpu.commit.op_class_0::IntAlu 36210459 64.48% 70.17% # Class of committed instruction 628system.cpu.commit.op_class_0::IntMult 60672 0.11% 70.28% # Class of committed instruction | 622system.cpu.commit.int_insts 52019202 # Number of committed integer instructions. 623system.cpu.commit.function_calls 740566 # Number of function calls committed. 624system.cpu.commit.op_class_0::No_OpClass 3197964 5.69% 5.69% # Class of committed instruction 625system.cpu.commit.op_class_0::IntAlu 36217526 64.48% 70.17% # Class of committed instruction 626system.cpu.commit.op_class_0::IntMult 60675 0.11% 70.28% # Class of committed instruction |
| 629system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 630system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 631system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 632system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 633system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 634system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction 635system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 636system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction --- 13 unchanged lines hidden (view full) --- 650system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction | 627system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 628system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 629system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 630system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 631system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 632system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction 633system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 634system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction --- 13 unchanged lines hidden (view full) --- 648system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction |
| 658system.cpu.commit.op_class_0::MemRead 9172524 16.33% 86.69% # Class of committed instruction 659system.cpu.commit.op_class_0::MemWrite 6245101 11.12% 97.81% # Class of committed instruction | 656system.cpu.commit.op_class_0::MemRead 9174285 16.33% 86.69% # Class of committed instruction 657system.cpu.commit.op_class_0::MemWrite 6245839 11.12% 97.81% # Class of committed instruction |
| 660system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction 661system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction 662system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction 663system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 658system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction 659system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction 660system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction 661system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 664system.cpu.commit.op_class_0::total 56159642 # Class of committed instruction 665system.cpu.commit.bw_lim_events 2035576 # number cycles where commit BW limit reached 666system.cpu.rob.rob_reads 187788618 # The number of ROB reads 667system.cpu.rob.rob_writes 139599579 # The number of ROB writes 668system.cpu.timesIdled 556181 # Number of times that the entire CPU went into an idle state and unscheduled itself 669system.cpu.idleCycles 6093749 # Total number of cycles that the CPU has spent unscheduled due to idling 670system.cpu.quiesceCycles 3600396704 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 671system.cpu.committedInsts 52969539 # Number of Instructions Simulated 672system.cpu.committedOps 52969539 # Number of Ops (including micro ops) Simulated 673system.cpu.cpi 2.447190 # CPI: Cycles Per Instruction 674system.cpu.cpi_total 2.447190 # CPI: Total CPI of All Threads 675system.cpu.ipc 0.408632 # IPC: Instructions Per Cycle 676system.cpu.ipc_total 0.408632 # IPC: Total IPC of All Threads 677system.cpu.int_regfile_reads 77875050 # number of integer regfile reads 678system.cpu.int_regfile_writes 42594378 # number of integer regfile writes 679system.cpu.fp_regfile_reads 166655 # number of floating regfile reads 680system.cpu.fp_regfile_writes 175866 # number of floating regfile writes 681system.cpu.misc_regfile_reads 2002132 # number of misc regfile reads 682system.cpu.misc_regfile_writes 939499 # number of misc regfile writes 683system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 684system.cpu.dcache.tags.replacements 1405977 # number of replacements | 662system.cpu.commit.op_class_0::total 56169799 # Class of committed instruction 663system.cpu.commit.bw_lim_events 2043126 # number cycles where commit BW limit reached 664system.cpu.rob.rob_reads 187851195 # The number of ROB reads 665system.cpu.rob.rob_writes 139687376 # The number of ROB writes 666system.cpu.timesIdled 556781 # Number of times that the entire CPU went into an idle state and unscheduled itself 667system.cpu.idleCycles 6089319 # Total number of cycles that the CPU has spent unscheduled due to idling 668system.cpu.quiesceCycles 3600366244 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 669system.cpu.committedInsts 52979108 # Number of Instructions Simulated 670system.cpu.committedOps 52979108 # Number of Ops (including micro ops) Simulated 671system.cpu.cpi 2.447252 # CPI: Cycles Per Instruction 672system.cpu.cpi_total 2.447252 # CPI: Total CPI of All Threads 673system.cpu.ipc 0.408622 # IPC: Instructions Per Cycle 674system.cpu.ipc_total 0.408622 # IPC: Total IPC of All Threads 675system.cpu.int_regfile_reads 77910051 # number of integer regfile reads 676system.cpu.int_regfile_writes 42617580 # number of integer regfile writes 677system.cpu.fp_regfile_reads 166665 # number of floating regfile reads 678system.cpu.fp_regfile_writes 175716 # number of floating regfile writes 679system.cpu.misc_regfile_reads 2001313 # number of misc regfile reads 680system.cpu.misc_regfile_writes 939513 # number of misc regfile writes 681system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 682system.cpu.dcache.tags.replacements 1405851 # number of replacements |
| 685system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use | 683system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use |
| 686system.cpu.dcache.tags.total_refs 12626898 # Total number of references to valid blocks. 687system.cpu.dcache.tags.sampled_refs 1406489 # Sample count of references to valid blocks. 688system.cpu.dcache.tags.avg_refs 8.977602 # Average number of references to valid blocks. | 684system.cpu.dcache.tags.total_refs 12629128 # Total number of references to valid blocks. 685system.cpu.dcache.tags.sampled_refs 1406363 # Sample count of references to valid blocks. 686system.cpu.dcache.tags.avg_refs 8.979992 # Average number of references to valid blocks. |
| 689system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit. 690system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor 691system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy 692system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy 693system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 694system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id 695system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 696system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 697system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 687system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit. 688system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor 689system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy 690system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy 691system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 692system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id 693system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 694system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 695system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 698system.cpu.dcache.tags.tag_accesses 67141007 # Number of tag accesses 699system.cpu.dcache.tags.data_accesses 67141007 # Number of data accesses 700system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 701system.cpu.dcache.ReadReq_hits::cpu.data 8018368 # number of ReadReq hits 702system.cpu.dcache.ReadReq_hits::total 8018368 # number of ReadReq hits 703system.cpu.dcache.WriteReq_hits::cpu.data 4180367 # number of WriteReq hits 704system.cpu.dcache.WriteReq_hits::total 4180367 # number of WriteReq hits 705system.cpu.dcache.LoadLockedReq_hits::cpu.data 212226 # number of LoadLockedReq hits 706system.cpu.dcache.LoadLockedReq_hits::total 212226 # number of LoadLockedReq hits 707system.cpu.dcache.StoreCondReq_hits::cpu.data 215667 # number of StoreCondReq hits 708system.cpu.dcache.StoreCondReq_hits::total 215667 # number of StoreCondReq hits 709system.cpu.dcache.demand_hits::cpu.data 12198735 # number of demand (read+write) hits 710system.cpu.dcache.demand_hits::total 12198735 # number of demand (read+write) hits 711system.cpu.dcache.overall_hits::cpu.data 12198735 # number of overall hits 712system.cpu.dcache.overall_hits::total 12198735 # number of overall hits 713system.cpu.dcache.ReadReq_misses::cpu.data 1817070 # number of ReadReq misses 714system.cpu.dcache.ReadReq_misses::total 1817070 # number of ReadReq misses 715system.cpu.dcache.WriteReq_misses::cpu.data 1966374 # number of WriteReq misses 716system.cpu.dcache.WriteReq_misses::total 1966374 # number of WriteReq misses 717system.cpu.dcache.LoadLockedReq_misses::cpu.data 23459 # number of LoadLockedReq misses 718system.cpu.dcache.LoadLockedReq_misses::total 23459 # number of LoadLockedReq misses 719system.cpu.dcache.StoreCondReq_misses::cpu.data 98 # number of StoreCondReq misses 720system.cpu.dcache.StoreCondReq_misses::total 98 # number of StoreCondReq misses 721system.cpu.dcache.demand_misses::cpu.data 3783444 # number of demand (read+write) misses 722system.cpu.dcache.demand_misses::total 3783444 # number of demand (read+write) misses 723system.cpu.dcache.overall_misses::cpu.data 3783444 # number of overall misses 724system.cpu.dcache.overall_misses::total 3783444 # number of overall misses 725system.cpu.dcache.ReadReq_miss_latency::cpu.data 45126424500 # number of ReadReq miss cycles 726system.cpu.dcache.ReadReq_miss_latency::total 45126424500 # number of ReadReq miss cycles 727system.cpu.dcache.WriteReq_miss_latency::cpu.data 92431305073 # number of WriteReq miss cycles 728system.cpu.dcache.WriteReq_miss_latency::total 92431305073 # number of WriteReq miss cycles 729system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 416761500 # number of LoadLockedReq miss cycles 730system.cpu.dcache.LoadLockedReq_miss_latency::total 416761500 # number of LoadLockedReq miss cycles 731system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1368500 # number of StoreCondReq miss cycles 732system.cpu.dcache.StoreCondReq_miss_latency::total 1368500 # number of StoreCondReq miss cycles 733system.cpu.dcache.demand_miss_latency::cpu.data 137557729573 # number of demand (read+write) miss cycles 734system.cpu.dcache.demand_miss_latency::total 137557729573 # number of demand (read+write) miss cycles 735system.cpu.dcache.overall_miss_latency::cpu.data 137557729573 # number of overall miss cycles 736system.cpu.dcache.overall_miss_latency::total 137557729573 # number of overall miss cycles 737system.cpu.dcache.ReadReq_accesses::cpu.data 9835438 # number of ReadReq accesses(hits+misses) 738system.cpu.dcache.ReadReq_accesses::total 9835438 # number of ReadReq accesses(hits+misses) 739system.cpu.dcache.WriteReq_accesses::cpu.data 6146741 # number of WriteReq accesses(hits+misses) 740system.cpu.dcache.WriteReq_accesses::total 6146741 # number of WriteReq accesses(hits+misses) 741system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235685 # number of LoadLockedReq accesses(hits+misses) 742system.cpu.dcache.LoadLockedReq_accesses::total 235685 # number of LoadLockedReq accesses(hits+misses) 743system.cpu.dcache.StoreCondReq_accesses::cpu.data 215765 # number of StoreCondReq accesses(hits+misses) 744system.cpu.dcache.StoreCondReq_accesses::total 215765 # number of StoreCondReq accesses(hits+misses) 745system.cpu.dcache.demand_accesses::cpu.data 15982179 # number of demand (read+write) accesses 746system.cpu.dcache.demand_accesses::total 15982179 # number of demand (read+write) accesses 747system.cpu.dcache.overall_accesses::cpu.data 15982179 # number of overall (read+write) accesses 748system.cpu.dcache.overall_accesses::total 15982179 # number of overall (read+write) accesses 749system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184747 # miss rate for ReadReq accesses 750system.cpu.dcache.ReadReq_miss_rate::total 0.184747 # miss rate for ReadReq accesses 751system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319905 # miss rate for WriteReq accesses 752system.cpu.dcache.WriteReq_miss_rate::total 0.319905 # miss rate for WriteReq accesses 753system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099535 # miss rate for LoadLockedReq accesses 754system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099535 # miss rate for LoadLockedReq accesses 755system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000454 # miss rate for StoreCondReq accesses 756system.cpu.dcache.StoreCondReq_miss_rate::total 0.000454 # miss rate for StoreCondReq accesses 757system.cpu.dcache.demand_miss_rate::cpu.data 0.236729 # miss rate for demand accesses 758system.cpu.dcache.demand_miss_rate::total 0.236729 # miss rate for demand accesses 759system.cpu.dcache.overall_miss_rate::cpu.data 0.236729 # miss rate for overall accesses 760system.cpu.dcache.overall_miss_rate::total 0.236729 # miss rate for overall accesses 761system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24834.719906 # average ReadReq miss latency 762system.cpu.dcache.ReadReq_avg_miss_latency::total 24834.719906 # average ReadReq miss latency 763system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47005.963806 # average WriteReq miss latency 764system.cpu.dcache.WriteReq_avg_miss_latency::total 47005.963806 # average WriteReq miss latency 765system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17765.527090 # average LoadLockedReq miss latency 766system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17765.527090 # average LoadLockedReq miss latency 767system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13964.285714 # average StoreCondReq miss latency 768system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13964.285714 # average StoreCondReq miss latency 769system.cpu.dcache.demand_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency 770system.cpu.dcache.demand_avg_miss_latency::total 36357.807747 # average overall miss latency 771system.cpu.dcache.overall_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency 772system.cpu.dcache.overall_avg_miss_latency::total 36357.807747 # average overall miss latency 773system.cpu.dcache.blocked_cycles::no_mshrs 4938618 # number of cycles access was blocked 774system.cpu.dcache.blocked_cycles::no_targets 4294 # number of cycles access was blocked 775system.cpu.dcache.blocked::no_mshrs 133157 # number of cycles access was blocked | 696system.cpu.dcache.tags.tag_accesses 67152661 # Number of tag accesses 697system.cpu.dcache.tags.data_accesses 67152661 # Number of data accesses 698system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 699system.cpu.dcache.ReadReq_hits::cpu.data 8020035 # number of ReadReq hits 700system.cpu.dcache.ReadReq_hits::total 8020035 # number of ReadReq hits 701system.cpu.dcache.WriteReq_hits::cpu.data 4180765 # number of WriteReq hits 702system.cpu.dcache.WriteReq_hits::total 4180765 # number of WriteReq hits 703system.cpu.dcache.LoadLockedReq_hits::cpu.data 212398 # number of LoadLockedReq hits 704system.cpu.dcache.LoadLockedReq_hits::total 212398 # number of LoadLockedReq hits 705system.cpu.dcache.StoreCondReq_hits::cpu.data 215680 # number of StoreCondReq hits 706system.cpu.dcache.StoreCondReq_hits::total 215680 # number of StoreCondReq hits 707system.cpu.dcache.demand_hits::cpu.data 12200800 # number of demand (read+write) hits 708system.cpu.dcache.demand_hits::total 12200800 # number of demand (read+write) hits 709system.cpu.dcache.overall_hits::cpu.data 12200800 # number of overall hits 710system.cpu.dcache.overall_hits::total 12200800 # number of overall hits 711system.cpu.dcache.ReadReq_misses::cpu.data 1817327 # number of ReadReq misses 712system.cpu.dcache.ReadReq_misses::total 1817327 # number of ReadReq misses 713system.cpu.dcache.WriteReq_misses::cpu.data 1966706 # number of WriteReq misses 714system.cpu.dcache.WriteReq_misses::total 1966706 # number of WriteReq misses 715system.cpu.dcache.LoadLockedReq_misses::cpu.data 23570 # number of LoadLockedReq misses 716system.cpu.dcache.LoadLockedReq_misses::total 23570 # number of LoadLockedReq misses 717system.cpu.dcache.StoreCondReq_misses::cpu.data 93 # number of StoreCondReq misses 718system.cpu.dcache.StoreCondReq_misses::total 93 # number of StoreCondReq misses 719system.cpu.dcache.demand_misses::cpu.data 3784033 # number of demand (read+write) misses 720system.cpu.dcache.demand_misses::total 3784033 # number of demand (read+write) misses 721system.cpu.dcache.overall_misses::cpu.data 3784033 # number of overall misses 722system.cpu.dcache.overall_misses::total 3784033 # number of overall misses 723system.cpu.dcache.ReadReq_miss_latency::cpu.data 45159601500 # number of ReadReq miss cycles 724system.cpu.dcache.ReadReq_miss_latency::total 45159601500 # number of ReadReq miss cycles 725system.cpu.dcache.WriteReq_miss_latency::cpu.data 92703832258 # number of WriteReq miss cycles 726system.cpu.dcache.WriteReq_miss_latency::total 92703832258 # number of WriteReq miss cycles 727system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 420302500 # number of LoadLockedReq miss cycles 728system.cpu.dcache.LoadLockedReq_miss_latency::total 420302500 # number of LoadLockedReq miss cycles 729system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1299500 # number of StoreCondReq miss cycles 730system.cpu.dcache.StoreCondReq_miss_latency::total 1299500 # number of StoreCondReq miss cycles 731system.cpu.dcache.demand_miss_latency::cpu.data 137863433758 # number of demand (read+write) miss cycles 732system.cpu.dcache.demand_miss_latency::total 137863433758 # number of demand (read+write) miss cycles 733system.cpu.dcache.overall_miss_latency::cpu.data 137863433758 # number of overall miss cycles 734system.cpu.dcache.overall_miss_latency::total 137863433758 # number of overall miss cycles 735system.cpu.dcache.ReadReq_accesses::cpu.data 9837362 # number of ReadReq accesses(hits+misses) 736system.cpu.dcache.ReadReq_accesses::total 9837362 # number of ReadReq accesses(hits+misses) 737system.cpu.dcache.WriteReq_accesses::cpu.data 6147471 # number of WriteReq accesses(hits+misses) 738system.cpu.dcache.WriteReq_accesses::total 6147471 # number of WriteReq accesses(hits+misses) 739system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235968 # number of LoadLockedReq accesses(hits+misses) 740system.cpu.dcache.LoadLockedReq_accesses::total 235968 # number of LoadLockedReq accesses(hits+misses) 741system.cpu.dcache.StoreCondReq_accesses::cpu.data 215773 # number of StoreCondReq accesses(hits+misses) 742system.cpu.dcache.StoreCondReq_accesses::total 215773 # number of StoreCondReq accesses(hits+misses) 743system.cpu.dcache.demand_accesses::cpu.data 15984833 # number of demand (read+write) accesses 744system.cpu.dcache.demand_accesses::total 15984833 # number of demand (read+write) accesses 745system.cpu.dcache.overall_accesses::cpu.data 15984833 # number of overall (read+write) accesses 746system.cpu.dcache.overall_accesses::total 15984833 # number of overall (read+write) accesses 747system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184737 # miss rate for ReadReq accesses 748system.cpu.dcache.ReadReq_miss_rate::total 0.184737 # miss rate for ReadReq accesses 749system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319921 # miss rate for WriteReq accesses 750system.cpu.dcache.WriteReq_miss_rate::total 0.319921 # miss rate for WriteReq accesses 751system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099886 # miss rate for LoadLockedReq accesses 752system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099886 # miss rate for LoadLockedReq accesses 753system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000431 # miss rate for StoreCondReq accesses 754system.cpu.dcache.StoreCondReq_miss_rate::total 0.000431 # miss rate for StoreCondReq accesses 755system.cpu.dcache.demand_miss_rate::cpu.data 0.236726 # miss rate for demand accesses 756system.cpu.dcache.demand_miss_rate::total 0.236726 # miss rate for demand accesses 757system.cpu.dcache.overall_miss_rate::cpu.data 0.236726 # miss rate for overall accesses 758system.cpu.dcache.overall_miss_rate::total 0.236726 # miss rate for overall accesses 759system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24849.463800 # average ReadReq miss latency 760system.cpu.dcache.ReadReq_avg_miss_latency::total 24849.463800 # average ReadReq miss latency 761system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47136.599094 # average WriteReq miss latency 762system.cpu.dcache.WriteReq_avg_miss_latency::total 47136.599094 # average WriteReq miss latency 763system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17832.095885 # average LoadLockedReq miss latency 764system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17832.095885 # average LoadLockedReq miss latency 765system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13973.118280 # average StoreCondReq miss latency 766system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13973.118280 # average StoreCondReq miss latency 767system.cpu.dcache.demand_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency 768system.cpu.dcache.demand_avg_miss_latency::total 36432.936435 # average overall miss latency 769system.cpu.dcache.overall_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency 770system.cpu.dcache.overall_avg_miss_latency::total 36432.936435 # average overall miss latency 771system.cpu.dcache.blocked_cycles::no_mshrs 4933871 # number of cycles access was blocked 772system.cpu.dcache.blocked_cycles::no_targets 2725 # number of cycles access was blocked 773system.cpu.dcache.blocked::no_mshrs 132268 # number of cycles access was blocked |
| 776system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked | 774system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked |
| 777system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.088685 # average number of cycles each access was blocked 778system.cpu.dcache.avg_blocked_cycles::no_targets 153.357143 # average number of cycles each access was blocked 779system.cpu.dcache.writebacks::writebacks 844399 # number of writebacks 780system.cpu.dcache.writebacks::total 844399 # number of writebacks 781system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716933 # number of ReadReq MSHR hits 782system.cpu.dcache.ReadReq_mshr_hits::total 716933 # number of ReadReq MSHR hits 783system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676859 # number of WriteReq MSHR hits 784system.cpu.dcache.WriteReq_mshr_hits::total 1676859 # number of WriteReq MSHR hits 785system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6505 # number of LoadLockedReq MSHR hits 786system.cpu.dcache.LoadLockedReq_mshr_hits::total 6505 # number of LoadLockedReq MSHR hits 787system.cpu.dcache.demand_mshr_hits::cpu.data 2393792 # number of demand (read+write) MSHR hits 788system.cpu.dcache.demand_mshr_hits::total 2393792 # number of demand (read+write) MSHR hits 789system.cpu.dcache.overall_mshr_hits::cpu.data 2393792 # number of overall MSHR hits 790system.cpu.dcache.overall_mshr_hits::total 2393792 # number of overall MSHR hits 791system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100137 # number of ReadReq MSHR misses 792system.cpu.dcache.ReadReq_mshr_misses::total 1100137 # number of ReadReq MSHR misses 793system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289515 # number of WriteReq MSHR misses 794system.cpu.dcache.WriteReq_mshr_misses::total 289515 # number of WriteReq MSHR misses 795system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16954 # number of LoadLockedReq MSHR misses 796system.cpu.dcache.LoadLockedReq_mshr_misses::total 16954 # number of LoadLockedReq MSHR misses 797system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 98 # number of StoreCondReq MSHR misses 798system.cpu.dcache.StoreCondReq_mshr_misses::total 98 # number of StoreCondReq MSHR misses 799system.cpu.dcache.demand_mshr_misses::cpu.data 1389652 # number of demand (read+write) MSHR misses 800system.cpu.dcache.demand_mshr_misses::total 1389652 # number of demand (read+write) MSHR misses 801system.cpu.dcache.overall_mshr_misses::cpu.data 1389652 # number of overall MSHR misses 802system.cpu.dcache.overall_mshr_misses::total 1389652 # number of overall MSHR misses | 775system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.302076 # average number of cycles each access was blocked 776system.cpu.dcache.avg_blocked_cycles::no_targets 97.321429 # average number of cycles each access was blocked 777system.cpu.dcache.writebacks::writebacks 844182 # number of writebacks 778system.cpu.dcache.writebacks::total 844182 # number of writebacks 779system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717105 # number of ReadReq MSHR hits 780system.cpu.dcache.ReadReq_mshr_hits::total 717105 # number of ReadReq MSHR hits 781system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677249 # number of WriteReq MSHR hits 782system.cpu.dcache.WriteReq_mshr_hits::total 1677249 # number of WriteReq MSHR hits 783system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6763 # number of LoadLockedReq MSHR hits 784system.cpu.dcache.LoadLockedReq_mshr_hits::total 6763 # number of LoadLockedReq MSHR hits 785system.cpu.dcache.demand_mshr_hits::cpu.data 2394354 # number of demand (read+write) MSHR hits 786system.cpu.dcache.demand_mshr_hits::total 2394354 # number of demand (read+write) MSHR hits 787system.cpu.dcache.overall_mshr_hits::cpu.data 2394354 # number of overall MSHR hits 788system.cpu.dcache.overall_mshr_hits::total 2394354 # number of overall MSHR hits 789system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100222 # number of ReadReq MSHR misses 790system.cpu.dcache.ReadReq_mshr_misses::total 1100222 # number of ReadReq MSHR misses 791system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289457 # number of WriteReq MSHR misses 792system.cpu.dcache.WriteReq_mshr_misses::total 289457 # number of WriteReq MSHR misses 793system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16807 # number of LoadLockedReq MSHR misses 794system.cpu.dcache.LoadLockedReq_mshr_misses::total 16807 # number of LoadLockedReq MSHR misses 795system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 93 # number of StoreCondReq MSHR misses 796system.cpu.dcache.StoreCondReq_mshr_misses::total 93 # number of StoreCondReq MSHR misses 797system.cpu.dcache.demand_mshr_misses::cpu.data 1389679 # number of demand (read+write) MSHR misses 798system.cpu.dcache.demand_mshr_misses::total 1389679 # number of demand (read+write) MSHR misses 799system.cpu.dcache.overall_mshr_misses::cpu.data 1389679 # number of overall MSHR misses 800system.cpu.dcache.overall_mshr_misses::total 1389679 # number of overall MSHR misses |
| 803system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 804system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 805system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 806system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 807system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 808system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses | 801system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 802system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 803system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 804system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 805system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 806system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses |
| 809system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33017901000 # number of ReadReq MSHR miss cycles 810system.cpu.dcache.ReadReq_mshr_miss_latency::total 33017901000 # number of ReadReq MSHR miss cycles 811system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14364764991 # number of WriteReq MSHR miss cycles 812system.cpu.dcache.WriteReq_mshr_miss_latency::total 14364764991 # number of WriteReq MSHR miss cycles 813system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212848500 # number of LoadLockedReq MSHR miss cycles 814system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212848500 # number of LoadLockedReq MSHR miss cycles 815system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1270500 # number of StoreCondReq MSHR miss cycles 816system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1270500 # number of StoreCondReq MSHR miss cycles 817system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47382665991 # number of demand (read+write) MSHR miss cycles 818system.cpu.dcache.demand_mshr_miss_latency::total 47382665991 # number of demand (read+write) MSHR miss cycles 819system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47382665991 # number of overall MSHR miss cycles 820system.cpu.dcache.overall_mshr_miss_latency::total 47382665991 # number of overall MSHR miss cycles 821system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535128000 # number of ReadReq MSHR uncacheable cycles 822system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535128000 # number of ReadReq MSHR uncacheable cycles 823system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535128000 # number of overall MSHR uncacheable cycles 824system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535128000 # number of overall MSHR uncacheable cycles 825system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111854 # mshr miss rate for ReadReq accesses 826system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111854 # mshr miss rate for ReadReq accesses 827system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for WriteReq accesses 828system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047101 # mshr miss rate for WriteReq accesses 829system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071935 # mshr miss rate for LoadLockedReq accesses 830system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071935 # mshr miss rate for LoadLockedReq accesses 831system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000454 # mshr miss rate for StoreCondReq accesses 832system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000454 # mshr miss rate for StoreCondReq accesses 833system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for demand accesses 834system.cpu.dcache.demand_mshr_miss_rate::total 0.086950 # mshr miss rate for demand accesses 835system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for overall accesses 836system.cpu.dcache.overall_mshr_miss_rate::total 0.086950 # mshr miss rate for overall accesses 837system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30012.535711 # average ReadReq mshr miss latency 838system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30012.535711 # average ReadReq mshr miss latency 839system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49616.651956 # average WriteReq mshr miss latency 840system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49616.651956 # average WriteReq mshr miss latency 841system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12554.470921 # average LoadLockedReq mshr miss latency 842system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12554.470921 # average LoadLockedReq mshr miss latency 843system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12964.285714 # average StoreCondReq mshr miss latency 844system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12964.285714 # average StoreCondReq mshr miss latency 845system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency 846system.cpu.dcache.demand_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency 847system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency 848system.cpu.dcache.overall_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency 849system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221519.191919 # average ReadReq mshr uncacheable latency 850system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221519.191919 # average ReadReq mshr uncacheable latency 851system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92874.826063 # average overall mshr uncacheable latency 852system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92874.826063 # average overall mshr uncacheable latency 853system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 854system.cpu.icache.tags.replacements 1076759 # number of replacements 855system.cpu.icache.tags.tagsinuse 509.003606 # Cycle average of tags in use 856system.cpu.icache.tags.total_refs 8782144 # Total number of references to valid blocks. 857system.cpu.icache.tags.sampled_refs 1077267 # Sample count of references to valid blocks. 858system.cpu.icache.tags.avg_refs 8.152245 # Average number of references to valid blocks. 859system.cpu.icache.tags.warmup_cycle 30283847500 # Cycle when the warmup percentage was hit. 860system.cpu.icache.tags.occ_blocks::cpu.inst 509.003606 # Average occupied blocks per requestor 861system.cpu.icache.tags.occ_percent::cpu.inst 0.994148 # Average percentage of cache occupancy 862system.cpu.icache.tags.occ_percent::total 0.994148 # Average percentage of cache occupancy | 807system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33013560500 # number of ReadReq MSHR miss cycles 808system.cpu.dcache.ReadReq_mshr_miss_latency::total 33013560500 # number of ReadReq MSHR miss cycles 809system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14384695133 # number of WriteReq MSHR miss cycles 810system.cpu.dcache.WriteReq_mshr_miss_latency::total 14384695133 # number of WriteReq MSHR miss cycles 811system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 210983000 # number of LoadLockedReq MSHR miss cycles 812system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 210983000 # number of LoadLockedReq MSHR miss cycles 813system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1206500 # number of StoreCondReq MSHR miss cycles 814system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1206500 # number of StoreCondReq MSHR miss cycles 815system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47398255633 # number of demand (read+write) MSHR miss cycles 816system.cpu.dcache.demand_mshr_miss_latency::total 47398255633 # number of demand (read+write) MSHR miss cycles 817system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47398255633 # number of overall MSHR miss cycles 818system.cpu.dcache.overall_mshr_miss_latency::total 47398255633 # number of overall MSHR miss cycles 819system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535352000 # number of ReadReq MSHR uncacheable cycles 820system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535352000 # number of ReadReq MSHR uncacheable cycles 821system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535352000 # number of overall MSHR uncacheable cycles 822system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535352000 # number of overall MSHR uncacheable cycles 823system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111841 # mshr miss rate for ReadReq accesses 824system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111841 # mshr miss rate for ReadReq accesses 825system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047086 # mshr miss rate for WriteReq accesses 826system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047086 # mshr miss rate for WriteReq accesses 827system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071226 # mshr miss rate for LoadLockedReq accesses 828system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071226 # mshr miss rate for LoadLockedReq accesses 829system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000431 # mshr miss rate for StoreCondReq accesses 830system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000431 # mshr miss rate for StoreCondReq accesses 831system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for demand accesses 832system.cpu.dcache.demand_mshr_miss_rate::total 0.086937 # mshr miss rate for demand accesses 833system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for overall accesses 834system.cpu.dcache.overall_mshr_miss_rate::total 0.086937 # mshr miss rate for overall accesses 835system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30006.271916 # average ReadReq mshr miss latency 836system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30006.271916 # average ReadReq mshr miss latency 837system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49695.447452 # average WriteReq mshr miss latency 838system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49695.447452 # average WriteReq mshr miss latency 839system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12553.281371 # average LoadLockedReq mshr miss latency 840system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12553.281371 # average LoadLockedReq mshr miss latency 841system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12973.118280 # average StoreCondReq mshr miss latency 842system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12973.118280 # average StoreCondReq mshr miss latency 843system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency 844system.cpu.dcache.demand_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency 845system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency 846system.cpu.dcache.overall_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency 847system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221551.515152 # average ReadReq mshr uncacheable latency 848system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221551.515152 # average ReadReq mshr uncacheable latency 849system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92888.378002 # average overall mshr uncacheable latency 850system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92888.378002 # average overall mshr uncacheable latency 851system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 852system.cpu.icache.tags.replacements 1077480 # number of replacements 853system.cpu.icache.tags.tagsinuse 509.004193 # Cycle average of tags in use 854system.cpu.icache.tags.total_refs 8783075 # Total number of references to valid blocks. 855system.cpu.icache.tags.sampled_refs 1077988 # Sample count of references to valid blocks. 856system.cpu.icache.tags.avg_refs 8.147656 # Average number of references to valid blocks. 857system.cpu.icache.tags.warmup_cycle 30284131500 # Cycle when the warmup percentage was hit. 858system.cpu.icache.tags.occ_blocks::cpu.inst 509.004193 # Average occupied blocks per requestor 859system.cpu.icache.tags.occ_percent::cpu.inst 0.994149 # Average percentage of cache occupancy 860system.cpu.icache.tags.occ_percent::total 0.994149 # Average percentage of cache occupancy |
| 863system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id | 861system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id |
| 864system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 865system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id | 862system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 863system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id |
| 866system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id 867system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id | 864system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id 865system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id |
| 868system.cpu.icache.tags.tag_accesses 11005677 # Number of tag accesses 869system.cpu.icache.tags.data_accesses 11005677 # Number of data accesses 870system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 871system.cpu.icache.ReadReq_hits::cpu.inst 8782144 # number of ReadReq hits 872system.cpu.icache.ReadReq_hits::total 8782144 # number of ReadReq hits 873system.cpu.icache.demand_hits::cpu.inst 8782144 # number of demand (read+write) hits 874system.cpu.icache.demand_hits::total 8782144 # number of demand (read+write) hits 875system.cpu.icache.overall_hits::cpu.inst 8782144 # number of overall hits 876system.cpu.icache.overall_hits::total 8782144 # number of overall hits 877system.cpu.icache.ReadReq_misses::cpu.inst 1145952 # number of ReadReq misses 878system.cpu.icache.ReadReq_misses::total 1145952 # number of ReadReq misses 879system.cpu.icache.demand_misses::cpu.inst 1145952 # number of demand (read+write) misses 880system.cpu.icache.demand_misses::total 1145952 # number of demand (read+write) misses 881system.cpu.icache.overall_misses::cpu.inst 1145952 # number of overall misses 882system.cpu.icache.overall_misses::total 1145952 # number of overall misses 883system.cpu.icache.ReadReq_miss_latency::cpu.inst 16332614990 # number of ReadReq miss cycles 884system.cpu.icache.ReadReq_miss_latency::total 16332614990 # number of ReadReq miss cycles 885system.cpu.icache.demand_miss_latency::cpu.inst 16332614990 # number of demand (read+write) miss cycles 886system.cpu.icache.demand_miss_latency::total 16332614990 # number of demand (read+write) miss cycles 887system.cpu.icache.overall_miss_latency::cpu.inst 16332614990 # number of overall miss cycles 888system.cpu.icache.overall_miss_latency::total 16332614990 # number of overall miss cycles 889system.cpu.icache.ReadReq_accesses::cpu.inst 9928096 # number of ReadReq accesses(hits+misses) 890system.cpu.icache.ReadReq_accesses::total 9928096 # number of ReadReq accesses(hits+misses) 891system.cpu.icache.demand_accesses::cpu.inst 9928096 # number of demand (read+write) accesses 892system.cpu.icache.demand_accesses::total 9928096 # number of demand (read+write) accesses 893system.cpu.icache.overall_accesses::cpu.inst 9928096 # number of overall (read+write) accesses 894system.cpu.icache.overall_accesses::total 9928096 # number of overall (read+write) accesses 895system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115425 # miss rate for ReadReq accesses 896system.cpu.icache.ReadReq_miss_rate::total 0.115425 # miss rate for ReadReq accesses 897system.cpu.icache.demand_miss_rate::cpu.inst 0.115425 # miss rate for demand accesses 898system.cpu.icache.demand_miss_rate::total 0.115425 # miss rate for demand accesses 899system.cpu.icache.overall_miss_rate::cpu.inst 0.115425 # miss rate for overall accesses 900system.cpu.icache.overall_miss_rate::total 0.115425 # miss rate for overall accesses 901system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14252.442502 # average ReadReq miss latency 902system.cpu.icache.ReadReq_avg_miss_latency::total 14252.442502 # average ReadReq miss latency 903system.cpu.icache.demand_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency 904system.cpu.icache.demand_avg_miss_latency::total 14252.442502 # average overall miss latency 905system.cpu.icache.overall_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency 906system.cpu.icache.overall_avg_miss_latency::total 14252.442502 # average overall miss latency 907system.cpu.icache.blocked_cycles::no_mshrs 8348 # number of cycles access was blocked | 866system.cpu.icache.tags.tag_accesses 11008225 # Number of tag accesses 867system.cpu.icache.tags.data_accesses 11008225 # Number of data accesses 868system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 869system.cpu.icache.ReadReq_hits::cpu.inst 8783075 # number of ReadReq hits 870system.cpu.icache.ReadReq_hits::total 8783075 # number of ReadReq hits 871system.cpu.icache.demand_hits::cpu.inst 8783075 # number of demand (read+write) hits 872system.cpu.icache.demand_hits::total 8783075 # number of demand (read+write) hits 873system.cpu.icache.overall_hits::cpu.inst 8783075 # number of overall hits 874system.cpu.icache.overall_hits::total 8783075 # number of overall hits 875system.cpu.icache.ReadReq_misses::cpu.inst 1146854 # number of ReadReq misses 876system.cpu.icache.ReadReq_misses::total 1146854 # number of ReadReq misses 877system.cpu.icache.demand_misses::cpu.inst 1146854 # number of demand (read+write) misses 878system.cpu.icache.demand_misses::total 1146854 # number of demand (read+write) misses 879system.cpu.icache.overall_misses::cpu.inst 1146854 # number of overall misses 880system.cpu.icache.overall_misses::total 1146854 # number of overall misses 881system.cpu.icache.ReadReq_miss_latency::cpu.inst 16347552990 # number of ReadReq miss cycles 882system.cpu.icache.ReadReq_miss_latency::total 16347552990 # number of ReadReq miss cycles 883system.cpu.icache.demand_miss_latency::cpu.inst 16347552990 # number of demand (read+write) miss cycles 884system.cpu.icache.demand_miss_latency::total 16347552990 # number of demand (read+write) miss cycles 885system.cpu.icache.overall_miss_latency::cpu.inst 16347552990 # number of overall miss cycles 886system.cpu.icache.overall_miss_latency::total 16347552990 # number of overall miss cycles 887system.cpu.icache.ReadReq_accesses::cpu.inst 9929929 # number of ReadReq accesses(hits+misses) 888system.cpu.icache.ReadReq_accesses::total 9929929 # number of ReadReq accesses(hits+misses) 889system.cpu.icache.demand_accesses::cpu.inst 9929929 # number of demand (read+write) accesses 890system.cpu.icache.demand_accesses::total 9929929 # number of demand (read+write) accesses 891system.cpu.icache.overall_accesses::cpu.inst 9929929 # number of overall (read+write) accesses 892system.cpu.icache.overall_accesses::total 9929929 # number of overall (read+write) accesses 893system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115495 # miss rate for ReadReq accesses 894system.cpu.icache.ReadReq_miss_rate::total 0.115495 # miss rate for ReadReq accesses 895system.cpu.icache.demand_miss_rate::cpu.inst 0.115495 # miss rate for demand accesses 896system.cpu.icache.demand_miss_rate::total 0.115495 # miss rate for demand accesses 897system.cpu.icache.overall_miss_rate::cpu.inst 0.115495 # miss rate for overall accesses 898system.cpu.icache.overall_miss_rate::total 0.115495 # miss rate for overall accesses 899system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14254.258162 # average ReadReq miss latency 900system.cpu.icache.ReadReq_avg_miss_latency::total 14254.258162 # average ReadReq miss latency 901system.cpu.icache.demand_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency 902system.cpu.icache.demand_avg_miss_latency::total 14254.258162 # average overall miss latency 903system.cpu.icache.overall_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency 904system.cpu.icache.overall_avg_miss_latency::total 14254.258162 # average overall miss latency 905system.cpu.icache.blocked_cycles::no_mshrs 8615 # number of cycles access was blocked |
| 908system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 906system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 909system.cpu.icache.blocked::no_mshrs 326 # number of cycles access was blocked | 907system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked |
| 910system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 908system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 911system.cpu.icache.avg_blocked_cycles::no_mshrs 25.607362 # average number of cycles each access was blocked | 909system.cpu.icache.avg_blocked_cycles::no_mshrs 25.716418 # average number of cycles each access was blocked |
| 912system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 910system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 913system.cpu.icache.writebacks::writebacks 1076759 # number of writebacks 914system.cpu.icache.writebacks::total 1076759 # number of writebacks 915system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68371 # number of ReadReq MSHR hits 916system.cpu.icache.ReadReq_mshr_hits::total 68371 # number of ReadReq MSHR hits 917system.cpu.icache.demand_mshr_hits::cpu.inst 68371 # number of demand (read+write) MSHR hits 918system.cpu.icache.demand_mshr_hits::total 68371 # number of demand (read+write) MSHR hits 919system.cpu.icache.overall_mshr_hits::cpu.inst 68371 # number of overall MSHR hits 920system.cpu.icache.overall_mshr_hits::total 68371 # number of overall MSHR hits 921system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077581 # number of ReadReq MSHR misses 922system.cpu.icache.ReadReq_mshr_misses::total 1077581 # number of ReadReq MSHR misses 923system.cpu.icache.demand_mshr_misses::cpu.inst 1077581 # number of demand (read+write) MSHR misses 924system.cpu.icache.demand_mshr_misses::total 1077581 # number of demand (read+write) MSHR misses 925system.cpu.icache.overall_mshr_misses::cpu.inst 1077581 # number of overall MSHR misses 926system.cpu.icache.overall_mshr_misses::total 1077581 # number of overall MSHR misses 927system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14423902993 # number of ReadReq MSHR miss cycles 928system.cpu.icache.ReadReq_mshr_miss_latency::total 14423902993 # number of ReadReq MSHR miss cycles 929system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14423902993 # number of demand (read+write) MSHR miss cycles 930system.cpu.icache.demand_mshr_miss_latency::total 14423902993 # number of demand (read+write) MSHR miss cycles 931system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14423902993 # number of overall MSHR miss cycles 932system.cpu.icache.overall_mshr_miss_latency::total 14423902993 # number of overall MSHR miss cycles 933system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for ReadReq accesses 934system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108539 # mshr miss rate for ReadReq accesses 935system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for demand accesses 936system.cpu.icache.demand_mshr_miss_rate::total 0.108539 # mshr miss rate for demand accesses 937system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for overall accesses 938system.cpu.icache.overall_mshr_miss_rate::total 0.108539 # mshr miss rate for overall accesses 939system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13385.446656 # average ReadReq mshr miss latency 940system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13385.446656 # average ReadReq mshr miss latency 941system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency 942system.cpu.icache.demand_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency 943system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency 944system.cpu.icache.overall_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency 945system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states | 911system.cpu.icache.writebacks::writebacks 1077480 # number of writebacks 912system.cpu.icache.writebacks::total 1077480 # number of writebacks 913system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68558 # number of ReadReq MSHR hits 914system.cpu.icache.ReadReq_mshr_hits::total 68558 # number of ReadReq MSHR hits 915system.cpu.icache.demand_mshr_hits::cpu.inst 68558 # number of demand (read+write) MSHR hits 916system.cpu.icache.demand_mshr_hits::total 68558 # number of demand (read+write) MSHR hits 917system.cpu.icache.overall_mshr_hits::cpu.inst 68558 # number of overall MSHR hits 918system.cpu.icache.overall_mshr_hits::total 68558 # number of overall MSHR hits 919system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078296 # number of ReadReq MSHR misses 920system.cpu.icache.ReadReq_mshr_misses::total 1078296 # number of ReadReq MSHR misses 921system.cpu.icache.demand_mshr_misses::cpu.inst 1078296 # number of demand (read+write) MSHR misses 922system.cpu.icache.demand_mshr_misses::total 1078296 # number of demand (read+write) MSHR misses 923system.cpu.icache.overall_mshr_misses::cpu.inst 1078296 # number of overall MSHR misses 924system.cpu.icache.overall_mshr_misses::total 1078296 # number of overall MSHR misses 925system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14436755994 # number of ReadReq MSHR miss cycles 926system.cpu.icache.ReadReq_mshr_miss_latency::total 14436755994 # number of ReadReq MSHR miss cycles 927system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14436755994 # number of demand (read+write) MSHR miss cycles 928system.cpu.icache.demand_mshr_miss_latency::total 14436755994 # number of demand (read+write) MSHR miss cycles 929system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14436755994 # number of overall MSHR miss cycles 930system.cpu.icache.overall_mshr_miss_latency::total 14436755994 # number of overall MSHR miss cycles 931system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for ReadReq accesses 932system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108591 # mshr miss rate for ReadReq accesses 933system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for demand accesses 934system.cpu.icache.demand_mshr_miss_rate::total 0.108591 # mshr miss rate for demand accesses 935system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for overall accesses 936system.cpu.icache.overall_mshr_miss_rate::total 0.108591 # mshr miss rate for overall accesses 937system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13388.490724 # average ReadReq mshr miss latency 938system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13388.490724 # average ReadReq mshr miss latency 939system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency 940system.cpu.icache.demand_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency 941system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency 942system.cpu.icache.overall_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency 943system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states |
| 946system.cpu.l2cache.tags.replacements 338614 # number of replacements | 944system.cpu.l2cache.tags.replacements 338614 # number of replacements |
| 947system.cpu.l2cache.tags.tagsinuse 65420.353665 # Cycle average of tags in use 948system.cpu.l2cache.tags.total_refs 4559964 # Total number of references to valid blocks. | 945system.cpu.l2cache.tags.tagsinuse 65420.361718 # Cycle average of tags in use 946system.cpu.l2cache.tags.total_refs 4561143 # Total number of references to valid blocks. |
| 949system.cpu.l2cache.tags.sampled_refs 404136 # Sample count of references to valid blocks. | 947system.cpu.l2cache.tags.sampled_refs 404136 # Sample count of references to valid blocks. |
| 950system.cpu.l2cache.tags.avg_refs 11.283241 # Average number of references to valid blocks. 951system.cpu.l2cache.tags.warmup_cycle 6414398000 # Cycle when the warmup percentage was hit. 952system.cpu.l2cache.tags.occ_blocks::writebacks 255.266765 # Average occupied blocks per requestor 953system.cpu.l2cache.tags.occ_blocks::cpu.inst 5296.205124 # Average occupied blocks per requestor 954system.cpu.l2cache.tags.occ_blocks::cpu.data 59868.881776 # Average occupied blocks per requestor | 948system.cpu.l2cache.tags.avg_refs 11.286159 # Average number of references to valid blocks. 949system.cpu.l2cache.tags.warmup_cycle 6414386000 # Cycle when the warmup percentage was hit. 950system.cpu.l2cache.tags.occ_blocks::writebacks 255.267028 # Average occupied blocks per requestor 951system.cpu.l2cache.tags.occ_blocks::cpu.inst 5315.608032 # Average occupied blocks per requestor 952system.cpu.l2cache.tags.occ_blocks::cpu.data 59849.486658 # Average occupied blocks per requestor |
| 955system.cpu.l2cache.tags.occ_percent::writebacks 0.003895 # Average percentage of cache occupancy | 953system.cpu.l2cache.tags.occ_percent::writebacks 0.003895 # Average percentage of cache occupancy |
| 956system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080814 # Average percentage of cache occupancy 957system.cpu.l2cache.tags.occ_percent::cpu.data 0.913527 # Average percentage of cache occupancy | 954system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081110 # Average percentage of cache occupancy 955system.cpu.l2cache.tags.occ_percent::cpu.data 0.913231 # Average percentage of cache occupancy |
| 958system.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy 959system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 960system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 961system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id | 956system.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy 957system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 958system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 959system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id |
| 962system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 963system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5602 # Occupied blocks per task id 964system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58570 # Occupied blocks per task id | 960system.cpu.l2cache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id 961system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5595 # Occupied blocks per task id 962system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58579 # Occupied blocks per task id |
| 965system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id | 963system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id |
| 966system.cpu.l2cache.tags.tag_accesses 40121077 # Number of tag accesses 967system.cpu.l2cache.tags.data_accesses 40121077 # Number of data accesses 968system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 969system.cpu.l2cache.WritebackDirty_hits::writebacks 844399 # number of WritebackDirty hits 970system.cpu.l2cache.WritebackDirty_hits::total 844399 # number of WritebackDirty hits 971system.cpu.l2cache.WritebackClean_hits::writebacks 1076079 # number of WritebackClean hits 972system.cpu.l2cache.WritebackClean_hits::total 1076079 # number of WritebackClean hits 973system.cpu.l2cache.UpgradeReq_hits::cpu.data 69 # number of UpgradeReq hits 974system.cpu.l2cache.UpgradeReq_hits::total 69 # number of UpgradeReq hits 975system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 98 # number of SCUpgradeReq hits 976system.cpu.l2cache.SCUpgradeReq_hits::total 98 # number of SCUpgradeReq hits 977system.cpu.l2cache.ReadExReq_hits::cpu.data 185276 # number of ReadExReq hits 978system.cpu.l2cache.ReadExReq_hits::total 185276 # number of ReadExReq hits 979system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062141 # number of ReadCleanReq hits 980system.cpu.l2cache.ReadCleanReq_hits::total 1062141 # number of ReadCleanReq hits 981system.cpu.l2cache.ReadSharedReq_hits::cpu.data 832063 # number of ReadSharedReq hits 982system.cpu.l2cache.ReadSharedReq_hits::total 832063 # number of ReadSharedReq hits 983system.cpu.l2cache.demand_hits::cpu.inst 1062141 # number of demand (read+write) hits 984system.cpu.l2cache.demand_hits::cpu.data 1017339 # number of demand (read+write) hits 985system.cpu.l2cache.demand_hits::total 2079480 # number of demand (read+write) hits 986system.cpu.l2cache.overall_hits::cpu.inst 1062141 # number of overall hits 987system.cpu.l2cache.overall_hits::cpu.data 1017339 # number of overall hits 988system.cpu.l2cache.overall_hits::total 2079480 # number of overall hits 989system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses 990system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses 991system.cpu.l2cache.ReadExReq_misses::cpu.data 114725 # number of ReadExReq misses 992system.cpu.l2cache.ReadExReq_misses::total 114725 # number of ReadExReq misses 993system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15044 # number of ReadCleanReq misses 994system.cpu.l2cache.ReadCleanReq_misses::total 15044 # number of ReadCleanReq misses 995system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274467 # number of ReadSharedReq misses 996system.cpu.l2cache.ReadSharedReq_misses::total 274467 # number of ReadSharedReq misses 997system.cpu.l2cache.demand_misses::cpu.inst 15044 # number of demand (read+write) misses 998system.cpu.l2cache.demand_misses::cpu.data 389192 # number of demand (read+write) misses 999system.cpu.l2cache.demand_misses::total 404236 # number of demand (read+write) misses 1000system.cpu.l2cache.overall_misses::cpu.inst 15044 # number of overall misses 1001system.cpu.l2cache.overall_misses::cpu.data 389192 # number of overall misses 1002system.cpu.l2cache.overall_misses::total 404236 # number of overall misses 1003system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 418500 # number of UpgradeReq miss cycles 1004system.cpu.l2cache.UpgradeReq_miss_latency::total 418500 # number of UpgradeReq miss cycles 1005system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12044968500 # number of ReadExReq miss cycles 1006system.cpu.l2cache.ReadExReq_miss_latency::total 12044968500 # number of ReadExReq miss cycles 1007system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1516847000 # number of ReadCleanReq miss cycles 1008system.cpu.l2cache.ReadCleanReq_miss_latency::total 1516847000 # number of ReadCleanReq miss cycles 1009system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22392456000 # number of ReadSharedReq miss cycles 1010system.cpu.l2cache.ReadSharedReq_miss_latency::total 22392456000 # number of ReadSharedReq miss cycles 1011system.cpu.l2cache.demand_miss_latency::cpu.inst 1516847000 # number of demand (read+write) miss cycles 1012system.cpu.l2cache.demand_miss_latency::cpu.data 34437424500 # number of demand (read+write) miss cycles 1013system.cpu.l2cache.demand_miss_latency::total 35954271500 # number of demand (read+write) miss cycles 1014system.cpu.l2cache.overall_miss_latency::cpu.inst 1516847000 # number of overall miss cycles 1015system.cpu.l2cache.overall_miss_latency::cpu.data 34437424500 # number of overall miss cycles 1016system.cpu.l2cache.overall_miss_latency::total 35954271500 # number of overall miss cycles 1017system.cpu.l2cache.WritebackDirty_accesses::writebacks 844399 # number of WritebackDirty accesses(hits+misses) 1018system.cpu.l2cache.WritebackDirty_accesses::total 844399 # number of WritebackDirty accesses(hits+misses) 1019system.cpu.l2cache.WritebackClean_accesses::writebacks 1076079 # number of WritebackClean accesses(hits+misses) 1020system.cpu.l2cache.WritebackClean_accesses::total 1076079 # number of WritebackClean accesses(hits+misses) 1021system.cpu.l2cache.UpgradeReq_accesses::cpu.data 78 # number of UpgradeReq accesses(hits+misses) 1022system.cpu.l2cache.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) 1023system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 98 # number of SCUpgradeReq accesses(hits+misses) 1024system.cpu.l2cache.SCUpgradeReq_accesses::total 98 # number of SCUpgradeReq accesses(hits+misses) 1025system.cpu.l2cache.ReadExReq_accesses::cpu.data 300001 # number of ReadExReq accesses(hits+misses) 1026system.cpu.l2cache.ReadExReq_accesses::total 300001 # number of ReadExReq accesses(hits+misses) 1027system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077185 # number of ReadCleanReq accesses(hits+misses) 1028system.cpu.l2cache.ReadCleanReq_accesses::total 1077185 # number of ReadCleanReq accesses(hits+misses) 1029system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106530 # number of ReadSharedReq accesses(hits+misses) 1030system.cpu.l2cache.ReadSharedReq_accesses::total 1106530 # number of ReadSharedReq accesses(hits+misses) 1031system.cpu.l2cache.demand_accesses::cpu.inst 1077185 # number of demand (read+write) accesses 1032system.cpu.l2cache.demand_accesses::cpu.data 1406531 # number of demand (read+write) accesses 1033system.cpu.l2cache.demand_accesses::total 2483716 # number of demand (read+write) accesses 1034system.cpu.l2cache.overall_accesses::cpu.inst 1077185 # number of overall (read+write) accesses 1035system.cpu.l2cache.overall_accesses::cpu.data 1406531 # number of overall (read+write) accesses 1036system.cpu.l2cache.overall_accesses::total 2483716 # number of overall (read+write) accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.115385 # miss rate for UpgradeReq accesses 1038system.cpu.l2cache.UpgradeReq_miss_rate::total 0.115385 # miss rate for UpgradeReq accesses 1039system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382415 # miss rate for ReadExReq accesses 1040system.cpu.l2cache.ReadExReq_miss_rate::total 0.382415 # miss rate for ReadExReq accesses 1041system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013966 # miss rate for ReadCleanReq accesses 1042system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013966 # miss rate for ReadCleanReq accesses 1043system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248043 # miss rate for ReadSharedReq accesses 1044system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248043 # miss rate for ReadSharedReq accesses 1045system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013966 # miss rate for demand accesses 1046system.cpu.l2cache.demand_miss_rate::cpu.data 0.276703 # miss rate for demand accesses 1047system.cpu.l2cache.demand_miss_rate::total 0.162755 # miss rate for demand accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013966 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.data 0.276703 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::total 0.162755 # miss rate for overall accesses 1051system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 46500 # average UpgradeReq miss latency 1052system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 46500 # average UpgradeReq miss latency 1053system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104989.919372 # average ReadExReq miss latency 1054system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104989.919372 # average ReadExReq miss latency 1055system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100827.373039 # average ReadCleanReq miss latency 1056system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100827.373039 # average ReadCleanReq miss latency 1057system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81585.239756 # average ReadSharedReq miss latency 1058system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81585.239756 # average ReadSharedReq miss latency 1059system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency 1060system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::total 88943.764286 # average overall miss latency 1062system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency 1063system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency 1064system.cpu.l2cache.overall_avg_miss_latency::total 88943.764286 # average overall miss latency | 964system.cpu.l2cache.tags.tag_accesses 40130556 # Number of tag accesses 965system.cpu.l2cache.tags.data_accesses 40130556 # Number of data accesses 966system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 967system.cpu.l2cache.WritebackDirty_hits::writebacks 844182 # number of WritebackDirty hits 968system.cpu.l2cache.WritebackDirty_hits::total 844182 # number of WritebackDirty hits 969system.cpu.l2cache.WritebackClean_hits::writebacks 1076791 # number of WritebackClean hits 970system.cpu.l2cache.WritebackClean_hits::total 1076791 # number of WritebackClean hits 971system.cpu.l2cache.UpgradeReq_hits::cpu.data 68 # number of UpgradeReq hits 972system.cpu.l2cache.UpgradeReq_hits::total 68 # number of UpgradeReq hits 973system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 93 # number of SCUpgradeReq hits 974system.cpu.l2cache.SCUpgradeReq_hits::total 93 # number of SCUpgradeReq hits 975system.cpu.l2cache.ReadExReq_hits::cpu.data 185239 # number of ReadExReq hits 976system.cpu.l2cache.ReadExReq_hits::total 185239 # number of ReadExReq hits 977system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062874 # number of ReadCleanReq hits 978system.cpu.l2cache.ReadCleanReq_hits::total 1062874 # number of ReadCleanReq hits 979system.cpu.l2cache.ReadSharedReq_hits::cpu.data 831967 # number of ReadSharedReq hits 980system.cpu.l2cache.ReadSharedReq_hits::total 831967 # number of ReadSharedReq hits 981system.cpu.l2cache.demand_hits::cpu.inst 1062874 # number of demand (read+write) hits 982system.cpu.l2cache.demand_hits::cpu.data 1017206 # number of demand (read+write) hits 983system.cpu.l2cache.demand_hits::total 2080080 # number of demand (read+write) hits 984system.cpu.l2cache.overall_hits::cpu.inst 1062874 # number of overall hits 985system.cpu.l2cache.overall_hits::cpu.data 1017206 # number of overall hits 986system.cpu.l2cache.overall_hits::total 2080080 # number of overall hits 987system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses 988system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses 989system.cpu.l2cache.ReadExReq_misses::cpu.data 114698 # number of ReadExReq misses 990system.cpu.l2cache.ReadExReq_misses::total 114698 # number of ReadExReq misses 991system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15038 # number of ReadCleanReq misses 992system.cpu.l2cache.ReadCleanReq_misses::total 15038 # number of ReadCleanReq misses 993system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274508 # number of ReadSharedReq misses 994system.cpu.l2cache.ReadSharedReq_misses::total 274508 # number of ReadSharedReq misses 995system.cpu.l2cache.demand_misses::cpu.inst 15038 # number of demand (read+write) misses 996system.cpu.l2cache.demand_misses::cpu.data 389206 # number of demand (read+write) misses 997system.cpu.l2cache.demand_misses::total 404244 # number of demand (read+write) misses 998system.cpu.l2cache.overall_misses::cpu.inst 15038 # number of overall misses 999system.cpu.l2cache.overall_misses::cpu.data 389206 # number of overall misses 1000system.cpu.l2cache.overall_misses::total 404244 # number of overall misses 1001system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 357500 # number of UpgradeReq miss cycles 1002system.cpu.l2cache.UpgradeReq_miss_latency::total 357500 # number of UpgradeReq miss cycles 1003system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12064669000 # number of ReadExReq miss cycles 1004system.cpu.l2cache.ReadExReq_miss_latency::total 12064669000 # number of ReadExReq miss cycles 1005system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1519815000 # number of ReadCleanReq miss cycles 1006system.cpu.l2cache.ReadCleanReq_miss_latency::total 1519815000 # number of ReadCleanReq miss cycles 1007system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22385224000 # number of ReadSharedReq miss cycles 1008system.cpu.l2cache.ReadSharedReq_miss_latency::total 22385224000 # number of ReadSharedReq miss cycles 1009system.cpu.l2cache.demand_miss_latency::cpu.inst 1519815000 # number of demand (read+write) miss cycles 1010system.cpu.l2cache.demand_miss_latency::cpu.data 34449893000 # number of demand (read+write) miss cycles 1011system.cpu.l2cache.demand_miss_latency::total 35969708000 # number of demand (read+write) miss cycles 1012system.cpu.l2cache.overall_miss_latency::cpu.inst 1519815000 # number of overall miss cycles 1013system.cpu.l2cache.overall_miss_latency::cpu.data 34449893000 # number of overall miss cycles 1014system.cpu.l2cache.overall_miss_latency::total 35969708000 # number of overall miss cycles 1015system.cpu.l2cache.WritebackDirty_accesses::writebacks 844182 # number of WritebackDirty accesses(hits+misses) 1016system.cpu.l2cache.WritebackDirty_accesses::total 844182 # number of WritebackDirty accesses(hits+misses) 1017system.cpu.l2cache.WritebackClean_accesses::writebacks 1076791 # number of WritebackClean accesses(hits+misses) 1018system.cpu.l2cache.WritebackClean_accesses::total 1076791 # number of WritebackClean accesses(hits+misses) 1019system.cpu.l2cache.UpgradeReq_accesses::cpu.data 75 # number of UpgradeReq accesses(hits+misses) 1020system.cpu.l2cache.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses) 1021system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 93 # number of SCUpgradeReq accesses(hits+misses) 1022system.cpu.l2cache.SCUpgradeReq_accesses::total 93 # number of SCUpgradeReq accesses(hits+misses) 1023system.cpu.l2cache.ReadExReq_accesses::cpu.data 299937 # number of ReadExReq accesses(hits+misses) 1024system.cpu.l2cache.ReadExReq_accesses::total 299937 # number of ReadExReq accesses(hits+misses) 1025system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077912 # number of ReadCleanReq accesses(hits+misses) 1026system.cpu.l2cache.ReadCleanReq_accesses::total 1077912 # number of ReadCleanReq accesses(hits+misses) 1027system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106475 # number of ReadSharedReq accesses(hits+misses) 1028system.cpu.l2cache.ReadSharedReq_accesses::total 1106475 # number of ReadSharedReq accesses(hits+misses) 1029system.cpu.l2cache.demand_accesses::cpu.inst 1077912 # number of demand (read+write) accesses 1030system.cpu.l2cache.demand_accesses::cpu.data 1406412 # number of demand (read+write) accesses 1031system.cpu.l2cache.demand_accesses::total 2484324 # number of demand (read+write) accesses 1032system.cpu.l2cache.overall_accesses::cpu.inst 1077912 # number of overall (read+write) accesses 1033system.cpu.l2cache.overall_accesses::cpu.data 1406412 # number of overall (read+write) accesses 1034system.cpu.l2cache.overall_accesses::total 2484324 # number of overall (read+write) accesses 1035system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093333 # miss rate for UpgradeReq accesses 1036system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093333 # miss rate for UpgradeReq accesses 1037system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382407 # miss rate for ReadExReq accesses 1038system.cpu.l2cache.ReadExReq_miss_rate::total 0.382407 # miss rate for ReadExReq accesses 1039system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013951 # miss rate for ReadCleanReq accesses 1040system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013951 # miss rate for ReadCleanReq accesses 1041system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248092 # miss rate for ReadSharedReq accesses 1042system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248092 # miss rate for ReadSharedReq accesses 1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013951 # miss rate for demand accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.data 0.276737 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::total 0.162718 # miss rate for demand accesses 1046system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013951 # miss rate for overall accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.data 0.276737 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::total 0.162718 # miss rate for overall accesses 1049system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51071.428571 # average UpgradeReq miss latency 1050system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51071.428571 # average UpgradeReq miss latency 1051system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105186.393834 # average ReadExReq miss latency 1052system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105186.393834 # average ReadExReq miss latency 1053system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101064.968746 # average ReadCleanReq miss latency 1054system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101064.968746 # average ReadCleanReq miss latency 1055system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81546.709021 # average ReadSharedReq miss latency 1056system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81546.709021 # average ReadSharedReq miss latency 1057system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency 1058system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency 1059system.cpu.l2cache.demand_avg_miss_latency::total 88980.190182 # average overall miss latency 1060system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency 1061system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency 1062system.cpu.l2cache.overall_avg_miss_latency::total 88980.190182 # average overall miss latency |
| 1065system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1066system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1067system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1068system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1069system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1070system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1063system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1064system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1065system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1066system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1067system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1068system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1071system.cpu.l2cache.writebacks::writebacks 75900 # number of writebacks 1072system.cpu.l2cache.writebacks::total 75900 # number of writebacks | 1069system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks 1070system.cpu.l2cache.writebacks::total 75929 # number of writebacks |
| 1073system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1074system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1075system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1076system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1077system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1078system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 1071system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1072system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1073system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1074system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1075system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1076system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 1079system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses 1080system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses 1081system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114725 # number of ReadExReq MSHR misses 1082system.cpu.l2cache.ReadExReq_mshr_misses::total 114725 # number of ReadExReq MSHR misses 1083system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15043 # number of ReadCleanReq MSHR misses 1084system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15043 # number of ReadCleanReq MSHR misses 1085system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274467 # number of ReadSharedReq MSHR misses 1086system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274467 # number of ReadSharedReq MSHR misses 1087system.cpu.l2cache.demand_mshr_misses::cpu.inst 15043 # number of demand (read+write) MSHR misses 1088system.cpu.l2cache.demand_mshr_misses::cpu.data 389192 # number of demand (read+write) MSHR misses 1089system.cpu.l2cache.demand_mshr_misses::total 404235 # number of demand (read+write) MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::cpu.inst 15043 # number of overall MSHR misses 1091system.cpu.l2cache.overall_mshr_misses::cpu.data 389192 # number of overall MSHR misses 1092system.cpu.l2cache.overall_mshr_misses::total 404235 # number of overall MSHR misses | 1077system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses 1078system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses 1079system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114698 # number of ReadExReq MSHR misses 1080system.cpu.l2cache.ReadExReq_mshr_misses::total 114698 # number of ReadExReq MSHR misses 1081system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15037 # number of ReadCleanReq MSHR misses 1082system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15037 # number of ReadCleanReq MSHR misses 1083system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274508 # number of ReadSharedReq MSHR misses 1084system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses 1085system.cpu.l2cache.demand_mshr_misses::cpu.inst 15037 # number of demand (read+write) MSHR misses 1086system.cpu.l2cache.demand_mshr_misses::cpu.data 389206 # number of demand (read+write) MSHR misses 1087system.cpu.l2cache.demand_mshr_misses::total 404243 # number of demand (read+write) MSHR misses 1088system.cpu.l2cache.overall_mshr_misses::cpu.inst 15037 # number of overall MSHR misses 1089system.cpu.l2cache.overall_mshr_misses::cpu.data 389206 # number of overall MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::total 404243 # number of overall MSHR misses |
| 1093system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 1094system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 1095system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 1096system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 1097system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 1098system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses | 1091system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 1092system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 1093system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 1094system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 1095system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 1096system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses |
| 1099system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 328500 # number of UpgradeReq MSHR miss cycles 1100system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 328500 # number of UpgradeReq MSHR miss cycles 1101system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10897718500 # number of ReadExReq MSHR miss cycles 1102system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10897718500 # number of ReadExReq MSHR miss cycles 1103system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1366325500 # number of ReadCleanReq MSHR miss cycles 1104system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1366325500 # number of ReadCleanReq MSHR miss cycles 1105system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19653014500 # number of ReadSharedReq MSHR miss cycles 1106system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19653014500 # number of ReadSharedReq MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1366325500 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30550733000 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::total 31917058500 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1366325500 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30550733000 # number of overall MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::total 31917058500 # number of overall MSHR miss cycles 1113system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448486500 # number of ReadReq MSHR uncacheable cycles 1114system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448486500 # number of ReadReq MSHR uncacheable cycles 1115system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448486500 # number of overall MSHR uncacheable cycles 1116system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448486500 # number of overall MSHR uncacheable cycles 1117system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses 1118system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses 1119system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382415 # mshr miss rate for ReadExReq accesses 1120system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382415 # mshr miss rate for ReadExReq accesses 1121system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for ReadCleanReq accesses 1122system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013965 # mshr miss rate for ReadCleanReq accesses 1123system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248043 # mshr miss rate for ReadSharedReq accesses 1124system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248043 # mshr miss rate for ReadSharedReq accesses 1125system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for demand accesses 1126system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for demand accesses 1127system.cpu.l2cache.demand_mshr_miss_rate::total 0.162754 # mshr miss rate for demand accesses 1128system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for overall accesses 1129system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for overall accesses 1130system.cpu.l2cache.overall_mshr_miss_rate::total 0.162754 # mshr miss rate for overall accesses 1131system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 36500 # average UpgradeReq mshr miss latency 1132system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36500 # average UpgradeReq mshr miss latency 1133system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94989.919372 # average ReadExReq mshr miss latency 1134system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94989.919372 # average ReadExReq mshr miss latency 1135system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90827.993086 # average ReadCleanReq mshr miss latency 1136system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90827.993086 # average ReadCleanReq mshr miss latency 1137system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71604.289405 # average ReadSharedReq mshr miss latency 1138system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71604.289405 # average ReadSharedReq mshr miss latency 1139system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency 1140system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency 1141system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency 1143system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency 1145system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209016.810967 # average ReadReq mshr uncacheable latency 1146system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209016.810967 # average ReadReq mshr uncacheable latency 1147system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87633.038901 # average overall mshr uncacheable latency 1148system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87633.038901 # average overall mshr uncacheable latency 1149system.cpu.toL2Bus.snoop_filter.tot_requests 4967024 # Total number of requests made to the snoop filter. 1150system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483092 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1151system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2362 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1097system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 287500 # number of UpgradeReq MSHR miss cycles 1098system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 287500 # number of UpgradeReq MSHR miss cycles 1099system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10917688501 # number of ReadExReq MSHR miss cycles 1100system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10917688501 # number of ReadExReq MSHR miss cycles 1101system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1369353500 # number of ReadCleanReq MSHR miss cycles 1102system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1369353500 # number of ReadCleanReq MSHR miss cycles 1103system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19646288000 # number of ReadSharedReq MSHR miss cycles 1104system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19646288000 # number of ReadSharedReq MSHR miss cycles 1105system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1369353500 # number of demand (read+write) MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30563976501 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::total 31933330001 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1369353500 # number of overall MSHR miss cycles 1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30563976501 # number of overall MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::total 31933330001 # number of overall MSHR miss cycles 1111system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448711500 # number of ReadReq MSHR uncacheable cycles 1112system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448711500 # number of ReadReq MSHR uncacheable cycles 1113system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448711500 # number of overall MSHR uncacheable cycles 1114system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448711500 # number of overall MSHR uncacheable cycles 1115system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093333 # mshr miss rate for UpgradeReq accesses 1116system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093333 # mshr miss rate for UpgradeReq accesses 1117system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382407 # mshr miss rate for ReadExReq accesses 1118system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382407 # mshr miss rate for ReadExReq accesses 1119system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for ReadCleanReq accesses 1120system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013950 # mshr miss rate for ReadCleanReq accesses 1121system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248092 # mshr miss rate for ReadSharedReq accesses 1122system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248092 # mshr miss rate for ReadSharedReq accesses 1123system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for demand accesses 1124system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for demand accesses 1125system.cpu.l2cache.demand_mshr_miss_rate::total 0.162718 # mshr miss rate for demand accesses 1126system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for overall accesses 1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for overall accesses 1128system.cpu.l2cache.overall_mshr_miss_rate::total 0.162718 # mshr miss rate for overall accesses 1129system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41071.428571 # average UpgradeReq mshr miss latency 1130system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41071.428571 # average UpgradeReq mshr miss latency 1131system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95186.389484 # average ReadExReq mshr miss latency 1132system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95186.389484 # average ReadExReq mshr miss latency 1133system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91065.604841 # average ReadCleanReq mshr miss latency 1134system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91065.604841 # average ReadCleanReq mshr miss latency 1135system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71569.090883 # average ReadSharedReq mshr miss latency 1136system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71569.090883 # average ReadSharedReq mshr miss latency 1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency 1138system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency 1139system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency 1143system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209049.278499 # average ReadReq mshr uncacheable latency 1144system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209049.278499 # average ReadReq mshr uncacheable latency 1145system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87646.651340 # average overall mshr uncacheable latency 1146system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87646.651340 # average overall mshr uncacheable latency 1147system.cpu.toL2Bus.snoop_filter.tot_requests 4968207 # Total number of requests made to the snoop filter. 1148system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483449 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1149system.cpu.toL2Bus.snoop_filter.hit_multi_requests 5093 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1152system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter. 1153system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1154system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1150system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter. 1151system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1152system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1155system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states | 1153system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states |
| 1156system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution | 1154system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1157system.cpu.toL2Bus.trans_dist::ReadResp 2191157 # Transaction distribution | 1155system.cpu.toL2Bus.trans_dist::ReadResp 2191810 # Transaction distribution |
| 1158system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution | 1156system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution |
| 1160system.cpu.toL2Bus.trans_dist::WritebackDirty 920299 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::WritebackClean 1076759 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::CleanEvict 824292 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::UpgradeReq 78 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::SCUpgradeReq 98 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::ReadExReq 300001 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::ReadExResp 300001 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077581 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106690 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::BadAddressError 40 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution 1172system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3231525 # Packet count per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252605 # Packet count per connected master and slave (bytes) 1174system.cpu.toL2Bus.pkt_count::total 7484130 # Packet count per connected master and slave (bytes) 1175system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137852416 # Cumulative packet size per connected master and slave (bytes) 1176system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144111100 # Cumulative packet size per connected master and slave (bytes) 1177system.cpu.toL2Bus.pkt_size::total 281963516 # Cumulative packet size per connected master and slave (bytes) 1178system.cpu.toL2Bus.snoops 339563 # Total snoops (count) 1179system.cpu.toL2Bus.snoopTraffic 4892928 # Total snoop traffic (bytes) 1180system.cpu.toL2Bus.snoop_fanout::samples 2839828 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::mean 0.001278 # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::stdev 0.035720 # Request fanout histogram | 1158system.cpu.toL2Bus.trans_dist::WritebackDirty 920111 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::WritebackClean 1077480 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::CleanEvict 824354 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::UpgradeReq 75 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::UpgradeResp 168 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::ReadExReq 299937 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::ReadExResp 299937 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078296 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106636 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution 1171system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3233688 # Packet count per connected master and slave (bytes) 1172system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252227 # Packet count per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_count::total 7485915 # Packet count per connected master and slave (bytes) 1174system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137945088 # Cumulative packet size per connected master and slave (bytes) 1175system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144089148 # Cumulative packet size per connected master and slave (bytes) 1176system.cpu.toL2Bus.pkt_size::total 282034236 # Cumulative packet size per connected master and slave (bytes) 1177system.cpu.toL2Bus.snoops 339553 # Total snoops (count) 1178system.cpu.toL2Bus.snoopTraffic 4894016 # Total snoop traffic (bytes) 1179system.cpu.toL2Bus.snoop_fanout::samples 2840416 # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::mean 0.002130 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::stdev 0.046099 # Request fanout histogram |
| 1183system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1182system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1184system.cpu.toL2Bus.snoop_fanout::0 2836200 99.87% 99.87% # Request fanout histogram 1185system.cpu.toL2Bus.snoop_fanout::1 3628 0.13% 100.00% # Request fanout histogram | 1183system.cpu.toL2Bus.snoop_fanout::0 2834367 99.79% 99.79% # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::1 6049 0.21% 100.00% # Request fanout histogram |
| 1186system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1189system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1185system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1186system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1190system.cpu.toL2Bus.snoop_fanout::total 2839828 # Request fanout histogram 1191system.cpu.toL2Bus.reqLayer0.occupancy 4417734000 # Layer occupancy (ticks) | 1189system.cpu.toL2Bus.snoop_fanout::total 2840416 # Request fanout histogram 1190system.cpu.toL2Bus.reqLayer0.occupancy 4418829500 # Layer occupancy (ticks) |
| 1192system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 1191system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 1193system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) | 1192system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) |
| 1194system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1193system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1195system.cpu.toL2Bus.respLayer0.occupancy 1617399440 # Layer occupancy (ticks) | 1194system.cpu.toL2Bus.respLayer0.occupancy 1618554275 # Layer occupancy (ticks) |
| 1196system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1195system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1197system.cpu.toL2Bus.respLayer1.occupancy 2121770107 # Layer occupancy (ticks) | 1196system.cpu.toL2Bus.respLayer1.occupancy 2121571625 # Layer occupancy (ticks) |
| 1198system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1199system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1200system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1201system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1202system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1203system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1204system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1205system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1206system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1207system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1208system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1209system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1210system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 1197system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1198system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1199system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1200system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1201system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1202system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1203system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1204system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1205system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1206system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1207system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1208system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1209system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 1211system.iobus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states | 1210system.iobus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states |
| 1212system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1213system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 1214system.iobus.trans_dist::WriteReq 51151 # Transaction distribution 1215system.iobus.trans_dist::WriteResp 51151 # Transaction distribution 1216system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) 1217system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1218system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1219system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 1234system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1235system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1236system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1237system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1238system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) 1239system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1240system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 1241system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) | 1211system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1212system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 1213system.iobus.trans_dist::WriteReq 51151 # Transaction distribution 1214system.iobus.trans_dist::WriteResp 51151 # Transaction distribution 1215system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) 1216system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1217system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1218system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 1233system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1234system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1235system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1236system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1237system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) 1238system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1239system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 1240system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) |
| 1242system.iobus.reqLayer0.occupancy 5359000 # Layer occupancy (ticks) | 1241system.iobus.reqLayer0.occupancy 5364500 # Layer occupancy (ticks) |
| 1243system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1242system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1244system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) | 1243system.iobus.reqLayer1.occupancy 813500 # Layer occupancy (ticks) |
| 1245system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1246system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 1247system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1244system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 1246system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1248system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) | 1247system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) |
| 1249system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1250system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) 1251system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) | 1248system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1249system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) 1250system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) |
| 1252system.iobus.reqLayer23.occupancy 14034000 # Layer occupancy (ticks) | 1251system.iobus.reqLayer23.occupancy 14114000 # Layer occupancy (ticks) |
| 1253system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1254system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks) 1255system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1252system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1253system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks) 1254system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1256system.iobus.reqLayer25.occupancy 6056500 # Layer occupancy (ticks) | 1255system.iobus.reqLayer25.occupancy 6040500 # Layer occupancy (ticks) |
| 1257system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) | 1256system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) |
| 1258system.iobus.reqLayer26.occupancy 92500 # Layer occupancy (ticks) | 1257system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) |
| 1259system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1258system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1260system.iobus.reqLayer27.occupancy 216222032 # Layer occupancy (ticks) | 1259system.iobus.reqLayer27.occupancy 216207792 # Layer occupancy (ticks) |
| 1261system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1262system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) 1263system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1264system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1265system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1260system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1261system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) 1262system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1263system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1264system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1266system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states | 1265system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states |
| 1267system.iocache.tags.replacements 41685 # number of replacements | 1266system.iocache.tags.replacements 41685 # number of replacements |
| 1268system.iocache.tags.tagsinuse 1.265413 # Cycle average of tags in use | 1267system.iocache.tags.tagsinuse 1.265392 # Cycle average of tags in use |
| 1269system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1270system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1271system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1268system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1269system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1270system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1272system.iocache.tags.warmup_cycle 1714256790000 # Cycle when the warmup percentage was hit. 1273system.iocache.tags.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor 1274system.iocache.tags.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy 1275system.iocache.tags.occ_percent::total 0.079088 # Average percentage of cache occupancy | 1271system.iocache.tags.warmup_cycle 1714257470000 # Cycle when the warmup percentage was hit. 1272system.iocache.tags.occ_blocks::tsunami.ide 1.265392 # Average occupied blocks per requestor 1273system.iocache.tags.occ_percent::tsunami.ide 0.079087 # Average percentage of cache occupancy 1274system.iocache.tags.occ_percent::total 0.079087 # Average percentage of cache occupancy |
| 1276system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1277system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1278system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1279system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1280system.iocache.tags.data_accesses 375525 # Number of data accesses | 1275system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1276system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1277system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1278system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1279system.iocache.tags.data_accesses 375525 # Number of data accesses |
| 1281system.iocache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states | 1280system.iocache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states |
| 1282system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1283system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1284system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1285system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1286system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1287system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1288system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1289system.iocache.overall_misses::total 41725 # number of overall misses | 1281system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1282system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1283system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1284system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1285system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1286system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1287system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1288system.iocache.overall_misses::total 41725 # number of overall misses |
| 1290system.iocache.ReadReq_miss_latency::tsunami.ide 21932883 # number of ReadReq miss cycles 1291system.iocache.ReadReq_miss_latency::total 21932883 # number of ReadReq miss cycles 1292system.iocache.WriteLineReq_miss_latency::tsunami.ide 4939835149 # number of WriteLineReq miss cycles 1293system.iocache.WriteLineReq_miss_latency::total 4939835149 # number of WriteLineReq miss cycles 1294system.iocache.demand_miss_latency::tsunami.ide 4961768032 # number of demand (read+write) miss cycles 1295system.iocache.demand_miss_latency::total 4961768032 # number of demand (read+write) miss cycles 1296system.iocache.overall_miss_latency::tsunami.ide 4961768032 # number of overall miss cycles 1297system.iocache.overall_miss_latency::total 4961768032 # number of overall miss cycles | 1289system.iocache.ReadReq_miss_latency::tsunami.ide 21940383 # number of ReadReq miss cycles 1290system.iocache.ReadReq_miss_latency::total 21940383 # number of ReadReq miss cycles 1291system.iocache.WriteLineReq_miss_latency::tsunami.ide 4930799409 # number of WriteLineReq miss cycles 1292system.iocache.WriteLineReq_miss_latency::total 4930799409 # number of WriteLineReq miss cycles 1293system.iocache.demand_miss_latency::tsunami.ide 4952739792 # number of demand (read+write) miss cycles 1294system.iocache.demand_miss_latency::total 4952739792 # number of demand (read+write) miss cycles 1295system.iocache.overall_miss_latency::tsunami.ide 4952739792 # number of overall miss cycles 1296system.iocache.overall_miss_latency::total 4952739792 # number of overall miss cycles |
| 1298system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1299system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1300system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1301system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1302system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1303system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1304system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1305system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1306system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1307system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1308system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1309system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1310system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1311system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1312system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1313system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1297system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1298system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1299system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1300system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1301system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1302system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1303system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1304system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1305system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1306system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1307system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1308system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1309system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1310system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1311system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1312system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1314system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126779.670520 # average ReadReq miss latency 1315system.iocache.ReadReq_avg_miss_latency::total 126779.670520 # average ReadReq miss latency 1316system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118883.210170 # average WriteLineReq miss latency 1317system.iocache.WriteLineReq_avg_miss_latency::total 118883.210170 # average WriteLineReq miss latency 1318system.iocache.demand_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency 1319system.iocache.demand_avg_miss_latency::total 118915.950437 # average overall miss latency 1320system.iocache.overall_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency 1321system.iocache.overall_avg_miss_latency::total 118915.950437 # average overall miss latency 1322system.iocache.blocked_cycles::no_mshrs 2115 # number of cycles access was blocked | 1313system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126823.023121 # average ReadReq miss latency 1314system.iocache.ReadReq_avg_miss_latency::total 126823.023121 # average ReadReq miss latency 1315system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118665.753971 # average WriteLineReq miss latency 1316system.iocache.WriteLineReq_avg_miss_latency::total 118665.753971 # average WriteLineReq miss latency 1317system.iocache.demand_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency 1318system.iocache.demand_avg_miss_latency::total 118699.575602 # average overall miss latency 1319system.iocache.overall_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency 1320system.iocache.overall_avg_miss_latency::total 118699.575602 # average overall miss latency 1321system.iocache.blocked_cycles::no_mshrs 1416 # number of cycles access was blocked |
| 1323system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1322system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1324system.iocache.blocked::no_mshrs 16 # number of cycles access was blocked | 1323system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked |
| 1325system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1324system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1326system.iocache.avg_blocked_cycles::no_mshrs 132.187500 # average number of cycles each access was blocked | 1325system.iocache.avg_blocked_cycles::no_mshrs 108.923077 # average number of cycles each access was blocked |
| 1327system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1328system.iocache.writebacks::writebacks 41512 # number of writebacks 1329system.iocache.writebacks::total 41512 # number of writebacks 1330system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1331system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1332system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1333system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1334system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1335system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1336system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1337system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 1326system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1327system.iocache.writebacks::writebacks 41512 # number of writebacks 1328system.iocache.writebacks::total 41512 # number of writebacks 1329system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1330system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1331system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1332system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1333system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1334system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1335system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1336system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 1338system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13282883 # number of ReadReq MSHR miss cycles 1339system.iocache.ReadReq_mshr_miss_latency::total 13282883 # number of ReadReq MSHR miss cycles 1340system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2859804565 # number of WriteLineReq MSHR miss cycles 1341system.iocache.WriteLineReq_mshr_miss_latency::total 2859804565 # number of WriteLineReq MSHR miss cycles 1342system.iocache.demand_mshr_miss_latency::tsunami.ide 2873087448 # number of demand (read+write) MSHR miss cycles 1343system.iocache.demand_mshr_miss_latency::total 2873087448 # number of demand (read+write) MSHR miss cycles 1344system.iocache.overall_mshr_miss_latency::tsunami.ide 2873087448 # number of overall MSHR miss cycles 1345system.iocache.overall_mshr_miss_latency::total 2873087448 # number of overall MSHR miss cycles | 1337system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13290383 # number of ReadReq MSHR miss cycles 1338system.iocache.ReadReq_mshr_miss_latency::total 13290383 # number of ReadReq MSHR miss cycles 1339system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2850780302 # number of WriteLineReq MSHR miss cycles 1340system.iocache.WriteLineReq_mshr_miss_latency::total 2850780302 # number of WriteLineReq MSHR miss cycles 1341system.iocache.demand_mshr_miss_latency::tsunami.ide 2864070685 # number of demand (read+write) MSHR miss cycles 1342system.iocache.demand_mshr_miss_latency::total 2864070685 # number of demand (read+write) MSHR miss cycles 1343system.iocache.overall_mshr_miss_latency::tsunami.ide 2864070685 # number of overall MSHR miss cycles 1344system.iocache.overall_mshr_miss_latency::total 2864070685 # number of overall MSHR miss cycles |
| 1346system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1347system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1348system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1349system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1350system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1351system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1352system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1353system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1345system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1346system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1347system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1348system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1349system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1350system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1351system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1352system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1354system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76779.670520 # average ReadReq mshr miss latency 1355system.iocache.ReadReq_avg_mshr_miss_latency::total 76779.670520 # average ReadReq mshr miss latency 1356system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68824.715176 # average WriteLineReq mshr miss latency 1357system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.715176 # average WriteLineReq mshr miss latency 1358system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency 1359system.iocache.demand_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency 1360system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency 1361system.iocache.overall_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency 1362system.membus.snoop_filter.tot_requests 825525 # Total number of requests made to the snoop filter. 1363system.membus.snoop_filter.hit_single_requests 380458 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1364system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1353system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76823.023121 # average ReadReq mshr miss latency 1354system.iocache.ReadReq_avg_mshr_miss_latency::total 76823.023121 # average ReadReq mshr miss latency 1355system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68607.535185 # average WriteLineReq mshr miss latency 1356system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68607.535185 # average WriteLineReq mshr miss latency 1357system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency 1358system.iocache.demand_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency 1359system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency 1360system.iocache.overall_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency 1361system.membus.snoop_filter.tot_requests 825546 # Total number of requests made to the snoop filter. 1362system.membus.snoop_filter.hit_single_requests 380389 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1363system.membus.snoop_filter.hit_multi_requests 528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1365system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1366system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1367system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1364system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1365system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1366system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1368system.membus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states | 1367system.membus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states |
| 1369system.membus.trans_dist::ReadReq 6930 # Transaction distribution | 1368system.membus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1370system.membus.trans_dist::ReadResp 296573 # Transaction distribution | 1369system.membus.trans_dist::ReadResp 296601 # Transaction distribution |
| 1371system.membus.trans_dist::WriteReq 9599 # Transaction distribution 1372system.membus.trans_dist::WriteResp 9599 # Transaction distribution | 1370system.membus.trans_dist::WriteReq 9599 # Transaction distribution 1371system.membus.trans_dist::WriteResp 9599 # Transaction distribution |
| 1373system.membus.trans_dist::WritebackDirty 117412 # Transaction distribution 1374system.membus.trans_dist::CleanEvict 262094 # Transaction distribution | 1372system.membus.trans_dist::WritebackDirty 117441 # Transaction distribution 1373system.membus.trans_dist::CleanEvict 262065 # Transaction distribution |
| 1375system.membus.trans_dist::UpgradeReq 137 # Transaction distribution 1376system.membus.trans_dist::UpgradeResp 3 # Transaction distribution | 1374system.membus.trans_dist::UpgradeReq 137 # Transaction distribution 1375system.membus.trans_dist::UpgradeResp 3 # Transaction distribution |
| 1377system.membus.trans_dist::ReadExReq 114597 # Transaction distribution 1378system.membus.trans_dist::ReadExResp 114597 # Transaction distribution 1379system.membus.trans_dist::ReadSharedReq 289683 # Transaction distribution 1380system.membus.trans_dist::BadAddressError 40 # Transaction distribution | 1376system.membus.trans_dist::ReadExReq 114568 # Transaction distribution 1377system.membus.trans_dist::ReadExResp 114568 # Transaction distribution 1378system.membus.trans_dist::ReadSharedReq 289718 # Transaction distribution 1379system.membus.trans_dist::BadAddressError 47 # Transaction distribution |
| 1381system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution | 1380system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 1381system.membus.trans_dist::InvalidateResp 124 # Transaction distribution |
|
| 1382system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) | 1382system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) |
| 1383system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145815 # Packet count per connected master and slave (bytes) 1384system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 80 # Packet count per connected master and slave (bytes) 1385system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178953 # Packet count per connected master and slave (bytes) | 1383system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145812 # Packet count per connected master and slave (bytes) 1384system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) 1385system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178964 # Packet count per connected master and slave (bytes) |
| 1386system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1387system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) | 1386system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1387system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) |
| 1388system.membus.pkt_count::total 1262378 # Packet count per connected master and slave (bytes) | 1388system.membus.pkt_count::total 1262389 # Packet count per connected master and slave (bytes) |
| 1389system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) | 1389system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) |
| 1390system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30700160 # Cumulative packet size per connected master and slave (bytes) 1391system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30744316 # Cumulative packet size per connected master and slave (bytes) | 1390system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701888 # Cumulative packet size per connected master and slave (bytes) 1391system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746044 # Cumulative packet size per connected master and slave (bytes) |
| 1392system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1393system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) | 1392system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1393system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) |
| 1394system.membus.pkt_size::total 33402044 # Cumulative packet size per connected master and slave (bytes) 1395system.membus.snoops 438 # Total snoops (count) 1396system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) 1397system.membus.snoop_fanout::samples 462498 # Request fanout histogram 1398system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram 1399system.membus.snoop_fanout::stdev 0.038232 # Request fanout histogram | 1394system.membus.pkt_size::total 33403772 # Cumulative packet size per connected master and slave (bytes) 1395system.membus.snoops 563 # Total snoops (count) 1396system.membus.snoopTraffic 27904 # Total snoop traffic (bytes) 1397system.membus.snoop_fanout::samples 462504 # Request fanout histogram 1398system.membus.snoop_fanout::mean 0.001466 # Request fanout histogram 1399system.membus.snoop_fanout::stdev 0.038259 # Request fanout histogram |
| 1400system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1400system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1401system.membus.snoop_fanout::0 461821 99.85% 99.85% # Request fanout histogram 1402system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram | 1401system.membus.snoop_fanout::0 461826 99.85% 99.85% # Request fanout histogram 1402system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram |
| 1403system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1404system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1405system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1406system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1403system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1404system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1405system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1406system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1407system.membus.snoop_fanout::total 462498 # Request fanout histogram 1408system.membus.reqLayer0.occupancy 28738500 # Layer occupancy (ticks) | 1407system.membus.snoop_fanout::total 462504 # Request fanout histogram 1408system.membus.reqLayer0.occupancy 28800500 # Layer occupancy (ticks) |
| 1409system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1409system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1410system.membus.reqLayer1.occupancy 1313413567 # Layer occupancy (ticks) | 1410system.membus.reqLayer1.occupancy 1313542061 # Layer occupancy (ticks) |
| 1411system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1411system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1412system.membus.reqLayer2.occupancy 48500 # Layer occupancy (ticks) | 1412system.membus.reqLayer2.occupancy 57500 # Layer occupancy (ticks) |
| 1413system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1413system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1414system.membus.respLayer1.occupancy 2137867250 # Layer occupancy (ticks) | 1414system.membus.respLayer1.occupancy 2137882250 # Layer occupancy (ticks) |
| 1415system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | 1415system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1416system.membus.respLayer2.occupancy 917617 # Layer occupancy (ticks) | 1416system.membus.respLayer2.occupancy 1056521 # Layer occupancy (ticks) |
| 1417system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1417system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1418system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1419system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1420system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1421system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1422system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states | 1418system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1419system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1420system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1421system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1422system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states |
| 1423system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1424system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1425system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1426system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1427system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1428system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1429system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1430system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1446system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1447system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1448system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1449system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1450system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1451system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1452system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1453system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 1423system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1424system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1425system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1426system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1427system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1428system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1429system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1430system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1446system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1447system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1448system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1449system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1450system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1451system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1452system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1453system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1454system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1455system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1456system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1457system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1458system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1459system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1460system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1461system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1462system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1463system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1464system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1465system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1466system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1467system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1468system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1469system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1470system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1471system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1472system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1473system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1474system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1475system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states 1476system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states | 1454system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1455system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1456system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1457system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1458system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1459system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1460system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1461system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1462system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1463system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1464system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1465system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1466system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1467system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1468system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1469system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1470system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1471system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1472system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1473system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1474system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1475system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states 1476system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states |
| 1477system.cpu.kern.inst.arm 0 # number of arm instructions executed 1478system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 1479system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed 1480system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl 1481system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1482system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl 1483system.cpu.kern.ipl_count::31 105578 57.93% 100.00% # number of times we switched to this ipl 1484system.cpu.kern.ipl_count::total 182260 # number of times we switched to this ipl 1485system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1486system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1487system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1488system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1489system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl | 1477system.cpu.kern.inst.arm 0 # number of arm instructions executed 1478system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 1479system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed 1480system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl 1481system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1482system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl 1483system.cpu.kern.ipl_count::31 105578 57.93% 100.00% # number of times we switched to this ipl 1484system.cpu.kern.ipl_count::total 182260 # number of times we switched to this ipl 1485system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1486system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1487system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1488system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1489system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl |
| 1490system.cpu.kern.ipl_ticks::0 1819136783500 97.54% 97.54% # number of cycles we spent at this ipl 1491system.cpu.kern.ipl_ticks::21 67099500 0.00% 97.54% # number of cycles we spent at this ipl 1492system.cpu.kern.ipl_ticks::22 565538000 0.03% 97.57% # number of cycles we spent at this ipl 1493system.cpu.kern.ipl_ticks::31 45241360000 2.43% 100.00% # number of cycles we spent at this ipl 1494system.cpu.kern.ipl_ticks::total 1865010781000 # number of cycles we spent at this ipl | 1490system.cpu.kern.ipl_ticks::0 1819124828000 97.54% 97.54% # number of cycles we spent at this ipl 1491system.cpu.kern.ipl_ticks::21 67368000 0.00% 97.54% # number of cycles we spent at this ipl 1492system.cpu.kern.ipl_ticks::22 565513500 0.03% 97.57% # number of cycles we spent at this ipl 1493system.cpu.kern.ipl_ticks::31 45251211500 2.43% 100.00% # number of cycles we spent at this ipl 1494system.cpu.kern.ipl_ticks::total 1865008921000 # number of cycles we spent at this ipl |
| 1495system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl 1496system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1497system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1498system.cpu.kern.ipl_used::31 0.694302 # fraction of swpipl calls that actually changed the ipl 1499system.cpu.kern.ipl_used::total 0.815418 # fraction of swpipl calls that actually changed the ipl 1500system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1501system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1502system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed --- 6 unchanged lines hidden (view full) --- 1509system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1510system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1511system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1512system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1513system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed 1514system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1515system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 1516system.cpu.kern.callpal::total 191988 # number of callpals executed | 1495system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl 1496system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1497system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1498system.cpu.kern.ipl_used::31 0.694302 # fraction of swpipl calls that actually changed the ipl 1499system.cpu.kern.ipl_used::total 0.815418 # fraction of swpipl calls that actually changed the ipl 1500system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1501system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1502system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed --- 6 unchanged lines hidden (view full) --- 1509system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1510system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1511system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1512system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1513system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed 1514system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1515system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 1516system.cpu.kern.callpal::total 191988 # number of callpals executed |
| 1517system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches | 1517system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches |
| 1518system.cpu.kern.mode_switch::user 1738 # number of protection mode switches | 1518system.cpu.kern.mode_switch::user 1738 # number of protection mode switches |
| 1519system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches | 1519system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches |
| 1520system.cpu.kern.mode_good::kernel 1908 1521system.cpu.kern.mode_good::user 1738 1522system.cpu.kern.mode_good::idle 170 | 1520system.cpu.kern.mode_good::kernel 1908 1521system.cpu.kern.mode_good::user 1738 1522system.cpu.kern.mode_good::idle 170 |
| 1523system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches | 1523system.cpu.kern.mode_switch_good::kernel 0.326098 # fraction of useful protection mode switches |
| 1524system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1524system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1525system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches | 1525system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches |
| 1526system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches | 1526system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches |
| 1527system.cpu.kern.mode_ticks::kernel 29668657000 1.59% 1.59% # number of ticks spent at the given mode 1528system.cpu.kern.mode_ticks::user 2761122500 0.15% 1.74% # number of ticks spent at the given mode 1529system.cpu.kern.mode_ticks::idle 1832580993500 98.26% 100.00% # number of ticks spent at the given mode | 1527system.cpu.kern.mode_ticks::kernel 29666586000 1.59% 1.59% # number of ticks spent at the given mode 1528system.cpu.kern.mode_ticks::user 2759246500 0.15% 1.74% # number of ticks spent at the given mode 1529system.cpu.kern.mode_ticks::idle 1832583080500 98.26% 100.00% # number of ticks spent at the given mode |
| 1530system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1531 1532---------- End Simulation Statistics ---------- | 1530system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1531 1532---------- End Simulation Statistics ---------- |