| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.876794 # Number of seconds simulated 4sim_ticks 1876794488000 # Number of ticks simulated 5final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.862042 # Number of seconds simulated 4sim_ticks 1862042063000 # Number of ticks simulated 5final_tick 1862042063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 152079 # Simulator instruction rate (inst/s) 8host_op_rate 152079 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5387044029 # Simulator tick rate (ticks/s) 10host_mem_usage 330796 # Number of bytes of host memory used 11host_seconds 348.39 # Real time elapsed on the host 12sim_insts 52982943 # Number of instructions simulated 13sim_ops 52982943 # Number of ops (including micro ops) simulated | 7host_inst_rate 137297 # Simulator instruction rate (inst/s) 8host_op_rate 137297 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4825772422 # Simulator tick rate (ticks/s) 10host_mem_usage 338492 # Number of bytes of host memory used 11host_seconds 385.85 # Real time elapsed on the host 12sim_insts 52976505 # Number of instructions simulated 13sim_ops 52976505 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 963392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24881792 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7527680 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 15027 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory | 20system.physmem.bytes_read::total 25846144 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 963392 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 963392 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7528832 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7528832 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 15053 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388778 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::total 403799 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 117620 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 117620 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 512431 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 13256885 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 13769827 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 512431 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 512431 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 4010924 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 4010924 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 4010924 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 512431 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 13256885 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 17780751 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 403799 # Number of read requests accepted 45system.physmem.writeReqs 117620 # Number of write requests accepted 46system.physmem.readBursts 403799 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 117620 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25835776 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7525824 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25843136 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7527680 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue | 28system.physmem.num_reads::total 403846 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 117638 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 117638 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 517385 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 13362637 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 13880537 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 517385 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 517385 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 4043320 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 4043320 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 4043320 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 517385 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 13362637 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 17923857 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 403846 # Number of read requests accepted 45system.physmem.writeReqs 117638 # Number of write requests accepted 46system.physmem.readBursts 403846 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 117638 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25839232 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7527104 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25846144 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7528832 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue |
| 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 25625 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25421 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25559 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25464 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25431 # Per bank write bursts 61system.physmem.perBankRdBursts::5 24732 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24935 # Per bank write bursts 63system.physmem.perBankRdBursts::7 25090 # Per bank write bursts 64system.physmem.perBankRdBursts::8 24946 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25020 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25560 # Per bank write bursts 67system.physmem.perBankRdBursts::11 24886 # Per bank write bursts 68system.physmem.perBankRdBursts::12 24460 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25266 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25703 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25586 # Per bank write bursts 72system.physmem.perBankWrBursts::0 7949 # Per bank write bursts 73system.physmem.perBankWrBursts::1 7513 # Per bank write bursts 74system.physmem.perBankWrBursts::2 7969 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7485 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7367 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6667 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6767 # Per bank write bursts 79system.physmem.perBankWrBursts::7 6715 # Per bank write bursts 80system.physmem.perBankWrBursts::8 7150 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6697 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7421 # Per bank write bursts 83system.physmem.perBankWrBursts::11 6978 # Per bank write bursts 84system.physmem.perBankWrBursts::12 7150 # Per bank write bursts 85system.physmem.perBankWrBursts::13 7899 # Per bank write bursts 86system.physmem.perBankWrBursts::14 8060 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7804 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 25618 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25426 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25537 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25512 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25419 # Per bank write bursts 61system.physmem.perBankRdBursts::5 24740 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24937 # Per bank write bursts 63system.physmem.perBankRdBursts::7 25096 # Per bank write bursts 64system.physmem.perBankRdBursts::8 24930 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25035 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25569 # Per bank write bursts 67system.physmem.perBankRdBursts::11 24892 # Per bank write bursts 68system.physmem.perBankRdBursts::12 24450 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25273 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25713 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25591 # Per bank write bursts 72system.physmem.perBankWrBursts::0 7930 # Per bank write bursts 73system.physmem.perBankWrBursts::1 7514 # Per bank write bursts 74system.physmem.perBankWrBursts::2 7945 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7523 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7351 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6673 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6769 # Per bank write bursts 79system.physmem.perBankWrBursts::7 6726 # Per bank write bursts 80system.physmem.perBankWrBursts::8 7138 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6708 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7428 # Per bank write bursts 83system.physmem.perBankWrBursts::11 6991 # Per bank write bursts 84system.physmem.perBankWrBursts::12 7147 # Per bank write bursts 85system.physmem.perBankWrBursts::13 7895 # Per bank write bursts 86system.physmem.perBankWrBursts::14 8063 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7810 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 89system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 90system.physmem.totGap 1876789160500 # Total gap between requests | 89system.physmem.numWrRetry 12 # Number of times write queue was full causing retry 90system.physmem.totGap 1862036687500 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 403799 # Read request sizes (log2) | 97system.physmem.readPktSize::6 403846 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 117620 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 315619 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 35764 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 28247 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 23961 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 117638 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 315267 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 36112 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 28338 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 23939 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see |
| 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 2968 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 4960 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 4449 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6001 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 5883 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6949 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 6473 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 8556 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 8916 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 7560 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 7602 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 6731 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5823 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 313 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 152 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 100 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 1560 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 2800 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 3376 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 4390 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 5897 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6646 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 7683 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 9037 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 7269 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 7983 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 8709 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7918 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 7106 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 7375 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 7621 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 5960 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 6241 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5674 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 189 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 137 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 212 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see |
| 182system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see | 182system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see |
| 183system.physmem.wrQLenPdf::46 200 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 157 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 111 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 43 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 62139 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 536.886657 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 331.247155 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 411.697741 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 13677 22.01% 22.01% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 10478 16.86% 38.87% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4968 7.99% 46.87% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 2775 4.47% 51.33% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2441 3.93% 55.26% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 1588 2.56% 57.82% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 3776 6.08% 63.89% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1174 1.89% 65.78% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 21262 34.22% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 62139 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5217 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 77.374545 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2903.927058 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5214 99.94% 99.94% # Reads before turning the bus around for writes | 183system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 205 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 216 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 154 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 175 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 112 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 129 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 110 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 63 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 61611 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 541.558358 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 333.246769 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 417.180517 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 13396 21.74% 21.74% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 10505 17.05% 38.79% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 5359 8.70% 47.49% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 2621 4.25% 51.75% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2461 3.99% 55.74% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 1425 2.31% 58.05% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1507 2.45% 60.50% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1351 2.19% 62.69% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 22986 37.31% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 61611 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5236 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 77.104660 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2917.579007 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5233 99.94% 99.94% # Reads before turning the bus around for writes |
| 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 222system.physmem.rdPerTurnAround::total 5217 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5217 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.539965 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 19.244136 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 20.635763 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4619 88.54% 88.54% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 29 0.56% 89.09% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 25 0.48% 89.57% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 38 0.73% 90.30% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 214 4.10% 94.40% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 9 0.17% 94.58% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 11 0.21% 94.79% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 34 0.65% 95.44% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 184 3.53% 98.96% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 5 0.10% 99.06% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 5 0.10% 99.16% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 4 0.08% 99.23% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::128-135 6 0.12% 99.35% # Writes before turning the bus around for reads | 222system.physmem.rdPerTurnAround::total 5236 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5236 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.461994 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 19.033018 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 22.013556 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4631 88.45% 88.45% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 42 0.80% 89.25% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 243 4.64% 93.89% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 21 0.40% 94.29% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 6 0.11% 94.40% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 10 0.19% 94.60% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 6 0.11% 94.71% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 2 0.04% 94.75% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 20 0.38% 95.13% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 23 0.44% 95.57% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 185 3.53% 99.10% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 2 0.04% 99.14% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::112-119 3 0.06% 99.20% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-127 1 0.02% 99.22% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 7 0.13% 99.35% # Writes before turning the bus around for reads |
| 240system.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::144-151 1 0.02% 99.39% # Writes before turning the bus around for reads | 242system.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::144-151 1 0.02% 99.39% # Writes before turning the bus around for reads |
| 242system.physmem.wrPerTurnAround::160-167 4 0.08% 99.46% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::168-175 8 0.15% 99.62% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::176-183 4 0.08% 99.69% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::184-191 3 0.06% 99.75% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::208-215 6 0.12% 99.94% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::256-263 2 0.04% 99.98% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::total 5217 # Writes before turning the bus around for reads 252system.physmem.totQLat 4201005000 # Total ticks spent queuing 253system.physmem.totMemAccLat 11770080000 # Total ticks spent from burst creation until serviced by the DRAM 254system.physmem.totBusLat 2018420000 # Total ticks spent in databus transfers 255system.physmem.avgQLat 10406.67 # Average queueing delay per DRAM burst | 244system.physmem.wrPerTurnAround::152-159 3 0.06% 99.45% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::160-167 2 0.04% 99.48% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::168-175 11 0.21% 99.69% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::208-215 3 0.06% 99.83% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::total 5236 # Writes before turning the bus around for reads 255system.physmem.totQLat 3726058000 # Total ticks spent queuing 256system.physmem.totMemAccLat 11296145500 # Total ticks spent from burst creation until serviced by the DRAM 257system.physmem.totBusLat 2018690000 # Total ticks spent in databus transfers 258system.physmem.avgQLat 9228.90 # Average queueing delay per DRAM burst |
| 256system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 257system.physmem.avgMemAccLat 29156.67 # Average memory access latency per DRAM burst 258system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 259system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s 260system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s 261system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s | 260system.physmem.avgMemAccLat 27978.90 # Average memory access latency per DRAM burst 261system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 263system.physmem.avgRdBWSys 13.88 # Average system read bandwidth in MiByte/s 264system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s |
| 262system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 263system.physmem.busUtil 0.14 # Data bus utilization in percentage 264system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 265system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 266system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing | 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 266system.physmem.busUtil 0.14 # Data bus utilization in percentage 267system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 268system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 269system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing |
| 267system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing 268system.physmem.readRowHits 363845 # Number of row buffer hits during reads 269system.physmem.writeRowHits 95291 # Number of row buffer hits during writes 270system.physmem.readRowHitRate 90.13 # Row buffer hit rate for reads 271system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes 272system.physmem.avgGap 3599387.75 # Average gap between requests 273system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined 274system.physmem_0.actEnergy 233399880 # Energy for activate commands per rank (pJ) 275system.physmem_0.preEnergy 127351125 # Energy for precharge commands per rank (pJ) 276system.physmem_0.readEnergy 1577604600 # Energy for read commands per rank (pJ) 277system.physmem_0.writeEnergy 378639360 # Energy for write commands per rank (pJ) 278system.physmem_0.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) 279system.physmem_0.actBackEnergy 61740410985 # Energy for active background per rank (pJ) 280system.physmem_0.preBackEnergy 1071915840750 # Energy for precharge background per rank (pJ) 281system.physmem_0.totalEnergy 1258556040540 # Total energy per rank (pJ) 282system.physmem_0.averagePower 670.589641 # Core power per rank (mW) 283system.physmem_0.memoryStateTime::IDLE 1783024934000 # Time in different power states 284system.physmem_0.memoryStateTime::REF 62670140000 # Time in different power states | 270system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing 271system.physmem.readRowHits 364089 # Number of row buffer hits during reads 272system.physmem.writeRowHits 95648 # Number of row buffer hits during writes 273system.physmem.readRowHitRate 90.18 # Row buffer hit rate for reads 274system.physmem.writeRowHitRate 81.31 # Row buffer hit rate for writes 275system.physmem.avgGap 3570649.70 # Average gap between requests 276system.physmem.pageHitRate 88.18 # Row buffer hit rate, read and write combined 277system.physmem_0.actEnergy 230882400 # Energy for activate commands per rank (pJ) 278system.physmem_0.preEnergy 125977500 # Energy for precharge commands per rank (pJ) 279system.physmem_0.readEnergy 1577823000 # Energy for read commands per rank (pJ) 280system.physmem_0.writeEnergy 378632880 # Energy for write commands per rank (pJ) 281system.physmem_0.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) 282system.physmem_0.actBackEnergy 56327619735 # Energy for active background per rank (pJ) 283system.physmem_0.preBackEnergy 1067810937000 # Energy for precharge background per rank (pJ) 284system.physmem_0.totalEnergy 1248070945155 # Total energy per rank (pJ) 285system.physmem_0.averagePower 670.272471 # Core power per rank (mW) 286system.physmem_0.memoryStateTime::IDLE 1776230272500 # Time in different power states 287system.physmem_0.memoryStateTime::REF 62177440000 # Time in different power states |
| 285system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 288system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 286system.physmem_0.memoryStateTime::ACT 31095099750 # Time in different power states | 289system.physmem_0.memoryStateTime::ACT 23627517500 # Time in different power states |
| 287system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 290system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 288system.physmem_1.actEnergy 236370960 # Energy for activate commands per rank (pJ) 289system.physmem_1.preEnergy 128972250 # Energy for precharge commands per rank (pJ) 290system.physmem_1.readEnergy 1571130600 # Energy for read commands per rank (pJ) 291system.physmem_1.writeEnergy 383350320 # Energy for write commands per rank (pJ) 292system.physmem_1.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) 293system.physmem_1.actBackEnergy 61477234290 # Energy for active background per rank (pJ) 294system.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ) 295system.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ) 296system.physmem_1.averagePower 670.573928 # Core power per rank (mW) 297system.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states 298system.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states | 291system.physmem_1.actEnergy 234896760 # Energy for activate commands per rank (pJ) 292system.physmem_1.preEnergy 128167875 # Energy for precharge commands per rank (pJ) 293system.physmem_1.readEnergy 1571286600 # Energy for read commands per rank (pJ) 294system.physmem_1.writeEnergy 383486400 # Energy for write commands per rank (pJ) 295system.physmem_1.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) 296system.physmem_1.actBackEnergy 56258103960 # Energy for active background per rank (pJ) 297system.physmem_1.preBackEnergy 1067871924000 # Energy for precharge background per rank (pJ) 298system.physmem_1.totalEnergy 1248066938235 # Total energy per rank (pJ) 299system.physmem_1.averagePower 670.270314 # Core power per rank (mW) 300system.physmem_1.memoryStateTime::IDLE 1776335363750 # Time in different power states 301system.physmem_1.memoryStateTime::REF 62177440000 # Time in different power states |
| 299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 302system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 300system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states | 303system.physmem_1.memoryStateTime::ACT 23523591750 # Time in different power states |
| 301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 304system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 302system.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 303system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 304system.cpu.branchPred.lookups 19569408 # Number of BP lookups 305system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted 306system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect 307system.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups 308system.cpu.branchPred.BTBHits 5420664 # Number of BTB hits | 305system.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 306system.bridge.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 307system.cpu.branchPred.lookups 19539848 # Number of BP lookups 308system.cpu.branchPred.condPredicted 16614646 # Number of conditional branches predicted 309system.cpu.branchPred.condIncorrect 591620 # Number of conditional branches incorrect 310system.cpu.branchPred.BTBLookups 12579114 # Number of BTB lookups 311system.cpu.branchPred.BTBHits 5416634 # Number of BTB hits |
| 309system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 312system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 310system.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage 311system.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target. 312system.cpu.branchPred.RASInCorrect 42865 # Number of incorrect RAS predictions. 313system.cpu.branchPred.indirectLookups 6372302 # Number of indirect predictor lookups. 314system.cpu.branchPred.indirectHits 563108 # Number of indirect target hits. 315system.cpu.branchPred.indirectMisses 5809194 # Number of indirect misses. 316system.cpu.branchPredindirectMispredicted 264983 # Number of mispredicted indirect branches. | 313system.cpu.branchPred.BTBHitPct 43.060537 # BTB Hit Percentage 314system.cpu.branchPred.usedRAS 1121926 # Number of times the RAS was used to get a target. 315system.cpu.branchPred.RASInCorrect 41569 # Number of incorrect RAS predictions. 316system.cpu.branchPred.indirectLookups 6087322 # Number of indirect predictor lookups. 317system.cpu.branchPred.indirectHits 563395 # Number of indirect target hits. 318system.cpu.branchPred.indirectMisses 5523927 # Number of indirect misses. 319system.cpu.branchPredindirectMispredicted 264320 # Number of mispredicted indirect branches. |
| 317system.cpu_clk_domain.clock 500 # Clock period in ticks 318system.cpu.dtb.fetch_hits 0 # ITB hits 319system.cpu.dtb.fetch_misses 0 # ITB misses 320system.cpu.dtb.fetch_acv 0 # ITB acv 321system.cpu.dtb.fetch_accesses 0 # ITB accesses | 320system.cpu_clk_domain.clock 500 # Clock period in ticks 321system.cpu.dtb.fetch_hits 0 # ITB hits 322system.cpu.dtb.fetch_misses 0 # ITB misses 323system.cpu.dtb.fetch_acv 0 # ITB acv 324system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 322system.cpu.dtb.read_hits 11131372 # DTB read hits 323system.cpu.dtb.read_misses 49301 # DTB read misses 324system.cpu.dtb.read_acv 623 # DTB read access violations 325system.cpu.dtb.read_accesses 996761 # DTB read accesses 326system.cpu.dtb.write_hits 6776847 # DTB write hits 327system.cpu.dtb.write_misses 12217 # DTB write misses 328system.cpu.dtb.write_acv 418 # DTB write access violations 329system.cpu.dtb.write_accesses 345142 # DTB write accesses 330system.cpu.dtb.data_hits 17908219 # DTB hits 331system.cpu.dtb.data_misses 61518 # DTB misses 332system.cpu.dtb.data_acv 1041 # DTB access violations 333system.cpu.dtb.data_accesses 1341903 # DTB accesses 334system.cpu.itb.fetch_hits 1817383 # ITB hits 335system.cpu.itb.fetch_misses 10321 # ITB misses 336system.cpu.itb.fetch_acv 767 # ITB acv 337system.cpu.itb.fetch_accesses 1827704 # ITB accesses | 325system.cpu.dtb.read_hits 11126873 # DTB read hits 326system.cpu.dtb.read_misses 49288 # DTB read misses 327system.cpu.dtb.read_acv 612 # DTB read access violations 328system.cpu.dtb.read_accesses 995471 # DTB read accesses 329system.cpu.dtb.write_hits 6773971 # DTB write hits 330system.cpu.dtb.write_misses 12183 # DTB write misses 331system.cpu.dtb.write_acv 423 # DTB write access violations 332system.cpu.dtb.write_accesses 345274 # DTB write accesses 333system.cpu.dtb.data_hits 17900844 # DTB hits 334system.cpu.dtb.data_misses 61471 # DTB misses 335system.cpu.dtb.data_acv 1035 # DTB access violations 336system.cpu.dtb.data_accesses 1340745 # DTB accesses 337system.cpu.itb.fetch_hits 1815480 # ITB hits 338system.cpu.itb.fetch_misses 10441 # ITB misses 339system.cpu.itb.fetch_acv 750 # ITB acv 340system.cpu.itb.fetch_accesses 1825921 # ITB accesses |
| 338system.cpu.itb.read_hits 0 # DTB read hits 339system.cpu.itb.read_misses 0 # DTB read misses 340system.cpu.itb.read_acv 0 # DTB read access violations 341system.cpu.itb.read_accesses 0 # DTB read accesses 342system.cpu.itb.write_hits 0 # DTB write hits 343system.cpu.itb.write_misses 0 # DTB write misses 344system.cpu.itb.write_acv 0 # DTB write access violations 345system.cpu.itb.write_accesses 0 # DTB write accesses 346system.cpu.itb.data_hits 0 # DTB hits 347system.cpu.itb.data_misses 0 # DTB misses 348system.cpu.itb.data_acv 0 # DTB access violations 349system.cpu.itb.data_accesses 0 # DTB accesses | 341system.cpu.itb.read_hits 0 # DTB read hits 342system.cpu.itb.read_misses 0 # DTB read misses 343system.cpu.itb.read_acv 0 # DTB read access violations 344system.cpu.itb.read_accesses 0 # DTB read accesses 345system.cpu.itb.write_hits 0 # DTB write hits 346system.cpu.itb.write_misses 0 # DTB write misses 347system.cpu.itb.write_acv 0 # DTB write access violations 348system.cpu.itb.write_accesses 0 # DTB write accesses 349system.cpu.itb.data_hits 0 # DTB hits 350system.cpu.itb.data_misses 0 # DTB misses 351system.cpu.itb.data_acv 0 # DTB access violations 352system.cpu.itb.data_accesses 0 # DTB accesses |
| 350system.cpu.numPwrStateTransitions 12876 # Number of power state transitions 351system.cpu.pwrStateClkGateDist::samples 6438 # Distribution of time spent in the clock gated state 352system.cpu.pwrStateClkGateDist::mean 279467835.818577 # Distribution of time spent in the clock gated state 353system.cpu.pwrStateClkGateDist::stdev 439243252.658256 # Distribution of time spent in the clock gated state 354system.cpu.pwrStateClkGateDist::1000-5e+10 6438 100.00% 100.00% # Distribution of time spent in the clock gated state 355system.cpu.pwrStateClkGateDist::min_value 81000 # Distribution of time spent in the clock gated state | 353system.cpu.numPwrStateTransitions 12878 # Number of power state transitions 354system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state 355system.cpu.pwrStateClkGateDist::mean 279534848.967231 # Distribution of time spent in the clock gated state 356system.cpu.pwrStateClkGateDist::stdev 439378966.267034 # Distribution of time spent in the clock gated state 357system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state 358system.cpu.pwrStateClkGateDist::min_value 96000 # Distribution of time spent in the clock gated state |
| 356system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state | 359system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state |
| 357system.cpu.pwrStateClkGateDist::total 6438 # Distribution of time spent in the clock gated state 358system.cpu.pwrStateResidencyTicks::ON 77580561000 # Cumulative time (in ticks) in various power states 359system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000 # Cumulative time (in ticks) in various power states 360system.cpu.numCycles 155167561 # number of cpu cycles simulated | 360system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state 361system.cpu.pwrStateResidencyTicks::ON 62117170500 # Cumulative time (in ticks) in various power states 362system.cpu.pwrStateResidencyTicks::CLK_GATED 1799924892500 # Cumulative time (in ticks) in various power states 363system.cpu.numCycles 124240781 # number of cpu cycles simulated |
| 361system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 362system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 364system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 365system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 363system.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss 364system.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed 365system.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered 366system.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken 367system.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked 368system.cpu.fetch.SquashCycles 1681668 # Number of cycles fetch has spent squashing 369system.cpu.fetch.TlbCycles 87 # Number of cycles fetch has spent waiting for tlb 370system.cpu.fetch.MiscStallCycles 29150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 371system.cpu.fetch.PendingTrapStallCycles 207083 # Number of stall cycles due to pending traps 372system.cpu.fetch.PendingQuiesceStallCycles 421165 # Number of stall cycles due to pending quiesce instructions 373system.cpu.fetch.IcacheWaitRetryStallCycles 751 # Number of stall cycles due to full MSHR 374system.cpu.fetch.CacheLines 9930605 # Number of cache lines fetched 375system.cpu.fetch.IcacheSquashes 406777 # Number of outstanding Icache misses that were squashed | 366system.cpu.fetch.icacheStallCycles 30188704 # Number of cycles fetch is stalled on an Icache miss 367system.cpu.fetch.Insts 85612379 # Number of instructions fetch has processed 368system.cpu.fetch.Branches 19539848 # Number of branches that fetch encountered 369system.cpu.fetch.predictedBranches 7101955 # Number of branches that fetch has predicted taken 370system.cpu.fetch.Cycles 86725868 # Number of cycles fetch has run and was not squashing or blocked 371system.cpu.fetch.SquashCycles 1678156 # Number of cycles fetch has spent squashing 372system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb 373system.cpu.fetch.MiscStallCycles 31498 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 374system.cpu.fetch.PendingTrapStallCycles 207275 # Number of stall cycles due to pending traps 375system.cpu.fetch.PendingQuiesceStallCycles 432547 # Number of stall cycles due to pending quiesce instructions 376system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR 377system.cpu.fetch.CacheLines 9909625 # Number of cache lines fetched 378system.cpu.fetch.IcacheSquashes 405389 # Number of outstanding Icache misses that were squashed |
| 376system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed | 379system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed |
| 377system.cpu.fetch.rateDist::samples 148422395 # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::mean 0.577690 # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::stdev 1.864310 # Number of instructions fetched each cycle (Total) | 380system.cpu.fetch.rateDist::samples 118425370 # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.rateDist::mean 0.722923 # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::stdev 2.060283 # Number of instructions fetched each cycle (Total) |
| 380system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 383system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 381system.cpu.fetch.rateDist::0 132578342 89.33% 89.33% # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::1 1033201 0.70% 90.02% # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::2 2106811 1.42% 91.44% # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::3 971505 0.65% 92.10% # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::4 2908700 1.96% 94.05% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::5 663530 0.45% 94.50% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::6 808471 0.54% 95.05% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::7 1037122 0.70% 95.75% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::8 6314713 4.25% 100.00% # Number of instructions fetched each cycle (Total) | 384system.cpu.fetch.rateDist::0 102607090 86.64% 86.64% # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::1 1029926 0.87% 87.51% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::2 2106958 1.78% 89.29% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::3 967243 0.82% 90.11% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::4 2899427 2.45% 92.56% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::5 665654 0.56% 93.12% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::6 809857 0.68% 93.80% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::7 1032032 0.87% 94.67% # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::8 6307183 5.33% 100.00% # Number of instructions fetched each cycle (Total) |
| 390system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 392system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 393system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 393system.cpu.fetch.rateDist::total 148422395 # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.branchRate 0.126118 # Number of branch fetches per cycle 395system.cpu.fetch.rate 0.552578 # Number of inst fetches per cycle 396system.cpu.decode.IdleCycles 24118440 # Number of cycles decode is idle 397system.cpu.decode.BlockedCycles 111208587 # Number of cycles decode is blocked 398system.cpu.decode.RunCycles 10245196 # Number of cycles decode is running 399system.cpu.decode.UnblockCycles 2044112 # Number of cycles decode is unblocking 400system.cpu.decode.SquashCycles 806059 # Number of cycles decode is squashing 401system.cpu.decode.BranchResolved 738327 # Number of times decode resolved a branch 402system.cpu.decode.BranchMispred 35573 # Number of times decode detected a branch misprediction 403system.cpu.decode.DecodedInsts 74062953 # Number of instructions handled by decode 404system.cpu.decode.SquashedInsts 114064 # Number of squashed instructions handled by decode 405system.cpu.rename.SquashCycles 806059 # Number of cycles rename is squashing 406system.cpu.rename.IdleCycles 25129468 # Number of cycles rename is idle 407system.cpu.rename.BlockCycles 79314805 # Number of cycles rename is blocking 408system.cpu.rename.serializeStallCycles 20217508 # count of cycles rename stalled for serializing inst 409system.cpu.rename.RunCycles 11209636 # Number of cycles rename is running 410system.cpu.rename.UnblockCycles 11744917 # Number of cycles rename is unblocking 411system.cpu.rename.RenamedInsts 71031430 # Number of instructions processed by rename 412system.cpu.rename.ROBFullEvents 202187 # Number of times rename has blocked due to ROB full 413system.cpu.rename.IQFullEvents 2134257 # Number of times rename has blocked due to IQ full 414system.cpu.rename.LQFullEvents 304114 # Number of times rename has blocked due to LQ full 415system.cpu.rename.SQFullEvents 7385918 # Number of times rename has blocked due to SQ full 416system.cpu.rename.RenamedOperands 47856784 # Number of destination operands rename has renamed 417system.cpu.rename.RenameLookups 85577316 # Number of register rename lookups that rename has made 418system.cpu.rename.int_rename_lookups 85396639 # Number of integer rename lookups 419system.cpu.rename.fp_rename_lookups 168224 # Number of floating rename lookups 420system.cpu.rename.CommittedMaps 38182032 # Number of HB maps that are committed 421system.cpu.rename.UndoneMaps 9674744 # Number of HB maps that are undone due to squashing 422system.cpu.rename.serializingInsts 1729903 # count of serializing insts renamed 423system.cpu.rename.tempSerializingInsts 277398 # count of temporary serializing insts renamed 424system.cpu.rename.skidInsts 13945265 # count of insts added to the skid buffer 425system.cpu.memDep0.insertedLoads 11667584 # Number of loads inserted to the mem dependence unit. 426system.cpu.memDep0.insertedStores 7222268 # Number of stores inserted to the mem dependence unit. 427system.cpu.memDep0.conflictingLoads 1740236 # Number of conflicting loads. 428system.cpu.memDep0.conflictingStores 1128330 # Number of conflicting stores. 429system.cpu.iq.iqInstsAdded 62719117 # Number of instructions added to the IQ (excludes non-spec) 430system.cpu.iq.iqNonSpecInstsAdded 2208284 # Number of non-speculative instructions added to the IQ 431system.cpu.iq.iqInstsIssued 60532785 # Number of instructions issued 432system.cpu.iq.iqSquashedInstsIssued 94680 # Number of squashed instructions issued 433system.cpu.iq.iqSquashedInstsExamined 11944453 # Number of squashed instructions iterated over during squash; mainly for profiling 434system.cpu.iq.iqSquashedOperandsExamined 5319004 # Number of squashed operands that are examined and possibly removed from graph 435system.cpu.iq.iqSquashedNonSpecRemoved 1547012 # Number of squashed non-spec instructions that were removed 436system.cpu.iq.issued_per_cycle::samples 148422395 # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::mean 0.407841 # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::stdev 1.141989 # Number of insts issued each cycle | 396system.cpu.fetch.rateDist::total 118425370 # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.branchRate 0.157274 # Number of branch fetches per cycle 398system.cpu.fetch.rate 0.689084 # Number of inst fetches per cycle 399system.cpu.decode.IdleCycles 24239485 # Number of cycles decode is idle 400system.cpu.decode.BlockedCycles 81100635 # Number of cycles decode is blocked 401system.cpu.decode.RunCycles 10246732 # Number of cycles decode is running 402system.cpu.decode.UnblockCycles 2034421 # Number of cycles decode is unblocking 403system.cpu.decode.SquashCycles 804096 # Number of cycles decode is squashing 404system.cpu.decode.BranchResolved 734883 # Number of times decode resolved a branch 405system.cpu.decode.BranchMispred 35786 # Number of times decode detected a branch misprediction 406system.cpu.decode.DecodedInsts 73972445 # Number of instructions handled by decode 407system.cpu.decode.SquashedInsts 113808 # Number of squashed instructions handled by decode 408system.cpu.rename.SquashCycles 804096 # Number of cycles rename is squashing 409system.cpu.rename.IdleCycles 25248689 # Number of cycles rename is idle 410system.cpu.rename.BlockCycles 52456334 # Number of cycles rename is blocking 411system.cpu.rename.serializeStallCycles 19565246 # count of cycles rename stalled for serializing inst 412system.cpu.rename.RunCycles 11202200 # Number of cycles rename is running 413system.cpu.rename.UnblockCycles 9148803 # Number of cycles rename is unblocking 414system.cpu.rename.RenamedInsts 70966243 # Number of instructions processed by rename 415system.cpu.rename.ROBFullEvents 196842 # Number of times rename has blocked due to ROB full 416system.cpu.rename.IQFullEvents 2117370 # Number of times rename has blocked due to IQ full 417system.cpu.rename.LQFullEvents 228092 # Number of times rename has blocked due to LQ full 418system.cpu.rename.SQFullEvents 4881037 # Number of times rename has blocked due to SQ full 419system.cpu.rename.RenamedOperands 47806174 # Number of destination operands rename has renamed 420system.cpu.rename.RenameLookups 85505184 # Number of register rename lookups that rename has made 421system.cpu.rename.int_rename_lookups 85324382 # Number of integer rename lookups 422system.cpu.rename.fp_rename_lookups 168350 # Number of floating rename lookups 423system.cpu.rename.CommittedMaps 38176913 # Number of HB maps that are committed 424system.cpu.rename.UndoneMaps 9629253 # Number of HB maps that are undone due to squashing 425system.cpu.rename.serializingInsts 1728484 # count of serializing insts renamed 426system.cpu.rename.tempSerializingInsts 276268 # count of temporary serializing insts renamed 427system.cpu.rename.skidInsts 13926032 # count of insts added to the skid buffer 428system.cpu.memDep0.insertedLoads 11656323 # Number of loads inserted to the mem dependence unit. 429system.cpu.memDep0.insertedStores 7221031 # Number of stores inserted to the mem dependence unit. 430system.cpu.memDep0.conflictingLoads 1724354 # Number of conflicting loads. 431system.cpu.memDep0.conflictingStores 1093863 # Number of conflicting stores. 432system.cpu.iq.iqInstsAdded 62666856 # Number of instructions added to the IQ (excludes non-spec) 433system.cpu.iq.iqNonSpecInstsAdded 2206869 # Number of non-speculative instructions added to the IQ 434system.cpu.iq.iqInstsIssued 60507866 # Number of instructions issued 435system.cpu.iq.iqSquashedInstsIssued 96262 # Number of squashed instructions issued 436system.cpu.iq.iqSquashedInstsExamined 11897215 # Number of squashed instructions iterated over during squash; mainly for profiling 437system.cpu.iq.iqSquashedOperandsExamined 5284366 # Number of squashed operands that are examined and possibly removed from graph 438system.cpu.iq.iqSquashedNonSpecRemoved 1545682 # Number of squashed non-spec instructions that were removed 439system.cpu.iq.issued_per_cycle::samples 118425370 # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::mean 0.510937 # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::stdev 1.257755 # Number of insts issued each cycle |
| 439system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 442system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 440system.cpu.iq.issued_per_cycle::0 123871811 83.46% 83.46% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::1 10428219 7.03% 90.49% # Number of insts issued each cycle 442system.cpu.iq.issued_per_cycle::2 4419616 2.98% 93.46% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::3 3188761 2.15% 95.61% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::4 3243069 2.19% 97.80% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::5 1605515 1.08% 98.88% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::6 1096686 0.74% 99.62% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::7 430660 0.29% 99.91% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::8 138058 0.09% 100.00% # Number of insts issued each cycle | 443system.cpu.iq.issued_per_cycle::0 93896241 79.29% 79.29% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::1 10410761 8.79% 88.08% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::2 4424184 3.74% 91.81% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::3 3178503 2.68% 94.50% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::4 3240709 2.74% 97.23% # Number of insts issued each cycle 448system.cpu.iq.issued_per_cycle::5 1606797 1.36% 98.59% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::6 1097474 0.93% 99.52% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::7 434045 0.37% 99.88% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::8 136656 0.12% 100.00% # Number of insts issued each cycle |
| 449system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 452system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 452system.cpu.iq.issued_per_cycle::total 148422395 # Number of insts issued each cycle | 455system.cpu.iq.issued_per_cycle::total 118425370 # Number of insts issued each cycle |
| 453system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 456system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 454system.cpu.iq.fu_full::IntAlu 206261 16.62% 16.62% # attempts to use FU when none available 455system.cpu.iq.fu_full::IntMult 0 0.00% 16.62% # attempts to use FU when none available 456system.cpu.iq.fu_full::IntDiv 0 0.00% 16.62% # attempts to use FU when none available 457system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.62% # attempts to use FU when none available 458system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.62% # attempts to use FU when none available 459system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.62% # attempts to use FU when none available 460system.cpu.iq.fu_full::FloatMult 0 0.00% 16.62% # attempts to use FU when none available 461system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.62% # attempts to use FU when none available 462system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.62% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.62% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.62% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.62% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.62% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.62% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.62% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdMult 0 0.00% 16.62% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.62% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdShift 0 0.00% 16.62% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.62% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.62% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.62% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.62% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.62% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.62% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.62% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.62% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.62% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.62% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.62% # attempts to use FU when none available 483system.cpu.iq.fu_full::MemRead 637065 51.34% 67.96% # attempts to use FU when none available 484system.cpu.iq.fu_full::MemWrite 397617 32.04% 100.00% # attempts to use FU when none available | 457system.cpu.iq.fu_full::IntAlu 206587 16.63% 16.63% # attempts to use FU when none available 458system.cpu.iq.fu_full::IntMult 0 0.00% 16.63% # attempts to use FU when none available 459system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available 460system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available 461system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available 462system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available 463system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available 464system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available 465system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available 486system.cpu.iq.fu_full::MemRead 638209 51.38% 68.02% # attempts to use FU when none available 487system.cpu.iq.fu_full::MemWrite 397270 31.98% 100.00% # attempts to use FU when none available |
| 485system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 486system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 488system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 489system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 487system.cpu.iq.FU_type_0::No_OpClass 7280 0.01% 0.01% # Type of FU issued 488system.cpu.iq.FU_type_0::IntAlu 40910867 67.58% 67.60% # Type of FU issued 489system.cpu.iq.FU_type_0::IntMult 62087 0.10% 67.70% # Type of FU issued | 490system.cpu.iq.FU_type_0::No_OpClass 7277 0.01% 0.01% # Type of FU issued 491system.cpu.iq.FU_type_0::IntAlu 40893641 67.58% 67.60% # Type of FU issued 492system.cpu.iq.FU_type_0::IntMult 62155 0.10% 67.70% # Type of FU issued |
| 490system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued | 493system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued |
| 491system.cpu.iq.FU_type_0::FloatAdd 38559 0.06% 67.76% # Type of FU issued | 494system.cpu.iq.FU_type_0::FloatAdd 38558 0.06% 67.76% # Type of FU issued |
| 492system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 493system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 494system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 495system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued 496system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 509system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued | 495system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 496system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 497system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 498system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued 499system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 512system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued |
| 517system.cpu.iq.FU_type_0::MemRead 11677582 19.29% 87.06% # Type of FU issued 518system.cpu.iq.FU_type_0::MemWrite 6883616 11.37% 98.43% # Type of FU issued 519system.cpu.iq.FU_type_0::IprAccess 949158 1.57% 100.00% # Type of FU issued | 520system.cpu.iq.FU_type_0::MemRead 11671611 19.29% 87.06% # Type of FU issued 521system.cpu.iq.FU_type_0::MemWrite 6881999 11.37% 98.43% # Type of FU issued 522system.cpu.iq.FU_type_0::IprAccess 948989 1.57% 100.00% # Type of FU issued |
| 520system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 523system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 521system.cpu.iq.FU_type_0::total 60532785 # Type of FU issued 522system.cpu.iq.rate 0.390112 # Inst issue rate 523system.cpu.iq.fu_busy_cnt 1240943 # FU busy when requested 524system.cpu.iq.fu_busy_rate 0.020500 # FU busy rate (busy events/executed inst) 525system.cpu.iq.int_inst_queue_reads 270086631 # Number of integer instruction queue reads 526system.cpu.iq.int_inst_queue_writes 76534291 # Number of integer instruction queue writes 527system.cpu.iq.int_inst_queue_wakeup_accesses 58304379 # Number of integer instruction queue wakeup accesses 528system.cpu.iq.fp_inst_queue_reads 736956 # Number of floating instruction queue reads 529system.cpu.iq.fp_inst_queue_writes 359180 # Number of floating instruction queue writes 530system.cpu.iq.fp_inst_queue_wakeup_accesses 336827 # Number of floating instruction queue wakeup accesses 531system.cpu.iq.int_alu_accesses 61370896 # Number of integer alu accesses 532system.cpu.iq.fp_alu_accesses 395552 # Number of floating point alu accesses 533system.cpu.iew.lsq.thread0.forwLoads 686477 # Number of loads that had data forwarded from stores | 524system.cpu.iq.FU_type_0::total 60507866 # Type of FU issued 525system.cpu.iq.rate 0.487021 # Inst issue rate 526system.cpu.iq.fu_busy_cnt 1242066 # FU busy when requested 527system.cpu.iq.fu_busy_rate 0.020527 # FU busy rate (busy events/executed inst) 528system.cpu.iq.int_inst_queue_reads 240042364 # Number of integer instruction queue reads 529system.cpu.iq.int_inst_queue_writes 76433076 # Number of integer instruction queue writes 530system.cpu.iq.int_inst_queue_wakeup_accesses 58286910 # Number of integer instruction queue wakeup accesses 531system.cpu.iq.fp_inst_queue_reads 737065 # Number of floating instruction queue reads 532system.cpu.iq.fp_inst_queue_writes 359346 # Number of floating instruction queue writes 533system.cpu.iq.fp_inst_queue_wakeup_accesses 336745 # Number of floating instruction queue wakeup accesses 534system.cpu.iq.int_alu_accesses 61347086 # Number of integer alu accesses 535system.cpu.iq.fp_alu_accesses 395569 # Number of floating point alu accesses 536system.cpu.iew.lsq.thread0.forwLoads 690461 # Number of loads that had data forwarded from stores |
| 534system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 537system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 535system.cpu.iew.lsq.thread0.squashedLoads 2574541 # Number of loads squashed 536system.cpu.iew.lsq.thread0.ignoredResponses 4210 # Number of memory responses ignored because the instruction is squashed 537system.cpu.iew.lsq.thread0.memOrderViolation 22293 # Number of memory ordering violations 538system.cpu.iew.lsq.thread0.squashedStores 843973 # Number of stores squashed | 538system.cpu.iew.lsq.thread0.squashedLoads 2564224 # Number of loads squashed 539system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed 540system.cpu.iew.lsq.thread0.memOrderViolation 22069 # Number of memory ordering violations 541system.cpu.iew.lsq.thread0.squashedStores 843181 # Number of stores squashed |
| 539system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 540system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 542system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 543system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 541system.cpu.iew.lsq.thread0.rescheduledLoads 18024 # Number of loads that were rescheduled 542system.cpu.iew.lsq.thread0.cacheBlocked 466103 # Number of times an access to memory failed due to the cache being blocked | 544system.cpu.iew.lsq.thread0.rescheduledLoads 17987 # Number of loads that were rescheduled 545system.cpu.iew.lsq.thread0.cacheBlocked 463704 # Number of times an access to memory failed due to the cache being blocked |
| 543system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 546system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 544system.cpu.iew.iewSquashCycles 806059 # Number of cycles IEW is squashing 545system.cpu.iew.iewBlockCycles 75493298 # Number of cycles IEW is blocking 546system.cpu.iew.iewUnblockCycles 1202730 # Number of cycles IEW is unblocking 547system.cpu.iew.iewDispatchedInsts 68906340 # Number of instructions dispatched to IQ 548system.cpu.iew.iewDispSquashedInsts 204916 # Number of squashed instructions skipped by dispatch 549system.cpu.iew.iewDispLoadInsts 11667584 # Number of dispatched load instructions 550system.cpu.iew.iewDispStoreInsts 7222268 # Number of dispatched store instructions 551system.cpu.iew.iewDispNonSpecInsts 1958885 # Number of dispatched non-speculative instructions 552system.cpu.iew.iewIQFullEvents 46577 # Number of times the IQ has become full, causing a stall 553system.cpu.iew.iewLSQFullEvents 953145 # Number of times the LSQ has become full, causing a stall 554system.cpu.iew.memOrderViolationEvents 22293 # Number of memory order violations 555system.cpu.iew.predictedTakenIncorrect 228745 # Number of branches that were predicted taken incorrectly 556system.cpu.iew.predictedNotTakenIncorrect 630471 # Number of branches that were predicted not taken incorrectly 557system.cpu.iew.branchMispredicts 859216 # Number of branch mispredicts detected at execute 558system.cpu.iew.iewExecutedInsts 59676170 # Number of executed instructions 559system.cpu.iew.iewExecLoadInsts 11213777 # Number of load instructions executed 560system.cpu.iew.iewExecSquashedInsts 856614 # Number of squashed instructions skipped in execute | 547system.cpu.iew.iewSquashCycles 804096 # Number of cycles IEW is squashing 548system.cpu.iew.iewBlockCycles 49123510 # Number of cycles IEW is blocking 549system.cpu.iew.iewUnblockCycles 920451 # Number of cycles IEW is unblocking 550system.cpu.iew.iewDispatchedInsts 68850753 # Number of instructions dispatched to IQ 551system.cpu.iew.iewDispSquashedInsts 204809 # Number of squashed instructions skipped by dispatch 552system.cpu.iew.iewDispLoadInsts 11656323 # Number of dispatched load instructions 553system.cpu.iew.iewDispStoreInsts 7221031 # Number of dispatched store instructions 554system.cpu.iew.iewDispNonSpecInsts 1958834 # Number of dispatched non-speculative instructions 555system.cpu.iew.iewIQFullEvents 45972 # Number of times the IQ has become full, causing a stall 556system.cpu.iew.iewLSQFullEvents 671584 # Number of times the LSQ has become full, causing a stall 557system.cpu.iew.memOrderViolationEvents 22069 # Number of memory order violations 558system.cpu.iew.predictedTakenIncorrect 229357 # Number of branches that were predicted taken incorrectly 559system.cpu.iew.predictedNotTakenIncorrect 628132 # Number of branches that were predicted not taken incorrectly 560system.cpu.iew.branchMispredicts 857489 # Number of branch mispredicts detected at execute 561system.cpu.iew.iewExecutedInsts 59656852 # Number of executed instructions 562system.cpu.iew.iewExecLoadInsts 11208773 # Number of load instructions executed 563system.cpu.iew.iewExecSquashedInsts 851013 # Number of squashed instructions skipped in execute |
| 561system.cpu.iew.exec_swp 0 # number of swp insts executed | 564system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 562system.cpu.iew.exec_nop 3978939 # number of nop insts executed 563system.cpu.iew.exec_refs 18023142 # number of memory reference insts executed 564system.cpu.iew.exec_branches 9384066 # Number of branches executed 565system.cpu.iew.exec_stores 6809365 # Number of stores executed 566system.cpu.iew.exec_rate 0.384592 # Inst execution rate 567system.cpu.iew.wb_sent 58885265 # cumulative count of insts sent to commit 568system.cpu.iew.wb_count 58641206 # cumulative count of insts written-back 569system.cpu.iew.wb_producers 29760600 # num instructions producing a value 570system.cpu.iew.wb_consumers 41260135 # num instructions consuming a value 571system.cpu.iew.wb_rate 0.377922 # insts written-back per cycle 572system.cpu.iew.wb_fanout 0.721292 # average fanout of values written-back 573system.cpu.commit.commitSquashedInsts 12542077 # The number of squashed insts skipped by commit 574system.cpu.commit.commitNonSpecStalls 661272 # The number of times commit has been forced to stall to communicate backwards 575system.cpu.commit.branchMispredicts 769434 # The number of times a branch was mispredicted 576system.cpu.commit.committed_per_cycle::samples 146251910 # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::mean 0.384089 # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::stdev 1.283290 # Number of insts commited each cycle | 565system.cpu.iew.exec_nop 3977028 # number of nop insts executed 566system.cpu.iew.exec_refs 18015122 # number of memory reference insts executed 567system.cpu.iew.exec_branches 9379233 # Number of branches executed 568system.cpu.iew.exec_stores 6806349 # Number of stores executed 569system.cpu.iew.exec_rate 0.480171 # Inst execution rate 570system.cpu.iew.wb_sent 58867691 # cumulative count of insts sent to commit 571system.cpu.iew.wb_count 58623655 # cumulative count of insts written-back 572system.cpu.iew.wb_producers 29756177 # num instructions producing a value 573system.cpu.iew.wb_consumers 41250197 # num instructions consuming a value 574system.cpu.iew.wb_rate 0.471855 # insts written-back per cycle 575system.cpu.iew.wb_fanout 0.721358 # average fanout of values written-back 576system.cpu.commit.commitSquashedInsts 12492004 # The number of squashed insts skipped by commit 577system.cpu.commit.commitNonSpecStalls 661187 # The number of times commit has been forced to stall to communicate backwards 578system.cpu.commit.branchMispredicts 767634 # The number of times a branch was mispredicted 579system.cpu.commit.committed_per_cycle::samples 116265516 # Number of insts commited each cycle 580system.cpu.commit.committed_per_cycle::mean 0.483093 # Number of insts commited each cycle 581system.cpu.commit.committed_per_cycle::stdev 1.421972 # Number of insts commited each cycle |
| 579system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 582system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 580system.cpu.commit.committed_per_cycle::0 126403677 86.43% 86.43% # Number of insts commited each cycle 581system.cpu.commit.committed_per_cycle::1 7969213 5.45% 91.88% # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::2 4187918 2.86% 94.74% # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::3 2256490 1.54% 96.28% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::4 1756984 1.20% 97.49% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::5 633259 0.43% 97.92% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::6 482491 0.33% 98.25% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::7 524954 0.36% 98.61% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::8 2036924 1.39% 100.00% # Number of insts commited each cycle | 583system.cpu.commit.committed_per_cycle::0 96403146 82.92% 82.92% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::1 7978599 6.86% 89.78% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::2 4192375 3.61% 93.38% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::3 2264506 1.95% 95.33% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::4 1757271 1.51% 96.84% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::5 632678 0.54% 97.39% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::6 482043 0.41% 97.80% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::7 513720 0.44% 98.24% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::8 2041178 1.76% 100.00% # Number of insts commited each cycle |
| 589system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 592system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 592system.cpu.commit.committed_per_cycle::total 146251910 # Number of insts commited each cycle 593system.cpu.commit.committedInsts 56173766 # Number of instructions committed 594system.cpu.commit.committedOps 56173766 # Number of ops (including micro ops) committed | 595system.cpu.commit.committed_per_cycle::total 116265516 # Number of insts commited each cycle 596system.cpu.commit.committedInsts 56167063 # Number of instructions committed 597system.cpu.commit.committedOps 56167063 # Number of ops (including micro ops) committed |
| 595system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 598system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 596system.cpu.commit.refs 15471338 # Number of memory references committed 597system.cpu.commit.loads 9093043 # Number of loads committed 598system.cpu.commit.membars 226379 # Number of memory barriers committed 599system.cpu.commit.branches 8441154 # Number of branches committed | 599system.cpu.commit.refs 15469949 # Number of memory references committed 600system.cpu.commit.loads 9092099 # Number of loads committed 601system.cpu.commit.membars 226348 # Number of memory barriers committed 602system.cpu.commit.branches 8440307 # Number of branches committed |
| 600system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 603system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 601system.cpu.commit.int_insts 52023017 # Number of committed integer instructions. 602system.cpu.commit.function_calls 740601 # Number of function calls committed. 603system.cpu.commit.op_class_0::No_OpClass 3198096 5.69% 5.69% # Class of committed instruction 604system.cpu.commit.op_class_0::IntAlu 36220454 64.48% 70.17% # Class of committed instruction 605system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.28% # Class of committed instruction | 604system.cpu.commit.int_insts 52016709 # Number of committed integer instructions. 605system.cpu.commit.function_calls 740521 # Number of function calls committed. 606system.cpu.commit.op_class_0::No_OpClass 3197831 5.69% 5.69% # Class of committed instruction 607system.cpu.commit.op_class_0::IntAlu 36215597 64.48% 70.17% # Class of committed instruction 608system.cpu.commit.op_class_0::IntMult 60674 0.11% 70.28% # Class of committed instruction |
| 606system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 607system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 608system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 609system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 610system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 611system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 612system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 625system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 626system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 627system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 630system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 631system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction | 609system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 610system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 611system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 612system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 613system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 614system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 615system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 628system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 630system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 631system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 634system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction |
| 633system.cpu.commit.op_class_0::MemRead 9319422 16.59% 86.95% # Class of committed instruction 634system.cpu.commit.op_class_0::MemWrite 6384252 11.37% 98.31% # Class of committed instruction 635system.cpu.commit.op_class_0::IprAccess 949158 1.69% 100.00% # Class of committed instruction | 636system.cpu.commit.op_class_0::MemRead 9318447 16.59% 86.94% # Class of committed instruction 637system.cpu.commit.op_class_0::MemWrite 6383804 11.37% 98.31% # Class of committed instruction 638system.cpu.commit.op_class_0::IprAccess 948989 1.69% 100.00% # Class of committed instruction |
| 636system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 639system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 637system.cpu.commit.op_class_0::total 56173766 # Class of committed instruction 638system.cpu.commit.bw_lim_events 2036924 # number cycles where commit BW limit reached 639system.cpu.rob.rob_reads 212681294 # The number of ROB reads 640system.cpu.rob.rob_writes 139606986 # The number of ROB writes 641system.cpu.timesIdled 557347 # Number of times that the entire CPU went into an idle state and unscheduled itself 642system.cpu.idleCycles 6745166 # Total number of cycles that the CPU has spent unscheduled due to idling 643system.cpu.quiesceCycles 3598421416 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 644system.cpu.committedInsts 52982943 # Number of Instructions Simulated 645system.cpu.committedOps 52982943 # Number of Ops (including micro ops) Simulated 646system.cpu.cpi 2.928632 # CPI: Cycles Per Instruction 647system.cpu.cpi_total 2.928632 # CPI: Total CPI of All Threads 648system.cpu.ipc 0.341456 # IPC: Instructions Per Cycle 649system.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads 650system.cpu.int_regfile_reads 77864960 # number of integer regfile reads 651system.cpu.int_regfile_writes 42584488 # number of integer regfile writes 652system.cpu.fp_regfile_reads 166613 # number of floating regfile reads 653system.cpu.fp_regfile_writes 175794 # number of floating regfile writes 654system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads 655system.cpu.misc_regfile_writes 939529 # number of misc regfile writes 656system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 657system.cpu.dcache.tags.replacements 1405900 # number of replacements 658system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use 659system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks. 660system.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks. 661system.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks. 662system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 663system.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor 664system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 665system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy | 640system.cpu.commit.op_class_0::total 56167063 # Class of committed instruction 641system.cpu.commit.bw_lim_events 2041178 # number cycles where commit BW limit reached 642system.cpu.rob.rob_reads 182633884 # The number of ROB reads 643system.cpu.rob.rob_writes 139481914 # The number of ROB writes 644system.cpu.timesIdled 555871 # Number of times that the entire CPU went into an idle state and unscheduled itself 645system.cpu.idleCycles 5815411 # Total number of cycles that the CPU has spent unscheduled due to idling 646system.cpu.quiesceCycles 3599843346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 647system.cpu.committedInsts 52976505 # Number of Instructions Simulated 648system.cpu.committedOps 52976505 # Number of Ops (including micro ops) Simulated 649system.cpu.cpi 2.345205 # CPI: Cycles Per Instruction 650system.cpu.cpi_total 2.345205 # CPI: Total CPI of All Threads 651system.cpu.ipc 0.426402 # IPC: Instructions Per Cycle 652system.cpu.ipc_total 0.426402 # IPC: Total IPC of All Threads 653system.cpu.int_regfile_reads 77842014 # number of integer regfile reads 654system.cpu.int_regfile_writes 42572961 # number of integer regfile writes 655system.cpu.fp_regfile_reads 166584 # number of floating regfile reads 656system.cpu.fp_regfile_writes 175742 # number of floating regfile writes 657system.cpu.misc_regfile_reads 2001057 # number of misc regfile reads 658system.cpu.misc_regfile_writes 939419 # number of misc regfile writes 659system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 660system.cpu.dcache.tags.replacements 1405448 # number of replacements 661system.cpu.dcache.tags.tagsinuse 511.994324 # Cycle average of tags in use 662system.cpu.dcache.tags.total_refs 12624146 # Total number of references to valid blocks. 663system.cpu.dcache.tags.sampled_refs 1405960 # Sample count of references to valid blocks. 664system.cpu.dcache.tags.avg_refs 8.979022 # Average number of references to valid blocks. 665system.cpu.dcache.tags.warmup_cycle 26885500 # Cycle when the warmup percentage was hit. 666system.cpu.dcache.tags.occ_blocks::cpu.data 511.994324 # Average occupied blocks per requestor 667system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 668system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy |
| 666system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 669system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 667system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id 668system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 669system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id | 670system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 671system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id 672system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id |
| 670system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 673system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 671system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses 672system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses 673system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 674system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits 675system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits 676system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits 677system.cpu.dcache.WriteReq_hits::total 4181578 # number of WriteReq hits 678system.cpu.dcache.LoadLockedReq_hits::cpu.data 212474 # number of LoadLockedReq hits 679system.cpu.dcache.LoadLockedReq_hits::total 212474 # number of LoadLockedReq hits 680system.cpu.dcache.StoreCondReq_hits::cpu.data 215675 # number of StoreCondReq hits 681system.cpu.dcache.StoreCondReq_hits::total 215675 # number of StoreCondReq hits 682system.cpu.dcache.demand_hits::cpu.data 12199345 # number of demand (read+write) hits 683system.cpu.dcache.demand_hits::total 12199345 # number of demand (read+write) hits 684system.cpu.dcache.overall_hits::cpu.data 12199345 # number of overall hits 685system.cpu.dcache.overall_hits::total 12199345 # number of overall hits 686system.cpu.dcache.ReadReq_misses::cpu.data 1817411 # number of ReadReq misses 687system.cpu.dcache.ReadReq_misses::total 1817411 # number of ReadReq misses 688system.cpu.dcache.WriteReq_misses::cpu.data 1966241 # number of WriteReq misses 689system.cpu.dcache.WriteReq_misses::total 1966241 # number of WriteReq misses 690system.cpu.dcache.LoadLockedReq_misses::cpu.data 23192 # number of LoadLockedReq misses 691system.cpu.dcache.LoadLockedReq_misses::total 23192 # number of LoadLockedReq misses 692system.cpu.dcache.StoreCondReq_misses::cpu.data 96 # number of StoreCondReq misses 693system.cpu.dcache.StoreCondReq_misses::total 96 # number of StoreCondReq misses 694system.cpu.dcache.demand_misses::cpu.data 3783652 # number of demand (read+write) misses 695system.cpu.dcache.demand_misses::total 3783652 # number of demand (read+write) misses 696system.cpu.dcache.overall_misses::cpu.data 3783652 # number of overall misses 697system.cpu.dcache.overall_misses::total 3783652 # number of overall misses 698system.cpu.dcache.ReadReq_miss_latency::cpu.data 57696836500 # number of ReadReq miss cycles 699system.cpu.dcache.ReadReq_miss_latency::total 57696836500 # number of ReadReq miss cycles 700system.cpu.dcache.WriteReq_miss_latency::cpu.data 116764719993 # number of WriteReq miss cycles 701system.cpu.dcache.WriteReq_miss_latency::total 116764719993 # number of WriteReq miss cycles 702system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 411714000 # number of LoadLockedReq miss cycles 703system.cpu.dcache.LoadLockedReq_miss_latency::total 411714000 # number of LoadLockedReq miss cycles 704system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1875000 # number of StoreCondReq miss cycles 705system.cpu.dcache.StoreCondReq_miss_latency::total 1875000 # number of StoreCondReq miss cycles 706system.cpu.dcache.demand_miss_latency::cpu.data 174461556493 # number of demand (read+write) miss cycles 707system.cpu.dcache.demand_miss_latency::total 174461556493 # number of demand (read+write) miss cycles 708system.cpu.dcache.overall_miss_latency::cpu.data 174461556493 # number of overall miss cycles 709system.cpu.dcache.overall_miss_latency::total 174461556493 # number of overall miss cycles 710system.cpu.dcache.ReadReq_accesses::cpu.data 9835178 # number of ReadReq accesses(hits+misses) 711system.cpu.dcache.ReadReq_accesses::total 9835178 # number of ReadReq accesses(hits+misses) 712system.cpu.dcache.WriteReq_accesses::cpu.data 6147819 # number of WriteReq accesses(hits+misses) 713system.cpu.dcache.WriteReq_accesses::total 6147819 # number of WriteReq accesses(hits+misses) 714system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235666 # number of LoadLockedReq accesses(hits+misses) 715system.cpu.dcache.LoadLockedReq_accesses::total 235666 # number of LoadLockedReq accesses(hits+misses) 716system.cpu.dcache.StoreCondReq_accesses::cpu.data 215771 # number of StoreCondReq accesses(hits+misses) 717system.cpu.dcache.StoreCondReq_accesses::total 215771 # number of StoreCondReq accesses(hits+misses) 718system.cpu.dcache.demand_accesses::cpu.data 15982997 # number of demand (read+write) accesses 719system.cpu.dcache.demand_accesses::total 15982997 # number of demand (read+write) accesses 720system.cpu.dcache.overall_accesses::cpu.data 15982997 # number of overall (read+write) accesses 721system.cpu.dcache.overall_accesses::total 15982997 # number of overall (read+write) accesses 722system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184787 # miss rate for ReadReq accesses 723system.cpu.dcache.ReadReq_miss_rate::total 0.184787 # miss rate for ReadReq accesses 724system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319827 # miss rate for WriteReq accesses 725system.cpu.dcache.WriteReq_miss_rate::total 0.319827 # miss rate for WriteReq accesses 726system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098410 # miss rate for LoadLockedReq accesses 727system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098410 # miss rate for LoadLockedReq accesses 728system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000445 # miss rate for StoreCondReq accesses 729system.cpu.dcache.StoreCondReq_miss_rate::total 0.000445 # miss rate for StoreCondReq accesses 730system.cpu.dcache.demand_miss_rate::cpu.data 0.236730 # miss rate for demand accesses 731system.cpu.dcache.demand_miss_rate::total 0.236730 # miss rate for demand accesses 732system.cpu.dcache.overall_miss_rate::cpu.data 0.236730 # miss rate for overall accesses 733system.cpu.dcache.overall_miss_rate::total 0.236730 # miss rate for overall accesses 734system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31746.719097 # average ReadReq miss latency 735system.cpu.dcache.ReadReq_avg_miss_latency::total 31746.719097 # average ReadReq miss latency 736system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59384.744796 # average WriteReq miss latency 737system.cpu.dcache.WriteReq_avg_miss_latency::total 59384.744796 # average WriteReq miss latency 738system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17752.414626 # average LoadLockedReq miss latency 739system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17752.414626 # average LoadLockedReq miss latency 740system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19531.250000 # average StoreCondReq miss latency 741system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19531.250000 # average StoreCondReq miss latency 742system.cpu.dcache.demand_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency 743system.cpu.dcache.demand_avg_miss_latency::total 46109.302994 # average overall miss latency 744system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency 745system.cpu.dcache.overall_avg_miss_latency::total 46109.302994 # average overall miss latency 746system.cpu.dcache.blocked_cycles::no_mshrs 7149027 # number of cycles access was blocked 747system.cpu.dcache.blocked_cycles::no_targets 5119 # number of cycles access was blocked 748system.cpu.dcache.blocked::no_mshrs 133846 # number of cycles access was blocked 749system.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked 750system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked 751system.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked 752system.cpu.dcache.writebacks::writebacks 843569 # number of writebacks 753system.cpu.dcache.writebacks::total 843569 # number of writebacks 754system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # number of ReadReq MSHR hits 755system.cpu.dcache.ReadReq_mshr_hits::total 717041 # number of ReadReq MSHR hits 756system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676919 # number of WriteReq MSHR hits 757system.cpu.dcache.WriteReq_mshr_hits::total 1676919 # number of WriteReq MSHR hits 758system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6351 # number of LoadLockedReq MSHR hits 759system.cpu.dcache.LoadLockedReq_mshr_hits::total 6351 # number of LoadLockedReq MSHR hits 760system.cpu.dcache.demand_mshr_hits::cpu.data 2393960 # number of demand (read+write) MSHR hits 761system.cpu.dcache.demand_mshr_hits::total 2393960 # number of demand (read+write) MSHR hits 762system.cpu.dcache.overall_mshr_hits::cpu.data 2393960 # number of overall MSHR hits 763system.cpu.dcache.overall_mshr_hits::total 2393960 # number of overall MSHR hits 764system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100370 # number of ReadReq MSHR misses 765system.cpu.dcache.ReadReq_mshr_misses::total 1100370 # number of ReadReq MSHR misses 766system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289322 # number of WriteReq MSHR misses 767system.cpu.dcache.WriteReq_mshr_misses::total 289322 # number of WriteReq MSHR misses 768system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16841 # number of LoadLockedReq MSHR misses 769system.cpu.dcache.LoadLockedReq_mshr_misses::total 16841 # number of LoadLockedReq MSHR misses 770system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 96 # number of StoreCondReq MSHR misses 771system.cpu.dcache.StoreCondReq_mshr_misses::total 96 # number of StoreCondReq MSHR misses 772system.cpu.dcache.demand_mshr_misses::cpu.data 1389692 # number of demand (read+write) MSHR misses 773system.cpu.dcache.demand_mshr_misses::total 1389692 # number of demand (read+write) MSHR misses 774system.cpu.dcache.overall_mshr_misses::cpu.data 1389692 # number of overall MSHR misses 775system.cpu.dcache.overall_mshr_misses::total 1389692 # number of overall MSHR misses | 674system.cpu.dcache.tags.tag_accesses 67117469 # Number of tag accesses 675system.cpu.dcache.tags.data_accesses 67117469 # Number of data accesses 676system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 677system.cpu.dcache.ReadReq_hits::cpu.data 8015814 # number of ReadReq hits 678system.cpu.dcache.ReadReq_hits::total 8015814 # number of ReadReq hits 679system.cpu.dcache.WriteReq_hits::cpu.data 4179783 # number of WriteReq hits 680system.cpu.dcache.WriteReq_hits::total 4179783 # number of WriteReq hits 681system.cpu.dcache.LoadLockedReq_hits::cpu.data 212605 # number of LoadLockedReq hits 682system.cpu.dcache.LoadLockedReq_hits::total 212605 # number of LoadLockedReq hits 683system.cpu.dcache.StoreCondReq_hits::cpu.data 215671 # number of StoreCondReq hits 684system.cpu.dcache.StoreCondReq_hits::total 215671 # number of StoreCondReq hits 685system.cpu.dcache.demand_hits::cpu.data 12195597 # number of demand (read+write) hits 686system.cpu.dcache.demand_hits::total 12195597 # number of demand (read+write) hits 687system.cpu.dcache.overall_hits::cpu.data 12195597 # number of overall hits 688system.cpu.dcache.overall_hits::total 12195597 # number of overall hits 689system.cpu.dcache.ReadReq_misses::cpu.data 1813103 # number of ReadReq misses 690system.cpu.dcache.ReadReq_misses::total 1813103 # number of ReadReq misses 691system.cpu.dcache.WriteReq_misses::cpu.data 1967603 # number of WriteReq misses 692system.cpu.dcache.WriteReq_misses::total 1967603 # number of WriteReq misses 693system.cpu.dcache.LoadLockedReq_misses::cpu.data 23208 # number of LoadLockedReq misses 694system.cpu.dcache.LoadLockedReq_misses::total 23208 # number of LoadLockedReq misses 695system.cpu.dcache.StoreCondReq_misses::cpu.data 90 # number of StoreCondReq misses 696system.cpu.dcache.StoreCondReq_misses::total 90 # number of StoreCondReq misses 697system.cpu.dcache.demand_misses::cpu.data 3780706 # number of demand (read+write) misses 698system.cpu.dcache.demand_misses::total 3780706 # number of demand (read+write) misses 699system.cpu.dcache.overall_misses::cpu.data 3780706 # number of overall misses 700system.cpu.dcache.overall_misses::total 3780706 # number of overall misses 701system.cpu.dcache.ReadReq_miss_latency::cpu.data 42125006500 # number of ReadReq miss cycles 702system.cpu.dcache.ReadReq_miss_latency::total 42125006500 # number of ReadReq miss cycles 703system.cpu.dcache.WriteReq_miss_latency::cpu.data 80961387023 # number of WriteReq miss cycles 704system.cpu.dcache.WriteReq_miss_latency::total 80961387023 # number of WriteReq miss cycles 705system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 351774000 # number of LoadLockedReq miss cycles 706system.cpu.dcache.LoadLockedReq_miss_latency::total 351774000 # number of LoadLockedReq miss cycles 707system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1258000 # number of StoreCondReq miss cycles 708system.cpu.dcache.StoreCondReq_miss_latency::total 1258000 # number of StoreCondReq miss cycles 709system.cpu.dcache.demand_miss_latency::cpu.data 123086393523 # number of demand (read+write) miss cycles 710system.cpu.dcache.demand_miss_latency::total 123086393523 # number of demand (read+write) miss cycles 711system.cpu.dcache.overall_miss_latency::cpu.data 123086393523 # number of overall miss cycles 712system.cpu.dcache.overall_miss_latency::total 123086393523 # number of overall miss cycles 713system.cpu.dcache.ReadReq_accesses::cpu.data 9828917 # number of ReadReq accesses(hits+misses) 714system.cpu.dcache.ReadReq_accesses::total 9828917 # number of ReadReq accesses(hits+misses) 715system.cpu.dcache.WriteReq_accesses::cpu.data 6147386 # number of WriteReq accesses(hits+misses) 716system.cpu.dcache.WriteReq_accesses::total 6147386 # number of WriteReq accesses(hits+misses) 717system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235813 # number of LoadLockedReq accesses(hits+misses) 718system.cpu.dcache.LoadLockedReq_accesses::total 235813 # number of LoadLockedReq accesses(hits+misses) 719system.cpu.dcache.StoreCondReq_accesses::cpu.data 215761 # number of StoreCondReq accesses(hits+misses) 720system.cpu.dcache.StoreCondReq_accesses::total 215761 # number of StoreCondReq accesses(hits+misses) 721system.cpu.dcache.demand_accesses::cpu.data 15976303 # number of demand (read+write) accesses 722system.cpu.dcache.demand_accesses::total 15976303 # number of demand (read+write) accesses 723system.cpu.dcache.overall_accesses::cpu.data 15976303 # number of overall (read+write) accesses 724system.cpu.dcache.overall_accesses::total 15976303 # number of overall (read+write) accesses 725system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184466 # miss rate for ReadReq accesses 726system.cpu.dcache.ReadReq_miss_rate::total 0.184466 # miss rate for ReadReq accesses 727system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320071 # miss rate for WriteReq accesses 728system.cpu.dcache.WriteReq_miss_rate::total 0.320071 # miss rate for WriteReq accesses 729system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098417 # miss rate for LoadLockedReq accesses 730system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098417 # miss rate for LoadLockedReq accesses 731system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000417 # miss rate for StoreCondReq accesses 732system.cpu.dcache.StoreCondReq_miss_rate::total 0.000417 # miss rate for StoreCondReq accesses 733system.cpu.dcache.demand_miss_rate::cpu.data 0.236645 # miss rate for demand accesses 734system.cpu.dcache.demand_miss_rate::total 0.236645 # miss rate for demand accesses 735system.cpu.dcache.overall_miss_rate::cpu.data 0.236645 # miss rate for overall accesses 736system.cpu.dcache.overall_miss_rate::total 0.236645 # miss rate for overall accesses 737system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23233.653300 # average ReadReq miss latency 738system.cpu.dcache.ReadReq_avg_miss_latency::total 23233.653300 # average ReadReq miss latency 739system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41147.216701 # average WriteReq miss latency 740system.cpu.dcache.WriteReq_avg_miss_latency::total 41147.216701 # average WriteReq miss latency 741system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15157.445708 # average LoadLockedReq miss latency 742system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15157.445708 # average LoadLockedReq miss latency 743system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13977.777778 # average StoreCondReq miss latency 744system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13977.777778 # average StoreCondReq miss latency 745system.cpu.dcache.demand_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency 746system.cpu.dcache.demand_avg_miss_latency::total 32556.457319 # average overall miss latency 747system.cpu.dcache.overall_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency 748system.cpu.dcache.overall_avg_miss_latency::total 32556.457319 # average overall miss latency 749system.cpu.dcache.blocked_cycles::no_mshrs 4549830 # number of cycles access was blocked 750system.cpu.dcache.blocked_cycles::no_targets 3359 # number of cycles access was blocked 751system.cpu.dcache.blocked::no_mshrs 133574 # number of cycles access was blocked 752system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked 753system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.062243 # average number of cycles each access was blocked 754system.cpu.dcache.avg_blocked_cycles::no_targets 93.305556 # average number of cycles each access was blocked 755system.cpu.dcache.writebacks::writebacks 843871 # number of writebacks 756system.cpu.dcache.writebacks::total 843871 # number of writebacks 757system.cpu.dcache.ReadReq_mshr_hits::cpu.data 713283 # number of ReadReq MSHR hits 758system.cpu.dcache.ReadReq_mshr_hits::total 713283 # number of ReadReq MSHR hits 759system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1678038 # number of WriteReq MSHR hits 760system.cpu.dcache.WriteReq_mshr_hits::total 1678038 # number of WriteReq MSHR hits 761system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6508 # number of LoadLockedReq MSHR hits 762system.cpu.dcache.LoadLockedReq_mshr_hits::total 6508 # number of LoadLockedReq MSHR hits 763system.cpu.dcache.demand_mshr_hits::cpu.data 2391321 # number of demand (read+write) MSHR hits 764system.cpu.dcache.demand_mshr_hits::total 2391321 # number of demand (read+write) MSHR hits 765system.cpu.dcache.overall_mshr_hits::cpu.data 2391321 # number of overall MSHR hits 766system.cpu.dcache.overall_mshr_hits::total 2391321 # number of overall MSHR hits 767system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1099820 # number of ReadReq MSHR misses 768system.cpu.dcache.ReadReq_mshr_misses::total 1099820 # number of ReadReq MSHR misses 769system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289565 # number of WriteReq MSHR misses 770system.cpu.dcache.WriteReq_mshr_misses::total 289565 # number of WriteReq MSHR misses 771system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16700 # number of LoadLockedReq MSHR misses 772system.cpu.dcache.LoadLockedReq_mshr_misses::total 16700 # number of LoadLockedReq MSHR misses 773system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 90 # number of StoreCondReq MSHR misses 774system.cpu.dcache.StoreCondReq_mshr_misses::total 90 # number of StoreCondReq MSHR misses 775system.cpu.dcache.demand_mshr_misses::cpu.data 1389385 # number of demand (read+write) MSHR misses 776system.cpu.dcache.demand_mshr_misses::total 1389385 # number of demand (read+write) MSHR misses 777system.cpu.dcache.overall_mshr_misses::cpu.data 1389385 # number of overall MSHR misses 778system.cpu.dcache.overall_mshr_misses::total 1389385 # number of overall MSHR misses |
| 776system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 777system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 779system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 780system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 778system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 779system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 780system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 781system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses 782system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44732838000 # number of ReadReq MSHR miss cycles 783system.cpu.dcache.ReadReq_mshr_miss_latency::total 44732838000 # number of ReadReq MSHR miss cycles 784system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18336828964 # number of WriteReq MSHR miss cycles 785system.cpu.dcache.WriteReq_mshr_miss_latency::total 18336828964 # number of WriteReq MSHR miss cycles 786system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214607500 # number of LoadLockedReq MSHR miss cycles 787system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214607500 # number of LoadLockedReq MSHR miss cycles 788system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1779000 # number of StoreCondReq MSHR miss cycles 789system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1779000 # number of StoreCondReq MSHR miss cycles 790system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63069666964 # number of demand (read+write) MSHR miss cycles 791system.cpu.dcache.demand_mshr_miss_latency::total 63069666964 # number of demand (read+write) MSHR miss cycles 792system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63069666964 # number of overall MSHR miss cycles 793system.cpu.dcache.overall_mshr_miss_latency::total 63069666964 # number of overall MSHR miss cycles 794system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528639000 # number of ReadReq MSHR uncacheable cycles 795system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528639000 # number of ReadReq MSHR uncacheable cycles 796system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528639000 # number of overall MSHR uncacheable cycles 797system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528639000 # number of overall MSHR uncacheable cycles 798system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111881 # mshr miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111881 # mshr miss rate for ReadReq accesses 800system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047061 # mshr miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047061 # mshr miss rate for WriteReq accesses 802system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071461 # mshr miss rate for LoadLockedReq accesses 803system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071461 # mshr miss rate for LoadLockedReq accesses 804system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000445 # mshr miss rate for StoreCondReq accesses 805system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000445 # mshr miss rate for StoreCondReq accesses 806system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for demand accesses 807system.cpu.dcache.demand_mshr_miss_rate::total 0.086948 # mshr miss rate for demand accesses 808system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for overall accesses 809system.cpu.dcache.overall_mshr_miss_rate::total 0.086948 # mshr miss rate for overall accesses 810system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.542327 # average ReadReq mshr miss latency 811system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.542327 # average ReadReq mshr miss latency 812system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63378.619545 # average WriteReq mshr miss latency 813system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63378.619545 # average WriteReq mshr miss latency 814system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12743.156582 # average LoadLockedReq mshr miss latency 815system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12743.156582 # average LoadLockedReq mshr miss latency 816system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000 # average StoreCondReq mshr miss latency 817system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000 # average StoreCondReq mshr miss latency 818system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 819system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 820system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 821system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 822system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency 823system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency 824system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency 825system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency 826system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 827system.cpu.icache.tags.replacements 1074186 # number of replacements 828system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use 829system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. 830system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks. 831system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks. 832system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit. 833system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor 834system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy 835system.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy | 781system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 782system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 783system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 784system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 785system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30901101000 # number of ReadReq MSHR miss cycles 786system.cpu.dcache.ReadReq_mshr_miss_latency::total 30901101000 # number of ReadReq MSHR miss cycles 787system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12647974805 # number of WriteReq MSHR miss cycles 788system.cpu.dcache.WriteReq_mshr_miss_latency::total 12647974805 # number of WriteReq MSHR miss cycles 789system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 208768500 # number of LoadLockedReq MSHR miss cycles 790system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 208768500 # number of LoadLockedReq MSHR miss cycles 791system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1168000 # number of StoreCondReq MSHR miss cycles 792system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1168000 # number of StoreCondReq MSHR miss cycles 793system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43549075805 # number of demand (read+write) MSHR miss cycles 794system.cpu.dcache.demand_mshr_miss_latency::total 43549075805 # number of demand (read+write) MSHR miss cycles 795system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43549075805 # number of overall MSHR miss cycles 796system.cpu.dcache.overall_mshr_miss_latency::total 43549075805 # number of overall MSHR miss cycles 797system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535163500 # number of ReadReq MSHR uncacheable cycles 798system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535163500 # number of ReadReq MSHR uncacheable cycles 799system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535163500 # number of overall MSHR uncacheable cycles 800system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535163500 # number of overall MSHR uncacheable cycles 801system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111896 # mshr miss rate for ReadReq accesses 802system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111896 # mshr miss rate for ReadReq accesses 803system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047104 # mshr miss rate for WriteReq accesses 804system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047104 # mshr miss rate for WriteReq accesses 805system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.070819 # mshr miss rate for LoadLockedReq accesses 806system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.070819 # mshr miss rate for LoadLockedReq accesses 807system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000417 # mshr miss rate for StoreCondReq accesses 808system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000417 # mshr miss rate for StoreCondReq accesses 809system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for demand accesses 810system.cpu.dcache.demand_mshr_miss_rate::total 0.086965 # mshr miss rate for demand accesses 811system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for overall accesses 812system.cpu.dcache.overall_mshr_miss_rate::total 0.086965 # mshr miss rate for overall accesses 813system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28096.507610 # average ReadReq mshr miss latency 814system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28096.507610 # average ReadReq mshr miss latency 815system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43679.225062 # average WriteReq mshr miss latency 816system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43679.225062 # average WriteReq mshr miss latency 817system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12501.107784 # average LoadLockedReq mshr miss latency 818system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12501.107784 # average LoadLockedReq mshr miss latency 819system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12977.777778 # average StoreCondReq mshr miss latency 820system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12977.777778 # average StoreCondReq mshr miss latency 821system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31344.138453 # average overall mshr miss latency 822system.cpu.dcache.demand_avg_mshr_miss_latency::total 31344.138453 # average overall mshr miss latency 823system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31344.138453 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency::total 31344.138453 # average overall mshr miss latency 825system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221524.314574 # average ReadReq mshr uncacheable latency 826system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221524.314574 # average ReadReq mshr uncacheable latency 827system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92882.593175 # average overall mshr uncacheable latency 828system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92882.593175 # average overall mshr uncacheable latency 829system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 830system.cpu.icache.tags.replacements 1075014 # number of replacements 831system.cpu.icache.tags.tagsinuse 509.176961 # Cycle average of tags in use 832system.cpu.icache.tags.total_refs 8765751 # Total number of references to valid blocks. 833system.cpu.icache.tags.sampled_refs 1075522 # Sample count of references to valid blocks. 834system.cpu.icache.tags.avg_refs 8.150229 # Average number of references to valid blocks. 835system.cpu.icache.tags.warmup_cycle 28399256500 # Cycle when the warmup percentage was hit. 836system.cpu.icache.tags.occ_blocks::cpu.inst 509.176961 # Average occupied blocks per requestor 837system.cpu.icache.tags.occ_percent::cpu.inst 0.994486 # Average percentage of cache occupancy 838system.cpu.icache.tags.occ_percent::total 0.994486 # Average percentage of cache occupancy |
| 836system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id | 839system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 840system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id |
| 838system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id | 841system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id 842system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id |
| 840system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id | 843system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id |
| 841system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses 842system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses 843system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 844system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits 845system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits 846system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits 847system.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits 848system.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits 849system.cpu.icache.overall_hits::total 8786985 # number of overall hits 850system.cpu.icache.ReadReq_misses::cpu.inst 1143615 # number of ReadReq misses 851system.cpu.icache.ReadReq_misses::total 1143615 # number of ReadReq misses 852system.cpu.icache.demand_misses::cpu.inst 1143615 # number of demand (read+write) misses 853system.cpu.icache.demand_misses::total 1143615 # number of demand (read+write) misses 854system.cpu.icache.overall_misses::cpu.inst 1143615 # number of overall misses 855system.cpu.icache.overall_misses::total 1143615 # number of overall misses 856system.cpu.icache.ReadReq_miss_latency::cpu.inst 17001547978 # number of ReadReq miss cycles 857system.cpu.icache.ReadReq_miss_latency::total 17001547978 # number of ReadReq miss cycles 858system.cpu.icache.demand_miss_latency::cpu.inst 17001547978 # number of demand (read+write) miss cycles 859system.cpu.icache.demand_miss_latency::total 17001547978 # number of demand (read+write) miss cycles 860system.cpu.icache.overall_miss_latency::cpu.inst 17001547978 # number of overall miss cycles 861system.cpu.icache.overall_miss_latency::total 17001547978 # number of overall miss cycles 862system.cpu.icache.ReadReq_accesses::cpu.inst 9930600 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.ReadReq_accesses::total 9930600 # number of ReadReq accesses(hits+misses) 864system.cpu.icache.demand_accesses::cpu.inst 9930600 # number of demand (read+write) accesses 865system.cpu.icache.demand_accesses::total 9930600 # number of demand (read+write) accesses 866system.cpu.icache.overall_accesses::cpu.inst 9930600 # number of overall (read+write) accesses 867system.cpu.icache.overall_accesses::total 9930600 # number of overall (read+write) accesses 868system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115161 # miss rate for ReadReq accesses 869system.cpu.icache.ReadReq_miss_rate::total 0.115161 # miss rate for ReadReq accesses 870system.cpu.icache.demand_miss_rate::cpu.inst 0.115161 # miss rate for demand accesses 871system.cpu.icache.demand_miss_rate::total 0.115161 # miss rate for demand accesses 872system.cpu.icache.overall_miss_rate::cpu.inst 0.115161 # miss rate for overall accesses 873system.cpu.icache.overall_miss_rate::total 0.115161 # miss rate for overall accesses 874system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14866.496136 # average ReadReq miss latency 875system.cpu.icache.ReadReq_avg_miss_latency::total 14866.496136 # average ReadReq miss latency 876system.cpu.icache.demand_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency 877system.cpu.icache.demand_avg_miss_latency::total 14866.496136 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency 879system.cpu.icache.overall_avg_miss_latency::total 14866.496136 # average overall miss latency 880system.cpu.icache.blocked_cycles::no_mshrs 12933 # number of cycles access was blocked | 844system.cpu.icache.tags.tag_accesses 10985459 # Number of tag accesses 845system.cpu.icache.tags.data_accesses 10985459 # Number of data accesses 846system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 847system.cpu.icache.ReadReq_hits::cpu.inst 8765751 # number of ReadReq hits 848system.cpu.icache.ReadReq_hits::total 8765751 # number of ReadReq hits 849system.cpu.icache.demand_hits::cpu.inst 8765751 # number of demand (read+write) hits 850system.cpu.icache.demand_hits::total 8765751 # number of demand (read+write) hits 851system.cpu.icache.overall_hits::cpu.inst 8765751 # number of overall hits 852system.cpu.icache.overall_hits::total 8765751 # number of overall hits 853system.cpu.icache.ReadReq_misses::cpu.inst 1143868 # number of ReadReq misses 854system.cpu.icache.ReadReq_misses::total 1143868 # number of ReadReq misses 855system.cpu.icache.demand_misses::cpu.inst 1143868 # number of demand (read+write) misses 856system.cpu.icache.demand_misses::total 1143868 # number of demand (read+write) misses 857system.cpu.icache.overall_misses::cpu.inst 1143868 # number of overall misses 858system.cpu.icache.overall_misses::total 1143868 # number of overall misses 859system.cpu.icache.ReadReq_miss_latency::cpu.inst 15979138992 # number of ReadReq miss cycles 860system.cpu.icache.ReadReq_miss_latency::total 15979138992 # number of ReadReq miss cycles 861system.cpu.icache.demand_miss_latency::cpu.inst 15979138992 # number of demand (read+write) miss cycles 862system.cpu.icache.demand_miss_latency::total 15979138992 # number of demand (read+write) miss cycles 863system.cpu.icache.overall_miss_latency::cpu.inst 15979138992 # number of overall miss cycles 864system.cpu.icache.overall_miss_latency::total 15979138992 # number of overall miss cycles 865system.cpu.icache.ReadReq_accesses::cpu.inst 9909619 # number of ReadReq accesses(hits+misses) 866system.cpu.icache.ReadReq_accesses::total 9909619 # number of ReadReq accesses(hits+misses) 867system.cpu.icache.demand_accesses::cpu.inst 9909619 # number of demand (read+write) accesses 868system.cpu.icache.demand_accesses::total 9909619 # number of demand (read+write) accesses 869system.cpu.icache.overall_accesses::cpu.inst 9909619 # number of overall (read+write) accesses 870system.cpu.icache.overall_accesses::total 9909619 # number of overall (read+write) accesses 871system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115430 # miss rate for ReadReq accesses 872system.cpu.icache.ReadReq_miss_rate::total 0.115430 # miss rate for ReadReq accesses 873system.cpu.icache.demand_miss_rate::cpu.inst 0.115430 # miss rate for demand accesses 874system.cpu.icache.demand_miss_rate::total 0.115430 # miss rate for demand accesses 875system.cpu.icache.overall_miss_rate::cpu.inst 0.115430 # miss rate for overall accesses 876system.cpu.icache.overall_miss_rate::total 0.115430 # miss rate for overall accesses 877system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13969.390692 # average ReadReq miss latency 878system.cpu.icache.ReadReq_avg_miss_latency::total 13969.390692 # average ReadReq miss latency 879system.cpu.icache.demand_avg_miss_latency::cpu.inst 13969.390692 # average overall miss latency 880system.cpu.icache.demand_avg_miss_latency::total 13969.390692 # average overall miss latency 881system.cpu.icache.overall_avg_miss_latency::cpu.inst 13969.390692 # average overall miss latency 882system.cpu.icache.overall_avg_miss_latency::total 13969.390692 # average overall miss latency 883system.cpu.icache.blocked_cycles::no_mshrs 7656 # number of cycles access was blocked |
| 881system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 884system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 882system.cpu.icache.blocked::no_mshrs 342 # number of cycles access was blocked | 885system.cpu.icache.blocked::no_mshrs 228 # number of cycles access was blocked |
| 883system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 886system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 884system.cpu.icache.avg_blocked_cycles::no_mshrs 37.815789 # average number of cycles each access was blocked | 887system.cpu.icache.avg_blocked_cycles::no_mshrs 33.578947 # average number of cycles each access was blocked |
| 885system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 888system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 886system.cpu.icache.writebacks::writebacks 1074186 # number of writebacks 887system.cpu.icache.writebacks::total 1074186 # number of writebacks 888system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68615 # number of ReadReq MSHR hits 889system.cpu.icache.ReadReq_mshr_hits::total 68615 # number of ReadReq MSHR hits 890system.cpu.icache.demand_mshr_hits::cpu.inst 68615 # number of demand (read+write) MSHR hits 891system.cpu.icache.demand_mshr_hits::total 68615 # number of demand (read+write) MSHR hits 892system.cpu.icache.overall_mshr_hits::cpu.inst 68615 # number of overall MSHR hits 893system.cpu.icache.overall_mshr_hits::total 68615 # number of overall MSHR hits 894system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075000 # number of ReadReq MSHR misses 895system.cpu.icache.ReadReq_mshr_misses::total 1075000 # number of ReadReq MSHR misses 896system.cpu.icache.demand_mshr_misses::cpu.inst 1075000 # number of demand (read+write) MSHR misses 897system.cpu.icache.demand_mshr_misses::total 1075000 # number of demand (read+write) MSHR misses 898system.cpu.icache.overall_mshr_misses::cpu.inst 1075000 # number of overall MSHR misses 899system.cpu.icache.overall_mshr_misses::total 1075000 # number of overall MSHR misses 900system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14900351984 # number of ReadReq MSHR miss cycles 901system.cpu.icache.ReadReq_mshr_miss_latency::total 14900351984 # number of ReadReq MSHR miss cycles 902system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14900351984 # number of demand (read+write) MSHR miss cycles 903system.cpu.icache.demand_mshr_miss_latency::total 14900351984 # number of demand (read+write) MSHR miss cycles 904system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14900351984 # number of overall MSHR miss cycles 905system.cpu.icache.overall_mshr_miss_latency::total 14900351984 # number of overall MSHR miss cycles 906system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for ReadReq accesses 907system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108251 # mshr miss rate for ReadReq accesses 908system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for demand accesses 909system.cpu.icache.demand_mshr_miss_rate::total 0.108251 # mshr miss rate for demand accesses 910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses 911system.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses 912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency 914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency 916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency 918system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 919system.cpu.l2cache.tags.replacements 338591 # number of replacements 920system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use 921system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks. 922system.cpu.l2cache.tags.sampled_refs 403759 # Sample count of references to valid blocks. 923system.cpu.l2cache.tags.avg_refs 10.534943 # Average number of references to valid blocks. 924system.cpu.l2cache.tags.warmup_cycle 9186566000 # Cycle when the warmup percentage was hit. 925system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616 # Average occupied blocks per requestor 926system.cpu.l2cache.tags.occ_blocks::cpu.inst 5255.268427 # Average occupied blocks per requestor 927system.cpu.l2cache.tags.occ_blocks::cpu.data 7006.243291 # Average occupied blocks per requestor 928system.cpu.l2cache.tags.occ_percent::writebacks 0.809083 # Average percentage of cache occupancy 929system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080189 # Average percentage of cache occupancy 930system.cpu.l2cache.tags.occ_percent::cpu.data 0.106907 # Average percentage of cache occupancy 931system.cpu.l2cache.tags.occ_percent::total 0.996179 # Average percentage of cache occupancy 932system.cpu.l2cache.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id 933system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id 934system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3471 # Occupied blocks per task id 935system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3347 # Occupied blocks per task id 936system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2431 # Occupied blocks per task id 937system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55427 # Occupied blocks per task id 938system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id 939system.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses 940system.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses 941system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 942system.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits 943system.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits 944system.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits 945system.cpu.l2cache.WritebackClean_hits::total 1073682 # number of WritebackClean hits 946system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits 947system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits 948system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 88 # number of SCUpgradeReq hits 949system.cpu.l2cache.SCUpgradeReq_hits::total 88 # number of SCUpgradeReq hits 950system.cpu.l2cache.ReadExReq_hits::cpu.data 185036 # number of ReadExReq hits 951system.cpu.l2cache.ReadExReq_hits::total 185036 # number of ReadExReq hits 952system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1059597 # number of ReadCleanReq hits 953system.cpu.l2cache.ReadCleanReq_hits::total 1059597 # number of ReadCleanReq hits 954system.cpu.l2cache.ReadSharedReq_hits::cpu.data 832111 # number of ReadSharedReq hits 955system.cpu.l2cache.ReadSharedReq_hits::total 832111 # number of ReadSharedReq hits 956system.cpu.l2cache.demand_hits::cpu.inst 1059597 # number of demand (read+write) hits 957system.cpu.l2cache.demand_hits::cpu.data 1017147 # number of demand (read+write) hits 958system.cpu.l2cache.demand_hits::total 2076744 # number of demand (read+write) hits 959system.cpu.l2cache.overall_hits::cpu.inst 1059597 # number of overall hits 960system.cpu.l2cache.overall_hits::cpu.data 1017147 # number of overall hits 961system.cpu.l2cache.overall_hits::total 2076744 # number of overall hits 962system.cpu.l2cache.UpgradeReq_misses::cpu.data 45 # number of UpgradeReq misses 963system.cpu.l2cache.UpgradeReq_misses::total 45 # number of UpgradeReq misses 964system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 8 # number of SCUpgradeReq misses 965system.cpu.l2cache.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses 966system.cpu.l2cache.ReadExReq_misses::cpu.data 114791 # number of ReadExReq misses 967system.cpu.l2cache.ReadExReq_misses::total 114791 # number of ReadExReq misses 968system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15028 # number of ReadCleanReq misses 969system.cpu.l2cache.ReadCleanReq_misses::total 15028 # number of ReadCleanReq misses 970system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274518 # number of ReadSharedReq misses 971system.cpu.l2cache.ReadSharedReq_misses::total 274518 # number of ReadSharedReq misses 972system.cpu.l2cache.demand_misses::cpu.inst 15028 # number of demand (read+write) misses 973system.cpu.l2cache.demand_misses::cpu.data 389309 # number of demand (read+write) misses 974system.cpu.l2cache.demand_misses::total 404337 # number of demand (read+write) misses 975system.cpu.l2cache.overall_misses::cpu.inst 15028 # number of overall misses 976system.cpu.l2cache.overall_misses::cpu.data 389309 # number of overall misses 977system.cpu.l2cache.overall_misses::total 404337 # number of overall misses 978system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 866000 # number of UpgradeReq miss cycles 979system.cpu.l2cache.UpgradeReq_miss_latency::total 866000 # number of UpgradeReq miss cycles 980system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 547500 # number of SCUpgradeReq miss cycles 981system.cpu.l2cache.SCUpgradeReq_miss_latency::total 547500 # number of SCUpgradeReq miss cycles 982system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16017370500 # number of ReadExReq miss cycles 983system.cpu.l2cache.ReadExReq_miss_latency::total 16017370500 # number of ReadExReq miss cycles 984system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2025075000 # number of ReadCleanReq miss cycles 985system.cpu.l2cache.ReadCleanReq_miss_latency::total 2025075000 # number of ReadCleanReq miss cycles 986system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34108164000 # number of ReadSharedReq miss cycles 987system.cpu.l2cache.ReadSharedReq_miss_latency::total 34108164000 # number of ReadSharedReq miss cycles 988system.cpu.l2cache.demand_miss_latency::cpu.inst 2025075000 # number of demand (read+write) miss cycles 989system.cpu.l2cache.demand_miss_latency::cpu.data 50125534500 # number of demand (read+write) miss cycles 990system.cpu.l2cache.demand_miss_latency::total 52150609500 # number of demand (read+write) miss cycles 991system.cpu.l2cache.overall_miss_latency::cpu.inst 2025075000 # number of overall miss cycles 992system.cpu.l2cache.overall_miss_latency::cpu.data 50125534500 # number of overall miss cycles 993system.cpu.l2cache.overall_miss_latency::total 52150609500 # number of overall miss cycles 994system.cpu.l2cache.WritebackDirty_accesses::writebacks 843569 # number of WritebackDirty accesses(hits+misses) 995system.cpu.l2cache.WritebackDirty_accesses::total 843569 # number of WritebackDirty accesses(hits+misses) 996system.cpu.l2cache.WritebackClean_accesses::writebacks 1073682 # number of WritebackClean accesses(hits+misses) 997system.cpu.l2cache.WritebackClean_accesses::total 1073682 # number of WritebackClean accesses(hits+misses) 998system.cpu.l2cache.UpgradeReq_accesses::cpu.data 80 # number of UpgradeReq accesses(hits+misses) 999system.cpu.l2cache.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses) 1000system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 96 # number of SCUpgradeReq accesses(hits+misses) 1001system.cpu.l2cache.SCUpgradeReq_accesses::total 96 # number of SCUpgradeReq accesses(hits+misses) 1002system.cpu.l2cache.ReadExReq_accesses::cpu.data 299827 # number of ReadExReq accesses(hits+misses) 1003system.cpu.l2cache.ReadExReq_accesses::total 299827 # number of ReadExReq accesses(hits+misses) 1004system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1074625 # number of ReadCleanReq accesses(hits+misses) 1005system.cpu.l2cache.ReadCleanReq_accesses::total 1074625 # number of ReadCleanReq accesses(hits+misses) 1006system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106629 # number of ReadSharedReq accesses(hits+misses) 1007system.cpu.l2cache.ReadSharedReq_accesses::total 1106629 # number of ReadSharedReq accesses(hits+misses) 1008system.cpu.l2cache.demand_accesses::cpu.inst 1074625 # number of demand (read+write) accesses 1009system.cpu.l2cache.demand_accesses::cpu.data 1406456 # number of demand (read+write) accesses 1010system.cpu.l2cache.demand_accesses::total 2481081 # number of demand (read+write) accesses 1011system.cpu.l2cache.overall_accesses::cpu.inst 1074625 # number of overall (read+write) accesses 1012system.cpu.l2cache.overall_accesses::cpu.data 1406456 # number of overall (read+write) accesses 1013system.cpu.l2cache.overall_accesses::total 2481081 # number of overall (read+write) accesses 1014system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.562500 # miss rate for UpgradeReq accesses 1015system.cpu.l2cache.UpgradeReq_miss_rate::total 0.562500 # miss rate for UpgradeReq accesses 1016system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.083333 # miss rate for SCUpgradeReq accesses 1017system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.083333 # miss rate for SCUpgradeReq accesses 1018system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382857 # miss rate for ReadExReq accesses 1019system.cpu.l2cache.ReadExReq_miss_rate::total 0.382857 # miss rate for ReadExReq accesses 1020system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013984 # miss rate for ReadCleanReq accesses 1021system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013984 # miss rate for ReadCleanReq accesses 1022system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248067 # miss rate for ReadSharedReq accesses 1023system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248067 # miss rate for ReadSharedReq accesses 1024system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013984 # miss rate for demand accesses 1025system.cpu.l2cache.demand_miss_rate::cpu.data 0.276801 # miss rate for demand accesses 1026system.cpu.l2cache.demand_miss_rate::total 0.162968 # miss rate for demand accesses 1027system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013984 # miss rate for overall accesses 1028system.cpu.l2cache.overall_miss_rate::cpu.data 0.276801 # miss rate for overall accesses 1029system.cpu.l2cache.overall_miss_rate::total 0.162968 # miss rate for overall accesses 1030system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19244.444444 # average UpgradeReq miss latency 1031system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19244.444444 # average UpgradeReq miss latency 1032system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 68437.500000 # average SCUpgradeReq miss latency 1033system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 68437.500000 # average SCUpgradeReq miss latency 1034system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139535.072436 # average ReadExReq miss latency 1035system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139535.072436 # average ReadExReq miss latency 1036system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134753.460208 # average ReadCleanReq miss latency 1037system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134753.460208 # average ReadCleanReq miss latency 1038system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124247.459183 # average ReadSharedReq miss latency 1039system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124247.459183 # average ReadSharedReq miss latency 1040system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134753.460208 # average overall miss latency 1041system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128755.139234 # average overall miss latency 1042system.cpu.l2cache.demand_avg_miss_latency::total 128978.078929 # average overall miss latency 1043system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134753.460208 # average overall miss latency 1044system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128755.139234 # average overall miss latency 1045system.cpu.l2cache.overall_avg_miss_latency::total 128978.078929 # average overall miss latency | 889system.cpu.icache.writebacks::writebacks 1075014 # number of writebacks 890system.cpu.icache.writebacks::total 1075014 # number of writebacks 891system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68028 # number of ReadReq MSHR hits 892system.cpu.icache.ReadReq_mshr_hits::total 68028 # number of ReadReq MSHR hits 893system.cpu.icache.demand_mshr_hits::cpu.inst 68028 # number of demand (read+write) MSHR hits 894system.cpu.icache.demand_mshr_hits::total 68028 # number of demand (read+write) MSHR hits 895system.cpu.icache.overall_mshr_hits::cpu.inst 68028 # number of overall MSHR hits 896system.cpu.icache.overall_mshr_hits::total 68028 # number of overall MSHR hits 897system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075840 # number of ReadReq MSHR misses 898system.cpu.icache.ReadReq_mshr_misses::total 1075840 # number of ReadReq MSHR misses 899system.cpu.icache.demand_mshr_misses::cpu.inst 1075840 # number of demand (read+write) MSHR misses 900system.cpu.icache.demand_mshr_misses::total 1075840 # number of demand (read+write) MSHR misses 901system.cpu.icache.overall_mshr_misses::cpu.inst 1075840 # number of overall MSHR misses 902system.cpu.icache.overall_mshr_misses::total 1075840 # number of overall MSHR misses 903system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14160831996 # number of ReadReq MSHR miss cycles 904system.cpu.icache.ReadReq_mshr_miss_latency::total 14160831996 # number of ReadReq MSHR miss cycles 905system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14160831996 # number of demand (read+write) MSHR miss cycles 906system.cpu.icache.demand_mshr_miss_latency::total 14160831996 # number of demand (read+write) MSHR miss cycles 907system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14160831996 # number of overall MSHR miss cycles 908system.cpu.icache.overall_mshr_miss_latency::total 14160831996 # number of overall MSHR miss cycles 909system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108565 # mshr miss rate for ReadReq accesses 910system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108565 # mshr miss rate for ReadReq accesses 911system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108565 # mshr miss rate for demand accesses 912system.cpu.icache.demand_mshr_miss_rate::total 0.108565 # mshr miss rate for demand accesses 913system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108565 # mshr miss rate for overall accesses 914system.cpu.icache.overall_mshr_miss_rate::total 0.108565 # mshr miss rate for overall accesses 915system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13162.581793 # average ReadReq mshr miss latency 916system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13162.581793 # average ReadReq mshr miss latency 917system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13162.581793 # average overall mshr miss latency 918system.cpu.icache.demand_avg_mshr_miss_latency::total 13162.581793 # average overall mshr miss latency 919system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13162.581793 # average overall mshr miss latency 920system.cpu.icache.overall_avg_mshr_miss_latency::total 13162.581793 # average overall mshr miss latency 921system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 922system.cpu.l2cache.tags.replacements 338638 # number of replacements 923system.cpu.l2cache.tags.tagsinuse 65427.252545 # Cycle average of tags in use 924system.cpu.l2cache.tags.total_refs 4555596 # Total number of references to valid blocks. 925system.cpu.l2cache.tags.sampled_refs 404160 # Sample count of references to valid blocks. 926system.cpu.l2cache.tags.avg_refs 11.271764 # Average number of references to valid blocks. 927system.cpu.l2cache.tags.warmup_cycle 5985561000 # Cycle when the warmup percentage was hit. 928system.cpu.l2cache.tags.occ_blocks::writebacks 253.752588 # Average occupied blocks per requestor 929system.cpu.l2cache.tags.occ_blocks::cpu.inst 5311.170770 # Average occupied blocks per requestor 930system.cpu.l2cache.tags.occ_blocks::cpu.data 59862.329187 # Average occupied blocks per requestor 931system.cpu.l2cache.tags.occ_percent::writebacks 0.003872 # Average percentage of cache occupancy 932system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081042 # Average percentage of cache occupancy 933system.cpu.l2cache.tags.occ_percent::cpu.data 0.913427 # Average percentage of cache occupancy 934system.cpu.l2cache.tags.occ_percent::total 0.998341 # Average percentage of cache occupancy 935system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 936system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 937system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id 938system.cpu.l2cache.tags.age_task_id_blocks_1024::2 449 # Occupied blocks per task id 939system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5579 # Occupied blocks per task id 940system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58592 # Occupied blocks per task id 941system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 942system.cpu.l2cache.tags.tag_accesses 40086542 # Number of tag accesses 943system.cpu.l2cache.tags.data_accesses 40086542 # Number of data accesses 944system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 945system.cpu.l2cache.WritebackDirty_hits::writebacks 843871 # number of WritebackDirty hits 946system.cpu.l2cache.WritebackDirty_hits::total 843871 # number of WritebackDirty hits 947system.cpu.l2cache.WritebackClean_hits::writebacks 1074552 # number of WritebackClean hits 948system.cpu.l2cache.WritebackClean_hits::total 1074552 # number of WritebackClean hits 949system.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits 950system.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits 951system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 90 # number of SCUpgradeReq hits 952system.cpu.l2cache.SCUpgradeReq_hits::total 90 # number of SCUpgradeReq hits 953system.cpu.l2cache.ReadExReq_hits::cpu.data 185367 # number of ReadExReq hits 954system.cpu.l2cache.ReadExReq_hits::total 185367 # number of ReadExReq hits 955system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1060413 # number of ReadCleanReq hits 956system.cpu.l2cache.ReadCleanReq_hits::total 1060413 # number of ReadCleanReq hits 957system.cpu.l2cache.ReadSharedReq_hits::cpu.data 831413 # number of ReadSharedReq hits 958system.cpu.l2cache.ReadSharedReq_hits::total 831413 # number of ReadSharedReq hits 959system.cpu.l2cache.demand_hits::cpu.inst 1060413 # number of demand (read+write) hits 960system.cpu.l2cache.demand_hits::cpu.data 1016780 # number of demand (read+write) hits 961system.cpu.l2cache.demand_hits::total 2077193 # number of demand (read+write) hits 962system.cpu.l2cache.overall_hits::cpu.inst 1060413 # number of overall hits 963system.cpu.l2cache.overall_hits::cpu.data 1016780 # number of overall hits 964system.cpu.l2cache.overall_hits::total 2077193 # number of overall hits 965system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses 966system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses 967system.cpu.l2cache.ReadExReq_misses::cpu.data 114699 # number of ReadExReq misses 968system.cpu.l2cache.ReadExReq_misses::total 114699 # number of ReadExReq misses 969system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15055 # number of ReadCleanReq misses 970system.cpu.l2cache.ReadCleanReq_misses::total 15055 # number of ReadCleanReq misses 971system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274527 # number of ReadSharedReq misses 972system.cpu.l2cache.ReadSharedReq_misses::total 274527 # number of ReadSharedReq misses 973system.cpu.l2cache.demand_misses::cpu.inst 15055 # number of demand (read+write) misses 974system.cpu.l2cache.demand_misses::cpu.data 389226 # number of demand (read+write) misses 975system.cpu.l2cache.demand_misses::total 404281 # number of demand (read+write) misses 976system.cpu.l2cache.overall_misses::cpu.inst 15055 # number of overall misses 977system.cpu.l2cache.overall_misses::cpu.data 389226 # number of overall misses 978system.cpu.l2cache.overall_misses::total 404281 # number of overall misses 979system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 387500 # number of UpgradeReq miss cycles 980system.cpu.l2cache.UpgradeReq_miss_latency::total 387500 # number of UpgradeReq miss cycles 981system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10326275500 # number of ReadExReq miss cycles 982system.cpu.l2cache.ReadExReq_miss_latency::total 10326275500 # number of ReadExReq miss cycles 983system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1274090500 # number of ReadCleanReq miss cycles 984system.cpu.l2cache.ReadCleanReq_miss_latency::total 1274090500 # number of ReadCleanReq miss cycles 985system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 20279625500 # number of ReadSharedReq miss cycles 986system.cpu.l2cache.ReadSharedReq_miss_latency::total 20279625500 # number of ReadSharedReq miss cycles 987system.cpu.l2cache.demand_miss_latency::cpu.inst 1274090500 # number of demand (read+write) miss cycles 988system.cpu.l2cache.demand_miss_latency::cpu.data 30605901000 # number of demand (read+write) miss cycles 989system.cpu.l2cache.demand_miss_latency::total 31879991500 # number of demand (read+write) miss cycles 990system.cpu.l2cache.overall_miss_latency::cpu.inst 1274090500 # number of overall miss cycles 991system.cpu.l2cache.overall_miss_latency::cpu.data 30605901000 # number of overall miss cycles 992system.cpu.l2cache.overall_miss_latency::total 31879991500 # number of overall miss cycles 993system.cpu.l2cache.WritebackDirty_accesses::writebacks 843871 # number of WritebackDirty accesses(hits+misses) 994system.cpu.l2cache.WritebackDirty_accesses::total 843871 # number of WritebackDirty accesses(hits+misses) 995system.cpu.l2cache.WritebackClean_accesses::writebacks 1074552 # number of WritebackClean accesses(hits+misses) 996system.cpu.l2cache.WritebackClean_accesses::total 1074552 # number of WritebackClean accesses(hits+misses) 997system.cpu.l2cache.UpgradeReq_accesses::cpu.data 82 # number of UpgradeReq accesses(hits+misses) 998system.cpu.l2cache.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) 999system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 90 # number of SCUpgradeReq accesses(hits+misses) 1000system.cpu.l2cache.SCUpgradeReq_accesses::total 90 # number of SCUpgradeReq accesses(hits+misses) 1001system.cpu.l2cache.ReadExReq_accesses::cpu.data 300066 # number of ReadExReq accesses(hits+misses) 1002system.cpu.l2cache.ReadExReq_accesses::total 300066 # number of ReadExReq accesses(hits+misses) 1003system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1075468 # number of ReadCleanReq accesses(hits+misses) 1004system.cpu.l2cache.ReadCleanReq_accesses::total 1075468 # number of ReadCleanReq accesses(hits+misses) 1005system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1105940 # number of ReadSharedReq accesses(hits+misses) 1006system.cpu.l2cache.ReadSharedReq_accesses::total 1105940 # number of ReadSharedReq accesses(hits+misses) 1007system.cpu.l2cache.demand_accesses::cpu.inst 1075468 # number of demand (read+write) accesses 1008system.cpu.l2cache.demand_accesses::cpu.data 1406006 # number of demand (read+write) accesses 1009system.cpu.l2cache.demand_accesses::total 2481474 # number of demand (read+write) accesses 1010system.cpu.l2cache.overall_accesses::cpu.inst 1075468 # number of overall (read+write) accesses 1011system.cpu.l2cache.overall_accesses::cpu.data 1406006 # number of overall (read+write) accesses 1012system.cpu.l2cache.overall_accesses::total 2481474 # number of overall (read+write) accesses 1013system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.097561 # miss rate for UpgradeReq accesses 1014system.cpu.l2cache.UpgradeReq_miss_rate::total 0.097561 # miss rate for UpgradeReq accesses 1015system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382246 # miss rate for ReadExReq accesses 1016system.cpu.l2cache.ReadExReq_miss_rate::total 0.382246 # miss rate for ReadExReq accesses 1017system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013999 # miss rate for ReadCleanReq accesses 1018system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013999 # miss rate for ReadCleanReq accesses 1019system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248230 # miss rate for ReadSharedReq accesses 1020system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248230 # miss rate for ReadSharedReq accesses 1021system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013999 # miss rate for demand accesses 1022system.cpu.l2cache.demand_miss_rate::cpu.data 0.276831 # miss rate for demand accesses 1023system.cpu.l2cache.demand_miss_rate::total 0.162920 # miss rate for demand accesses 1024system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013999 # miss rate for overall accesses 1025system.cpu.l2cache.overall_miss_rate::cpu.data 0.276831 # miss rate for overall accesses 1026system.cpu.l2cache.overall_miss_rate::total 0.162920 # miss rate for overall accesses 1027system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48437.500000 # average UpgradeReq miss latency 1028system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48437.500000 # average UpgradeReq miss latency 1029system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90029.342017 # average ReadExReq miss latency 1030system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90029.342017 # average ReadExReq miss latency 1031system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84629.060113 # average ReadCleanReq miss latency 1032system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84629.060113 # average ReadCleanReq miss latency 1033system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73871.151107 # average ReadSharedReq miss latency 1034system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73871.151107 # average ReadSharedReq miss latency 1035system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84629.060113 # average overall miss latency 1036system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78632.724946 # average overall miss latency 1037system.cpu.l2cache.demand_avg_miss_latency::total 78856.022173 # average overall miss latency 1038system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84629.060113 # average overall miss latency 1039system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78632.724946 # average overall miss latency 1040system.cpu.l2cache.overall_avg_miss_latency::total 78856.022173 # average overall miss latency |
| 1046system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1047system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1048system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1049system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1050system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1051system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1041system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1042system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1043system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1044system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1045system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1046system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1052system.cpu.l2cache.writebacks::writebacks 76108 # number of writebacks 1053system.cpu.l2cache.writebacks::total 76108 # number of writebacks 1054system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 45 # number of UpgradeReq MSHR misses 1055system.cpu.l2cache.UpgradeReq_mshr_misses::total 45 # number of UpgradeReq MSHR misses 1056system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses 1057system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses 1058system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114791 # number of ReadExReq MSHR misses 1059system.cpu.l2cache.ReadExReq_mshr_misses::total 114791 # number of ReadExReq MSHR misses 1060system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15028 # number of ReadCleanReq MSHR misses 1061system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15028 # number of ReadCleanReq MSHR misses 1062system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274518 # number of ReadSharedReq MSHR misses 1063system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274518 # number of ReadSharedReq MSHR misses 1064system.cpu.l2cache.demand_mshr_misses::cpu.inst 15028 # number of demand (read+write) MSHR misses 1065system.cpu.l2cache.demand_mshr_misses::cpu.data 389309 # number of demand (read+write) MSHR misses 1066system.cpu.l2cache.demand_mshr_misses::total 404337 # number of demand (read+write) MSHR misses 1067system.cpu.l2cache.overall_mshr_misses::cpu.inst 15028 # number of overall MSHR misses 1068system.cpu.l2cache.overall_mshr_misses::cpu.data 389309 # number of overall MSHR misses 1069system.cpu.l2cache.overall_mshr_misses::total 404337 # number of overall MSHR misses | 1047system.cpu.l2cache.writebacks::writebacks 76126 # number of writebacks 1048system.cpu.l2cache.writebacks::total 76126 # number of writebacks 1049system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1050system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1051system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1052system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1053system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1054system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1055system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses 1056system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses 1057system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114699 # number of ReadExReq MSHR misses 1058system.cpu.l2cache.ReadExReq_mshr_misses::total 114699 # number of ReadExReq MSHR misses 1059system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15054 # number of ReadCleanReq MSHR misses 1060system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15054 # number of ReadCleanReq MSHR misses 1061system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274527 # number of ReadSharedReq MSHR misses 1062system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274527 # number of ReadSharedReq MSHR misses 1063system.cpu.l2cache.demand_mshr_misses::cpu.inst 15054 # number of demand (read+write) MSHR misses 1064system.cpu.l2cache.demand_mshr_misses::cpu.data 389226 # number of demand (read+write) MSHR misses 1065system.cpu.l2cache.demand_mshr_misses::total 404280 # number of demand (read+write) MSHR misses 1066system.cpu.l2cache.overall_mshr_misses::cpu.inst 15054 # number of overall MSHR misses 1067system.cpu.l2cache.overall_mshr_misses::cpu.data 389226 # number of overall MSHR misses 1068system.cpu.l2cache.overall_mshr_misses::total 404280 # number of overall MSHR misses |
| 1070system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 1071system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 1069system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 1070system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 1072system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable 1073system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable 1074system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 1075system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses 1076system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3100000 # number of UpgradeReq MSHR miss cycles 1077system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3100000 # number of UpgradeReq MSHR miss cycles 1078system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 546000 # number of SCUpgradeReq MSHR miss cycles 1079system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 546000 # number of SCUpgradeReq MSHR miss cycles 1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14869460001 # number of ReadExReq MSHR miss cycles 1081system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14869460001 # number of ReadExReq MSHR miss cycles 1082system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1874795000 # number of ReadCleanReq MSHR miss cycles 1083system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1874795000 # number of ReadCleanReq MSHR miss cycles 1084system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31368563001 # number of ReadSharedReq MSHR miss cycles 1085system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31368563001 # number of ReadSharedReq MSHR miss cycles 1086system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1874795000 # number of demand (read+write) MSHR miss cycles 1087system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46238023002 # number of demand (read+write) MSHR miss cycles 1088system.cpu.l2cache.demand_mshr_miss_latency::total 48112818002 # number of demand (read+write) MSHR miss cycles 1089system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1874795000 # number of overall MSHR miss cycles 1090system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46238023002 # number of overall MSHR miss cycles 1091system.cpu.l2cache.overall_mshr_miss_latency::total 48112818002 # number of overall MSHR miss cycles 1092system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442000500 # number of ReadReq MSHR uncacheable cycles 1093system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442000500 # number of ReadReq MSHR uncacheable cycles 1094system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1442000500 # number of overall MSHR uncacheable cycles 1095system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1442000500 # number of overall MSHR uncacheable cycles 1096system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.562500 # mshr miss rate for UpgradeReq accesses 1097system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.562500 # mshr miss rate for UpgradeReq accesses 1098system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.083333 # mshr miss rate for SCUpgradeReq accesses 1099system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses 1100system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382857 # mshr miss rate for ReadExReq accesses 1101system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382857 # mshr miss rate for ReadExReq accesses 1102system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for ReadCleanReq accesses 1103system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013984 # mshr miss rate for ReadCleanReq accesses 1104system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248067 # mshr miss rate for ReadSharedReq accesses 1105system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248067 # mshr miss rate for ReadSharedReq accesses 1106system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for demand accesses 1107system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276801 # mshr miss rate for demand accesses 1108system.cpu.l2cache.demand_mshr_miss_rate::total 0.162968 # mshr miss rate for demand accesses 1109system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for overall accesses 1110system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276801 # mshr miss rate for overall accesses 1111system.cpu.l2cache.overall_mshr_miss_rate::total 0.162968 # mshr miss rate for overall accesses 1112system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68888.888889 # average UpgradeReq mshr miss latency 1113system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68888.888889 # average UpgradeReq mshr miss latency 1114system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68250 # average SCUpgradeReq mshr miss latency 1115system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68250 # average SCUpgradeReq mshr miss latency 1116system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129535.068089 # average ReadExReq mshr miss latency 1117system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129535.068089 # average ReadExReq mshr miss latency 1118system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124753.460208 # average ReadCleanReq mshr miss latency 1119system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124753.460208 # average ReadCleanReq mshr miss latency 1120system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114267.782080 # average ReadSharedReq mshr miss latency 1121system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114267.782080 # average ReadSharedReq mshr miss latency 1122system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency 1123system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency 1124system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency 1125system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency 1126system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency 1127system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency 1128system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231 # average ReadReq mshr uncacheable latency 1129system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231 # average ReadReq mshr uncacheable latency 1130system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency 1131system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency 1132system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter. 1133system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1134system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1135system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 1136system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1071system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 1072system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 1073system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 1074system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 1075system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 307500 # number of UpgradeReq MSHR miss cycles 1076system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 307500 # number of UpgradeReq MSHR miss cycles 1077system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9179285500 # number of ReadExReq MSHR miss cycles 1078system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9179285500 # number of ReadExReq MSHR miss cycles 1079system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1123478500 # number of ReadCleanReq MSHR miss cycles 1080system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1123478500 # number of ReadCleanReq MSHR miss cycles 1081system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17540240000 # number of ReadSharedReq MSHR miss cycles 1082system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17540240000 # number of ReadSharedReq MSHR miss cycles 1083system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1123478500 # number of demand (read+write) MSHR miss cycles 1084system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26719525500 # number of demand (read+write) MSHR miss cycles 1085system.cpu.l2cache.demand_mshr_miss_latency::total 27843004000 # number of demand (read+write) MSHR miss cycles 1086system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1123478500 # number of overall MSHR miss cycles 1087system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26719525500 # number of overall MSHR miss cycles 1088system.cpu.l2cache.overall_mshr_miss_latency::total 27843004000 # number of overall MSHR miss cycles 1089system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448524000 # number of ReadReq MSHR uncacheable cycles 1090system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448524000 # number of ReadReq MSHR uncacheable cycles 1091system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448524000 # number of overall MSHR uncacheable cycles 1092system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448524000 # number of overall MSHR uncacheable cycles 1093system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097561 # mshr miss rate for UpgradeReq accesses 1094system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097561 # mshr miss rate for UpgradeReq accesses 1095system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382246 # mshr miss rate for ReadExReq accesses 1096system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382246 # mshr miss rate for ReadExReq accesses 1097system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for ReadCleanReq accesses 1098system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013998 # mshr miss rate for ReadCleanReq accesses 1099system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248230 # mshr miss rate for ReadSharedReq accesses 1100system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248230 # mshr miss rate for ReadSharedReq accesses 1101system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for demand accesses 1102system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for demand accesses 1103system.cpu.l2cache.demand_mshr_miss_rate::total 0.162919 # mshr miss rate for demand accesses 1104system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for overall accesses 1105system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for overall accesses 1106system.cpu.l2cache.overall_mshr_miss_rate::total 0.162919 # mshr miss rate for overall accesses 1107system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 38437.500000 # average UpgradeReq mshr miss latency 1108system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 38437.500000 # average UpgradeReq mshr miss latency 1109system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80029.342017 # average ReadExReq mshr miss latency 1110system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80029.342017 # average ReadExReq mshr miss latency 1111system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74629.899030 # average ReadCleanReq mshr miss latency 1112system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74629.899030 # average ReadCleanReq mshr miss latency 1113system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63892.586157 # average ReadSharedReq mshr miss latency 1114system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63892.586157 # average ReadSharedReq mshr miss latency 1115system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency 1116system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency 1117system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency 1118system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency 1119system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency 1120system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency 1121system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209022.222222 # average ReadReq mshr uncacheable latency 1122system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209022.222222 # average ReadReq mshr uncacheable latency 1123system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87640.609874 # average overall mshr uncacheable latency 1124system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87640.609874 # average overall mshr uncacheable latency 1125system.cpu.toL2Bus.snoop_filter.tot_requests 4962480 # Total number of requests made to the snoop filter. 1126system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480820 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1127system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1128system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. 1129system.cpu.toL2Bus.snoop_filter.hit_single_snoops 950 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1137system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1130system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1138system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states | 1131system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states |
| 1139system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution | 1132system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1140system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution 1141system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution 1147system.cpu.toL2Bus.trans_dist::SCUpgradeReq 96 # Transaction distribution 1148system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution 1149system.cpu.toL2Bus.trans_dist::ReadExReq 299827 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::ReadExResp 299827 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075000 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106802 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::BadAddressError 43 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 1155system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3223811 # Packet count per connected master and slave (bytes) 1156system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252378 # Packet count per connected master and slave (bytes) 1157system.cpu.toL2Bus.pkt_count::total 7476189 # Packet count per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137523904 # Cumulative packet size per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144052988 # Cumulative packet size per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_size::total 281576892 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu.toL2Bus.snoops 422541 # Total snoops (count) 1162system.cpu.toL2Bus.snoopTraffic 7562240 # Total snoop traffic (bytes) 1163system.cpu.toL2Bus.snoop_fanout::samples 2920171 # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::mean 0.001264 # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::stdev 0.035530 # Request fanout histogram | 1133system.cpu.toL2Bus.trans_dist::ReadResp 2188821 # Transaction distribution 1134system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 1135system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 1136system.cpu.toL2Bus.trans_dist::WritebackDirty 919997 # Transaction distribution 1137system.cpu.toL2Bus.trans_dist::WritebackClean 1075014 # Transaction distribution 1138system.cpu.toL2Bus.trans_dist::CleanEvict 824089 # Transaction distribution 1139system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution 1140system.cpu.toL2Bus.trans_dist::SCUpgradeReq 90 # Transaction distribution 1141system.cpu.toL2Bus.trans_dist::UpgradeResp 172 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::ReadExReq 300066 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::ReadExResp 300066 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075840 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106100 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution 1147system.cpu.toL2Bus.trans_dist::InvalidateReq 254 # Transaction distribution 1148system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3226322 # Packet count per connected master and slave (bytes) 1149system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4251016 # Packet count per connected master and slave (bytes) 1150system.cpu.toL2Bus.pkt_count::total 7477338 # Packet count per connected master and slave (bytes) 1151system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137630848 # Cumulative packet size per connected master and slave (bytes) 1152system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144043380 # Cumulative packet size per connected master and slave (bytes) 1153system.cpu.toL2Bus.pkt_size::total 281674228 # Cumulative packet size per connected master and slave (bytes) 1154system.cpu.toL2Bus.snoops 339580 # Total snoops (count) 1155system.cpu.toL2Bus.snoopTraffic 4905856 # Total snoop traffic (bytes) 1156system.cpu.toL2Bus.snoop_fanout::samples 2837598 # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::mean 0.001208 # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::stdev 0.034736 # Request fanout histogram |
| 1166system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1159system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1167system.cpu.toL2Bus.snoop_fanout::0 2916480 99.87% 99.87% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::1 3691 0.13% 100.00% # Request fanout histogram | 1160system.cpu.toL2Bus.snoop_fanout::0 2834170 99.88% 99.88% # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::1 3428 0.12% 100.00% # Request fanout histogram |
| 1169system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1162system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1173system.cpu.toL2Bus.snoop_fanout::total 2920171 # Request fanout histogram 1174system.cpu.toL2Bus.reqLayer0.occupancy 4411678000 # Layer occupancy (ticks) | 1166system.cpu.toL2Bus.snoop_fanout::total 2837598 # Request fanout histogram 1167system.cpu.toL2Bus.reqLayer0.occupancy 4413188000 # Layer occupancy (ticks) |
| 1175system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1176system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 1177system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1168system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1169system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 1170system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1178system.cpu.toL2Bus.respLayer0.occupancy 1613546403 # Layer occupancy (ticks) | 1171system.cpu.toL2Bus.respLayer0.occupancy 1614811393 # Layer occupancy (ticks) |
| 1179system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1172system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1180system.cpu.toL2Bus.respLayer1.occupancy 2121618679 # Layer occupancy (ticks) | 1173system.cpu.toL2Bus.respLayer1.occupancy 2121037981 # Layer occupancy (ticks) |
| 1181system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1182system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1183system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1184system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1185system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1186system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1187system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1188system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1189system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1190system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1191system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1192system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1193system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 1174system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1175system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1176system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1177system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1178system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1179system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1180system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1181system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1182system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1183system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1184system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1185system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1186system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 1194system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states | 1187system.iobus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states |
| 1195system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1196system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 1188system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1189system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 1197system.iobus.trans_dist::WriteReq 51151 # Transaction distribution 1198system.iobus.trans_dist::WriteResp 51151 # Transaction distribution 1199system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) | 1190system.iobus.trans_dist::WriteReq 51150 # Transaction distribution 1191system.iobus.trans_dist::WriteResp 51150 # Transaction distribution 1192system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) |
| 1200system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1201system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1202system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1203system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1204system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 1205system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1206system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1207system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) | 1193system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1195system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1196system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1197system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 1198system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1199system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1200system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) |
| 1208system.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes) | 1201system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) |
| 1209system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1210system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 1202system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1203system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 1211system.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes) 1212system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes) | 1204system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 1205system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) |
| 1213system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1217system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1218system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1219system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1220system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) | 1206system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1210system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1211system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1212system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) |
| 1221system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) | 1214system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) |
| 1222system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1223system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) | 1215system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) |
| 1224system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) 1225system.iobus.reqLayer0.occupancy 5364000 # Layer occupancy (ticks) | 1217system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 1218system.iobus.reqLayer0.occupancy 5361000 # Layer occupancy (ticks) |
| 1226system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1219system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1227system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) | 1220system.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) |
| 1228system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1229system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 1230system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1231system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1232system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) | 1221system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1222system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 1223system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1224system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1225system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
| 1233system.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks) | 1226system.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks) |
| 1234system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) | 1227system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) |
| 1235system.iobus.reqLayer23.occupancy 14181000 # Layer occupancy (ticks) | 1228system.iobus.reqLayer23.occupancy 14040000 # Layer occupancy (ticks) |
| 1236system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1229system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1237system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) | 1230system.iobus.reqLayer24.occupancy 2177500 # Layer occupancy (ticks) |
| 1238system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1231system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1239system.iobus.reqLayer25.occupancy 6052000 # Layer occupancy (ticks) | 1232system.iobus.reqLayer25.occupancy 6050500 # Layer occupancy (ticks) |
| 1240system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1241system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) 1242system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1233system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1234system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) 1235system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1243system.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks) | 1236system.iobus.reqLayer27.occupancy 216173801 # Layer occupancy (ticks) |
| 1244system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) | 1237system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) |
| 1245system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) | 1238system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) |
| 1246system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1247system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1248system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1239system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1240system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1241system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1249system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states | 1242system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states |
| 1250system.iocache.tags.replacements 41685 # number of replacements | 1243system.iocache.tags.replacements 41685 # number of replacements |
| 1251system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use | 1244system.iocache.tags.tagsinuse 1.258860 # Cycle average of tags in use |
| 1252system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1253system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1254system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1245system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1246system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1247system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1255system.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit. 1256system.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor 1257system.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy 1258system.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy | 1248system.iocache.tags.warmup_cycle 1712294555000 # Cycle when the warmup percentage was hit. 1249system.iocache.tags.occ_blocks::tsunami.ide 1.258860 # Average occupied blocks per requestor 1250system.iocache.tags.occ_percent::tsunami.ide 0.078679 # Average percentage of cache occupancy 1251system.iocache.tags.occ_percent::total 0.078679 # Average percentage of cache occupancy |
| 1259system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1260system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1261system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1262system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1263system.iocache.tags.data_accesses 375525 # Number of data accesses | 1252system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1253system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1254system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1255system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1256system.iocache.tags.data_accesses 375525 # Number of data accesses |
| 1264system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states | 1257system.iocache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states |
| 1265system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1266system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1267system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1268system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1269system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1270system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1271system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1272system.iocache.overall_misses::total 41725 # number of overall misses | 1258system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1259system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1260system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1261system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1262system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1263system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1264system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1265system.iocache.overall_misses::total 41725 # number of overall misses |
| 1273system.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles 1274system.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles 1275system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles 1276system.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles 1277system.iocache.demand_miss_latency::tsunami.ide 5268272163 # number of demand (read+write) miss cycles 1278system.iocache.demand_miss_latency::total 5268272163 # number of demand (read+write) miss cycles 1279system.iocache.overall_miss_latency::tsunami.ide 5268272163 # number of overall miss cycles 1280system.iocache.overall_miss_latency::total 5268272163 # number of overall miss cycles | 1266system.iocache.ReadReq_miss_latency::tsunami.ide 21845883 # number of ReadReq miss cycles 1267system.iocache.ReadReq_miss_latency::total 21845883 # number of ReadReq miss cycles 1268system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858784918 # number of WriteLineReq miss cycles 1269system.iocache.WriteLineReq_miss_latency::total 4858784918 # number of WriteLineReq miss cycles 1270system.iocache.demand_miss_latency::tsunami.ide 4880630801 # number of demand (read+write) miss cycles 1271system.iocache.demand_miss_latency::total 4880630801 # number of demand (read+write) miss cycles 1272system.iocache.overall_miss_latency::tsunami.ide 4880630801 # number of overall miss cycles 1273system.iocache.overall_miss_latency::total 4880630801 # number of overall miss cycles |
| 1281system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1282system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1283system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1284system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1285system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1286system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1287system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1288system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1289system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1290system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1291system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1292system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1293system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1294system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1295system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1296system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1274system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1275system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1276system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1277system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1278system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1279system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1280system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1281system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1282system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1283system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1284system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1285system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1286system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1287system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1288system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1289system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1297system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451 # average ReadReq miss latency 1298system.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency 1299system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency 1300system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency 1301system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency 1302system.iocache.demand_avg_miss_latency::total 126261.765440 # average overall miss latency 1303system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency 1304system.iocache.overall_avg_miss_latency::total 126261.765440 # average overall miss latency 1305system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked | 1290system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126276.780347 # average ReadReq miss latency 1291system.iocache.ReadReq_avg_miss_latency::total 126276.780347 # average ReadReq miss latency 1292system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116932.636648 # average WriteLineReq miss latency 1293system.iocache.WriteLineReq_avg_miss_latency::total 116932.636648 # average WriteLineReq miss latency 1294system.iocache.demand_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency 1295system.iocache.demand_avg_miss_latency::total 116971.379293 # average overall miss latency 1296system.iocache.overall_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency 1297system.iocache.overall_avg_miss_latency::total 116971.379293 # average overall miss latency 1298system.iocache.blocked_cycles::no_mshrs 8 # number of cycles access was blocked |
| 1306system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1307system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked 1308system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1299system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1300system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked 1301system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1309system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked | 1302system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked |
| 1310system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1311system.iocache.writebacks::writebacks 41512 # number of writebacks 1312system.iocache.writebacks::total 41512 # number of writebacks 1313system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1314system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1315system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1316system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1317system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1318system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1319system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1320system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 1303system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1304system.iocache.writebacks::writebacks 41512 # number of writebacks 1305system.iocache.writebacks::total 41512 # number of writebacks 1306system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1307system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1308system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1309system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1310system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1311system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1312system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1313system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 1321system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles 1322system.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles 1323system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles 1324system.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles 1325system.iocache.demand_mshr_miss_latency::tsunami.ide 3180227354 # number of demand (read+write) MSHR miss cycles 1326system.iocache.demand_mshr_miss_latency::total 3180227354 # number of demand (read+write) MSHR miss cycles 1327system.iocache.overall_mshr_miss_latency::tsunami.ide 3180227354 # number of overall MSHR miss cycles 1328system.iocache.overall_mshr_miss_latency::total 3180227354 # number of overall MSHR miss cycles | 1314system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13195883 # number of ReadReq MSHR miss cycles 1315system.iocache.ReadReq_mshr_miss_latency::total 13195883 # number of ReadReq MSHR miss cycles 1316system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778792164 # number of WriteLineReq MSHR miss cycles 1317system.iocache.WriteLineReq_mshr_miss_latency::total 2778792164 # number of WriteLineReq MSHR miss cycles 1318system.iocache.demand_mshr_miss_latency::tsunami.ide 2791988047 # number of demand (read+write) MSHR miss cycles 1319system.iocache.demand_mshr_miss_latency::total 2791988047 # number of demand (read+write) MSHR miss cycles 1320system.iocache.overall_mshr_miss_latency::tsunami.ide 2791988047 # number of overall MSHR miss cycles 1321system.iocache.overall_mshr_miss_latency::total 2791988047 # number of overall MSHR miss cycles |
| 1329system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1330system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1331system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1332system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1333system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1334system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1335system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1336system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1322system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1323system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1324system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1325system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1326system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1327system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1328system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1329system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1337system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency 1338system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency 1339system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency 1340system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency 1341system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency 1342system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency 1343system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency 1344system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency 1345system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states | 1330system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76276.780347 # average ReadReq mshr miss latency 1331system.iocache.ReadReq_avg_mshr_miss_latency::total 76276.780347 # average ReadReq mshr miss latency 1332system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66875.052079 # average WriteLineReq mshr miss latency 1333system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66875.052079 # average WriteLineReq mshr miss latency 1334system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency 1335system.iocache.demand_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency 1336system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency 1337system.iocache.overall_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency 1338system.membus.snoop_filter.tot_requests 825555 # Total number of requests made to the snoop filter. 1339system.membus.snoop_filter.hit_single_requests 380464 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1340system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1341system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1342system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1343system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1344system.membus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states |
| 1346system.membus.trans_dist::ReadReq 6930 # Transaction distribution | 1345system.membus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1347system.membus.trans_dist::ReadResp 296606 # Transaction distribution 1348system.membus.trans_dist::WriteReq 9599 # Transaction distribution 1349system.membus.trans_dist::WriteResp 9599 # Transaction distribution 1350system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution 1351system.membus.trans_dist::CleanEvict 261864 # Transaction distribution 1352system.membus.trans_dist::UpgradeReq 278 # Transaction distribution 1353system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution | 1346system.membus.trans_dist::ReadResp 296639 # Transaction distribution 1347system.membus.trans_dist::WriteReq 9598 # Transaction distribution 1348system.membus.trans_dist::WriteResp 9598 # Transaction distribution 1349system.membus.trans_dist::WritebackDirty 117638 # Transaction distribution 1350system.membus.trans_dist::CleanEvict 261892 # Transaction distribution 1351system.membus.trans_dist::UpgradeReq 135 # Transaction distribution |
| 1354system.membus.trans_dist::UpgradeResp 3 # Transaction distribution | 1352system.membus.trans_dist::UpgradeResp 3 # Transaction distribution |
| 1355system.membus.trans_dist::ReadExReq 114558 # Transaction distribution 1356system.membus.trans_dist::ReadExResp 114558 # Transaction distribution 1357system.membus.trans_dist::ReadSharedReq 289719 # Transaction distribution 1358system.membus.trans_dist::BadAddressError 43 # Transaction distribution | 1353system.membus.trans_dist::ReadExReq 114572 # Transaction distribution 1354system.membus.trans_dist::ReadExResp 114572 # Transaction distribution 1355system.membus.trans_dist::ReadSharedReq 289754 # Transaction distribution 1356system.membus.trans_dist::BadAddressError 45 # Transaction distribution |
| 1359system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution | 1357system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 1360system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) 1361system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145930 # Packet count per connected master and slave (bytes) 1362system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 86 # Packet count per connected master and slave (bytes) 1363system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179074 # Packet count per connected master and slave (bytes) | 1358system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 1359system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145919 # Packet count per connected master and slave (bytes) 1360system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) 1361system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179065 # Packet count per connected master and slave (bytes) |
| 1364system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1365system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) | 1362system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1363system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) |
| 1366system.membus.pkt_count::total 1262499 # Packet count per connected master and slave (bytes) 1367system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) 1368system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30713088 # Cumulative packet size per connected master and slave (bytes) 1369system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757244 # Cumulative packet size per connected master and slave (bytes) | 1364system.membus.pkt_count::total 1262490 # Packet count per connected master and slave (bytes) 1365system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 1366system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30717248 # Cumulative packet size per connected master and slave (bytes) 1367system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30761396 # Cumulative packet size per connected master and slave (bytes) |
| 1370system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1371system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) | 1368system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1369system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) |
| 1372system.membus.pkt_size::total 33414972 # Cumulative packet size per connected master and slave (bytes) | 1370system.membus.pkt_size::total 33419124 # Cumulative packet size per connected master and slave (bytes) |
| 1373system.membus.snoops 438 # Total snoops (count) 1374system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) | 1371system.membus.snoops 438 # Total snoops (count) 1372system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) |
| 1375system.membus.snoop_fanout::samples 842137 # Request fanout histogram 1376system.membus.snoop_fanout::mean 1 # Request fanout histogram 1377system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 1373system.membus.snoop_fanout::samples 462541 # Request fanout histogram 1374system.membus.snoop_fanout::mean 0.001500 # Request fanout histogram 1375system.membus.snoop_fanout::stdev 0.038706 # Request fanout histogram |
| 1378system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1376system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1379system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1380system.membus.snoop_fanout::1 842137 100.00% 100.00% # Request fanout histogram | 1377system.membus.snoop_fanout::0 461847 99.85% 99.85% # Request fanout histogram 1378system.membus.snoop_fanout::1 694 0.15% 100.00% # Request fanout histogram |
| 1381system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1382system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1379system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1380system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1383system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 1381system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1384system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1382system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1385system.membus.snoop_fanout::total 842137 # Request fanout histogram 1386system.membus.reqLayer0.occupancy 28883000 # Layer occupancy (ticks) | 1383system.membus.snoop_fanout::total 462541 # Request fanout histogram 1384system.membus.reqLayer0.occupancy 28740000 # Layer occupancy (ticks) |
| 1387system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1385system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1388system.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks) | 1386system.membus.reqLayer1.occupancy 1314155780 # Layer occupancy (ticks) |
| 1389system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1387system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1390system.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks) | 1388system.membus.reqLayer2.occupancy 57000 # Layer occupancy (ticks) |
| 1391system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1389system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1392system.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks) | 1390system.membus.respLayer1.occupancy 2139053000 # Layer occupancy (ticks) |
| 1393system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1394system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) 1395system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1391system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1392system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) 1393system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1396system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1397system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1398system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1399system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1400system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states | 1394system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1395system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1396system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1397system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1398system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states |
| 1401system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1402system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1403system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1404system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1405system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1406system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1407system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1408system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1424system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1425system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1426system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1427system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1428system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1429system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1430system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1431system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 1399system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1400system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1401system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1402system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1403system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1404system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1405system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1406system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1422system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1423system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1424system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1425system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1426system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1427system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1428system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1429system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1432system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1433system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1434system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1435system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1436system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1437system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1438system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1439system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1440system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1441system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1442system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1443system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1444system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1445system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1446system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1447system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1448system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1449system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1450system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1451system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1452system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1453system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1454system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states | 1430system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1431system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1432system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1433system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1434system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1435system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1436system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1437system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1438system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1439system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1440system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1441system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1442system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1443system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1444system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1445system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1446system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1447system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1448system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1449system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1450system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1451system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states 1452system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states |
| 1455system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1453system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1456system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed 1457system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed 1458system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl | 1454system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 1455system.cpu.kern.inst.hwrei 210996 # number of hwrei instructions executed 1456system.cpu.kern.ipl_count::0 74658 40.97% 40.97% # number of times we switched to this ipl |
| 1459system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl | 1457system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl |
| 1460system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl 1461system.cpu.kern.ipl_count::31 105584 57.93% 100.00% # number of times we switched to this ipl 1462system.cpu.kern.ipl_count::total 182266 # number of times we switched to this ipl 1463system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 1458system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1459system.cpu.kern.ipl_count::31 105558 57.93% 100.00% # number of times we switched to this ipl 1460system.cpu.kern.ipl_count::total 182227 # number of times we switched to this ipl 1461system.cpu.kern.ipl_good::0 73291 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 1464system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl | 1462system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl |
| 1465system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1466system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1467system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl 1468system.cpu.kern.ipl_ticks::0 1818987792000 96.92% 96.92% # number of cycles we spent at this ipl 1469system.cpu.kern.ipl_ticks::21 67503500 0.00% 96.92% # number of cycles we spent at this ipl 1470system.cpu.kern.ipl_ticks::22 563118000 0.03% 96.95% # number of cycles we spent at this ipl 1471system.cpu.kern.ipl_ticks::31 57175249500 3.05% 100.00% # number of cycles we spent at this ipl 1472system.cpu.kern.ipl_ticks::total 1876793663000 # number of cycles we spent at this ipl 1473system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl | 1463system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1464system.cpu.kern.ipl_good::31 73291 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1465system.cpu.kern.ipl_good::total 148593 # number of times we switched to this ipl from a different ipl 1466system.cpu.kern.ipl_ticks::0 1818067214500 97.64% 97.64% # number of cycles we spent at this ipl 1467system.cpu.kern.ipl_ticks::21 67498000 0.00% 97.64% # number of cycles we spent at this ipl 1468system.cpu.kern.ipl_ticks::22 564111500 0.03% 97.67% # number of cycles we spent at this ipl 1469system.cpu.kern.ipl_ticks::31 43342412500 2.33% 100.00% # number of cycles we spent at this ipl 1470system.cpu.kern.ipl_ticks::total 1862041236500 # number of cycles we spent at this ipl 1471system.cpu.kern.ipl_used::0 0.981690 # fraction of swpipl calls that actually changed the ipl |
| 1474system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1475system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 1472system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1473system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 1476system.cpu.kern.ipl_used::31 0.694262 # fraction of swpipl calls that actually changed the ipl 1477system.cpu.kern.ipl_used::total 0.815391 # fraction of swpipl calls that actually changed the ipl | 1474system.cpu.kern.ipl_used::31 0.694320 # fraction of swpipl calls that actually changed the ipl 1475system.cpu.kern.ipl_used::total 0.815428 # fraction of swpipl calls that actually changed the ipl |
| 1478system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1479system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1480system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1481system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1482system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1483system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1484system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1485system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 1508system.cpu.kern.syscall::total 326 # number of syscalls executed 1509system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1510system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1511system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1512system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1513system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1514system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1515system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed | 1476system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1477system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1478system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1479system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1480system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1481system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1482system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1483system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 1506system.cpu.kern.syscall::total 326 # number of syscalls executed 1507system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1508system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1509system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1510system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1511system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1512system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1513system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed |
| 1516system.cpu.kern.callpal::swpipl 175147 91.23% 93.43% # number of callpals executed 1517system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed | 1514system.cpu.kern.callpal::swpipl 175110 91.22% 93.43% # number of callpals executed 1515system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed |
| 1518system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1519system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1520system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1521system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed | 1516system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1517system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1518system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1519system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed |
| 1522system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed | 1520system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed |
| 1523system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1524system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 1521system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1522system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 1525system.cpu.kern.callpal::total 191994 # number of callpals executed 1526system.cpu.kern.mode_switch::kernel 5854 # number of protection mode switches 1527system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 1528system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 1529system.cpu.kern.mode_good::kernel 1910 1530system.cpu.kern.mode_good::user 1740 | 1523system.cpu.kern.callpal::total 191955 # number of callpals executed 1524system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches 1525system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 1526system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 1527system.cpu.kern.mode_good::kernel 1909 1528system.cpu.kern.mode_good::user 1739 |
| 1531system.cpu.kern.mode_good::idle 170 | 1529system.cpu.kern.mode_good::idle 170 |
| 1532system.cpu.kern.mode_switch_good::kernel 0.326273 # fraction of useful protection mode switches | 1530system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches |
| 1533system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1531system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1534system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches 1535system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches 1536system.cpu.kern.mode_ticks::kernel 30164955000 1.61% 1.61% # number of ticks spent at the given mode 1537system.cpu.kern.mode_ticks::user 2918722500 0.16% 1.76% # number of ticks spent at the given mode 1538system.cpu.kern.mode_ticks::idle 1843709977500 98.24% 100.00% # number of ticks spent at the given mode | 1532system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 1533system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches 1534system.cpu.kern.mode_ticks::kernel 29461996000 1.58% 1.58% # number of ticks spent at the given mode 1535system.cpu.kern.mode_ticks::user 2701361000 0.15% 1.73% # number of ticks spent at the given mode 1536system.cpu.kern.mode_ticks::idle 1829877871500 98.27% 100.00% # number of ticks spent at the given mode |
| 1539system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1540 1541---------- End Simulation Statistics ---------- | 1537system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1538 1539---------- End Simulation Statistics ---------- |