Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

stats.txt (11502:e273e86a873d)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.876794 # Number of seconds simulated 4sim_ticks 1876794488000 # Number of ticks simulated 5final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.876794 # Number of seconds simulated 4sim_ticks 1876794488000 # Number of ticks simulated 5final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 156335 # Simulator instruction rate (inst/s) 8host_op_rate 156335 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5537786455 # Simulator tick rate (ticks/s) 10host_mem_usage 329540 # Number of bytes of host memory used 11host_seconds 338.91 # Real time elapsed on the host	7host_inst_rate 191271 # Simulator instruction rate (inst/s) 8host_op_rate 191271 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6775305946 # Simulator tick rate (ticks/s) 10host_mem_usage 377772 # Number of bytes of host memory used 11host_seconds 277.01 # Real time elapsed on the host
12sim_insts 52982943 # Number of instructions simulated 13sim_ops 52982943 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 52982943 # Number of instructions simulated 13sim_ops 52982943 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7527680 # Number of bytes written to this memory --- 269 unchanged lines hidden (view full) --- 293system.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ) 294system.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ) 295system.physmem_1.averagePower 670.573928 # Core power per rank (mW) 296system.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states 297system.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states 298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states 300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states	17system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7527680 # Number of bytes written to this memory --- 269 unchanged lines hidden (view full) --- 294system.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ) 295system.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ) 296system.physmem_1.averagePower 670.573928 # Core power per rank (mW) 297system.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states 298system.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states 299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 300system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states 301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
	302system.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 303system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
301system.cpu.branchPred.lookups 19569408 # Number of BP lookups 302system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted 303system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect 304system.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups 305system.cpu.branchPred.BTBHits 5420664 # Number of BTB hits 306system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 307system.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage 308system.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target. --- 30 unchanged lines hidden (view full) --- 339system.cpu.itb.write_hits 0 # DTB write hits 340system.cpu.itb.write_misses 0 # DTB write misses 341system.cpu.itb.write_acv 0 # DTB write access violations 342system.cpu.itb.write_accesses 0 # DTB write accesses 343system.cpu.itb.data_hits 0 # DTB hits 344system.cpu.itb.data_misses 0 # DTB misses 345system.cpu.itb.data_acv 0 # DTB access violations 346system.cpu.itb.data_accesses 0 # DTB accesses	304system.cpu.branchPred.lookups 19569408 # Number of BP lookups 305system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted 306system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect 307system.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups 308system.cpu.branchPred.BTBHits 5420664 # Number of BTB hits 309system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 310system.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage 311system.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target. --- 30 unchanged lines hidden (view full) --- 342system.cpu.itb.write_hits 0 # DTB write hits 343system.cpu.itb.write_misses 0 # DTB write misses 344system.cpu.itb.write_acv 0 # DTB write access violations 345system.cpu.itb.write_accesses 0 # DTB write accesses 346system.cpu.itb.data_hits 0 # DTB hits 347system.cpu.itb.data_misses 0 # DTB misses 348system.cpu.itb.data_acv 0 # DTB access violations 349system.cpu.itb.data_accesses 0 # DTB accesses
	350system.cpu.numPwrStateTransitions 12876 # Number of power state transitions 351system.cpu.pwrStateClkGateDist::samples 6438 # Distribution of time spent in the clock gated state 352system.cpu.pwrStateClkGateDist::mean 279467835.818577 # Distribution of time spent in the clock gated state 353system.cpu.pwrStateClkGateDist::stdev 439243252.658256 # Distribution of time spent in the clock gated state 354system.cpu.pwrStateClkGateDist::1000-5e+10 6438 100.00% 100.00% # Distribution of time spent in the clock gated state 355system.cpu.pwrStateClkGateDist::min_value 81000 # Distribution of time spent in the clock gated state 356system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 357system.cpu.pwrStateClkGateDist::total 6438 # Distribution of time spent in the clock gated state 358system.cpu.pwrStateResidencyTicks::ON 77580561000 # Cumulative time (in ticks) in various power states 359system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000 # Cumulative time (in ticks) in various power states
347system.cpu.numCycles 155167561 # number of cpu cycles simulated 348system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 349system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 350system.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss 351system.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed 352system.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered 353system.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken 354system.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked --- 280 unchanged lines hidden (view full) --- 635system.cpu.ipc 0.341456 # IPC: Instructions Per Cycle 636system.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads 637system.cpu.int_regfile_reads 77864960 # number of integer regfile reads 638system.cpu.int_regfile_writes 42584488 # number of integer regfile writes 639system.cpu.fp_regfile_reads 166613 # number of floating regfile reads 640system.cpu.fp_regfile_writes 175794 # number of floating regfile writes 641system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads 642system.cpu.misc_regfile_writes 939529 # number of misc regfile writes	360system.cpu.numCycles 155167561 # number of cpu cycles simulated 361system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 362system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 363system.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss 364system.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed 365system.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered 366system.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken 367system.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked --- 280 unchanged lines hidden (view full) --- 648system.cpu.ipc 0.341456 # IPC: Instructions Per Cycle 649system.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads 650system.cpu.int_regfile_reads 77864960 # number of integer regfile reads 651system.cpu.int_regfile_writes 42584488 # number of integer regfile writes 652system.cpu.fp_regfile_reads 166613 # number of floating regfile reads 653system.cpu.fp_regfile_writes 175794 # number of floating regfile writes 654system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads 655system.cpu.misc_regfile_writes 939529 # number of misc regfile writes
	656system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
643system.cpu.dcache.tags.replacements 1405900 # number of replacements 644system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use 645system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks. 646system.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks. 647system.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks. 648system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 649system.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor 650system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 651system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy 652system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 653system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id 654system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 655system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id 656system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 657system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses 658system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses	657system.cpu.dcache.tags.replacements 1405900 # number of replacements 658system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use 659system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks. 660system.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks. 661system.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks. 662system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 663system.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor 664system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 665system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy 666system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 667system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id 668system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 669system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id 670system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 671system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses 672system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses
	673system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
659system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits 660system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits 661system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits 662system.cpu.dcache.WriteReq_hits::total 4181578 # number of WriteReq hits 663system.cpu.dcache.LoadLockedReq_hits::cpu.data 212474 # number of LoadLockedReq hits 664system.cpu.dcache.LoadLockedReq_hits::total 212474 # number of LoadLockedReq hits 665system.cpu.dcache.StoreCondReq_hits::cpu.data 215675 # number of StoreCondReq hits 666system.cpu.dcache.StoreCondReq_hits::total 215675 # number of StoreCondReq hits --- 136 unchanged lines hidden (view full) --- 803system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 804system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 805system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 806system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 807system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency 808system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency 809system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency 810system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency	674system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits 675system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits 676system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits 677system.cpu.dcache.WriteReq_hits::total 4181578 # number of WriteReq hits 678system.cpu.dcache.LoadLockedReq_hits::cpu.data 212474 # number of LoadLockedReq hits 679system.cpu.dcache.LoadLockedReq_hits::total 212474 # number of LoadLockedReq hits 680system.cpu.dcache.StoreCondReq_hits::cpu.data 215675 # number of StoreCondReq hits 681system.cpu.dcache.StoreCondReq_hits::total 215675 # number of StoreCondReq hits --- 136 unchanged lines hidden (view full) --- 818system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 819system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 820system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 821system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 822system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency 823system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency 824system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency 825system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency
	826system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
811system.cpu.icache.tags.replacements 1074186 # number of replacements 812system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use 813system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. 814system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks. 815system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks. 816system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit. 817system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor 818system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy 819system.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy 820system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 821system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 822system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id 823system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id 824system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 825system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses 826system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses	827system.cpu.icache.tags.replacements 1074186 # number of replacements 828system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use 829system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. 830system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks. 831system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks. 832system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit. 833system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor 834system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy 835system.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy 836system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id 840system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 841system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses 842system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses
	843system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
827system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits 828system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits 829system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits 830system.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits 831system.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits 832system.cpu.icache.overall_hits::total 8786985 # number of overall hits 833system.cpu.icache.ReadReq_misses::cpu.inst 1143615 # number of ReadReq misses 834system.cpu.icache.ReadReq_misses::total 1143615 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 893system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses 894system.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses 895system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency 896system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency 897system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 898system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency 899system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 900system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency	844system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits 845system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits 846system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits 847system.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits 848system.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits 849system.cpu.icache.overall_hits::total 8786985 # number of overall hits 850system.cpu.icache.ReadReq_misses::cpu.inst 1143615 # number of ReadReq misses 851system.cpu.icache.ReadReq_misses::total 1143615 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses 911system.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses 912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency 914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency 916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency
	918system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
901system.cpu.l2cache.tags.replacements 338591 # number of replacements 902system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use 903system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks. 904system.cpu.l2cache.tags.sampled_refs 403759 # Sample count of references to valid blocks. 905system.cpu.l2cache.tags.avg_refs 10.534943 # Average number of references to valid blocks. 906system.cpu.l2cache.tags.warmup_cycle 9186566000 # Cycle when the warmup percentage was hit. 907system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616 # Average occupied blocks per requestor 908system.cpu.l2cache.tags.occ_blocks::cpu.inst 5255.268427 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 915system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id 916system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3471 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3347 # Occupied blocks per task id 918system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2431 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55427 # Occupied blocks per task id 920system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id 921system.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses 922system.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses	919system.cpu.l2cache.tags.replacements 338591 # number of replacements 920system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use 921system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks. 922system.cpu.l2cache.tags.sampled_refs 403759 # Sample count of references to valid blocks. 923system.cpu.l2cache.tags.avg_refs 10.534943 # Average number of references to valid blocks. 924system.cpu.l2cache.tags.warmup_cycle 9186566000 # Cycle when the warmup percentage was hit. 925system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616 # Average occupied blocks per requestor 926system.cpu.l2cache.tags.occ_blocks::cpu.inst 5255.268427 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 933system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id 934system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3471 # Occupied blocks per task id 935system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3347 # Occupied blocks per task id 936system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2431 # Occupied blocks per task id 937system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55427 # Occupied blocks per task id 938system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id 939system.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses 940system.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses
	941system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
923system.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits 924system.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits 925system.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits 926system.cpu.l2cache.WritebackClean_hits::total 1073682 # number of WritebackClean hits 927system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits 928system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits 929system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 88 # number of SCUpgradeReq hits 930system.cpu.l2cache.SCUpgradeReq_hits::total 88 # number of SCUpgradeReq hits --- 180 unchanged lines hidden (view full) --- 1111system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency 1112system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency 1113system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter. 1114system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1115system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1116system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 1117system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1118system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	942system.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits 943system.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits 944system.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits 945system.cpu.l2cache.WritebackClean_hits::total 1073682 # number of WritebackClean hits 946system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits 947system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits 948system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 88 # number of SCUpgradeReq hits 949system.cpu.l2cache.SCUpgradeReq_hits::total 88 # number of SCUpgradeReq hits --- 180 unchanged lines hidden (view full) --- 1130system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency 1131system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency 1132system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter. 1133system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1134system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1135system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 1136system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1137system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	1138system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1119system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 1165system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1166system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1167system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1168system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1169system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1170system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1171system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1172system.disk2.dma_write_txs 1 # Number of DMA write transactions.	1139system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 1140system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution 1141system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 1185system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1186system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1187system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1188system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1189system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1190system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1191system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1192system.disk2.dma_write_txs 1 # Number of DMA write transactions.
	1193system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1173system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1174system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 1175system.iobus.trans_dist::WriteReq 51151 # Transaction distribution 1176system.iobus.trans_dist::WriteResp 51151 # Transaction distribution 1177system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 38 unchanged lines hidden (view full) --- 1219system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) 1220system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1221system.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks) 1222system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1223system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) 1224system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1225system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1226system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)	1194system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1195system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 1196system.iobus.trans_dist::WriteReq 51151 # Transaction distribution 1197system.iobus.trans_dist::WriteResp 51151 # Transaction distribution 1198system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) 1199system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1200system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1201system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 38 unchanged lines hidden (view full) --- 1240system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) 1241system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1242system.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks) 1243system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1244system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) 1245system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1246system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1247system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
	1248system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1227system.iocache.tags.replacements 41685 # number of replacements 1228system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use 1229system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1230system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1231system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1232system.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit. 1233system.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor 1234system.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy 1235system.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy 1236system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1237system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1238system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1239system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1240system.iocache.tags.data_accesses 375525 # Number of data accesses	1249system.iocache.tags.replacements 41685 # number of replacements 1250system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use 1251system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1252system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1253system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1254system.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit. 1255system.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor 1256system.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy 1257system.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy 1258system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1259system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1260system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1261system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1262system.iocache.tags.data_accesses 375525 # Number of data accesses
	1263system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1241system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1242system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1243system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1244system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1245system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1246system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1247system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1248system.iocache.overall_misses::total 41725 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1313system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency 1314system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency 1315system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency 1316system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency 1317system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency 1318system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency 1319system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency 1320system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency	1264system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1265system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1266system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1267system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1268system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1269system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1270system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1271system.iocache.overall_misses::total 41725 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1336system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency 1337system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency 1338system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency 1339system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency 1340system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency 1341system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency 1342system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency 1343system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
	1344system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1321system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1322system.membus.trans_dist::ReadResp 296606 # Transaction distribution 1323system.membus.trans_dist::WriteReq 9599 # Transaction distribution 1324system.membus.trans_dist::WriteResp 9599 # Transaction distribution 1325system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution 1326system.membus.trans_dist::CleanEvict 261864 # Transaction distribution 1327system.membus.trans_dist::UpgradeReq 278 # Transaction distribution 1328system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution --- 33 unchanged lines hidden (view full) --- 1362system.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks) 1363system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1364system.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks) 1365system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1366system.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks) 1367system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1368system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) 1369system.membus.respLayer2.utilization 0.0 # Layer utilization (%)	1345system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1346system.membus.trans_dist::ReadResp 296606 # Transaction distribution 1347system.membus.trans_dist::WriteReq 9599 # Transaction distribution 1348system.membus.trans_dist::WriteResp 9599 # Transaction distribution 1349system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution 1350system.membus.trans_dist::CleanEvict 261864 # Transaction distribution 1351system.membus.trans_dist::UpgradeReq 278 # Transaction distribution 1352system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution --- 33 unchanged lines hidden (view full) --- 1386system.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks) 1387system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1388system.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks) 1389system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1390system.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks) 1391system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1392system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) 1393system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
	1394system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1395system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1396system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1397system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1398system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1370system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1371system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1372system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1373system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1374system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1375system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1376system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1377system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1393system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1394system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1395system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1396system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1397system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1398system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1399system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1400system.tsunami.ethernet.droppedPackets 0 # number of packets dropped	1399system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1400system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1401system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1402system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1403system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1404system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1405system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1406system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1422system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1423system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1424system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1425system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1426system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1427system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1428system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1429system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
	1430system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1431system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1432system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1433system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1434system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1435system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1436system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1437system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1438system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1439system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1440system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1441system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1442system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1443system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1444system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1445system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1446system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1447system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1448system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1449system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1450system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1451system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states 1452system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1401system.cpu.kern.inst.arm 0 # number of arm instructions executed 1402system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed 1403system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed 1404system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl 1405system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1406system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl 1407system.cpu.kern.ipl_count::31 105584 57.93% 100.00% # number of times we switched to this ipl 1408system.cpu.kern.ipl_count::total 182266 # number of times we switched to this ipl --- 79 unchanged lines hidden ---	1453system.cpu.kern.inst.arm 0 # number of arm instructions executed 1454system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed 1455system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed 1456system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl 1457system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1458system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl 1459system.cpu.kern.ipl_count::31 105584 57.93% 100.00% # number of times we switched to this ipl 1460system.cpu.kern.ipl_count::total 182266 # number of times we switched to this ipl --- 79 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.876794 # Number of seconds simulated
4sim_ticks 1876794488000 # Number of ticks simulated
5final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 156335 # Simulator instruction rate (inst/s)
8host_op_rate 156335 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5537786455 # Simulator tick rate (ticks/s)
10host_mem_usage 329540 # Number of bytes of host memory used
11host_seconds 338.91 # Real time elapsed on the host

7host_inst_rate 191271 # Simulator instruction rate (inst/s)
8host_op_rate 191271 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 6775305946 # Simulator tick rate (ticks/s)
10host_mem_usage 377772 # Number of bytes of host memory used
11host_seconds 277.01 # Real time elapsed on the host

12sim_insts 52982943 # Number of instructions simulated
13sim_ops 52982943 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7527680 # Number of bytes written to this memory

--- 269 unchanged lines hidden (view full) ---

293system.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ)
294system.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ)
295system.physmem_1.averagePower 670.573928 # Core power per rank (mW)
296system.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states
297system.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states
298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
299system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states
300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

17system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory
19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
20system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory
21system.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory
23system.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory
24system.physmem.bytes_written::total 7527680 # Number of bytes written to this memory

--- 269 unchanged lines hidden (view full) ---

294system.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ)
295system.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ)
296system.physmem_1.averagePower 670.573928 # Core power per rank (mW)
297system.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states
298system.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states
299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
300system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states
301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

302system.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
303system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

301system.cpu.branchPred.lookups 19569408 # Number of BP lookups
302system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted
303system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect
304system.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups
305system.cpu.branchPred.BTBHits 5420664 # Number of BTB hits
306system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
307system.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage
308system.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target.

--- 30 unchanged lines hidden (view full) ---

339system.cpu.itb.write_hits 0 # DTB write hits
340system.cpu.itb.write_misses 0 # DTB write misses
341system.cpu.itb.write_acv 0 # DTB write access violations
342system.cpu.itb.write_accesses 0 # DTB write accesses
343system.cpu.itb.data_hits 0 # DTB hits
344system.cpu.itb.data_misses 0 # DTB misses
345system.cpu.itb.data_acv 0 # DTB access violations
346system.cpu.itb.data_accesses 0 # DTB accesses

304system.cpu.branchPred.lookups 19569408 # Number of BP lookups
305system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted
306system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect
307system.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups
308system.cpu.branchPred.BTBHits 5420664 # Number of BTB hits
309system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
310system.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage
311system.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target.

--- 30 unchanged lines hidden (view full) ---

342system.cpu.itb.write_hits 0 # DTB write hits
343system.cpu.itb.write_misses 0 # DTB write misses
344system.cpu.itb.write_acv 0 # DTB write access violations
345system.cpu.itb.write_accesses 0 # DTB write accesses
346system.cpu.itb.data_hits 0 # DTB hits
347system.cpu.itb.data_misses 0 # DTB misses
348system.cpu.itb.data_acv 0 # DTB access violations
349system.cpu.itb.data_accesses 0 # DTB accesses

350system.cpu.numPwrStateTransitions 12876 # Number of power state transitions
351system.cpu.pwrStateClkGateDist::samples 6438 # Distribution of time spent in the clock gated state
352system.cpu.pwrStateClkGateDist::mean 279467835.818577 # Distribution of time spent in the clock gated state
353system.cpu.pwrStateClkGateDist::stdev 439243252.658256 # Distribution of time spent in the clock gated state
354system.cpu.pwrStateClkGateDist::1000-5e+10 6438 100.00% 100.00% # Distribution of time spent in the clock gated state
355system.cpu.pwrStateClkGateDist::min_value 81000 # Distribution of time spent in the clock gated state
356system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
357system.cpu.pwrStateClkGateDist::total 6438 # Distribution of time spent in the clock gated state
358system.cpu.pwrStateResidencyTicks::ON 77580561000 # Cumulative time (in ticks) in various power states
359system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000 # Cumulative time (in ticks) in various power states

347system.cpu.numCycles 155167561 # number of cpu cycles simulated
348system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
349system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
350system.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss
351system.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed
352system.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered
353system.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken
354system.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked

--- 280 unchanged lines hidden (view full) ---

635system.cpu.ipc 0.341456 # IPC: Instructions Per Cycle
636system.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads
637system.cpu.int_regfile_reads 77864960 # number of integer regfile reads
638system.cpu.int_regfile_writes 42584488 # number of integer regfile writes
639system.cpu.fp_regfile_reads 166613 # number of floating regfile reads
640system.cpu.fp_regfile_writes 175794 # number of floating regfile writes
641system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads
642system.cpu.misc_regfile_writes 939529 # number of misc regfile writes

360system.cpu.numCycles 155167561 # number of cpu cycles simulated
361system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
362system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
363system.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss
364system.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed
365system.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered
366system.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken
367system.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked

--- 280 unchanged lines hidden (view full) ---

648system.cpu.ipc 0.341456 # IPC: Instructions Per Cycle
649system.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads
650system.cpu.int_regfile_reads 77864960 # number of integer regfile reads
651system.cpu.int_regfile_writes 42584488 # number of integer regfile writes
652system.cpu.fp_regfile_reads 166613 # number of floating regfile reads
653system.cpu.fp_regfile_writes 175794 # number of floating regfile writes
654system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads
655system.cpu.misc_regfile_writes 939529 # number of misc regfile writes

656system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

643system.cpu.dcache.tags.replacements 1405900 # number of replacements
644system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use
645system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks.
646system.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks.
647system.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks.
648system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit.
649system.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor
650system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
651system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy
652system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
653system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id
654system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
655system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
656system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
657system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses
658system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses

657system.cpu.dcache.tags.replacements 1405900 # number of replacements
658system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use
659system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks.
660system.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks.
661system.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks.
662system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit.
663system.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor
664system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
665system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy
666system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
667system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id
668system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
669system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
670system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
671system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses
672system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses

673system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

659system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits
660system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits
661system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits
662system.cpu.dcache.WriteReq_hits::total 4181578 # number of WriteReq hits
663system.cpu.dcache.LoadLockedReq_hits::cpu.data 212474 # number of LoadLockedReq hits
664system.cpu.dcache.LoadLockedReq_hits::total 212474 # number of LoadLockedReq hits
665system.cpu.dcache.StoreCondReq_hits::cpu.data 215675 # number of StoreCondReq hits
666system.cpu.dcache.StoreCondReq_hits::total 215675 # number of StoreCondReq hits

--- 136 unchanged lines hidden (view full) ---

803system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency
804system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency
805system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency
806system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency
807system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency
808system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency
809system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency
810system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency

674system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits
675system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits
676system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits
677system.cpu.dcache.WriteReq_hits::total 4181578 # number of WriteReq hits
678system.cpu.dcache.LoadLockedReq_hits::cpu.data 212474 # number of LoadLockedReq hits
679system.cpu.dcache.LoadLockedReq_hits::total 212474 # number of LoadLockedReq hits
680system.cpu.dcache.StoreCondReq_hits::cpu.data 215675 # number of StoreCondReq hits
681system.cpu.dcache.StoreCondReq_hits::total 215675 # number of StoreCondReq hits

--- 136 unchanged lines hidden (view full) ---

818system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency
819system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency
820system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency
821system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency
822system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency
823system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency
824system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency
825system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency

826system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

811system.cpu.icache.tags.replacements 1074186 # number of replacements
812system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use
813system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks.
814system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks.
815system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks.
816system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit.
817system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor
818system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy
819system.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy
820system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
821system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
822system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
823system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id
824system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
825system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses
826system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses

827system.cpu.icache.tags.replacements 1074186 # number of replacements
828system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use
829system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks.
830system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks.
831system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks.
832system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit.
833system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor
834system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy
835system.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy
836system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
837system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
838system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
839system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id
840system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
841system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses
842system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses

843system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

827system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits
828system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits
829system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits
830system.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits
831system.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits
832system.cpu.icache.overall_hits::total 8786985 # number of overall hits
833system.cpu.icache.ReadReq_misses::cpu.inst 1143615 # number of ReadReq misses
834system.cpu.icache.ReadReq_misses::total 1143615 # number of ReadReq misses

--- 58 unchanged lines hidden (view full) ---

893system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses
894system.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses
895system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency
896system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency
897system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency
898system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency
899system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency
900system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency

844system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits
845system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits
846system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits
847system.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits
848system.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits
849system.cpu.icache.overall_hits::total 8786985 # number of overall hits
850system.cpu.icache.ReadReq_misses::cpu.inst 1143615 # number of ReadReq misses
851system.cpu.icache.ReadReq_misses::total 1143615 # number of ReadReq misses

--- 58 unchanged lines hidden (view full) ---

910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses
911system.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses
912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency
913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency
914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency
915system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency
916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency
917system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency

918system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

901system.cpu.l2cache.tags.replacements 338591 # number of replacements
902system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use
903system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks.
904system.cpu.l2cache.tags.sampled_refs 403759 # Sample count of references to valid blocks.
905system.cpu.l2cache.tags.avg_refs 10.534943 # Average number of references to valid blocks.
906system.cpu.l2cache.tags.warmup_cycle 9186566000 # Cycle when the warmup percentage was hit.
907system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616 # Average occupied blocks per requestor
908system.cpu.l2cache.tags.occ_blocks::cpu.inst 5255.268427 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

915system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id
916system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3471 # Occupied blocks per task id
917system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3347 # Occupied blocks per task id
918system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2431 # Occupied blocks per task id
919system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55427 # Occupied blocks per task id
920system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id
921system.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses
922system.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses

919system.cpu.l2cache.tags.replacements 338591 # number of replacements
920system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use
921system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks.
922system.cpu.l2cache.tags.sampled_refs 403759 # Sample count of references to valid blocks.
923system.cpu.l2cache.tags.avg_refs 10.534943 # Average number of references to valid blocks.
924system.cpu.l2cache.tags.warmup_cycle 9186566000 # Cycle when the warmup percentage was hit.
925system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616 # Average occupied blocks per requestor
926system.cpu.l2cache.tags.occ_blocks::cpu.inst 5255.268427 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

933system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id
934system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3471 # Occupied blocks per task id
935system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3347 # Occupied blocks per task id
936system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2431 # Occupied blocks per task id
937system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55427 # Occupied blocks per task id
938system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id
939system.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses
940system.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses

941system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

923system.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits
924system.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits
925system.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits
926system.cpu.l2cache.WritebackClean_hits::total 1073682 # number of WritebackClean hits
927system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits
928system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits
929system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 88 # number of SCUpgradeReq hits
930system.cpu.l2cache.SCUpgradeReq_hits::total 88 # number of SCUpgradeReq hits

--- 180 unchanged lines hidden (view full) ---

1111system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency
1112system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency
1113system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter.
1114system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1115system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1116system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter.
1117system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1118system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

942system.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits
943system.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits
944system.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits
945system.cpu.l2cache.WritebackClean_hits::total 1073682 # number of WritebackClean hits
946system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits
947system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits
948system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 88 # number of SCUpgradeReq hits
949system.cpu.l2cache.SCUpgradeReq_hits::total 88 # number of SCUpgradeReq hits

--- 180 unchanged lines hidden (view full) ---

1130system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency
1131system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency
1132system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter.
1133system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1134system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1135system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter.
1136system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1137system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1138system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

1119system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
1120system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution
1121system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution
1122system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution
1123system.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution
1124system.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution
1125system.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution
1126system.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution

--- 38 unchanged lines hidden (view full) ---

1165system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1166system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1167system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1168system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1169system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1170system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1171system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1172system.disk2.dma_write_txs 1 # Number of DMA write transactions.

1139system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
1140system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution
1141system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution
1142system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution
1143system.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution
1144system.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution
1145system.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution
1146system.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution

--- 38 unchanged lines hidden (view full) ---

1185system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1186system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1187system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1188system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1189system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1190system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1191system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1192system.disk2.dma_write_txs 1 # Number of DMA write transactions.

1193system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

1173system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
1174system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
1175system.iobus.trans_dist::WriteReq 51151 # Transaction distribution
1176system.iobus.trans_dist::WriteResp 51151 # Transaction distribution
1177system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes)
1178system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
1179system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1180system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)

--- 38 unchanged lines hidden (view full) ---

1219system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks)
1220system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1221system.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks)
1222system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1223system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks)
1224system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1225system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
1226system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)

1194system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
1195system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
1196system.iobus.trans_dist::WriteReq 51151 # Transaction distribution
1197system.iobus.trans_dist::WriteResp 51151 # Transaction distribution
1198system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes)
1199system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
1200system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1201system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)

--- 38 unchanged lines hidden (view full) ---

1240system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks)
1241system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1242system.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks)
1243system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1244system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks)
1245system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1246system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
1247system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)

1248system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

1227system.iocache.tags.replacements 41685 # number of replacements
1228system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use
1229system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1230system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1231system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1232system.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit.
1233system.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor
1234system.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy
1235system.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy
1236system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1237system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1238system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1239system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1240system.iocache.tags.data_accesses 375525 # Number of data accesses

1249system.iocache.tags.replacements 41685 # number of replacements
1250system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use
1251system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1252system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1253system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1254system.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit.
1255system.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor
1256system.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy
1257system.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy
1258system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1259system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1260system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1261system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1262system.iocache.tags.data_accesses 375525 # Number of data accesses

1263system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

1241system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1242system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1243system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1244system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1245system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
1246system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
1247system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
1248system.iocache.overall_misses::total 41725 # number of overall misses

--- 64 unchanged lines hidden (view full) ---

1313system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency
1314system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency
1315system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency
1316system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency
1317system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
1318system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
1319system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
1320system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency

1264system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1265system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1266system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1267system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1268system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
1269system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
1270system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
1271system.iocache.overall_misses::total 41725 # number of overall misses

--- 64 unchanged lines hidden (view full) ---

1336system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency
1337system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency
1338system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency
1339system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency
1340system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
1341system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
1342system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
1343system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency

1344system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

1321system.membus.trans_dist::ReadReq 6930 # Transaction distribution
1322system.membus.trans_dist::ReadResp 296606 # Transaction distribution
1323system.membus.trans_dist::WriteReq 9599 # Transaction distribution
1324system.membus.trans_dist::WriteResp 9599 # Transaction distribution
1325system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution
1326system.membus.trans_dist::CleanEvict 261864 # Transaction distribution
1327system.membus.trans_dist::UpgradeReq 278 # Transaction distribution
1328system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution

--- 33 unchanged lines hidden (view full) ---

1362system.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks)
1363system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1364system.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks)
1365system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1366system.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks)
1367system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1368system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks)
1369system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

1345system.membus.trans_dist::ReadReq 6930 # Transaction distribution
1346system.membus.trans_dist::ReadResp 296606 # Transaction distribution
1347system.membus.trans_dist::WriteReq 9599 # Transaction distribution
1348system.membus.trans_dist::WriteResp 9599 # Transaction distribution
1349system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution
1350system.membus.trans_dist::CleanEvict 261864 # Transaction distribution
1351system.membus.trans_dist::UpgradeReq 278 # Transaction distribution
1352system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution

--- 33 unchanged lines hidden (view full) ---

1386system.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks)
1387system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1388system.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks)
1389system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1390system.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks)
1391system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1392system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks)
1393system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

1394system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1395system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1396system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1397system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1398system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states

1370system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1371system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1372system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1373system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1374system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1375system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1376system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1377system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

1393system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1394system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1395system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1396system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1397system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1398system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1399system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1400system.tsunami.ethernet.droppedPackets 0 # number of packets dropped

1399system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1400system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1401system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1402system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1403system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1404system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1405system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1406system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

1422system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1423system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1424system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1425system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1426system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1427system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1428system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1429system.tsunami.ethernet.droppedPackets 0 # number of packets dropped

1430system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1431system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1432system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1433system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1434system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1435system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1436system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1437system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1438system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1439system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1440system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1441system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1442system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1443system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1444system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1445system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1446system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1447system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1448system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1449system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1450system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1451system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
1452system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states