| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.876794 # Number of seconds simulated 4sim_ticks 1876794488000 # Number of ticks simulated 5final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.876794 # Number of seconds simulated 4sim_ticks 1876794488000 # Number of ticks simulated 5final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 164316 # Simulator instruction rate (inst/s) 8host_op_rate 164316 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5820514836 # Simulator tick rate (ticks/s) | 7host_inst_rate 142986 # Simulator instruction rate (inst/s) 8host_op_rate 142986 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5064945596 # Simulator tick rate (ticks/s) |
| 10host_mem_usage 335448 # Number of bytes of host memory used | 10host_mem_usage 335448 # Number of bytes of host memory used |
| 11host_seconds 322.44 # Real time elapsed on the host | 11host_seconds 370.55 # Real time elapsed on the host |
| 12sim_insts 52982943 # Number of instructions simulated 13sim_ops 52982943 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory --- 709 unchanged lines hidden (view full) --- 729system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency 730system.cpu.dcache.overall_avg_miss_latency::total 46109.302994 # average overall miss latency 731system.cpu.dcache.blocked_cycles::no_mshrs 7149027 # number of cycles access was blocked 732system.cpu.dcache.blocked_cycles::no_targets 5119 # number of cycles access was blocked 733system.cpu.dcache.blocked::no_mshrs 133846 # number of cycles access was blocked 734system.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked 735system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked 736system.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked | 12sim_insts 52982943 # Number of instructions simulated 13sim_ops 52982943 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory --- 709 unchanged lines hidden (view full) --- 729system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency 730system.cpu.dcache.overall_avg_miss_latency::total 46109.302994 # average overall miss latency 731system.cpu.dcache.blocked_cycles::no_mshrs 7149027 # number of cycles access was blocked 732system.cpu.dcache.blocked_cycles::no_targets 5119 # number of cycles access was blocked 733system.cpu.dcache.blocked::no_mshrs 133846 # number of cycles access was blocked 734system.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked 735system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked 736system.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked |
| 737system.cpu.dcache.fast_writes 0 # number of fast writes performed 738system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 739system.cpu.dcache.writebacks::writebacks 843569 # number of writebacks 740system.cpu.dcache.writebacks::total 843569 # number of writebacks 741system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # number of ReadReq MSHR hits 742system.cpu.dcache.ReadReq_mshr_hits::total 717041 # number of ReadReq MSHR hits 743system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676919 # number of WriteReq MSHR hits 744system.cpu.dcache.WriteReq_mshr_hits::total 1676919 # number of WriteReq MSHR hits 745system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6351 # number of LoadLockedReq MSHR hits 746system.cpu.dcache.LoadLockedReq_mshr_hits::total 6351 # number of LoadLockedReq MSHR hits --- 28 unchanged lines hidden (view full) --- 775system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1779000 # number of StoreCondReq MSHR miss cycles 776system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1779000 # number of StoreCondReq MSHR miss cycles 777system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63069666964 # number of demand (read+write) MSHR miss cycles 778system.cpu.dcache.demand_mshr_miss_latency::total 63069666964 # number of demand (read+write) MSHR miss cycles 779system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63069666964 # number of overall MSHR miss cycles 780system.cpu.dcache.overall_mshr_miss_latency::total 63069666964 # number of overall MSHR miss cycles 781system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528639000 # number of ReadReq MSHR uncacheable cycles 782system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528639000 # number of ReadReq MSHR uncacheable cycles | 737system.cpu.dcache.writebacks::writebacks 843569 # number of writebacks 738system.cpu.dcache.writebacks::total 843569 # number of writebacks 739system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # number of ReadReq MSHR hits 740system.cpu.dcache.ReadReq_mshr_hits::total 717041 # number of ReadReq MSHR hits 741system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676919 # number of WriteReq MSHR hits 742system.cpu.dcache.WriteReq_mshr_hits::total 1676919 # number of WriteReq MSHR hits 743system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6351 # number of LoadLockedReq MSHR hits 744system.cpu.dcache.LoadLockedReq_mshr_hits::total 6351 # number of LoadLockedReq MSHR hits --- 28 unchanged lines hidden (view full) --- 773system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1779000 # number of StoreCondReq MSHR miss cycles 774system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1779000 # number of StoreCondReq MSHR miss cycles 775system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63069666964 # number of demand (read+write) MSHR miss cycles 776system.cpu.dcache.demand_mshr_miss_latency::total 63069666964 # number of demand (read+write) MSHR miss cycles 777system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63069666964 # number of overall MSHR miss cycles 778system.cpu.dcache.overall_mshr_miss_latency::total 63069666964 # number of overall MSHR miss cycles 779system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528639000 # number of ReadReq MSHR uncacheable cycles 780system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528639000 # number of ReadReq MSHR uncacheable cycles |
| 783system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154562000 # number of WriteReq MSHR uncacheable cycles 784system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154562000 # number of WriteReq MSHR uncacheable cycles 785system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683201000 # number of overall MSHR uncacheable cycles 786system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683201000 # number of overall MSHR uncacheable cycles | 781system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528639000 # number of overall MSHR uncacheable cycles 782system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528639000 # number of overall MSHR uncacheable cycles |
| 787system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111881 # mshr miss rate for ReadReq accesses 788system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111881 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047061 # mshr miss rate for WriteReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047061 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071461 # mshr miss rate for LoadLockedReq accesses 792system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071461 # mshr miss rate for LoadLockedReq accesses 793system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000445 # mshr miss rate for StoreCondReq accesses 794system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000445 # mshr miss rate for StoreCondReq accesses --- 10 unchanged lines hidden (view full) --- 805system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000 # average StoreCondReq mshr miss latency 806system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000 # average StoreCondReq mshr miss latency 807system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 808system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 809system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 810system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 811system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency 812system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency | 783system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111881 # mshr miss rate for ReadReq accesses 784system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111881 # mshr miss rate for ReadReq accesses 785system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047061 # mshr miss rate for WriteReq accesses 786system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047061 # mshr miss rate for WriteReq accesses 787system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071461 # mshr miss rate for LoadLockedReq accesses 788system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071461 # mshr miss rate for LoadLockedReq accesses 789system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000445 # mshr miss rate for StoreCondReq accesses 790system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000445 # mshr miss rate for StoreCondReq accesses --- 10 unchanged lines hidden (view full) --- 801system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000 # average StoreCondReq mshr miss latency 802system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000 # average StoreCondReq mshr miss latency 803system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 804system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 805system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency 806system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency 807system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency 808system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency |
| 813system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596 # average WriteReq mshr uncacheable latency 814system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596 # average WriteReq mshr uncacheable latency 815system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753 # average overall mshr uncacheable latency 816system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753 # average overall mshr uncacheable latency 817system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 809system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency 810system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency |
| 818system.cpu.icache.tags.replacements 1074186 # number of replacements 819system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use 820system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. 821system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks. 822system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks. 823system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit. 824system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor 825system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 868system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency 869system.cpu.icache.overall_avg_miss_latency::total 14866.496136 # average overall miss latency 870system.cpu.icache.blocked_cycles::no_mshrs 12933 # number of cycles access was blocked 871system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 872system.cpu.icache.blocked::no_mshrs 342 # number of cycles access was blocked 873system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 874system.cpu.icache.avg_blocked_cycles::no_mshrs 37.815789 # average number of cycles each access was blocked 875system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 811system.cpu.icache.tags.replacements 1074186 # number of replacements 812system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use 813system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. 814system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks. 815system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks. 816system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit. 817system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor 818system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 861system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency 862system.cpu.icache.overall_avg_miss_latency::total 14866.496136 # average overall miss latency 863system.cpu.icache.blocked_cycles::no_mshrs 12933 # number of cycles access was blocked 864system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 865system.cpu.icache.blocked::no_mshrs 342 # number of cycles access was blocked 866system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 867system.cpu.icache.avg_blocked_cycles::no_mshrs 37.815789 # average number of cycles each access was blocked 868system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 876system.cpu.icache.fast_writes 0 # number of fast writes performed 877system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 878system.cpu.icache.writebacks::writebacks 1074186 # number of writebacks 879system.cpu.icache.writebacks::total 1074186 # number of writebacks 880system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68615 # number of ReadReq MSHR hits 881system.cpu.icache.ReadReq_mshr_hits::total 68615 # number of ReadReq MSHR hits 882system.cpu.icache.demand_mshr_hits::cpu.inst 68615 # number of demand (read+write) MSHR hits 883system.cpu.icache.demand_mshr_hits::total 68615 # number of demand (read+write) MSHR hits 884system.cpu.icache.overall_mshr_hits::cpu.inst 68615 # number of overall MSHR hits 885system.cpu.icache.overall_mshr_hits::total 68615 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 902system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses 903system.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses 904system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency 905system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency 906system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 907system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency 908system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 909system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency | 869system.cpu.icache.writebacks::writebacks 1074186 # number of writebacks 870system.cpu.icache.writebacks::total 1074186 # number of writebacks 871system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68615 # number of ReadReq MSHR hits 872system.cpu.icache.ReadReq_mshr_hits::total 68615 # number of ReadReq MSHR hits 873system.cpu.icache.demand_mshr_hits::cpu.inst 68615 # number of demand (read+write) MSHR hits 874system.cpu.icache.demand_mshr_hits::total 68615 # number of demand (read+write) MSHR hits 875system.cpu.icache.overall_mshr_hits::cpu.inst 68615 # number of overall MSHR hits 876system.cpu.icache.overall_mshr_hits::total 68615 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 893system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses 894system.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses 895system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency 896system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency 897system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 898system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency 899system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency 900system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency |
| 910system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 911system.cpu.l2cache.tags.replacements 338591 # number of replacements 912system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use 913system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks. 914system.cpu.l2cache.tags.sampled_refs 403759 # Sample count of references to valid blocks. 915system.cpu.l2cache.tags.avg_refs 10.534943 # Average number of references to valid blocks. 916system.cpu.l2cache.tags.warmup_cycle 9186566000 # Cycle when the warmup percentage was hit. 917system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616 # Average occupied blocks per requestor 918system.cpu.l2cache.tags.occ_blocks::cpu.inst 5255.268427 # Average occupied blocks per requestor --- 116 unchanged lines hidden (view full) --- 1035system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128755.139234 # average overall miss latency 1036system.cpu.l2cache.overall_avg_miss_latency::total 128978.078929 # average overall miss latency 1037system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1038system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1039system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1040system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1041system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1042system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 901system.cpu.l2cache.tags.replacements 338591 # number of replacements 902system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use 903system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks. 904system.cpu.l2cache.tags.sampled_refs 403759 # Sample count of references to valid blocks. 905system.cpu.l2cache.tags.avg_refs 10.534943 # Average number of references to valid blocks. 906system.cpu.l2cache.tags.warmup_cycle 9186566000 # Cycle when the warmup percentage was hit. 907system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616 # Average occupied blocks per requestor 908system.cpu.l2cache.tags.occ_blocks::cpu.inst 5255.268427 # Average occupied blocks per requestor --- 116 unchanged lines hidden (view full) --- 1025system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128755.139234 # average overall miss latency 1026system.cpu.l2cache.overall_avg_miss_latency::total 128978.078929 # average overall miss latency 1027system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1028system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1029system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1030system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1031system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1032system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1043system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1044system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1045system.cpu.l2cache.writebacks::writebacks 76108 # number of writebacks 1046system.cpu.l2cache.writebacks::total 76108 # number of writebacks 1047system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 45 # number of UpgradeReq MSHR misses 1048system.cpu.l2cache.UpgradeReq_mshr_misses::total 45 # number of UpgradeReq MSHR misses 1049system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses 1050system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses 1051system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114791 # number of ReadExReq MSHR misses 1052system.cpu.l2cache.ReadExReq_mshr_misses::total 114791 # number of ReadExReq MSHR misses --- 26 unchanged lines hidden (view full) --- 1079system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1874795000 # number of demand (read+write) MSHR miss cycles 1080system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46238023002 # number of demand (read+write) MSHR miss cycles 1081system.cpu.l2cache.demand_mshr_miss_latency::total 48112818002 # number of demand (read+write) MSHR miss cycles 1082system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1874795000 # number of overall MSHR miss cycles 1083system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46238023002 # number of overall MSHR miss cycles 1084system.cpu.l2cache.overall_mshr_miss_latency::total 48112818002 # number of overall MSHR miss cycles 1085system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442000500 # number of ReadReq MSHR uncacheable cycles 1086system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442000500 # number of ReadReq MSHR uncacheable cycles | 1033system.cpu.l2cache.writebacks::writebacks 76108 # number of writebacks 1034system.cpu.l2cache.writebacks::total 76108 # number of writebacks 1035system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 45 # number of UpgradeReq MSHR misses 1036system.cpu.l2cache.UpgradeReq_mshr_misses::total 45 # number of UpgradeReq MSHR misses 1037system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses 1038system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses 1039system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114791 # number of ReadExReq MSHR misses 1040system.cpu.l2cache.ReadExReq_mshr_misses::total 114791 # number of ReadExReq MSHR misses --- 26 unchanged lines hidden (view full) --- 1067system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1874795000 # number of demand (read+write) MSHR miss cycles 1068system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46238023002 # number of demand (read+write) MSHR miss cycles 1069system.cpu.l2cache.demand_mshr_miss_latency::total 48112818002 # number of demand (read+write) MSHR miss cycles 1070system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1874795000 # number of overall MSHR miss cycles 1071system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46238023002 # number of overall MSHR miss cycles 1072system.cpu.l2cache.overall_mshr_miss_latency::total 48112818002 # number of overall MSHR miss cycles 1073system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442000500 # number of ReadReq MSHR uncacheable cycles 1074system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442000500 # number of ReadReq MSHR uncacheable cycles |
| 1087system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2044145000 # number of WriteReq MSHR uncacheable cycles 1088system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2044145000 # number of WriteReq MSHR uncacheable cycles 1089system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486145500 # number of overall MSHR uncacheable cycles 1090system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486145500 # number of overall MSHR uncacheable cycles | 1075system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1442000500 # number of overall MSHR uncacheable cycles 1076system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1442000500 # number of overall MSHR uncacheable cycles |
| 1091system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.562500 # mshr miss rate for UpgradeReq accesses 1092system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.562500 # mshr miss rate for UpgradeReq accesses 1093system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.083333 # mshr miss rate for SCUpgradeReq accesses 1094system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses 1095system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382857 # mshr miss rate for ReadExReq accesses 1096system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382857 # mshr miss rate for ReadExReq accesses 1097system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for ReadCleanReq accesses 1098system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013984 # mshr miss rate for ReadCleanReq accesses --- 18 unchanged lines hidden (view full) --- 1117system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency 1118system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency 1119system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency 1120system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency 1121system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency 1122system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency 1123system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231 # average ReadReq mshr uncacheable latency 1124system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231 # average ReadReq mshr uncacheable latency | 1077system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.562500 # mshr miss rate for UpgradeReq accesses 1078system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.562500 # mshr miss rate for UpgradeReq accesses 1079system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.083333 # mshr miss rate for SCUpgradeReq accesses 1080system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses 1081system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382857 # mshr miss rate for ReadExReq accesses 1082system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382857 # mshr miss rate for ReadExReq accesses 1083system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for ReadCleanReq accesses 1084system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013984 # mshr miss rate for ReadCleanReq accesses --- 18 unchanged lines hidden (view full) --- 1103system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency 1104system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency 1105system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency 1106system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency 1107system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency 1108system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency 1109system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231 # average ReadReq mshr uncacheable latency 1110system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231 # average ReadReq mshr uncacheable latency |
| 1125system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537 # average WriteReq mshr uncacheable latency 1126system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537 # average WriteReq mshr uncacheable latency 1127system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651 # average overall mshr uncacheable latency 1128system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651 # average overall mshr uncacheable latency 1129system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1111system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency 1112system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency |
| 1130system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter. 1131system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1132system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1133system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 1134system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1135system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1136system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 1137system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution --- 116 unchanged lines hidden (view full) --- 1254system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1255system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1256system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1257system.iocache.tags.data_accesses 375525 # Number of data accesses 1258system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1259system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1260system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1261system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses | 1113system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter. 1114system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1115system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1116system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 1117system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1118system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1119system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution --- 116 unchanged lines hidden (view full) --- 1237system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1238system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1239system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1240system.iocache.tags.data_accesses 375525 # Number of data accesses 1241system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1242system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1243system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1244system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses |
| 1262system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1263system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1264system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1265system.iocache.overall_misses::total 173 # number of overall misses | 1245system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1246system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1247system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1248system.iocache.overall_misses::total 41725 # number of overall misses |
| 1266system.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles 1267system.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles 1268system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles 1269system.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles | 1249system.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles 1250system.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles 1251system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles 1252system.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles |
| 1270system.iocache.demand_miss_latency::tsunami.ide 21828883 # number of demand (read+write) miss cycles 1271system.iocache.demand_miss_latency::total 21828883 # number of demand (read+write) miss cycles 1272system.iocache.overall_miss_latency::tsunami.ide 21828883 # number of overall miss cycles 1273system.iocache.overall_miss_latency::total 21828883 # number of overall miss cycles | 1253system.iocache.demand_miss_latency::tsunami.ide 5268272163 # number of demand (read+write) miss cycles 1254system.iocache.demand_miss_latency::total 5268272163 # number of demand (read+write) miss cycles 1255system.iocache.overall_miss_latency::tsunami.ide 5268272163 # number of overall miss cycles 1256system.iocache.overall_miss_latency::total 5268272163 # number of overall miss cycles |
| 1274system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1275system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1276system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1277system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) | 1257system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1258system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1259system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1260system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) |
| 1278system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1279system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1280system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1281system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses | 1261system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1262system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1263system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1264system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses |
| 1282system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1283system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1284system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1285system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1286system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1287system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1288system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1289system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1290system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451 # average ReadReq miss latency 1291system.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency 1292system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency 1293system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency | 1265system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1266system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1267system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1268system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1269system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1270system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1271system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1272system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1273system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451 # average ReadReq miss latency 1274system.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency 1275system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency 1276system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency |
| 1294system.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency 1295system.iocache.demand_avg_miss_latency::total 126178.514451 # average overall miss latency 1296system.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency 1297system.iocache.overall_avg_miss_latency::total 126178.514451 # average overall miss latency | 1277system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency 1278system.iocache.demand_avg_miss_latency::total 126261.765440 # average overall miss latency 1279system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency 1280system.iocache.overall_avg_miss_latency::total 126261.765440 # average overall miss latency |
| 1298system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked 1299system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1300system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked 1301system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1302system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 1303system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1281system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked 1282system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1283system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked 1284system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1285system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 1286system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1304system.iocache.fast_writes 0 # number of fast writes performed 1305system.iocache.cache_copies 0 # number of cache copies performed | |
| 1306system.iocache.writebacks::writebacks 41512 # number of writebacks 1307system.iocache.writebacks::total 41512 # number of writebacks 1308system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1309system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1310system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1311system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses | 1287system.iocache.writebacks::writebacks 41512 # number of writebacks 1288system.iocache.writebacks::total 41512 # number of writebacks 1289system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1290system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1291system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1292system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses |
| 1312system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1313system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1314system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1315system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses | 1293system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1294system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1295system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1296system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 1316system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles 1317system.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles 1318system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles 1319system.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles | 1297system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles 1298system.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles 1299system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles 1300system.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles |
| 1320system.iocache.demand_mshr_miss_latency::tsunami.ide 13178883 # number of demand (read+write) MSHR miss cycles 1321system.iocache.demand_mshr_miss_latency::total 13178883 # number of demand (read+write) MSHR miss cycles 1322system.iocache.overall_mshr_miss_latency::tsunami.ide 13178883 # number of overall MSHR miss cycles 1323system.iocache.overall_mshr_miss_latency::total 13178883 # number of overall MSHR miss cycles | 1301system.iocache.demand_mshr_miss_latency::tsunami.ide 3180227354 # number of demand (read+write) MSHR miss cycles 1302system.iocache.demand_mshr_miss_latency::total 3180227354 # number of demand (read+write) MSHR miss cycles 1303system.iocache.overall_mshr_miss_latency::tsunami.ide 3180227354 # number of overall MSHR miss cycles 1304system.iocache.overall_mshr_miss_latency::total 3180227354 # number of overall MSHR miss cycles |
| 1324system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1325system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1326system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1327system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1328system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1329system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1330system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1331system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1332system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency 1333system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency 1334system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency 1335system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency | 1305system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1306system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1307system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1308system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1309system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1310system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1311system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1312system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1313system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency 1314system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency 1315system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency 1316system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency |
| 1336system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency 1337system.iocache.demand_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency 1338system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency 1339system.iocache.overall_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency 1340system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1317system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency 1318system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency 1319system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency 1320system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency |
| 1341system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1342system.membus.trans_dist::ReadResp 296606 # Transaction distribution 1343system.membus.trans_dist::WriteReq 9599 # Transaction distribution 1344system.membus.trans_dist::WriteResp 9599 # Transaction distribution 1345system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution 1346system.membus.trans_dist::CleanEvict 261864 # Transaction distribution 1347system.membus.trans_dist::UpgradeReq 278 # Transaction distribution 1348system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution --- 159 unchanged lines hidden --- | 1321system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1322system.membus.trans_dist::ReadResp 296606 # Transaction distribution 1323system.membus.trans_dist::WriteReq 9599 # Transaction distribution 1324system.membus.trans_dist::WriteResp 9599 # Transaction distribution 1325system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution 1326system.membus.trans_dist::CleanEvict 261864 # Transaction distribution 1327system.membus.trans_dist::UpgradeReq 278 # Transaction distribution 1328system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution --- 159 unchanged lines hidden --- |