| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.860990 # Number of seconds simulated 4sim_ticks 1860990273000 # Number of ticks simulated 5final_tick 1860990273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.875745 # Number of seconds simulated 4sim_ticks 1875745192000 # Number of ticks simulated 5final_tick 1875745192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 102674 # Simulator instruction rate (inst/s) 8host_op_rate 102674 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3606509618 # Simulator tick rate (ticks/s) 10host_mem_usage 370916 # Number of bytes of host memory used 11host_seconds 516.01 # Real time elapsed on the host 12sim_insts 52980740 # Number of instructions simulated 13sim_ops 52980740 # Number of ops (including micro ops) simulated | 7host_inst_rate 131976 # Simulator instruction rate (inst/s) 8host_op_rate 131976 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4672432142 # Simulator tick rate (ticks/s) 10host_mem_usage 378172 # Number of bytes of host memory used 11host_seconds 401.45 # Real time elapsed on the host 12sim_insts 52981683 # Number of instructions simulated 13sim_ops 52981683 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 964096 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 962112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24881536 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 25845056 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 964096 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 964096 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7523456 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7523456 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 15064 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 25844608 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 962112 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 962112 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7523648 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7523648 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 15033 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388774 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::total 403829 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 117554 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 117554 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 518055 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13369226 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 13887797 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 518055 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 518055 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4042716 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4042716 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4042716 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 518055 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13369226 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17930514 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 403829 # Number of read requests accepted 44system.physmem.writeReqs 117554 # Number of write requests accepted 45system.physmem.readBursts 403829 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 117554 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25837696 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7522048 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25845056 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7523456 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue | 27system.physmem.num_reads::total 403822 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 117557 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 117557 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 512923 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13264881 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 13778315 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 512923 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 512923 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4011018 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4011018 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4011018 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 512923 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13264881 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17789333 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 403822 # Number of read requests accepted 44system.physmem.writeReqs 117557 # Number of write requests accepted 45system.physmem.readBursts 403822 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 117557 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25836864 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7522176 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25844608 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7523648 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue |
| 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write | 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write |
| 55system.physmem.perBankRdBursts::0 25640 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25420 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25567 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25490 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25392 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24736 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24946 # Per bank write bursts 62system.physmem.perBankRdBursts::7 25069 # Per bank write bursts 63system.physmem.perBankRdBursts::8 24934 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25024 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25571 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24874 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24488 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25240 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25741 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25582 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7942 # Per bank write bursts | 55system.physmem.perBankRdBursts::0 25633 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25421 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25565 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25492 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25387 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24737 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24937 # Per bank write bursts 62system.physmem.perBankRdBursts::7 25080 # Per bank write bursts 63system.physmem.perBankRdBursts::8 24933 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25019 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25561 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24878 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24487 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25242 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25745 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25584 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7946 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::1 7515 # Per bank write bursts | 72system.physmem.perBankWrBursts::1 7515 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::2 7958 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7515 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7335 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6671 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6772 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6705 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7147 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6708 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7414 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6974 # Per bank write bursts | 73system.physmem.perBankWrBursts::2 7960 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7517 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7330 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6676 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6762 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6719 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7146 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6702 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7407 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6970 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::12 7148 # Per bank write bursts | 83system.physmem.perBankWrBursts::12 7148 # Per bank write bursts |
| 84system.physmem.perBankWrBursts::13 7857 # Per bank write bursts 85system.physmem.perBankWrBursts::14 8057 # Per bank write bursts | 84system.physmem.perBankWrBursts::13 7861 # Per bank write bursts 85system.physmem.perBankWrBursts::14 8061 # Per bank write bursts |
| 86system.physmem.perBankWrBursts::15 7814 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 86system.physmem.perBankWrBursts::15 7814 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 88system.physmem.numWrRetry 22 # Number of times write queue was full causing retry 89system.physmem.totGap 1860985018500 # Total gap between requests | 88system.physmem.numWrRetry 19 # Number of times write queue was full causing retry 89system.physmem.totGap 1875739913500 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 403829 # Read request sizes (log2) | 96system.physmem.readPktSize::6 403822 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 117554 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 314954 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 36116 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 28406 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 117557 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 315399 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 36013 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 28212 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 23984 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 76 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see |
| 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 1546 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1892 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 3644 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4720 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 5263 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 6242 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 7047 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 9676 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8910 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 7716 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8590 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 6996 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7044 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 8436 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6109 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6198 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5726 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 321 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 182 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 150 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 187 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 175 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 105 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 61694 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 540.722923 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 331.893410 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 417.338201 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 13637 22.10% 22.10% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10472 16.97% 39.08% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4852 7.86% 46.94% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3164 5.13% 52.07% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2278 3.69% 55.76% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1550 2.51% 58.28% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1469 2.38% 60.66% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1300 2.11% 62.76% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 22972 37.24% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 61694 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5210 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 77.486564 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2926.418549 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5207 99.94% 99.94% # Reads before turning the bus around for writes | 151system.physmem.wrQLenPdf::15 1634 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1915 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 3287 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4150 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 5413 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 6026 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 6352 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8246 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 9376 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8640 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8795 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7819 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6510 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6491 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5735 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 222 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 133 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 259 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 149 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 139 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 115 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 93 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 110 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 62141 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 536.822002 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 331.292900 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 411.615573 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 13686 22.02% 22.02% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10474 16.86% 38.88% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4974 8.00% 46.88% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 2759 4.44% 51.32% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2428 3.91% 55.23% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1656 2.66% 57.90% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 3743 6.02% 63.92% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1149 1.85% 65.77% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 21272 34.23% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 62141 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5219 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 77.350259 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2906.647984 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5216 99.94% 99.94% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::total 5210 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5210 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 22.558925 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 18.942347 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 23.343325 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-19 4470 85.80% 85.80% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20-23 144 2.76% 88.56% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-27 197 3.78% 92.34% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::28-31 15 0.29% 92.63% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::32-35 22 0.42% 93.05% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-39 47 0.90% 93.95% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::40-43 16 0.31% 94.26% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::44-47 1 0.02% 94.28% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::48-51 3 0.06% 94.34% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::52-55 6 0.12% 94.45% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::56-59 5 0.10% 94.55% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::60-63 2 0.04% 94.59% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::64-67 4 0.08% 94.66% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::68-71 2 0.04% 94.70% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::72-75 3 0.06% 94.76% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::76-79 10 0.19% 94.95% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::84-87 6 0.12% 95.07% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::88-91 10 0.19% 95.26% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::92-95 18 0.35% 95.60% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::96-99 17 0.33% 95.93% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::100-103 156 2.99% 98.93% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-107 8 0.15% 99.08% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::108-111 2 0.04% 99.12% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::120-123 1 0.02% 99.14% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::128-131 7 0.13% 99.27% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::132-135 1 0.02% 99.29% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::148-151 1 0.02% 99.31% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::152-155 3 0.06% 99.37% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::156-159 1 0.02% 99.39% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::164-167 3 0.06% 99.44% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::172-175 3 0.06% 99.50% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::176-179 1 0.02% 99.52% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::180-183 3 0.06% 99.58% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::184-187 1 0.02% 99.60% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::196-199 2 0.04% 99.64% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::200-203 2 0.04% 99.67% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::216-219 1 0.02% 99.69% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::220-223 4 0.08% 99.77% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::224-227 1 0.02% 99.79% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::228-231 11 0.21% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::total 5210 # Writes before turning the bus around for reads 267system.physmem.totQLat 3803541750 # Total ticks spent queuing 268system.physmem.totMemAccLat 11373179250 # Total ticks spent from burst creation until serviced by the DRAM 269system.physmem.totBusLat 2018570000 # Total ticks spent in databus transfers 270system.physmem.avgQLat 9421.38 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 5219 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5219 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 22.520406 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 19.103659 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 21.296995 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-19 4441 85.09% 85.09% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20-23 172 3.30% 88.39% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-27 18 0.34% 88.73% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::28-31 180 3.45% 92.18% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::32-35 4 0.08% 92.26% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-39 21 0.40% 92.66% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::40-43 36 0.69% 93.35% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::44-47 2 0.04% 93.39% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::48-51 12 0.23% 93.62% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::52-55 25 0.48% 94.10% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::56-59 3 0.06% 94.16% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::60-63 4 0.08% 94.23% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::64-67 11 0.21% 94.44% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::68-71 4 0.08% 94.52% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::72-75 20 0.38% 94.90% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::76-79 29 0.56% 95.46% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::80-83 1 0.02% 95.48% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::84-87 29 0.56% 96.03% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::100-103 164 3.14% 99.18% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::108-111 1 0.02% 99.20% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::120-123 1 0.02% 99.21% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::124-127 1 0.02% 99.23% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::128-131 5 0.10% 99.33% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::132-135 3 0.06% 99.39% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::156-159 6 0.11% 99.52% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::160-163 4 0.08% 99.60% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::164-167 1 0.02% 99.62% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::168-171 4 0.08% 99.69% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::172-175 1 0.02% 99.71% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::180-183 11 0.21% 99.92% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::196-199 1 0.02% 99.96% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 5219 # Writes before turning the bus around for reads 262system.physmem.totQLat 4201414500 # Total ticks spent queuing 263system.physmem.totMemAccLat 11770808250 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 2018505000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 10407.24 # Average queueing delay per DRAM burst |
| 271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 272system.physmem.avgMemAccLat 28171.38 # Average memory access latency per DRAM burst 273system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s 274system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 275system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s 276system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s | 267system.physmem.avgMemAccLat 29157.24 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s |
| 277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 278system.physmem.busUtil 0.14 # Data bus utilization in percentage 279system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 280system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.14 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 281system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing 282system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing 283system.physmem.readRowHits 364213 # Number of row buffer hits during reads 284system.physmem.writeRowHits 95338 # Number of row buffer hits during writes 285system.physmem.readRowHitRate 90.22 # Row buffer hit rate for reads 286system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes 287system.physmem.avgGap 3569324.31 # Average gap between requests 288system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined 289system.physmem_0.actEnergy 231343560 # Energy for activate commands per rank (pJ) 290system.physmem_0.preEnergy 126229125 # Energy for precharge commands per rank (pJ) 291system.physmem_0.readEnergy 1577628000 # Energy for read commands per rank (pJ) 292system.physmem_0.writeEnergy 378516240 # Energy for write commands per rank (pJ) 293system.physmem_0.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) 294system.physmem_0.actBackEnergy 56189479095 # Energy for active background per rank (pJ) 295system.physmem_0.preBackEnergy 1067301426750 # Energy for precharge background per rank (pJ) 296system.physmem_0.totalEnergy 1247355039810 # Total energy per rank (pJ) 297system.physmem_0.averagePower 670.266370 # Core power per rank (mW) 298system.physmem_0.memoryStateTime::IDLE 1775383293000 # Time in different power states 299system.physmem_0.memoryStateTime::REF 62142340000 # Time in different power states | 276system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing 277system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing 278system.physmem.readRowHits 363834 # Number of row buffer hits during reads 279system.physmem.writeRowHits 95259 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 81.03 # Row buffer hit rate for writes 282system.physmem.avgGap 3597651.45 # Average gap between requests 283system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined 284system.physmem_0.actEnergy 233286480 # Energy for activate commands per rank (pJ) 285system.physmem_0.preEnergy 127289250 # Energy for precharge commands per rank (pJ) 286system.physmem_0.readEnergy 1577565600 # Energy for read commands per rank (pJ) 287system.physmem_0.writeEnergy 378594000 # Energy for write commands per rank (pJ) 288system.physmem_0.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) 289system.physmem_0.actBackEnergy 61659983700 # Energy for active background per rank (pJ) 290system.physmem_0.preBackEnergy 1071355704750 # Energy for precharge background per rank (pJ) 291system.physmem_0.totalEnergy 1257846562020 # Total energy per rank (pJ) 292system.physmem_0.averagePower 670.587193 # Core power per rank (mW) 293system.physmem_0.memoryStateTime::IDLE 1782093997750 # Time in different power states 294system.physmem_0.memoryStateTime::REF 62635040000 # Time in different power states |
| 300system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 295system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 301system.physmem_0.memoryStateTime::ACT 23458453250 # Time in different power states | 296system.physmem_0.memoryStateTime::ACT 31009992250 # Time in different power states |
| 302system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 297system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 303system.physmem_1.actEnergy 235063080 # Energy for activate commands per rank (pJ) 304system.physmem_1.preEnergy 128258625 # Energy for precharge commands per rank (pJ) 305system.physmem_1.readEnergy 1571294400 # Energy for read commands per rank (pJ) 306system.physmem_1.writeEnergy 383091120 # Energy for write commands per rank (pJ) 307system.physmem_1.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) 308system.physmem_1.actBackEnergy 55921872645 # Energy for active background per rank (pJ) 309system.physmem_1.preBackEnergy 1067536177500 # Energy for precharge background per rank (pJ) 310system.physmem_1.totalEnergy 1247326174410 # Total energy per rank (pJ) 311system.physmem_1.averagePower 670.250855 # Core power per rank (mW) 312system.physmem_1.memoryStateTime::IDLE 1775778508500 # Time in different power states 313system.physmem_1.memoryStateTime::REF 62142340000 # Time in different power states | 298system.physmem_1.actEnergy 236499480 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 129042375 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 1571255400 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 383026320 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 61488464715 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 1071506168250 # Energy for precharge background per rank (pJ) 305system.physmem_1.totalEnergy 1257828594780 # Total energy per rank (pJ) 306system.physmem_1.averagePower 670.577609 # Core power per rank (mW) 307system.physmem_1.memoryStateTime::IDLE 1782344410500 # Time in different power states 308system.physmem_1.memoryStateTime::REF 62635040000 # Time in different power states |
| 314system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 309system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 315system.physmem_1.memoryStateTime::ACT 23063881500 # Time in different power states | 310system.physmem_1.memoryStateTime::ACT 30760024500 # Time in different power states |
| 316system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 311system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 317system.cpu.branchPred.lookups 17952495 # Number of BP lookups 318system.cpu.branchPred.condPredicted 15650737 # Number of conditional branches predicted 319system.cpu.branchPred.condIncorrect 369298 # Number of conditional branches incorrect 320system.cpu.branchPred.BTBLookups 11540660 # Number of BTB lookups 321system.cpu.branchPred.BTBHits 5852648 # Number of BTB hits | 312system.cpu.branchPred.lookups 17977610 # Number of BP lookups 313system.cpu.branchPred.condPredicted 15676073 # Number of conditional branches predicted 314system.cpu.branchPred.condIncorrect 370677 # Number of conditional branches incorrect 315system.cpu.branchPred.BTBLookups 11479744 # Number of BTB lookups 316system.cpu.branchPred.BTBHits 5859077 # Number of BTB hits |
| 322system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 317system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 323system.cpu.branchPred.BTBHitPct 50.713287 # BTB Hit Percentage 324system.cpu.branchPred.usedRAS 911814 # Number of times the RAS was used to get a target. 325system.cpu.branchPred.RASInCorrect 21176 # Number of incorrect RAS predictions. | 318system.cpu.branchPred.BTBHitPct 51.038394 # BTB Hit Percentage 319system.cpu.branchPred.usedRAS 912903 # Number of times the RAS was used to get a target. 320system.cpu.branchPred.RASInCorrect 21206 # Number of incorrect RAS predictions. |
| 326system.cpu_clk_domain.clock 500 # Clock period in ticks 327system.cpu.dtb.fetch_hits 0 # ITB hits 328system.cpu.dtb.fetch_misses 0 # ITB misses 329system.cpu.dtb.fetch_acv 0 # ITB acv 330system.cpu.dtb.fetch_accesses 0 # ITB accesses | 321system.cpu_clk_domain.clock 500 # Clock period in ticks 322system.cpu.dtb.fetch_hits 0 # ITB hits 323system.cpu.dtb.fetch_misses 0 # ITB misses 324system.cpu.dtb.fetch_acv 0 # ITB acv 325system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 331system.cpu.dtb.read_hits 10266725 # DTB read hits 332system.cpu.dtb.read_misses 41420 # DTB read misses 333system.cpu.dtb.read_acv 529 # DTB read access violations 334system.cpu.dtb.read_accesses 965767 # DTB read accesses 335system.cpu.dtb.write_hits 6642195 # DTB write hits 336system.cpu.dtb.write_misses 9809 # DTB write misses 337system.cpu.dtb.write_acv 405 # DTB write access violations 338system.cpu.dtb.write_accesses 342270 # DTB write accesses 339system.cpu.dtb.data_hits 16908920 # DTB hits 340system.cpu.dtb.data_misses 51229 # DTB misses 341system.cpu.dtb.data_acv 934 # DTB access violations 342system.cpu.dtb.data_accesses 1308037 # DTB accesses 343system.cpu.itb.fetch_hits 1768997 # ITB hits 344system.cpu.itb.fetch_misses 27603 # ITB misses | 326system.cpu.dtb.read_hits 10250294 # DTB read hits 327system.cpu.dtb.read_misses 41452 # DTB read misses 328system.cpu.dtb.read_acv 531 # DTB read access violations 329system.cpu.dtb.read_accesses 965916 # DTB read accesses 330system.cpu.dtb.write_hits 6642949 # DTB write hits 331system.cpu.dtb.write_misses 9723 # DTB write misses 332system.cpu.dtb.write_acv 398 # DTB write access violations 333system.cpu.dtb.write_accesses 342082 # DTB write accesses 334system.cpu.dtb.data_hits 16893243 # DTB hits 335system.cpu.dtb.data_misses 51175 # DTB misses 336system.cpu.dtb.data_acv 929 # DTB access violations 337system.cpu.dtb.data_accesses 1307998 # DTB accesses 338system.cpu.itb.fetch_hits 1771116 # ITB hits 339system.cpu.itb.fetch_misses 27251 # ITB misses |
| 345system.cpu.itb.fetch_acv 655 # ITB acv | 340system.cpu.itb.fetch_acv 655 # ITB acv |
| 346system.cpu.itb.fetch_accesses 1796600 # ITB accesses | 341system.cpu.itb.fetch_accesses 1798367 # ITB accesses |
| 347system.cpu.itb.read_hits 0 # DTB read hits 348system.cpu.itb.read_misses 0 # DTB read misses 349system.cpu.itb.read_acv 0 # DTB read access violations 350system.cpu.itb.read_accesses 0 # DTB read accesses 351system.cpu.itb.write_hits 0 # DTB write hits 352system.cpu.itb.write_misses 0 # DTB write misses 353system.cpu.itb.write_acv 0 # DTB write access violations 354system.cpu.itb.write_accesses 0 # DTB write accesses 355system.cpu.itb.data_hits 0 # DTB hits 356system.cpu.itb.data_misses 0 # DTB misses 357system.cpu.itb.data_acv 0 # DTB access violations 358system.cpu.itb.data_accesses 0 # DTB accesses | 342system.cpu.itb.read_hits 0 # DTB read hits 343system.cpu.itb.read_misses 0 # DTB read misses 344system.cpu.itb.read_acv 0 # DTB read access violations 345system.cpu.itb.read_accesses 0 # DTB read accesses 346system.cpu.itb.write_hits 0 # DTB write hits 347system.cpu.itb.write_misses 0 # DTB write misses 348system.cpu.itb.write_acv 0 # DTB write access violations 349system.cpu.itb.write_accesses 0 # DTB write accesses 350system.cpu.itb.data_hits 0 # DTB hits 351system.cpu.itb.data_misses 0 # DTB misses 352system.cpu.itb.data_acv 0 # DTB access violations 353system.cpu.itb.data_accesses 0 # DTB accesses |
| 359system.cpu.numCycles 122250725 # number of cpu cycles simulated | 354system.cpu.numCycles 153807945 # number of cpu cycles simulated |
| 360system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 361system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 355system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 356system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 362system.cpu.fetch.icacheStallCycles 29590872 # Number of cycles fetch is stalled on an Icache miss 363system.cpu.fetch.Insts 78035312 # Number of instructions fetch has processed 364system.cpu.fetch.Branches 17952495 # Number of branches that fetch encountered 365system.cpu.fetch.predictedBranches 6764462 # Number of branches that fetch has predicted taken 366system.cpu.fetch.Cycles 84736015 # Number of cycles fetch has run and was not squashing or blocked 367system.cpu.fetch.SquashCycles 1230846 # Number of cycles fetch has spent squashing 368system.cpu.fetch.TlbCycles 3604 # Number of cycles fetch has spent waiting for tlb 369system.cpu.fetch.MiscStallCycles 27977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 370system.cpu.fetch.PendingTrapStallCycles 1246103 # Number of stall cycles due to pending traps 371system.cpu.fetch.PendingQuiesceStallCycles 463506 # Number of stall cycles due to pending quiesce instructions 372system.cpu.fetch.IcacheWaitRetryStallCycles 270 # Number of stall cycles due to full MSHR 373system.cpu.fetch.CacheLines 8988072 # Number of cache lines fetched 374system.cpu.fetch.IcacheSquashes 271207 # Number of outstanding Icache misses that were squashed 375system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed 376system.cpu.fetch.rateDist::samples 116683770 # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::mean 0.668776 # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::stdev 1.983888 # Number of instructions fetched each cycle (Total) | 357system.cpu.fetch.icacheStallCycles 29589963 # Number of cycles fetch is stalled on an Icache miss 358system.cpu.fetch.Insts 78082078 # Number of instructions fetch has processed 359system.cpu.fetch.Branches 17977610 # Number of branches that fetch encountered 360system.cpu.fetch.predictedBranches 6771980 # Number of branches that fetch has predicted taken 361system.cpu.fetch.Cycles 115315004 # Number of cycles fetch has run and was not squashing or blocked 362system.cpu.fetch.SquashCycles 1233982 # Number of cycles fetch has spent squashing 363system.cpu.fetch.TlbCycles 2306 # Number of cycles fetch has spent waiting for tlb 364system.cpu.fetch.MiscStallCycles 29550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 365system.cpu.fetch.PendingTrapStallCycles 1247451 # Number of stall cycles due to pending traps 366system.cpu.fetch.PendingQuiesceStallCycles 470617 # Number of stall cycles due to pending quiesce instructions 367system.cpu.fetch.IcacheWaitRetryStallCycles 460 # Number of stall cycles due to full MSHR 368system.cpu.fetch.CacheLines 8997640 # Number of cache lines fetched 369system.cpu.fetch.IcacheSquashes 271780 # Number of outstanding Icache misses that were squashed 370system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed 371system.cpu.fetch.rateDist::samples 147272342 # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::mean 0.530188 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::stdev 1.786973 # Number of instructions fetched each cycle (Total) |
| 379system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 374system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 380system.cpu.fetch.rateDist::0 102162821 87.56% 87.56% # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.rateDist::1 926771 0.79% 88.35% # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::2 1955000 1.68% 90.03% # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::3 905545 0.78% 90.80% # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::4 2771139 2.37% 93.18% # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::5 614884 0.53% 93.70% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::6 724459 0.62% 94.32% # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::7 1009032 0.86% 95.19% # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.rateDist::8 5614119 4.81% 100.00% # Number of instructions fetched each cycle (Total) | 375system.cpu.fetch.rateDist::0 132738967 90.13% 90.13% # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::1 930397 0.63% 90.76% # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::2 1956016 1.33% 92.09% # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::3 907001 0.62% 92.71% # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::4 2772714 1.88% 94.59% # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.rateDist::5 615474 0.42% 95.01% # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.rateDist::6 727209 0.49% 95.50% # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::7 1009346 0.69% 96.19% # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::8 5615218 3.81% 100.00% # Number of instructions fetched each cycle (Total) |
| 389system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 384system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 392system.cpu.fetch.rateDist::total 116683770 # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.branchRate 0.146850 # Number of branch fetches per cycle 394system.cpu.fetch.rate 0.638322 # Number of inst fetches per cycle 395system.cpu.decode.IdleCycles 24065548 # Number of cycles decode is idle 396system.cpu.decode.BlockedCycles 80700938 # Number of cycles decode is blocked 397system.cpu.decode.RunCycles 9436968 # Number of cycles decode is running 398system.cpu.decode.UnblockCycles 1906955 # Number of cycles decode is unblocking 399system.cpu.decode.SquashCycles 573360 # Number of cycles decode is squashing 400system.cpu.decode.BranchResolved 582340 # Number of times decode resolved a branch 401system.cpu.decode.BranchMispred 42404 # Number of times decode detected a branch misprediction 402system.cpu.decode.DecodedInsts 68029803 # Number of instructions handled by decode 403system.cpu.decode.SquashedInsts 132508 # Number of squashed instructions handled by decode 404system.cpu.rename.SquashCycles 573360 # Number of cycles rename is squashing 405system.cpu.rename.IdleCycles 24987085 # Number of cycles rename is idle 406system.cpu.rename.BlockCycles 50897393 # Number of cycles rename is blocking 407system.cpu.rename.serializeStallCycles 20868454 # count of cycles rename stalled for serializing inst 408system.cpu.rename.RunCycles 10337136 # Number of cycles rename is running 409system.cpu.rename.UnblockCycles 9020340 # Number of cycles rename is unblocking 410system.cpu.rename.RenamedInsts 65614260 # Number of instructions processed by rename 411system.cpu.rename.ROBFullEvents 203152 # Number of times rename has blocked due to ROB full 412system.cpu.rename.IQFullEvents 2087104 # Number of times rename has blocked due to IQ full 413system.cpu.rename.LQFullEvents 150571 # Number of times rename has blocked due to LQ full 414system.cpu.rename.SQFullEvents 4833262 # Number of times rename has blocked due to SQ full 415system.cpu.rename.RenamedOperands 43733220 # Number of destination operands rename has renamed 416system.cpu.rename.RenameLookups 79561709 # Number of register rename lookups that rename has made 417system.cpu.rename.int_rename_lookups 79380946 # Number of integer rename lookups 418system.cpu.rename.fp_rename_lookups 168313 # Number of floating rename lookups 419system.cpu.rename.CommittedMaps 38180223 # Number of HB maps that are committed 420system.cpu.rename.UndoneMaps 5552989 # Number of HB maps that are undone due to squashing 421system.cpu.rename.serializingInsts 1689330 # count of serializing insts renamed 422system.cpu.rename.tempSerializingInsts 239361 # count of temporary serializing insts renamed 423system.cpu.rename.skidInsts 13544094 # count of insts added to the skid buffer 424system.cpu.memDep0.insertedLoads 10376074 # Number of loads inserted to the mem dependence unit. 425system.cpu.memDep0.insertedStores 6949198 # Number of stores inserted to the mem dependence unit. 426system.cpu.memDep0.conflictingLoads 1492318 # Number of conflicting loads. 427system.cpu.memDep0.conflictingStores 1087072 # Number of conflicting stores. 428system.cpu.iq.iqInstsAdded 58452380 # Number of instructions added to the IQ (excludes non-spec) 429system.cpu.iq.iqNonSpecInstsAdded 2137932 # Number of non-speculative instructions added to the IQ 430system.cpu.iq.iqInstsIssued 57496742 # Number of instructions issued | 387system.cpu.fetch.rateDist::total 147272342 # Number of instructions fetched each cycle (Total) 388system.cpu.fetch.branchRate 0.116883 # Number of branch fetches per cycle 389system.cpu.fetch.rate 0.507660 # Number of inst fetches per cycle 390system.cpu.decode.IdleCycles 24002291 # Number of cycles decode is idle 391system.cpu.decode.BlockedCycles 111345789 # Number of cycles decode is blocked 392system.cpu.decode.RunCycles 9440793 # Number of cycles decode is running 393system.cpu.decode.UnblockCycles 1908530 # Number of cycles decode is unblocking 394system.cpu.decode.SquashCycles 574938 # Number of cycles decode is squashing 395system.cpu.decode.BranchResolved 581140 # Number of times decode resolved a branch 396system.cpu.decode.BranchMispred 42414 # Number of times decode detected a branch misprediction 397system.cpu.decode.DecodedInsts 68062016 # Number of instructions handled by decode 398system.cpu.decode.SquashedInsts 132549 # Number of squashed instructions handled by decode 399system.cpu.rename.SquashCycles 574938 # Number of cycles rename is squashing 400system.cpu.rename.IdleCycles 24926396 # Number of cycles rename is idle 401system.cpu.rename.BlockCycles 78168566 # Number of cycles rename is blocking 402system.cpu.rename.serializeStallCycles 21593766 # count of cycles rename stalled for serializing inst 403system.cpu.rename.RunCycles 10339140 # Number of cycles rename is running 404system.cpu.rename.UnblockCycles 11669534 # Number of cycles rename is unblocking 405system.cpu.rename.RenamedInsts 65637228 # Number of instructions processed by rename 406system.cpu.rename.ROBFullEvents 204564 # Number of times rename has blocked due to ROB full 407system.cpu.rename.IQFullEvents 2092706 # Number of times rename has blocked due to IQ full 408system.cpu.rename.LQFullEvents 229144 # Number of times rename has blocked due to LQ full 409system.cpu.rename.SQFullEvents 7400964 # Number of times rename has blocked due to SQ full 410system.cpu.rename.RenamedOperands 43743792 # Number of destination operands rename has renamed 411system.cpu.rename.RenameLookups 79597549 # Number of register rename lookups that rename has made 412system.cpu.rename.int_rename_lookups 79416724 # Number of integer rename lookups 413system.cpu.rename.fp_rename_lookups 168373 # Number of floating rename lookups 414system.cpu.rename.CommittedMaps 38181235 # Number of HB maps that are committed 415system.cpu.rename.UndoneMaps 5562549 # Number of HB maps that are undone due to squashing 416system.cpu.rename.serializingInsts 1689699 # count of serializing insts renamed 417system.cpu.rename.tempSerializingInsts 239435 # count of temporary serializing insts renamed 418system.cpu.rename.skidInsts 13568621 # count of insts added to the skid buffer 419system.cpu.memDep0.insertedLoads 10378795 # Number of loads inserted to the mem dependence unit. 420system.cpu.memDep0.insertedStores 6951631 # Number of stores inserted to the mem dependence unit. 421system.cpu.memDep0.conflictingLoads 1513940 # Number of conflicting loads. 422system.cpu.memDep0.conflictingStores 1098335 # Number of conflicting stores. 423system.cpu.iq.iqInstsAdded 58473138 # Number of instructions added to the IQ (excludes non-spec) 424system.cpu.iq.iqNonSpecInstsAdded 2139162 # Number of non-speculative instructions added to the IQ 425system.cpu.iq.iqInstsIssued 57493462 # Number of instructions issued |
| 431system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued | 426system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued |
| 432system.cpu.iq.iqSquashedInstsExamined 7609567 # Number of squashed instructions iterated over during squash; mainly for profiling 433system.cpu.iq.iqSquashedOperandsExamined 3401604 # Number of squashed operands that are examined and possibly removed from graph 434system.cpu.iq.iqSquashedNonSpecRemoved 1476871 # Number of squashed non-spec instructions that were removed 435system.cpu.iq.issued_per_cycle::samples 116683770 # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::mean 0.492757 # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::stdev 1.231576 # Number of insts issued each cycle | 427system.cpu.iq.iqSquashedInstsExamined 7630612 # Number of squashed instructions iterated over during squash; mainly for profiling 428system.cpu.iq.iqSquashedOperandsExamined 3411321 # Number of squashed operands that are examined and possibly removed from graph 429system.cpu.iq.iqSquashedNonSpecRemoved 1477941 # Number of squashed non-spec instructions that were removed 430system.cpu.iq.issued_per_cycle::samples 147272342 # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::mean 0.390389 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::stdev 1.114131 # Number of insts issued each cycle |
| 438system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 433system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 439system.cpu.iq.issued_per_cycle::0 93080109 79.77% 79.77% # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::1 10182698 8.73% 88.50% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::2 4288903 3.68% 92.17% # Number of insts issued each cycle 442system.cpu.iq.issued_per_cycle::3 3018996 2.59% 94.76% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::4 3082938 2.64% 97.40% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::5 1488362 1.28% 98.68% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::6 1011835 0.87% 99.55% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::7 404754 0.35% 99.89% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::8 125175 0.11% 100.00% # Number of insts issued each cycle | 434system.cpu.iq.issued_per_cycle::0 123663895 83.97% 83.97% # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::1 10186331 6.92% 90.89% # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::2 4292878 2.91% 93.80% # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::3 3019293 2.05% 95.85% # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::4 3081041 2.09% 97.94% # Number of insts issued each cycle 439system.cpu.iq.issued_per_cycle::5 1488323 1.01% 98.95% # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::6 1011420 0.69% 99.64% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::7 404091 0.27% 99.92% # Number of insts issued each cycle 442system.cpu.iq.issued_per_cycle::8 125070 0.08% 100.00% # Number of insts issued each cycle |
| 448system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 443system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 451system.cpu.iq.issued_per_cycle::total 116683770 # Number of insts issued each cycle | 446system.cpu.iq.issued_per_cycle::total 147272342 # Number of insts issued each cycle |
| 452system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 447system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 453system.cpu.iq.fu_full::IntAlu 209669 18.63% 18.63% # attempts to use FU when none available 454system.cpu.iq.fu_full::IntMult 0 0.00% 18.63% # attempts to use FU when none available 455system.cpu.iq.fu_full::IntDiv 0 0.00% 18.63% # attempts to use FU when none available 456system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.63% # attempts to use FU when none available 457system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.63% # attempts to use FU when none available 458system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.63% # attempts to use FU when none available 459system.cpu.iq.fu_full::FloatMult 0 0.00% 18.63% # attempts to use FU when none available 460system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.63% # attempts to use FU when none available 461system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.63% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.63% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.63% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.63% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.63% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.63% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.63% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdMult 0 0.00% 18.63% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.63% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdShift 0 0.00% 18.63% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.63% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.63% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.63% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.63% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.63% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.63% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.63% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.63% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.63% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.63% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.63% # attempts to use FU when none available 482system.cpu.iq.fu_full::MemRead 542046 48.17% 66.80% # attempts to use FU when none available 483system.cpu.iq.fu_full::MemWrite 373622 33.20% 100.00% # attempts to use FU when none available | 448system.cpu.iq.fu_full::IntAlu 210189 18.68% 18.68% # attempts to use FU when none available 449system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available 450system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available 451system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available 452system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available 453system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available 454system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available 455system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available 456system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available 477system.cpu.iq.fu_full::MemRead 539111 47.92% 66.61% # attempts to use FU when none available 478system.cpu.iq.fu_full::MemWrite 375615 33.39% 100.00% # attempts to use FU when none available |
| 484system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 485system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 486system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued | 479system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 480system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 481system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued |
| 487system.cpu.iq.FU_type_0::IntAlu 39037181 67.89% 67.91% # Type of FU issued 488system.cpu.iq.FU_type_0::IntMult 61834 0.11% 68.01% # Type of FU issued 489system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued 490system.cpu.iq.FU_type_0::FloatAdd 38554 0.07% 68.08% # Type of FU issued 491system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued 492system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued 493system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued 494system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued 495system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued 516system.cpu.iq.FU_type_0::MemRead 10676723 18.57% 86.66% # Type of FU issued 517system.cpu.iq.FU_type_0::MemWrite 6722717 11.69% 98.35% # Type of FU issued 518system.cpu.iq.FU_type_0::IprAccess 948811 1.65% 100.00% # Type of FU issued | 482system.cpu.iq.FU_type_0::IntAlu 39049173 67.92% 67.93% # Type of FU issued 483system.cpu.iq.FU_type_0::IntMult 61879 0.11% 68.04% # Type of FU issued 484system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued 485system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued 486system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued 487system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued 488system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued 489system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.11% # Type of FU issued 490system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued 511system.cpu.iq.FU_type_0::MemRead 10660314 18.54% 86.65% # Type of FU issued 512system.cpu.iq.FU_type_0::MemWrite 6723536 11.69% 98.35% # Type of FU issued 513system.cpu.iq.FU_type_0::IprAccess 949085 1.65% 100.00% # Type of FU issued |
| 519system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 514system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 520system.cpu.iq.FU_type_0::total 57496742 # Type of FU issued 521system.cpu.iq.rate 0.470318 # Inst issue rate 522system.cpu.iq.fu_busy_cnt 1125337 # FU busy when requested 523system.cpu.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst) 524system.cpu.iq.int_inst_queue_reads 232146820 # Number of integer instruction queue reads 525system.cpu.iq.int_inst_queue_writes 67882277 # Number of integer instruction queue writes 526system.cpu.iq.int_inst_queue_wakeup_accesses 55834928 # Number of integer instruction queue wakeup accesses 527system.cpu.iq.fp_inst_queue_reads 712827 # Number of floating instruction queue reads 528system.cpu.iq.fp_inst_queue_writes 336508 # Number of floating instruction queue writes 529system.cpu.iq.fp_inst_queue_wakeup_accesses 328971 # Number of floating instruction queue wakeup accesses 530system.cpu.iq.int_alu_accesses 58232105 # Number of integer alu accesses 531system.cpu.iq.fp_alu_accesses 382688 # Number of floating point alu accesses 532system.cpu.iew.lsq.thread0.forwLoads 634703 # Number of loads that had data forwarded from stores | 515system.cpu.iq.FU_type_0::total 57493462 # Type of FU issued 516system.cpu.iq.rate 0.373800 # Inst issue rate 517system.cpu.iq.fu_busy_cnt 1124915 # FU busy when requested 518system.cpu.iq.fu_busy_rate 0.019566 # FU busy rate (busy events/executed inst) 519system.cpu.iq.int_inst_queue_reads 262728196 # Number of integer instruction queue reads 520system.cpu.iq.int_inst_queue_writes 67925320 # Number of integer instruction queue writes 521system.cpu.iq.int_inst_queue_wakeup_accesses 55850502 # Number of integer instruction queue wakeup accesses 522system.cpu.iq.fp_inst_queue_reads 713041 # Number of floating instruction queue reads 523system.cpu.iq.fp_inst_queue_writes 336604 # Number of floating instruction queue writes 524system.cpu.iq.fp_inst_queue_wakeup_accesses 329051 # Number of floating instruction queue wakeup accesses 525system.cpu.iq.int_alu_accesses 58228243 # Number of integer alu accesses 526system.cpu.iq.fp_alu_accesses 382848 # Number of floating point alu accesses 527system.cpu.iew.lsq.thread0.forwLoads 635438 # Number of loads that had data forwarded from stores |
| 533system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 528system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 534system.cpu.iew.lsq.thread0.squashedLoads 1283936 # Number of loads squashed 535system.cpu.iew.lsq.thread0.ignoredResponses 3373 # Number of memory responses ignored because the instruction is squashed 536system.cpu.iew.lsq.thread0.memOrderViolation 19308 # Number of memory ordering violations 537system.cpu.iew.lsq.thread0.squashedStores 571381 # Number of stores squashed | 529system.cpu.iew.lsq.thread0.squashedLoads 1285740 # Number of loads squashed 530system.cpu.iew.lsq.thread0.ignoredResponses 3115 # Number of memory responses ignored because the instruction is squashed 531system.cpu.iew.lsq.thread0.memOrderViolation 19427 # Number of memory ordering violations 532system.cpu.iew.lsq.thread0.squashedStores 573353 # Number of stores squashed |
| 538system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 539system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 533system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 534system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 540system.cpu.iew.lsq.thread0.rescheduledLoads 18194 # Number of loads that were rescheduled 541system.cpu.iew.lsq.thread0.cacheBlocked 477327 # Number of times an access to memory failed due to the cache being blocked | 535system.cpu.iew.lsq.thread0.rescheduledLoads 18203 # Number of loads that were rescheduled 536system.cpu.iew.lsq.thread0.cacheBlocked 457581 # Number of times an access to memory failed due to the cache being blocked |
| 542system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 537system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 543system.cpu.iew.iewSquashCycles 573360 # Number of cycles IEW is squashing 544system.cpu.iew.iewBlockCycles 47668673 # Number of cycles IEW is blocking 545system.cpu.iew.iewUnblockCycles 853294 # Number of cycles IEW is unblocking 546system.cpu.iew.iewDispatchedInsts 64278853 # Number of instructions dispatched to IQ 547system.cpu.iew.iewDispSquashedInsts 140556 # Number of squashed instructions skipped by dispatch 548system.cpu.iew.iewDispLoadInsts 10376074 # Number of dispatched load instructions 549system.cpu.iew.iewDispStoreInsts 6949198 # Number of dispatched store instructions 550system.cpu.iew.iewDispNonSpecInsts 1890343 # Number of dispatched non-speculative instructions 551system.cpu.iew.iewIQFullEvents 43583 # Number of times the IQ has become full, causing a stall 552system.cpu.iew.iewLSQFullEvents 606693 # Number of times the LSQ has become full, causing a stall 553system.cpu.iew.memOrderViolationEvents 19308 # Number of memory order violations 554system.cpu.iew.predictedTakenIncorrect 178271 # Number of branches that were predicted taken incorrectly 555system.cpu.iew.predictedNotTakenIncorrect 409117 # Number of branches that were predicted not taken incorrectly 556system.cpu.iew.branchMispredicts 587388 # Number of branch mispredicts detected at execute 557system.cpu.iew.iewExecutedInsts 56911436 # Number of executed instructions 558system.cpu.iew.iewExecLoadInsts 10335818 # Number of load instructions executed 559system.cpu.iew.iewExecSquashedInsts 585305 # Number of squashed instructions skipped in execute | 538system.cpu.iew.iewSquashCycles 574938 # Number of cycles IEW is squashing 539system.cpu.iew.iewBlockCycles 74485816 # Number of cycles IEW is blocking 540system.cpu.iew.iewUnblockCycles 1122121 # Number of cycles IEW is unblocking 541system.cpu.iew.iewDispatchedInsts 64302959 # Number of instructions dispatched to IQ 542system.cpu.iew.iewDispSquashedInsts 140159 # Number of squashed instructions skipped by dispatch 543system.cpu.iew.iewDispLoadInsts 10378795 # Number of dispatched load instructions 544system.cpu.iew.iewDispStoreInsts 6951631 # Number of dispatched store instructions 545system.cpu.iew.iewDispNonSpecInsts 1891041 # Number of dispatched non-speculative instructions 546system.cpu.iew.iewIQFullEvents 44126 # Number of times the IQ has become full, causing a stall 547system.cpu.iew.iewLSQFullEvents 874685 # Number of times the LSQ has become full, causing a stall 548system.cpu.iew.memOrderViolationEvents 19427 # Number of memory order violations 549system.cpu.iew.predictedTakenIncorrect 179710 # Number of branches that were predicted taken incorrectly 550system.cpu.iew.predictedNotTakenIncorrect 409314 # Number of branches that were predicted not taken incorrectly 551system.cpu.iew.branchMispredicts 589024 # Number of branch mispredicts detected at execute 552system.cpu.iew.iewExecutedInsts 56907888 # Number of executed instructions 553system.cpu.iew.iewExecLoadInsts 10319427 # Number of load instructions executed 554system.cpu.iew.iewExecSquashedInsts 585573 # Number of squashed instructions skipped in execute |
| 560system.cpu.iew.exec_swp 0 # number of swp insts executed | 555system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 561system.cpu.iew.exec_nop 3688541 # number of nop insts executed 562system.cpu.iew.exec_refs 17002933 # number of memory reference insts executed 563system.cpu.iew.exec_branches 8971597 # Number of branches executed 564system.cpu.iew.exec_stores 6667115 # Number of stores executed 565system.cpu.iew.exec_rate 0.465530 # Inst execution rate 566system.cpu.iew.wb_sent 56299831 # cumulative count of insts sent to commit 567system.cpu.iew.wb_count 56163899 # cumulative count of insts written-back 568system.cpu.iew.wb_producers 28741573 # num instructions producing a value 569system.cpu.iew.wb_consumers 39917507 # num instructions consuming a value | 556system.cpu.iew.exec_nop 3690659 # number of nop insts executed 557system.cpu.iew.exec_refs 16987198 # number of memory reference insts executed 558system.cpu.iew.exec_branches 8973802 # Number of branches executed 559system.cpu.iew.exec_stores 6667771 # Number of stores executed 560system.cpu.iew.exec_rate 0.369993 # Inst execution rate 561system.cpu.iew.wb_sent 56315493 # cumulative count of insts sent to commit 562system.cpu.iew.wb_count 56179553 # cumulative count of insts written-back 563system.cpu.iew.wb_producers 28757989 # num instructions producing a value 564system.cpu.iew.wb_consumers 39945326 # num instructions consuming a value |
| 570system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 565system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 571system.cpu.iew.wb_rate 0.459416 # insts written-back per cycle 572system.cpu.iew.wb_fanout 0.720024 # average fanout of values written-back | 566system.cpu.iew.wb_rate 0.365258 # insts written-back per cycle 567system.cpu.iew.wb_fanout 0.719934 # average fanout of values written-back |
| 573system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 568system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 574system.cpu.commit.commitSquashedInsts 7990103 # The number of squashed insts skipped by commit 575system.cpu.commit.commitNonSpecStalls 661061 # The number of times commit has been forced to stall to communicate backwards 576system.cpu.commit.branchMispredicts 538190 # The number of times a branch was mispredicted 577system.cpu.commit.committed_per_cycle::samples 115283305 # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::mean 0.487246 # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::stdev 1.430050 # Number of insts commited each cycle | 569system.cpu.commit.commitSquashedInsts 8014233 # The number of squashed insts skipped by commit 570system.cpu.commit.commitNonSpecStalls 661221 # The number of times commit has been forced to stall to communicate backwards 571system.cpu.commit.branchMispredicts 539644 # The number of times a branch was mispredicted 572system.cpu.commit.committed_per_cycle::samples 145865842 # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::mean 0.385097 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::stdev 1.287358 # Number of insts commited each cycle |
| 580system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 575system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 581system.cpu.commit.committed_per_cycle::0 95489644 82.83% 82.83% # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::1 7861367 6.82% 89.65% # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::2 4279666 3.71% 93.36% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::3 2238986 1.94% 95.30% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::4 1753667 1.52% 96.83% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::5 610357 0.53% 97.35% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::6 475106 0.41% 97.77% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::7 479497 0.42% 98.18% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::8 2095015 1.82% 100.00% # Number of insts commited each cycle | 576system.cpu.commit.committed_per_cycle::0 126089885 86.44% 86.44% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::1 7851403 5.38% 91.82% # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::2 4272179 2.93% 94.75% # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::3 2235192 1.53% 96.29% # Number of insts commited each cycle 580system.cpu.commit.committed_per_cycle::4 1747101 1.20% 97.48% # Number of insts commited each cycle 581system.cpu.commit.committed_per_cycle::5 615790 0.42% 97.91% # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::6 475839 0.33% 98.23% # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::7 478833 0.33% 98.56% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::8 2099620 1.44% 100.00% # Number of insts commited each cycle |
| 590system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 585system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 593system.cpu.commit.committed_per_cycle::total 115283305 # Number of insts commited each cycle 594system.cpu.commit.committedInsts 56171345 # Number of instructions committed 595system.cpu.commit.committedOps 56171345 # Number of ops (including micro ops) committed | 588system.cpu.commit.committed_per_cycle::total 145865842 # Number of insts commited each cycle 589system.cpu.commit.committedInsts 56172516 # Number of instructions committed 590system.cpu.commit.committedOps 56172516 # Number of ops (including micro ops) committed |
| 596system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 591system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 597system.cpu.commit.refs 15469955 # Number of memory references committed 598system.cpu.commit.loads 9092138 # Number of loads committed 599system.cpu.commit.membars 226307 # Number of memory barriers committed 600system.cpu.commit.branches 8441356 # Number of branches committed | 592system.cpu.commit.refs 15471333 # Number of memory references committed 593system.cpu.commit.loads 9093055 # Number of loads committed 594system.cpu.commit.membars 226352 # Number of memory barriers committed 595system.cpu.commit.branches 8440752 # Number of branches committed |
| 601system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 596system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 602system.cpu.commit.int_insts 52021098 # Number of committed integer instructions. 603system.cpu.commit.function_calls 740502 # Number of function calls committed. 604system.cpu.commit.op_class_0::No_OpClass 3197878 5.69% 5.69% # Class of committed instruction 605system.cpu.commit.op_class_0::IntAlu 36220066 64.48% 70.17% # Class of committed instruction 606system.cpu.commit.op_class_0::IntMult 60657 0.11% 70.28% # Class of committed instruction | 597system.cpu.commit.int_insts 52021823 # Number of committed integer instructions. 598system.cpu.commit.function_calls 740586 # Number of function calls committed. 599system.cpu.commit.op_class_0::No_OpClass 3198106 5.69% 5.69% # Class of committed instruction 600system.cpu.commit.op_class_0::IntAlu 36219281 64.48% 70.17% # Class of committed instruction 601system.cpu.commit.op_class_0::IntMult 60683 0.11% 70.28% # Class of committed instruction |
| 607system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 608system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 609system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 610system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 611system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction | 602system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 603system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction 604system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 605system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 606system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction |
| 612system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction 613system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction 617system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction 618system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction 619system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction 620system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction 621system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction 622system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction 623system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction 624system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction 625system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction 626system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction 627system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction 630system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction 631system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction 632system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction 633system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction 634system.cpu.commit.op_class_0::MemRead 9318445 16.59% 86.95% # Class of committed instruction 635system.cpu.commit.op_class_0::MemWrite 6383767 11.36% 98.31% # Class of committed instruction 636system.cpu.commit.op_class_0::IprAccess 948811 1.69% 100.00% # Class of committed instruction | 607system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 608system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 617system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 618system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 619system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 620system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 621system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 622system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 623system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 624system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 625system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 626system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 627system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 629system.cpu.commit.op_class_0::MemRead 9319407 16.59% 86.95% # Class of committed instruction 630system.cpu.commit.op_class_0::MemWrite 6384233 11.37% 98.31% # Class of committed instruction 631system.cpu.commit.op_class_0::IprAccess 949085 1.69% 100.00% # Class of committed instruction |
| 637system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 632system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 638system.cpu.commit.op_class_0::total 56171345 # Class of committed instruction 639system.cpu.commit.bw_lim_events 2095015 # number cycles where commit BW limit reached 640system.cpu.rob.rob_reads 177100105 # The number of ROB reads 641system.cpu.rob.rob_writes 129718981 # The number of ROB writes 642system.cpu.timesIdled 575678 # Number of times that the entire CPU went into an idle state and unscheduled itself 643system.cpu.idleCycles 5566955 # Total number of cycles that the CPU has spent unscheduled due to idling 644system.cpu.quiesceCycles 3599729822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 645system.cpu.committedInsts 52980740 # Number of Instructions Simulated 646system.cpu.committedOps 52980740 # Number of Ops (including micro ops) Simulated 647system.cpu.cpi 2.307456 # CPI: Cycles Per Instruction 648system.cpu.cpi_total 2.307456 # CPI: Total CPI of All Threads 649system.cpu.ipc 0.433378 # IPC: Instructions Per Cycle 650system.cpu.ipc_total 0.433378 # IPC: Total IPC of All Threads 651system.cpu.int_regfile_reads 74560962 # number of integer regfile reads 652system.cpu.int_regfile_writes 40515010 # number of integer regfile writes 653system.cpu.fp_regfile_reads 167029 # number of floating regfile reads 654system.cpu.fp_regfile_writes 167528 # number of floating regfile writes 655system.cpu.misc_regfile_reads 2030483 # number of misc regfile reads 656system.cpu.misc_regfile_writes 939256 # number of misc regfile writes 657system.cpu.dcache.tags.replacements 1402429 # number of replacements 658system.cpu.dcache.tags.tagsinuse 511.994497 # Cycle average of tags in use 659system.cpu.dcache.tags.total_refs 11825966 # Total number of references to valid blocks. 660system.cpu.dcache.tags.sampled_refs 1402941 # Sample count of references to valid blocks. 661system.cpu.dcache.tags.avg_refs 8.429411 # Average number of references to valid blocks. 662system.cpu.dcache.tags.warmup_cycle 26175500 # Cycle when the warmup percentage was hit. 663system.cpu.dcache.tags.occ_blocks::cpu.data 511.994497 # Average occupied blocks per requestor 664system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 665system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy | 633system.cpu.commit.op_class_0::total 56172516 # Class of committed instruction 634system.cpu.commit.bw_lim_events 2099620 # number cycles where commit BW limit reached 635system.cpu.rob.rob_reads 207703277 # The number of ROB reads 636system.cpu.rob.rob_writes 129775597 # The number of ROB writes 637system.cpu.timesIdled 576321 # Number of times that the entire CPU went into an idle state and unscheduled itself 638system.cpu.idleCycles 6535603 # Total number of cycles that the CPU has spent unscheduled due to idling 639system.cpu.quiesceCycles 3597682440 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 640system.cpu.committedInsts 52981683 # Number of Instructions Simulated 641system.cpu.committedOps 52981683 # Number of Ops (including micro ops) Simulated 642system.cpu.cpi 2.903040 # CPI: Cycles Per Instruction 643system.cpu.cpi_total 2.903040 # CPI: Total CPI of All Threads 644system.cpu.ipc 0.344466 # IPC: Instructions Per Cycle 645system.cpu.ipc_total 0.344466 # IPC: Total IPC of All Threads 646system.cpu.int_regfile_reads 74566924 # number of integer regfile reads 647system.cpu.int_regfile_writes 40527176 # number of integer regfile writes 648system.cpu.fp_regfile_reads 167101 # number of floating regfile reads 649system.cpu.fp_regfile_writes 167535 # number of floating regfile writes 650system.cpu.misc_regfile_reads 1985778 # number of misc regfile reads 651system.cpu.misc_regfile_writes 939467 # number of misc regfile writes 652system.cpu.dcache.tags.replacements 1402095 # number of replacements 653system.cpu.dcache.tags.tagsinuse 511.992786 # Cycle average of tags in use 654system.cpu.dcache.tags.total_refs 11832212 # Total number of references to valid blocks. 655system.cpu.dcache.tags.sampled_refs 1402607 # Sample count of references to valid blocks. 656system.cpu.dcache.tags.avg_refs 8.435871 # Average number of references to valid blocks. 657system.cpu.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. 658system.cpu.dcache.tags.occ_blocks::cpu.data 511.992786 # Average occupied blocks per requestor 659system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 660system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy |
| 666system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 661system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 667system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id 668system.cpu.dcache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 669system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id | 662system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 663system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 664system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id |
| 670system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 665system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 671system.cpu.dcache.tags.tag_accesses 63836458 # Number of tag accesses 672system.cpu.dcache.tags.data_accesses 63836458 # Number of data accesses 673system.cpu.dcache.ReadReq_hits::cpu.data 7233922 # number of ReadReq hits 674system.cpu.dcache.ReadReq_hits::total 7233922 # number of ReadReq hits 675system.cpu.dcache.WriteReq_hits::cpu.data 4189857 # number of WriteReq hits 676system.cpu.dcache.WriteReq_hits::total 4189857 # number of WriteReq hits 677system.cpu.dcache.LoadLockedReq_hits::cpu.data 186093 # number of LoadLockedReq hits 678system.cpu.dcache.LoadLockedReq_hits::total 186093 # number of LoadLockedReq hits 679system.cpu.dcache.StoreCondReq_hits::cpu.data 215697 # number of StoreCondReq hits 680system.cpu.dcache.StoreCondReq_hits::total 215697 # number of StoreCondReq hits 681system.cpu.dcache.demand_hits::cpu.data 11423779 # number of demand (read+write) hits 682system.cpu.dcache.demand_hits::total 11423779 # number of demand (read+write) hits 683system.cpu.dcache.overall_hits::cpu.data 11423779 # number of overall hits 684system.cpu.dcache.overall_hits::total 11423779 # number of overall hits 685system.cpu.dcache.ReadReq_misses::cpu.data 1801919 # number of ReadReq misses 686system.cpu.dcache.ReadReq_misses::total 1801919 # number of ReadReq misses 687system.cpu.dcache.WriteReq_misses::cpu.data 1957536 # number of WriteReq misses 688system.cpu.dcache.WriteReq_misses::total 1957536 # number of WriteReq misses 689system.cpu.dcache.LoadLockedReq_misses::cpu.data 23327 # number of LoadLockedReq misses 690system.cpu.dcache.LoadLockedReq_misses::total 23327 # number of LoadLockedReq misses 691system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses 692system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses 693system.cpu.dcache.demand_misses::cpu.data 3759455 # number of demand (read+write) misses 694system.cpu.dcache.demand_misses::total 3759455 # number of demand (read+write) misses 695system.cpu.dcache.overall_misses::cpu.data 3759455 # number of overall misses 696system.cpu.dcache.overall_misses::total 3759455 # number of overall misses 697system.cpu.dcache.ReadReq_miss_latency::cpu.data 41733061500 # number of ReadReq miss cycles 698system.cpu.dcache.ReadReq_miss_latency::total 41733061500 # number of ReadReq miss cycles 699system.cpu.dcache.WriteReq_miss_latency::cpu.data 80455809465 # number of WriteReq miss cycles 700system.cpu.dcache.WriteReq_miss_latency::total 80455809465 # number of WriteReq miss cycles 701system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376093000 # number of LoadLockedReq miss cycles 702system.cpu.dcache.LoadLockedReq_miss_latency::total 376093000 # number of LoadLockedReq miss cycles 703system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 485000 # number of StoreCondReq miss cycles 704system.cpu.dcache.StoreCondReq_miss_latency::total 485000 # number of StoreCondReq miss cycles 705system.cpu.dcache.demand_miss_latency::cpu.data 122188870965 # number of demand (read+write) miss cycles 706system.cpu.dcache.demand_miss_latency::total 122188870965 # number of demand (read+write) miss cycles 707system.cpu.dcache.overall_miss_latency::cpu.data 122188870965 # number of overall miss cycles 708system.cpu.dcache.overall_miss_latency::total 122188870965 # number of overall miss cycles 709system.cpu.dcache.ReadReq_accesses::cpu.data 9035841 # number of ReadReq accesses(hits+misses) 710system.cpu.dcache.ReadReq_accesses::total 9035841 # number of ReadReq accesses(hits+misses) 711system.cpu.dcache.WriteReq_accesses::cpu.data 6147393 # number of WriteReq accesses(hits+misses) 712system.cpu.dcache.WriteReq_accesses::total 6147393 # number of WriteReq accesses(hits+misses) 713system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209420 # number of LoadLockedReq accesses(hits+misses) 714system.cpu.dcache.LoadLockedReq_accesses::total 209420 # number of LoadLockedReq accesses(hits+misses) 715system.cpu.dcache.StoreCondReq_accesses::cpu.data 215725 # number of StoreCondReq accesses(hits+misses) 716system.cpu.dcache.StoreCondReq_accesses::total 215725 # number of StoreCondReq accesses(hits+misses) 717system.cpu.dcache.demand_accesses::cpu.data 15183234 # number of demand (read+write) accesses 718system.cpu.dcache.demand_accesses::total 15183234 # number of demand (read+write) accesses 719system.cpu.dcache.overall_accesses::cpu.data 15183234 # number of overall (read+write) accesses 720system.cpu.dcache.overall_accesses::total 15183234 # number of overall (read+write) accesses 721system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199419 # miss rate for ReadReq accesses 722system.cpu.dcache.ReadReq_miss_rate::total 0.199419 # miss rate for ReadReq accesses 723system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318434 # miss rate for WriteReq accesses 724system.cpu.dcache.WriteReq_miss_rate::total 0.318434 # miss rate for WriteReq accesses 725system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111389 # miss rate for LoadLockedReq accesses 726system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111389 # miss rate for LoadLockedReq accesses 727system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses 728system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses 729system.cpu.dcache.demand_miss_rate::cpu.data 0.247606 # miss rate for demand accesses 730system.cpu.dcache.demand_miss_rate::total 0.247606 # miss rate for demand accesses 731system.cpu.dcache.overall_miss_rate::cpu.data 0.247606 # miss rate for overall accesses 732system.cpu.dcache.overall_miss_rate::total 0.247606 # miss rate for overall accesses 733system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23160.342668 # average ReadReq miss latency 734system.cpu.dcache.ReadReq_avg_miss_latency::total 23160.342668 # average ReadReq miss latency 735system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41100.551645 # average WriteReq miss latency 736system.cpu.dcache.WriteReq_avg_miss_latency::total 41100.551645 # average WriteReq miss latency 737system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16122.647576 # average LoadLockedReq miss latency 738system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16122.647576 # average LoadLockedReq miss latency 739system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17321.428571 # average StoreCondReq miss latency 740system.cpu.dcache.StoreCondReq_avg_miss_latency::total 17321.428571 # average StoreCondReq miss latency 741system.cpu.dcache.demand_avg_miss_latency::cpu.data 32501.751175 # average overall miss latency 742system.cpu.dcache.demand_avg_miss_latency::total 32501.751175 # average overall miss latency 743system.cpu.dcache.overall_avg_miss_latency::cpu.data 32501.751175 # average overall miss latency 744system.cpu.dcache.overall_avg_miss_latency::total 32501.751175 # average overall miss latency 745system.cpu.dcache.blocked_cycles::no_mshrs 4515997 # number of cycles access was blocked 746system.cpu.dcache.blocked_cycles::no_targets 2303 # number of cycles access was blocked 747system.cpu.dcache.blocked::no_mshrs 134454 # number of cycles access was blocked 748system.cpu.dcache.blocked::no_targets 26 # number of cycles access was blocked 749system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.587673 # average number of cycles each access was blocked 750system.cpu.dcache.avg_blocked_cycles::no_targets 88.576923 # average number of cycles each access was blocked | 666system.cpu.dcache.tags.tag_accesses 63847952 # Number of tag accesses 667system.cpu.dcache.tags.data_accesses 63847952 # Number of data accesses 668system.cpu.dcache.ReadReq_hits::cpu.data 7239475 # number of ReadReq hits 669system.cpu.dcache.ReadReq_hits::total 7239475 # number of ReadReq hits 670system.cpu.dcache.WriteReq_hits::cpu.data 4190405 # number of WriteReq hits 671system.cpu.dcache.WriteReq_hits::total 4190405 # number of WriteReq hits 672system.cpu.dcache.LoadLockedReq_hits::cpu.data 186164 # number of LoadLockedReq hits 673system.cpu.dcache.LoadLockedReq_hits::total 186164 # number of LoadLockedReq hits 674system.cpu.dcache.StoreCondReq_hits::cpu.data 215734 # number of StoreCondReq hits 675system.cpu.dcache.StoreCondReq_hits::total 215734 # number of StoreCondReq hits 676system.cpu.dcache.demand_hits::cpu.data 11429880 # number of demand (read+write) hits 677system.cpu.dcache.demand_hits::total 11429880 # number of demand (read+write) hits 678system.cpu.dcache.overall_hits::cpu.data 11429880 # number of overall hits 679system.cpu.dcache.overall_hits::total 11429880 # number of overall hits 680system.cpu.dcache.ReadReq_misses::cpu.data 1798792 # number of ReadReq misses 681system.cpu.dcache.ReadReq_misses::total 1798792 # number of ReadReq misses 682system.cpu.dcache.WriteReq_misses::cpu.data 1957410 # number of WriteReq misses 683system.cpu.dcache.WriteReq_misses::total 1957410 # number of WriteReq misses 684system.cpu.dcache.LoadLockedReq_misses::cpu.data 23330 # number of LoadLockedReq misses 685system.cpu.dcache.LoadLockedReq_misses::total 23330 # number of LoadLockedReq misses 686system.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses 687system.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses 688system.cpu.dcache.demand_misses::cpu.data 3756202 # number of demand (read+write) misses 689system.cpu.dcache.demand_misses::total 3756202 # number of demand (read+write) misses 690system.cpu.dcache.overall_misses::cpu.data 3756202 # number of overall misses 691system.cpu.dcache.overall_misses::total 3756202 # number of overall misses 692system.cpu.dcache.ReadReq_miss_latency::cpu.data 57198715500 # number of ReadReq miss cycles 693system.cpu.dcache.ReadReq_miss_latency::total 57198715500 # number of ReadReq miss cycles 694system.cpu.dcache.WriteReq_miss_latency::cpu.data 116967363039 # number of WriteReq miss cycles 695system.cpu.dcache.WriteReq_miss_latency::total 116967363039 # number of WriteReq miss cycles 696system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 446591500 # number of LoadLockedReq miss cycles 697system.cpu.dcache.LoadLockedReq_miss_latency::total 446591500 # number of LoadLockedReq miss cycles 698system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 850000 # number of StoreCondReq miss cycles 699system.cpu.dcache.StoreCondReq_miss_latency::total 850000 # number of StoreCondReq miss cycles 700system.cpu.dcache.demand_miss_latency::cpu.data 174166078539 # number of demand (read+write) miss cycles 701system.cpu.dcache.demand_miss_latency::total 174166078539 # number of demand (read+write) miss cycles 702system.cpu.dcache.overall_miss_latency::cpu.data 174166078539 # number of overall miss cycles 703system.cpu.dcache.overall_miss_latency::total 174166078539 # number of overall miss cycles 704system.cpu.dcache.ReadReq_accesses::cpu.data 9038267 # number of ReadReq accesses(hits+misses) 705system.cpu.dcache.ReadReq_accesses::total 9038267 # number of ReadReq accesses(hits+misses) 706system.cpu.dcache.WriteReq_accesses::cpu.data 6147815 # number of WriteReq accesses(hits+misses) 707system.cpu.dcache.WriteReq_accesses::total 6147815 # number of WriteReq accesses(hits+misses) 708system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209494 # number of LoadLockedReq accesses(hits+misses) 709system.cpu.dcache.LoadLockedReq_accesses::total 209494 # number of LoadLockedReq accesses(hits+misses) 710system.cpu.dcache.StoreCondReq_accesses::cpu.data 215760 # number of StoreCondReq accesses(hits+misses) 711system.cpu.dcache.StoreCondReq_accesses::total 215760 # number of StoreCondReq accesses(hits+misses) 712system.cpu.dcache.demand_accesses::cpu.data 15186082 # number of demand (read+write) accesses 713system.cpu.dcache.demand_accesses::total 15186082 # number of demand (read+write) accesses 714system.cpu.dcache.overall_accesses::cpu.data 15186082 # number of overall (read+write) accesses 715system.cpu.dcache.overall_accesses::total 15186082 # number of overall (read+write) accesses 716system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199020 # miss rate for ReadReq accesses 717system.cpu.dcache.ReadReq_miss_rate::total 0.199020 # miss rate for ReadReq accesses 718system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318391 # miss rate for WriteReq accesses 719system.cpu.dcache.WriteReq_miss_rate::total 0.318391 # miss rate for WriteReq accesses 720system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111364 # miss rate for LoadLockedReq accesses 721system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111364 # miss rate for LoadLockedReq accesses 722system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses 723system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses 724system.cpu.dcache.demand_miss_rate::cpu.data 0.247345 # miss rate for demand accesses 725system.cpu.dcache.demand_miss_rate::total 0.247345 # miss rate for demand accesses 726system.cpu.dcache.overall_miss_rate::cpu.data 0.247345 # miss rate for overall accesses 727system.cpu.dcache.overall_miss_rate::total 0.247345 # miss rate for overall accesses 728system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31798.404429 # average ReadReq miss latency 729system.cpu.dcache.ReadReq_avg_miss_latency::total 31798.404429 # average ReadReq miss latency 730system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59756.189577 # average WriteReq miss latency 731system.cpu.dcache.WriteReq_avg_miss_latency::total 59756.189577 # average WriteReq miss latency 732system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19142.370339 # average LoadLockedReq miss latency 733system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19142.370339 # average LoadLockedReq miss latency 734system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 32692.307692 # average StoreCondReq miss latency 735system.cpu.dcache.StoreCondReq_avg_miss_latency::total 32692.307692 # average StoreCondReq miss latency 736system.cpu.dcache.demand_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency 737system.cpu.dcache.demand_avg_miss_latency::total 46367.601779 # average overall miss latency 738system.cpu.dcache.overall_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency 739system.cpu.dcache.overall_avg_miss_latency::total 46367.601779 # average overall miss latency 740system.cpu.dcache.blocked_cycles::no_mshrs 7156530 # number of cycles access was blocked 741system.cpu.dcache.blocked_cycles::no_targets 5457 # number of cycles access was blocked 742system.cpu.dcache.blocked::no_mshrs 133923 # number of cycles access was blocked 743system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked 744system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437647 # average number of cycles each access was blocked 745system.cpu.dcache.avg_blocked_cycles::no_targets 188.172414 # average number of cycles each access was blocked |
| 751system.cpu.dcache.fast_writes 0 # number of fast writes performed 752system.cpu.dcache.cache_copies 0 # number of cache copies performed | 746system.cpu.dcache.fast_writes 0 # number of fast writes performed 747system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 753system.cpu.dcache.writebacks::writebacks 841625 # number of writebacks 754system.cpu.dcache.writebacks::total 841625 # number of writebacks 755system.cpu.dcache.ReadReq_mshr_hits::cpu.data 707636 # number of ReadReq MSHR hits 756system.cpu.dcache.ReadReq_mshr_hits::total 707636 # number of ReadReq MSHR hits 757system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666818 # number of WriteReq MSHR hits 758system.cpu.dcache.WriteReq_mshr_hits::total 1666818 # number of WriteReq MSHR hits 759system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5179 # number of LoadLockedReq MSHR hits 760system.cpu.dcache.LoadLockedReq_mshr_hits::total 5179 # number of LoadLockedReq MSHR hits 761system.cpu.dcache.demand_mshr_hits::cpu.data 2374454 # number of demand (read+write) MSHR hits 762system.cpu.dcache.demand_mshr_hits::total 2374454 # number of demand (read+write) MSHR hits 763system.cpu.dcache.overall_mshr_hits::cpu.data 2374454 # number of overall MSHR hits 764system.cpu.dcache.overall_mshr_hits::total 2374454 # number of overall MSHR hits 765system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1094283 # number of ReadReq MSHR misses 766system.cpu.dcache.ReadReq_mshr_misses::total 1094283 # number of ReadReq MSHR misses 767system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290718 # number of WriteReq MSHR misses 768system.cpu.dcache.WriteReq_mshr_misses::total 290718 # number of WriteReq MSHR misses 769system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18148 # number of LoadLockedReq MSHR misses 770system.cpu.dcache.LoadLockedReq_mshr_misses::total 18148 # number of LoadLockedReq MSHR misses 771system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses 772system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses 773system.cpu.dcache.demand_mshr_misses::cpu.data 1385001 # number of demand (read+write) MSHR misses 774system.cpu.dcache.demand_mshr_misses::total 1385001 # number of demand (read+write) MSHR misses 775system.cpu.dcache.overall_mshr_misses::cpu.data 1385001 # number of overall MSHR misses 776system.cpu.dcache.overall_mshr_misses::total 1385001 # number of overall MSHR misses | 748system.cpu.dcache.writebacks::writebacks 841276 # number of writebacks 749system.cpu.dcache.writebacks::total 841276 # number of writebacks 750system.cpu.dcache.ReadReq_mshr_hits::cpu.data 704782 # number of ReadReq MSHR hits 751system.cpu.dcache.ReadReq_mshr_hits::total 704782 # number of ReadReq MSHR hits 752system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666649 # number of WriteReq MSHR hits 753system.cpu.dcache.WriteReq_mshr_hits::total 1666649 # number of WriteReq MSHR hits 754system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5284 # number of LoadLockedReq MSHR hits 755system.cpu.dcache.LoadLockedReq_mshr_hits::total 5284 # number of LoadLockedReq MSHR hits 756system.cpu.dcache.demand_mshr_hits::cpu.data 2371431 # number of demand (read+write) MSHR hits 757system.cpu.dcache.demand_mshr_hits::total 2371431 # number of demand (read+write) MSHR hits 758system.cpu.dcache.overall_mshr_hits::cpu.data 2371431 # number of overall MSHR hits 759system.cpu.dcache.overall_mshr_hits::total 2371431 # number of overall MSHR hits 760system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1094010 # number of ReadReq MSHR misses 761system.cpu.dcache.ReadReq_mshr_misses::total 1094010 # number of ReadReq MSHR misses 762system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290761 # number of WriteReq MSHR misses 763system.cpu.dcache.WriteReq_mshr_misses::total 290761 # number of WriteReq MSHR misses 764system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18046 # number of LoadLockedReq MSHR misses 765system.cpu.dcache.LoadLockedReq_mshr_misses::total 18046 # number of LoadLockedReq MSHR misses 766system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses 767system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses 768system.cpu.dcache.demand_mshr_misses::cpu.data 1384771 # number of demand (read+write) MSHR misses 769system.cpu.dcache.demand_mshr_misses::total 1384771 # number of demand (read+write) MSHR misses 770system.cpu.dcache.overall_mshr_misses::cpu.data 1384771 # number of overall MSHR misses 771system.cpu.dcache.overall_mshr_misses::total 1384771 # number of overall MSHR misses |
| 777system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 778system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 772system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 773system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 779system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable 780system.cpu.dcache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable 781system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses 782system.cpu.dcache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses 783system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30550296500 # number of ReadReq MSHR miss cycles 784system.cpu.dcache.ReadReq_mshr_miss_latency::total 30550296500 # number of ReadReq MSHR miss cycles 785system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12634151241 # number of WriteReq MSHR miss cycles 786system.cpu.dcache.WriteReq_mshr_miss_latency::total 12634151241 # number of WriteReq MSHR miss cycles 787system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226327000 # number of LoadLockedReq MSHR miss cycles 788system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226327000 # number of LoadLockedReq MSHR miss cycles 789system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 457000 # number of StoreCondReq MSHR miss cycles 790system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 457000 # number of StoreCondReq MSHR miss cycles 791system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43184447741 # number of demand (read+write) MSHR miss cycles 792system.cpu.dcache.demand_mshr_miss_latency::total 43184447741 # number of demand (read+write) MSHR miss cycles 793system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43184447741 # number of overall MSHR miss cycles 794system.cpu.dcache.overall_mshr_miss_latency::total 43184447741 # number of overall MSHR miss cycles 795system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450758000 # number of ReadReq MSHR uncacheable cycles 796system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450758000 # number of ReadReq MSHR uncacheable cycles 797system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035709998 # number of WriteReq MSHR uncacheable cycles 798system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035709998 # number of WriteReq MSHR uncacheable cycles 799system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486467998 # number of overall MSHR uncacheable cycles 800system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486467998 # number of overall MSHR uncacheable cycles 801system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121105 # mshr miss rate for ReadReq accesses 802system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121105 # mshr miss rate for ReadReq accesses 803system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047291 # mshr miss rate for WriteReq accesses 804system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047291 # mshr miss rate for WriteReq accesses 805system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086658 # mshr miss rate for LoadLockedReq accesses 806system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086658 # mshr miss rate for LoadLockedReq accesses 807system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses 808system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses 809system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for demand accesses 810system.cpu.dcache.demand_mshr_miss_rate::total 0.091219 # mshr miss rate for demand accesses 811system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for overall accesses 812system.cpu.dcache.overall_mshr_miss_rate::total 0.091219 # mshr miss rate for overall accesses 813system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27918.094771 # average ReadReq mshr miss latency 814system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27918.094771 # average ReadReq mshr miss latency 815system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43458.441655 # average WriteReq mshr miss latency 816system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43458.441655 # average WriteReq mshr miss latency 817system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12471.181397 # average LoadLockedReq mshr miss latency 818system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12471.181397 # average LoadLockedReq mshr miss latency 819system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16321.428571 # average StoreCondReq mshr miss latency 820system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16321.428571 # average StoreCondReq mshr miss latency 821system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency 822system.cpu.dcache.demand_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency 823system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency 825system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209344.588745 # average ReadReq mshr uncacheable latency 826system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209344.588745 # average ReadReq mshr uncacheable latency 827system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212141.517090 # average WriteReq mshr uncacheable latency 828system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212141.517090 # average WriteReq mshr uncacheable latency 829system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210968.655331 # average overall mshr uncacheable latency 830system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210968.655331 # average overall mshr uncacheable latency | 774system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 775system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 776system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 777system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 778system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44554526500 # number of ReadReq MSHR miss cycles 779system.cpu.dcache.ReadReq_mshr_miss_latency::total 44554526500 # number of ReadReq MSHR miss cycles 780system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18468782348 # number of WriteReq MSHR miss cycles 781system.cpu.dcache.WriteReq_mshr_miss_latency::total 18468782348 # number of WriteReq MSHR miss cycles 782system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 228783500 # number of LoadLockedReq MSHR miss cycles 783system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 228783500 # number of LoadLockedReq MSHR miss cycles 784system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 824000 # number of StoreCondReq MSHR miss cycles 785system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 824000 # number of StoreCondReq MSHR miss cycles 786system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63023308848 # number of demand (read+write) MSHR miss cycles 787system.cpu.dcache.demand_mshr_miss_latency::total 63023308848 # number of demand (read+write) MSHR miss cycles 788system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63023308848 # number of overall MSHR miss cycles 789system.cpu.dcache.overall_mshr_miss_latency::total 63023308848 # number of overall MSHR miss cycles 790system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450570000 # number of ReadReq MSHR uncacheable cycles 791system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450570000 # number of ReadReq MSHR uncacheable cycles 792system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2036143500 # number of WriteReq MSHR uncacheable cycles 793system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2036143500 # number of WriteReq MSHR uncacheable cycles 794system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486713500 # number of overall MSHR uncacheable cycles 795system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486713500 # number of overall MSHR uncacheable cycles 796system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121042 # mshr miss rate for ReadReq accesses 797system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121042 # mshr miss rate for ReadReq accesses 798system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047295 # mshr miss rate for WriteReq accesses 799system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047295 # mshr miss rate for WriteReq accesses 800system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086141 # mshr miss rate for LoadLockedReq accesses 801system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086141 # mshr miss rate for LoadLockedReq accesses 802system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses 803system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses 804system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for demand accesses 805system.cpu.dcache.demand_mshr_miss_rate::total 0.091187 # mshr miss rate for demand accesses 806system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for overall accesses 807system.cpu.dcache.overall_mshr_miss_rate::total 0.091187 # mshr miss rate for overall accesses 808system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40725.885961 # average ReadReq mshr miss latency 809system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40725.885961 # average ReadReq mshr miss latency 810system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63518.774347 # average WriteReq mshr miss latency 811system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63518.774347 # average WriteReq mshr miss latency 812system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12677.795633 # average LoadLockedReq mshr miss latency 813system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12677.795633 # average LoadLockedReq mshr miss latency 814system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 31692.307692 # average StoreCondReq mshr miss latency 815system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 31692.307692 # average StoreCondReq mshr miss latency 816system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency 817system.cpu.dcache.demand_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency 818system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency 819system.cpu.dcache.overall_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency 820system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209317.460317 # average ReadReq mshr uncacheable latency 821system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209317.460317 # average ReadReq mshr uncacheable latency 822system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.477599 # average WriteReq mshr uncacheable latency 823system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.477599 # average WriteReq mshr uncacheable latency 824system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210957.980397 # average overall mshr uncacheable latency 825system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210957.980397 # average overall mshr uncacheable latency |
| 831system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 826system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 832system.cpu.icache.tags.replacements 1038549 # number of replacements 833system.cpu.icache.tags.tagsinuse 509.170339 # Cycle average of tags in use 834system.cpu.icache.tags.total_refs 7895321 # Total number of references to valid blocks. 835system.cpu.icache.tags.sampled_refs 1039057 # Sample count of references to valid blocks. 836system.cpu.icache.tags.avg_refs 7.598545 # Average number of references to valid blocks. 837system.cpu.icache.tags.warmup_cycle 28146856500 # Cycle when the warmup percentage was hit. 838system.cpu.icache.tags.occ_blocks::cpu.inst 509.170339 # Average occupied blocks per requestor 839system.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy 840system.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy | 827system.cpu.icache.tags.replacements 1038950 # number of replacements 828system.cpu.icache.tags.tagsinuse 507.834309 # Cycle average of tags in use 829system.cpu.icache.tags.total_refs 7904301 # Total number of references to valid blocks. 830system.cpu.icache.tags.sampled_refs 1039458 # Sample count of references to valid blocks. 831system.cpu.icache.tags.avg_refs 7.604252 # Average number of references to valid blocks. 832system.cpu.icache.tags.warmup_cycle 42289841500 # Cycle when the warmup percentage was hit. 833system.cpu.icache.tags.occ_blocks::cpu.inst 507.834309 # Average occupied blocks per requestor 834system.cpu.icache.tags.occ_percent::cpu.inst 0.991864 # Average percentage of cache occupancy 835system.cpu.icache.tags.occ_percent::total 0.991864 # Average percentage of cache occupancy |
| 841system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id | 836system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id |
| 842system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 843system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 844system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id | 837system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id |
| 845system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id | 840system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id |
| 846system.cpu.icache.tags.tag_accesses 10027494 # Number of tag accesses 847system.cpu.icache.tags.data_accesses 10027494 # Number of data accesses 848system.cpu.icache.ReadReq_hits::cpu.inst 7895322 # number of ReadReq hits 849system.cpu.icache.ReadReq_hits::total 7895322 # number of ReadReq hits 850system.cpu.icache.demand_hits::cpu.inst 7895322 # number of demand (read+write) hits 851system.cpu.icache.demand_hits::total 7895322 # number of demand (read+write) hits 852system.cpu.icache.overall_hits::cpu.inst 7895322 # number of overall hits 853system.cpu.icache.overall_hits::total 7895322 # number of overall hits 854system.cpu.icache.ReadReq_misses::cpu.inst 1092746 # number of ReadReq misses 855system.cpu.icache.ReadReq_misses::total 1092746 # number of ReadReq misses 856system.cpu.icache.demand_misses::cpu.inst 1092746 # number of demand (read+write) misses 857system.cpu.icache.demand_misses::total 1092746 # number of demand (read+write) misses 858system.cpu.icache.overall_misses::cpu.inst 1092746 # number of overall misses 859system.cpu.icache.overall_misses::total 1092746 # number of overall misses 860system.cpu.icache.ReadReq_miss_latency::cpu.inst 15273300993 # number of ReadReq miss cycles 861system.cpu.icache.ReadReq_miss_latency::total 15273300993 # number of ReadReq miss cycles 862system.cpu.icache.demand_miss_latency::cpu.inst 15273300993 # number of demand (read+write) miss cycles 863system.cpu.icache.demand_miss_latency::total 15273300993 # number of demand (read+write) miss cycles 864system.cpu.icache.overall_miss_latency::cpu.inst 15273300993 # number of overall miss cycles 865system.cpu.icache.overall_miss_latency::total 15273300993 # number of overall miss cycles 866system.cpu.icache.ReadReq_accesses::cpu.inst 8988068 # number of ReadReq accesses(hits+misses) 867system.cpu.icache.ReadReq_accesses::total 8988068 # number of ReadReq accesses(hits+misses) 868system.cpu.icache.demand_accesses::cpu.inst 8988068 # number of demand (read+write) accesses 869system.cpu.icache.demand_accesses::total 8988068 # number of demand (read+write) accesses 870system.cpu.icache.overall_accesses::cpu.inst 8988068 # number of overall (read+write) accesses 871system.cpu.icache.overall_accesses::total 8988068 # number of overall (read+write) accesses 872system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121577 # miss rate for ReadReq accesses 873system.cpu.icache.ReadReq_miss_rate::total 0.121577 # miss rate for ReadReq accesses 874system.cpu.icache.demand_miss_rate::cpu.inst 0.121577 # miss rate for demand accesses 875system.cpu.icache.demand_miss_rate::total 0.121577 # miss rate for demand accesses 876system.cpu.icache.overall_miss_rate::cpu.inst 0.121577 # miss rate for overall accesses 877system.cpu.icache.overall_miss_rate::total 0.121577 # miss rate for overall accesses 878system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.990987 # average ReadReq miss latency 879system.cpu.icache.ReadReq_avg_miss_latency::total 13976.990987 # average ReadReq miss latency 880system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency 881system.cpu.icache.demand_avg_miss_latency::total 13976.990987 # average overall miss latency 882system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency 883system.cpu.icache.overall_avg_miss_latency::total 13976.990987 # average overall miss latency 884system.cpu.icache.blocked_cycles::no_mshrs 6859 # number of cycles access was blocked | 841system.cpu.icache.tags.tag_accesses 10037466 # Number of tag accesses 842system.cpu.icache.tags.data_accesses 10037466 # Number of data accesses 843system.cpu.icache.ReadReq_hits::cpu.inst 7904302 # number of ReadReq hits 844system.cpu.icache.ReadReq_hits::total 7904302 # number of ReadReq hits 845system.cpu.icache.demand_hits::cpu.inst 7904302 # number of demand (read+write) hits 846system.cpu.icache.demand_hits::total 7904302 # number of demand (read+write) hits 847system.cpu.icache.overall_hits::cpu.inst 7904302 # number of overall hits 848system.cpu.icache.overall_hits::total 7904302 # number of overall hits 849system.cpu.icache.ReadReq_misses::cpu.inst 1093336 # number of ReadReq misses 850system.cpu.icache.ReadReq_misses::total 1093336 # number of ReadReq misses 851system.cpu.icache.demand_misses::cpu.inst 1093336 # number of demand (read+write) misses 852system.cpu.icache.demand_misses::total 1093336 # number of demand (read+write) misses 853system.cpu.icache.overall_misses::cpu.inst 1093336 # number of overall misses 854system.cpu.icache.overall_misses::total 1093336 # number of overall misses 855system.cpu.icache.ReadReq_miss_latency::cpu.inst 16294267486 # number of ReadReq miss cycles 856system.cpu.icache.ReadReq_miss_latency::total 16294267486 # number of ReadReq miss cycles 857system.cpu.icache.demand_miss_latency::cpu.inst 16294267486 # number of demand (read+write) miss cycles 858system.cpu.icache.demand_miss_latency::total 16294267486 # number of demand (read+write) miss cycles 859system.cpu.icache.overall_miss_latency::cpu.inst 16294267486 # number of overall miss cycles 860system.cpu.icache.overall_miss_latency::total 16294267486 # number of overall miss cycles 861system.cpu.icache.ReadReq_accesses::cpu.inst 8997638 # number of ReadReq accesses(hits+misses) 862system.cpu.icache.ReadReq_accesses::total 8997638 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.demand_accesses::cpu.inst 8997638 # number of demand (read+write) accesses 864system.cpu.icache.demand_accesses::total 8997638 # number of demand (read+write) accesses 865system.cpu.icache.overall_accesses::cpu.inst 8997638 # number of overall (read+write) accesses 866system.cpu.icache.overall_accesses::total 8997638 # number of overall (read+write) accesses 867system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses 868system.cpu.icache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses 869system.cpu.icache.demand_miss_rate::cpu.inst 0.121514 # miss rate for demand accesses 870system.cpu.icache.demand_miss_rate::total 0.121514 # miss rate for demand accesses 871system.cpu.icache.overall_miss_rate::cpu.inst 0.121514 # miss rate for overall accesses 872system.cpu.icache.overall_miss_rate::total 0.121514 # miss rate for overall accesses 873system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.257083 # average ReadReq miss latency 874system.cpu.icache.ReadReq_avg_miss_latency::total 14903.257083 # average ReadReq miss latency 875system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.257083 # average overall miss latency 876system.cpu.icache.demand_avg_miss_latency::total 14903.257083 # average overall miss latency 877system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.257083 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::total 14903.257083 # average overall miss latency 879system.cpu.icache.blocked_cycles::no_mshrs 10533 # number of cycles access was blocked |
| 885system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 880system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 886system.cpu.icache.blocked::no_mshrs 220 # number of cycles access was blocked | 881system.cpu.icache.blocked::no_mshrs 301 # number of cycles access was blocked |
| 887system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 882system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 888system.cpu.icache.avg_blocked_cycles::no_mshrs 31.177273 # average number of cycles each access was blocked | 883system.cpu.icache.avg_blocked_cycles::no_mshrs 34.993355 # average number of cycles each access was blocked |
| 889system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 890system.cpu.icache.fast_writes 0 # number of fast writes performed 891system.cpu.icache.cache_copies 0 # number of cache copies performed | 884system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 885system.cpu.icache.fast_writes 0 # number of fast writes performed 886system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 892system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53320 # number of ReadReq MSHR hits 893system.cpu.icache.ReadReq_mshr_hits::total 53320 # number of ReadReq MSHR hits 894system.cpu.icache.demand_mshr_hits::cpu.inst 53320 # number of demand (read+write) MSHR hits 895system.cpu.icache.demand_mshr_hits::total 53320 # number of demand (read+write) MSHR hits 896system.cpu.icache.overall_mshr_hits::cpu.inst 53320 # number of overall MSHR hits 897system.cpu.icache.overall_mshr_hits::total 53320 # number of overall MSHR hits 898system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039426 # number of ReadReq MSHR misses 899system.cpu.icache.ReadReq_mshr_misses::total 1039426 # number of ReadReq MSHR misses 900system.cpu.icache.demand_mshr_misses::cpu.inst 1039426 # number of demand (read+write) MSHR misses 901system.cpu.icache.demand_mshr_misses::total 1039426 # number of demand (read+write) MSHR misses 902system.cpu.icache.overall_mshr_misses::cpu.inst 1039426 # number of overall MSHR misses 903system.cpu.icache.overall_mshr_misses::total 1039426 # number of overall MSHR misses 904system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13594657497 # number of ReadReq MSHR miss cycles 905system.cpu.icache.ReadReq_mshr_miss_latency::total 13594657497 # number of ReadReq MSHR miss cycles 906system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13594657497 # number of demand (read+write) MSHR miss cycles 907system.cpu.icache.demand_mshr_miss_latency::total 13594657497 # number of demand (read+write) MSHR miss cycles 908system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13594657497 # number of overall MSHR miss cycles 909system.cpu.icache.overall_mshr_miss_latency::total 13594657497 # number of overall MSHR miss cycles 910system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for ReadReq accesses 911system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115645 # mshr miss rate for ReadReq accesses 912system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for demand accesses 913system.cpu.icache.demand_mshr_miss_rate::total 0.115645 # mshr miss rate for demand accesses 914system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for overall accesses 915system.cpu.icache.overall_mshr_miss_rate::total 0.115645 # mshr miss rate for overall accesses 916system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13079.004659 # average ReadReq mshr miss latency 917system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13079.004659 # average ReadReq mshr miss latency 918system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13079.004659 # average overall mshr miss latency 919system.cpu.icache.demand_avg_mshr_miss_latency::total 13079.004659 # average overall mshr miss latency 920system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13079.004659 # average overall mshr miss latency 921system.cpu.icache.overall_avg_mshr_miss_latency::total 13079.004659 # average overall mshr miss latency | 887system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53508 # number of ReadReq MSHR hits 888system.cpu.icache.ReadReq_mshr_hits::total 53508 # number of ReadReq MSHR hits 889system.cpu.icache.demand_mshr_hits::cpu.inst 53508 # number of demand (read+write) MSHR hits 890system.cpu.icache.demand_mshr_hits::total 53508 # number of demand (read+write) MSHR hits 891system.cpu.icache.overall_mshr_hits::cpu.inst 53508 # number of overall MSHR hits 892system.cpu.icache.overall_mshr_hits::total 53508 # number of overall MSHR hits 893system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039828 # number of ReadReq MSHR misses 894system.cpu.icache.ReadReq_mshr_misses::total 1039828 # number of ReadReq MSHR misses 895system.cpu.icache.demand_mshr_misses::cpu.inst 1039828 # number of demand (read+write) MSHR misses 896system.cpu.icache.demand_mshr_misses::total 1039828 # number of demand (read+write) MSHR misses 897system.cpu.icache.overall_mshr_misses::cpu.inst 1039828 # number of overall MSHR misses 898system.cpu.icache.overall_mshr_misses::total 1039828 # number of overall MSHR misses 899system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14359854493 # number of ReadReq MSHR miss cycles 900system.cpu.icache.ReadReq_mshr_miss_latency::total 14359854493 # number of ReadReq MSHR miss cycles 901system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14359854493 # number of demand (read+write) MSHR miss cycles 902system.cpu.icache.demand_mshr_miss_latency::total 14359854493 # number of demand (read+write) MSHR miss cycles 903system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14359854493 # number of overall MSHR miss cycles 904system.cpu.icache.overall_mshr_miss_latency::total 14359854493 # number of overall MSHR miss cycles 905system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for ReadReq accesses 906system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115567 # mshr miss rate for ReadReq accesses 907system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for demand accesses 908system.cpu.icache.demand_mshr_miss_rate::total 0.115567 # mshr miss rate for demand accesses 909system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for overall accesses 910system.cpu.icache.overall_mshr_miss_rate::total 0.115567 # mshr miss rate for overall accesses 911system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13809.836332 # average ReadReq mshr miss latency 912system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13809.836332 # average ReadReq mshr miss latency 913system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency 914system.cpu.icache.demand_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency 915system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency 916system.cpu.icache.overall_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency |
| 922system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 917system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 923system.cpu.l2cache.tags.replacements 338316 # number of replacements 924system.cpu.l2cache.tags.tagsinuse 65333.743960 # Cycle average of tags in use 925system.cpu.l2cache.tags.total_refs 4173914 # Total number of references to valid blocks. 926system.cpu.l2cache.tags.sampled_refs 403482 # Sample count of references to valid blocks. 927system.cpu.l2cache.tags.avg_refs 10.344734 # Average number of references to valid blocks. 928system.cpu.l2cache.tags.warmup_cycle 5938026000 # Cycle when the warmup percentage was hit. 929system.cpu.l2cache.tags.occ_blocks::writebacks 53662.904675 # Average occupied blocks per requestor 930system.cpu.l2cache.tags.occ_blocks::cpu.inst 5355.130521 # Average occupied blocks per requestor 931system.cpu.l2cache.tags.occ_blocks::cpu.data 6315.708764 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_percent::writebacks 0.818831 # Average percentage of cache occupancy 933system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081713 # Average percentage of cache occupancy 934system.cpu.l2cache.tags.occ_percent::cpu.data 0.096370 # Average percentage of cache occupancy 935system.cpu.l2cache.tags.occ_percent::total 0.996914 # Average percentage of cache occupancy 936system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id 937system.cpu.l2cache.tags.age_task_id_blocks_1024::0 494 # Occupied blocks per task id 938system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3498 # Occupied blocks per task id 939system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id 940system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2393 # Occupied blocks per task id 941system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55462 # Occupied blocks per task id 942system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id 943system.cpu.l2cache.tags.tag_accesses 39757135 # Number of tag accesses 944system.cpu.l2cache.tags.data_accesses 39757135 # Number of data accesses 945system.cpu.l2cache.Writeback_hits::writebacks 841625 # number of Writeback hits 946system.cpu.l2cache.Writeback_hits::total 841625 # number of Writeback hits 947system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits 948system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits 949system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 950system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 951system.cpu.l2cache.ReadExReq_hits::cpu.data 185982 # number of ReadExReq hits 952system.cpu.l2cache.ReadExReq_hits::total 185982 # number of ReadExReq hits 953system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1024048 # number of ReadCleanReq hits 954system.cpu.l2cache.ReadCleanReq_hits::total 1024048 # number of ReadCleanReq hits 955system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827700 # number of ReadSharedReq hits 956system.cpu.l2cache.ReadSharedReq_hits::total 827700 # number of ReadSharedReq hits 957system.cpu.l2cache.demand_hits::cpu.inst 1024048 # number of demand (read+write) hits 958system.cpu.l2cache.demand_hits::cpu.data 1013682 # number of demand (read+write) hits 959system.cpu.l2cache.demand_hits::total 2037730 # number of demand (read+write) hits 960system.cpu.l2cache.overall_hits::cpu.inst 1024048 # number of overall hits 961system.cpu.l2cache.overall_hits::cpu.data 1013682 # number of overall hits 962system.cpu.l2cache.overall_hits::total 2037730 # number of overall hits | 918system.cpu.l2cache.tags.replacements 338309 # number of replacements 919system.cpu.l2cache.tags.tagsinuse 65280.236813 # Cycle average of tags in use 920system.cpu.l2cache.tags.total_refs 4173910 # Total number of references to valid blocks. 921system.cpu.l2cache.tags.sampled_refs 403476 # Sample count of references to valid blocks. 922system.cpu.l2cache.tags.avg_refs 10.344878 # Average number of references to valid blocks. 923system.cpu.l2cache.tags.warmup_cycle 9183094000 # Cycle when the warmup percentage was hit. 924system.cpu.l2cache.tags.occ_blocks::writebacks 53277.296150 # Average occupied blocks per requestor 925system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.937838 # Average occupied blocks per requestor 926system.cpu.l2cache.tags.occ_blocks::cpu.data 6694.002825 # Average occupied blocks per requestor 927system.cpu.l2cache.tags.occ_percent::writebacks 0.812947 # Average percentage of cache occupancy 928system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081008 # Average percentage of cache occupancy 929system.cpu.l2cache.tags.occ_percent::cpu.data 0.102142 # Average percentage of cache occupancy 930system.cpu.l2cache.tags.occ_percent::total 0.996097 # Average percentage of cache occupancy 931system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id 932system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 933system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3483 # Occupied blocks per task id 934system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3330 # Occupied blocks per task id 935system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2415 # Occupied blocks per task id 936system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55446 # Occupied blocks per task id 937system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id 938system.cpu.l2cache.tags.tag_accesses 39757210 # Number of tag accesses 939system.cpu.l2cache.tags.data_accesses 39757210 # Number of data accesses 940system.cpu.l2cache.Writeback_hits::writebacks 841276 # number of Writeback hits 941system.cpu.l2cache.Writeback_hits::total 841276 # number of Writeback hits 942system.cpu.l2cache.UpgradeReq_hits::cpu.data 30 # number of UpgradeReq hits 943system.cpu.l2cache.UpgradeReq_hits::total 30 # number of UpgradeReq hits 944system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 19 # number of SCUpgradeReq hits 945system.cpu.l2cache.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits 946system.cpu.l2cache.ReadExReq_hits::cpu.data 186016 # number of ReadExReq hits 947system.cpu.l2cache.ReadExReq_hits::total 186016 # number of ReadExReq hits 948system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1024478 # number of ReadCleanReq hits 949system.cpu.l2cache.ReadCleanReq_hits::total 1024478 # number of ReadCleanReq hits 950system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827309 # number of ReadSharedReq hits 951system.cpu.l2cache.ReadSharedReq_hits::total 827309 # number of ReadSharedReq hits 952system.cpu.l2cache.demand_hits::cpu.inst 1024478 # number of demand (read+write) hits 953system.cpu.l2cache.demand_hits::cpu.data 1013325 # number of demand (read+write) hits 954system.cpu.l2cache.demand_hits::total 2037803 # number of demand (read+write) hits 955system.cpu.l2cache.overall_hits::cpu.inst 1024478 # number of overall hits 956system.cpu.l2cache.overall_hits::cpu.data 1013325 # number of overall hits 957system.cpu.l2cache.overall_hits::total 2037803 # number of overall hits |
| 963system.cpu.l2cache.UpgradeReq_misses::cpu.data 98 # number of UpgradeReq misses 964system.cpu.l2cache.UpgradeReq_misses::total 98 # number of UpgradeReq misses | 958system.cpu.l2cache.UpgradeReq_misses::cpu.data 98 # number of UpgradeReq misses 959system.cpu.l2cache.UpgradeReq_misses::total 98 # number of UpgradeReq misses |
| 965system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses 966system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses 967system.cpu.l2cache.ReadExReq_misses::cpu.data 115503 # number of ReadExReq misses 968system.cpu.l2cache.ReadExReq_misses::total 115503 # number of ReadExReq misses 969system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15066 # number of ReadCleanReq misses 970system.cpu.l2cache.ReadCleanReq_misses::total 15066 # number of ReadCleanReq misses 971system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273839 # number of ReadSharedReq misses 972system.cpu.l2cache.ReadSharedReq_misses::total 273839 # number of ReadSharedReq misses 973system.cpu.l2cache.demand_misses::cpu.inst 15066 # number of demand (read+write) misses 974system.cpu.l2cache.demand_misses::cpu.data 389342 # number of demand (read+write) misses 975system.cpu.l2cache.demand_misses::total 404408 # number of demand (read+write) misses 976system.cpu.l2cache.overall_misses::cpu.inst 15066 # number of overall misses 977system.cpu.l2cache.overall_misses::cpu.data 389342 # number of overall misses 978system.cpu.l2cache.overall_misses::total 404408 # number of overall misses 979system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 454500 # number of UpgradeReq miss cycles 980system.cpu.l2cache.UpgradeReq_miss_latency::total 454500 # number of UpgradeReq miss cycles 981system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 61000 # number of SCUpgradeReq miss cycles 982system.cpu.l2cache.SCUpgradeReq_miss_latency::total 61000 # number of SCUpgradeReq miss cycles 983system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10302938500 # number of ReadExReq miss cycles 984system.cpu.l2cache.ReadExReq_miss_latency::total 10302938500 # number of ReadExReq miss cycles 985system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1259119000 # number of ReadCleanReq miss cycles 986system.cpu.l2cache.ReadCleanReq_miss_latency::total 1259119000 # number of ReadCleanReq miss cycles 987system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19992285500 # number of ReadSharedReq miss cycles 988system.cpu.l2cache.ReadSharedReq_miss_latency::total 19992285500 # number of ReadSharedReq miss cycles 989system.cpu.l2cache.demand_miss_latency::cpu.inst 1259119000 # number of demand (read+write) miss cycles 990system.cpu.l2cache.demand_miss_latency::cpu.data 30295224000 # number of demand (read+write) miss cycles 991system.cpu.l2cache.demand_miss_latency::total 31554343000 # number of demand (read+write) miss cycles 992system.cpu.l2cache.overall_miss_latency::cpu.inst 1259119000 # number of overall miss cycles 993system.cpu.l2cache.overall_miss_latency::cpu.data 30295224000 # number of overall miss cycles 994system.cpu.l2cache.overall_miss_latency::total 31554343000 # number of overall miss cycles 995system.cpu.l2cache.Writeback_accesses::writebacks 841625 # number of Writeback accesses(hits+misses) 996system.cpu.l2cache.Writeback_accesses::total 841625 # number of Writeback accesses(hits+misses) 997system.cpu.l2cache.UpgradeReq_accesses::cpu.data 127 # number of UpgradeReq accesses(hits+misses) 998system.cpu.l2cache.UpgradeReq_accesses::total 127 # number of UpgradeReq accesses(hits+misses) 999system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) 1000system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) 1001system.cpu.l2cache.ReadExReq_accesses::cpu.data 301485 # number of ReadExReq accesses(hits+misses) 1002system.cpu.l2cache.ReadExReq_accesses::total 301485 # number of ReadExReq accesses(hits+misses) 1003system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1039114 # number of ReadCleanReq accesses(hits+misses) 1004system.cpu.l2cache.ReadCleanReq_accesses::total 1039114 # number of ReadCleanReq accesses(hits+misses) 1005system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1101539 # number of ReadSharedReq accesses(hits+misses) 1006system.cpu.l2cache.ReadSharedReq_accesses::total 1101539 # number of ReadSharedReq accesses(hits+misses) 1007system.cpu.l2cache.demand_accesses::cpu.inst 1039114 # number of demand (read+write) accesses 1008system.cpu.l2cache.demand_accesses::cpu.data 1403024 # number of demand (read+write) accesses 1009system.cpu.l2cache.demand_accesses::total 2442138 # number of demand (read+write) accesses 1010system.cpu.l2cache.overall_accesses::cpu.inst 1039114 # number of overall (read+write) accesses 1011system.cpu.l2cache.overall_accesses::cpu.data 1403024 # number of overall (read+write) accesses 1012system.cpu.l2cache.overall_accesses::total 2442138 # number of overall (read+write) accesses 1013system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.771654 # miss rate for UpgradeReq accesses 1014system.cpu.l2cache.UpgradeReq_miss_rate::total 0.771654 # miss rate for UpgradeReq accesses 1015system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses 1016system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses 1017system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383114 # miss rate for ReadExReq accesses 1018system.cpu.l2cache.ReadExReq_miss_rate::total 0.383114 # miss rate for ReadExReq accesses 1019system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014499 # miss rate for ReadCleanReq accesses 1020system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014499 # miss rate for ReadCleanReq accesses 1021system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248597 # miss rate for ReadSharedReq accesses 1022system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248597 # miss rate for ReadSharedReq accesses 1023system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014499 # miss rate for demand accesses 1024system.cpu.l2cache.demand_miss_rate::cpu.data 0.277502 # miss rate for demand accesses 1025system.cpu.l2cache.demand_miss_rate::total 0.165596 # miss rate for demand accesses 1026system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014499 # miss rate for overall accesses 1027system.cpu.l2cache.overall_miss_rate::cpu.data 0.277502 # miss rate for overall accesses 1028system.cpu.l2cache.overall_miss_rate::total 0.165596 # miss rate for overall accesses 1029system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4637.755102 # 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number of SCUpgradeReq miss cycles 978system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16132911000 # number of ReadExReq miss cycles 979system.cpu.l2cache.ReadExReq_miss_latency::total 16132911000 # number of ReadExReq miss cycles 980system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2019085000 # number of ReadCleanReq miss cycles 981system.cpu.l2cache.ReadCleanReq_miss_latency::total 2019085000 # number of ReadCleanReq miss cycles 982system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34002540500 # number of ReadSharedReq miss cycles 983system.cpu.l2cache.ReadSharedReq_miss_latency::total 34002540500 # number of ReadSharedReq miss cycles 984system.cpu.l2cache.demand_miss_latency::cpu.inst 2019085000 # number of demand (read+write) miss cycles 985system.cpu.l2cache.demand_miss_latency::cpu.data 50135451500 # number of demand (read+write) miss cycles 986system.cpu.l2cache.demand_miss_latency::total 52154536500 # number of demand (read+write) miss cycles 987system.cpu.l2cache.overall_miss_latency::cpu.inst 2019085000 # number of overall miss cycles 988system.cpu.l2cache.overall_miss_latency::cpu.data 50135451500 # number of overall miss cycles 989system.cpu.l2cache.overall_miss_latency::total 52154536500 # number of overall miss cycles 990system.cpu.l2cache.Writeback_accesses::writebacks 841276 # number of Writeback accesses(hits+misses) 991system.cpu.l2cache.Writeback_accesses::total 841276 # number of Writeback accesses(hits+misses) 992system.cpu.l2cache.UpgradeReq_accesses::cpu.data 128 # number of UpgradeReq accesses(hits+misses) 993system.cpu.l2cache.UpgradeReq_accesses::total 128 # number of UpgradeReq accesses(hits+misses) 994system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 26 # number of SCUpgradeReq accesses(hits+misses) 995system.cpu.l2cache.SCUpgradeReq_accesses::total 26 # number of SCUpgradeReq accesses(hits+misses) 996system.cpu.l2cache.ReadExReq_accesses::cpu.data 301527 # number of ReadExReq accesses(hits+misses) 997system.cpu.l2cache.ReadExReq_accesses::total 301527 # number of ReadExReq accesses(hits+misses) 998system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1039513 # number of ReadCleanReq accesses(hits+misses) 999system.cpu.l2cache.ReadCleanReq_accesses::total 1039513 # number of ReadCleanReq accesses(hits+misses) 1000system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1101164 # number of ReadSharedReq accesses(hits+misses) 1001system.cpu.l2cache.ReadSharedReq_accesses::total 1101164 # number of ReadSharedReq accesses(hits+misses) 1002system.cpu.l2cache.demand_accesses::cpu.inst 1039513 # number of demand (read+write) accesses 1003system.cpu.l2cache.demand_accesses::cpu.data 1402691 # number of demand (read+write) accesses 1004system.cpu.l2cache.demand_accesses::total 2442204 # number of demand (read+write) accesses 1005system.cpu.l2cache.overall_accesses::cpu.inst 1039513 # number of overall (read+write) accesses 1006system.cpu.l2cache.overall_accesses::cpu.data 1402691 # number of overall (read+write) accesses 1007system.cpu.l2cache.overall_accesses::total 2442204 # number of overall (read+write) accesses 1008system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.765625 # miss rate for UpgradeReq accesses 1009system.cpu.l2cache.UpgradeReq_miss_rate::total 0.765625 # miss rate for UpgradeReq accesses 1010system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.269231 # miss rate for SCUpgradeReq accesses 1011system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.269231 # miss rate for SCUpgradeReq accesses 1012system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383087 # miss rate for ReadExReq accesses 1013system.cpu.l2cache.ReadExReq_miss_rate::total 0.383087 # miss rate for ReadExReq accesses 1014system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014464 # miss rate for ReadCleanReq accesses 1015system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014464 # miss rate for ReadCleanReq accesses 1016system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248696 # miss rate for ReadSharedReq accesses 1017system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248696 # miss rate for ReadSharedReq accesses 1018system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014464 # miss rate for demand accesses 1019system.cpu.l2cache.demand_miss_rate::cpu.data 0.277585 # miss rate for demand accesses 1020system.cpu.l2cache.demand_miss_rate::total 0.165589 # miss rate for demand accesses 1021system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014464 # miss rate for overall accesses 1022system.cpu.l2cache.overall_miss_rate::cpu.data 0.277585 # miss rate for overall accesses 1023system.cpu.l2cache.overall_miss_rate::total 0.165589 # miss rate for overall accesses 1024system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8204.081633 # average UpgradeReq miss latency 1025system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8204.081633 # average UpgradeReq miss latency 1026system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 34785.714286 # average SCUpgradeReq miss latency 1027system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 34785.714286 # average SCUpgradeReq miss latency 1028system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139665.581633 # average ReadExReq miss latency 1029system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139665.581633 # average ReadExReq miss latency 1030system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134292.317925 # average ReadCleanReq miss latency 1031system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134292.317925 # average ReadCleanReq miss latency 1032system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124162.569608 # average ReadSharedReq miss latency 1033system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124162.569608 # average ReadSharedReq miss latency 1034system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134292.317925 # average overall miss latency 1035system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128761.760143 # average overall miss latency 1036system.cpu.l2cache.demand_avg_miss_latency::total 128967.377677 # average overall miss latency 1037system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134292.317925 # average overall miss latency 1038system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128761.760143 # average overall miss latency 1039system.cpu.l2cache.overall_avg_miss_latency::total 128967.377677 # average overall miss latency |
| 1045system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1046system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1047system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1048system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1049system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1050system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1051system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1052system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1040system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1041system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1043system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1045system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1046system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1047system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1053system.cpu.l2cache.writebacks::writebacks 76042 # number of writebacks 1054system.cpu.l2cache.writebacks::total 76042 # number of writebacks | 1048system.cpu.l2cache.writebacks::writebacks 76045 # number of writebacks 1049system.cpu.l2cache.writebacks::total 76045 # number of writebacks |
| 1055system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1056system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1057system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1058system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1059system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1060system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 1050system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1051system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1052system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1053system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1054system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1055system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 1061system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 305 # number of CleanEvict MSHR misses 1062system.cpu.l2cache.CleanEvict_mshr_misses::total 305 # number of CleanEvict MSHR misses | 1056system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 304 # number of CleanEvict MSHR misses 1057system.cpu.l2cache.CleanEvict_mshr_misses::total 304 # number of CleanEvict MSHR misses |
| 1063system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 98 # number of UpgradeReq MSHR misses 1064system.cpu.l2cache.UpgradeReq_mshr_misses::total 98 # number of UpgradeReq MSHR misses | 1058system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 98 # number of UpgradeReq MSHR misses 1059system.cpu.l2cache.UpgradeReq_mshr_misses::total 98 # number of UpgradeReq MSHR misses |
| 1065system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses 1066system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses 1067system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115503 # number of ReadExReq MSHR misses 1068system.cpu.l2cache.ReadExReq_mshr_misses::total 115503 # number of ReadExReq MSHR misses 1069system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15065 # number of ReadCleanReq MSHR misses 1070system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15065 # number of ReadCleanReq MSHR misses 1071system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273839 # number of ReadSharedReq MSHR misses 1072system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273839 # number of ReadSharedReq MSHR misses 1073system.cpu.l2cache.demand_mshr_misses::cpu.inst 15065 # number of demand (read+write) MSHR misses 1074system.cpu.l2cache.demand_mshr_misses::cpu.data 389342 # number of demand (read+write) MSHR misses 1075system.cpu.l2cache.demand_mshr_misses::total 404407 # number of demand (read+write) MSHR misses 1076system.cpu.l2cache.overall_mshr_misses::cpu.inst 15065 # number of overall MSHR misses 1077system.cpu.l2cache.overall_mshr_misses::cpu.data 389342 # number of overall MSHR misses 1078system.cpu.l2cache.overall_mshr_misses::total 404407 # number of overall MSHR misses | 1060system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 7 # number of SCUpgradeReq MSHR misses 1061system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses 1062system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115511 # number of ReadExReq MSHR misses 1063system.cpu.l2cache.ReadExReq_mshr_misses::total 115511 # number of ReadExReq MSHR misses 1064system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15034 # number of ReadCleanReq MSHR misses 1065system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15034 # number of ReadCleanReq MSHR misses 1066system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273855 # number of ReadSharedReq MSHR misses 1067system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273855 # number of ReadSharedReq MSHR misses 1068system.cpu.l2cache.demand_mshr_misses::cpu.inst 15034 # number of demand (read+write) MSHR misses 1069system.cpu.l2cache.demand_mshr_misses::cpu.data 389366 # number of demand (read+write) MSHR misses 1070system.cpu.l2cache.demand_mshr_misses::total 404400 # number of demand (read+write) MSHR misses 1071system.cpu.l2cache.overall_mshr_misses::cpu.inst 15034 # number of overall MSHR misses 1072system.cpu.l2cache.overall_mshr_misses::cpu.data 389366 # number of overall MSHR misses 1073system.cpu.l2cache.overall_mshr_misses::total 404400 # number of overall MSHR misses |
| 1079system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 1080system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 1074system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 1075system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 1081system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable 1082system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable 1083system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses 1084system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses 1085system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2195000 # number of UpgradeReq MSHR miss cycles 1086system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2195000 # number of UpgradeReq MSHR miss cycles 1087system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 124000 # number of SCUpgradeReq MSHR miss cycles 1088system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 124000 # number of SCUpgradeReq MSHR miss cycles 1089system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9147908500 # number of ReadExReq MSHR miss cycles 1090system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9147908500 # number of ReadExReq MSHR miss cycles 1091system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1108373500 # number of ReadCleanReq MSHR miss cycles 1092system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1108373500 # number of ReadCleanReq MSHR miss cycles 1093system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17263967500 # number of ReadSharedReq MSHR miss cycles 1094system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17263967500 # number of ReadSharedReq MSHR miss cycles 1095system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1108373500 # number of demand (read+write) MSHR miss cycles 1096system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26411876000 # number of demand (read+write) MSHR miss cycles 1097system.cpu.l2cache.demand_mshr_miss_latency::total 27520249500 # number of demand (read+write) MSHR miss cycles 1098system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1108373500 # number of overall MSHR miss cycles 1099system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26411876000 # number of overall MSHR miss cycles 1100system.cpu.l2cache.overall_mshr_miss_latency::total 27520249500 # number of overall MSHR miss cycles 1101system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364133000 # number of ReadReq MSHR uncacheable cycles 1102system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364133000 # number of ReadReq MSHR uncacheable cycles 1103system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925339500 # number of WriteReq MSHR uncacheable cycles 1104system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925339500 # number of WriteReq MSHR uncacheable cycles 1105system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289472500 # number of overall MSHR uncacheable cycles 1106system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289472500 # number of overall MSHR uncacheable cycles | 1076system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable 1077system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable 1078system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses 1079system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses 1080system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 7022000 # number of UpgradeReq MSHR miss cycles 1081system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 7022000 # number of UpgradeReq MSHR miss cycles 1082system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 499500 # number of SCUpgradeReq MSHR miss cycles 1083system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 499500 # number of SCUpgradeReq MSHR miss cycles 1084system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14977801000 # number of ReadExReq MSHR miss cycles 1085system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14977801000 # number of ReadExReq MSHR miss cycles 1086system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1868614000 # number of ReadCleanReq MSHR miss cycles 1087system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1868614000 # number of ReadCleanReq MSHR miss cycles 1088system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31274184500 # number of ReadSharedReq MSHR miss cycles 1089system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31274184500 # number of ReadSharedReq MSHR miss cycles 1090system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1868614000 # number of demand (read+write) MSHR miss cycles 1091system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46251985500 # number of demand (read+write) MSHR miss cycles 1092system.cpu.l2cache.demand_mshr_miss_latency::total 48120599500 # number of demand (read+write) MSHR miss cycles 1093system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1868614000 # number of overall MSHR miss cycles 1094system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46251985500 # number of overall MSHR miss cycles 1095system.cpu.l2cache.overall_mshr_miss_latency::total 48120599500 # number of overall MSHR miss cycles 1096system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363945000 # number of ReadReq MSHR uncacheable cycles 1097system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363945000 # number of ReadReq MSHR uncacheable cycles 1098system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925742500 # number of WriteReq MSHR uncacheable cycles 1099system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925742500 # number of WriteReq MSHR uncacheable cycles 1100system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289687500 # number of overall MSHR uncacheable cycles 1101system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289687500 # number of overall MSHR uncacheable cycles |
| 1107system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1108system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 1102system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1103system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 1109system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.771654 # mshr miss rate for UpgradeReq accesses 1110system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.771654 # mshr miss rate for UpgradeReq accesses 1111system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses 1112system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses 1113system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383114 # mshr miss rate for ReadExReq accesses 1114system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383114 # mshr miss rate for ReadExReq accesses 1115system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for ReadCleanReq accesses 1116system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014498 # mshr miss rate for ReadCleanReq accesses 1117system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248597 # mshr miss rate for ReadSharedReq accesses 1118system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248597 # mshr miss rate for ReadSharedReq accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for demand accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for demand accesses 1121system.cpu.l2cache.demand_mshr_miss_rate::total 0.165595 # mshr miss rate for demand accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for overall accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for overall accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::total 0.165595 # mshr miss rate for overall accesses 1125system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22397.959184 # average UpgradeReq mshr miss latency 1126system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22397.959184 # average UpgradeReq mshr miss latency 1127system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20666.666667 # average SCUpgradeReq mshr miss latency 1128system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20666.666667 # average SCUpgradeReq mshr miss latency 1129system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79200.613837 # average ReadExReq mshr miss latency 1130system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79200.613837 # average ReadExReq mshr miss latency 1131system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73572.751411 # average ReadCleanReq mshr miss latency 1132system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73572.751411 # average ReadCleanReq mshr miss latency 1133system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63044.224891 # average ReadSharedReq mshr miss latency 1134system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63044.224891 # average ReadSharedReq mshr miss latency 1135system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency 1136system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency 1137system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency 1141system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196844.588745 # average ReadReq mshr uncacheable latency 1142system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196844.588745 # average ReadReq mshr uncacheable latency 1143system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.797832 # average WriteReq mshr uncacheable latency 1144system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.797832 # average WriteReq mshr uncacheable latency 1145system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199048.317802 # average overall mshr uncacheable latency 1146system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199048.317802 # average overall mshr uncacheable latency | 1104system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.765625 # mshr miss rate for UpgradeReq accesses 1105system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.765625 # mshr miss rate for UpgradeReq accesses 1106system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.269231 # mshr miss rate for SCUpgradeReq accesses 1107system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.269231 # mshr miss rate for SCUpgradeReq accesses 1108system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383087 # mshr miss rate for ReadExReq accesses 1109system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383087 # mshr miss rate for ReadExReq accesses 1110system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for ReadCleanReq accesses 1111system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014463 # mshr miss rate for ReadCleanReq accesses 1112system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248696 # mshr miss rate for ReadSharedReq accesses 1113system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248696 # mshr miss rate for ReadSharedReq accesses 1114system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for demand accesses 1115system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for demand accesses 1116system.cpu.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses 1117system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for overall accesses 1118system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for overall accesses 1119system.cpu.l2cache.overall_mshr_miss_rate::total 0.165588 # mshr miss rate for overall accesses 1120system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71653.061224 # average UpgradeReq mshr miss latency 1121system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71653.061224 # average UpgradeReq mshr miss latency 1122system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71357.142857 # average SCUpgradeReq mshr miss latency 1123system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71357.142857 # average SCUpgradeReq mshr miss latency 1124system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129665.581633 # average ReadExReq mshr miss latency 1125system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129665.581633 # average ReadExReq mshr miss latency 1126system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124292.536916 # average ReadCleanReq mshr miss latency 1127system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124292.536916 # average ReadCleanReq mshr miss latency 1128system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114199.793686 # average ReadSharedReq mshr miss latency 1129system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114199.793686 # average ReadSharedReq mshr miss latency 1130system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency 1131system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency 1132system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency 1133system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency 1134system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency 1135system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency 1136system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196817.460317 # average ReadReq mshr uncacheable latency 1137system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196817.460317 # average ReadReq mshr uncacheable latency 1138system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.977079 # average WriteReq mshr uncacheable latency 1139system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.977079 # average WriteReq mshr uncacheable latency 1140system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199037.239835 # average overall mshr uncacheable latency 1141system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199037.239835 # average overall mshr uncacheable latency |
| 1147system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1142system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1143system.cpu.toL2Bus.snoop_filter.tot_requests 4883718 # Total number of requests made to the snoop filter. 1144system.cpu.toL2Bus.snoop_filter.hit_single_requests 2441508 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1145system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1146system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. 1147system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1148system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 1148system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution | 1149system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1149system.cpu.toL2Bus.trans_dist::ReadResp 2147969 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::WriteReq 9596 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::WriteResp 9596 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::Writeback 959201 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::CleanEvict 1860011 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::UpgradeReq 127 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::UpgradeResp 155 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::ReadExReq 301485 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::ReadExResp 301485 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039426 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101712 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::BadAddressError 82 # Transaction distribution | 1150system.cpu.toL2Bus.trans_dist::ReadResp 2147995 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::Writeback 958852 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::CleanEvict 1860290 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::UpgradeReq 128 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::UpgradeResp 154 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::ReadExReq 301527 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::ReadExResp 301527 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039828 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101337 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution |
| 1162system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution | 1163system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 1163system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3116681 # Packet count per connected master and slave (bytes) 1164system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240614 # Packet count per connected master and slave (bytes) 1165system.cpu.toL2Bus.pkt_count::total 7357295 # Packet count per connected master and slave (bytes) 1166system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66503296 # Cumulative packet size per connected master and slave (bytes) 1167system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143706404 # Cumulative packet size per connected master and slave (bytes) 1168system.cpu.toL2Bus.pkt_size::total 210209700 # Cumulative packet size per connected master and slave (bytes) 1169system.cpu.toL2Bus.snoops 422216 # Total snoops (count) 1170system.cpu.toL2Bus.snoop_fanout::samples 5321857 # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::mean 1.079248 # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::stdev 0.270126 # Request fanout histogram | 1164system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3117755 # Packet count per connected master and slave (bytes) 1165system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4239617 # Packet count per connected master and slave (bytes) 1166system.cpu.toL2Bus.pkt_count::total 7357372 # Packet count per connected master and slave (bytes) 1167system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66528832 # Cumulative packet size per connected master and slave (bytes) 1168system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143662708 # Cumulative packet size per connected master and slave (bytes) 1169system.cpu.toL2Bus.pkt_size::total 210191540 # Cumulative packet size per connected master and slave (bytes) 1170system.cpu.toL2Bus.snoops 422209 # Total snoops (count) 1171system.cpu.toL2Bus.snoop_fanout::samples 5321984 # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::stdev 0.032932 # Request fanout histogram |
| 1173system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1174system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1174system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::1 4900109 92.08% 92.08% # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::2 421748 7.92% 100.00% # Request fanout histogram | 1175system.cpu.toL2Bus.snoop_fanout::0 5316206 99.89% 99.89% # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::1 5778 0.11% 100.00% # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| 1177system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1178system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1178system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::total 5321857 # Request fanout histogram 1181system.cpu.toL2Bus.reqLayer0.occupancy 3296477500 # Layer occupancy (ticks) | 1179system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::total 5321984 # Request fanout histogram 1182system.cpu.toL2Bus.reqLayer0.occupancy 3296198000 # Layer occupancy (ticks) |
| 1182system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 1183system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 1183system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) | 1184system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) |
| 1184system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1185system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1185system.cpu.toL2Bus.respLayer0.occupancy 1560615042 # Layer occupancy (ticks) | 1186system.cpu.toL2Bus.respLayer0.occupancy 1561216545 # Layer occupancy (ticks) |
| 1186system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1187system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1187system.cpu.toL2Bus.respLayer1.occupancy 2116394230 # Layer occupancy (ticks) | 1188system.cpu.toL2Bus.respLayer1.occupancy 2115809899 # Layer occupancy (ticks) |
| 1188system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1189system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1190system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1191system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1192system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1193system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1194system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1195system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1196system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1197system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1198system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1199system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1200system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1201system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1202system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 1189system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1190system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1191system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1192system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1193system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1194system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1195system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1196system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1197system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1198system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1199system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1200system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1201system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1202system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1203system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 1203system.iobus.trans_dist::WriteReq 51148 # Transaction distribution 1204system.iobus.trans_dist::WriteResp 51148 # Transaction distribution 1205system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5048 # Packet count per connected master and slave (bytes) | 1204system.iobus.trans_dist::WriteReq 51150 # Transaction distribution 1205system.iobus.trans_dist::WriteResp 51150 # Transaction distribution 1206system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) |
| 1206system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 1207system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1208system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1209system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1210system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 1211system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1212system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1213system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1214system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1215system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1216system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 1207system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 1208system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1209system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1210system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1211system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 1212system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1213system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1214system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1215system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1216system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1217system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 1217system.iobus.pkt_count_system.bridge.master::total 33052 # Packet count per connected master and slave (bytes) | 1218system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) |
| 1218system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1219system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 1219system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1220system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 1220system.iobus.pkt_count::total 116502 # Packet count per connected master and slave (bytes) 1221system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20192 # Cumulative packet size per connected master and slave (bytes) | 1221system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 1222system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) |
| 1222system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 1223system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1224system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1225system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1226system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1227system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1228system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1229system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1230system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1231system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1232system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 1223system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 1224system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1225system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1226system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1227system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1228system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1229system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1230system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1231system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1232system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1233system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 1233system.iobus.pkt_size_system.bridge.master::total 44132 # Cumulative packet size per connected master and slave (bytes) | 1234system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) |
| 1234system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1235system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) | 1235system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1236system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) |
| 1236system.iobus.pkt_size::total 2705740 # Cumulative packet size per connected master and slave (bytes) 1237system.iobus.reqLayer0.occupancy 4659000 # Layer occupancy (ticks) | 1237system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 1238system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) |
| 1238system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1239system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 1240system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1241system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1242system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1243system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1244system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1251system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1252system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1253system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1254system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1255system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1256system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1257system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1258system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1239system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1240system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 1241system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1242system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1243system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1244system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1245system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1246system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1252system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1253system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1254system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1255system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1256system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1257system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1258system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1259system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1259system.iobus.reqLayer29.occupancy 216075504 # Layer occupancy (ticks) | 1260system.iobus.reqLayer29.occupancy 215079498 # Layer occupancy (ticks) |
| 1260system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1261system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1262system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 1261system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1262system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1263system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 1263system.iobus.respLayer0.occupancy 23456000 # Layer occupancy (ticks) | 1264system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) |
| 1264system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1265system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1266system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1267system.iocache.tags.replacements 41685 # number of replacements | 1265system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1266system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1267system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1268system.iocache.tags.replacements 41685 # number of replacements |
| 1268system.iocache.tags.tagsinuse 1.259061 # Cycle average of tags in use | 1269system.iocache.tags.tagsinuse 1.249403 # Cycle average of tags in use |
| 1269system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1270system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1271system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1270system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1271system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1272system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1272system.iocache.tags.warmup_cycle 1711310965000 # Cycle when the warmup percentage was hit. 1273system.iocache.tags.occ_blocks::tsunami.ide 1.259061 # Average occupied blocks per requestor 1274system.iocache.tags.occ_percent::tsunami.ide 0.078691 # Average percentage of cache occupancy 1275system.iocache.tags.occ_percent::total 0.078691 # Average percentage of cache occupancy | 1273system.iocache.tags.warmup_cycle 1725991887000 # Cycle when the warmup percentage was hit. 1274system.iocache.tags.occ_blocks::tsunami.ide 1.249403 # Average occupied blocks per requestor 1275system.iocache.tags.occ_percent::tsunami.ide 0.078088 # Average percentage of cache occupancy 1276system.iocache.tags.occ_percent::total 0.078088 # Average percentage of cache occupancy |
| 1276system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1277system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1278system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1279system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1280system.iocache.tags.data_accesses 375525 # Number of data accesses 1281system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1282system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1283system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1284system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1285system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1286system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1287system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1288system.iocache.overall_misses::total 173 # number of overall misses | 1277system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1278system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1279system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1280system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1281system.iocache.tags.data_accesses 375525 # Number of data accesses 1282system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1283system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1284system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1285system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1286system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1287system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1288system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1289system.iocache.overall_misses::total 173 # number of overall misses |
| 1289system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles 1290system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles 1291system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908771621 # number of WriteLineReq miss cycles 1292system.iocache.WriteLineReq_miss_latency::total 4908771621 # number of WriteLineReq miss cycles 1293system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles 1294system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles 1295system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles 1296system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles | 1290system.iocache.ReadReq_miss_latency::tsunami.ide 21903883 # number of ReadReq miss cycles 1291system.iocache.ReadReq_miss_latency::total 21903883 # number of ReadReq miss cycles 1292system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427983615 # number of WriteLineReq miss cycles 1293system.iocache.WriteLineReq_miss_latency::total 5427983615 # number of WriteLineReq miss cycles 1294system.iocache.demand_miss_latency::tsunami.ide 21903883 # number of demand (read+write) miss cycles 1295system.iocache.demand_miss_latency::total 21903883 # number of demand (read+write) miss cycles 1296system.iocache.overall_miss_latency::tsunami.ide 21903883 # number of overall miss cycles 1297system.iocache.overall_miss_latency::total 21903883 # number of overall miss cycles |
| 1297system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1298system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1299system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1300system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1301system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1302system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1303system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1304system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1305system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1306system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1307system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1308system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1309system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1310system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1311system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1312system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1298system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1299system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1300system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1301system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1302system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1303system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1304system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1305system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1306system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1307system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1308system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1309system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1310system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1311system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1312system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1313system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1313system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency 1314system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency 1315system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118135.628153 # average WriteLineReq miss latency 1316system.iocache.WriteLineReq_avg_miss_latency::total 118135.628153 # average WriteLineReq miss latency 1317system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency 1318system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency 1319system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency 1320system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency 1321system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked | 1314system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126612.040462 # average ReadReq miss latency 1315system.iocache.ReadReq_avg_miss_latency::total 126612.040462 # average ReadReq miss latency 1316system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.103557 # average WriteLineReq miss latency 1317system.iocache.WriteLineReq_avg_miss_latency::total 130631.103557 # average WriteLineReq miss latency 1318system.iocache.demand_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency 1319system.iocache.demand_avg_miss_latency::total 126612.040462 # average overall miss latency 1320system.iocache.overall_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency 1321system.iocache.overall_avg_miss_latency::total 126612.040462 # average overall miss latency 1322system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1322system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1323system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1323system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked | 1324system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1324system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1325system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1325system.iocache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked | 1326system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1326system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1327system.iocache.fast_writes 0 # number of fast writes performed 1328system.iocache.cache_copies 0 # number of cache copies performed 1329system.iocache.writebacks::writebacks 41512 # number of writebacks 1330system.iocache.writebacks::total 41512 # number of writebacks 1331system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1332system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1333system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1334system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1335system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1336system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1337system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1338system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses | 1327system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1328system.iocache.fast_writes 0 # number of fast writes performed 1329system.iocache.cache_copies 0 # number of cache copies performed 1330system.iocache.writebacks::writebacks 41512 # number of writebacks 1331system.iocache.writebacks::total 41512 # number of writebacks 1332system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1333system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1334system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1335system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1336system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1337system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1338system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1339system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses |
| 1339system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles 1340system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles 1341system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831171621 # number of WriteLineReq MSHR miss cycles 1342system.iocache.WriteLineReq_mshr_miss_latency::total 2831171621 # number of WriteLineReq MSHR miss cycles 1343system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles 1344system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles 1345system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles 1346system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles | 1340system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13253883 # number of ReadReq MSHR miss cycles 1341system.iocache.ReadReq_mshr_miss_latency::total 13253883 # number of ReadReq MSHR miss cycles 1342system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350383615 # number of WriteLineReq MSHR miss cycles 1343system.iocache.WriteLineReq_mshr_miss_latency::total 3350383615 # number of WriteLineReq MSHR miss cycles 1344system.iocache.demand_mshr_miss_latency::tsunami.ide 13253883 # number of demand (read+write) MSHR miss cycles 1345system.iocache.demand_mshr_miss_latency::total 13253883 # number of demand (read+write) MSHR miss cycles 1346system.iocache.overall_mshr_miss_latency::tsunami.ide 13253883 # number of overall MSHR miss cycles 1347system.iocache.overall_mshr_miss_latency::total 13253883 # number of overall MSHR miss cycles |
| 1347system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1348system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1349system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1350system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1351system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1352system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1353system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1354system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1348system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1349system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1350system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1351system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1352system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1353system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1354system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1355system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1355system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency 1356system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency 1357system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68135.628153 # average WriteLineReq mshr miss latency 1358system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68135.628153 # average WriteLineReq mshr miss latency 1359system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency 1360system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency 1361system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency 1362system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency | 1356system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average ReadReq mshr miss latency 1357system.iocache.ReadReq_avg_mshr_miss_latency::total 76612.040462 # average ReadReq mshr miss latency 1358system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.103557 # average WriteLineReq mshr miss latency 1359system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.103557 # average WriteLineReq mshr miss latency 1360system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency 1361system.iocache.demand_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency 1362system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency 1363system.iocache.overall_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency |
| 1363system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1364system.membus.trans_dist::ReadReq 6930 # Transaction distribution | 1364system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1365system.membus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1365system.membus.trans_dist::ReadResp 295925 # Transaction distribution 1366system.membus.trans_dist::WriteReq 9596 # Transaction distribution 1367system.membus.trans_dist::WriteResp 9596 # Transaction distribution 1368system.membus.trans_dist::Writeback 117554 # Transaction distribution 1369system.membus.trans_dist::CleanEvict 261799 # Transaction distribution 1370system.membus.trans_dist::UpgradeReq 335 # Transaction distribution 1371system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution | 1366system.membus.trans_dist::ReadResp 295909 # Transaction distribution 1367system.membus.trans_dist::WriteReq 9598 # Transaction distribution 1368system.membus.trans_dist::WriteResp 9598 # Transaction distribution 1369system.membus.trans_dist::Writeback 117557 # Transaction distribution 1370system.membus.trans_dist::CleanEvict 261789 # Transaction distribution 1371system.membus.trans_dist::UpgradeReq 334 # Transaction distribution 1372system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution |
| 1372system.membus.trans_dist::UpgradeResp 341 # Transaction distribution | 1373system.membus.trans_dist::UpgradeResp 341 # Transaction distribution |
| 1373system.membus.trans_dist::ReadExReq 115266 # Transaction distribution 1374system.membus.trans_dist::ReadExResp 115266 # Transaction distribution 1375system.membus.trans_dist::ReadSharedReq 289077 # Transaction distribution 1376system.membus.trans_dist::BadAddressError 82 # Transaction distribution | 1374system.membus.trans_dist::ReadExReq 115275 # Transaction distribution 1375system.membus.trans_dist::ReadExResp 115275 # Transaction distribution 1376system.membus.trans_dist::ReadSharedReq 289062 # Transaction distribution 1377system.membus.trans_dist::BadAddressError 83 # Transaction distribution |
| 1377system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1378system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution | 1378system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1379system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution |
| 1379system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33052 # Packet count per connected master and slave (bytes) 1380system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146409 # Packet count per connected master and slave (bytes) 1381system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 164 # Packet count per connected master and slave (bytes) 1382system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179625 # Packet count per connected master and slave (bytes) | 1380system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 1381system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146388 # Packet count per connected master and slave (bytes) 1382system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) 1383system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179610 # Packet count per connected master and slave (bytes) |
| 1383system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 1384system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) | 1384system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 1385system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) |
| 1385system.membus.pkt_count::total 1304442 # Packet count per connected master and slave (bytes) 1386system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44132 # Cumulative packet size per connected master and slave (bytes) 1387system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710784 # Cumulative packet size per connected master and slave (bytes) 1388system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754916 # Cumulative packet size per connected master and slave (bytes) | 1386system.membus.pkt_count::total 1304427 # Packet count per connected master and slave (bytes) 1387system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 1388system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710528 # Cumulative packet size per connected master and slave (bytes) 1389system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754676 # Cumulative packet size per connected master and slave (bytes) |
| 1389system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1390system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) | 1390system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1391system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) |
| 1391system.membus.pkt_size::total 33412644 # Cumulative packet size per connected master and slave (bytes) | 1392system.membus.pkt_size::total 33412404 # Cumulative packet size per connected master and slave (bytes) |
| 1392system.membus.snoops 435 # Total snoops (count) | 1393system.membus.snoops 435 # Total snoops (count) |
| 1393system.membus.snoop_fanout::samples 842297 # Request fanout histogram | 1394system.membus.snoop_fanout::samples 842283 # Request fanout histogram |
| 1394system.membus.snoop_fanout::mean 1 # Request fanout histogram 1395system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1396system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1397system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1395system.membus.snoop_fanout::mean 1 # Request fanout histogram 1396system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1397system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1398system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1398system.membus.snoop_fanout::1 842297 100.00% 100.00% # Request fanout histogram | 1399system.membus.snoop_fanout::1 842283 100.00% 100.00% # Request fanout histogram |
| 1399system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1400system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1401system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1402system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1400system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1401system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1402system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1403system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1403system.membus.snoop_fanout::total 842297 # Request fanout histogram 1404system.membus.reqLayer0.occupancy 28891000 # Layer occupancy (ticks) | 1404system.membus.snoop_fanout::total 842283 # Request fanout histogram 1405system.membus.reqLayer0.occupancy 28662500 # Layer occupancy (ticks) |
| 1405system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1406system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1406system.membus.reqLayer1.occupancy 1313747676 # Layer occupancy (ticks) | 1407system.membus.reqLayer1.occupancy 1313672631 # Layer occupancy (ticks) |
| 1407system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1408system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1408system.membus.reqLayer2.occupancy 109000 # Layer occupancy (ticks) | 1409system.membus.reqLayer2.occupancy 106500 # Layer occupancy (ticks) |
| 1409system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1410system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1410system.membus.respLayer1.occupancy 2139659662 # Layer occupancy (ticks) | 1411system.membus.respLayer1.occupancy 2139416664 # Layer occupancy (ticks) |
| 1411system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | 1412system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1412system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks) | 1413system.membus.respLayer2.occupancy 69895667 # Layer occupancy (ticks) |
| 1413system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1414system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1415system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1416system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1417system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1418system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1419system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1420system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 17 unchanged lines hidden (view full) --- 1438system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1439system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1440system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1441system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1442system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1443system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1444system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1445system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1414system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1415system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1416system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1417system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1418system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1419system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1420system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1421system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 17 unchanged lines hidden (view full) --- 1439system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1440system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1441system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1442system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1443system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1444system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1445system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1446system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1446system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed 1447system.cpu.kern.inst.hwrei 210955 # number of hwrei instructions executed 1448system.cpu.kern.ipl_count::0 74645 40.97% 40.97% # number of times we switched to this ipl | 1447system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed 1448system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed 1449system.cpu.kern.ipl_count::0 74668 40.97% 40.97% # number of times we switched to this ipl |
| 1449system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl | 1450system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl |
| 1450system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl 1451system.cpu.kern.ipl_count::31 105533 57.93% 100.00% # number of times we switched to this ipl 1452system.cpu.kern.ipl_count::total 182187 # number of times we switched to this ipl 1453system.cpu.kern.ipl_good::0 73278 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 1451system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1452system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl 1453system.cpu.kern.ipl_count::total 182251 # number of times we switched to this ipl 1454system.cpu.kern.ipl_good::0 73301 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 1454system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl | 1455system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl |
| 1455system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl 1456system.cpu.kern.ipl_good::31 73278 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1457system.cpu.kern.ipl_good::total 148565 # number of times we switched to this ipl from a different ipl 1458system.cpu.kern.ipl_ticks::0 1817526707500 97.66% 97.66% # number of cycles we spent at this ipl 1459system.cpu.kern.ipl_ticks::21 62603000 0.00% 97.67% # number of cycles we spent at this ipl 1460system.cpu.kern.ipl_ticks::22 536431500 0.03% 97.70% # number of cycles we spent at this ipl 1461system.cpu.kern.ipl_ticks::31 42863705000 2.30% 100.00% # number of cycles we spent at this ipl 1462system.cpu.kern.ipl_ticks::total 1860989447000 # number of cycles we spent at this ipl 1463system.cpu.kern.ipl_used::0 0.981687 # fraction of swpipl calls that actually changed the ipl | 1456system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1457system.cpu.kern.ipl_good::31 73301 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1458system.cpu.kern.ipl_good::total 148613 # number of times we switched to this ipl from a different ipl 1459system.cpu.kern.ipl_ticks::0 1818203066500 96.93% 96.93% # number of cycles we spent at this ipl 1460system.cpu.kern.ipl_ticks::21 62700500 0.00% 96.94% # number of cycles we spent at this ipl 1461system.cpu.kern.ipl_ticks::22 538036000 0.03% 96.96% # number of cycles we spent at this ipl 1462system.cpu.kern.ipl_ticks::31 56940563000 3.04% 100.00% # number of cycles we spent at this ipl 1463system.cpu.kern.ipl_ticks::total 1875744366000 # number of cycles we spent at this ipl 1464system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl |
| 1464system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1465system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 1465system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1466system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 1466system.cpu.kern.ipl_used::31 0.694361 # fraction of swpipl calls that actually changed the ipl 1467system.cpu.kern.ipl_used::total 0.815453 # fraction of swpipl calls that actually changed the ipl | 1467system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl 1468system.cpu.kern.ipl_used::total 0.815430 # fraction of swpipl calls that actually changed the ipl |
| 1468system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1469system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1470system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1471system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1472system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1473system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1474system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1475system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 1498system.cpu.kern.syscall::total 326 # number of syscalls executed 1499system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1500system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1501system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1502system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1503system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1504system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1505system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed | 1469system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1470system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1471system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1472system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1473system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1474system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1475system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1476system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 1499system.cpu.kern.syscall::total 326 # number of syscalls executed 1500system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1501system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1502system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1503system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1504system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1505system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1506system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed |
| 1506system.cpu.kern.callpal::swpipl 175074 91.22% 93.43% # number of callpals executed 1507system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed | 1507system.cpu.kern.callpal::swpipl 175134 91.23% 93.43% # number of callpals executed 1508system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed |
| 1508system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1509system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1510system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1511system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed | 1509system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1510system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1511system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1512system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed |
| 1512system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed | 1513system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed |
| 1513system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1514system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 1514system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1515system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 1515system.cpu.kern.callpal::total 191916 # number of callpals executed 1516system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches | 1516system.cpu.kern.callpal::total 191979 # number of callpals executed 1517system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches |
| 1517system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 1518system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 1519system.cpu.kern.mode_good::kernel 1909 1520system.cpu.kern.mode_good::user 1739 1521system.cpu.kern.mode_good::idle 170 | 1518system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 1519system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 1520system.cpu.kern.mode_good::kernel 1909 1521system.cpu.kern.mode_good::user 1739 1522system.cpu.kern.mode_good::idle 170 |
| 1522system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches | 1523system.cpu.kern.mode_switch_good::kernel 0.326325 # fraction of useful protection mode switches |
| 1523system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1524system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches | 1524system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1525system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches |
| 1525system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches 1526system.cpu.kern.mode_ticks::kernel 29189899500 1.57% 1.57% # number of ticks spent at the given mode 1527system.cpu.kern.mode_ticks::user 2667621500 0.14% 1.71% # number of ticks spent at the given mode 1528system.cpu.kern.mode_ticks::idle 1829131918000 98.29% 100.00% # number of ticks spent at the given mode | 1526system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches 1527system.cpu.kern.mode_ticks::kernel 29901576500 1.59% 1.59% # number of ticks spent at the given mode 1528system.cpu.kern.mode_ticks::user 2896080000 0.15% 1.75% # number of ticks spent at the given mode 1529system.cpu.kern.mode_ticks::idle 1842946701500 98.25% 100.00% # number of ticks spent at the given mode |
| 1529system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1530 1531---------- End Simulation Statistics ---------- | 1530system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1531 1532---------- End Simulation Statistics ---------- |