| stats.txt (10798:74e3c7359393) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.861006 # Number of seconds simulated 4sim_ticks 1861005569500 # Number of ticks simulated 5final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.861006 # Number of seconds simulated 4sim_ticks 1861005569500 # Number of ticks simulated 5final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 145313 # Simulator instruction rate (inst/s) 8host_op_rate 145313 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5108711594 # Simulator tick rate (ticks/s) 10host_mem_usage 309496 # Number of bytes of host memory used 11host_seconds 364.28 # Real time elapsed on the host | 7host_inst_rate 152837 # Simulator instruction rate (inst/s) 8host_op_rate 152837 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5373256396 # Simulator tick rate (ticks/s) 10host_mem_usage 376300 # Number of bytes of host memory used 11host_seconds 346.35 # Real time elapsed on the host |
| 12sim_insts 52934565 # Number of instructions simulated 13sim_ops 52934565 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory --- 26 unchanged lines hidden (view full) --- 46system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue 49system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one | 12sim_insts 52934565 # Number of instructions simulated 13sim_ops 52934565 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory --- 26 unchanged lines hidden (view full) --- 46system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue 49system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one |
| 54system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write | 54system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write |
| 55system.physmem.perBankRdBursts::0 25748 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25559 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25508 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25346 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25393 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24806 # Per bank write bursts 61system.physmem.perBankRdBursts::6 25027 # Per bank write bursts 62system.physmem.perBankRdBursts::7 25127 # Per bank write bursts --- 193 unchanged lines hidden (view full) --- 256system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads | 55system.physmem.perBankRdBursts::0 25748 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25559 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25508 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25346 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25393 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24806 # Per bank write bursts 61system.physmem.perBankRdBursts::6 25027 # Per bank write bursts 62system.physmem.perBankRdBursts::7 25127 # Per bank write bursts --- 193 unchanged lines hidden (view full) --- 256system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads |
| 264system.physmem.totQLat 3741903500 # Total ticks spent queuing 265system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM | 264system.physmem.totQLat 3741904500 # Total ticks spent queuing 265system.physmem.totMemAccLat 11312067000 # Total ticks spent from burst creation until serviced by the DRAM |
| 266system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers 267system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 269system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst 270system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s --- 120 unchanged lines hidden (view full) --- 394system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking 395system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing 396system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch 397system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction 398system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode 399system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode 400system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing 401system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle | 266system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers 267system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 269system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst 270system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s --- 120 unchanged lines hidden (view full) --- 394system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking 395system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing 396system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch 397system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction 398system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode 399system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode 400system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing 401system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle |
| 402system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking | 402system.cpu.rename.BlockCycles 51456440 # Number of cycles rename is blocking |
| 403system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst | 403system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst |
| 404system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running 405system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking | 404system.cpu.rename.RunCycles 10391328 # Number of cycles rename is running 405system.cpu.rename.UnblockCycles 8777492 # Number of cycles rename is unblocking |
| 406system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename 407system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full 408system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full 409system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full | 406system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename 407system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full 408system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full 409system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full |
| 410system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full | 410system.cpu.rename.SQFullEvents 4578470 # Number of times rename has blocked due to SQ full |
| 411system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed 412system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made 413system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups 414system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups 415system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed 416system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing 417system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed 418system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed | 411system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed 412system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made 413system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups 414system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups 415system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed 416system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing 417system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed 418system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed |
| 419system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer | 419system.cpu.rename.skidInsts 13460579 # count of insts added to the skid buffer |
| 420system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. 421system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. 422system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. | 420system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. 421system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. 422system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. |
| 423system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores. | 423system.cpu.memDep0.conflictingStores 1107333 # Number of conflicting stores. |
| 424system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) 425system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ 426system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued 427system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued 428system.cpu.iq.iqSquashedInstsExamined 7824422 # Number of squashed instructions iterated over during squash; mainly for profiling 429system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph 430system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed 431system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 424system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) 425system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ 426system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued 427system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued 428system.cpu.iq.iqSquashedInstsExamined 7824422 # Number of squashed instructions iterated over during squash; mainly for profiling 429system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph 430system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed 431system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 435system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle | 435system.cpu.iq.issued_per_cycle::0 93391037 79.81% 79.81% # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::1 10179390 8.70% 88.51% # Number of insts issued each cycle |
| 437system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle | 437system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle |
| 438system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle | 438system.cpu.iq.issued_per_cycle::3 3008329 2.57% 94.77% # Number of insts issued each cycle |
| 439system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle | 439system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle |
| 440system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle | 440system.cpu.iq.issued_per_cycle::5 1515380 1.30% 98.70% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::6 1001151 0.86% 99.55% # Number of insts issued each cycle |
| 442system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle 448system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 449system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available --- 21 unchanged lines hidden (view full) --- 471system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available 478system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available | 442system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle 448system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 449system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available --- 21 unchanged lines hidden (view full) --- 471system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available 478system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available |
| 479system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available | 479system.cpu.iq.fu_full::MemWrite 367354 32.94% 100.00% # attempts to use FU when none available |
| 480system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 481system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 482system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 483system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued 484system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued 485system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued 486system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued 487system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued --- 22 unchanged lines hidden (view full) --- 510system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued 512system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued 513system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued 514system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued 515system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 516system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued 517system.cpu.iq.rate 0.469435 # Inst issue rate | 480system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 481system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 482system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 483system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued 484system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued 485system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued 486system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued 487system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued --- 22 unchanged lines hidden (view full) --- 510system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued 512system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued 513system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued 514system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued 515system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 516system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued 517system.cpu.iq.rate 0.469435 # Inst issue rate |
| 518system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested | 518system.cpu.iq.fu_busy_cnt 1115223 # FU busy when requested |
| 519system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) | 519system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) |
| 520system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads | 520system.cpu.iq.int_inst_queue_reads 232558248 # Number of integer instruction queue reads |
| 521system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes 522system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses 523system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads 524system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes 525system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses | 521system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes 522system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses 523system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads 524system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes 525system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses |
| 526system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses | 526system.cpu.iq.int_alu_accesses 58264569 # Number of integer alu accesses |
| 527system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses 528system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores 529system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 530system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed 531system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed 532system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations 533system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed 534system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 535system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 536system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled | 527system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses 528system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores 529system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 530system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed 531system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed 532system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations 533system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed 534system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 535system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 536system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled |
| 537system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked | 537system.cpu.iew.lsq.thread0.cacheBlocked 442853 # Number of times an access to memory failed due to the cache being blocked |
| 538system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 539system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing 540system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking | 538system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 539system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing 540system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking |
| 541system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking | 541system.cpu.iew.iewUnblockCycles 1105875 # Number of cycles IEW is unblocking |
| 542system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ 543system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch 544system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions 545system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions 546system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions 547system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall | 542system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ 543system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch 544system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions 545system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions 546system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions 547system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall |
| 548system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall | 548system.cpu.iew.iewLSQFullEvents 856452 # Number of times the LSQ has become full, causing a stall |
| 549system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations 550system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly 551system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly 552system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute 553system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions 554system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed 555system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute 556system.cpu.iew.exec_swp 0 # number of swp insts executed --- 14 unchanged lines hidden (view full) --- 571system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards 572system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted 573system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle | 549system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations 550system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly 551system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly 552system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute 553system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions 554system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed 555system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute 556system.cpu.iew.exec_swp 0 # number of swp insts executed --- 14 unchanged lines hidden (view full) --- 571system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards 572system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted 573system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle |
| 579system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle | 579system.cpu.commit.committed_per_cycle::2 4272055 3.70% 93.39% # Number of insts commited each cycle |
| 580system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle | 580system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle |
| 581system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle | 581system.cpu.commit.committed_per_cycle::4 1764306 1.53% 96.83% # Number of insts commited each cycle |
| 582system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle | 582system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle |
| 583system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle | 583system.cpu.commit.committed_per_cycle::6 473669 0.41% 97.77% # Number of insts commited each cycle |
| 584system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle | 584system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle |
| 585system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle | 585system.cpu.commit.committed_per_cycle::8 2085446 1.80% 100.00% # Number of insts commited each cycle |
| 586system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle 590system.cpu.commit.committedInsts 56123349 # Number of instructions committed 591system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed 592system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 593system.cpu.commit.refs 15459994 # Number of memory references committed --- 33 unchanged lines hidden (view full) --- 627system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 630system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction 631system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction 632system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction 633system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 634system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction | 586system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle 590system.cpu.commit.committedInsts 56123349 # Number of instructions committed 591system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed 592system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 593system.cpu.commit.refs 15459994 # Number of memory references committed --- 33 unchanged lines hidden (view full) --- 627system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 630system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction 631system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction 632system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction 633system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 634system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction |
| 635system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached 636system.cpu.rob.rob_reads 177593269 # The number of ROB reads | 635system.cpu.commit.bw_lim_events 2085446 # number cycles where commit BW limit reached 636system.cpu.rob.rob_reads 177593268 # The number of ROB reads |
| 637system.cpu.rob.rob_writes 130137832 # The number of ROB writes 638system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself 639system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling 640system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 641system.cpu.committedInsts 52934565 # Number of Instructions Simulated 642system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated 643system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction 644system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads --- 42 unchanged lines hidden (view full) --- 687system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses 688system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses 689system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses 690system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses 691system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses 692system.cpu.dcache.overall_misses::total 3751566 # number of overall misses 693system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles 694system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles | 637system.cpu.rob.rob_writes 130137832 # The number of ROB writes 638system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself 639system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling 640system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 641system.cpu.committedInsts 52934565 # Number of Instructions Simulated 642system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated 643system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction 644system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads --- 42 unchanged lines hidden (view full) --- 687system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses 688system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses 689system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses 690system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses 691system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses 692system.cpu.dcache.overall_misses::total 3751566 # number of overall misses 693system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles 694system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles |
| 695system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles 696system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles | 695system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890725520 # number of WriteReq miss cycles 696system.cpu.dcache.WriteReq_miss_latency::total 80890725520 # number of WriteReq miss cycles |
| 697system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles 698system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles 699system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles 700system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles | 697system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles 698system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles 699system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles 700system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles |
| 701system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles 702system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles 703system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles 704system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles | 701system.cpu.dcache.demand_miss_latency::cpu.data 122732079835 # number of demand (read+write) miss cycles 702system.cpu.dcache.demand_miss_latency::total 122732079835 # number of demand (read+write) miss cycles 703system.cpu.dcache.overall_miss_latency::cpu.data 122732079835 # number of overall miss cycles 704system.cpu.dcache.overall_miss_latency::total 122732079835 # number of overall miss cycles |
| 705system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) 706system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) 707system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) 708system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses) 709system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses) 710system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses) 711system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses) 712system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 723system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses 724system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses 725system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses 726system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses 727system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses 728system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses 729system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency 730system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency | 705system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) 706system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) 707system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) 708system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses) 709system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses) 710system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses) 711system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses) 712system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 723system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses 724system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses 725system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses 726system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses 727system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses 728system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses 729system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency 730system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency |
| 731system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency 732system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency | 731system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.547423 # average WriteReq miss latency 732system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.547423 # average WriteReq miss latency |
| 733system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency 734system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency 735system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency 736system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency | 733system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency 734system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency 735system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency 736system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency |
| 737system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency 738system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency 739system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency 740system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency 741system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked | 737system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency 738system.cpu.dcache.demand_avg_miss_latency::total 32714.892883 # average overall miss latency 739system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency 740system.cpu.dcache.overall_avg_miss_latency::total 32714.892883 # average overall miss latency 741system.cpu.dcache.blocked_cycles::no_mshrs 4477894 # number of cycles access was blocked |
| 742system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked 743system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked 744system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked | 742system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked 743system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked 744system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked |
| 745system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked | 745system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.235072 # average number of cycles each access was blocked |
| 746system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked 747system.cpu.dcache.fast_writes 0 # number of fast writes performed 748system.cpu.dcache.cache_copies 0 # number of cache copies performed 749system.cpu.dcache.writebacks::writebacks 842087 # number of writebacks 750system.cpu.dcache.writebacks::total 842087 # number of writebacks 751system.cpu.dcache.ReadReq_mshr_hits::cpu.data 701160 # number of ReadReq MSHR hits 752system.cpu.dcache.ReadReq_mshr_hits::total 701160 # number of ReadReq MSHR hits 753system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664055 # number of WriteReq MSHR hits --- 11 unchanged lines hidden (view full) --- 765system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17997 # number of LoadLockedReq MSHR misses 766system.cpu.dcache.LoadLockedReq_mshr_misses::total 17997 # number of LoadLockedReq MSHR misses 767system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 27 # number of StoreCondReq MSHR misses 768system.cpu.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses 769system.cpu.dcache.demand_mshr_misses::cpu.data 1386351 # number of demand (read+write) MSHR misses 770system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses 771system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses 772system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses | 746system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked 747system.cpu.dcache.fast_writes 0 # number of fast writes performed 748system.cpu.dcache.cache_copies 0 # number of cache copies performed 749system.cpu.dcache.writebacks::writebacks 842087 # number of writebacks 750system.cpu.dcache.writebacks::total 842087 # number of writebacks 751system.cpu.dcache.ReadReq_mshr_hits::cpu.data 701160 # number of ReadReq MSHR hits 752system.cpu.dcache.ReadReq_mshr_hits::total 701160 # number of ReadReq MSHR hits 753system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664055 # number of WriteReq MSHR hits --- 11 unchanged lines hidden (view full) --- 765system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17997 # number of LoadLockedReq MSHR misses 766system.cpu.dcache.LoadLockedReq_mshr_misses::total 17997 # number of LoadLockedReq MSHR misses 767system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 27 # number of StoreCondReq MSHR misses 768system.cpu.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses 769system.cpu.dcache.demand_mshr_misses::cpu.data 1386351 # number of demand (read+write) MSHR misses 770system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses 771system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses 772system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses |
| 773system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 774system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 775system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable 776system.cpu.dcache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable 777system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses 778system.cpu.dcache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses |
|
| 773system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles 774system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles | 779system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles 780system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles |
| 775system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482487876 # number of WriteReq MSHR miss cycles 776system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482487876 # number of WriteReq MSHR miss cycles | 781system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482529124 # number of WriteReq MSHR miss cycles 782system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482529124 # number of WriteReq MSHR miss cycles |
| 777system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles 778system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles 779system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles 780system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles | 783system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles 784system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles 785system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles 786system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles |
| 781system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479420899 # number of demand (read+write) MSHR miss cycles 782system.cpu.dcache.demand_mshr_miss_latency::total 42479420899 # number of demand (read+write) MSHR miss cycles 783system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479420899 # number of overall MSHR miss cycles 784system.cpu.dcache.overall_mshr_miss_latency::total 42479420899 # number of overall MSHR miss cycles | 787system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479462147 # number of demand (read+write) MSHR miss cycles 788system.cpu.dcache.demand_mshr_miss_latency::total 42479462147 # number of demand (read+write) MSHR miss cycles 789system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479462147 # number of overall MSHR miss cycles 790system.cpu.dcache.overall_mshr_miss_latency::total 42479462147 # number of overall MSHR miss cycles |
| 785system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles 786system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles 787system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles 788system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011966000 # number of WriteReq MSHR uncacheable cycles 789system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3445672500 # number of overall MSHR uncacheable cycles 790system.cpu.dcache.overall_mshr_uncacheable_latency::total 3445672500 # number of overall MSHR uncacheable cycles 791system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for ReadReq accesses 792system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120872 # mshr miss rate for ReadReq accesses --- 4 unchanged lines hidden (view full) --- 797system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000125 # mshr miss rate for StoreCondReq accesses 798system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000125 # mshr miss rate for StoreCondReq accesses 799system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for demand accesses 800system.cpu.dcache.demand_mshr_miss_rate::total 0.091160 # mshr miss rate for demand accesses 801system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for overall accesses 802system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses 803system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency 804system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency | 791system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles 792system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles 793system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles 794system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011966000 # number of WriteReq MSHR uncacheable cycles 795system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3445672500 # number of overall MSHR uncacheable cycles 796system.cpu.dcache.overall_mshr_uncacheable_latency::total 3445672500 # number of overall MSHR uncacheable cycles 797system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for ReadReq accesses 798system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120872 # mshr miss rate for ReadReq accesses --- 4 unchanged lines hidden (view full) --- 803system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000125 # mshr miss rate for StoreCondReq accesses 804system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000125 # mshr miss rate for StoreCondReq accesses 805system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for demand accesses 806system.cpu.dcache.demand_mshr_miss_rate::total 0.091160 # mshr miss rate for demand accesses 807system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for overall accesses 808system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses 809system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency 810system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency |
| 805system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.682104 # average WriteReq mshr miss latency 806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.682104 # average WriteReq mshr miss latency | 811system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.823950 # average WriteReq mshr miss latency 812system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.823950 # average WriteReq mshr miss latency |
| 807system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency 808system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency 809system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency 810system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency | 813system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency 814system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency 815system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency 816system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency |
| 811system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency 812system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency 813system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency 814system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency 815system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 816system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 817system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 818system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 819system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 820system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 817system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency 818system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency 819system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency 820system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency 821system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206884.054834 # average ReadReq mshr uncacheable latency 822system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206884.054834 # average ReadReq mshr uncacheable latency 823system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209645.305825 # average WriteReq mshr uncacheable latency 824system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209645.305825 # average WriteReq mshr uncacheable latency 825system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208487.475041 # average overall mshr uncacheable latency 826system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208487.475041 # average overall mshr uncacheable latency |
| 821system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 822system.cpu.icache.tags.replacements 1032757 # number of replacements 823system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use 824system.cpu.icache.tags.total_refs 7965141 # Total number of references to valid blocks. 825system.cpu.icache.tags.sampled_refs 1033265 # Sample count of references to valid blocks. 826system.cpu.icache.tags.avg_refs 7.708711 # Average number of references to valid blocks. 827system.cpu.icache.tags.warmup_cycle 28360334250 # Cycle when the warmup percentage was hit. 828system.cpu.icache.tags.occ_blocks::cpu.inst 509.197301 # Average occupied blocks per requestor --- 107 unchanged lines hidden (view full) --- 936system.cpu.l2cache.ReadReq_hits::cpu.data 828726 # number of ReadReq hits 937system.cpu.l2cache.ReadReq_hits::total 1846951 # number of ReadReq hits 938system.cpu.l2cache.Writeback_hits::writebacks 842087 # number of Writeback hits 939system.cpu.l2cache.Writeback_hits::total 842087 # number of Writeback hits 940system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 941system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits 942system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 943system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits | 827system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 828system.cpu.icache.tags.replacements 1032757 # number of replacements 829system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use 830system.cpu.icache.tags.total_refs 7965141 # Total number of references to valid blocks. 831system.cpu.icache.tags.sampled_refs 1033265 # Sample count of references to valid blocks. 832system.cpu.icache.tags.avg_refs 7.708711 # Average number of references to valid blocks. 833system.cpu.icache.tags.warmup_cycle 28360334250 # Cycle when the warmup percentage was hit. 834system.cpu.icache.tags.occ_blocks::cpu.inst 509.197301 # Average occupied blocks per requestor --- 107 unchanged lines hidden (view full) --- 942system.cpu.l2cache.ReadReq_hits::cpu.data 828726 # number of ReadReq hits 943system.cpu.l2cache.ReadReq_hits::total 1846951 # number of ReadReq hits 944system.cpu.l2cache.Writeback_hits::writebacks 842087 # number of Writeback hits 945system.cpu.l2cache.Writeback_hits::total 842087 # number of Writeback hits 946system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 947system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits 948system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 949system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits |
| 944system.cpu.l2cache.ReadExReq_hits::cpu.data 186339 # number of ReadExReq hits 945system.cpu.l2cache.ReadExReq_hits::total 186339 # number of ReadExReq hits | 950system.cpu.l2cache.ReadExReq_hits::cpu.data 186337 # number of ReadExReq hits 951system.cpu.l2cache.ReadExReq_hits::total 186337 # number of ReadExReq hits |
| 946system.cpu.l2cache.demand_hits::cpu.inst 1018225 # number of demand (read+write) hits | 952system.cpu.l2cache.demand_hits::cpu.inst 1018225 # number of demand (read+write) hits |
| 947system.cpu.l2cache.demand_hits::cpu.data 1015065 # number of demand (read+write) hits 948system.cpu.l2cache.demand_hits::total 2033290 # number of demand (read+write) hits | 953system.cpu.l2cache.demand_hits::cpu.data 1015063 # number of demand (read+write) hits 954system.cpu.l2cache.demand_hits::total 2033288 # number of demand (read+write) hits |
| 949system.cpu.l2cache.overall_hits::cpu.inst 1018225 # number of overall hits | 955system.cpu.l2cache.overall_hits::cpu.inst 1018225 # number of overall hits |
| 950system.cpu.l2cache.overall_hits::cpu.data 1015065 # number of overall hits 951system.cpu.l2cache.overall_hits::total 2033290 # number of overall hits | 956system.cpu.l2cache.overall_hits::cpu.data 1015063 # number of overall hits 957system.cpu.l2cache.overall_hits::total 2033288 # number of overall hits |
| 952system.cpu.l2cache.ReadReq_misses::cpu.inst 15127 # number of ReadReq misses 953system.cpu.l2cache.ReadReq_misses::cpu.data 273931 # number of ReadReq misses 954system.cpu.l2cache.ReadReq_misses::total 289058 # number of ReadReq misses 955system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses 956system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses 957system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses 958system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses | 958system.cpu.l2cache.ReadReq_misses::cpu.inst 15127 # number of ReadReq misses 959system.cpu.l2cache.ReadReq_misses::cpu.data 273931 # number of ReadReq misses 960system.cpu.l2cache.ReadReq_misses::total 289058 # number of ReadReq misses 961system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses 962system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses 963system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses 964system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses |
| 959system.cpu.l2cache.ReadExReq_misses::cpu.data 115274 # number of ReadExReq misses 960system.cpu.l2cache.ReadExReq_misses::total 115274 # number of ReadExReq misses | 965system.cpu.l2cache.ReadExReq_misses::cpu.data 115276 # number of ReadExReq misses 966system.cpu.l2cache.ReadExReq_misses::total 115276 # number of ReadExReq misses |
| 961system.cpu.l2cache.demand_misses::cpu.inst 15127 # number of demand (read+write) misses | 967system.cpu.l2cache.demand_misses::cpu.inst 15127 # number of demand (read+write) misses |
| 962system.cpu.l2cache.demand_misses::cpu.data 389205 # number of demand (read+write) misses 963system.cpu.l2cache.demand_misses::total 404332 # number of demand (read+write) misses | 968system.cpu.l2cache.demand_misses::cpu.data 389207 # number of demand (read+write) misses 969system.cpu.l2cache.demand_misses::total 404334 # number of demand (read+write) misses |
| 964system.cpu.l2cache.overall_misses::cpu.inst 15127 # number of overall misses | 970system.cpu.l2cache.overall_misses::cpu.inst 15127 # number of overall misses |
| 965system.cpu.l2cache.overall_misses::cpu.data 389205 # number of overall misses 966system.cpu.l2cache.overall_misses::total 404332 # number of overall misses | 971system.cpu.l2cache.overall_misses::cpu.data 389207 # number of overall misses 972system.cpu.l2cache.overall_misses::total 404334 # number of overall misses |
| 967system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1264836999 # number of ReadReq miss cycles 968system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20020012000 # number of ReadReq miss cycles 969system.cpu.l2cache.ReadReq_miss_latency::total 21284848999 # number of ReadReq miss cycles 970system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395995 # number of UpgradeReq miss cycles 971system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles 972system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles 973system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles | 973system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1264836999 # number of ReadReq miss cycles 974system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20020012000 # number of ReadReq miss cycles 975system.cpu.l2cache.ReadReq_miss_latency::total 21284848999 # number of ReadReq miss cycles 976system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395995 # number of UpgradeReq miss cycles 977system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles 978system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles 979system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles |
| 974system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271336364 # number of ReadExReq miss cycles 975system.cpu.l2cache.ReadExReq_miss_latency::total 10271336364 # number of ReadExReq miss cycles | 980system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271399612 # number of ReadExReq miss cycles 981system.cpu.l2cache.ReadExReq_miss_latency::total 10271399612 # number of ReadExReq miss cycles |
| 976system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles | 982system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles |
| 977system.cpu.l2cache.demand_miss_latency::cpu.data 30291348364 # number of demand (read+write) miss cycles 978system.cpu.l2cache.demand_miss_latency::total 31556185363 # number of demand (read+write) miss cycles | 983system.cpu.l2cache.demand_miss_latency::cpu.data 30291411612 # number of demand (read+write) miss cycles 984system.cpu.l2cache.demand_miss_latency::total 31556248611 # number of demand (read+write) miss cycles |
| 979system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles | 985system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles |
| 980system.cpu.l2cache.overall_miss_latency::cpu.data 30291348364 # number of overall miss cycles 981system.cpu.l2cache.overall_miss_latency::total 31556185363 # number of overall miss cycles | 986system.cpu.l2cache.overall_miss_latency::cpu.data 30291411612 # number of overall miss cycles 987system.cpu.l2cache.overall_miss_latency::total 31556248611 # number of overall miss cycles |
| 982system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses) 983system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses) 984system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses) 985system.cpu.l2cache.Writeback_accesses::writebacks 842087 # number of Writeback accesses(hits+misses) 986system.cpu.l2cache.Writeback_accesses::total 842087 # number of Writeback accesses(hits+misses) 987system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) 988system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 989system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 27 # number of SCUpgradeReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 998system.cpu.l2cache.overall_accesses::total 2437622 # number of overall (read+write) accesses 999system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014639 # miss rate for ReadReq accesses 1000system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248428 # miss rate for ReadReq accesses 1001system.cpu.l2cache.ReadReq_miss_rate::total 0.135326 # miss rate for ReadReq accesses 1002system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.607595 # miss rate for UpgradeReq accesses 1003system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses 1004system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses 1005system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses | 988system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses) 989system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses) 990system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses) 991system.cpu.l2cache.Writeback_accesses::writebacks 842087 # number of Writeback accesses(hits+misses) 992system.cpu.l2cache.Writeback_accesses::total 842087 # number of Writeback accesses(hits+misses) 993system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) 994system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 995system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 27 # number of SCUpgradeReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 1004system.cpu.l2cache.overall_accesses::total 2437622 # number of overall (read+write) accesses 1005system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014639 # miss rate for ReadReq accesses 1006system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248428 # miss rate for ReadReq accesses 1007system.cpu.l2cache.ReadReq_miss_rate::total 0.135326 # miss rate for ReadReq accesses 1008system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.607595 # miss rate for UpgradeReq accesses 1009system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses 1010system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses 1011system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses |
| 1006system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382192 # miss rate for ReadExReq accesses 1007system.cpu.l2cache.ReadExReq_miss_rate::total 0.382192 # miss rate for ReadExReq accesses | 1012system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382198 # miss rate for ReadExReq accesses 1013system.cpu.l2cache.ReadExReq_miss_rate::total 0.382198 # miss rate for ReadExReq accesses |
| 1008system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses | 1014system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses |
| 1009system.cpu.l2cache.demand_miss_rate::cpu.data 0.277158 # miss rate for demand accesses 1010system.cpu.l2cache.demand_miss_rate::total 0.165871 # miss rate for demand accesses | 1015system.cpu.l2cache.demand_miss_rate::cpu.data 0.277160 # miss rate for demand accesses 1016system.cpu.l2cache.demand_miss_rate::total 0.165872 # miss rate for demand accesses |
| 1011system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses | 1017system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses |
| 1012system.cpu.l2cache.overall_miss_rate::cpu.data 0.277158 # miss rate for overall accesses 1013system.cpu.l2cache.overall_miss_rate::total 0.165871 # miss rate for overall accesses | 1018system.cpu.l2cache.overall_miss_rate::cpu.data 0.277160 # miss rate for overall accesses 1019system.cpu.l2cache.overall_miss_rate::total 0.165872 # miss rate for overall accesses |
| 1014system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency 1015system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency 1016system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency 1017system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8249.895833 # average UpgradeReq miss latency 1018system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency 1019system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency 1020system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency | 1020system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency 1021system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency 1022system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency 1023system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8249.895833 # average UpgradeReq miss latency 1024system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency 1025system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency 1026system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency |
| 1021system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89103.669206 # average ReadExReq miss latency 1022system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89103.669206 # average ReadExReq miss latency | 1027system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89102.671953 # average ReadExReq miss latency 1028system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89102.671953 # average ReadExReq miss latency |
| 1023system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency | 1029system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency |
| 1024system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency 1025system.cpu.l2cache.demand_avg_miss_latency::total 78045.233528 # average overall miss latency | 1030system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency 1031system.cpu.l2cache.demand_avg_miss_latency::total 78045.003910 # average overall miss latency |
| 1026system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency | 1032system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency |
| 1027system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency 1028system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency | 1033system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::total 78045.003910 # average overall miss latency |
| 1029system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1030system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1031system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1032system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1033system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1034system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1035system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1036system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 1044system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1045system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15126 # number of ReadReq MSHR misses 1046system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273931 # number of ReadReq MSHR misses 1047system.cpu.l2cache.ReadReq_mshr_misses::total 289057 # number of ReadReq MSHR misses 1048system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses 1049system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses 1050system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses 1051system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses | 1035system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1036system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1037system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1038system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1039system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1040system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1041system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1042system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 1050system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1051system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15126 # number of ReadReq MSHR misses 1052system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273931 # number of ReadReq MSHR misses 1053system.cpu.l2cache.ReadReq_mshr_misses::total 289057 # number of ReadReq MSHR misses 1054system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses 1055system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses 1056system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses 1057system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses |
| 1052system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses 1053system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses | 1058system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115276 # number of ReadExReq MSHR misses 1059system.cpu.l2cache.ReadExReq_mshr_misses::total 115276 # number of ReadExReq MSHR misses |
| 1054system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses | 1060system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses |
| 1055system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # number of demand (read+write) MSHR misses 1056system.cpu.l2cache.demand_mshr_misses::total 404331 # number of demand (read+write) MSHR misses | 1061system.cpu.l2cache.demand_mshr_misses::cpu.data 389207 # number of demand (read+write) MSHR misses 1062system.cpu.l2cache.demand_mshr_misses::total 404333 # number of demand (read+write) MSHR misses |
| 1057system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses | 1063system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses |
| 1058system.cpu.l2cache.overall_mshr_misses::cpu.data 389205 # number of overall MSHR misses 1059system.cpu.l2cache.overall_mshr_misses::total 404331 # number of overall MSHR misses | 1064system.cpu.l2cache.overall_mshr_misses::cpu.data 389207 # number of overall MSHR misses 1065system.cpu.l2cache.overall_mshr_misses::total 404333 # number of overall MSHR misses 1066system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 1067system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 1068system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable 1069system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable 1070system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses 1071system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses |
| 1060system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles 1061system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles 1062system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles 1063system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1000544 # number of UpgradeReq MSHR miss cycles 1064system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles 1065system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles 1066system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles | 1072system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles 1073system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles 1074system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles 1075system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1000544 # number of UpgradeReq MSHR miss cycles 1076system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles 1077system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles 1078system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles |
| 1067system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861608136 # number of ReadExReq MSHR miss cycles 1068system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861608136 # number of ReadExReq MSHR miss cycles | 1079system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861643888 # number of ReadExReq MSHR miss cycles 1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861643888 # number of ReadExReq MSHR miss cycles |
| 1069system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles | 1081system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles |
| 1070system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469504136 # number of demand (read+write) MSHR miss cycles 1071system.cpu.l2cache.demand_mshr_miss_latency::total 26545330885 # number of demand (read+write) MSHR miss cycles | 1082system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469539888 # number of demand (read+write) MSHR miss cycles 1083system.cpu.l2cache.demand_mshr_miss_latency::total 26545366637 # number of demand (read+write) MSHR miss cycles |
| 1072system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles | 1084system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles |
| 1073system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469504136 # number of overall MSHR miss cycles 1074system.cpu.l2cache.overall_mshr_miss_latency::total 26545330885 # number of overall MSHR miss cycles | 1085system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469539888 # number of overall MSHR miss cycles 1086system.cpu.l2cache.overall_mshr_miss_latency::total 26545366637 # number of overall MSHR miss cycles |
| 1075system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles 1076system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles 1077system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles 1078system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887182500 # number of WriteReq MSHR uncacheable cycles 1079system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223869000 # number of overall MSHR uncacheable cycles 1080system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223869000 # number of overall MSHR uncacheable cycles 1081system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for ReadReq accesses 1082system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248428 # mshr miss rate for ReadReq accesses 1083system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135326 # mshr miss rate for ReadReq accesses 1084system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 # mshr miss rate for UpgradeReq accesses 1085system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses 1086system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses 1087system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses | 1087system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles 1088system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles 1089system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles 1090system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887182500 # number of WriteReq MSHR uncacheable cycles 1091system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223869000 # number of overall MSHR uncacheable cycles 1092system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223869000 # number of overall MSHR uncacheable cycles 1093system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for ReadReq accesses 1094system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248428 # mshr miss rate for ReadReq accesses 1095system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135326 # mshr miss rate for ReadReq accesses 1096system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 # mshr miss rate for UpgradeReq accesses 1097system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses 1098system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses 1099system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses |
| 1088system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382192 # mshr miss rate for ReadExReq accesses 1089system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382192 # mshr miss rate for ReadExReq accesses | 1100system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382198 # mshr miss rate for ReadExReq accesses 1101system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382198 # mshr miss rate for ReadExReq accesses |
| 1090system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses | 1102system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses |
| 1091system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for demand accesses 1092system.cpu.l2cache.demand_mshr_miss_rate::total 0.165871 # mshr miss rate for demand accesses | 1103system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for demand accesses 1104system.cpu.l2cache.demand_mshr_miss_rate::total 0.165872 # mshr miss rate for demand accesses |
| 1093system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses | 1105system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses |
| 1094system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for overall accesses 1095system.cpu.l2cache.overall_mshr_miss_rate::total 0.165871 # mshr miss rate for overall accesses | 1106system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for overall accesses 1107system.cpu.l2cache.overall_mshr_miss_rate::total 0.165872 # mshr miss rate for overall accesses |
| 1096system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency 1097system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency 1098system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency 1099system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 # average UpgradeReq mshr miss latency 1100system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency 1101system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency 1102system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency | 1108system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency 1109system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency 1110system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency 1111system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 # average UpgradeReq mshr miss latency 1112system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency 1113system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency 1114system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency |
| 1103system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency 1104system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency | 1115system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76873.277074 # average ReadExReq mshr miss latency 1116system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76873.277074 # average ReadExReq mshr miss latency |
| 1105system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency | 1117system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency |
| 1106system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency 1107system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency | 1118system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency 1119system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency |
| 1108system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency | 1120system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency |
| 1109system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency 1110system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency 1111system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1112system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1113system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1114system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1115system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1116system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1121system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency 1122system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency 1123system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192884.054834 # average ReadReq mshr uncacheable latency 1124system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192884.054834 # average ReadReq mshr uncacheable latency 1125system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196642.961342 # average WriteReq mshr uncacheable latency 1126system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196642.961342 # average WriteReq mshr uncacheable latency 1127system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195066.799782 # average overall mshr uncacheable latency 1128system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195066.799782 # average overall mshr uncacheable latency |
| 1117system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1118system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution --- 4 unchanged lines hidden (view full) --- 1129system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution 1130system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes) 1131system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes) 1132system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes) 1133system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes) 1134system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) 1135system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) 1136system.cpu.toL2Bus.snoops 42097 # Total snoops (count) | 1129system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1130system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution 1131system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution 1132system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 1133system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution 1134system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution 1135system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution 1136system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution --- 4 unchanged lines hidden (view full) --- 1141system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution 1142system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes) 1143system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes) 1144system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes) 1145system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes) 1146system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) 1147system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) 1148system.cpu.toL2Bus.snoops 42097 # Total snoops (count) |
| 1137system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram 1138system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram 1139system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram | 1149system.cpu.toL2Bus.snoop_fanout::samples 3338284 # Request fanout histogram 1150system.cpu.toL2Bus.snoop_fanout::mean 1.012514 # Request fanout histogram 1151system.cpu.toL2Bus.snoop_fanout::stdev 0.111162 # Request fanout histogram |
| 1140system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1152system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1153system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1142system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram 1143system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram | 1154system.cpu.toL2Bus.snoop_fanout::1 3296510 98.75% 98.75% # Request fanout histogram 1155system.cpu.toL2Bus.snoop_fanout::2 41774 1.25% 100.00% # Request fanout histogram |
| 1144system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1145system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1156system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1147system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram | 1159system.cpu.toL2Bus.snoop_fanout::total 3338284 # Request fanout histogram |
| 1148system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) 1149system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1150system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 1151system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1152system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) 1153system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1160system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) 1161system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1162system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 1163system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1164system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) 1165system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1154system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks) | 1166system.cpu.toL2Bus.respLayer1.occupancy 2190379636 # Layer occupancy (ticks) |
| 1155system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1156system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1157system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1158system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1159system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1160system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1161system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1162system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 168 unchanged lines hidden (view full) --- 1331system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1332system.membus.trans_dist::ReadReq 296160 # Transaction distribution 1333system.membus.trans_dist::ReadResp 296066 # Transaction distribution 1334system.membus.trans_dist::WriteReq 9597 # Transaction distribution 1335system.membus.trans_dist::WriteResp 9597 # Transaction distribution 1336system.membus.trans_dist::Writeback 117457 # Transaction distribution 1337system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1338system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution | 1167system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1168system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1169system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1170system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1171system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1172system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1173system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1174system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 168 unchanged lines hidden (view full) --- 1343system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1344system.membus.trans_dist::ReadReq 296160 # Transaction distribution 1345system.membus.trans_dist::ReadResp 296066 # Transaction distribution 1346system.membus.trans_dist::WriteReq 9597 # Transaction distribution 1347system.membus.trans_dist::WriteResp 9597 # Transaction distribution 1348system.membus.trans_dist::Writeback 117457 # Transaction distribution 1349system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1350system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 1339system.membus.trans_dist::UpgradeReq 185 # Transaction distribution | 1351system.membus.trans_dist::UpgradeReq 187 # Transaction distribution |
| 1340system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution | 1352system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution |
| 1341system.membus.trans_dist::UpgradeResp 190 # Transaction distribution | 1353system.membus.trans_dist::UpgradeResp 192 # Transaction distribution |
| 1342system.membus.trans_dist::ReadExReq 115137 # Transaction distribution 1343system.membus.trans_dist::ReadExResp 115137 # Transaction distribution 1344system.membus.trans_dist::BadAddressError 94 # Transaction distribution 1345system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) | 1354system.membus.trans_dist::ReadExReq 115137 # Transaction distribution 1355system.membus.trans_dist::ReadExResp 115137 # Transaction distribution 1356system.membus.trans_dist::BadAddressError 94 # Transaction distribution 1357system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) |
| 1346system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes) | 1358system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884252 # Packet count per connected master and slave (bytes) |
| 1347system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) | 1359system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) |
| 1348system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes) | 1360system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917494 # Packet count per connected master and slave (bytes) |
| 1349system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1350system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) | 1361system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1362system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) |
| 1351system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes) | 1363system.membus.pkt_count::total 1042298 # Packet count per connected master and slave (bytes) |
| 1352system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) 1353system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) 1354system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) 1355system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1356system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1357system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) 1358system.membus.snoops 435 # Total snoops (count) | 1364system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) 1365system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) 1366system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) 1367system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1368system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1369system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) 1370system.membus.snoops 435 # Total snoops (count) |
| 1359system.membus.snoop_fanout::samples 563651 # Request fanout histogram | 1371system.membus.snoop_fanout::samples 580180 # Request fanout histogram |
| 1360system.membus.snoop_fanout::mean 1 # Request fanout histogram 1361system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1362system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1363system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1372system.membus.snoop_fanout::mean 1 # Request fanout histogram 1373system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1374system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1375system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1364system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram | 1376system.membus.snoop_fanout::1 580180 100.00% 100.00% # Request fanout histogram |
| 1365system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1366system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1367system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1368system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1377system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1378system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1379system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1380system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1369system.membus.snoop_fanout::total 563651 # Request fanout histogram | 1381system.membus.snoop_fanout::total 580180 # Request fanout histogram |
| 1370system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) 1371system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1382system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) 1383system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1372system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks) | 1384system.membus.reqLayer1.occupancy 1226050062 # Layer occupancy (ticks) |
| 1373system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1374system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) 1375system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1385system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1386system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) 1387system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1376system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks) | 1388system.membus.respLayer1.occupancy 2139458813 # Layer occupancy (ticks) |
| 1377system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1378system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) 1379system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1380system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1381system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1382system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1383system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1384system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 113 unchanged lines hidden --- | 1389system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1390system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) 1391system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1392system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1393system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1394system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1395system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1396system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 113 unchanged lines hidden --- |