stats.txt (10726:8a20e2a1562d) stats.txt (10736:4433fb00fa7d)
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2---------- Begin Simulation Statistics ----------
3sim_seconds 1.861006 # Number of seconds simulated
4sim_ticks 1861005569500 # Number of ticks simulated
5final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 153218 # Simulator instruction rate (inst/s)
8host_op_rate 153218 # Simulator op (including micro ops) rate (op/s)

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628system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
629system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
630system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction
631system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction
632system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction
633system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
634system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction
635system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached
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2---------- Begin Simulation Statistics ----------
3sim_seconds 1.861006 # Number of seconds simulated
4sim_ticks 1861005569500 # Number of ticks simulated
5final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 153218 # Simulator instruction rate (inst/s)
8host_op_rate 153218 # Simulator op (including micro ops) rate (op/s)

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628system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
629system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
630system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction
631system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction
632system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction
633system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
634system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction
635system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached
636system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
637system.cpu.rob.rob_reads 177593269 # The number of ROB reads
638system.cpu.rob.rob_writes 130137832 # The number of ROB writes
639system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself
640system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling
641system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
642system.cpu.committedInsts 52934565 # Number of Instructions Simulated
643system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated
644system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction

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636system.cpu.rob.rob_reads 177593269 # The number of ROB reads
637system.cpu.rob.rob_writes 130137832 # The number of ROB writes
638system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself
639system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling
640system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
641system.cpu.committedInsts 52934565 # Number of Instructions Simulated
642system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated
643system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction

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