| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.859045 # Number of seconds simulated 4sim_ticks 1859045389000 # Number of ticks simulated 5final_tick 1859045389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.861006 # Number of seconds simulated 4sim_ticks 1861005569500 # Number of ticks simulated 5final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 155751 # Simulator instruction rate (inst/s) 8host_op_rate 155751 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5470499619 # Simulator tick rate (ticks/s) 10host_mem_usage 374716 # Number of bytes of host memory used 11host_seconds 339.83 # Real time elapsed on the host 12sim_insts 52929026 # Number of instructions simulated 13sim_ops 52929026 # Number of ops (including micro ops) simulated | 7host_inst_rate 153218 # Simulator instruction rate (inst/s) 8host_op_rate 153218 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5386630373 # Simulator tick rate (ticks/s) 10host_mem_usage 376136 # Number of bytes of host memory used 11host_seconds 345.49 # Real time elapsed on the host 12sim_insts 52934565 # Number of instructions simulated 13sim_ops 52934565 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 968128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24876416 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 25845504 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 968128 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 968128 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7516800 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7516800 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 15127 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388694 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 968000 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 968000 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7517248 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 15125 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388701 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::total 403836 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 117450 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 117450 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 520766 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13381285 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::total 403841 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 117457 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 520149 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13367431 # Total read bandwidth from this memory (bytes/s) |
| 32system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::total 13902567 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 520766 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 520766 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4043366 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4043366 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4043366 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 520766 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13381285 # Total bandwidth to/from this memory (bytes/s) | 33system.physmem.bw_read::total 13888096 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 520149 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 520149 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4039347 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4039347 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4039347 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 520149 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13367431 # Total bandwidth to/from this memory (bytes/s) |
| 41system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) | 41system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) |
| 42system.physmem.bw_total::total 17945933 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 403836 # Number of read requests accepted 44system.physmem.writeReqs 159002 # Number of write requests accepted 45system.physmem.readBursts 403836 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 159002 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25838848 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue 49system.physmem.bytesWritten 10042304 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25845504 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10176128 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 2068 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 208 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25744 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25557 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25510 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25348 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25387 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24799 # Per bank write bursts | 42system.physmem.bw_total::total 17927443 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 403841 # Number of read requests accepted 44system.physmem.writeReqs 159009 # Number of write requests accepted 45system.physmem.readBursts 403841 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue 49system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25748 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25559 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25508 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25346 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25393 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24806 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::6 25027 # Per bank write bursts | 61system.physmem.perBankRdBursts::6 25027 # Per bank write bursts |
| 62system.physmem.perBankRdBursts::7 25129 # Per bank write bursts 63system.physmem.perBankRdBursts::8 24928 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25032 # Per bank write bursts | 62system.physmem.perBankRdBursts::7 25127 # Per bank write bursts 63system.physmem.perBankRdBursts::8 24925 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25034 # Per bank write bursts |
| 65system.physmem.perBankRdBursts::10 25436 # Per bank write bursts | 65system.physmem.perBankRdBursts::10 25436 # Per bank write bursts |
| 66system.physmem.perBankRdBursts::11 24784 # Per bank write bursts | 66system.physmem.perBankRdBursts::11 24774 # Per bank write bursts |
| 67system.physmem.perBankRdBursts::12 24551 # Per bank write bursts | 67system.physmem.perBankRdBursts::12 24551 # Per bank write bursts |
| 68system.physmem.perBankRdBursts::13 25235 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25659 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25606 # Per bank write bursts 71system.physmem.perBankWrBursts::0 10485 # Per bank write bursts 72system.physmem.perBankWrBursts::1 10108 # Per bank write bursts 73system.physmem.perBankWrBursts::2 10574 # Per bank write bursts 74system.physmem.perBankWrBursts::3 9632 # Per bank write bursts 75system.physmem.perBankWrBursts::4 9668 # Per bank write bursts 76system.physmem.perBankWrBursts::5 9137 # Per bank write bursts 77system.physmem.perBankWrBursts::6 9064 # Per bank write bursts 78system.physmem.perBankWrBursts::7 8900 # Per bank write bursts 79system.physmem.perBankWrBursts::8 9821 # Per bank write bursts 80system.physmem.perBankWrBursts::9 8750 # Per bank write bursts 81system.physmem.perBankWrBursts::10 9677 # Per bank write bursts 82system.physmem.perBankWrBursts::11 9460 # Per bank write bursts 83system.physmem.perBankWrBursts::12 10019 # Per bank write bursts 84system.physmem.perBankWrBursts::13 10709 # Per bank write bursts 85system.physmem.perBankWrBursts::14 10502 # Per bank write bursts 86system.physmem.perBankWrBursts::15 10405 # Per bank write bursts | 68system.physmem.perBankRdBursts::13 25233 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25663 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25612 # Per bank write bursts 71system.physmem.perBankWrBursts::0 9148 # Per bank write bursts 72system.physmem.perBankWrBursts::1 8514 # Per bank write bursts 73system.physmem.perBankWrBursts::2 8998 # Per bank write bursts 74system.physmem.perBankWrBursts::3 8298 # Per bank write bursts 75system.physmem.perBankWrBursts::4 8214 # Per bank write bursts 76system.physmem.perBankWrBursts::5 7705 # Per bank write bursts 77system.physmem.perBankWrBursts::6 7696 # Per bank write bursts 78system.physmem.perBankWrBursts::7 7707 # Per bank write bursts 79system.physmem.perBankWrBursts::8 8055 # Per bank write bursts 80system.physmem.perBankWrBursts::9 7602 # Per bank write bursts 81system.physmem.perBankWrBursts::10 8149 # Per bank write bursts 82system.physmem.perBankWrBursts::11 7799 # Per bank write bursts 83system.physmem.perBankWrBursts::12 8377 # Per bank write bursts 84system.physmem.perBankWrBursts::13 9062 # Per bank write bursts 85system.physmem.perBankWrBursts::14 8903 # Per bank write bursts 86system.physmem.perBankWrBursts::15 8889 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 88system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 89system.physmem.totGap 1859040142000 # Total gap between requests | 88system.physmem.numWrRetry 85 # Number of times write queue was full causing retry 89system.physmem.totGap 1861000236500 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 403836 # Read request sizes (log2) | 96system.physmem.readPktSize::6 403841 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 159002 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 314988 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 42944 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 8167 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 159009 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 314763 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 36627 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 28957 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 23318 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see |
| 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see --- 24 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see --- 24 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 1972 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 3943 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 5463 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 7486 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 9283 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 10669 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 11213 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 12176 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 11727 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 11991 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 10998 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 10334 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 9228 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 9381 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 7187 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6922 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6754 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 403 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 340 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 313 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 184 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 178 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 164 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 63696 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 563.318764 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 349.809758 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 419.596932 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 13378 21.00% 21.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10306 16.18% 37.18% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4860 7.63% 44.81% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 2855 4.48% 49.30% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2272 3.57% 52.86% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1671 2.62% 55.49% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1518 2.38% 57.87% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1616 2.54% 60.41% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 25220 39.59% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 63696 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5671 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 71.190619 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2803.945627 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5668 99.95% 99.95% # Reads before turning the bus around for writes | 151system.physmem.wrQLenPdf::15 1177 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1767 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 3672 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4051 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 5591 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5498 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5482 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5462 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 5789 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5773 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 7246 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 6053 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 7006 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5988 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 1362 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 680 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 1298 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 1299 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1703 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1519 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1726 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 2145 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1965 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 2231 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 2575 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 2937 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 2118 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1790 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1255 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1214 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 722 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 404 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 263 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 194 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 165 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 323 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 62685 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 548.114030 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 339.010384 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 417.134053 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 13424 21.42% 21.42% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10425 16.63% 38.05% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 5386 8.59% 46.64% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 2710 4.32% 50.96% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2462 3.93% 54.89% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1644 2.62% 57.51% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1512 2.41% 59.92% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1300 2.07% 62.00% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 23822 38.00% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 62685 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4847 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 83.295234 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 3032.862596 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 4844 99.94% 99.94% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::total 5671 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5671 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 27.669018 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 20.928355 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 34.069194 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-23 4623 81.52% 81.52% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-31 171 3.02% 84.54% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-39 302 5.33% 89.86% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-47 63 1.11% 90.97% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-55 97 1.71% 92.68% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::56-63 43 0.76% 93.44% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::64-71 19 0.34% 93.78% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-79 6 0.11% 93.88% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::80-87 22 0.39% 94.27% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::88-95 4 0.07% 94.34% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::96-103 17 0.30% 94.64% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-111 4 0.07% 94.71% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::112-119 14 0.25% 94.96% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::120-127 6 0.11% 95.06% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-135 18 0.32% 95.38% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::136-143 43 0.76% 96.14% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::144-151 8 0.14% 96.28% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::152-159 17 0.30% 96.58% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 89 1.57% 98.15% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::168-175 36 0.63% 98.78% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 17 0.30% 99.08% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 22 0.39% 99.47% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::192-199 13 0.23% 99.70% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 1 0.02% 99.72% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::208-215 4 0.07% 99.79% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::232-239 5 0.09% 99.93% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::total 5671 # Writes before turning the bus around for reads 258system.physmem.totQLat 3621320000 # Total ticks spent queuing 259system.physmem.totMemAccLat 11191295000 # Total ticks spent from burst creation until serviced by the DRAM 260system.physmem.totBusLat 2018660000 # Total ticks spent in databus transfers 261system.physmem.avgQLat 8969.61 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 4847 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 4847 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 27.463586 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 18.516932 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 62.014286 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-31 4601 94.92% 94.92% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-47 56 1.16% 96.08% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::48-63 4 0.08% 96.16% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::64-79 1 0.02% 96.18% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::80-95 13 0.27% 96.45% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::96-111 3 0.06% 96.51% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::112-127 3 0.06% 96.58% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::128-143 6 0.12% 96.70% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::144-159 21 0.43% 97.13% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::160-175 18 0.37% 97.50% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::176-191 8 0.17% 97.67% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::192-207 12 0.25% 97.92% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::208-223 2 0.04% 97.96% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::224-239 4 0.08% 98.04% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::256-271 1 0.02% 98.06% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::288-303 2 0.04% 98.10% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::304-319 5 0.10% 98.21% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::320-335 17 0.35% 98.56% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::336-351 13 0.27% 98.82% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::352-367 3 0.06% 98.89% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::368-383 11 0.23% 99.11% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::384-399 4 0.08% 99.20% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::432-447 2 0.04% 99.24% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::448-463 2 0.04% 99.28% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::464-479 4 0.08% 99.36% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::480-495 4 0.08% 99.44% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::496-511 4 0.08% 99.53% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::512-527 2 0.04% 99.57% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::528-543 2 0.04% 99.61% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::544-559 8 0.17% 99.77% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads 264system.physmem.totQLat 3741903500 # Total ticks spent queuing 265system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM 266system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers 267system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst |
| 262system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 263system.physmem.avgMemAccLat 27719.61 # Average memory access latency per DRAM burst 264system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s 265system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s 266system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s | 269system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst 270system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s |
| 267system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s 268system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 273system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s 274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 269system.physmem.busUtil 0.15 # Data bus utilization in percentage | 275system.physmem.busUtil 0.14 # Data bus utilization in percentage |
| 270system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 271system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes | 276system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 277system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes |
| 272system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing 273system.physmem.avgWrQLen 25.54 # Average write queue length when enqueuing 274system.physmem.readRowHits 364717 # Number of row buffer hits during reads 275system.physmem.writeRowHits 132230 # Number of row buffer hits during writes 276system.physmem.readRowHitRate 90.34 # Row buffer hit rate for reads 277system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes 278system.physmem.avgGap 3302975.53 # Average gap between requests 279system.physmem.pageHitRate 88.64 # Row buffer hit rate, read and write combined 280system.physmem_0.actEnergy 239009400 # Energy for activate commands per rank (pJ) 281system.physmem_0.preEnergy 130411875 # Energy for precharge commands per rank (pJ) 282system.physmem_0.readEnergy 1579507800 # Energy for read commands per rank (pJ) 283system.physmem_0.writeEnergy 502640640 # Energy for write commands per rank (pJ) 284system.physmem_0.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) 285system.physmem_0.actBackEnergy 55671864660 # Energy for active background per rank (pJ) 286system.physmem_0.preBackEnergy 1066592208750 # Energy for precharge background per rank (pJ) 287system.physmem_0.totalEnergy 1246139428725 # Total energy per rank (pJ) 288system.physmem_0.averagePower 670.311493 # Core power per rank (mW) 289system.physmem_0.memoryStateTime::IDLE 1774205493250 # Time in different power states 290system.physmem_0.memoryStateTime::REF 62077600000 # Time in different power states | 278system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing 279system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing 280system.physmem.readRowHits 364326 # Number of row buffer hits during reads 281system.physmem.writeRowHits 109846 # Number of row buffer hits during writes 282system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads 283system.physmem.writeRowHitRate 82.50 # Row buffer hit rate for writes 284system.physmem.avgGap 3306387.56 # Average gap between requests 285system.physmem.pageHitRate 88.32 # Row buffer hit rate, read and write combined 286system.physmem_0.actEnergy 235516680 # Energy for activate commands per rank (pJ) 287system.physmem_0.preEnergy 128506125 # Energy for precharge commands per rank (pJ) 288system.physmem_0.readEnergy 1579609200 # Energy for read commands per rank (pJ) 289system.physmem_0.writeEnergy 429494400 # Energy for write commands per rank (pJ) 290system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) 291system.physmem_0.actBackEnergy 56182721175 # Energy for active background per rank (pJ) 292system.physmem_0.preBackEnergy 1067316698250 # Energy for precharge background per rank (pJ) 293system.physmem_0.totalEnergy 1247423979990 # Total energy per rank (pJ) 294system.physmem_0.averagePower 670.297807 # Core power per rank (mW) 295system.physmem_0.memoryStateTime::IDLE 1775410357162 # Time in different power states 296system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states |
| 291system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 297system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 292system.physmem_0.memoryStateTime::ACT 22762216750 # Time in different power states | 298system.physmem_0.memoryStateTime::ACT 23446441588 # Time in different power states |
| 293system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 299system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 294system.physmem_1.actEnergy 242532360 # Energy for activate commands per rank (pJ) 295system.physmem_1.preEnergy 132334125 # Energy for precharge commands per rank (pJ) 296system.physmem_1.readEnergy 1569601800 # Energy for read commands per rank (pJ) 297system.physmem_1.writeEnergy 514142640 # Energy for write commands per rank (pJ) 298system.physmem_1.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) 299system.physmem_1.actBackEnergy 55569327930 # Energy for active background per rank (pJ) 300system.physmem_1.preBackEnergy 1066682161500 # Energy for precharge background per rank (pJ) 301system.physmem_1.totalEnergy 1246133885955 # Total energy per rank (pJ) 302system.physmem_1.averagePower 670.308507 # Core power per rank (mW) 303system.physmem_1.memoryStateTime::IDLE 1774360012750 # Time in different power states 304system.physmem_1.memoryStateTime::REF 62077600000 # Time in different power states | 300system.physmem_1.actEnergy 238381920 # Energy for activate commands per rank (pJ) 301system.physmem_1.preEnergy 130069500 # Energy for precharge commands per rank (pJ) 302system.physmem_1.readEnergy 1569531600 # Energy for read commands per rank (pJ) 303system.physmem_1.writeEnergy 433097280 # Energy for write commands per rank (pJ) 304system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) 305system.physmem_1.actBackEnergy 56034129015 # Energy for active background per rank (pJ) 306system.physmem_1.preBackEnergy 1067447050500 # Energy for precharge background per rank (pJ) 307system.physmem_1.totalEnergy 1247403693975 # Total energy per rank (pJ) 308system.physmem_1.averagePower 670.286901 # Core power per rank (mW) 309system.physmem_1.memoryStateTime::IDLE 1775626000168 # Time in different power states 310system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states |
| 305system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 306system.physmem_1.memoryStateTime::ACT 22607711000 # Time in different power states | 312system.physmem_1.memoryStateTime::ACT 23231077332 # Time in different power states |
| 307system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 308system.cpu.branchPred.lookups 17755011 # Number of BP lookups 309system.cpu.branchPred.condPredicted 15447257 # Number of conditional branches predicted 310system.cpu.branchPred.condIncorrect 380557 # Number of conditional branches incorrect 311system.cpu.branchPred.BTBLookups 11928628 # Number of BTB lookups 312system.cpu.branchPred.BTBHits 5915753 # Number of BTB hits | 314system.cpu.branchPred.lookups 17721924 # Number of BP lookups 315system.cpu.branchPred.condPredicted 15403228 # Number of conditional branches predicted 316system.cpu.branchPred.condIncorrect 380344 # Number of conditional branches incorrect 317system.cpu.branchPred.BTBLookups 11703979 # Number of BTB lookups 318system.cpu.branchPred.BTBHits 5913014 # Number of BTB hits |
| 313system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 319system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 314system.cpu.branchPred.BTBHitPct 49.592904 # BTB Hit Percentage 315system.cpu.branchPred.usedRAS 917507 # Number of times the RAS was used to get a target. 316system.cpu.branchPred.RASInCorrect 21428 # Number of incorrect RAS predictions. | 320system.cpu.branchPred.BTBHitPct 50.521400 # BTB Hit Percentage 321system.cpu.branchPred.usedRAS 923784 # Number of times the RAS was used to get a target. 322system.cpu.branchPred.RASInCorrect 21447 # Number of incorrect RAS predictions. |
| 317system.cpu_clk_domain.clock 500 # Clock period in ticks 318system.cpu.dtb.fetch_hits 0 # ITB hits 319system.cpu.dtb.fetch_misses 0 # ITB misses 320system.cpu.dtb.fetch_acv 0 # ITB acv 321system.cpu.dtb.fetch_accesses 0 # ITB accesses | 323system.cpu_clk_domain.clock 500 # Clock period in ticks 324system.cpu.dtb.fetch_hits 0 # ITB hits 325system.cpu.dtb.fetch_misses 0 # ITB misses 326system.cpu.dtb.fetch_acv 0 # ITB acv 327system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 322system.cpu.dtb.read_hits 10297861 # DTB read hits 323system.cpu.dtb.read_misses 41459 # DTB read misses 324system.cpu.dtb.read_acv 502 # DTB read access violations 325system.cpu.dtb.read_accesses 968382 # DTB read accesses 326system.cpu.dtb.write_hits 6648165 # DTB write hits 327system.cpu.dtb.write_misses 9537 # DTB write misses 328system.cpu.dtb.write_acv 407 # DTB write access violations 329system.cpu.dtb.write_accesses 342637 # DTB write accesses 330system.cpu.dtb.data_hits 16946026 # DTB hits 331system.cpu.dtb.data_misses 50996 # DTB misses | 328system.cpu.dtb.read_hits 10269214 # DTB read hits 329system.cpu.dtb.read_misses 41261 # DTB read misses 330system.cpu.dtb.read_acv 507 # DTB read access violations 331system.cpu.dtb.read_accesses 967301 # DTB read accesses 332system.cpu.dtb.write_hits 6648637 # DTB write hits 333system.cpu.dtb.write_misses 9303 # DTB write misses 334system.cpu.dtb.write_acv 402 # DTB write access violations 335system.cpu.dtb.write_accesses 342644 # DTB write accesses 336system.cpu.dtb.data_hits 16917851 # DTB hits 337system.cpu.dtb.data_misses 50564 # DTB misses |
| 332system.cpu.dtb.data_acv 909 # DTB access violations | 338system.cpu.dtb.data_acv 909 # DTB access violations |
| 333system.cpu.dtb.data_accesses 1311019 # DTB accesses 334system.cpu.itb.fetch_hits 1769037 # ITB hits 335system.cpu.itb.fetch_misses 35976 # ITB misses 336system.cpu.itb.fetch_acv 675 # ITB acv 337system.cpu.itb.fetch_accesses 1805013 # ITB accesses | 339system.cpu.dtb.data_accesses 1309945 # DTB accesses 340system.cpu.itb.fetch_hits 1769158 # ITB hits 341system.cpu.itb.fetch_misses 36068 # ITB misses 342system.cpu.itb.fetch_acv 660 # ITB acv 343system.cpu.itb.fetch_accesses 1805226 # ITB accesses |
| 338system.cpu.itb.read_hits 0 # DTB read hits 339system.cpu.itb.read_misses 0 # DTB read misses 340system.cpu.itb.read_acv 0 # DTB read access violations 341system.cpu.itb.read_accesses 0 # DTB read accesses 342system.cpu.itb.write_hits 0 # DTB write hits 343system.cpu.itb.write_misses 0 # DTB write misses 344system.cpu.itb.write_acv 0 # DTB write access violations 345system.cpu.itb.write_accesses 0 # DTB write accesses 346system.cpu.itb.data_hits 0 # DTB hits 347system.cpu.itb.data_misses 0 # DTB misses 348system.cpu.itb.data_acv 0 # DTB access violations 349system.cpu.itb.data_accesses 0 # DTB accesses | 344system.cpu.itb.read_hits 0 # DTB read hits 345system.cpu.itb.read_misses 0 # DTB read misses 346system.cpu.itb.read_acv 0 # DTB read access violations 347system.cpu.itb.read_accesses 0 # DTB read accesses 348system.cpu.itb.write_hits 0 # DTB write hits 349system.cpu.itb.write_misses 0 # DTB write misses 350system.cpu.itb.write_acv 0 # DTB write access violations 351system.cpu.itb.write_accesses 0 # DTB write accesses 352system.cpu.itb.data_hits 0 # DTB hits 353system.cpu.itb.data_misses 0 # DTB misses 354system.cpu.itb.data_acv 0 # DTB access violations 355system.cpu.itb.data_accesses 0 # DTB accesses |
| 350system.cpu.numCycles 118253854 # number of cpu cycles simulated | 356system.cpu.numCycles 122572361 # number of cpu cycles simulated |
| 351system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 352system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 357system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 358system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 353system.cpu.fetch.icacheStallCycles 29528041 # Number of cycles fetch is stalled on an Icache miss 354system.cpu.fetch.Insts 78024704 # Number of instructions fetch has processed 355system.cpu.fetch.Branches 17755011 # Number of branches that fetch encountered 356system.cpu.fetch.predictedBranches 6833260 # Number of branches that fetch has predicted taken 357system.cpu.fetch.Cycles 80443267 # Number of cycles fetch has run and was not squashing or blocked 358system.cpu.fetch.SquashCycles 1255548 # Number of cycles fetch has spent squashing 359system.cpu.fetch.TlbCycles 1917 # Number of cycles fetch has spent waiting for tlb 360system.cpu.fetch.MiscStallCycles 27791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 361system.cpu.fetch.PendingTrapStallCycles 1737879 # Number of stall cycles due to pending traps 362system.cpu.fetch.PendingQuiesceStallCycles 457742 # Number of stall cycles due to pending quiesce instructions 363system.cpu.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR 364system.cpu.fetch.CacheLines 9020958 # Number of cache lines fetched 365system.cpu.fetch.IcacheSquashes 272859 # Number of outstanding Icache misses that were squashed 366system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 367system.cpu.fetch.rateDist::samples 112824612 # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::mean 0.691557 # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::stdev 2.011053 # Number of instructions fetched each cycle (Total) | 359system.cpu.fetch.icacheStallCycles 29541441 # Number of cycles fetch is stalled on an Icache miss 360system.cpu.fetch.Insts 78093998 # Number of instructions fetch has processed 361system.cpu.fetch.Branches 17721924 # Number of branches that fetch encountered 362system.cpu.fetch.predictedBranches 6836798 # Number of branches that fetch has predicted taken 363system.cpu.fetch.Cycles 84630340 # Number of cycles fetch has run and was not squashing or blocked 364system.cpu.fetch.SquashCycles 1254210 # Number of cycles fetch has spent squashing 365system.cpu.fetch.TlbCycles 1349 # Number of cycles fetch has spent waiting for tlb 366system.cpu.fetch.MiscStallCycles 26888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 367system.cpu.fetch.PendingTrapStallCycles 1745325 # Number of stall cycles due to pending traps 368system.cpu.fetch.PendingQuiesceStallCycles 441267 # Number of stall cycles due to pending quiesce instructions 369system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR 370system.cpu.fetch.CacheLines 9051182 # Number of cache lines fetched 371system.cpu.fetch.IcacheSquashes 273719 # Number of outstanding Icache misses that were squashed 372system.cpu.fetch.rateDist::samples 117014009 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::mean 0.667390 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::stdev 1.979034 # Number of instructions fetched each cycle (Total) |
| 370system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 375system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 371system.cpu.fetch.rateDist::0 98261708 87.09% 87.09% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::1 933543 0.83% 87.92% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::2 1973411 1.75% 89.67% # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::3 908515 0.81% 90.47% # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::4 2794922 2.48% 92.95% # Number of instructions fetched each cycle (Total) 376system.cpu.fetch.rateDist::5 638903 0.57% 93.52% # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::6 728605 0.65% 94.16% # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::7 1007079 0.89% 95.06% # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::8 5577926 4.94% 100.00% # Number of instructions fetched each cycle (Total) | 376system.cpu.fetch.rateDist::0 102427448 87.53% 87.53% # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::1 934169 0.80% 88.33% # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::2 1984138 1.70% 90.03% # Number of instructions fetched each cycle (Total) 379system.cpu.fetch.rateDist::3 910061 0.78% 90.81% # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.rateDist::4 2793690 2.39% 93.19% # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.rateDist::5 647956 0.55% 93.75% # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::6 739168 0.63% 94.38% # Number of instructions fetched each cycle (Total) 383system.cpu.fetch.rateDist::7 1007210 0.86% 95.24% # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.rateDist::8 5570169 4.76% 100.00% # Number of instructions fetched each cycle (Total) |
| 380system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 381system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 382system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 385system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 387system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 383system.cpu.fetch.rateDist::total 112824612 # Number of instructions fetched each cycle (Total) 384system.cpu.fetch.branchRate 0.150143 # Number of branch fetches per cycle 385system.cpu.fetch.rate 0.659807 # Number of inst fetches per cycle 386system.cpu.decode.IdleCycles 24062318 # Number of cycles decode is idle 387system.cpu.decode.BlockedCycles 76790103 # Number of cycles decode is blocked 388system.cpu.decode.RunCycles 9490656 # Number of cycles decode is running 389system.cpu.decode.UnblockCycles 1896068 # Number of cycles decode is unblocking 390system.cpu.decode.SquashCycles 585466 # Number of cycles decode is squashing 391system.cpu.decode.BranchResolved 586954 # Number of times decode resolved a branch 392system.cpu.decode.BranchMispred 42767 # Number of times decode detected a branch misprediction 393system.cpu.decode.DecodedInsts 68209057 # Number of instructions handled by decode 394system.cpu.decode.SquashedInsts 130935 # Number of squashed instructions handled by decode 395system.cpu.rename.SquashCycles 585466 # Number of cycles rename is squashing 396system.cpu.rename.IdleCycles 24987088 # Number of cycles rename is idle 397system.cpu.rename.BlockCycles 47248716 # Number of cycles rename is blocking 398system.cpu.rename.serializeStallCycles 20734654 # count of cycles rename stalled for serializing inst 399system.cpu.rename.RunCycles 10372019 # Number of cycles rename is running 400system.cpu.rename.UnblockCycles 8896667 # Number of cycles rename is unblocking 401system.cpu.rename.RenamedInsts 65782894 # Number of instructions processed by rename 402system.cpu.rename.ROBFullEvents 200446 # Number of times rename has blocked due to ROB full 403system.cpu.rename.IQFullEvents 2040001 # Number of times rename has blocked due to IQ full 404system.cpu.rename.LQFullEvents 143212 # Number of times rename has blocked due to LQ full 405system.cpu.rename.SQFullEvents 4746299 # Number of times rename has blocked due to SQ full 406system.cpu.rename.RenamedOperands 43863584 # Number of destination operands rename has renamed 407system.cpu.rename.RenameLookups 79748694 # Number of register rename lookups that rename has made 408system.cpu.rename.int_rename_lookups 79567373 # Number of integer rename lookups 409system.cpu.rename.fp_rename_lookups 168869 # Number of floating rename lookups 410system.cpu.rename.CommittedMaps 38138490 # Number of HB maps that are committed 411system.cpu.rename.UndoneMaps 5725086 # Number of HB maps that are undone due to squashing 412system.cpu.rename.serializingInsts 1691130 # count of serializing insts renamed 413system.cpu.rename.tempSerializingInsts 241601 # count of temporary serializing insts renamed 414system.cpu.rename.skidInsts 13583154 # count of insts added to the skid buffer 415system.cpu.memDep0.insertedLoads 10423192 # Number of loads inserted to the mem dependence unit. 416system.cpu.memDep0.insertedStores 6953251 # Number of stores inserted to the mem dependence unit. 417system.cpu.memDep0.conflictingLoads 1496634 # Number of conflicting loads. 418system.cpu.memDep0.conflictingStores 1073096 # Number of conflicting stores. 419system.cpu.iq.iqInstsAdded 58558441 # Number of instructions added to the IQ (excludes non-spec) 420system.cpu.iq.iqNonSpecInstsAdded 2136854 # Number of non-speculative instructions added to the IQ 421system.cpu.iq.iqInstsIssued 57535876 # Number of instructions issued 422system.cpu.iq.iqSquashedInstsIssued 59225 # Number of squashed instructions issued 423system.cpu.iq.iqSquashedInstsExamined 7428094 # Number of squashed instructions iterated over during squash; mainly for profiling 424system.cpu.iq.iqSquashedOperandsExamined 3503981 # Number of squashed operands that are examined and possibly removed from graph 425system.cpu.iq.iqSquashedNonSpecRemoved 1475675 # Number of squashed non-spec instructions that were removed 426system.cpu.iq.issued_per_cycle::samples 112824612 # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::mean 0.509959 # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::stdev 1.252016 # Number of insts issued each cycle | 388system.cpu.fetch.rateDist::total 117014009 # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.branchRate 0.144583 # Number of branch fetches per cycle 390system.cpu.fetch.rate 0.637126 # Number of inst fetches per cycle 391system.cpu.decode.IdleCycles 24038562 # Number of cycles decode is idle 392system.cpu.decode.BlockedCycles 80987042 # Number of cycles decode is blocked 393system.cpu.decode.RunCycles 9497307 # Number of cycles decode is running 394system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking 395system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing 396system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch 397system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction 398system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode 399system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode 400system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing 401system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle 402system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking 403system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst 404system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running 405system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking 406system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename 407system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full 408system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full 409system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full 410system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full 411system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed 412system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made 413system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups 414system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups 415system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed 416system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing 417system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed 418system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed 419system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer 420system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. 421system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. 422system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. 423system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores. 424system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) 425system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ 426system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued 427system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued 428system.cpu.iq.iqSquashedInstsExamined 7497440 # Number of squashed instructions iterated over during squash; mainly for profiling 429system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph 430system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed 431system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle |
| 429system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 434system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 430system.cpu.iq.issued_per_cycle::0 89346173 79.19% 79.19% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::1 10029271 8.89% 88.08% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::2 4305402 3.82% 91.90% # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::3 2956038 2.62% 94.52% # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::4 3073019 2.72% 97.24% # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::5 1592834 1.41% 98.65% # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::6 1003723 0.89% 99.54% # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::7 396113 0.35% 99.89% # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::8 122039 0.11% 100.00% # Number of insts issued each cycle | 435system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle 438system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle 439system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle 442system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle 443system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle |
| 439system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 444system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 442system.cpu.iq.issued_per_cycle::total 112824612 # Number of insts issued each cycle | 447system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle |
| 443system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 448system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 444system.cpu.iq.fu_full::IntAlu 206156 18.23% 18.23% # attempts to use FU when none available 445system.cpu.iq.fu_full::IntMult 0 0.00% 18.23% # attempts to use FU when none available 446system.cpu.iq.fu_full::IntDiv 0 0.00% 18.23% # attempts to use FU when none available 447system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.23% # attempts to use FU when none available 448system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.23% # attempts to use FU when none available 449system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.23% # attempts to use FU when none available 450system.cpu.iq.fu_full::FloatMult 0 0.00% 18.23% # attempts to use FU when none available 451system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.23% # attempts to use FU when none available 452system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.23% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.23% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.23% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.23% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.23% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.23% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.23% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdMult 0 0.00% 18.23% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.23% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdShift 0 0.00% 18.23% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.23% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.23% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.23% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.23% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.23% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.23% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.23% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.23% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.23% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.23% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.23% # attempts to use FU when none available 473system.cpu.iq.fu_full::MemRead 547934 48.46% 66.69% # attempts to use FU when none available 474system.cpu.iq.fu_full::MemWrite 376604 33.31% 100.00% # attempts to use FU when none available | 449system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available 450system.cpu.iq.fu_full::IntMult 0 0.00% 18.84% # attempts to use FU when none available 451system.cpu.iq.fu_full::IntDiv 0 0.00% 18.84% # attempts to use FU when none available 452system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.84% # attempts to use FU when none available 453system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.84% # attempts to use FU when none available 454system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.84% # attempts to use FU when none available 455system.cpu.iq.fu_full::FloatMult 0 0.00% 18.84% # attempts to use FU when none available 456system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.84% # attempts to use FU when none available 457system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.84% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.84% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.84% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.84% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.84% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.84% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.84% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdMult 0 0.00% 18.84% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.84% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdShift 0 0.00% 18.84% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.84% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.84% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.84% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.84% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available 478system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available 479system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available |
| 475system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 476system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 477system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued | 480system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 481system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 482system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued |
| 478system.cpu.iq.FU_type_0::IntAlu 39037949 67.85% 67.86% # Type of FU issued 479system.cpu.iq.FU_type_0::IntMult 61847 0.11% 67.97% # Type of FU issued 480system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued 481system.cpu.iq.FU_type_0::FloatAdd 38375 0.07% 68.04% # Type of FU issued 482system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued 483system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued 484system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued 485system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.04% # Type of FU issued 486system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.04% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued 507system.cpu.iq.FU_type_0::MemRead 10709010 18.61% 86.66% # Type of FU issued 508system.cpu.iq.FU_type_0::MemWrite 6728743 11.69% 98.35% # Type of FU issued 509system.cpu.iq.FU_type_0::IprAccess 949030 1.65% 100.00% # Type of FU issued | 483system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued 484system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued 485system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued 486system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued 487system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued 488system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued 489system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued 490system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued 491system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued 512system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued 513system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued 514system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued |
| 510system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 515system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 511system.cpu.iq.FU_type_0::total 57535876 # Type of FU issued 512system.cpu.iq.rate 0.486545 # Inst issue rate 513system.cpu.iq.fu_busy_cnt 1130694 # FU busy when requested 514system.cpu.iq.fu_busy_rate 0.019652 # FU busy rate (busy events/executed inst) 515system.cpu.iq.int_inst_queue_reads 228371695 # Number of integer instruction queue reads 516system.cpu.iq.int_inst_queue_writes 67806986 # Number of integer instruction queue writes 517system.cpu.iq.int_inst_queue_wakeup_accesses 55854530 # Number of integer instruction queue wakeup accesses 518system.cpu.iq.fp_inst_queue_reads 714587 # Number of floating instruction queue reads 519system.cpu.iq.fp_inst_queue_writes 336328 # Number of floating instruction queue writes 520system.cpu.iq.fp_inst_queue_wakeup_accesses 329574 # Number of floating instruction queue wakeup accesses 521system.cpu.iq.int_alu_accesses 58275622 # Number of integer alu accesses 522system.cpu.iq.fp_alu_accesses 383662 # Number of floating point alu accesses 523system.cpu.iew.lsq.thread0.forwLoads 641458 # Number of loads that had data forwarded from stores | 516system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued 517system.cpu.iq.rate 0.469435 # Inst issue rate 518system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested 519system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) 520system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads 521system.cpu.iq.int_inst_queue_writes 67941522 # Number of integer instruction queue writes 522system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses 523system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads 524system.cpu.iq.fp_inst_queue_writes 334790 # Number of floating instruction queue writes 525system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses 526system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses 527system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses 528system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores |
| 524system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 529system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 525system.cpu.iew.lsq.thread0.squashedLoads 1338736 # Number of loads squashed 526system.cpu.iew.lsq.thread0.ignoredResponses 3932 # Number of memory responses ignored because the instruction is squashed 527system.cpu.iew.lsq.thread0.memOrderViolation 20392 # Number of memory ordering violations 528system.cpu.iew.lsq.thread0.squashedStores 579549 # Number of stores squashed | 530system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed 531system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed 532system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations 533system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed |
| 529system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 530system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 534system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 535system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 531system.cpu.iew.lsq.thread0.rescheduledLoads 18260 # Number of loads that were rescheduled 532system.cpu.iew.lsq.thread0.cacheBlocked 537508 # Number of times an access to memory failed due to the cache being blocked | 536system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled 537system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked |
| 533system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 538system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 534system.cpu.iew.iewSquashCycles 585466 # Number of cycles IEW is squashing 535system.cpu.iew.iewBlockCycles 44292826 # Number of cycles IEW is blocking 536system.cpu.iew.iewUnblockCycles 620223 # Number of cycles IEW is unblocking 537system.cpu.iew.iewDispatchedInsts 64391845 # Number of instructions dispatched to IQ 538system.cpu.iew.iewDispSquashedInsts 145304 # Number of squashed instructions skipped by dispatch 539system.cpu.iew.iewDispLoadInsts 10423192 # Number of dispatched load instructions 540system.cpu.iew.iewDispStoreInsts 6953251 # Number of dispatched store instructions 541system.cpu.iew.iewDispNonSpecInsts 1888969 # Number of dispatched non-speculative instructions 542system.cpu.iew.iewIQFullEvents 42563 # Number of times the IQ has become full, causing a stall 543system.cpu.iew.iewLSQFullEvents 374293 # Number of times the LSQ has become full, causing a stall 544system.cpu.iew.memOrderViolationEvents 20392 # Number of memory order violations 545system.cpu.iew.predictedTakenIncorrect 192990 # Number of branches that were predicted taken incorrectly 546system.cpu.iew.predictedNotTakenIncorrect 410068 # Number of branches that were predicted not taken incorrectly 547system.cpu.iew.branchMispredicts 603058 # Number of branch mispredicts detected at execute 548system.cpu.iew.iewExecutedInsts 56949005 # Number of executed instructions 549system.cpu.iew.iewExecLoadInsts 10367007 # Number of load instructions executed 550system.cpu.iew.iewExecSquashedInsts 586870 # Number of squashed instructions skipped in execute | 539system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing 540system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking 541system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking 542system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ 543system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch 544system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions 545system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions 546system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions 547system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall 548system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall 549system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations 550system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly 551system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly 552system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute 553system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions 554system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed 555system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute |
| 551system.cpu.iew.exec_swp 0 # number of swp insts executed | 556system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 552system.cpu.iew.exec_nop 3696550 # number of nop insts executed 553system.cpu.iew.exec_refs 17039818 # number of memory reference insts executed 554system.cpu.iew.exec_branches 8972525 # Number of branches executed 555system.cpu.iew.exec_stores 6672811 # Number of stores executed 556system.cpu.iew.exec_rate 0.481583 # Inst execution rate 557system.cpu.iew.wb_sent 56323297 # cumulative count of insts sent to commit 558system.cpu.iew.wb_count 56184104 # cumulative count of insts written-back 559system.cpu.iew.wb_producers 28889312 # num instructions producing a value 560system.cpu.iew.wb_consumers 40263081 # num instructions consuming a value | 557system.cpu.iew.exec_nop 3706829 # number of nop insts executed 558system.cpu.iew.exec_refs 17011176 # number of memory reference insts executed 559system.cpu.iew.exec_branches 8976912 # Number of branches executed 560system.cpu.iew.exec_stores 6673045 # Number of stores executed 561system.cpu.iew.exec_rate 0.464599 # Inst execution rate 562system.cpu.iew.wb_sent 56353404 # cumulative count of insts sent to commit 563system.cpu.iew.wb_count 56212492 # cumulative count of insts written-back 564system.cpu.iew.wb_producers 28792537 # num instructions producing a value 565system.cpu.iew.wb_consumers 40027235 # num instructions consuming a value |
| 561system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 566system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 562system.cpu.iew.wb_rate 0.475114 # insts written-back per cycle 563system.cpu.iew.wb_fanout 0.717514 # average fanout of values written-back | 567system.cpu.iew.wb_rate 0.458607 # insts written-back per cycle 568system.cpu.iew.wb_fanout 0.719324 # average fanout of values written-back |
| 564system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 569system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 565system.cpu.commit.commitSquashedInsts 8158001 # The number of squashed insts skipped by commit 566system.cpu.commit.commitNonSpecStalls 661179 # The number of times commit has been forced to stall to communicate backwards 567system.cpu.commit.branchMispredicts 549251 # The number of times a branch was mispredicted 568system.cpu.commit.committed_per_cycle::samples 111396128 # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::mean 0.503767 # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::stdev 1.456242 # Number of insts commited each cycle | 570system.cpu.commit.commitSquashedInsts 8228560 # The number of squashed insts skipped by commit 571system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards 572system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted 573system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle |
| 571system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 576system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 572system.cpu.commit.committed_per_cycle::0 91779533 82.39% 82.39% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::1 7802293 7.00% 89.39% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::2 4122327 3.70% 93.09% # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::3 2151634 1.93% 95.03% # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::4 1854051 1.66% 96.69% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::5 612708 0.55% 97.24% # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::6 470628 0.42% 97.66% # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::7 511278 0.46% 98.12% # Number of insts commited each cycle 580system.cpu.commit.committed_per_cycle::8 2091676 1.88% 100.00% # Number of insts commited each cycle | 577system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle 580system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle 581system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle 584system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle 585system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle |
| 581system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 586system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 584system.cpu.commit.committed_per_cycle::total 111396128 # Number of insts commited each cycle 585system.cpu.commit.committedInsts 56117715 # Number of instructions committed 586system.cpu.commit.committedOps 56117715 # Number of ops (including micro ops) committed | 589system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle 590system.cpu.commit.committedInsts 56123349 # Number of instructions committed 591system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed |
| 587system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 592system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 588system.cpu.commit.refs 15458158 # Number of memory references committed 589system.cpu.commit.loads 9084456 # Number of loads committed 590system.cpu.commit.membars 226347 # Number of memory barriers committed 591system.cpu.commit.branches 8434758 # Number of branches committed | 593system.cpu.commit.refs 15459994 # Number of memory references committed 594system.cpu.commit.loads 9085408 # Number of loads committed 595system.cpu.commit.membars 226308 # Number of memory barriers committed 596system.cpu.commit.branches 8435685 # Number of branches committed |
| 592system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. | 597system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. |
| 593system.cpu.commit.int_insts 51969244 # Number of committed integer instructions. 594system.cpu.commit.function_calls 739915 # Number of function calls committed. 595system.cpu.commit.op_class_0::No_OpClass 3195962 5.70% 5.70% # Class of committed instruction 596system.cpu.commit.op_class_0::IntAlu 36179881 64.47% 70.17% # Class of committed instruction 597system.cpu.commit.op_class_0::IntMult 60661 0.11% 70.27% # Class of committed instruction | 598system.cpu.commit.int_insts 51974864 # Number of committed integer instructions. 599system.cpu.commit.function_calls 740049 # Number of function calls committed. 600system.cpu.commit.op_class_0::No_OpClass 3196057 5.69% 5.69% # Class of committed instruction 601system.cpu.commit.op_class_0::IntAlu 36183700 64.47% 70.17% # Class of committed instruction 602system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.27% # Class of committed instruction |
| 598system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction 599system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction 600system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction 601system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction 602system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction 603system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 604system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 605system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 617system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 618system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 619system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 620system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 621system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 622system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 623system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 624system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction | 603system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction 604system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction 605system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction 606system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction 607system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction 608system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 609system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 622system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 623system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 624system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 625system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 626system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 627system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 628system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 629system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction |
| 625system.cpu.commit.op_class_0::MemRead 9310803 16.59% 86.94% # Class of committed instruction 626system.cpu.commit.op_class_0::MemWrite 6379655 11.37% 98.31% # Class of committed instruction 627system.cpu.commit.op_class_0::IprAccess 949030 1.69% 100.00% # Class of committed instruction | 630system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction 631system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction 632system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction |
| 628system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 633system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 629system.cpu.commit.op_class_0::total 56117715 # Class of committed instruction 630system.cpu.commit.bw_lim_events 2091676 # number cycles where commit BW limit reached | 634system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction 635system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached |
| 631system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 636system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 632system.cpu.rob.rob_reads 173330307 # The number of ROB reads 633system.cpu.rob.rob_writes 129976168 # The number of ROB writes 634system.cpu.timesIdled 574999 # Number of times that the entire CPU went into an idle state and unscheduled itself 635system.cpu.idleCycles 5429242 # Total number of cycles that the CPU has spent unscheduled due to idling 636system.cpu.quiesceCycles 3599836925 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 637system.cpu.committedInsts 52929026 # Number of Instructions Simulated 638system.cpu.committedOps 52929026 # Number of Ops (including micro ops) Simulated 639system.cpu.cpi 2.234197 # CPI: Cycles Per Instruction 640system.cpu.cpi_total 2.234197 # CPI: Total CPI of All Threads 641system.cpu.ipc 0.447588 # IPC: Instructions Per Cycle 642system.cpu.ipc_total 0.447588 # IPC: Total IPC of All Threads 643system.cpu.int_regfile_reads 74582639 # number of integer regfile reads 644system.cpu.int_regfile_writes 40531859 # number of integer regfile writes 645system.cpu.fp_regfile_reads 167323 # number of floating regfile reads 646system.cpu.fp_regfile_writes 167888 # number of floating regfile writes 647system.cpu.misc_regfile_reads 2030592 # number of misc regfile reads 648system.cpu.misc_regfile_writes 939419 # number of misc regfile writes 649system.cpu.dcache.tags.replacements 1404198 # number of replacements 650system.cpu.dcache.tags.tagsinuse 511.994647 # Cycle average of tags in use 651system.cpu.dcache.tags.total_refs 11876238 # Total number of references to valid blocks. 652system.cpu.dcache.tags.sampled_refs 1404710 # Sample count of references to valid blocks. 653system.cpu.dcache.tags.avg_refs 8.454584 # Average number of references to valid blocks. 654system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. 655system.cpu.dcache.tags.occ_blocks::cpu.data 511.994647 # Average occupied blocks per requestor 656system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 657system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy | 637system.cpu.rob.rob_reads 177593269 # The number of ROB reads 638system.cpu.rob.rob_writes 130137832 # The number of ROB writes 639system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself 640system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling 641system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 642system.cpu.committedInsts 52934565 # Number of Instructions Simulated 643system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated 644system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction 645system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads 646system.cpu.ipc 0.431864 # IPC: Instructions Per Cycle 647system.cpu.ipc_total 0.431864 # IPC: Total IPC of All Threads 648system.cpu.int_regfile_reads 74599299 # number of integer regfile reads 649system.cpu.int_regfile_writes 40560409 # number of integer regfile writes 650system.cpu.fp_regfile_reads 167171 # number of floating regfile reads 651system.cpu.fp_regfile_writes 167579 # number of floating regfile writes 652system.cpu.misc_regfile_reads 2029670 # number of misc regfile reads 653system.cpu.misc_regfile_writes 939349 # number of misc regfile writes 654system.cpu.dcache.tags.replacements 1403663 # number of replacements 655system.cpu.dcache.tags.tagsinuse 511.994456 # Cycle average of tags in use 656system.cpu.dcache.tags.total_refs 11858482 # Total number of references to valid blocks. 657system.cpu.dcache.tags.sampled_refs 1404175 # Sample count of references to valid blocks. 658system.cpu.dcache.tags.avg_refs 8.445160 # Average number of references to valid blocks. 659system.cpu.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. 660system.cpu.dcache.tags.occ_blocks::cpu.data 511.994456 # Average occupied blocks per requestor 661system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 662system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy |
| 658system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 659system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id | 663system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 664system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id |
| 660system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 661system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id | 665system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id 666system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id |
| 662system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 667system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 663system.cpu.dcache.tags.tag_accesses 63918355 # Number of tag accesses 664system.cpu.dcache.tags.data_accesses 63918355 # Number of data accesses 665system.cpu.dcache.ReadReq_hits::cpu.data 7286393 # number of ReadReq hits 666system.cpu.dcache.ReadReq_hits::total 7286393 # number of ReadReq hits 667system.cpu.dcache.WriteReq_hits::cpu.data 4187319 # number of WriteReq hits 668system.cpu.dcache.WriteReq_hits::total 4187319 # number of WriteReq hits 669system.cpu.dcache.LoadLockedReq_hits::cpu.data 186500 # number of LoadLockedReq hits 670system.cpu.dcache.LoadLockedReq_hits::total 186500 # number of LoadLockedReq hits 671system.cpu.dcache.StoreCondReq_hits::cpu.data 215720 # number of StoreCondReq hits 672system.cpu.dcache.StoreCondReq_hits::total 215720 # number of StoreCondReq hits 673system.cpu.dcache.demand_hits::cpu.data 11473712 # number of demand (read+write) hits 674system.cpu.dcache.demand_hits::total 11473712 # number of demand (read+write) hits 675system.cpu.dcache.overall_hits::cpu.data 11473712 # number of overall hits 676system.cpu.dcache.overall_hits::total 11473712 # number of overall hits 677system.cpu.dcache.ReadReq_misses::cpu.data 1773211 # number of ReadReq misses 678system.cpu.dcache.ReadReq_misses::total 1773211 # number of ReadReq misses 679system.cpu.dcache.WriteReq_misses::cpu.data 1955934 # number of WriteReq misses 680system.cpu.dcache.WriteReq_misses::total 1955934 # number of WriteReq misses 681system.cpu.dcache.LoadLockedReq_misses::cpu.data 23306 # number of LoadLockedReq misses 682system.cpu.dcache.LoadLockedReq_misses::total 23306 # number of LoadLockedReq misses 683system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses 684system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses 685system.cpu.dcache.demand_misses::cpu.data 3729145 # number of demand (read+write) misses 686system.cpu.dcache.demand_misses::total 3729145 # number of demand (read+write) misses 687system.cpu.dcache.overall_misses::cpu.data 3729145 # number of overall misses 688system.cpu.dcache.overall_misses::total 3729145 # number of overall misses 689system.cpu.dcache.ReadReq_miss_latency::cpu.data 39410540501 # number of ReadReq miss cycles 690system.cpu.dcache.ReadReq_miss_latency::total 39410540501 # number of ReadReq miss cycles 691system.cpu.dcache.WriteReq_miss_latency::cpu.data 77932908678 # number of WriteReq miss cycles 692system.cpu.dcache.WriteReq_miss_latency::total 77932908678 # number of WriteReq miss cycles 693system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 363692999 # number of LoadLockedReq miss cycles 694system.cpu.dcache.LoadLockedReq_miss_latency::total 363692999 # number of LoadLockedReq miss cycles 695system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 466008 # number of StoreCondReq miss cycles 696system.cpu.dcache.StoreCondReq_miss_latency::total 466008 # number of StoreCondReq miss cycles 697system.cpu.dcache.demand_miss_latency::cpu.data 117343449179 # number of demand (read+write) miss cycles 698system.cpu.dcache.demand_miss_latency::total 117343449179 # number of demand (read+write) miss cycles 699system.cpu.dcache.overall_miss_latency::cpu.data 117343449179 # number of overall miss cycles 700system.cpu.dcache.overall_miss_latency::total 117343449179 # number of overall miss cycles 701system.cpu.dcache.ReadReq_accesses::cpu.data 9059604 # number of ReadReq accesses(hits+misses) 702system.cpu.dcache.ReadReq_accesses::total 9059604 # number of ReadReq accesses(hits+misses) 703system.cpu.dcache.WriteReq_accesses::cpu.data 6143253 # number of WriteReq accesses(hits+misses) 704system.cpu.dcache.WriteReq_accesses::total 6143253 # number of WriteReq accesses(hits+misses) 705system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209806 # number of LoadLockedReq accesses(hits+misses) 706system.cpu.dcache.LoadLockedReq_accesses::total 209806 # number of LoadLockedReq accesses(hits+misses) 707system.cpu.dcache.StoreCondReq_accesses::cpu.data 215748 # number of StoreCondReq accesses(hits+misses) 708system.cpu.dcache.StoreCondReq_accesses::total 215748 # number of StoreCondReq accesses(hits+misses) 709system.cpu.dcache.demand_accesses::cpu.data 15202857 # number of demand (read+write) accesses 710system.cpu.dcache.demand_accesses::total 15202857 # number of demand (read+write) accesses 711system.cpu.dcache.overall_accesses::cpu.data 15202857 # number of overall (read+write) accesses 712system.cpu.dcache.overall_accesses::total 15202857 # number of overall (read+write) accesses 713system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195727 # miss rate for ReadReq accesses 714system.cpu.dcache.ReadReq_miss_rate::total 0.195727 # miss rate for ReadReq accesses 715system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318387 # miss rate for WriteReq accesses 716system.cpu.dcache.WriteReq_miss_rate::total 0.318387 # miss rate for WriteReq accesses 717system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111084 # miss rate for LoadLockedReq accesses 718system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111084 # miss rate for LoadLockedReq accesses 719system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses 720system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses 721system.cpu.dcache.demand_miss_rate::cpu.data 0.245292 # miss rate for demand accesses 722system.cpu.dcache.demand_miss_rate::total 0.245292 # miss rate for demand accesses 723system.cpu.dcache.overall_miss_rate::cpu.data 0.245292 # miss rate for overall accesses 724system.cpu.dcache.overall_miss_rate::total 0.245292 # miss rate for overall accesses 725system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.522231 # average ReadReq miss latency 726system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.522231 # average ReadReq miss latency 727system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39844.344788 # average WriteReq miss latency 728system.cpu.dcache.WriteReq_avg_miss_latency::total 39844.344788 # average WriteReq miss latency 729system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15605.123101 # average LoadLockedReq miss latency 730system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15605.123101 # average LoadLockedReq miss latency 731system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16643.142857 # average StoreCondReq miss latency 732system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16643.142857 # average StoreCondReq miss latency 733system.cpu.dcache.demand_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency 734system.cpu.dcache.demand_avg_miss_latency::total 31466.582602 # average overall miss latency 735system.cpu.dcache.overall_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency 736system.cpu.dcache.overall_avg_miss_latency::total 31466.582602 # average overall miss latency 737system.cpu.dcache.blocked_cycles::no_mshrs 3975824 # number of cycles access was blocked 738system.cpu.dcache.blocked_cycles::no_targets 1887 # number of cycles access was blocked 739system.cpu.dcache.blocked::no_mshrs 179816 # number of cycles access was blocked | 668system.cpu.dcache.tags.tag_accesses 63936372 # Number of tag accesses 669system.cpu.dcache.tags.data_accesses 63936372 # Number of data accesses 670system.cpu.dcache.ReadReq_hits::cpu.data 7267066 # number of ReadReq hits 671system.cpu.dcache.ReadReq_hits::total 7267066 # number of ReadReq hits 672system.cpu.dcache.WriteReq_hits::cpu.data 4189300 # number of WriteReq hits 673system.cpu.dcache.WriteReq_hits::total 4189300 # number of WriteReq hits 674system.cpu.dcache.LoadLockedReq_hits::cpu.data 186111 # number of LoadLockedReq hits 675system.cpu.dcache.LoadLockedReq_hits::total 186111 # number of LoadLockedReq hits 676system.cpu.dcache.StoreCondReq_hits::cpu.data 215710 # number of StoreCondReq hits 677system.cpu.dcache.StoreCondReq_hits::total 215710 # number of StoreCondReq hits 678system.cpu.dcache.demand_hits::cpu.data 11456366 # number of demand (read+write) hits 679system.cpu.dcache.demand_hits::total 11456366 # number of demand (read+write) hits 680system.cpu.dcache.overall_hits::cpu.data 11456366 # number of overall hits 681system.cpu.dcache.overall_hits::total 11456366 # number of overall hits 682system.cpu.dcache.ReadReq_misses::cpu.data 1796718 # number of ReadReq misses 683system.cpu.dcache.ReadReq_misses::total 1796718 # number of ReadReq misses 684system.cpu.dcache.WriteReq_misses::cpu.data 1954848 # number of WriteReq misses 685system.cpu.dcache.WriteReq_misses::total 1954848 # number of WriteReq misses 686system.cpu.dcache.LoadLockedReq_misses::cpu.data 23269 # number of LoadLockedReq misses 687system.cpu.dcache.LoadLockedReq_misses::total 23269 # number of LoadLockedReq misses 688system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses 689system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses 690system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses 691system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses 692system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses 693system.cpu.dcache.overall_misses::total 3751566 # number of overall misses 694system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles 695system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles 696system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles 697system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles 698system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles 699system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles 700system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles 701system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles 702system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles 703system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles 704system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles 705system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles 706system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) 707system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) 708system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) 709system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses) 710system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses) 711system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses) 712system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses) 713system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses) 714system.cpu.dcache.demand_accesses::cpu.data 15207932 # number of demand (read+write) accesses 715system.cpu.dcache.demand_accesses::total 15207932 # number of demand (read+write) accesses 716system.cpu.dcache.overall_accesses::cpu.data 15207932 # number of overall (read+write) accesses 717system.cpu.dcache.overall_accesses::total 15207932 # number of overall (read+write) accesses 718system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198230 # miss rate for ReadReq accesses 719system.cpu.dcache.ReadReq_miss_rate::total 0.198230 # miss rate for ReadReq accesses 720system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318164 # miss rate for WriteReq accesses 721system.cpu.dcache.WriteReq_miss_rate::total 0.318164 # miss rate for WriteReq accesses 722system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111133 # miss rate for LoadLockedReq accesses 723system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111133 # miss rate for LoadLockedReq accesses 724system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses 725system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses 726system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses 727system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses 728system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses 729system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses 730system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency 731system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency 732system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency 733system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency 734system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency 735system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency 736system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency 737system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency 738system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency 739system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency 740system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency 741system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency 742system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked 743system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked 744system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked |
| 740system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked | 745system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked |
| 741system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.110513 # average number of cycles each access was blocked 742system.cpu.dcache.avg_blocked_cycles::no_targets 82.043478 # average number of cycles each access was blocked | 746system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked 747system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked |
| 743system.cpu.dcache.fast_writes 0 # number of fast writes performed 744system.cpu.dcache.cache_copies 0 # number of cache copies performed | 748system.cpu.dcache.fast_writes 0 # number of fast writes performed 749system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 745system.cpu.dcache.writebacks::writebacks 842396 # number of writebacks 746system.cpu.dcache.writebacks::total 842396 # number of writebacks 747system.cpu.dcache.ReadReq_mshr_hits::cpu.data 677447 # number of ReadReq MSHR hits 748system.cpu.dcache.ReadReq_mshr_hits::total 677447 # number of ReadReq MSHR hits 749system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664842 # number of WriteReq MSHR hits 750system.cpu.dcache.WriteReq_mshr_hits::total 1664842 # number of WriteReq MSHR hits 751system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5278 # number of LoadLockedReq MSHR hits 752system.cpu.dcache.LoadLockedReq_mshr_hits::total 5278 # number of LoadLockedReq MSHR hits 753system.cpu.dcache.demand_mshr_hits::cpu.data 2342289 # number of demand (read+write) MSHR hits 754system.cpu.dcache.demand_mshr_hits::total 2342289 # number of demand (read+write) MSHR hits 755system.cpu.dcache.overall_mshr_hits::cpu.data 2342289 # number of overall MSHR hits 756system.cpu.dcache.overall_mshr_hits::total 2342289 # number of overall MSHR hits 757system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095764 # number of ReadReq MSHR misses 758system.cpu.dcache.ReadReq_mshr_misses::total 1095764 # number of ReadReq MSHR misses 759system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291092 # number of WriteReq MSHR misses 760system.cpu.dcache.WriteReq_mshr_misses::total 291092 # number of WriteReq MSHR misses 761system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18028 # number of LoadLockedReq MSHR misses 762system.cpu.dcache.LoadLockedReq_mshr_misses::total 18028 # number of LoadLockedReq MSHR misses 763system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses 764system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses 765system.cpu.dcache.demand_mshr_misses::cpu.data 1386856 # number of demand (read+write) MSHR misses 766system.cpu.dcache.demand_mshr_misses::total 1386856 # number of demand (read+write) MSHR misses 767system.cpu.dcache.overall_mshr_misses::cpu.data 1386856 # number of overall MSHR misses 768system.cpu.dcache.overall_mshr_misses::total 1386856 # number of overall MSHR misses 769system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27504145773 # number of ReadReq MSHR miss cycles 770system.cpu.dcache.ReadReq_mshr_miss_latency::total 27504145773 # number of ReadReq MSHR miss cycles 771system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11747551273 # number of WriteReq MSHR miss cycles 772system.cpu.dcache.WriteReq_mshr_miss_latency::total 11747551273 # number of WriteReq MSHR miss cycles 773system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205106501 # number of LoadLockedReq MSHR miss cycles 774system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205106501 # number of LoadLockedReq MSHR miss cycles 775system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 409992 # number of StoreCondReq MSHR miss cycles 776system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 409992 # number of StoreCondReq MSHR miss cycles 777system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39251697046 # number of demand (read+write) MSHR miss cycles 778system.cpu.dcache.demand_mshr_miss_latency::total 39251697046 # number of demand (read+write) MSHR miss cycles 779system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39251697046 # number of overall MSHR miss cycles 780system.cpu.dcache.overall_mshr_miss_latency::total 39251697046 # number of overall MSHR miss cycles 781system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423712500 # number of ReadReq MSHR uncacheable cycles 782system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423712500 # number of ReadReq MSHR uncacheable cycles 783system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999632498 # number of WriteReq MSHR uncacheable cycles 784system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999632498 # number of WriteReq MSHR uncacheable cycles 785system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423344998 # number of overall MSHR uncacheable cycles 786system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423344998 # number of overall MSHR uncacheable cycles 787system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120951 # mshr miss rate for ReadReq accesses 788system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120951 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047384 # mshr miss rate for WriteReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047384 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085927 # mshr miss rate for LoadLockedReq accesses 792system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085927 # mshr miss rate for LoadLockedReq accesses 793system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses 794system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses 795system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for demand accesses 796system.cpu.dcache.demand_mshr_miss_rate::total 0.091223 # mshr miss rate for demand accesses 797system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for overall accesses 798system.cpu.dcache.overall_mshr_miss_rate::total 0.091223 # mshr miss rate for overall accesses 799system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25100.428352 # average ReadReq mshr miss latency 800system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25100.428352 # average ReadReq mshr miss latency 801system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40356.833142 # average WriteReq mshr miss latency 802system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40356.833142 # average WriteReq mshr miss latency 803system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.107888 # average LoadLockedReq mshr miss latency 804system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.107888 # average LoadLockedReq mshr miss latency 805system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14642.571429 # average StoreCondReq mshr miss latency 806system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14642.571429 # average StoreCondReq mshr miss latency 807system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency 808system.cpu.dcache.demand_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency 809system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency 810system.cpu.dcache.overall_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency | 750system.cpu.dcache.writebacks::writebacks 842087 # number of writebacks 751system.cpu.dcache.writebacks::total 842087 # number of writebacks 752system.cpu.dcache.ReadReq_mshr_hits::cpu.data 701160 # number of ReadReq MSHR hits 753system.cpu.dcache.ReadReq_mshr_hits::total 701160 # number of ReadReq MSHR hits 754system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664055 # number of WriteReq MSHR hits 755system.cpu.dcache.WriteReq_mshr_hits::total 1664055 # number of WriteReq MSHR hits 756system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5272 # number of LoadLockedReq MSHR hits 757system.cpu.dcache.LoadLockedReq_mshr_hits::total 5272 # number of LoadLockedReq MSHR hits 758system.cpu.dcache.demand_mshr_hits::cpu.data 2365215 # number of demand (read+write) MSHR hits 759system.cpu.dcache.demand_mshr_hits::total 2365215 # number of demand (read+write) MSHR hits 760system.cpu.dcache.overall_mshr_hits::cpu.data 2365215 # number of overall MSHR hits 761system.cpu.dcache.overall_mshr_hits::total 2365215 # number of overall MSHR hits 762system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095558 # number of ReadReq MSHR misses 763system.cpu.dcache.ReadReq_mshr_misses::total 1095558 # number of ReadReq MSHR misses 764system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290793 # number of WriteReq MSHR misses 765system.cpu.dcache.WriteReq_mshr_misses::total 290793 # number of WriteReq MSHR misses 766system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17997 # number of LoadLockedReq MSHR misses 767system.cpu.dcache.LoadLockedReq_mshr_misses::total 17997 # number of LoadLockedReq MSHR misses 768system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 27 # number of StoreCondReq MSHR misses 769system.cpu.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses 770system.cpu.dcache.demand_mshr_misses::cpu.data 1386351 # number of demand (read+write) MSHR misses 771system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses 772system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses 773system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses 774system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles 775system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles 776system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482487876 # number of WriteReq MSHR miss cycles 777system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482487876 # number of WriteReq MSHR miss cycles 778system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles 779system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles 780system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles 781system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles 782system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479420899 # number of demand (read+write) MSHR miss cycles 783system.cpu.dcache.demand_mshr_miss_latency::total 42479420899 # number of demand (read+write) MSHR miss cycles 784system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479420899 # number of overall MSHR miss cycles 785system.cpu.dcache.overall_mshr_miss_latency::total 42479420899 # number of overall MSHR miss cycles 786system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles 787system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles 788system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles 789system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011966000 # number of WriteReq MSHR uncacheable cycles 790system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3445672500 # number of overall MSHR uncacheable cycles 791system.cpu.dcache.overall_mshr_uncacheable_latency::total 3445672500 # number of overall MSHR uncacheable cycles 792system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for ReadReq accesses 793system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120872 # mshr miss rate for ReadReq accesses 794system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047328 # mshr miss rate for WriteReq accesses 795system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047328 # mshr miss rate for WriteReq accesses 796system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085954 # mshr miss rate for LoadLockedReq accesses 797system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085954 # mshr miss rate for LoadLockedReq accesses 798system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000125 # mshr miss rate for StoreCondReq accesses 799system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000125 # mshr miss rate for StoreCondReq accesses 800system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for demand accesses 801system.cpu.dcache.demand_mshr_miss_rate::total 0.091160 # mshr miss rate for demand accesses 802system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for overall accesses 803system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses 804system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency 805system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency 806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.682104 # average WriteReq mshr miss latency 807system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.682104 # average WriteReq mshr miss latency 808system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency 809system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency 810system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency 811system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency 812system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency 813system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency 814system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency 815system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency |
| 811system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 812system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 813system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 814system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 815system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 816system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 817system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 816system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 817system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 818system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 819system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 820system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 821system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 822system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 818system.cpu.icache.tags.replacements 1034381 # number of replacements 819system.cpu.icache.tags.tagsinuse 509.395054 # Cycle average of tags in use 820system.cpu.icache.tags.total_refs 7933874 # Total number of references to valid blocks. 821system.cpu.icache.tags.sampled_refs 1034889 # Sample count of references to valid blocks. 822system.cpu.icache.tags.avg_refs 7.666401 # Average number of references to valid blocks. 823system.cpu.icache.tags.warmup_cycle 26421984250 # Cycle when the warmup percentage was hit. 824system.cpu.icache.tags.occ_blocks::cpu.inst 509.395054 # Average occupied blocks per requestor 825system.cpu.icache.tags.occ_percent::cpu.inst 0.994912 # Average percentage of cache occupancy 826system.cpu.icache.tags.occ_percent::total 0.994912 # Average percentage of cache occupancy | 823system.cpu.icache.tags.replacements 1032757 # number of replacements 824system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use 825system.cpu.icache.tags.total_refs 7965141 # Total number of references to valid blocks. 826system.cpu.icache.tags.sampled_refs 1033265 # Sample count of references to valid blocks. 827system.cpu.icache.tags.avg_refs 7.708711 # Average number of references to valid blocks. 828system.cpu.icache.tags.warmup_cycle 28360334250 # Cycle when the warmup percentage was hit. 829system.cpu.icache.tags.occ_blocks::cpu.inst 509.197301 # Average occupied blocks per requestor 830system.cpu.icache.tags.occ_percent::cpu.inst 0.994526 # Average percentage of cache occupancy 831system.cpu.icache.tags.occ_percent::total 0.994526 # Average percentage of cache occupancy |
| 827system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id | 832system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id |
| 828system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 829system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id 830system.cpu.icache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id | 833system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 834system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id 835system.cpu.icache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id |
| 831system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id | 836system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id |
| 832system.cpu.icache.tags.tag_accesses 10056110 # Number of tag accesses 833system.cpu.icache.tags.data_accesses 10056110 # Number of data accesses 834system.cpu.icache.ReadReq_hits::cpu.inst 7933875 # number of ReadReq hits 835system.cpu.icache.ReadReq_hits::total 7933875 # number of ReadReq hits 836system.cpu.icache.demand_hits::cpu.inst 7933875 # number of demand (read+write) hits 837system.cpu.icache.demand_hits::total 7933875 # number of demand (read+write) hits 838system.cpu.icache.overall_hits::cpu.inst 7933875 # number of overall hits 839system.cpu.icache.overall_hits::total 7933875 # number of overall hits 840system.cpu.icache.ReadReq_misses::cpu.inst 1087081 # number of ReadReq misses 841system.cpu.icache.ReadReq_misses::total 1087081 # number of ReadReq misses 842system.cpu.icache.demand_misses::cpu.inst 1087081 # number of demand (read+write) misses 843system.cpu.icache.demand_misses::total 1087081 # number of demand (read+write) misses 844system.cpu.icache.overall_misses::cpu.inst 1087081 # number of overall misses 845system.cpu.icache.overall_misses::total 1087081 # number of overall misses 846system.cpu.icache.ReadReq_miss_latency::cpu.inst 15110067823 # number of ReadReq miss cycles 847system.cpu.icache.ReadReq_miss_latency::total 15110067823 # number of ReadReq miss cycles 848system.cpu.icache.demand_miss_latency::cpu.inst 15110067823 # number of demand (read+write) miss cycles 849system.cpu.icache.demand_miss_latency::total 15110067823 # number of demand (read+write) miss cycles 850system.cpu.icache.overall_miss_latency::cpu.inst 15110067823 # number of overall miss cycles 851system.cpu.icache.overall_miss_latency::total 15110067823 # number of overall miss cycles 852system.cpu.icache.ReadReq_accesses::cpu.inst 9020956 # number of ReadReq accesses(hits+misses) 853system.cpu.icache.ReadReq_accesses::total 9020956 # number of ReadReq accesses(hits+misses) 854system.cpu.icache.demand_accesses::cpu.inst 9020956 # number of demand (read+write) accesses 855system.cpu.icache.demand_accesses::total 9020956 # number of demand (read+write) accesses 856system.cpu.icache.overall_accesses::cpu.inst 9020956 # number of overall (read+write) accesses 857system.cpu.icache.overall_accesses::total 9020956 # number of overall (read+write) accesses 858system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120506 # miss rate for ReadReq accesses 859system.cpu.icache.ReadReq_miss_rate::total 0.120506 # miss rate for ReadReq accesses 860system.cpu.icache.demand_miss_rate::cpu.inst 0.120506 # miss rate for demand accesses 861system.cpu.icache.demand_miss_rate::total 0.120506 # miss rate for demand accesses 862system.cpu.icache.overall_miss_rate::cpu.inst 0.120506 # miss rate for overall accesses 863system.cpu.icache.overall_miss_rate::total 0.120506 # miss rate for overall accesses 864system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13899.670607 # average ReadReq miss latency 865system.cpu.icache.ReadReq_avg_miss_latency::total 13899.670607 # average ReadReq miss latency 866system.cpu.icache.demand_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency 867system.cpu.icache.demand_avg_miss_latency::total 13899.670607 # average overall miss latency 868system.cpu.icache.overall_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency 869system.cpu.icache.overall_avg_miss_latency::total 13899.670607 # average overall miss latency 870system.cpu.icache.blocked_cycles::no_mshrs 3991 # number of cycles access was blocked | 837system.cpu.icache.tags.tag_accesses 10084699 # Number of tag accesses 838system.cpu.icache.tags.data_accesses 10084699 # Number of data accesses 839system.cpu.icache.ReadReq_hits::cpu.inst 7965142 # number of ReadReq hits 840system.cpu.icache.ReadReq_hits::total 7965142 # number of ReadReq hits 841system.cpu.icache.demand_hits::cpu.inst 7965142 # number of demand (read+write) hits 842system.cpu.icache.demand_hits::total 7965142 # number of demand (read+write) hits 843system.cpu.icache.overall_hits::cpu.inst 7965142 # number of overall hits 844system.cpu.icache.overall_hits::total 7965142 # number of overall hits 845system.cpu.icache.ReadReq_misses::cpu.inst 1086038 # number of ReadReq misses 846system.cpu.icache.ReadReq_misses::total 1086038 # number of ReadReq misses 847system.cpu.icache.demand_misses::cpu.inst 1086038 # number of demand (read+write) misses 848system.cpu.icache.demand_misses::total 1086038 # number of demand (read+write) misses 849system.cpu.icache.overall_misses::cpu.inst 1086038 # number of overall misses 850system.cpu.icache.overall_misses::total 1086038 # number of overall misses 851system.cpu.icache.ReadReq_miss_latency::cpu.inst 15222356868 # number of ReadReq miss cycles 852system.cpu.icache.ReadReq_miss_latency::total 15222356868 # number of ReadReq miss cycles 853system.cpu.icache.demand_miss_latency::cpu.inst 15222356868 # number of demand (read+write) miss cycles 854system.cpu.icache.demand_miss_latency::total 15222356868 # number of demand (read+write) miss cycles 855system.cpu.icache.overall_miss_latency::cpu.inst 15222356868 # number of overall miss cycles 856system.cpu.icache.overall_miss_latency::total 15222356868 # number of overall miss cycles 857system.cpu.icache.ReadReq_accesses::cpu.inst 9051180 # number of ReadReq accesses(hits+misses) 858system.cpu.icache.ReadReq_accesses::total 9051180 # number of ReadReq accesses(hits+misses) 859system.cpu.icache.demand_accesses::cpu.inst 9051180 # number of demand (read+write) accesses 860system.cpu.icache.demand_accesses::total 9051180 # number of demand (read+write) accesses 861system.cpu.icache.overall_accesses::cpu.inst 9051180 # number of overall (read+write) accesses 862system.cpu.icache.overall_accesses::total 9051180 # number of overall (read+write) accesses 863system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119989 # miss rate for ReadReq accesses 864system.cpu.icache.ReadReq_miss_rate::total 0.119989 # miss rate for ReadReq accesses 865system.cpu.icache.demand_miss_rate::cpu.inst 0.119989 # miss rate for demand accesses 866system.cpu.icache.demand_miss_rate::total 0.119989 # miss rate for demand accesses 867system.cpu.icache.overall_miss_rate::cpu.inst 0.119989 # miss rate for overall accesses 868system.cpu.icache.overall_miss_rate::total 0.119989 # miss rate for overall accesses 869system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.412748 # average ReadReq miss latency 870system.cpu.icache.ReadReq_avg_miss_latency::total 14016.412748 # average ReadReq miss latency 871system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency 872system.cpu.icache.demand_avg_miss_latency::total 14016.412748 # average overall miss latency 873system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency 874system.cpu.icache.overall_avg_miss_latency::total 14016.412748 # average overall miss latency 875system.cpu.icache.blocked_cycles::no_mshrs 5848 # number of cycles access was blocked |
| 871system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 876system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 872system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked | 877system.cpu.icache.blocked::no_mshrs 208 # number of cycles access was blocked |
| 873system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 878system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 874system.cpu.icache.avg_blocked_cycles::no_mshrs 21.808743 # average number of cycles each access was blocked | 879system.cpu.icache.avg_blocked_cycles::no_mshrs 28.115385 # average number of cycles each access was blocked |
| 875system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 876system.cpu.icache.fast_writes 0 # number of fast writes performed 877system.cpu.icache.cache_copies 0 # number of cache copies performed | 880system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 881system.cpu.icache.fast_writes 0 # number of fast writes performed 882system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 878system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51927 # number of ReadReq MSHR hits 879system.cpu.icache.ReadReq_mshr_hits::total 51927 # number of ReadReq MSHR hits 880system.cpu.icache.demand_mshr_hits::cpu.inst 51927 # number of demand (read+write) MSHR hits 881system.cpu.icache.demand_mshr_hits::total 51927 # number of demand (read+write) MSHR hits 882system.cpu.icache.overall_mshr_hits::cpu.inst 51927 # number of overall MSHR hits 883system.cpu.icache.overall_mshr_hits::total 51927 # number of overall MSHR hits 884system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035154 # number of ReadReq MSHR misses 885system.cpu.icache.ReadReq_mshr_misses::total 1035154 # number of ReadReq MSHR misses 886system.cpu.icache.demand_mshr_misses::cpu.inst 1035154 # number of demand (read+write) MSHR misses 887system.cpu.icache.demand_mshr_misses::total 1035154 # number of demand (read+write) MSHR misses 888system.cpu.icache.overall_mshr_misses::cpu.inst 1035154 # number of overall MSHR misses 889system.cpu.icache.overall_mshr_misses::total 1035154 # number of overall MSHR misses 890system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12419429847 # number of ReadReq MSHR miss cycles 891system.cpu.icache.ReadReq_mshr_miss_latency::total 12419429847 # number of ReadReq MSHR miss cycles 892system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12419429847 # number of demand (read+write) MSHR miss cycles 893system.cpu.icache.demand_mshr_miss_latency::total 12419429847 # number of demand (read+write) MSHR miss cycles 894system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12419429847 # number of overall MSHR miss cycles 895system.cpu.icache.overall_mshr_miss_latency::total 12419429847 # number of overall MSHR miss cycles 896system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for ReadReq accesses 897system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114750 # mshr miss rate for ReadReq accesses 898system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for demand accesses 899system.cpu.icache.demand_mshr_miss_rate::total 0.114750 # mshr miss rate for demand accesses 900system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for overall accesses 901system.cpu.icache.overall_mshr_miss_rate::total 0.114750 # mshr miss rate for overall accesses 902system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11997.663968 # average ReadReq mshr miss latency 903system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11997.663968 # average ReadReq mshr miss latency 904system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency 905system.cpu.icache.demand_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency 906system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency 907system.cpu.icache.overall_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency | 883system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52519 # number of ReadReq MSHR hits 884system.cpu.icache.ReadReq_mshr_hits::total 52519 # number of ReadReq MSHR hits 885system.cpu.icache.demand_mshr_hits::cpu.inst 52519 # number of demand (read+write) MSHR hits 886system.cpu.icache.demand_mshr_hits::total 52519 # number of demand (read+write) MSHR hits 887system.cpu.icache.overall_mshr_hits::cpu.inst 52519 # number of overall MSHR hits 888system.cpu.icache.overall_mshr_hits::total 52519 # number of overall MSHR hits 889system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1033519 # number of ReadReq MSHR misses 890system.cpu.icache.ReadReq_mshr_misses::total 1033519 # number of ReadReq MSHR misses 891system.cpu.icache.demand_mshr_misses::cpu.inst 1033519 # number of demand (read+write) MSHR misses 892system.cpu.icache.demand_mshr_misses::total 1033519 # number of demand (read+write) MSHR misses 893system.cpu.icache.overall_mshr_misses::cpu.inst 1033519 # number of overall MSHR misses 894system.cpu.icache.overall_mshr_misses::total 1033519 # number of overall MSHR misses 895system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13013904297 # number of ReadReq MSHR miss cycles 896system.cpu.icache.ReadReq_mshr_miss_latency::total 13013904297 # number of ReadReq MSHR miss cycles 897system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13013904297 # number of demand (read+write) MSHR miss cycles 898system.cpu.icache.demand_mshr_miss_latency::total 13013904297 # number of demand (read+write) MSHR miss cycles 899system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13013904297 # number of overall MSHR miss cycles 900system.cpu.icache.overall_mshr_miss_latency::total 13013904297 # number of overall MSHR miss cycles 901system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for ReadReq accesses 902system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114186 # mshr miss rate for ReadReq accesses 903system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for demand accesses 904system.cpu.icache.demand_mshr_miss_rate::total 0.114186 # mshr miss rate for demand accesses 905system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for overall accesses 906system.cpu.icache.overall_mshr_miss_rate::total 0.114186 # mshr miss rate for overall accesses 907system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12591.838464 # average ReadReq mshr miss latency 908system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12591.838464 # average ReadReq mshr miss latency 909system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency 910system.cpu.icache.demand_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency 911system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency 912system.cpu.icache.overall_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency |
| 908system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 909system.cpu.l2cache.tags.replacements 338332 # number of replacements | 913system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 914system.cpu.l2cache.tags.replacements 338332 # number of replacements |
| 910system.cpu.l2cache.tags.tagsinuse 65337.269998 # Cycle average of tags in use 911system.cpu.l2cache.tags.total_refs 2574624 # Total number of references to valid blocks. 912system.cpu.l2cache.tags.sampled_refs 403501 # Sample count of references to valid blocks. 913system.cpu.l2cache.tags.avg_refs 6.380713 # Average number of references to valid blocks. 914system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. 915system.cpu.l2cache.tags.occ_blocks::writebacks 53714.137748 # Average occupied blocks per requestor 916system.cpu.l2cache.tags.occ_blocks::cpu.inst 5350.111230 # Average occupied blocks per requestor 917system.cpu.l2cache.tags.occ_blocks::cpu.data 6273.021020 # Average occupied blocks per requestor 918system.cpu.l2cache.tags.occ_percent::writebacks 0.819613 # Average percentage of cache occupancy 919system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081636 # Average percentage of cache occupancy 920system.cpu.l2cache.tags.occ_percent::cpu.data 0.095719 # Average percentage of cache occupancy 921system.cpu.l2cache.tags.occ_percent::total 0.996968 # Average percentage of cache occupancy 922system.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id 923system.cpu.l2cache.tags.age_task_id_blocks_1024::0 498 # Occupied blocks per task id 924system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3501 # Occupied blocks per task id 925system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id 926system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id 927system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id 928system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id 929system.cpu.l2cache.tags.tag_accesses 26963891 # Number of tag accesses 930system.cpu.l2cache.tags.data_accesses 26963891 # Number of data accesses 931system.cpu.l2cache.ReadReq_hits::cpu.inst 1019836 # number of ReadReq hits 932system.cpu.l2cache.ReadReq_hits::cpu.data 829079 # number of ReadReq hits 933system.cpu.l2cache.ReadReq_hits::total 1848915 # number of ReadReq hits 934system.cpu.l2cache.Writeback_hits::writebacks 842396 # number of Writeback hits 935system.cpu.l2cache.Writeback_hits::total 842396 # number of Writeback hits | 915system.cpu.l2cache.tags.tagsinuse 65331.413764 # Cycle average of tags in use 916system.cpu.l2cache.tags.total_refs 2572439 # Total number of references to valid blocks. 917system.cpu.l2cache.tags.sampled_refs 403497 # Sample count of references to valid blocks. 918system.cpu.l2cache.tags.avg_refs 6.375361 # Average number of references to valid blocks. 919system.cpu.l2cache.tags.warmup_cycle 5986676750 # Cycle when the warmup percentage was hit. 920system.cpu.l2cache.tags.occ_blocks::writebacks 53648.492013 # Average occupied blocks per requestor 921system.cpu.l2cache.tags.occ_blocks::cpu.inst 5347.510273 # Average occupied blocks per requestor 922system.cpu.l2cache.tags.occ_blocks::cpu.data 6335.411477 # Average occupied blocks per requestor 923system.cpu.l2cache.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy 924system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081597 # Average percentage of cache occupancy 925system.cpu.l2cache.tags.occ_percent::cpu.data 0.096671 # Average percentage of cache occupancy 926system.cpu.l2cache.tags.occ_percent::total 0.996878 # Average percentage of cache occupancy 927system.cpu.l2cache.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id 928system.cpu.l2cache.tags.age_task_id_blocks_1024::0 491 # Occupied blocks per task id 929system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id 930system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id 931system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2403 # Occupied blocks per task id 932system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55444 # Occupied blocks per task id 933system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id 934system.cpu.l2cache.tags.tag_accesses 26943938 # Number of tag accesses 935system.cpu.l2cache.tags.data_accesses 26943938 # Number of data accesses 936system.cpu.l2cache.ReadReq_hits::cpu.inst 1018225 # number of ReadReq hits 937system.cpu.l2cache.ReadReq_hits::cpu.data 828726 # number of ReadReq hits 938system.cpu.l2cache.ReadReq_hits::total 1846951 # number of ReadReq hits 939system.cpu.l2cache.Writeback_hits::writebacks 842087 # number of Writeback hits 940system.cpu.l2cache.Writeback_hits::total 842087 # number of Writeback hits |
| 936system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 937system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits | 941system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 942system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits |
| 938system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 20 # number of SCUpgradeReq hits 939system.cpu.l2cache.SCUpgradeReq_hits::total 20 # number of SCUpgradeReq hits 940system.cpu.l2cache.ReadExReq_hits::cpu.data 186519 # number of ReadExReq hits 941system.cpu.l2cache.ReadExReq_hits::total 186519 # number of ReadExReq hits 942system.cpu.l2cache.demand_hits::cpu.inst 1019836 # number of demand (read+write) hits 943system.cpu.l2cache.demand_hits::cpu.data 1015598 # number of demand (read+write) hits 944system.cpu.l2cache.demand_hits::total 2035434 # number of demand (read+write) hits 945system.cpu.l2cache.overall_hits::cpu.inst 1019836 # number of overall hits 946system.cpu.l2cache.overall_hits::cpu.data 1015598 # number of overall hits 947system.cpu.l2cache.overall_hits::total 2035434 # number of overall hits 948system.cpu.l2cache.ReadReq_misses::cpu.inst 15129 # number of ReadReq misses 949system.cpu.l2cache.ReadReq_misses::cpu.data 273823 # number of ReadReq misses 950system.cpu.l2cache.ReadReq_misses::total 288952 # number of ReadReq misses 951system.cpu.l2cache.UpgradeReq_misses::cpu.data 57 # number of UpgradeReq misses 952system.cpu.l2cache.UpgradeReq_misses::total 57 # number of UpgradeReq misses 953system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 8 # number of SCUpgradeReq misses 954system.cpu.l2cache.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses 955system.cpu.l2cache.ReadExReq_misses::cpu.data 115376 # number of ReadExReq misses 956system.cpu.l2cache.ReadExReq_misses::total 115376 # number of ReadExReq misses 957system.cpu.l2cache.demand_misses::cpu.inst 15129 # number of demand (read+write) misses 958system.cpu.l2cache.demand_misses::cpu.data 389199 # number of demand (read+write) misses 959system.cpu.l2cache.demand_misses::total 404328 # number of demand (read+write) misses 960system.cpu.l2cache.overall_misses::cpu.inst 15129 # number of overall misses 961system.cpu.l2cache.overall_misses::cpu.data 389199 # number of overall misses 962system.cpu.l2cache.overall_misses::total 404328 # number of overall misses 963system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1155504000 # number of ReadReq miss cycles 964system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17984856500 # number of ReadReq miss cycles 965system.cpu.l2cache.ReadReq_miss_latency::total 19140360500 # number of ReadReq miss cycles 966system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331495 # number of UpgradeReq miss cycles 967system.cpu.l2cache.UpgradeReq_miss_latency::total 331495 # number of UpgradeReq miss cycles 968system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 92996 # number of SCUpgradeReq miss cycles 969system.cpu.l2cache.SCUpgradeReq_miss_latency::total 92996 # number of SCUpgradeReq miss cycles 970system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9647937355 # number of ReadExReq miss cycles 971system.cpu.l2cache.ReadExReq_miss_latency::total 9647937355 # number of ReadExReq miss cycles 972system.cpu.l2cache.demand_miss_latency::cpu.inst 1155504000 # number of demand (read+write) miss cycles 973system.cpu.l2cache.demand_miss_latency::cpu.data 27632793855 # number of demand (read+write) miss cycles 974system.cpu.l2cache.demand_miss_latency::total 28788297855 # number of demand (read+write) miss cycles 975system.cpu.l2cache.overall_miss_latency::cpu.inst 1155504000 # number of overall miss cycles 976system.cpu.l2cache.overall_miss_latency::cpu.data 27632793855 # number of overall miss cycles 977system.cpu.l2cache.overall_miss_latency::total 28788297855 # number of overall miss cycles 978system.cpu.l2cache.ReadReq_accesses::cpu.inst 1034965 # number of ReadReq accesses(hits+misses) 979system.cpu.l2cache.ReadReq_accesses::cpu.data 1102902 # number of ReadReq accesses(hits+misses) 980system.cpu.l2cache.ReadReq_accesses::total 2137867 # number of ReadReq accesses(hits+misses) 981system.cpu.l2cache.Writeback_accesses::writebacks 842396 # number of Writeback accesses(hits+misses) 982system.cpu.l2cache.Writeback_accesses::total 842396 # number of Writeback accesses(hits+misses) 983system.cpu.l2cache.UpgradeReq_accesses::cpu.data 88 # number of UpgradeReq accesses(hits+misses) 984system.cpu.l2cache.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) 985system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) 986system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) 987system.cpu.l2cache.ReadExReq_accesses::cpu.data 301895 # number of ReadExReq accesses(hits+misses) 988system.cpu.l2cache.ReadExReq_accesses::total 301895 # number of ReadExReq accesses(hits+misses) 989system.cpu.l2cache.demand_accesses::cpu.inst 1034965 # number of demand (read+write) accesses 990system.cpu.l2cache.demand_accesses::cpu.data 1404797 # number of demand (read+write) accesses 991system.cpu.l2cache.demand_accesses::total 2439762 # number of demand (read+write) accesses 992system.cpu.l2cache.overall_accesses::cpu.inst 1034965 # number of overall (read+write) accesses 993system.cpu.l2cache.overall_accesses::cpu.data 1404797 # number of overall (read+write) accesses 994system.cpu.l2cache.overall_accesses::total 2439762 # number of overall (read+write) accesses 995system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014618 # miss rate for ReadReq accesses 996system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248275 # miss rate for ReadReq accesses 997system.cpu.l2cache.ReadReq_miss_rate::total 0.135159 # miss rate for ReadReq accesses 998system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.647727 # miss rate for UpgradeReq accesses 999system.cpu.l2cache.UpgradeReq_miss_rate::total 0.647727 # miss rate for UpgradeReq accesses 1000system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses 1001system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses 1002system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382173 # miss rate for ReadExReq accesses 1003system.cpu.l2cache.ReadExReq_miss_rate::total 0.382173 # miss rate for ReadExReq accesses 1004system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014618 # miss rate for demand accesses 1005system.cpu.l2cache.demand_miss_rate::cpu.data 0.277050 # miss rate for demand accesses 1006system.cpu.l2cache.demand_miss_rate::total 0.165724 # miss rate for demand accesses 1007system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014618 # miss rate for overall accesses 1008system.cpu.l2cache.overall_miss_rate::cpu.data 0.277050 # miss rate for overall accesses 1009system.cpu.l2cache.overall_miss_rate::total 0.165724 # miss rate for overall accesses 1010system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76376.759865 # average ReadReq miss latency 1011system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65680.591112 # average ReadReq miss latency 1012system.cpu.l2cache.ReadReq_avg_miss_latency::total 66240.623010 # average ReadReq miss latency 1013system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5815.701754 # average UpgradeReq miss latency 1014system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5815.701754 # average UpgradeReq miss latency 1015system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 11624.500000 # average SCUpgradeReq miss latency 1016system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 11624.500000 # average SCUpgradeReq miss latency 1017system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83621.700830 # average ReadExReq miss latency 1018system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83621.700830 # average ReadExReq miss latency 1019system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency 1020system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency 1021system.cpu.l2cache.demand_avg_miss_latency::total 71200.356777 # average overall miss latency 1022system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency 1023system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency 1024system.cpu.l2cache.overall_avg_miss_latency::total 71200.356777 # average overall miss latency | 943system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 944system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 945system.cpu.l2cache.ReadExReq_hits::cpu.data 186339 # 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number of ReadReq miss cycles 971system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395995 # number of UpgradeReq miss cycles 972system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles 973system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles 974system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles 975system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271336364 # number of ReadExReq miss cycles 976system.cpu.l2cache.ReadExReq_miss_latency::total 10271336364 # number of ReadExReq miss cycles 977system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles 978system.cpu.l2cache.demand_miss_latency::cpu.data 30291348364 # number of demand (read+write) miss cycles 979system.cpu.l2cache.demand_miss_latency::total 31556185363 # number of demand (read+write) miss cycles 980system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles 981system.cpu.l2cache.overall_miss_latency::cpu.data 30291348364 # number of overall miss cycles 982system.cpu.l2cache.overall_miss_latency::total 31556185363 # number of overall miss cycles 983system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses) 984system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses) 985system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses) 986system.cpu.l2cache.Writeback_accesses::writebacks 842087 # number of Writeback accesses(hits+misses) 987system.cpu.l2cache.Writeback_accesses::total 842087 # number of Writeback accesses(hits+misses) 988system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) 989system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 990system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 27 # number of SCUpgradeReq accesses(hits+misses) 991system.cpu.l2cache.SCUpgradeReq_accesses::total 27 # number of SCUpgradeReq accesses(hits+misses) 992system.cpu.l2cache.ReadExReq_accesses::cpu.data 301613 # number of ReadExReq accesses(hits+misses) 993system.cpu.l2cache.ReadExReq_accesses::total 301613 # number of ReadExReq accesses(hits+misses) 994system.cpu.l2cache.demand_accesses::cpu.inst 1033352 # number of demand (read+write) accesses 995system.cpu.l2cache.demand_accesses::cpu.data 1404270 # number of demand (read+write) accesses 996system.cpu.l2cache.demand_accesses::total 2437622 # number of demand (read+write) accesses 997system.cpu.l2cache.overall_accesses::cpu.inst 1033352 # number of overall (read+write) accesses 998system.cpu.l2cache.overall_accesses::cpu.data 1404270 # number of overall (read+write) accesses 999system.cpu.l2cache.overall_accesses::total 2437622 # number of overall (read+write) accesses 1000system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014639 # miss rate for ReadReq accesses 1001system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248428 # miss rate for ReadReq accesses 1002system.cpu.l2cache.ReadReq_miss_rate::total 0.135326 # miss rate for ReadReq accesses 1003system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.607595 # miss rate for UpgradeReq accesses 1004system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses 1005system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses 1006system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses 1007system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382192 # miss rate for ReadExReq accesses 1008system.cpu.l2cache.ReadExReq_miss_rate::total 0.382192 # miss rate for ReadExReq accesses 1009system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses 1010system.cpu.l2cache.demand_miss_rate::cpu.data 0.277158 # miss rate for demand accesses 1011system.cpu.l2cache.demand_miss_rate::total 0.165871 # miss rate for demand accesses 1012system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses 1013system.cpu.l2cache.overall_miss_rate::cpu.data 0.277158 # miss rate for overall accesses 1014system.cpu.l2cache.overall_miss_rate::total 0.165871 # miss rate for overall accesses 1015system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency 1016system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency 1017system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency 1018system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8249.895833 # average UpgradeReq miss latency 1019system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency 1020system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency 1021system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency 1022system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89103.669206 # average ReadExReq miss latency 1023system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89103.669206 # average ReadExReq miss latency 1024system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency 1025system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::total 78045.233528 # average overall miss latency 1027system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency 1028system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency 1029system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency |
| 1025system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1026system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1027system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1028system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1029system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1030system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1031system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1032system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1030system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1031system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1032system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1033system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1034system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1035system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1036system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1037system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1033system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks 1034system.cpu.l2cache.writebacks::total 75938 # number of writebacks | 1038system.cpu.l2cache.writebacks::writebacks 75945 # number of writebacks 1039system.cpu.l2cache.writebacks::total 75945 # number of writebacks |
| 1035system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1036system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1037system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1038system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1039system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1040system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 1040system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1041system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1042system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1043system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1044system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1045system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 1041system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15128 # number of ReadReq MSHR misses 1042system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273823 # number of ReadReq MSHR misses 1043system.cpu.l2cache.ReadReq_mshr_misses::total 288951 # number of ReadReq MSHR misses 1044system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 57 # number of UpgradeReq MSHR misses 1045system.cpu.l2cache.UpgradeReq_mshr_misses::total 57 # number of UpgradeReq MSHR misses 1046system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses 1047system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses 1048system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses 1049system.cpu.l2cache.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses 1050system.cpu.l2cache.demand_mshr_misses::cpu.inst 15128 # number of demand (read+write) MSHR misses 1051system.cpu.l2cache.demand_mshr_misses::cpu.data 389199 # number of demand (read+write) MSHR misses 1052system.cpu.l2cache.demand_mshr_misses::total 404327 # number of demand (read+write) MSHR misses 1053system.cpu.l2cache.overall_mshr_misses::cpu.inst 15128 # number of overall MSHR misses 1054system.cpu.l2cache.overall_mshr_misses::cpu.data 389199 # number of overall MSHR misses 1055system.cpu.l2cache.overall_mshr_misses::total 404327 # number of overall MSHR misses 1056system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 964671250 # number of ReadReq MSHR miss cycles 1057system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14573298500 # number of ReadReq MSHR miss cycles 1058system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15537969750 # number of ReadReq MSHR miss cycles 1059system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 720554 # number of UpgradeReq MSHR miss cycles 1060system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 720554 # number of UpgradeReq MSHR miss cycles 1061system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80008 # 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number of overall MSHR miss cycles 1071system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333622500 # number of ReadReq MSHR uncacheable cycles 1072system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333622500 # number of ReadReq MSHR uncacheable cycles 1073system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884454000 # number of WriteReq MSHR uncacheable cycles 1074system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884454000 # number of WriteReq MSHR uncacheable cycles 1075system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218076500 # number of overall MSHR uncacheable cycles 1076system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218076500 # number of overall MSHR uncacheable cycles 1077system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for ReadReq accesses 1078system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248275 # mshr miss rate for ReadReq accesses 1079system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135159 # mshr miss rate for ReadReq accesses 1080system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.647727 # mshr miss rate for UpgradeReq accesses 1081system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.647727 # mshr miss rate for UpgradeReq accesses 1082system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses 1083system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses 1084system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382173 # mshr miss rate for ReadExReq accesses 1085system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382173 # mshr miss rate for ReadExReq accesses 1086system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for demand accesses 1087system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277050 # mshr miss rate for demand accesses 1088system.cpu.l2cache.demand_mshr_miss_rate::total 0.165724 # mshr miss rate for demand accesses 1089system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014617 # 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number of ReadReq MSHR misses 1049system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses 1050system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses 1051system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses 1052system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses 1053system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses 1054system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses 1055system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses 1056system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # number of demand (read+write) MSHR misses 1057system.cpu.l2cache.demand_mshr_misses::total 404331 # number of demand (read+write) MSHR misses 1058system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses 1059system.cpu.l2cache.overall_mshr_misses::cpu.data 389205 # number of overall MSHR misses 1060system.cpu.l2cache.overall_mshr_misses::total 404331 # number of overall MSHR misses 1061system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles 1062system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles 1063system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles 1064system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1000544 # number of UpgradeReq MSHR miss cycles 1065system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles 1066system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles 1067system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles 1068system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861608136 # number of ReadExReq MSHR miss cycles 1069system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861608136 # number of ReadExReq MSHR miss cycles 1070system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles 1071system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469504136 # number of demand (read+write) MSHR miss cycles 1072system.cpu.l2cache.demand_mshr_miss_latency::total 26545330885 # number of demand (read+write) MSHR miss cycles 1073system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles 1074system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469504136 # number of overall MSHR miss cycles 1075system.cpu.l2cache.overall_mshr_miss_latency::total 26545330885 # number of overall MSHR miss cycles 1076system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles 1077system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles 1078system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles 1079system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887182500 # number of WriteReq MSHR uncacheable cycles 1080system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223869000 # number of overall MSHR uncacheable cycles 1081system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223869000 # number of overall MSHR uncacheable cycles 1082system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for ReadReq accesses 1083system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248428 # mshr miss rate for ReadReq accesses 1084system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135326 # mshr miss rate for ReadReq accesses 1085system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 # mshr miss rate for UpgradeReq accesses 1086system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses 1087system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses 1088system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses 1089system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382192 # mshr miss rate for ReadExReq accesses 1090system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382192 # mshr miss rate for ReadExReq accesses 1091system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses 1092system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for demand accesses 1093system.cpu.l2cache.demand_mshr_miss_rate::total 0.165871 # mshr miss rate for demand accesses 1094system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses 1095system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for overall accesses 1096system.cpu.l2cache.overall_mshr_miss_rate::total 0.165871 # mshr miss rate for overall accesses 1097system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency 1098system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency 1099system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency 1100system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 # average UpgradeReq mshr miss latency 1101system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency 1102system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency 1103system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency 1104system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency 1105system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency 1106system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency 1107system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency 1108system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency 1109system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency 1110system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency 1111system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency |
| 1107system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1108system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1109system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1110system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1111system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1112system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1113system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1112system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1113system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1114system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1115system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1116system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1117system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1118system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1114system.cpu.toL2Bus.trans_dist::ReadReq 2145159 # Transaction distribution 1115system.cpu.toL2Bus.trans_dist::ReadResp 2145056 # Transaction distribution | 1119system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution |
| 1116system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution | 1121system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution |
| 1118system.cpu.toL2Bus.trans_dist::Writeback 842396 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::UpgradeReq 88 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::UpgradeResp 116 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::ReadExReq 301895 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::ReadExResp 301895 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::BadAddressError 86 # Transaction distribution 1126system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2070119 # Packet count per connected master and slave (bytes) 1127system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3685432 # Packet count per connected master and slave (bytes) 1128system.cpu.toL2Bus.pkt_count::total 5755551 # Packet count per connected master and slave (bytes) 1129system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66237760 # Cumulative packet size per connected master and slave (bytes) 1130system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143868972 # Cumulative packet size per connected master and slave (bytes) 1131system.cpu.toL2Bus.pkt_size::total 210106732 # Cumulative packet size per connected master and slave (bytes) 1132system.cpu.toL2Bus.snoops 42071 # Total snoops (count) 1133system.cpu.toL2Bus.snoop_fanout::samples 3324189 # Request fanout histogram 1134system.cpu.toL2Bus.snoop_fanout::mean 1.012552 # Request fanout histogram 1135system.cpu.toL2Bus.snoop_fanout::stdev 0.111331 # Request fanout histogram | 1123system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution 1127system.cpu.toL2Bus.trans_dist::UpgradeResp 106 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::ReadExReq 301613 # Transaction distribution 1129system.cpu.toL2Bus.trans_dist::ReadExResp 301613 # Transaction distribution 1130system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution 1131system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes) 1132system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes) 1133system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes) 1134system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes) 1135system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) 1136system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) 1137system.cpu.toL2Bus.snoops 42097 # Total snoops (count) 1138system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram 1139system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram 1140system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram |
| 1136system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1137system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1141system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1142system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1138system.cpu.toL2Bus.snoop_fanout::1 3282463 98.74% 98.74% # Request fanout histogram 1139system.cpu.toL2Bus.snoop_fanout::2 41726 1.26% 100.00% # Request fanout histogram | 1143system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram 1144system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram |
| 1140system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1142system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1145system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1147system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1143system.cpu.toL2Bus.snoop_fanout::total 3324189 # Request fanout histogram 1144system.cpu.toL2Bus.reqLayer0.occupancy 2496690997 # Layer occupancy (ticks) | 1148system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram 1149system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) |
| 1145system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1146system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 1147system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1150system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1151system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 1152system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1148system.cpu.toL2Bus.respLayer0.occupancy 1556745400 # Layer occupancy (ticks) | 1153system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) |
| 1149system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1154system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1150system.cpu.toL2Bus.respLayer1.occupancy 2189304171 # Layer occupancy (ticks) | 1155system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks) |
| 1151system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1152system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1153system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1154system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1155system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1156system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1157system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1158system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 56 unchanged lines hidden (view full) --- 1215system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1216system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1217system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1218system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1219system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1220system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1221system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1222system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1156system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1157system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1158system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1159system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1160system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1161system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1162system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1163system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 56 unchanged lines hidden (view full) --- 1220system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1221system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1222system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1223system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1224system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1225system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1226system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1227system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1223system.iobus.reqLayer29.occupancy 406216778 # Layer occupancy (ticks) | 1228system.iobus.reqLayer29.occupancy 242053963 # Layer occupancy (ticks) |
| 1224system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1225system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1226system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1227system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) 1228system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1229system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1230system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1231system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1232system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) 1233system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1229system.iobus.respLayer1.occupancy 42011283 # Layer occupancy (ticks) | 1234system.iobus.respLayer1.occupancy 42024003 # Layer occupancy (ticks) |
| 1230system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1231system.iocache.tags.replacements 41685 # number of replacements | 1235system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1236system.iocache.tags.replacements 41685 # number of replacements |
| 1232system.iocache.tags.tagsinuse 1.260535 # Cycle average of tags in use | 1237system.iocache.tags.tagsinuse 1.259192 # Cycle average of tags in use |
| 1233system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1234system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1235system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1238system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1239system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1240system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1236system.iocache.tags.warmup_cycle 1709356303000 # Cycle when the warmup percentage was hit. 1237system.iocache.tags.occ_blocks::tsunami.ide 1.260535 # Average occupied blocks per requestor 1238system.iocache.tags.occ_percent::tsunami.ide 0.078783 # Average percentage of cache occupancy 1239system.iocache.tags.occ_percent::total 0.078783 # Average percentage of cache occupancy | 1241system.iocache.tags.warmup_cycle 1711311066000 # Cycle when the warmup percentage was hit. 1242system.iocache.tags.occ_blocks::tsunami.ide 1.259192 # Average occupied blocks per requestor 1243system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy 1244system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy |
| 1240system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1241system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1242system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1243system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1244system.iocache.tags.data_accesses 375525 # Number of data accesses 1245system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1246system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1247system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 1248system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 1249system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1250system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1251system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1252system.iocache.overall_misses::total 173 # number of overall misses | 1245system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1246system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1247system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1248system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1249system.iocache.tags.data_accesses 375525 # Number of data accesses 1250system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1251system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1252system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 1253system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 1254system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1255system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1256system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1257system.iocache.overall_misses::total 173 # number of overall misses |
| 1253system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 1254system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 1255system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13645647112 # number of WriteInvalidateReq miss cycles 1256system.iocache.WriteInvalidateReq_miss_latency::total 13645647112 # number of WriteInvalidateReq miss cycles 1257system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 1258system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 1259system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 1260system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles | 1258system.iocache.ReadReq_miss_latency::tsunami.ide 21719383 # number of ReadReq miss cycles 1259system.iocache.ReadReq_miss_latency::total 21719383 # number of ReadReq miss cycles 1260system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8765491577 # number of WriteInvalidateReq miss cycles 1261system.iocache.WriteInvalidateReq_miss_latency::total 8765491577 # number of WriteInvalidateReq miss cycles 1262system.iocache.demand_miss_latency::tsunami.ide 21719383 # number of demand (read+write) miss cycles 1263system.iocache.demand_miss_latency::total 21719383 # number of demand (read+write) miss cycles 1264system.iocache.overall_miss_latency::tsunami.ide 21719383 # number of overall miss cycles 1265system.iocache.overall_miss_latency::total 21719383 # number of overall miss cycles |
| 1261system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1262system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1263system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1264system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 1265system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1266system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1267system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1268system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1269system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1270system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1271system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1272system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1273system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1274system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1275system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1276system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1266system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1267system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1268system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1269system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 1270system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1271system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1272system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1273system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1274system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1275system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1276system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1277system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1278system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1279system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1280system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1281system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1277system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 1278system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 1279system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328399.285522 # average WriteInvalidateReq miss latency 1280system.iocache.WriteInvalidateReq_avg_miss_latency::total 328399.285522 # average WriteInvalidateReq miss latency 1281system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 1282system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 1283system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 1284system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 1285system.iocache.blocked_cycles::no_mshrs 206436 # number of cycles access was blocked | 1282system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125545.566474 # average ReadReq miss latency 1283system.iocache.ReadReq_avg_miss_latency::total 125545.566474 # average ReadReq miss latency 1284system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210952.338684 # average WriteInvalidateReq miss latency 1285system.iocache.WriteInvalidateReq_avg_miss_latency::total 210952.338684 # average WriteInvalidateReq miss latency 1286system.iocache.demand_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency 1287system.iocache.demand_avg_miss_latency::total 125545.566474 # average overall miss latency 1288system.iocache.overall_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency 1289system.iocache.overall_avg_miss_latency::total 125545.566474 # average overall miss latency 1290system.iocache.blocked_cycles::no_mshrs 73146 # number of cycles access was blocked |
| 1286system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1291system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1287system.iocache.blocked::no_mshrs 23523 # number of cycles access was blocked | 1292system.iocache.blocked::no_mshrs 10015 # number of cycles access was blocked |
| 1288system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1293system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1289system.iocache.avg_blocked_cycles::no_mshrs 8.775921 # average number of cycles each access was blocked | 1294system.iocache.avg_blocked_cycles::no_mshrs 7.303645 # average number of cycles each access was blocked |
| 1290system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1291system.iocache.fast_writes 0 # number of fast writes performed 1292system.iocache.cache_copies 0 # number of cache copies performed 1293system.iocache.writebacks::writebacks 41512 # number of writebacks 1294system.iocache.writebacks::total 41512 # number of writebacks 1295system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1296system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1297system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1298system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1299system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1300system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1301system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1302system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses | 1295system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1296system.iocache.fast_writes 0 # number of fast writes performed 1297system.iocache.cache_copies 0 # number of cache copies performed 1298system.iocache.writebacks::writebacks 41512 # number of writebacks 1299system.iocache.writebacks::total 41512 # number of writebacks 1300system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1301system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1302system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1303system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1304system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1305system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1306system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1307system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses |
| 1303system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 1304system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 1305system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11484876678 # number of WriteInvalidateReq MSHR miss cycles 1306system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11484876678 # number of WriteInvalidateReq MSHR miss cycles 1307system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 1308system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 1309system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 1310system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles | 1308system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12567383 # number of ReadReq MSHR miss cycles 1309system.iocache.ReadReq_mshr_miss_latency::total 12567383 # number of ReadReq MSHR miss cycles 1310system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6604781583 # number of WriteInvalidateReq MSHR miss cycles 1311system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6604781583 # number of WriteInvalidateReq MSHR miss cycles 1312system.iocache.demand_mshr_miss_latency::tsunami.ide 12567383 # number of demand (read+write) MSHR miss cycles 1313system.iocache.demand_mshr_miss_latency::total 12567383 # number of demand (read+write) MSHR miss cycles 1314system.iocache.overall_mshr_miss_latency::tsunami.ide 12567383 # number of overall MSHR miss cycles 1315system.iocache.overall_mshr_miss_latency::total 12567383 # number of overall MSHR miss cycles |
| 1311system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1312system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1313system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1314system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1315system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1316system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1317system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1318system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1316system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1317system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1318system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1319system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1320system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1321system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1322system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1323system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1319system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 1320system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 1321system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276397.686706 # average WriteInvalidateReq mshr miss latency 1322system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276397.686706 # average WriteInvalidateReq mshr miss latency 1323system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1324system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 1325system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1326system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency | 1324system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average ReadReq mshr miss latency 1325system.iocache.ReadReq_avg_mshr_miss_latency::total 72643.832370 # average ReadReq mshr miss latency 1326system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158952.194431 # average WriteInvalidateReq mshr miss latency 1327system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158952.194431 # average WriteInvalidateReq mshr miss latency 1328system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency 1329system.iocache.demand_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency 1330system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency 1331system.iocache.overall_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency |
| 1327system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1332system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1328system.membus.trans_dist::ReadReq 296054 # Transaction distribution 1329system.membus.trans_dist::ReadResp 295968 # Transaction distribution | 1333system.membus.trans_dist::ReadReq 296160 # Transaction distribution 1334system.membus.trans_dist::ReadResp 296066 # Transaction distribution |
| 1330system.membus.trans_dist::WriteReq 9597 # Transaction distribution 1331system.membus.trans_dist::WriteResp 9597 # Transaction distribution | 1335system.membus.trans_dist::WriteReq 9597 # Transaction distribution 1336system.membus.trans_dist::WriteResp 9597 # Transaction distribution |
| 1332system.membus.trans_dist::Writeback 117450 # Transaction distribution | 1337system.membus.trans_dist::Writeback 117457 # Transaction distribution |
| 1333system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1334system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution | 1338system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1339system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 1335system.membus.trans_dist::UpgradeReq 203 # Transaction distribution 1336system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution 1337system.membus.trans_dist::UpgradeResp 211 # Transaction distribution 1338system.membus.trans_dist::ReadExReq 115230 # Transaction distribution 1339system.membus.trans_dist::ReadExResp 115230 # Transaction distribution 1340system.membus.trans_dist::BadAddressError 86 # Transaction distribution | 1340system.membus.trans_dist::UpgradeReq 185 # Transaction distribution 1341system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1342system.membus.trans_dist::UpgradeResp 190 # Transaction distribution 1343system.membus.trans_dist::ReadExReq 115137 # Transaction distribution 1344system.membus.trans_dist::ReadExResp 115137 # Transaction distribution 1345system.membus.trans_dist::BadAddressError 94 # Transaction distribution |
| 1341system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) | 1346system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) |
| 1342system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884273 # Packet count per connected master and slave (bytes) 1343system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 172 # Packet count per connected master and slave (bytes) 1344system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917499 # Packet count per connected master and slave (bytes) | 1347system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes) 1348system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) 1349system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes) |
| 1345system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1346system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) | 1350system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1351system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) |
| 1347system.membus.pkt_count::total 1042303 # Packet count per connected master and slave (bytes) | 1352system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes) |
| 1348system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) | 1353system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) |
| 1349system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704576 # Cumulative packet size per connected master and slave (bytes) 1350system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30748716 # Cumulative packet size per connected master and slave (bytes) | 1354system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) 1355system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) |
| 1351system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1352system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) | 1356system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1357system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) |
| 1353system.membus.pkt_size::total 36065772 # Cumulative packet size per connected master and slave (bytes) | 1358system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) |
| 1354system.membus.snoops 435 # Total snoops (count) | 1359system.membus.snoops 435 # Total snoops (count) |
| 1355system.membus.snoop_fanout::samples 563568 # Request fanout histogram | 1360system.membus.snoop_fanout::samples 563651 # Request fanout histogram |
| 1356system.membus.snoop_fanout::mean 1 # Request fanout histogram 1357system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1358system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1359system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1361system.membus.snoop_fanout::mean 1 # Request fanout histogram 1362system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1363system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1364system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1360system.membus.snoop_fanout::1 563568 100.00% 100.00% # Request fanout histogram | 1365system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram |
| 1361system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1362system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1363system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1364system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1366system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1367system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1368system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1369system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1365system.membus.snoop_fanout::total 563568 # Request fanout histogram 1366system.membus.reqLayer0.occupancy 31570500 # Layer occupancy (ticks) | 1370system.membus.snoop_fanout::total 563651 # Request fanout histogram 1371system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) |
| 1367system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1372system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1368system.membus.reqLayer1.occupancy 1858044250 # Layer occupancy (ticks) | 1373system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks) |
| 1369system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1374system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1370system.membus.reqLayer2.occupancy 107000 # Layer occupancy (ticks) | 1375system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) |
| 1371system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1376system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1372system.membus.respLayer1.occupancy 3754720043 # Layer occupancy (ticks) 1373system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1374system.membus.respLayer2.occupancy 43142717 # Layer occupancy (ticks) | 1377system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks) 1378system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1379system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) |
| 1375system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1376system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1377system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1378system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1379system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1380system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1381system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1382system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 17 unchanged lines hidden (view full) --- 1400system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1401system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1402system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1403system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1404system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1405system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1406system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1407system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1380system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1381system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1382system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1383system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1384system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1385system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1386system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1387system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 17 unchanged lines hidden (view full) --- 1405system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1406system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1407system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1408system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1409system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1410system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1411system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 1412system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1408system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed 1409system.cpu.kern.inst.hwrei 211002 # number of hwrei instructions executed 1410system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl | 1413system.cpu.kern.inst.quiesce 6445 # number of quiesce instructions executed 1414system.cpu.kern.inst.hwrei 210982 # number of hwrei instructions executed 1415system.cpu.kern.ipl_count::0 74654 40.97% 40.97% # number of times we switched to this ipl |
| 1411system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1412system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl | 1416system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1417system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl |
| 1413system.cpu.kern.ipl_count::31 105562 57.93% 100.00% # number of times we switched to this ipl 1414system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl 1415system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 1418system.cpu.kern.ipl_count::31 105549 57.93% 100.00% # number of times we switched to this ipl 1419system.cpu.kern.ipl_count::total 182213 # number of times we switched to this ipl 1420system.cpu.kern.ipl_good::0 73287 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 1416system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1417system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl | 1421system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1422system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl |
| 1418system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1419system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl 1420system.cpu.kern.ipl_ticks::0 1817332157500 97.76% 97.76% # number of cycles we spent at this ipl 1421system.cpu.kern.ipl_ticks::21 61952500 0.00% 97.76% # number of cycles we spent at this ipl 1422system.cpu.kern.ipl_ticks::22 528077500 0.03% 97.79% # number of cycles we spent at this ipl 1423system.cpu.kern.ipl_ticks::31 41122369500 2.21% 100.00% # number of cycles we spent at this ipl 1424system.cpu.kern.ipl_ticks::total 1859044557000 # number of cycles we spent at this ipl 1425system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl | 1423system.cpu.kern.ipl_good::31 73287 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1424system.cpu.kern.ipl_good::total 148584 # number of times we switched to this ipl from a different ipl 1425system.cpu.kern.ipl_ticks::0 1817355802000 97.65% 97.65% # number of cycles we spent at this ipl 1426system.cpu.kern.ipl_ticks::21 62075500 0.00% 97.66% # number of cycles we spent at this ipl 1427system.cpu.kern.ipl_ticks::22 532990500 0.03% 97.69% # number of cycles we spent at this ipl 1428system.cpu.kern.ipl_ticks::31 43053863500 2.31% 100.00% # number of cycles we spent at this ipl 1429system.cpu.kern.ipl_ticks::total 1861004731500 # number of cycles we spent at this ipl 1430system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl |
| 1426system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1427system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 1431system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1432system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 1428system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl 1429system.cpu.kern.ipl_used::total 0.815429 # fraction of swpipl calls that actually changed the ipl | 1433system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl 1434system.cpu.kern.ipl_used::total 0.815441 # fraction of swpipl calls that actually changed the ipl |
| 1430system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1431system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1432system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1433system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1434system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1435system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1436system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1437system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 1460system.cpu.kern.syscall::total 326 # number of syscalls executed 1461system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1462system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1463system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1464system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1465system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed 1466system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1467system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed | 1435system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1436system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1437system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1438system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1439system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1440system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1441system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1442system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 1465system.cpu.kern.syscall::total 326 # number of syscalls executed 1466system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1467system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1468system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1469system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1470system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed 1471system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1472system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed |
| 1468system.cpu.kern.callpal::swpipl 175118 91.23% 93.44% # number of callpals executed | 1473system.cpu.kern.callpal::swpipl 175098 91.22% 93.43% # number of callpals executed |
| 1469system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 1470system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1471system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1472system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1473system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1474system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 1475system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1476system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 1474system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 1475system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1476system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1477system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1478system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1479system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 1480system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1481system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 1477system.cpu.kern.callpal::total 191962 # number of callpals executed 1478system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches 1479system.cpu.kern.mode_switch::user 1743 # number of protection mode switches 1480system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 1481system.cpu.kern.mode_good::kernel 1913 1482system.cpu.kern.mode_good::user 1743 | 1482system.cpu.kern.callpal::total 191942 # number of callpals executed 1483system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches 1484system.cpu.kern.mode_switch::user 1741 # number of protection mode switches 1485system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 1486system.cpu.kern.mode_good::kernel 1911 1487system.cpu.kern.mode_good::user 1741 |
| 1483system.cpu.kern.mode_good::idle 170 | 1488system.cpu.kern.mode_good::idle 170 |
| 1484system.cpu.kern.mode_switch_good::kernel 0.326953 # fraction of useful protection mode switches | 1489system.cpu.kern.mode_switch_good::kernel 0.326667 # fraction of useful protection mode switches |
| 1485system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1490system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1486system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 1487system.cpu.kern.mode_switch_good::total 0.394840 # fraction of useful protection mode switches 1488system.cpu.kern.mode_ticks::kernel 29081819500 1.56% 1.56% # number of ticks spent at the given mode 1489system.cpu.kern.mode_ticks::user 2655993500 0.14% 1.71% # number of ticks spent at the given mode 1490system.cpu.kern.mode_ticks::idle 1827306736000 98.29% 100.00% # number of ticks spent at the given mode | 1491system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 1492system.cpu.kern.mode_switch_good::total 0.394509 # fraction of useful protection mode switches 1493system.cpu.kern.mode_ticks::kernel 29153631500 1.57% 1.57% # number of ticks spent at the given mode 1494system.cpu.kern.mode_ticks::user 2692582500 0.14% 1.71% # number of ticks spent at the given mode 1495system.cpu.kern.mode_ticks::idle 1829158509500 98.29% 100.00% # number of ticks spent at the given mode |
| 1491system.cpu.kern.swap_context 4178 # number of times the context was actually changed 1492 1493---------- End Simulation Statistics ---------- | 1496system.cpu.kern.swap_context 4178 # number of times the context was actually changed 1497 1498---------- End Simulation Statistics ---------- |