| stats.txt (10513:ca4438b6e39a) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.859039 # Number of seconds simulated 4sim_ticks 1859038679000 # Number of ticks simulated 5final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.859049 # Number of seconds simulated 4sim_ticks 1859049148500 # Number of ticks simulated 5final_tick 1859049148500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 164458 # Simulator instruction rate (inst/s) 8host_op_rate 164458 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5776457310 # Simulator tick rate (ticks/s) 10host_mem_usage 314484 # Number of bytes of host memory used 11host_seconds 321.83 # Real time elapsed on the host 12sim_insts 52927600 # Number of instructions simulated 13sim_ops 52927600 # Number of ops (including micro ops) simulated | 7host_inst_rate 168870 # Simulator instruction rate (inst/s) 8host_op_rate 168870 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5931192571 # Simulator tick rate (ticks/s) 10host_mem_usage 320216 # Number of bytes of host memory used 11host_seconds 313.44 # Real time elapsed on the host 12sim_insts 52930035 # Number of instructions simulated 13sim_ops 52930035 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24875776 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 25861824 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 968256 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4860032 # Number of bytes written to this memory 23system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7519360 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 15129 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388947 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 25843904 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388684 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::total 404091 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 75938 # Number of write requests responded to by this memory 30system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 117490 # Number of write requests responded to by this memory 32system.physmem.bw_read::cpu.inst 520837 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.data 13390043 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::total 403811 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 520249 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13380914 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::total 13911396 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::cpu.inst 520837 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_inst_read::total 520837 # Instruction read bandwidth from this memory (bytes/s) 38system.physmem.bw_write::writebacks 2614272 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_write::tsunami.ide 1430486 # Write bandwidth from this memory (bytes/s) 40system.physmem.bw_write::total 4044757 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_total::writebacks 2614272 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 520837 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 13390043 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::tsunami.ide 1431002 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::total 17956154 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.readReqs 404091 # Number of read requests accepted 47system.physmem.writeReqs 117490 # Number of write requests accepted 48system.physmem.readBursts 404091 # Number of DRAM read bursts, including those serviced by the write queue 49system.physmem.writeBursts 117490 # Number of DRAM write bursts, including those merged in the write queue 50system.physmem.bytesReadDRAM 25850368 # Total number of bytes read from DRAM 51system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue 52system.physmem.bytesWritten 7517888 # Total number of bytes written to DRAM 53system.physmem.bytesReadSys 25861824 # Total read bytes from the system interface side 54system.physmem.bytesWrittenSys 7519360 # Total written bytes from the system interface side 55system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue 56system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 57system.physmem.neitherReadNorWriteReqs 193 # Number of requests that are neither read nor write 58system.physmem.perBankRdBursts::0 25747 # Per bank write bursts 59system.physmem.perBankRdBursts::1 25572 # Per bank write bursts 60system.physmem.perBankRdBursts::2 25523 # Per bank write bursts 61system.physmem.perBankRdBursts::3 25355 # Per bank write bursts 62system.physmem.perBankRdBursts::4 25392 # Per bank write bursts 63system.physmem.perBankRdBursts::5 24811 # Per bank write bursts 64system.physmem.perBankRdBursts::6 25029 # Per bank write bursts 65system.physmem.perBankRdBursts::7 25134 # Per bank write bursts 66system.physmem.perBankRdBursts::8 24968 # Per bank write bursts 67system.physmem.perBankRdBursts::9 25052 # Per bank write bursts 68system.physmem.perBankRdBursts::10 25439 # Per bank write bursts 69system.physmem.perBankRdBursts::11 24779 # Per bank write bursts 70system.physmem.perBankRdBursts::12 24568 # Per bank write bursts 71system.physmem.perBankRdBursts::13 25250 # Per bank write bursts 72system.physmem.perBankRdBursts::14 25688 # Per bank write bursts 73system.physmem.perBankRdBursts::15 25605 # Per bank write bursts 74system.physmem.perBankWrBursts::0 8041 # Per bank write bursts 75system.physmem.perBankWrBursts::1 7603 # Per bank write bursts 76system.physmem.perBankWrBursts::2 7894 # Per bank write bursts 77system.physmem.perBankWrBursts::3 7385 # Per bank write bursts 78system.physmem.perBankWrBursts::4 7327 # Per bank write bursts 79system.physmem.perBankWrBursts::5 6730 # Per bank write bursts 80system.physmem.perBankWrBursts::6 6858 # Per bank write bursts 81system.physmem.perBankWrBursts::7 6765 # Per bank write bursts 82system.physmem.perBankWrBursts::8 7133 # Per bank write bursts 83system.physmem.perBankWrBursts::9 6722 # Per bank write bursts 84system.physmem.perBankWrBursts::10 7301 # Per bank write bursts 85system.physmem.perBankWrBursts::11 6871 # Per bank write bursts 86system.physmem.perBankWrBursts::12 7190 # Per bank write bursts 87system.physmem.perBankWrBursts::13 7853 # Per bank write bursts 88system.physmem.perBankWrBursts::14 7964 # Per bank write bursts 89system.physmem.perBankWrBursts::15 7830 # Per bank write bursts | 33system.physmem.bw_read::total 13901679 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 520249 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 520249 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4043047 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4043047 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4043047 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 520249 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13380914 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17944726 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 403811 # Number of read requests accepted 44system.physmem.writeReqs 158993 # Number of write requests accepted 45system.physmem.readBursts 403811 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 158993 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25836928 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue 49system.physmem.bytesWritten 10037376 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25843904 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10175552 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 2130 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25744 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25560 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25512 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25342 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25388 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24802 # Per bank write bursts 61system.physmem.perBankRdBursts::6 25022 # Per bank write bursts 62system.physmem.perBankRdBursts::7 25128 # Per bank write bursts 63system.physmem.perBankRdBursts::8 24929 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25033 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25435 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24778 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24542 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25239 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25649 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25599 # Per bank write bursts 71system.physmem.perBankWrBursts::0 10531 # Per bank write bursts 72system.physmem.perBankWrBursts::1 10049 # Per bank write bursts 73system.physmem.perBankWrBursts::2 10576 # Per bank write bursts 74system.physmem.perBankWrBursts::3 9740 # Per bank write bursts 75system.physmem.perBankWrBursts::4 9614 # Per bank write bursts 76system.physmem.perBankWrBursts::5 9115 # Per bank write bursts 77system.physmem.perBankWrBursts::6 9087 # Per bank write bursts 78system.physmem.perBankWrBursts::7 8933 # Per bank write bursts 79system.physmem.perBankWrBursts::8 9694 # Per bank write bursts 80system.physmem.perBankWrBursts::9 8895 # Per bank write bursts 81system.physmem.perBankWrBursts::10 9699 # Per bank write bursts 82system.physmem.perBankWrBursts::11 9449 # Per bank write bursts 83system.physmem.perBankWrBursts::12 10004 # Per bank write bursts 84system.physmem.perBankWrBursts::13 10709 # Per bank write bursts 85system.physmem.perBankWrBursts::14 10413 # Per bank write bursts 86system.physmem.perBankWrBursts::15 10326 # Per bank write bursts |
| 90system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 91system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 92system.physmem.totGap 1859033424000 # Total gap between requests | 88system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 89system.physmem.totGap 1859043836000 # Total gap between requests |
| 93system.physmem.readPktSize::0 0 # Read request sizes (log2) 94system.physmem.readPktSize::1 0 # Read request sizes (log2) 95system.physmem.readPktSize::2 0 # Read request sizes (log2) 96system.physmem.readPktSize::3 0 # Read request sizes (log2) 97system.physmem.readPktSize::4 0 # Read request sizes (log2) 98system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 99system.physmem.readPktSize::6 404091 # Read request sizes (log2) | 96system.physmem.readPktSize::6 403811 # Read request sizes (log2) |
| 100system.physmem.writePktSize::0 0 # Write request sizes (log2) 101system.physmem.writePktSize::1 0 # Write request sizes (log2) 102system.physmem.writePktSize::2 0 # Write request sizes (log2) 103system.physmem.writePktSize::3 0 # Write request sizes (log2) 104system.physmem.writePktSize::4 0 # Write request sizes (log2) 105system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 106system.physmem.writePktSize::6 117490 # Write request sizes (log2) 107system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::1 37620 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 42963 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 8182 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 158993 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 314947 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 42912 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 8209 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see |
| 112system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 146system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 109system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::15 1544 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 2141 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 3054 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 4174 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 5440 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6763 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 7142 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 8810 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 9005 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 8758 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 8976 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 7859 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 7939 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 6211 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 6103 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 6088 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::35 158 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::36 154 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::39 113 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::41 141 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::44 155 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see | 151system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 3979 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 5517 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 7478 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 9204 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 10713 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 11173 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 12066 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 11628 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 11816 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 10845 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 10205 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 9101 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 9155 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 7171 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6920 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6788 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6319 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 496 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 385 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 365 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 338 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 283 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 237 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 220 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see |
| 186system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see | 183system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see 203system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::mean 544.521149 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::gmean 334.160448 # Bytes accessed per row activation 206system.physmem.bytesPerActivate::stdev 418.029082 # Bytes accessed per row activation 207system.physmem.bytesPerActivate::0-127 13483 22.00% 22.00% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::128-255 10372 16.93% 38.93% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::256-383 4758 7.76% 46.69% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::384-511 2785 4.54% 51.24% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::512-639 2293 3.74% 54.98% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::640-767 1673 2.73% 57.71% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::768-895 1477 2.41% 60.12% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::896-1023 1592 2.60% 62.72% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1024-1151 22847 37.28% 100.00% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation 217system.physmem.rdPerTurnAround::samples 5232 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::mean 77.198394 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::stdev 2919.153555 # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::0-8191 5229 99.94% 99.94% # Reads before turning the bus around for writes | 184system.physmem.wrQLenPdf::48 127 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 107 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 63789 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 562.390130 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 348.747922 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 419.715872 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 13502 21.17% 21.17% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10319 16.18% 37.34% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4795 7.52% 44.86% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 2857 4.48% 49.34% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2332 3.66% 53.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1655 2.59% 55.59% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1501 2.35% 57.94% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1587 2.49% 60.43% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 25241 39.57% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 63789 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5661 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 71.309309 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2806.420357 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5658 99.95% 99.95% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 224system.physmem.rdPerTurnAround::total 5232 # Reads before turning the bus around for writes 225system.physmem.wrPerTurnAround::samples 5232 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::mean 22.451644 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::gmean 19.067800 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::stdev 21.155033 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::16-19 4469 85.42% 85.42% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20-23 138 2.64% 88.05% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::24-27 12 0.23% 88.28% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::28-31 232 4.43% 92.72% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::32-35 44 0.84% 93.56% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::36-39 2 0.04% 93.60% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::40-43 5 0.10% 93.69% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::44-47 10 0.19% 93.88% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-51 17 0.32% 94.21% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::52-55 2 0.04% 94.25% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::56-59 1 0.02% 94.27% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::60-63 2 0.04% 94.30% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::64-67 7 0.13% 94.44% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::68-71 3 0.06% 94.50% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-75 4 0.08% 94.57% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::76-79 1 0.02% 94.59% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::80-83 28 0.54% 95.13% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::84-87 15 0.29% 95.41% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::92-95 15 0.29% 95.70% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::96-99 171 3.27% 98.97% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::100-103 6 0.11% 99.08% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::116-119 2 0.04% 99.14% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::120-123 2 0.04% 99.18% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::124-127 1 0.02% 99.20% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::128-131 5 0.10% 99.29% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::132-135 1 0.02% 99.31% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::136-139 6 0.11% 99.43% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::140-143 4 0.08% 99.50% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::144-147 11 0.21% 99.71% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::148-151 1 0.02% 99.73% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::152-155 2 0.04% 99.77% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::176-179 1 0.02% 99.85% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::224-227 7 0.13% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 5232 # Writes before turning the bus around for reads 268system.physmem.totQLat 3681492750 # Total ticks spent queuing 269system.physmem.totMemAccLat 11254842750 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 2019560000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 9114.59 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 5661 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5661 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 27.704293 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 20.909682 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 34.456612 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-23 4621 81.63% 81.63% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-31 191 3.37% 85.00% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-39 281 4.96% 89.97% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-47 54 0.95% 90.92% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-55 96 1.70% 92.62% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::56-63 48 0.85% 93.46% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::64-71 17 0.30% 93.76% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-79 14 0.25% 94.01% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::80-87 19 0.34% 94.35% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::88-95 5 0.09% 94.44% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::96-103 15 0.26% 94.70% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-111 4 0.07% 94.77% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::112-119 5 0.09% 94.86% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::120-127 2 0.04% 94.89% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-135 19 0.34% 95.23% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::136-143 42 0.74% 95.97% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::144-151 21 0.37% 96.34% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::152-159 11 0.19% 96.54% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 96 1.70% 98.23% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::168-175 35 0.62% 98.85% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 14 0.25% 99.10% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 13 0.23% 99.33% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::192-199 10 0.18% 99.51% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 5 0.09% 99.59% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::208-215 5 0.09% 99.68% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::216-223 2 0.04% 99.72% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::224-231 5 0.09% 99.81% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::232-239 6 0.11% 99.91% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::240-247 2 0.04% 99.95% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::total 5661 # Writes before turning the bus around for reads 259system.physmem.totQLat 3666880250 # Total ticks spent queuing 260system.physmem.totMemAccLat 11236292750 # Total ticks spent from burst creation until serviced by the DRAM 261system.physmem.totBusLat 2018510000 # Total ticks spent in databus transfers 262system.physmem.avgQLat 9083.14 # Average queueing delay per DRAM burst |
| 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 263system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 273system.physmem.avgMemAccLat 27864.59 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 13.91 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s | 264system.physmem.avgMemAccLat 27833.14 # Average memory access latency per DRAM burst 265system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s 266system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s 267system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s 268system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s |
| 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 269system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 279system.physmem.busUtil 0.14 # Data bus utilization in percentage | 270system.physmem.busUtil 0.15 # Data bus utilization in percentage |
| 280system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads | 271system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads |
| 281system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 272system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes |
| 282system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing | 273system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing |
| 283system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing 284system.physmem.readRowHits 364830 # Number of row buffer hits during reads 285system.physmem.writeRowHits 95269 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 90.32 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 81.09 # Row buffer hit rate for writes 288system.physmem.avgGap 3564227.65 # Average gap between requests 289system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined 290system.physmem.memoryStateTime::IDLE 1761056207000 # Time in different power states 291system.physmem.memoryStateTime::REF 62077340000 # Time in different power states | 274system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing 275system.physmem.readRowHits 364667 # Number of row buffer hits during reads 276system.physmem.writeRowHits 132080 # Number of row buffer hits during writes 277system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads 278system.physmem.writeRowHitRate 84.20 # Row buffer hit rate for writes 279system.physmem.avgGap 3303181.63 # Average gap between requests 280system.physmem.pageHitRate 88.62 # Row buffer hit rate, read and write combined 281system.physmem.memoryStateTime::IDLE 1760890123500 # Time in different power states 282system.physmem.memoryStateTime::REF 62077600000 # Time in different power states |
| 292system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 283system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 293system.physmem.memoryStateTime::ACT 35903990500 # Time in different power states | 284system.physmem.memoryStateTime::ACT 36077600250 # Time in different power states |
| 294system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 285system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 295system.physmem.actEnergy::0 230322960 # Energy for activate commands per rank (pJ) 296system.physmem.actEnergy::1 232953840 # Energy for activate commands per rank (pJ) 297system.physmem.preEnergy::0 125672250 # Energy for precharge commands per rank (pJ) 298system.physmem.preEnergy::1 127107750 # Energy for precharge commands per rank (pJ) 299system.physmem.readEnergy::0 1579991400 # Energy for read commands per rank (pJ) 300system.physmem.readEnergy::1 1570522200 # Energy for read commands per rank (pJ) 301system.physmem.writeEnergy::0 379747440 # Energy for write commands per rank (pJ) 302system.physmem.writeEnergy::1 381438720 # Energy for write commands per rank (pJ) 303system.physmem.refreshEnergy::0 121423277040 # Energy for refresh commands per rank (pJ) 304system.physmem.refreshEnergy::1 121423277040 # Energy for refresh commands per rank (pJ) 305system.physmem.actBackEnergy::0 55561357620 # Energy for active background per rank (pJ) 306system.physmem.actBackEnergy::1 55436078745 # Energy for active background per rank (pJ) 307system.physmem.preBackEnergy::0 1066684481250 # Energy for precharge background per rank (pJ) 308system.physmem.preBackEnergy::1 1066794375000 # Energy for precharge background per rank (pJ) 309system.physmem.totalEnergy::0 1245984849960 # Total energy per rank (pJ) 310system.physmem.totalEnergy::1 1245965753295 # Total energy per rank (pJ) 311system.physmem.averagePower::0 670.231146 # Core power per rank (mW) 312system.physmem.averagePower::1 670.220874 # Core power per rank (mW) 313system.membus.trans_dist::ReadReq 296046 # Transaction distribution 314system.membus.trans_dist::ReadResp 295957 # Transaction distribution 315system.membus.trans_dist::WriteReq 9597 # Transaction distribution 316system.membus.trans_dist::WriteResp 9597 # Transaction distribution 317system.membus.trans_dist::Writeback 75938 # Transaction distribution 318system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 319system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 320system.membus.trans_dist::UpgradeReq 188 # Transaction distribution 321system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution 322system.membus.trans_dist::UpgradeResp 193 # Transaction distribution 323system.membus.trans_dist::ReadExReq 115222 # Transaction distribution 324system.membus.trans_dist::ReadExResp 115222 # Transaction distribution 325system.membus.trans_dist::BadAddressError 89 # Transaction distribution 326system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884476 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917708 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count::total 1001000 # Packet count per connected master and slave (bytes) 333system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) 334system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30720896 # Cumulative packet size per connected master and slave (bytes) 335system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30765036 # Cumulative packet size per connected master and slave (bytes) 336system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 337system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 338system.membus.pkt_size::total 33425324 # Cumulative packet size per connected master and slave (bytes) 339system.membus.snoops 158 # Total snoops (count) 340system.membus.snoop_fanout::samples 522030 # Request fanout histogram 341system.membus.snoop_fanout::mean 1 # Request fanout histogram 342system.membus.snoop_fanout::stdev 0 # Request fanout histogram 343system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 344system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 345system.membus.snoop_fanout::1 522030 100.00% 100.00% # Request fanout histogram 346system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 347system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 348system.membus.snoop_fanout::min_value 1 # Request fanout histogram 349system.membus.snoop_fanout::max_value 1 # Request fanout histogram 350system.membus.snoop_fanout::total 522030 # Request fanout histogram 351system.membus.reqLayer0.occupancy 31457000 # Layer occupancy (ticks) 352system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 353system.membus.reqLayer1.occupancy 1484421249 # Layer occupancy (ticks) 354system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 355system.membus.reqLayer2.occupancy 110500 # Layer occupancy (ticks) 356system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 357system.membus.respLayer1.occupancy 3754388311 # Layer occupancy (ticks) 358system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 359system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) 360system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 361system.iocache.tags.replacements 41685 # number of replacements 362system.iocache.tags.tagsinuse 1.260487 # Cycle average of tags in use 363system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 364system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 365system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 366system.iocache.tags.warmup_cycle 1709355301000 # Cycle when the warmup percentage was hit. 367system.iocache.tags.occ_blocks::tsunami.ide 1.260487 # Average occupied blocks per requestor 368system.iocache.tags.occ_percent::tsunami.ide 0.078780 # Average percentage of cache occupancy 369system.iocache.tags.occ_percent::total 0.078780 # Average percentage of cache occupancy 370system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 371system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 372system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 373system.iocache.tags.tag_accesses 376213 # Number of tag accesses 374system.iocache.tags.data_accesses 376213 # Number of data accesses 375system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 376system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 377system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 378system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 379system.iocache.WriteInvalidateReq_misses::tsunami.ide 86 # number of WriteInvalidateReq misses 380system.iocache.WriteInvalidateReq_misses::total 86 # number of WriteInvalidateReq misses 381system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 382system.iocache.demand_misses::total 173 # number of demand (read+write) misses 383system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 384system.iocache.overall_misses::total 173 # number of overall misses 385system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 386system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 387system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 388system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 389system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 390system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 391system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 392system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 393system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41638 # number of WriteInvalidateReq accesses(hits+misses) 394system.iocache.WriteInvalidateReq_accesses::total 41638 # number of WriteInvalidateReq accesses(hits+misses) 395system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 396system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 397system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 398system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 399system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 400system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 401system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.002065 # miss rate for WriteInvalidateReq accesses 402system.iocache.WriteInvalidateReq_miss_rate::total 0.002065 # miss rate for WriteInvalidateReq accesses 403system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 404system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 405system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 406system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 407system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 408system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 409system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 410system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 411system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 412system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 413system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 414system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.iocache.blocked::no_targets 0 # number of cycles access was blocked 417system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.iocache.fast_writes 41552 # number of fast writes performed 420system.iocache.cache_copies 0 # number of cache copies performed 421system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 422system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 423system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 424system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 425system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 426system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 427system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 428system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 429system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles 430system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles 431system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 432system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 433system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 434system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 435system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 436system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 437system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 438system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 439system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 440system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 441system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 442system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 443system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency 444system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 445system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 446system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 447system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 448system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 449system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 450system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 451system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 452system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 453system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 454system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 455system.disk0.dma_write_txs 395 # Number of DMA write transactions. 456system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 457system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 458system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 459system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 460system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 461system.disk2.dma_write_txs 1 # Number of DMA write transactions. 462system.cpu.branchPred.lookups 17804968 # Number of BP lookups 463system.cpu.branchPred.condPredicted 15499600 # Number of conditional branches predicted 464system.cpu.branchPred.condIncorrect 379466 # Number of conditional branches incorrect 465system.cpu.branchPred.BTBLookups 11923628 # Number of BTB lookups 466system.cpu.branchPred.BTBHits 5932721 # Number of BTB hits | 286system.physmem.actEnergy::0 239795640 # Energy for activate commands per rank (pJ) 287system.physmem.actEnergy::1 242449200 # Energy for activate commands per rank (pJ) 288system.physmem.preEnergy::0 130840875 # Energy for precharge commands per rank (pJ) 289system.physmem.preEnergy::1 132288750 # Energy for precharge commands per rank (pJ) 290system.physmem.readEnergy::0 1579484400 # Energy for read commands per rank (pJ) 291system.physmem.readEnergy::1 1569391200 # Energy for read commands per rank (pJ) 292system.physmem.writeEnergy::0 503139600 # Energy for write commands per rank (pJ) 293system.physmem.writeEnergy::1 513144720 # Energy for write commands per rank (pJ) 294system.physmem.refreshEnergy::0 121423785600 # Energy for refresh commands per rank (pJ) 295system.physmem.refreshEnergy::1 121423785600 # Energy for refresh commands per rank (pJ) 296system.physmem.actBackEnergy::0 55719498420 # Energy for active background per rank (pJ) 297system.physmem.actBackEnergy::1 55486362150 # Energy for active background per rank (pJ) 298system.physmem.preBackEnergy::0 1066550433000 # Energy for precharge background per rank (pJ) 299system.physmem.preBackEnergy::1 1066754938500 # Energy for precharge background per rank (pJ) 300system.physmem.totalEnergy::0 1246146977535 # Total energy per rank (pJ) 301system.physmem.totalEnergy::1 1246122360120 # Total energy per rank (pJ) 302system.physmem.averagePower::0 670.315549 # Core power per rank (mW) 303system.physmem.averagePower::1 670.302307 # Core power per rank (mW) 304system.cpu.branchPred.lookups 17761302 # Number of BP lookups 305system.cpu.branchPred.condPredicted 15456576 # Number of conditional branches predicted 306system.cpu.branchPred.condIncorrect 379954 # Number of conditional branches incorrect 307system.cpu.branchPred.BTBLookups 12009119 # Number of BTB lookups 308system.cpu.branchPred.BTBHits 5937139 # Number of BTB hits |
| 467system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 309system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 468system.cpu.branchPred.BTBHitPct 49.756005 # BTB Hit Percentage 469system.cpu.branchPred.usedRAS 914118 # Number of times the RAS was used to get a target. 470system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions. | 310system.cpu.branchPred.BTBHitPct 49.438589 # BTB Hit Percentage 311system.cpu.branchPred.usedRAS 914399 # Number of times the RAS was used to get a target. 312system.cpu.branchPred.RASInCorrect 21305 # Number of incorrect RAS predictions. |
| 471system.cpu_clk_domain.clock 500 # Clock period in ticks 472system.cpu.dtb.fetch_hits 0 # ITB hits 473system.cpu.dtb.fetch_misses 0 # ITB misses 474system.cpu.dtb.fetch_acv 0 # ITB acv 475system.cpu.dtb.fetch_accesses 0 # ITB accesses | 313system.cpu_clk_domain.clock 500 # Clock period in ticks 314system.cpu.dtb.fetch_hits 0 # ITB hits 315system.cpu.dtb.fetch_misses 0 # ITB misses 316system.cpu.dtb.fetch_acv 0 # ITB acv 317system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 476system.cpu.dtb.read_hits 10302215 # DTB read hits 477system.cpu.dtb.read_misses 41309 # DTB read misses 478system.cpu.dtb.read_acv 513 # DTB read access violations 479system.cpu.dtb.read_accesses 965594 # DTB read accesses 480system.cpu.dtb.write_hits 6646492 # DTB write hits 481system.cpu.dtb.write_misses 9371 # DTB write misses 482system.cpu.dtb.write_acv 419 # DTB write access violations 483system.cpu.dtb.write_accesses 342338 # DTB write accesses 484system.cpu.dtb.data_hits 16948707 # DTB hits 485system.cpu.dtb.data_misses 50680 # DTB misses 486system.cpu.dtb.data_acv 932 # DTB access violations 487system.cpu.dtb.data_accesses 1307932 # DTB accesses 488system.cpu.itb.fetch_hits 1774610 # ITB hits 489system.cpu.itb.fetch_misses 34401 # ITB misses 490system.cpu.itb.fetch_acv 653 # ITB acv 491system.cpu.itb.fetch_accesses 1809011 # ITB accesses | 318system.cpu.dtb.read_hits 10308188 # DTB read hits 319system.cpu.dtb.read_misses 41379 # DTB read misses 320system.cpu.dtb.read_acv 521 # DTB read access violations 321system.cpu.dtb.read_accesses 967155 # DTB read accesses 322system.cpu.dtb.write_hits 6646702 # DTB write hits 323system.cpu.dtb.write_misses 9325 # DTB write misses 324system.cpu.dtb.write_acv 410 # DTB write access violations 325system.cpu.dtb.write_accesses 342603 # DTB write accesses 326system.cpu.dtb.data_hits 16954890 # DTB hits 327system.cpu.dtb.data_misses 50704 # DTB misses 328system.cpu.dtb.data_acv 931 # DTB access violations 329system.cpu.dtb.data_accesses 1309758 # DTB accesses 330system.cpu.itb.fetch_hits 1770443 # ITB hits 331system.cpu.itb.fetch_misses 36092 # ITB misses 332system.cpu.itb.fetch_acv 664 # ITB acv 333system.cpu.itb.fetch_accesses 1806535 # ITB accesses |
| 492system.cpu.itb.read_hits 0 # DTB read hits 493system.cpu.itb.read_misses 0 # DTB read misses 494system.cpu.itb.read_acv 0 # DTB read access violations 495system.cpu.itb.read_accesses 0 # DTB read accesses 496system.cpu.itb.write_hits 0 # DTB write hits 497system.cpu.itb.write_misses 0 # DTB write misses 498system.cpu.itb.write_acv 0 # DTB write access violations 499system.cpu.itb.write_accesses 0 # DTB write accesses 500system.cpu.itb.data_hits 0 # DTB hits 501system.cpu.itb.data_misses 0 # DTB misses 502system.cpu.itb.data_acv 0 # DTB access violations 503system.cpu.itb.data_accesses 0 # DTB accesses | 334system.cpu.itb.read_hits 0 # DTB read hits 335system.cpu.itb.read_misses 0 # DTB read misses 336system.cpu.itb.read_acv 0 # DTB read access violations 337system.cpu.itb.read_accesses 0 # DTB read accesses 338system.cpu.itb.write_hits 0 # DTB write hits 339system.cpu.itb.write_misses 0 # DTB write misses 340system.cpu.itb.write_acv 0 # DTB write access violations 341system.cpu.itb.write_accesses 0 # DTB write accesses 342system.cpu.itb.data_hits 0 # DTB hits 343system.cpu.itb.data_misses 0 # DTB misses 344system.cpu.itb.data_acv 0 # DTB access violations 345system.cpu.itb.data_accesses 0 # DTB accesses |
| 504system.cpu.numCycles 118301061 # number of cpu cycles simulated | 346system.cpu.numCycles 118298016 # number of cpu cycles simulated |
| 505system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 506system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 347system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 348system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 507system.cpu.fetch.icacheStallCycles 29562966 # Number of cycles fetch is stalled on an Icache miss 508system.cpu.fetch.Insts 78094807 # Number of instructions fetch has processed 509system.cpu.fetch.Branches 17804968 # Number of branches that fetch encountered 510system.cpu.fetch.predictedBranches 6846839 # Number of branches that fetch has predicted taken 511system.cpu.fetch.Cycles 80553195 # Number of cycles fetch has run and was not squashing or blocked 512system.cpu.fetch.SquashCycles 1252096 # Number of cycles fetch has spent squashing 513system.cpu.fetch.TlbCycles 1416 # Number of cycles fetch has spent waiting for tlb 514system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 515system.cpu.fetch.PendingTrapStallCycles 1649882 # Number of stall cycles due to pending traps 516system.cpu.fetch.PendingQuiesceStallCycles 450417 # Number of stall cycles due to pending quiesce instructions 517system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR 518system.cpu.fetch.CacheLines 9025532 # Number of cache lines fetched 519system.cpu.fetch.IcacheSquashes 274121 # Number of outstanding Icache misses that were squashed 520system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed 521system.cpu.fetch.rateDist::samples 112872082 # Number of instructions fetched each cycle (Total) 522system.cpu.fetch.rateDist::mean 0.691888 # Number of instructions fetched each cycle (Total) 523system.cpu.fetch.rateDist::stdev 2.011514 # Number of instructions fetched each cycle (Total) | 349system.cpu.fetch.icacheStallCycles 29541198 # Number of cycles fetch is stalled on an Icache miss 350system.cpu.fetch.Insts 78055768 # Number of instructions fetch has processed 351system.cpu.fetch.Branches 17761302 # Number of branches that fetch encountered 352system.cpu.fetch.predictedBranches 6851538 # Number of branches that fetch has predicted taken 353system.cpu.fetch.Cycles 80476428 # Number of cycles fetch has run and was not squashing or blocked 354system.cpu.fetch.SquashCycles 1253224 # Number of cycles fetch has spent squashing 355system.cpu.fetch.TlbCycles 1384 # Number of cycles fetch has spent waiting for tlb 356system.cpu.fetch.MiscStallCycles 28562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 357system.cpu.fetch.PendingTrapStallCycles 1737629 # Number of stall cycles due to pending traps 358system.cpu.fetch.PendingQuiesceStallCycles 451562 # Number of stall cycles due to pending quiesce instructions 359system.cpu.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR 360system.cpu.fetch.CacheLines 9019799 # Number of cache lines fetched 361system.cpu.fetch.IcacheSquashes 273133 # Number of outstanding Icache misses that were squashed 362system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 363system.cpu.fetch.rateDist::samples 112863592 # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::mean 0.691594 # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::stdev 2.010851 # Number of instructions fetched each cycle (Total) |
| 524system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 366system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 525system.cpu.fetch.rateDist::0 98296528 87.09% 87.09% # Number of instructions fetched each cycle (Total) 526system.cpu.fetch.rateDist::1 933530 0.83% 87.91% # Number of instructions fetched each cycle (Total) 527system.cpu.fetch.rateDist::2 1975700 1.75% 89.66% # Number of instructions fetched each cycle (Total) 528system.cpu.fetch.rateDist::3 908755 0.81% 90.47% # Number of instructions fetched each cycle (Total) 529system.cpu.fetch.rateDist::4 2800334 2.48% 92.95% # Number of instructions fetched each cycle (Total) 530system.cpu.fetch.rateDist::5 638924 0.57% 93.52% # Number of instructions fetched each cycle (Total) 531system.cpu.fetch.rateDist::6 725896 0.64% 94.16% # Number of instructions fetched each cycle (Total) 532system.cpu.fetch.rateDist::7 1007040 0.89% 95.05% # Number of instructions fetched each cycle (Total) 533system.cpu.fetch.rateDist::8 5585375 4.95% 100.00% # Number of instructions fetched each cycle (Total) | 367system.cpu.fetch.rateDist::0 98289284 87.09% 87.09% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::1 935566 0.83% 87.92% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::2 1976201 1.75% 89.67% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::3 911928 0.81% 90.47% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::4 2795335 2.48% 92.95% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::5 642698 0.57% 93.52% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::6 727750 0.64% 94.17% # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.rateDist::7 1007954 0.89% 95.06% # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::8 5576876 4.94% 100.00% # Number of instructions fetched each cycle (Total) |
| 534system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 535system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 536system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 376system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 537system.cpu.fetch.rateDist::total 112872082 # Number of instructions fetched each cycle (Total) 538system.cpu.fetch.branchRate 0.150506 # Number of branch fetches per cycle 539system.cpu.fetch.rate 0.660136 # Number of inst fetches per cycle 540system.cpu.decode.IdleCycles 24068860 # Number of cycles decode is idle 541system.cpu.decode.BlockedCycles 76820836 # Number of cycles decode is blocked 542system.cpu.decode.RunCycles 9500551 # Number of cycles decode is running 543system.cpu.decode.UnblockCycles 1898196 # Number of cycles decode is unblocking 544system.cpu.decode.SquashCycles 583638 # Number of cycles decode is squashing 545system.cpu.decode.BranchResolved 588301 # Number of times decode resolved a branch 546system.cpu.decode.BranchMispred 42850 # Number of times decode detected a branch misprediction 547system.cpu.decode.DecodedInsts 68299285 # Number of instructions handled by decode 548system.cpu.decode.SquashedInsts 133126 # Number of squashed instructions handled by decode 549system.cpu.rename.SquashCycles 583638 # Number of cycles rename is squashing 550system.cpu.rename.IdleCycles 24994916 # Number of cycles rename is idle 551system.cpu.rename.BlockCycles 47249741 # Number of cycles rename is blocking 552system.cpu.rename.serializeStallCycles 20742683 # count of cycles rename stalled for serializing inst 553system.cpu.rename.RunCycles 10385328 # Number of cycles rename is running 554system.cpu.rename.UnblockCycles 8915774 # Number of cycles rename is unblocking 555system.cpu.rename.RenamedInsts 65865702 # Number of instructions processed by rename 556system.cpu.rename.ROBFullEvents 202022 # Number of times rename has blocked due to ROB full 557system.cpu.rename.IQFullEvents 2036806 # Number of times rename has blocked due to IQ full 558system.cpu.rename.LQFullEvents 141544 # Number of times rename has blocked due to LQ full 559system.cpu.rename.SQFullEvents 4770005 # Number of times rename has blocked due to SQ full 560system.cpu.rename.RenamedOperands 43944287 # Number of destination operands rename has renamed 561system.cpu.rename.RenameLookups 79812474 # Number of register rename lookups that rename has made 562system.cpu.rename.int_rename_lookups 79631676 # Number of integer rename lookups 563system.cpu.rename.fp_rename_lookups 168345 # Number of floating rename lookups 564system.cpu.rename.CommittedMaps 38137411 # Number of HB maps that are committed 565system.cpu.rename.UndoneMaps 5806868 # Number of HB maps that are undone due to squashing 566system.cpu.rename.serializingInsts 1690855 # count of serializing insts renamed 567system.cpu.rename.tempSerializingInsts 241233 # count of temporary serializing insts renamed 568system.cpu.rename.skidInsts 13548292 # count of insts added to the skid buffer 569system.cpu.memDep0.insertedLoads 10425085 # Number of loads inserted to the mem dependence unit. 570system.cpu.memDep0.insertedStores 6927485 # Number of stores inserted to the mem dependence unit. 571system.cpu.memDep0.conflictingLoads 1490397 # Number of conflicting loads. 572system.cpu.memDep0.conflictingStores 1054253 # Number of conflicting stores. 573system.cpu.iq.iqInstsAdded 58626057 # Number of instructions added to the IQ (excludes non-spec) 574system.cpu.iq.iqNonSpecInstsAdded 2139161 # Number of non-speculative instructions added to the IQ 575system.cpu.iq.iqInstsIssued 57592696 # Number of instructions issued 576system.cpu.iq.iqSquashedInstsIssued 51229 # Number of squashed instructions issued 577system.cpu.iq.iqSquashedInstsExamined 7502337 # Number of squashed instructions iterated over during squash; mainly for profiling 578system.cpu.iq.iqSquashedOperandsExamined 3486338 # Number of squashed operands that are examined and possibly removed from graph 579system.cpu.iq.iqSquashedNonSpecRemoved 1478017 # Number of squashed non-spec instructions that were removed 580system.cpu.iq.issued_per_cycle::samples 112872082 # Number of insts issued each cycle 581system.cpu.iq.issued_per_cycle::mean 0.510247 # Number of insts issued each cycle 582system.cpu.iq.issued_per_cycle::stdev 1.252928 # Number of insts issued each cycle | 379system.cpu.fetch.rateDist::total 112863592 # Number of instructions fetched each cycle (Total) 380system.cpu.fetch.branchRate 0.150140 # Number of branch fetches per cycle 381system.cpu.fetch.rate 0.659823 # Number of inst fetches per cycle 382system.cpu.decode.IdleCycles 24058379 # Number of cycles decode is idle 383system.cpu.decode.BlockedCycles 76821722 # Number of cycles decode is blocked 384system.cpu.decode.RunCycles 9496623 # Number of cycles decode is running 385system.cpu.decode.UnblockCycles 1902660 # Number of cycles decode is unblocking 386system.cpu.decode.SquashCycles 584207 # Number of cycles decode is squashing 387system.cpu.decode.BranchResolved 588094 # Number of times decode resolved a branch 388system.cpu.decode.BranchMispred 42817 # Number of times decode detected a branch misprediction 389system.cpu.decode.DecodedInsts 68303161 # Number of instructions handled by decode 390system.cpu.decode.SquashedInsts 133250 # Number of squashed instructions handled by decode 391system.cpu.rename.SquashCycles 584207 # Number of cycles rename is squashing 392system.cpu.rename.IdleCycles 24982800 # Number of cycles rename is idle 393system.cpu.rename.BlockCycles 47259981 # Number of cycles rename is blocking 394system.cpu.rename.serializeStallCycles 20734687 # count of cycles rename stalled for serializing inst 395system.cpu.rename.RunCycles 10387203 # Number of cycles rename is running 396system.cpu.rename.UnblockCycles 8914712 # Number of cycles rename is unblocking 397system.cpu.rename.RenamedInsts 65869472 # Number of instructions processed by rename 398system.cpu.rename.ROBFullEvents 202922 # Number of times rename has blocked due to ROB full 399system.cpu.rename.IQFullEvents 2041149 # Number of times rename has blocked due to IQ full 400system.cpu.rename.LQFullEvents 141248 # Number of times rename has blocked due to LQ full 401system.cpu.rename.SQFullEvents 4766165 # Number of times rename has blocked due to SQ full 402system.cpu.rename.RenamedOperands 43946104 # Number of destination operands rename has renamed 403system.cpu.rename.RenameLookups 79818079 # Number of register rename lookups that rename has made 404system.cpu.rename.int_rename_lookups 79637315 # Number of integer rename lookups 405system.cpu.rename.fp_rename_lookups 168311 # Number of floating rename lookups 406system.cpu.rename.CommittedMaps 38139253 # Number of HB maps that are committed 407system.cpu.rename.UndoneMaps 5806843 # Number of HB maps that are undone due to squashing 408system.cpu.rename.serializingInsts 1691151 # count of serializing insts renamed 409system.cpu.rename.tempSerializingInsts 241440 # count of temporary serializing insts renamed 410system.cpu.rename.skidInsts 13536828 # count of insts added to the skid buffer 411system.cpu.memDep0.insertedLoads 10424364 # Number of loads inserted to the mem dependence unit. 412system.cpu.memDep0.insertedStores 6928356 # Number of stores inserted to the mem dependence unit. 413system.cpu.memDep0.conflictingLoads 1483959 # Number of conflicting loads. 414system.cpu.memDep0.conflictingStores 1059889 # Number of conflicting stores. 415system.cpu.iq.iqInstsAdded 58630025 # Number of instructions added to the IQ (excludes non-spec) 416system.cpu.iq.iqNonSpecInstsAdded 2138995 # Number of non-speculative instructions added to the IQ 417system.cpu.iq.iqInstsIssued 57603342 # Number of instructions issued 418system.cpu.iq.iqSquashedInstsIssued 50950 # Number of squashed instructions issued 419system.cpu.iq.iqSquashedInstsExamined 7503583 # Number of squashed instructions iterated over during squash; mainly for profiling 420system.cpu.iq.iqSquashedOperandsExamined 3485287 # Number of squashed operands that are examined and possibly removed from graph 421system.cpu.iq.iqSquashedNonSpecRemoved 1477804 # Number of squashed non-spec instructions that were removed 422system.cpu.iq.issued_per_cycle::samples 112863592 # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::mean 0.510380 # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::stdev 1.252962 # Number of insts issued each cycle |
| 583system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 425system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 584system.cpu.iq.issued_per_cycle::0 89394835 79.20% 79.20% # Number of insts issued each cycle 585system.cpu.iq.issued_per_cycle::1 10016384 8.87% 88.07% # Number of insts issued each cycle 586system.cpu.iq.issued_per_cycle::2 4304507 3.81% 91.89% # Number of insts issued each cycle 587system.cpu.iq.issued_per_cycle::3 2950730 2.61% 94.50% # Number of insts issued each cycle 588system.cpu.iq.issued_per_cycle::4 3082787 2.73% 97.23% # Number of insts issued each cycle 589system.cpu.iq.issued_per_cycle::5 1592384 1.41% 98.64% # Number of insts issued each cycle 590system.cpu.iq.issued_per_cycle::6 1013037 0.90% 99.54% # Number of insts issued each cycle 591system.cpu.iq.issued_per_cycle::7 395526 0.35% 99.89% # Number of insts issued each cycle 592system.cpu.iq.issued_per_cycle::8 121892 0.11% 100.00% # Number of insts issued each cycle | 426system.cpu.iq.issued_per_cycle::0 89383207 79.20% 79.20% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::1 10013548 8.87% 88.07% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::2 4301377 3.81% 91.88% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::3 2962557 2.62% 94.50% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::4 3086274 2.73% 97.24% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::5 1586017 1.41% 98.64% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::6 1012124 0.90% 99.54% # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::7 396460 0.35% 99.89% # Number of insts issued each cycle 434system.cpu.iq.issued_per_cycle::8 122028 0.11% 100.00% # Number of insts issued each cycle |
| 593system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 594system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 595system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 435system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 436system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 596system.cpu.iq.issued_per_cycle::total 112872082 # Number of insts issued each cycle | 438system.cpu.iq.issued_per_cycle::total 112863592 # Number of insts issued each cycle |
| 597system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 439system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 598system.cpu.iq.fu_full::IntAlu 212963 18.82% 18.82% # attempts to use FU when none available 599system.cpu.iq.fu_full::IntMult 0 0.00% 18.82% # attempts to use FU when none available 600system.cpu.iq.fu_full::IntDiv 0 0.00% 18.82% # attempts to use FU when none available 601system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.82% # attempts to use FU when none available 602system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.82% # attempts to use FU when none available 603system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.82% # attempts to use FU when none available 604system.cpu.iq.fu_full::FloatMult 0 0.00% 18.82% # attempts to use FU when none available 605system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.82% # attempts to use FU when none available 606system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.82% # attempts to use FU when none available 607system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.82% # attempts to use FU when none available 608system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.82% # attempts to use FU when none available 609system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.82% # attempts to use FU when none available 610system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.82% # attempts to use FU when none available 611system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.82% # attempts to use FU when none available 612system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.82% # attempts to use FU when none available 613system.cpu.iq.fu_full::SimdMult 0 0.00% 18.82% # attempts to use FU when none available 614system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.82% # attempts to use FU when none available 615system.cpu.iq.fu_full::SimdShift 0 0.00% 18.82% # attempts to use FU when none available 616system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.82% # attempts to use FU when none available 617system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.82% # attempts to use FU when none available 618system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.82% # attempts to use FU when none available 619system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.82% # attempts to use FU when none available 620system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.82% # attempts to use FU when none available 621system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.82% # attempts to use FU when none available 622system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.82% # attempts to use FU when none available 623system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.82% # attempts to use FU when none available 624system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.82% # attempts to use FU when none available 625system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.82% # attempts to use FU when none available 626system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.82% # attempts to use FU when none available 627system.cpu.iq.fu_full::MemRead 545078 48.16% 66.97% # attempts to use FU when none available 628system.cpu.iq.fu_full::MemWrite 373836 33.03% 100.00% # attempts to use FU when none available | 440system.cpu.iq.fu_full::IntAlu 213045 18.77% 18.77% # attempts to use FU when none available 441system.cpu.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available 442system.cpu.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available 445system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available 446system.cpu.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available 447system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available 448system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available 469system.cpu.iq.fu_full::MemRead 547519 48.24% 67.01% # attempts to use FU when none available 470system.cpu.iq.fu_full::MemWrite 374446 32.99% 100.00% # attempts to use FU when none available |
| 629system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 630system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 631system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued | 471system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 472system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 473system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued |
| 632system.cpu.iq.FU_type_0::IntAlu 39097776 67.89% 67.90% # Type of FU issued 633system.cpu.iq.FU_type_0::IntMult 61804 0.11% 68.01% # Type of FU issued 634system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued 635system.cpu.iq.FU_type_0::FloatAdd 38376 0.07% 68.07% # Type of FU issued | 474system.cpu.iq.FU_type_0::IntAlu 39102059 67.88% 67.89% # Type of FU issued 475system.cpu.iq.FU_type_0::IntMult 61815 0.11% 68.00% # Type of FU issued 476system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.00% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatAdd 38377 0.07% 68.07% # Type of FU issued |
| 636system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued 637system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued 638system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued | 478system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued 479system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued 480system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued |
| 639system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.08% # Type of FU issued 640system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued 641system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued 642system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued 643system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued 644system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued 645system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued 646system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued 647system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued 648system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued 649system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued 650system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued 651system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued 652system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued 653system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued 654system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued 655system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued 656system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued 657system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued 658system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.08% # Type of FU issued 659system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued 660system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued 661system.cpu.iq.FU_type_0::MemRead 10712581 18.60% 86.68% # Type of FU issued 662system.cpu.iq.FU_type_0::MemWrite 6722276 11.67% 98.35% # Type of FU issued 663system.cpu.iq.FU_type_0::IprAccess 948961 1.65% 100.00% # Type of FU issued | 481system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.07% # Type of FU issued 482system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.07% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.07% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.07% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.07% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.07% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.07% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.07% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.07% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.07% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.07% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.07% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued 503system.cpu.iq.FU_type_0::MemRead 10718615 18.61% 86.68% # Type of FU issued 504system.cpu.iq.FU_type_0::MemWrite 6722522 11.67% 98.35% # Type of FU issued 505system.cpu.iq.FU_type_0::IprAccess 949032 1.65% 100.00% # Type of FU issued |
| 664system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 506system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 665system.cpu.iq.FU_type_0::total 57592696 # Type of FU issued 666system.cpu.iq.rate 0.486832 # Inst issue rate 667system.cpu.iq.fu_busy_cnt 1131877 # FU busy when requested 668system.cpu.iq.fu_busy_rate 0.019653 # FU busy rate (busy events/executed inst) 669system.cpu.iq.int_inst_queue_reads 228528169 # Number of integer instruction queue reads 670system.cpu.iq.int_inst_queue_writes 67952558 # Number of integer instruction queue writes 671system.cpu.iq.int_inst_queue_wakeup_accesses 55916727 # Number of integer instruction queue wakeup accesses 672system.cpu.iq.fp_inst_queue_reads 712410 # Number of floating instruction queue reads 673system.cpu.iq.fp_inst_queue_writes 334609 # Number of floating instruction queue writes 674system.cpu.iq.fp_inst_queue_wakeup_accesses 328997 # Number of floating instruction queue wakeup accesses 675system.cpu.iq.int_alu_accesses 58334880 # Number of integer alu accesses 676system.cpu.iq.fp_alu_accesses 382407 # Number of floating point alu accesses 677system.cpu.iew.lsq.thread0.forwLoads 639606 # Number of loads that had data forwarded from stores | 507system.cpu.iq.FU_type_0::total 57603342 # Type of FU issued 508system.cpu.iq.rate 0.486934 # Inst issue rate 509system.cpu.iq.fu_busy_cnt 1135010 # FU busy when requested 510system.cpu.iq.fu_busy_rate 0.019704 # FU busy rate (busy events/executed inst) 511system.cpu.iq.int_inst_queue_reads 228544022 # Number of integer instruction queue reads 512system.cpu.iq.int_inst_queue_writes 67957775 # Number of integer instruction queue writes 513system.cpu.iq.int_inst_queue_wakeup_accesses 55921178 # Number of integer instruction queue wakeup accesses 514system.cpu.iq.fp_inst_queue_reads 712213 # Number of floating instruction queue reads 515system.cpu.iq.fp_inst_queue_writes 334464 # Number of floating instruction queue writes 516system.cpu.iq.fp_inst_queue_wakeup_accesses 328973 # Number of floating instruction queue wakeup accesses 517system.cpu.iq.int_alu_accesses 58348779 # Number of integer alu accesses 518system.cpu.iq.fp_alu_accesses 382287 # Number of floating point alu accesses 519system.cpu.iew.lsq.thread0.forwLoads 639736 # Number of loads that had data forwarded from stores |
| 678system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 520system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 679system.cpu.iew.lsq.thread0.squashedLoads 1340629 # Number of loads squashed 680system.cpu.iew.lsq.thread0.ignoredResponses 4088 # Number of memory responses ignored because the instruction is squashed | 521system.cpu.iew.lsq.thread0.squashedLoads 1339690 # Number of loads squashed 522system.cpu.iew.lsq.thread0.ignoredResponses 4038 # Number of memory responses ignored because the instruction is squashed |
| 681system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations | 523system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations |
| 682system.cpu.iew.lsq.thread0.squashedStores 553798 # Number of stores squashed | 524system.cpu.iew.lsq.thread0.squashedStores 554552 # Number of stores squashed |
| 683system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 684system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 525system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 526system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 685system.cpu.iew.lsq.thread0.rescheduledLoads 18287 # Number of loads that were rescheduled 686system.cpu.iew.lsq.thread0.cacheBlocked 539247 # Number of times an access to memory failed due to the cache being blocked | 527system.cpu.iew.lsq.thread0.rescheduledLoads 18285 # Number of loads that were rescheduled 528system.cpu.iew.lsq.thread0.cacheBlocked 544771 # Number of times an access to memory failed due to the cache being blocked |
| 687system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 529system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 688system.cpu.iew.iewSquashCycles 583638 # Number of cycles IEW is squashing 689system.cpu.iew.iewBlockCycles 44307486 # Number of cycles IEW is blocking 690system.cpu.iew.iewUnblockCycles 616008 # Number of cycles IEW is unblocking 691system.cpu.iew.iewDispatchedInsts 64468948 # Number of instructions dispatched to IQ 692system.cpu.iew.iewDispSquashedInsts 145079 # Number of squashed instructions skipped by dispatch 693system.cpu.iew.iewDispLoadInsts 10425085 # Number of dispatched load instructions 694system.cpu.iew.iewDispStoreInsts 6927485 # Number of dispatched store instructions 695system.cpu.iew.iewDispNonSpecInsts 1890835 # Number of dispatched non-speculative instructions 696system.cpu.iew.iewIQFullEvents 42893 # Number of times the IQ has become full, causing a stall 697system.cpu.iew.iewLSQFullEvents 369751 # Number of times the LSQ has become full, causing a stall | 530system.cpu.iew.iewSquashCycles 584207 # Number of cycles IEW is squashing 531system.cpu.iew.iewBlockCycles 44318330 # Number of cycles IEW is blocking 532system.cpu.iew.iewUnblockCycles 613096 # Number of cycles IEW is unblocking 533system.cpu.iew.iewDispatchedInsts 64473181 # Number of instructions dispatched to IQ 534system.cpu.iew.iewDispSquashedInsts 145267 # Number of squashed instructions skipped by dispatch 535system.cpu.iew.iewDispLoadInsts 10424364 # Number of dispatched load instructions 536system.cpu.iew.iewDispStoreInsts 6928356 # Number of dispatched store instructions 537system.cpu.iew.iewDispNonSpecInsts 1890724 # Number of dispatched non-speculative instructions 538system.cpu.iew.iewIQFullEvents 42751 # Number of times the IQ has become full, causing a stall 539system.cpu.iew.iewLSQFullEvents 366947 # Number of times the LSQ has become full, causing a stall |
| 698system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations | 540system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations |
| 699system.cpu.iew.predictedTakenIncorrect 190429 # Number of branches that were predicted taken incorrectly 700system.cpu.iew.predictedNotTakenIncorrect 410127 # Number of branches that were predicted not taken incorrectly 701system.cpu.iew.branchMispredicts 600556 # Number of branch mispredicts detected at execute 702system.cpu.iew.iewExecutedInsts 57009373 # Number of executed instructions 703system.cpu.iew.iewExecLoadInsts 10371242 # Number of load instructions executed 704system.cpu.iew.iewExecSquashedInsts 583322 # Number of squashed instructions skipped in execute | 541system.cpu.iew.predictedTakenIncorrect 190952 # Number of branches that were predicted taken incorrectly 542system.cpu.iew.predictedNotTakenIncorrect 410451 # Number of branches that were predicted not taken incorrectly 543system.cpu.iew.branchMispredicts 601403 # Number of branch mispredicts detected at execute 544system.cpu.iew.iewExecutedInsts 57018878 # Number of executed instructions 545system.cpu.iew.iewExecLoadInsts 10377294 # Number of load instructions executed 546system.cpu.iew.iewExecSquashedInsts 584463 # Number of squashed instructions skipped in execute |
| 705system.cpu.iew.exec_swp 0 # number of swp insts executed | 547system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 706system.cpu.iew.exec_nop 3703730 # number of nop insts executed 707system.cpu.iew.exec_refs 17042240 # number of memory reference insts executed 708system.cpu.iew.exec_branches 8981920 # Number of branches executed 709system.cpu.iew.exec_stores 6670998 # Number of stores executed 710system.cpu.iew.exec_rate 0.481901 # Inst execution rate 711system.cpu.iew.wb_sent 56380366 # cumulative count of insts sent to commit 712system.cpu.iew.wb_count 56245724 # cumulative count of insts written-back 713system.cpu.iew.wb_producers 28936691 # num instructions producing a value 714system.cpu.iew.wb_consumers 40310167 # num instructions consuming a value | 548system.cpu.iew.exec_nop 3704161 # number of nop insts executed 549system.cpu.iew.exec_refs 17048455 # number of memory reference insts executed 550system.cpu.iew.exec_branches 8982580 # Number of branches executed 551system.cpu.iew.exec_stores 6671161 # Number of stores executed 552system.cpu.iew.exec_rate 0.481994 # Inst execution rate 553system.cpu.iew.wb_sent 56384919 # cumulative count of insts sent to commit 554system.cpu.iew.wb_count 56250151 # cumulative count of insts written-back 555system.cpu.iew.wb_producers 28947314 # num instructions producing a value 556system.cpu.iew.wb_consumers 40326252 # num instructions consuming a value |
| 715system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 557system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 716system.cpu.iew.wb_rate 0.475446 # insts written-back per cycle 717system.cpu.iew.wb_fanout 0.717851 # average fanout of values written-back | 558system.cpu.iew.wb_rate 0.475495 # insts written-back per cycle 559system.cpu.iew.wb_fanout 0.717828 # average fanout of values written-back |
| 718system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 560system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 719system.cpu.commit.commitSquashedInsts 8239182 # The number of squashed insts skipped by commit 720system.cpu.commit.commitNonSpecStalls 661144 # The number of times commit has been forced to stall to communicate backwards 721system.cpu.commit.branchMispredicts 548042 # The number of times a branch was mispredicted 722system.cpu.commit.committed_per_cycle::samples 111437316 # Number of insts commited each cycle 723system.cpu.commit.committed_per_cycle::mean 0.503568 # Number of insts commited each cycle 724system.cpu.commit.committed_per_cycle::stdev 1.455315 # Number of insts commited each cycle | 561system.cpu.commit.commitSquashedInsts 8239076 # The number of squashed insts skipped by commit 562system.cpu.commit.commitNonSpecStalls 661191 # The number of times commit has been forced to stall to communicate backwards 563system.cpu.commit.branchMispredicts 548552 # The number of times a branch was mispredicted 564system.cpu.commit.committed_per_cycle::samples 111427799 # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::mean 0.503633 # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::stdev 1.455266 # Number of insts commited each cycle |
| 725system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 567system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 726system.cpu.commit.committed_per_cycle::0 91810154 82.39% 82.39% # Number of insts commited each cycle 727system.cpu.commit.committed_per_cycle::1 7802563 7.00% 89.39% # Number of insts commited each cycle 728system.cpu.commit.committed_per_cycle::2 4132031 3.71% 93.10% # Number of insts commited each cycle 729system.cpu.commit.committed_per_cycle::3 2155493 1.93% 95.03% # Number of insts commited each cycle 730system.cpu.commit.committed_per_cycle::4 1853584 1.66% 96.69% # Number of insts commited each cycle 731system.cpu.commit.committed_per_cycle::5 616181 0.55% 97.25% # Number of insts commited each cycle 732system.cpu.commit.committed_per_cycle::6 467348 0.42% 97.67% # Number of insts commited each cycle 733system.cpu.commit.committed_per_cycle::7 515869 0.46% 98.13% # Number of insts commited each cycle 734system.cpu.commit.committed_per_cycle::8 2084093 1.87% 100.00% # Number of insts commited each cycle | 568system.cpu.commit.committed_per_cycle::0 91796177 82.38% 82.38% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::1 7808087 7.01% 89.39% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::2 4129534 3.71% 93.10% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::3 2155296 1.93% 95.03% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::4 1855711 1.67% 96.69% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::5 615462 0.55% 97.25% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::6 470761 0.42% 97.67% # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::7 513166 0.46% 98.13% # Number of insts commited each cycle 576system.cpu.commit.committed_per_cycle::8 2083605 1.87% 100.00% # Number of insts commited each cycle |
| 735system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 736system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 737system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 577system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 579system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 738system.cpu.commit.committed_per_cycle::total 111437316 # Number of insts commited each cycle 739system.cpu.commit.committedInsts 56116260 # Number of instructions committed 740system.cpu.commit.committedOps 56116260 # Number of ops (including micro ops) committed | 580system.cpu.commit.committed_per_cycle::total 111427799 # Number of insts commited each cycle 581system.cpu.commit.committedInsts 56118765 # Number of instructions committed 582system.cpu.commit.committedOps 56118765 # Number of ops (including micro ops) committed |
| 741system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 583system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 742system.cpu.commit.refs 15458143 # Number of memory references committed 743system.cpu.commit.loads 9084456 # Number of loads committed 744system.cpu.commit.membars 226334 # Number of memory barriers committed 745system.cpu.commit.branches 8434463 # Number of branches committed | 584system.cpu.commit.refs 15458478 # Number of memory references committed 585system.cpu.commit.loads 9084674 # Number of loads committed 586system.cpu.commit.membars 226351 # Number of memory barriers committed 587system.cpu.commit.branches 8434924 # Number of branches committed |
| 746system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. | 588system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. |
| 747system.cpu.commit.int_insts 51967854 # Number of committed integer instructions. 748system.cpu.commit.function_calls 739911 # Number of function calls committed. 749system.cpu.commit.op_class_0::No_OpClass 3195933 5.70% 5.70% # Class of committed instruction 750system.cpu.commit.op_class_0::IntAlu 36178550 64.47% 70.17% # Class of committed instruction 751system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.27% # Class of committed instruction | 589system.cpu.commit.int_insts 51970227 # Number of committed integer instructions. 590system.cpu.commit.function_calls 739937 # Number of function calls committed. 591system.cpu.commit.op_class_0::No_OpClass 3196003 5.70% 5.70% # Class of committed instruction 592system.cpu.commit.op_class_0::IntAlu 36180557 64.47% 70.17% # Class of committed instruction 593system.cpu.commit.op_class_0::IntMult 60666 0.11% 70.27% # Class of committed instruction |
| 752system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction 753system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction 754system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction 755system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction 756system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction 757system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 758system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 759system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 771system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 772system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 773system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 774system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 775system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 776system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 777system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 778system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction | 594system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction 596system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction 597system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction 598system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction 599system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 600system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 613system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 614system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 615system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 616system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 617system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 618system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 619system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 620system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction |
| 779system.cpu.commit.op_class_0::MemRead 9310790 16.59% 86.94% # Class of committed instruction 780system.cpu.commit.op_class_0::MemWrite 6379639 11.37% 98.31% # Class of committed instruction 781system.cpu.commit.op_class_0::IprAccess 948960 1.69% 100.00% # Class of committed instruction | 621system.cpu.commit.op_class_0::MemRead 9311025 16.59% 86.94% # Class of committed instruction 622system.cpu.commit.op_class_0::MemWrite 6379757 11.37% 98.31% # Class of committed instruction 623system.cpu.commit.op_class_0::IprAccess 949032 1.69% 100.00% # Class of committed instruction |
| 782system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 624system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 783system.cpu.commit.op_class_0::total 56116260 # Class of committed instruction 784system.cpu.commit.bw_lim_events 2084093 # number cycles where commit BW limit reached | 625system.cpu.commit.op_class_0::total 56118765 # Class of committed instruction 626system.cpu.commit.bw_lim_events 2083605 # number cycles where commit BW limit reached |
| 785system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 627system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 786system.cpu.rob.rob_reads 173459156 # The number of ROB reads 787system.cpu.rob.rob_writes 130141826 # The number of ROB writes 788system.cpu.timesIdled 576115 # Number of times that the entire CPU went into an idle state and unscheduled itself 789system.cpu.idleCycles 5428979 # Total number of cycles that the CPU has spent unscheduled due to idling 790system.cpu.quiesceCycles 3599776298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 791system.cpu.committedInsts 52927600 # Number of Instructions Simulated 792system.cpu.committedOps 52927600 # Number of Ops (including micro ops) Simulated 793system.cpu.cpi 2.235149 # CPI: Cycles Per Instruction 794system.cpu.cpi_total 2.235149 # CPI: Total CPI of All Threads 795system.cpu.ipc 0.447398 # IPC: Instructions Per Cycle 796system.cpu.ipc_total 0.447398 # IPC: Total IPC of All Threads 797system.cpu.int_regfile_reads 74648651 # number of integer regfile reads 798system.cpu.int_regfile_writes 40584029 # number of integer regfile writes 799system.cpu.fp_regfile_reads 166982 # number of floating regfile reads 800system.cpu.fp_regfile_writes 167600 # number of floating regfile writes 801system.cpu.misc_regfile_reads 2029015 # number of misc regfile reads 802system.cpu.misc_regfile_writes 939371 # number of misc regfile writes 803system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 804system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 805system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 806system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 807system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 808system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 809system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 810system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 811system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 812system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 813system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 814system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 815system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 816system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 817system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 818system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 819system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 820system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 821system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 822system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 823system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 824system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 825system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 826system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 827system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 828system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 829system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 830system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 831system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 832system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 833system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 628system.cpu.rob.rob_reads 173452486 # The number of ROB reads 629system.cpu.rob.rob_writes 130147702 # The number of ROB writes 630system.cpu.timesIdled 575947 # Number of times that the entire CPU went into an idle state and unscheduled itself 631system.cpu.idleCycles 5434424 # Total number of cycles that the CPU has spent unscheduled due to idling 632system.cpu.quiesceCycles 3599800282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 633system.cpu.committedInsts 52930035 # Number of Instructions Simulated 634system.cpu.committedOps 52930035 # Number of Ops (including micro ops) Simulated 635system.cpu.cpi 2.234988 # CPI: Cycles Per Instruction 636system.cpu.cpi_total 2.234988 # CPI: Total CPI of All Threads 637system.cpu.ipc 0.447430 # IPC: Instructions Per Cycle 638system.cpu.ipc_total 0.447430 # IPC: Total IPC of All Threads 639system.cpu.int_regfile_reads 74659793 # number of integer regfile reads 640system.cpu.int_regfile_writes 40587610 # number of integer regfile writes 641system.cpu.fp_regfile_reads 166949 # number of floating regfile reads 642system.cpu.fp_regfile_writes 167607 # number of floating regfile writes 643system.cpu.misc_regfile_reads 2029497 # number of misc regfile reads 644system.cpu.misc_regfile_writes 939434 # number of misc regfile writes 645system.cpu.dcache.tags.replacements 1404580 # number of replacements 646system.cpu.dcache.tags.tagsinuse 511.994645 # Cycle average of tags in use 647system.cpu.dcache.tags.total_refs 11874772 # Total number of references to valid blocks. 648system.cpu.dcache.tags.sampled_refs 1405092 # Sample count of references to valid blocks. 649system.cpu.dcache.tags.avg_refs 8.451242 # Average number of references to valid blocks. 650system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. 651system.cpu.dcache.tags.occ_blocks::cpu.data 511.994645 # Average occupied blocks per requestor 652system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 653system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy 654system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 655system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id 656system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id 657system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 658system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 659system.cpu.dcache.tags.tag_accesses 63937777 # Number of tag accesses 660system.cpu.dcache.tags.data_accesses 63937777 # Number of data accesses 661system.cpu.dcache.ReadReq_hits::cpu.data 7284414 # number of ReadReq hits 662system.cpu.dcache.ReadReq_hits::total 7284414 # number of ReadReq hits 663system.cpu.dcache.WriteReq_hits::cpu.data 4188003 # number of WriteReq hits 664system.cpu.dcache.WriteReq_hits::total 4188003 # number of WriteReq hits 665system.cpu.dcache.LoadLockedReq_hits::cpu.data 186359 # number of LoadLockedReq hits 666system.cpu.dcache.LoadLockedReq_hits::total 186359 # number of LoadLockedReq hits 667system.cpu.dcache.StoreCondReq_hits::cpu.data 215726 # number of StoreCondReq hits 668system.cpu.dcache.StoreCondReq_hits::total 215726 # number of StoreCondReq hits 669system.cpu.dcache.demand_hits::cpu.data 11472417 # number of demand (read+write) hits 670system.cpu.dcache.demand_hits::total 11472417 # number of demand (read+write) hits 671system.cpu.dcache.overall_hits::cpu.data 11472417 # number of overall hits 672system.cpu.dcache.overall_hits::total 11472417 # number of overall hits 673system.cpu.dcache.ReadReq_misses::cpu.data 1780024 # number of ReadReq misses 674system.cpu.dcache.ReadReq_misses::total 1780024 # number of ReadReq misses 675system.cpu.dcache.WriteReq_misses::cpu.data 1955346 # number of WriteReq misses 676system.cpu.dcache.WriteReq_misses::total 1955346 # number of WriteReq misses 677system.cpu.dcache.LoadLockedReq_misses::cpu.data 23271 # number of LoadLockedReq misses 678system.cpu.dcache.LoadLockedReq_misses::total 23271 # number of LoadLockedReq misses 679system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses 680system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses 681system.cpu.dcache.demand_misses::cpu.data 3735370 # number of demand (read+write) misses 682system.cpu.dcache.demand_misses::total 3735370 # number of demand (read+write) misses 683system.cpu.dcache.overall_misses::cpu.data 3735370 # number of overall misses 684system.cpu.dcache.overall_misses::total 3735370 # number of overall misses 685system.cpu.dcache.ReadReq_miss_latency::cpu.data 39520730746 # number of ReadReq miss cycles 686system.cpu.dcache.ReadReq_miss_latency::total 39520730746 # number of ReadReq miss cycles 687system.cpu.dcache.WriteReq_miss_latency::cpu.data 78084026192 # number of WriteReq miss cycles 688system.cpu.dcache.WriteReq_miss_latency::total 78084026192 # number of WriteReq miss cycles 689system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364876749 # number of LoadLockedReq miss cycles 690system.cpu.dcache.LoadLockedReq_miss_latency::total 364876749 # number of LoadLockedReq miss cycles 691system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 441006 # number of StoreCondReq miss cycles 692system.cpu.dcache.StoreCondReq_miss_latency::total 441006 # number of StoreCondReq miss cycles 693system.cpu.dcache.demand_miss_latency::cpu.data 117604756938 # number of demand (read+write) miss cycles 694system.cpu.dcache.demand_miss_latency::total 117604756938 # number of demand (read+write) miss cycles 695system.cpu.dcache.overall_miss_latency::cpu.data 117604756938 # number of overall miss cycles 696system.cpu.dcache.overall_miss_latency::total 117604756938 # number of overall miss cycles 697system.cpu.dcache.ReadReq_accesses::cpu.data 9064438 # number of ReadReq accesses(hits+misses) 698system.cpu.dcache.ReadReq_accesses::total 9064438 # number of ReadReq accesses(hits+misses) 699system.cpu.dcache.WriteReq_accesses::cpu.data 6143349 # number of WriteReq accesses(hits+misses) 700system.cpu.dcache.WriteReq_accesses::total 6143349 # number of WriteReq accesses(hits+misses) 701system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209630 # number of LoadLockedReq accesses(hits+misses) 702system.cpu.dcache.LoadLockedReq_accesses::total 209630 # number of LoadLockedReq accesses(hits+misses) 703system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) 704system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) 705system.cpu.dcache.demand_accesses::cpu.data 15207787 # number of demand (read+write) accesses 706system.cpu.dcache.demand_accesses::total 15207787 # number of demand (read+write) accesses 707system.cpu.dcache.overall_accesses::cpu.data 15207787 # number of overall (read+write) accesses 708system.cpu.dcache.overall_accesses::total 15207787 # number of overall (read+write) accesses 709system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196374 # miss rate for ReadReq accesses 710system.cpu.dcache.ReadReq_miss_rate::total 0.196374 # miss rate for ReadReq accesses 711system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318287 # miss rate for WriteReq accesses 712system.cpu.dcache.WriteReq_miss_rate::total 0.318287 # miss rate for WriteReq accesses 713system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111010 # miss rate for LoadLockedReq accesses 714system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111010 # miss rate for LoadLockedReq accesses 715system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses 716system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses 717system.cpu.dcache.demand_miss_rate::cpu.data 0.245622 # miss rate for demand accesses 718system.cpu.dcache.demand_miss_rate::total 0.245622 # miss rate for demand accesses 719system.cpu.dcache.overall_miss_rate::cpu.data 0.245622 # miss rate for overall accesses 720system.cpu.dcache.overall_miss_rate::total 0.245622 # miss rate for overall accesses 721system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22202.358365 # average ReadReq miss latency 722system.cpu.dcache.ReadReq_avg_miss_latency::total 22202.358365 # average ReadReq miss latency 723system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39933.610825 # average WriteReq miss latency 724system.cpu.dcache.WriteReq_avg_miss_latency::total 39933.610825 # average WriteReq miss latency 725system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15679.461519 # average LoadLockedReq miss latency 726system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15679.461519 # average LoadLockedReq miss latency 727system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15750.214286 # average StoreCondReq miss latency 728system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15750.214286 # average StoreCondReq miss latency 729system.cpu.dcache.demand_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency 730system.cpu.dcache.demand_avg_miss_latency::total 31484.098480 # average overall miss latency 731system.cpu.dcache.overall_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency 732system.cpu.dcache.overall_avg_miss_latency::total 31484.098480 # average overall miss latency 733system.cpu.dcache.blocked_cycles::no_mshrs 3992388 # number of cycles access was blocked 734system.cpu.dcache.blocked_cycles::no_targets 1705 # number of cycles access was blocked 735system.cpu.dcache.blocked::no_mshrs 180260 # number of cycles access was blocked 736system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked 737system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.147942 # average number of cycles each access was blocked 738system.cpu.dcache.avg_blocked_cycles::no_targets 71.041667 # average number of cycles each access was blocked 739system.cpu.dcache.fast_writes 0 # number of fast writes performed 740system.cpu.dcache.cache_copies 0 # number of cache copies performed 741system.cpu.dcache.writebacks::writebacks 842675 # number of writebacks 742system.cpu.dcache.writebacks::total 842675 # number of writebacks 743system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683874 # number of ReadReq MSHR hits 744system.cpu.dcache.ReadReq_mshr_hits::total 683874 # number of ReadReq MSHR hits 745system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664228 # number of WriteReq MSHR hits 746system.cpu.dcache.WriteReq_mshr_hits::total 1664228 # number of WriteReq MSHR hits 747system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5276 # number of LoadLockedReq MSHR hits 748system.cpu.dcache.LoadLockedReq_mshr_hits::total 5276 # number of LoadLockedReq MSHR hits 749system.cpu.dcache.demand_mshr_hits::cpu.data 2348102 # number of demand (read+write) MSHR hits 750system.cpu.dcache.demand_mshr_hits::total 2348102 # number of demand (read+write) MSHR hits 751system.cpu.dcache.overall_mshr_hits::cpu.data 2348102 # number of overall MSHR hits 752system.cpu.dcache.overall_mshr_hits::total 2348102 # number of overall MSHR hits 753system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096150 # number of ReadReq MSHR misses 754system.cpu.dcache.ReadReq_mshr_misses::total 1096150 # number of ReadReq MSHR misses 755system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291118 # number of WriteReq MSHR misses 756system.cpu.dcache.WriteReq_mshr_misses::total 291118 # number of WriteReq MSHR misses 757system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17995 # number of LoadLockedReq MSHR misses 758system.cpu.dcache.LoadLockedReq_mshr_misses::total 17995 # number of LoadLockedReq MSHR misses 759system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses 760system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses 761system.cpu.dcache.demand_mshr_misses::cpu.data 1387268 # number of demand (read+write) MSHR misses 762system.cpu.dcache.demand_mshr_misses::total 1387268 # number of demand (read+write) MSHR misses 763system.cpu.dcache.overall_mshr_misses::cpu.data 1387268 # number of overall MSHR misses 764system.cpu.dcache.overall_mshr_misses::total 1387268 # number of overall MSHR misses 765system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27519652282 # number of ReadReq MSHR miss cycles 766system.cpu.dcache.ReadReq_mshr_miss_latency::total 27519652282 # number of ReadReq MSHR miss cycles 767system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11779193020 # number of WriteReq MSHR miss cycles 768system.cpu.dcache.WriteReq_mshr_miss_latency::total 11779193020 # number of WriteReq MSHR miss cycles 769system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204738251 # number of LoadLockedReq MSHR miss cycles 770system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204738251 # number of LoadLockedReq MSHR miss cycles 771system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 384994 # number of StoreCondReq MSHR miss cycles 772system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 384994 # number of StoreCondReq MSHR miss cycles 773system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39298845302 # number of demand (read+write) MSHR miss cycles 774system.cpu.dcache.demand_mshr_miss_latency::total 39298845302 # number of demand (read+write) MSHR miss cycles 775system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39298845302 # number of overall MSHR miss cycles 776system.cpu.dcache.overall_mshr_miss_latency::total 39298845302 # number of overall MSHR miss cycles 777system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423580000 # number of ReadReq MSHR uncacheable cycles 778system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423580000 # number of ReadReq MSHR uncacheable cycles 779system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999637498 # number of WriteReq MSHR uncacheable cycles 780system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999637498 # number of WriteReq MSHR uncacheable cycles 781system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423217498 # number of overall MSHR uncacheable cycles 782system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423217498 # number of overall MSHR uncacheable cycles 783system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120929 # mshr miss rate for ReadReq accesses 784system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120929 # mshr miss rate for ReadReq accesses 785system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses 786system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses 787system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085842 # mshr miss rate for LoadLockedReq accesses 788system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085842 # mshr miss rate for LoadLockedReq accesses 789system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses 790system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses 791system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses 792system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses 793system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses 794system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses 795system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25105.735786 # average ReadReq mshr miss latency 796system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25105.735786 # average ReadReq mshr miss latency 797system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40461.919290 # average WriteReq mshr miss latency 798system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40461.919290 # average WriteReq mshr miss latency 799system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.507697 # average LoadLockedReq mshr miss latency 800system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.507697 # average LoadLockedReq mshr miss latency 801system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13749.785714 # average StoreCondReq mshr miss latency 802system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13749.785714 # average StoreCondReq mshr miss latency 803system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency 804system.cpu.dcache.demand_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency 805system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency 806system.cpu.dcache.overall_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency 807system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 808system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 809system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 810system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 811system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 812system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 813system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 814system.cpu.icache.tags.replacements 1035530 # number of replacements 815system.cpu.icache.tags.tagsinuse 509.402349 # Cycle average of tags in use 816system.cpu.icache.tags.total_refs 7932375 # Total number of references to valid blocks. 817system.cpu.icache.tags.sampled_refs 1036038 # Sample count of references to valid blocks. 818system.cpu.icache.tags.avg_refs 7.656452 # Average number of references to valid blocks. 819system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. 820system.cpu.icache.tags.occ_blocks::cpu.inst 509.402349 # Average occupied blocks per requestor 821system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy 822system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy 823system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 824system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 825system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id 826system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id 827system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 828system.cpu.icache.tags.tag_accesses 10056088 # Number of tag accesses 829system.cpu.icache.tags.data_accesses 10056088 # Number of data accesses 830system.cpu.icache.ReadReq_hits::cpu.inst 7932376 # number of ReadReq hits 831system.cpu.icache.ReadReq_hits::total 7932376 # number of ReadReq hits 832system.cpu.icache.demand_hits::cpu.inst 7932376 # number of demand (read+write) hits 833system.cpu.icache.demand_hits::total 7932376 # number of demand (read+write) hits 834system.cpu.icache.overall_hits::cpu.inst 7932376 # number of overall hits 835system.cpu.icache.overall_hits::total 7932376 # number of overall hits 836system.cpu.icache.ReadReq_misses::cpu.inst 1087421 # number of ReadReq misses 837system.cpu.icache.ReadReq_misses::total 1087421 # number of ReadReq misses 838system.cpu.icache.demand_misses::cpu.inst 1087421 # number of demand (read+write) misses 839system.cpu.icache.demand_misses::total 1087421 # number of demand (read+write) misses 840system.cpu.icache.overall_misses::cpu.inst 1087421 # number of overall misses 841system.cpu.icache.overall_misses::total 1087421 # number of overall misses 842system.cpu.icache.ReadReq_miss_latency::cpu.inst 15131971529 # number of ReadReq miss cycles 843system.cpu.icache.ReadReq_miss_latency::total 15131971529 # number of ReadReq miss cycles 844system.cpu.icache.demand_miss_latency::cpu.inst 15131971529 # number of demand (read+write) miss cycles 845system.cpu.icache.demand_miss_latency::total 15131971529 # number of demand (read+write) miss cycles 846system.cpu.icache.overall_miss_latency::cpu.inst 15131971529 # number of overall miss cycles 847system.cpu.icache.overall_miss_latency::total 15131971529 # number of overall miss cycles 848system.cpu.icache.ReadReq_accesses::cpu.inst 9019797 # number of ReadReq accesses(hits+misses) 849system.cpu.icache.ReadReq_accesses::total 9019797 # number of ReadReq accesses(hits+misses) 850system.cpu.icache.demand_accesses::cpu.inst 9019797 # number of demand (read+write) accesses 851system.cpu.icache.demand_accesses::total 9019797 # number of demand (read+write) accesses 852system.cpu.icache.overall_accesses::cpu.inst 9019797 # number of overall (read+write) accesses 853system.cpu.icache.overall_accesses::total 9019797 # number of overall (read+write) accesses 854system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120559 # miss rate for ReadReq accesses 855system.cpu.icache.ReadReq_miss_rate::total 0.120559 # miss rate for ReadReq accesses 856system.cpu.icache.demand_miss_rate::cpu.inst 0.120559 # miss rate for demand accesses 857system.cpu.icache.demand_miss_rate::total 0.120559 # miss rate for demand accesses 858system.cpu.icache.overall_miss_rate::cpu.inst 0.120559 # miss rate for overall accesses 859system.cpu.icache.overall_miss_rate::total 0.120559 # miss rate for overall accesses 860system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13915.467449 # average ReadReq miss latency 861system.cpu.icache.ReadReq_avg_miss_latency::total 13915.467449 # average ReadReq miss latency 862system.cpu.icache.demand_avg_miss_latency::cpu.inst 13915.467449 # average overall miss latency 863system.cpu.icache.demand_avg_miss_latency::total 13915.467449 # average overall miss latency 864system.cpu.icache.overall_avg_miss_latency::cpu.inst 13915.467449 # average overall miss latency 865system.cpu.icache.overall_avg_miss_latency::total 13915.467449 # average overall miss latency 866system.cpu.icache.blocked_cycles::no_mshrs 5307 # number of cycles access was blocked 867system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 868system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked 869system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 870system.cpu.icache.avg_blocked_cycles::no_mshrs 26.142857 # average number of cycles each access was blocked 871system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 872system.cpu.icache.fast_writes 0 # number of fast writes performed 873system.cpu.icache.cache_copies 0 # number of cache copies performed 874system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51130 # number of ReadReq MSHR hits 875system.cpu.icache.ReadReq_mshr_hits::total 51130 # number of ReadReq MSHR hits 876system.cpu.icache.demand_mshr_hits::cpu.inst 51130 # number of demand (read+write) MSHR hits 877system.cpu.icache.demand_mshr_hits::total 51130 # number of demand (read+write) MSHR hits 878system.cpu.icache.overall_mshr_hits::cpu.inst 51130 # number of overall MSHR hits 879system.cpu.icache.overall_mshr_hits::total 51130 # number of overall MSHR hits 880system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1036291 # number of ReadReq MSHR misses 881system.cpu.icache.ReadReq_mshr_misses::total 1036291 # number of ReadReq MSHR misses 882system.cpu.icache.demand_mshr_misses::cpu.inst 1036291 # number of demand (read+write) MSHR misses 883system.cpu.icache.demand_mshr_misses::total 1036291 # number of demand (read+write) MSHR misses 884system.cpu.icache.overall_mshr_misses::cpu.inst 1036291 # number of overall MSHR misses 885system.cpu.icache.overall_mshr_misses::total 1036291 # number of overall MSHR misses 886system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12436978135 # number of ReadReq MSHR miss cycles 887system.cpu.icache.ReadReq_mshr_miss_latency::total 12436978135 # number of ReadReq MSHR miss cycles 888system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12436978135 # number of demand (read+write) MSHR miss cycles 889system.cpu.icache.demand_mshr_miss_latency::total 12436978135 # number of demand (read+write) MSHR miss cycles 890system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12436978135 # number of overall MSHR miss cycles 891system.cpu.icache.overall_mshr_miss_latency::total 12436978135 # number of overall MSHR miss cycles 892system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for ReadReq accesses 893system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114891 # mshr miss rate for ReadReq accesses 894system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for demand accesses 895system.cpu.icache.demand_mshr_miss_rate::total 0.114891 # mshr miss rate for demand accesses 896system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for overall accesses 897system.cpu.icache.overall_mshr_miss_rate::total 0.114891 # mshr miss rate for overall accesses 898system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12001.434090 # average ReadReq mshr miss latency 899system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12001.434090 # average ReadReq mshr miss latency 900system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12001.434090 # average overall mshr miss latency 901system.cpu.icache.demand_avg_mshr_miss_latency::total 12001.434090 # average overall mshr miss latency 902system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12001.434090 # average overall mshr miss latency 903system.cpu.icache.overall_avg_mshr_miss_latency::total 12001.434090 # average overall mshr miss latency 904system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 905system.cpu.l2cache.tags.replacements 338304 # number of replacements 906system.cpu.l2cache.tags.tagsinuse 65336.722890 # Cycle average of tags in use 907system.cpu.l2cache.tags.total_refs 2576408 # Total number of references to valid blocks. 908system.cpu.l2cache.tags.sampled_refs 403470 # Sample count of references to valid blocks. 909system.cpu.l2cache.tags.avg_refs 6.385625 # Average number of references to valid blocks. 910system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. 911system.cpu.l2cache.tags.occ_blocks::writebacks 53740.358806 # Average occupied blocks per requestor 912system.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.050861 # Average occupied blocks per requestor 913system.cpu.l2cache.tags.occ_blocks::cpu.data 6255.313222 # Average occupied blocks per requestor 914system.cpu.l2cache.tags.occ_percent::writebacks 0.820013 # Average percentage of cache occupancy 915system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081498 # Average percentage of cache occupancy 916system.cpu.l2cache.tags.occ_percent::cpu.data 0.095449 # Average percentage of cache occupancy 917system.cpu.l2cache.tags.occ_percent::total 0.996959 # Average percentage of cache occupancy 918system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::0 494 # Occupied blocks per task id 920system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3497 # Occupied blocks per task id 921system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3329 # Occupied blocks per task id 922system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id 923system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55432 # Occupied blocks per task id 924system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id 925system.cpu.l2cache.tags.tag_accesses 26978409 # Number of tag accesses 926system.cpu.l2cache.tags.data_accesses 26978409 # Number of data accesses 927system.cpu.l2cache.ReadReq_hits::cpu.inst 1021005 # number of ReadReq hits 928system.cpu.l2cache.ReadReq_hits::cpu.data 829436 # number of ReadReq hits 929system.cpu.l2cache.ReadReq_hits::total 1850441 # number of ReadReq hits 930system.cpu.l2cache.Writeback_hits::writebacks 842675 # number of Writeback hits 931system.cpu.l2cache.Writeback_hits::total 842675 # number of Writeback hits 932system.cpu.l2cache.UpgradeReq_hits::cpu.data 32 # number of UpgradeReq hits 933system.cpu.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits 934system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 935system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 936system.cpu.l2cache.ReadExReq_hits::cpu.data 186561 # number of ReadExReq hits 937system.cpu.l2cache.ReadExReq_hits::total 186561 # number of ReadExReq hits 938system.cpu.l2cache.demand_hits::cpu.inst 1021005 # number of demand (read+write) hits 939system.cpu.l2cache.demand_hits::cpu.data 1015997 # number of demand (read+write) hits 940system.cpu.l2cache.demand_hits::total 2037002 # number of demand (read+write) hits 941system.cpu.l2cache.overall_hits::cpu.inst 1021005 # number of overall hits 942system.cpu.l2cache.overall_hits::cpu.data 1015997 # number of overall hits 943system.cpu.l2cache.overall_hits::total 2037002 # number of overall hits 944system.cpu.l2cache.ReadReq_misses::cpu.inst 15114 # number of ReadReq misses 945system.cpu.l2cache.ReadReq_misses::cpu.data 273817 # number of ReadReq misses 946system.cpu.l2cache.ReadReq_misses::total 288931 # number of ReadReq misses 947system.cpu.l2cache.UpgradeReq_misses::cpu.data 47 # number of UpgradeReq misses 948system.cpu.l2cache.UpgradeReq_misses::total 47 # number of UpgradeReq misses 949system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses 950system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses 951system.cpu.l2cache.ReadExReq_misses::cpu.data 115372 # number of ReadExReq misses 952system.cpu.l2cache.ReadExReq_misses::total 115372 # number of ReadExReq misses 953system.cpu.l2cache.demand_misses::cpu.inst 15114 # number of demand (read+write) misses 954system.cpu.l2cache.demand_misses::cpu.data 389189 # number of demand (read+write) misses 955system.cpu.l2cache.demand_misses::total 404303 # number of demand (read+write) misses 956system.cpu.l2cache.overall_misses::cpu.inst 15114 # number of overall misses 957system.cpu.l2cache.overall_misses::cpu.data 389189 # number of overall misses 958system.cpu.l2cache.overall_misses::total 404303 # number of overall misses 959system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1159992750 # number of ReadReq miss cycles 960system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17995310250 # number of ReadReq miss cycles 961system.cpu.l2cache.ReadReq_miss_latency::total 19155303000 # number of ReadReq miss cycles 962system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 355494 # number of UpgradeReq miss cycles 963system.cpu.l2cache.UpgradeReq_miss_latency::total 355494 # number of UpgradeReq miss cycles 964system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 92496 # number of SCUpgradeReq miss cycles 965system.cpu.l2cache.SCUpgradeReq_miss_latency::total 92496 # number of SCUpgradeReq miss cycles 966system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9679121611 # number of ReadExReq miss cycles 967system.cpu.l2cache.ReadExReq_miss_latency::total 9679121611 # number of ReadExReq miss cycles 968system.cpu.l2cache.demand_miss_latency::cpu.inst 1159992750 # number of demand (read+write) miss cycles 969system.cpu.l2cache.demand_miss_latency::cpu.data 27674431861 # number of demand (read+write) miss cycles 970system.cpu.l2cache.demand_miss_latency::total 28834424611 # number of demand (read+write) miss cycles 971system.cpu.l2cache.overall_miss_latency::cpu.inst 1159992750 # number of overall miss cycles 972system.cpu.l2cache.overall_miss_latency::cpu.data 27674431861 # number of overall miss cycles 973system.cpu.l2cache.overall_miss_latency::total 28834424611 # number of overall miss cycles 974system.cpu.l2cache.ReadReq_accesses::cpu.inst 1036119 # number of ReadReq accesses(hits+misses) 975system.cpu.l2cache.ReadReq_accesses::cpu.data 1103253 # number of ReadReq accesses(hits+misses) 976system.cpu.l2cache.ReadReq_accesses::total 2139372 # number of ReadReq accesses(hits+misses) 977system.cpu.l2cache.Writeback_accesses::writebacks 842675 # number of Writeback accesses(hits+misses) 978system.cpu.l2cache.Writeback_accesses::total 842675 # number of Writeback accesses(hits+misses) 979system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) 980system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) 981system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) 982system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) 983system.cpu.l2cache.ReadExReq_accesses::cpu.data 301933 # number of ReadExReq accesses(hits+misses) 984system.cpu.l2cache.ReadExReq_accesses::total 301933 # number of ReadExReq accesses(hits+misses) 985system.cpu.l2cache.demand_accesses::cpu.inst 1036119 # number of demand (read+write) accesses 986system.cpu.l2cache.demand_accesses::cpu.data 1405186 # number of demand (read+write) accesses 987system.cpu.l2cache.demand_accesses::total 2441305 # number of demand (read+write) accesses 988system.cpu.l2cache.overall_accesses::cpu.inst 1036119 # number of overall (read+write) accesses 989system.cpu.l2cache.overall_accesses::cpu.data 1405186 # number of overall (read+write) accesses 990system.cpu.l2cache.overall_accesses::total 2441305 # number of overall (read+write) accesses 991system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014587 # miss rate for ReadReq accesses 992system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248191 # miss rate for ReadReq accesses 993system.cpu.l2cache.ReadReq_miss_rate::total 0.135054 # miss rate for ReadReq accesses 994system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.594937 # miss rate for UpgradeReq accesses 995system.cpu.l2cache.UpgradeReq_miss_rate::total 0.594937 # miss rate for UpgradeReq accesses 996system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses 997system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses 998system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382111 # miss rate for ReadExReq accesses 999system.cpu.l2cache.ReadExReq_miss_rate::total 0.382111 # miss rate for ReadExReq accesses 1000system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014587 # miss rate for demand accesses 1001system.cpu.l2cache.demand_miss_rate::cpu.data 0.276966 # miss rate for demand accesses 1002system.cpu.l2cache.demand_miss_rate::total 0.165609 # miss rate for demand accesses 1003system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014587 # miss rate for overall accesses 1004system.cpu.l2cache.overall_miss_rate::cpu.data 0.276966 # miss rate for overall accesses 1005system.cpu.l2cache.overall_miss_rate::total 0.165609 # miss rate for overall accesses 1006system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76749.553394 # average ReadReq miss latency 1007system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65720.208205 # average ReadReq miss latency 1008system.cpu.l2cache.ReadReq_avg_miss_latency::total 66297.153992 # average ReadReq miss latency 1009system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7563.702128 # average UpgradeReq miss latency 1010system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7563.702128 # average UpgradeReq miss latency 1011system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 15416 # average SCUpgradeReq miss latency 1012system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 15416 # average SCUpgradeReq miss latency 1013system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83894.893137 # average ReadExReq miss latency 1014system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83894.893137 # average ReadExReq miss latency 1015system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76749.553394 # average overall miss latency 1016system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71107.949765 # average overall miss latency 1017system.cpu.l2cache.demand_avg_miss_latency::total 71318.849009 # average overall miss latency 1018system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76749.553394 # average overall miss latency 1019system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71107.949765 # average overall miss latency 1020system.cpu.l2cache.overall_avg_miss_latency::total 71318.849009 # average overall miss latency 1021system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1022system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1023system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1024system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1025system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1026system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1027system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1028system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1029system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks 1030system.cpu.l2cache.writebacks::total 75929 # number of writebacks 1031system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1032system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1033system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1034system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1035system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1036system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1037system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses 1038system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273817 # number of ReadReq MSHR misses 1039system.cpu.l2cache.ReadReq_mshr_misses::total 288930 # number of ReadReq MSHR misses 1040system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 47 # number of UpgradeReq MSHR misses 1041system.cpu.l2cache.UpgradeReq_mshr_misses::total 47 # number of UpgradeReq MSHR misses 1042system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses 1043system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses 1044system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115372 # number of ReadExReq MSHR misses 1045system.cpu.l2cache.ReadExReq_mshr_misses::total 115372 # number of ReadExReq MSHR misses 1046system.cpu.l2cache.demand_mshr_misses::cpu.inst 15113 # number of demand (read+write) MSHR misses 1047system.cpu.l2cache.demand_mshr_misses::cpu.data 389189 # number of demand (read+write) MSHR misses 1048system.cpu.l2cache.demand_mshr_misses::total 404302 # number of demand (read+write) MSHR misses 1049system.cpu.l2cache.overall_mshr_misses::cpu.inst 15113 # number of overall MSHR misses 1050system.cpu.l2cache.overall_mshr_misses::cpu.data 389189 # number of overall MSHR misses 1051system.cpu.l2cache.overall_mshr_misses::total 404302 # number of overall MSHR misses 1052system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 969372000 # number of ReadReq MSHR miss cycles 1053system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14584664250 # number of ReadReq MSHR miss cycles 1054system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15554036250 # number of ReadReq MSHR miss cycles 1055system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 622542 # number of UpgradeReq MSHR miss cycles 1056system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 622542 # number of UpgradeReq MSHR miss cycles 1057system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 60006 # number of SCUpgradeReq MSHR miss cycles 1058system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 60006 # number of SCUpgradeReq MSHR miss cycles 1059system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8273073889 # number of ReadExReq MSHR miss cycles 1060system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8273073889 # number of ReadExReq MSHR miss cycles 1061system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 969372000 # number of demand (read+write) MSHR miss cycles 1062system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22857738139 # number of demand (read+write) MSHR miss cycles 1063system.cpu.l2cache.demand_mshr_miss_latency::total 23827110139 # number of demand (read+write) MSHR miss cycles 1064system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 969372000 # number of overall MSHR miss cycles 1065system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22857738139 # number of overall MSHR miss cycles 1066system.cpu.l2cache.overall_mshr_miss_latency::total 23827110139 # number of overall MSHR miss cycles 1067system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333490000 # number of ReadReq MSHR uncacheable cycles 1068system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333490000 # number of ReadReq MSHR uncacheable cycles 1069system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884459000 # number of WriteReq MSHR uncacheable cycles 1070system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884459000 # number of WriteReq MSHR uncacheable cycles 1071system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217949000 # number of overall MSHR uncacheable cycles 1072system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217949000 # number of overall MSHR uncacheable cycles 1073system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for ReadReq accesses 1074system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248191 # mshr miss rate for ReadReq accesses 1075system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135054 # mshr miss rate for ReadReq accesses 1076system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.594937 # mshr miss rate for UpgradeReq accesses 1077system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.594937 # mshr miss rate for UpgradeReq accesses 1078system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses 1079system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses 1080system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382111 # mshr miss rate for ReadExReq accesses 1081system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382111 # mshr miss rate for ReadExReq accesses 1082system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for demand accesses 1083system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276966 # mshr miss rate for demand accesses 1084system.cpu.l2cache.demand_mshr_miss_rate::total 0.165609 # mshr miss rate for demand accesses 1085system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for overall accesses 1086system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276966 # mshr miss rate for overall accesses 1087system.cpu.l2cache.overall_mshr_miss_rate::total 0.165609 # mshr miss rate for overall accesses 1088system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64141.599947 # average ReadReq mshr miss latency 1089system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53264.275958 # average ReadReq mshr miss latency 1090system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53833.233828 # average ReadReq mshr miss latency 1091system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13245.574468 # average UpgradeReq mshr miss latency 1092system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13245.574468 # average UpgradeReq mshr miss latency 1093system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1094system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1095system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71707.813759 # average ReadExReq mshr miss latency 1096system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71707.813759 # average ReadExReq mshr miss latency 1097system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency 1098system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency 1099system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency 1100system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency 1101system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency 1102system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency 1103system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1104system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1105system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1106system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1107system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1108system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1109system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1110system.cpu.toL2Bus.trans_dist::ReadReq 2146647 # Transaction distribution 1111system.cpu.toL2Bus.trans_dist::ReadResp 2146537 # Transaction distribution 1112system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 1113system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution 1114system.cpu.toL2Bus.trans_dist::Writeback 842675 # Transaction distribution 1115system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1116system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution 1118system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::ReadExReq 301933 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::ReadExResp 301933 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::BadAddressError 93 # Transaction distribution 1122system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2072410 # Packet count per connected master and slave (bytes) 1123system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686471 # Packet count per connected master and slave (bytes) 1124system.cpu.toL2Bus.pkt_count::total 5758881 # Packet count per connected master and slave (bytes) 1125system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66311616 # Cumulative packet size per connected master and slave (bytes) 1126system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143911276 # Cumulative packet size per connected master and slave (bytes) 1127system.cpu.toL2Bus.pkt_size::total 210222892 # Cumulative packet size per connected master and slave (bytes) 1128system.cpu.toL2Bus.snoops 42053 # Total snoops (count) 1129system.cpu.toL2Bus.snoop_fanout::samples 3325984 # Request fanout histogram 1130system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram 1131system.cpu.toL2Bus.snoop_fanout::stdev 0.111300 # Request fanout histogram 1132system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1133system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1134system.cpu.toL2Bus.snoop_fanout::1 3284259 98.75% 98.75% # Request fanout histogram 1135system.cpu.toL2Bus.snoop_fanout::2 41725 1.25% 100.00% # Request fanout histogram 1136system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1137system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1138system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1139system.cpu.toL2Bus.snoop_fanout::total 3325984 # Request fanout histogram 1140system.cpu.toL2Bus.reqLayer0.occupancy 2497867498 # Layer occupancy (ticks) 1141system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1142system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 1143system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1144system.cpu.toL2Bus.respLayer0.occupancy 1558461609 # Layer occupancy (ticks) 1145system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1146system.cpu.toL2Bus.respLayer1.occupancy 2189866891 # Layer occupancy (ticks) 1147system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1148system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1149system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1150system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1151system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1152system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1153system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1154system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1155system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1156system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1157system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1158system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1159system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 834system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 835system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 1160system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 1161system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 836system.iobus.trans_dist::WriteReq 51063 # Transaction distribution 837system.iobus.trans_dist::WriteResp 51149 # Transaction distribution 838system.iobus.trans_dist::WriteInvalidateReq 86 # Transaction distribution | 1162system.iobus.trans_dist::WriteReq 51149 # Transaction distribution 1163system.iobus.trans_dist::WriteResp 9597 # Transaction distribution 1164system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 839system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) 840system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 841system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 842system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 843system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 844system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 845system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 846system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) --- 38 unchanged lines hidden (view full) --- 885system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 886system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 887system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 888system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 889system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 890system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 891system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 892system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1165system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) --- 38 unchanged lines hidden (view full) --- 1211system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1212system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1213system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1214system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1215system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1216system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1217system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1218system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 893system.iobus.reqLayer29.occupancy 374547621 # Layer occupancy (ticks) | 1219system.iobus.reqLayer29.occupancy 406221775 # Layer occupancy (ticks) |
| 894system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 895system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 896system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 897system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) 898system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1220system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1221system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1222system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1223system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) 1224system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 899system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) | 1225system.iobus.respLayer1.occupancy 42010536 # Layer occupancy (ticks) |
| 900system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1226system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 901system.cpu.toL2Bus.trans_dist::ReadReq 2147499 # Transaction distribution 902system.cpu.toL2Bus.trans_dist::ReadResp 2147393 # Transaction distribution 903system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 904system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution 905system.cpu.toL2Bus.trans_dist::Writeback 842679 # Transaction distribution 906system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution 907system.cpu.toL2Bus.trans_dist::UpgradeReq 81 # Transaction distribution 908system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution 909system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution 910system.cpu.toL2Bus.trans_dist::ReadExReq 301934 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::ReadExResp 301934 # Transaction distribution 912system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution 913system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074254 # Packet count per connected master and slave (bytes) 914system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686339 # Packet count per connected master and slave (bytes) 915system.cpu.toL2Bus.pkt_count::total 5760593 # Packet count per connected master and slave (bytes) 916system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66370688 # Cumulative packet size per connected master and slave (bytes) 917system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143907436 # Cumulative packet size per connected master and slave (bytes) 918system.cpu.toL2Bus.pkt_size::total 210278124 # Cumulative packet size per connected master and slave (bytes) 919system.cpu.toL2Bus.snoops 42060 # Total snoops (count) 920system.cpu.toL2Bus.snoop_fanout::samples 3326850 # Request fanout histogram 921system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram 922system.cpu.toL2Bus.snoop_fanout::stdev 0.111298 # Request fanout histogram 923system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 924system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 925system.cpu.toL2Bus.snoop_fanout::1 3285116 98.75% 98.75% # Request fanout histogram 926system.cpu.toL2Bus.snoop_fanout::2 41734 1.25% 100.00% # Request fanout histogram 927system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 928system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 929system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 930system.cpu.toL2Bus.snoop_fanout::total 3326850 # Request fanout histogram 931system.cpu.toL2Bus.reqLayer0.occupancy 2498300996 # Layer occupancy (ticks) 932system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 933system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 934system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 935system.cpu.toL2Bus.respLayer0.occupancy 1559854344 # Layer occupancy (ticks) 936system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 937system.cpu.toL2Bus.respLayer1.occupancy 2189806641 # Layer occupancy (ticks) 938system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 939system.cpu.icache.tags.replacements 1036451 # number of replacements 940system.cpu.icache.tags.tagsinuse 509.402237 # Cycle average of tags in use 941system.cpu.icache.tags.total_refs 7937240 # Total number of references to valid blocks. 942system.cpu.icache.tags.sampled_refs 1036959 # Sample count of references to valid blocks. 943system.cpu.icache.tags.avg_refs 7.654343 # Average number of references to valid blocks. 944system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. 945system.cpu.icache.tags.occ_blocks::cpu.inst 509.402237 # Average occupied blocks per requestor 946system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy 947system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy 948system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 949system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 950system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id 951system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id 952system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id 953system.cpu.icache.tags.tag_accesses 10062742 # Number of tag accesses 954system.cpu.icache.tags.data_accesses 10062742 # Number of data accesses 955system.cpu.icache.ReadReq_hits::cpu.inst 7937241 # number of ReadReq hits 956system.cpu.icache.ReadReq_hits::total 7937241 # number of ReadReq hits 957system.cpu.icache.demand_hits::cpu.inst 7937241 # number of demand (read+write) hits 958system.cpu.icache.demand_hits::total 7937241 # number of demand (read+write) hits 959system.cpu.icache.overall_hits::cpu.inst 7937241 # number of overall hits 960system.cpu.icache.overall_hits::total 7937241 # number of overall hits 961system.cpu.icache.ReadReq_misses::cpu.inst 1088289 # number of ReadReq misses 962system.cpu.icache.ReadReq_misses::total 1088289 # number of ReadReq misses 963system.cpu.icache.demand_misses::cpu.inst 1088289 # number of demand (read+write) misses 964system.cpu.icache.demand_misses::total 1088289 # number of demand (read+write) misses 965system.cpu.icache.overall_misses::cpu.inst 1088289 # number of overall misses 966system.cpu.icache.overall_misses::total 1088289 # number of overall misses 967system.cpu.icache.ReadReq_miss_latency::cpu.inst 15130440508 # number of ReadReq miss cycles 968system.cpu.icache.ReadReq_miss_latency::total 15130440508 # number of ReadReq miss cycles 969system.cpu.icache.demand_miss_latency::cpu.inst 15130440508 # number of demand (read+write) miss cycles 970system.cpu.icache.demand_miss_latency::total 15130440508 # number of demand (read+write) miss cycles 971system.cpu.icache.overall_miss_latency::cpu.inst 15130440508 # number of overall miss cycles 972system.cpu.icache.overall_miss_latency::total 15130440508 # number of overall miss cycles 973system.cpu.icache.ReadReq_accesses::cpu.inst 9025530 # number of ReadReq accesses(hits+misses) 974system.cpu.icache.ReadReq_accesses::total 9025530 # number of ReadReq accesses(hits+misses) 975system.cpu.icache.demand_accesses::cpu.inst 9025530 # number of demand (read+write) accesses 976system.cpu.icache.demand_accesses::total 9025530 # number of demand (read+write) accesses 977system.cpu.icache.overall_accesses::cpu.inst 9025530 # number of overall (read+write) accesses 978system.cpu.icache.overall_accesses::total 9025530 # number of overall (read+write) accesses 979system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120579 # miss rate for ReadReq accesses 980system.cpu.icache.ReadReq_miss_rate::total 0.120579 # miss rate for ReadReq accesses 981system.cpu.icache.demand_miss_rate::cpu.inst 0.120579 # miss rate for demand accesses 982system.cpu.icache.demand_miss_rate::total 0.120579 # miss rate for demand accesses 983system.cpu.icache.overall_miss_rate::cpu.inst 0.120579 # miss rate for overall accesses 984system.cpu.icache.overall_miss_rate::total 0.120579 # miss rate for overall accesses 985system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13902.961904 # average ReadReq miss latency 986system.cpu.icache.ReadReq_avg_miss_latency::total 13902.961904 # average ReadReq miss latency 987system.cpu.icache.demand_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency 988system.cpu.icache.demand_avg_miss_latency::total 13902.961904 # average overall miss latency 989system.cpu.icache.overall_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency 990system.cpu.icache.overall_avg_miss_latency::total 13902.961904 # average overall miss latency 991system.cpu.icache.blocked_cycles::no_mshrs 4627 # number of cycles access was blocked 992system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 993system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked 994system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 995system.cpu.icache.avg_blocked_cycles::no_mshrs 22.793103 # average number of cycles each access was blocked 996system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 997system.cpu.icache.fast_writes 0 # number of fast writes performed 998system.cpu.icache.cache_copies 0 # number of cache copies performed 999system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51077 # number of ReadReq MSHR hits 1000system.cpu.icache.ReadReq_mshr_hits::total 51077 # number of ReadReq MSHR hits 1001system.cpu.icache.demand_mshr_hits::cpu.inst 51077 # number of demand (read+write) MSHR hits 1002system.cpu.icache.demand_mshr_hits::total 51077 # number of demand (read+write) MSHR hits 1003system.cpu.icache.overall_mshr_hits::cpu.inst 51077 # number of overall MSHR hits 1004system.cpu.icache.overall_mshr_hits::total 51077 # number of overall MSHR hits 1005system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037212 # number of ReadReq MSHR misses 1006system.cpu.icache.ReadReq_mshr_misses::total 1037212 # number of ReadReq MSHR misses 1007system.cpu.icache.demand_mshr_misses::cpu.inst 1037212 # number of demand (read+write) MSHR misses 1008system.cpu.icache.demand_mshr_misses::total 1037212 # number of demand (read+write) MSHR misses 1009system.cpu.icache.overall_mshr_misses::cpu.inst 1037212 # number of overall MSHR misses 1010system.cpu.icache.overall_mshr_misses::total 1037212 # number of overall MSHR misses 1011system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12445124401 # number of ReadReq MSHR miss cycles 1012system.cpu.icache.ReadReq_mshr_miss_latency::total 12445124401 # number of ReadReq MSHR miss cycles 1013system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12445124401 # number of demand (read+write) MSHR miss cycles 1014system.cpu.icache.demand_mshr_miss_latency::total 12445124401 # number of demand (read+write) MSHR miss cycles 1015system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12445124401 # number of overall MSHR miss cycles 1016system.cpu.icache.overall_mshr_miss_latency::total 12445124401 # number of overall MSHR miss cycles 1017system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for ReadReq accesses 1018system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114920 # mshr miss rate for ReadReq accesses 1019system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for demand accesses 1020system.cpu.icache.demand_mshr_miss_rate::total 0.114920 # mshr miss rate for demand accesses 1021system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for overall accesses 1022system.cpu.icache.overall_mshr_miss_rate::total 0.114920 # mshr miss rate for overall accesses 1023system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.631332 # average ReadReq mshr miss latency 1024system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.631332 # average ReadReq mshr miss latency 1025system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency 1026system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency 1027system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency 1028system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency 1029system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1030system.cpu.l2cache.tags.replacements 338311 # number of replacements 1031system.cpu.l2cache.tags.tagsinuse 65336.723406 # Cycle average of tags in use 1032system.cpu.l2cache.tags.total_refs 2577279 # Total number of references to valid blocks. 1033system.cpu.l2cache.tags.sampled_refs 403479 # Sample count of references to valid blocks. 1034system.cpu.l2cache.tags.avg_refs 6.387641 # Average number of references to valid blocks. 1035system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. 1036system.cpu.l2cache.tags.occ_blocks::writebacks 53740.150485 # Average occupied blocks per requestor 1037system.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.296148 # Average occupied blocks per requestor 1038system.cpu.l2cache.tags.occ_blocks::cpu.data 6255.276773 # Average occupied blocks per requestor 1039system.cpu.l2cache.tags.occ_percent::writebacks 0.820010 # Average percentage of cache occupancy 1040system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081502 # Average percentage of cache occupancy 1041system.cpu.l2cache.tags.occ_percent::cpu.data 0.095448 # Average percentage of cache occupancy 1042system.cpu.l2cache.tags.occ_percent::total 0.996959 # Average percentage of cache occupancy 1043system.cpu.l2cache.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id 1044system.cpu.l2cache.tags.age_task_id_blocks_1024::0 497 # Occupied blocks per task id 1045system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id 1046system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id 1047system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2421 # Occupied blocks per task id 1048system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id 1049system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id 1050system.cpu.l2cache.tags.tag_accesses 26985288 # Number of tag accesses 1051system.cpu.l2cache.tags.data_accesses 26985288 # Number of data accesses 1052system.cpu.l2cache.ReadReq_hits::cpu.inst 1021912 # number of ReadReq hits 1053system.cpu.l2cache.ReadReq_hits::cpu.data 829370 # number of ReadReq hits 1054system.cpu.l2cache.ReadReq_hits::total 1851282 # number of ReadReq hits 1055system.cpu.l2cache.Writeback_hits::writebacks 842679 # number of Writeback hits 1056system.cpu.l2cache.Writeback_hits::total 842679 # number of Writeback hits 1057system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits 1058system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits 1059system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 21 # number of SCUpgradeReq hits 1060system.cpu.l2cache.SCUpgradeReq_hits::total 21 # number of SCUpgradeReq hits 1061system.cpu.l2cache.ReadExReq_hits::cpu.data 186572 # number of ReadExReq hits 1062system.cpu.l2cache.ReadExReq_hits::total 186572 # number of ReadExReq hits 1063system.cpu.l2cache.demand_hits::cpu.inst 1021912 # number of demand (read+write) hits 1064system.cpu.l2cache.demand_hits::cpu.data 1015942 # number of demand (read+write) hits 1065system.cpu.l2cache.demand_hits::total 2037854 # number of demand (read+write) hits 1066system.cpu.l2cache.overall_hits::cpu.inst 1021912 # number of overall hits 1067system.cpu.l2cache.overall_hits::cpu.data 1015942 # number of overall hits 1068system.cpu.l2cache.overall_hits::total 2037854 # number of overall hits 1069system.cpu.l2cache.ReadReq_misses::cpu.inst 15130 # number of ReadReq misses 1070system.cpu.l2cache.ReadReq_misses::cpu.data 273814 # number of ReadReq misses 1071system.cpu.l2cache.ReadReq_misses::total 288944 # number of ReadReq misses 1072system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses 1073system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses 1074system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses 1075system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses 1076system.cpu.l2cache.ReadExReq_misses::cpu.data 115362 # number of ReadExReq misses 1077system.cpu.l2cache.ReadExReq_misses::total 115362 # number of ReadExReq misses 1078system.cpu.l2cache.demand_misses::cpu.inst 15130 # number of demand (read+write) misses 1079system.cpu.l2cache.demand_misses::cpu.data 389176 # number of demand (read+write) misses 1080system.cpu.l2cache.demand_misses::total 404306 # number of demand (read+write) misses 1081system.cpu.l2cache.overall_misses::cpu.inst 15130 # number of overall misses 1082system.cpu.l2cache.overall_misses::cpu.data 389176 # number of overall misses 1083system.cpu.l2cache.overall_misses::total 404306 # number of overall misses 1084system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1158124750 # number of ReadReq miss cycles 1085system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17992143250 # number of ReadReq miss cycles 1086system.cpu.l2cache.ReadReq_miss_latency::total 19150268000 # number of ReadReq miss cycles 1087system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 194993 # number of UpgradeReq miss cycles 1088system.cpu.l2cache.UpgradeReq_miss_latency::total 194993 # number of UpgradeReq miss cycles 1089system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 69497 # number of SCUpgradeReq miss cycles 1090system.cpu.l2cache.SCUpgradeReq_miss_latency::total 69497 # number of SCUpgradeReq miss cycles 1091system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9692879611 # number of ReadExReq miss cycles 1092system.cpu.l2cache.ReadExReq_miss_latency::total 9692879611 # number of ReadExReq miss cycles 1093system.cpu.l2cache.demand_miss_latency::cpu.inst 1158124750 # number of demand (read+write) miss cycles 1094system.cpu.l2cache.demand_miss_latency::cpu.data 27685022861 # number of demand (read+write) miss cycles 1095system.cpu.l2cache.demand_miss_latency::total 28843147611 # number of demand (read+write) miss cycles 1096system.cpu.l2cache.overall_miss_latency::cpu.inst 1158124750 # number of overall miss cycles 1097system.cpu.l2cache.overall_miss_latency::cpu.data 27685022861 # number of overall miss cycles 1098system.cpu.l2cache.overall_miss_latency::total 28843147611 # number of overall miss cycles 1099system.cpu.l2cache.ReadReq_accesses::cpu.inst 1037042 # number of ReadReq accesses(hits+misses) 1100system.cpu.l2cache.ReadReq_accesses::cpu.data 1103184 # number of ReadReq accesses(hits+misses) 1101system.cpu.l2cache.ReadReq_accesses::total 2140226 # number of ReadReq accesses(hits+misses) 1102system.cpu.l2cache.Writeback_accesses::writebacks 842679 # number of Writeback accesses(hits+misses) 1103system.cpu.l2cache.Writeback_accesses::total 842679 # number of Writeback accesses(hits+misses) 1104system.cpu.l2cache.UpgradeReq_accesses::cpu.data 81 # number of UpgradeReq accesses(hits+misses) 1105system.cpu.l2cache.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) 1106system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 26 # number of SCUpgradeReq accesses(hits+misses) 1107system.cpu.l2cache.SCUpgradeReq_accesses::total 26 # number of SCUpgradeReq accesses(hits+misses) 1108system.cpu.l2cache.ReadExReq_accesses::cpu.data 301934 # number of ReadExReq accesses(hits+misses) 1109system.cpu.l2cache.ReadExReq_accesses::total 301934 # number of ReadExReq accesses(hits+misses) 1110system.cpu.l2cache.demand_accesses::cpu.inst 1037042 # number of demand (read+write) accesses 1111system.cpu.l2cache.demand_accesses::cpu.data 1405118 # number of demand (read+write) accesses 1112system.cpu.l2cache.demand_accesses::total 2442160 # number of demand (read+write) accesses 1113system.cpu.l2cache.overall_accesses::cpu.inst 1037042 # number of overall (read+write) accesses 1114system.cpu.l2cache.overall_accesses::cpu.data 1405118 # number of overall (read+write) accesses 1115system.cpu.l2cache.overall_accesses::total 2442160 # number of overall (read+write) accesses 1116system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014590 # miss rate for ReadReq accesses 1117system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248203 # miss rate for ReadReq accesses 1118system.cpu.l2cache.ReadReq_miss_rate::total 0.135006 # miss rate for ReadReq accesses 1119system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.592593 # miss rate for UpgradeReq accesses 1120system.cpu.l2cache.UpgradeReq_miss_rate::total 0.592593 # miss rate for UpgradeReq accesses 1121system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.192308 # miss rate for SCUpgradeReq accesses 1122system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.192308 # miss rate for SCUpgradeReq accesses 1123system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382077 # miss rate for ReadExReq accesses 1124system.cpu.l2cache.ReadExReq_miss_rate::total 0.382077 # miss rate for ReadExReq accesses 1125system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014590 # miss rate for demand accesses 1126system.cpu.l2cache.demand_miss_rate::cpu.data 0.276970 # miss rate for demand accesses 1127system.cpu.l2cache.demand_miss_rate::total 0.165553 # miss rate for demand accesses 1128system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014590 # miss rate for overall accesses 1129system.cpu.l2cache.overall_miss_rate::cpu.data 0.276970 # miss rate for overall accesses 1130system.cpu.l2cache.overall_miss_rate::total 0.165553 # miss rate for overall accesses 1131system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76544.927297 # average ReadReq miss latency 1132system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65709.362012 # average ReadReq miss latency 1133system.cpu.l2cache.ReadReq_avg_miss_latency::total 66276.745667 # average ReadReq miss latency 1134system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4062.354167 # average UpgradeReq miss latency 1135system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4062.354167 # average UpgradeReq miss latency 1136system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 13899.400000 # average SCUpgradeReq miss latency 1137system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 13899.400000 # average SCUpgradeReq miss latency 1138system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84021.424828 # average ReadExReq miss latency 1139system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84021.424828 # average ReadExReq miss latency 1140system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency 1141system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency 1142system.cpu.l2cache.demand_avg_miss_latency::total 71339.895057 # average overall miss latency 1143system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency 1144system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency 1145system.cpu.l2cache.overall_avg_miss_latency::total 71339.895057 # average overall miss latency 1146system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1147system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1148system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1149system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1150system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1151system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1152system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1153system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1154system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks 1155system.cpu.l2cache.writebacks::total 75938 # number of writebacks 1156system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1157system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1158system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1159system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1160system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1161system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1162system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15129 # number of ReadReq MSHR misses 1163system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273814 # number of ReadReq MSHR misses 1164system.cpu.l2cache.ReadReq_mshr_misses::total 288943 # number of ReadReq MSHR misses 1165system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses 1166system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses 1167system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses 1168system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses 1169system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115362 # number of ReadExReq MSHR misses 1170system.cpu.l2cache.ReadExReq_mshr_misses::total 115362 # number of ReadExReq MSHR misses 1171system.cpu.l2cache.demand_mshr_misses::cpu.inst 15129 # number of demand (read+write) MSHR misses 1172system.cpu.l2cache.demand_mshr_misses::cpu.data 389176 # number of demand (read+write) MSHR misses 1173system.cpu.l2cache.demand_mshr_misses::total 404305 # number of demand (read+write) MSHR misses 1174system.cpu.l2cache.overall_mshr_misses::cpu.inst 15129 # number of overall MSHR misses 1175system.cpu.l2cache.overall_mshr_misses::cpu.data 389176 # number of overall MSHR misses 1176system.cpu.l2cache.overall_mshr_misses::total 404305 # number of overall MSHR misses 1177system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967311000 # number of ReadReq MSHR miss cycles 1178system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14580972250 # number of ReadReq MSHR miss cycles 1179system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15548283250 # number of ReadReq MSHR miss cycles 1180system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 493045 # number of UpgradeReq MSHR miss cycles 1181system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 493045 # number of UpgradeReq MSHR miss cycles 1182system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 50005 # number of SCUpgradeReq MSHR miss cycles 1183system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 50005 # number of SCUpgradeReq MSHR miss cycles 1184system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8286916389 # number of ReadExReq MSHR miss cycles 1185system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8286916389 # number of ReadExReq MSHR miss cycles 1186system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967311000 # number of demand (read+write) MSHR miss cycles 1187system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22867888639 # number of demand (read+write) MSHR miss cycles 1188system.cpu.l2cache.demand_mshr_miss_latency::total 23835199639 # number of demand (read+write) MSHR miss cycles 1189system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967311000 # number of overall MSHR miss cycles 1190system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22867888639 # number of overall MSHR miss cycles 1191system.cpu.l2cache.overall_mshr_miss_latency::total 23835199639 # number of overall MSHR miss cycles 1192system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333507000 # number of ReadReq MSHR uncacheable cycles 1193system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333507000 # number of ReadReq MSHR uncacheable cycles 1194system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884436000 # number of WriteReq MSHR uncacheable cycles 1195system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884436000 # number of WriteReq MSHR uncacheable cycles 1196system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217943000 # number of overall MSHR uncacheable cycles 1197system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217943000 # number of overall MSHR uncacheable cycles 1198system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for ReadReq accesses 1199system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248203 # mshr miss rate for ReadReq accesses 1200system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135006 # mshr miss rate for ReadReq accesses 1201system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.592593 # mshr miss rate for UpgradeReq accesses 1202system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.592593 # mshr miss rate for UpgradeReq accesses 1203system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.192308 # mshr miss rate for SCUpgradeReq accesses 1204system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.192308 # mshr miss rate for SCUpgradeReq accesses 1205system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382077 # mshr miss rate for ReadExReq accesses 1206system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382077 # mshr miss rate for ReadExReq accesses 1207system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for demand accesses 1208system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for demand accesses 1209system.cpu.l2cache.demand_mshr_miss_rate::total 0.165552 # mshr miss rate for demand accesses 1210system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for overall accesses 1211system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for overall accesses 1212system.cpu.l2cache.overall_mshr_miss_rate::total 0.165552 # mshr miss rate for overall accesses 1213system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63937.537180 # average ReadReq mshr miss latency 1214system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53251.375934 # average ReadReq mshr miss latency 1215system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53810.901285 # average ReadReq mshr miss latency 1216system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10271.770833 # average UpgradeReq mshr miss latency 1217system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10271.770833 # average UpgradeReq mshr miss latency 1218system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1219system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1220system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71834.021506 # average ReadExReq mshr miss latency 1221system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71834.021506 # average ReadExReq mshr miss latency 1222system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency 1223system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency 1224system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency 1225system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency 1226system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency 1227system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency 1228system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1229system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1230system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1231system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1232system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1233system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1234system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1235system.cpu.dcache.tags.replacements 1404516 # number of replacements 1236system.cpu.dcache.tags.tagsinuse 511.994651 # Cycle average of tags in use 1237system.cpu.dcache.tags.total_refs 11877087 # Total number of references to valid blocks. 1238system.cpu.dcache.tags.sampled_refs 1405028 # Sample count of references to valid blocks. 1239system.cpu.dcache.tags.avg_refs 8.453274 # Average number of references to valid blocks. 1240system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. 1241system.cpu.dcache.tags.occ_blocks::cpu.data 511.994651 # Average occupied blocks per requestor 1242system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 1243system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy 1244system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1245system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 1246system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id 1247system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 1248system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1249system.cpu.dcache.tags.tag_accesses 63934725 # Number of tag accesses 1250system.cpu.dcache.tags.data_accesses 63934725 # Number of data accesses 1251system.cpu.dcache.ReadReq_hits::cpu.data 7287009 # number of ReadReq hits 1252system.cpu.dcache.ReadReq_hits::total 7287009 # number of ReadReq hits 1253system.cpu.dcache.WriteReq_hits::cpu.data 4187789 # number of WriteReq hits 1254system.cpu.dcache.WriteReq_hits::total 4187789 # number of WriteReq hits 1255system.cpu.dcache.LoadLockedReq_hits::cpu.data 186297 # number of LoadLockedReq hits 1256system.cpu.dcache.LoadLockedReq_hits::total 186297 # number of LoadLockedReq hits 1257system.cpu.dcache.StoreCondReq_hits::cpu.data 215715 # number of StoreCondReq hits 1258system.cpu.dcache.StoreCondReq_hits::total 215715 # number of StoreCondReq hits 1259system.cpu.dcache.demand_hits::cpu.data 11474798 # number of demand (read+write) hits 1260system.cpu.dcache.demand_hits::total 11474798 # number of demand (read+write) hits 1261system.cpu.dcache.overall_hits::cpu.data 11474798 # number of overall hits 1262system.cpu.dcache.overall_hits::total 11474798 # number of overall hits 1263system.cpu.dcache.ReadReq_misses::cpu.data 1776849 # number of ReadReq misses 1264system.cpu.dcache.ReadReq_misses::total 1776849 # number of ReadReq misses 1265system.cpu.dcache.WriteReq_misses::cpu.data 1955456 # number of WriteReq misses 1266system.cpu.dcache.WriteReq_misses::total 1955456 # number of WriteReq misses 1267system.cpu.dcache.LoadLockedReq_misses::cpu.data 23283 # number of LoadLockedReq misses 1268system.cpu.dcache.LoadLockedReq_misses::total 23283 # number of LoadLockedReq misses 1269system.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses 1270system.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses 1271system.cpu.dcache.demand_misses::cpu.data 3732305 # number of demand (read+write) misses 1272system.cpu.dcache.demand_misses::total 3732305 # number of demand (read+write) misses 1273system.cpu.dcache.overall_misses::cpu.data 3732305 # number of overall misses 1274system.cpu.dcache.overall_misses::total 3732305 # number of overall misses 1275system.cpu.dcache.ReadReq_miss_latency::cpu.data 39503001495 # number of ReadReq miss cycles 1276system.cpu.dcache.ReadReq_miss_latency::total 39503001495 # number of ReadReq miss cycles 1277system.cpu.dcache.WriteReq_miss_latency::cpu.data 78159072008 # number of WriteReq miss cycles 1278system.cpu.dcache.WriteReq_miss_latency::total 78159072008 # number of WriteReq miss cycles 1279system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364867750 # number of LoadLockedReq miss cycles 1280system.cpu.dcache.LoadLockedReq_miss_latency::total 364867750 # number of LoadLockedReq miss cycles 1281system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 402005 # number of StoreCondReq miss cycles 1282system.cpu.dcache.StoreCondReq_miss_latency::total 402005 # number of StoreCondReq miss cycles 1283system.cpu.dcache.demand_miss_latency::cpu.data 117662073503 # number of demand (read+write) miss cycles 1284system.cpu.dcache.demand_miss_latency::total 117662073503 # number of demand (read+write) miss cycles 1285system.cpu.dcache.overall_miss_latency::cpu.data 117662073503 # number of overall miss cycles 1286system.cpu.dcache.overall_miss_latency::total 117662073503 # number of overall miss cycles 1287system.cpu.dcache.ReadReq_accesses::cpu.data 9063858 # number of ReadReq accesses(hits+misses) 1288system.cpu.dcache.ReadReq_accesses::total 9063858 # number of ReadReq accesses(hits+misses) 1289system.cpu.dcache.WriteReq_accesses::cpu.data 6143245 # number of WriteReq accesses(hits+misses) 1290system.cpu.dcache.WriteReq_accesses::total 6143245 # number of WriteReq accesses(hits+misses) 1291system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209580 # number of LoadLockedReq accesses(hits+misses) 1292system.cpu.dcache.LoadLockedReq_accesses::total 209580 # number of LoadLockedReq accesses(hits+misses) 1293system.cpu.dcache.StoreCondReq_accesses::cpu.data 215741 # number of StoreCondReq accesses(hits+misses) 1294system.cpu.dcache.StoreCondReq_accesses::total 215741 # number of StoreCondReq accesses(hits+misses) 1295system.cpu.dcache.demand_accesses::cpu.data 15207103 # number of demand (read+write) accesses 1296system.cpu.dcache.demand_accesses::total 15207103 # number of demand (read+write) accesses 1297system.cpu.dcache.overall_accesses::cpu.data 15207103 # number of overall (read+write) accesses 1298system.cpu.dcache.overall_accesses::total 15207103 # number of overall (read+write) accesses 1299system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196037 # miss rate for ReadReq accesses 1300system.cpu.dcache.ReadReq_miss_rate::total 0.196037 # miss rate for ReadReq accesses 1301system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318310 # miss rate for WriteReq accesses 1302system.cpu.dcache.WriteReq_miss_rate::total 0.318310 # miss rate for WriteReq accesses 1303system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111094 # miss rate for LoadLockedReq accesses 1304system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111094 # miss rate for LoadLockedReq accesses 1305system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses 1306system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses 1307system.cpu.dcache.demand_miss_rate::cpu.data 0.245432 # miss rate for demand accesses 1308system.cpu.dcache.demand_miss_rate::total 0.245432 # miss rate for demand accesses 1309system.cpu.dcache.overall_miss_rate::cpu.data 0.245432 # miss rate for overall accesses 1310system.cpu.dcache.overall_miss_rate::total 0.245432 # miss rate for overall accesses 1311system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22232.053199 # average ReadReq miss latency 1312system.cpu.dcache.ReadReq_avg_miss_latency::total 22232.053199 # average ReadReq miss latency 1313system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39969.742100 # average WriteReq miss latency 1314system.cpu.dcache.WriteReq_avg_miss_latency::total 39969.742100 # average WriteReq miss latency 1315system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15670.993858 # average LoadLockedReq miss latency 1316system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15670.993858 # average LoadLockedReq miss latency 1317system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15461.730769 # average StoreCondReq miss latency 1318system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15461.730769 # average StoreCondReq miss latency 1319system.cpu.dcache.demand_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency 1320system.cpu.dcache.demand_avg_miss_latency::total 31525.310365 # average overall miss latency 1321system.cpu.dcache.overall_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency 1322system.cpu.dcache.overall_avg_miss_latency::total 31525.310365 # average overall miss latency 1323system.cpu.dcache.blocked_cycles::no_mshrs 3999248 # number of cycles access was blocked 1324system.cpu.dcache.blocked_cycles::no_targets 1376 # number of cycles access was blocked 1325system.cpu.dcache.blocked::no_mshrs 180044 # number of cycles access was blocked 1326system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked 1327system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.212615 # average number of cycles each access was blocked 1328system.cpu.dcache.avg_blocked_cycles::no_targets 62.545455 # average number of cycles each access was blocked 1329system.cpu.dcache.fast_writes 0 # number of fast writes performed 1330system.cpu.dcache.cache_copies 0 # number of cache copies performed 1331system.cpu.dcache.writebacks::writebacks 842679 # number of writebacks 1332system.cpu.dcache.writebacks::total 842679 # number of writebacks 1333system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680758 # number of ReadReq MSHR hits 1334system.cpu.dcache.ReadReq_mshr_hits::total 680758 # number of ReadReq MSHR hits 1335system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664340 # number of WriteReq MSHR hits 1336system.cpu.dcache.WriteReq_mshr_hits::total 1664340 # number of WriteReq MSHR hits 1337system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5292 # number of LoadLockedReq MSHR hits 1338system.cpu.dcache.LoadLockedReq_mshr_hits::total 5292 # number of LoadLockedReq MSHR hits 1339system.cpu.dcache.demand_mshr_hits::cpu.data 2345098 # number of demand (read+write) MSHR hits 1340system.cpu.dcache.demand_mshr_hits::total 2345098 # number of demand (read+write) MSHR hits 1341system.cpu.dcache.overall_mshr_hits::cpu.data 2345098 # number of overall MSHR hits 1342system.cpu.dcache.overall_mshr_hits::total 2345098 # number of overall MSHR hits 1343system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096091 # number of ReadReq MSHR misses 1344system.cpu.dcache.ReadReq_mshr_misses::total 1096091 # number of ReadReq MSHR misses 1345system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291116 # number of WriteReq MSHR misses 1346system.cpu.dcache.WriteReq_mshr_misses::total 291116 # number of WriteReq MSHR misses 1347system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17991 # number of LoadLockedReq MSHR misses 1348system.cpu.dcache.LoadLockedReq_mshr_misses::total 17991 # number of LoadLockedReq MSHR misses 1349system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses 1350system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses 1351system.cpu.dcache.demand_mshr_misses::cpu.data 1387207 # number of demand (read+write) MSHR misses 1352system.cpu.dcache.demand_mshr_misses::total 1387207 # number of demand (read+write) MSHR misses 1353system.cpu.dcache.overall_mshr_misses::cpu.data 1387207 # number of overall MSHR misses 1354system.cpu.dcache.overall_mshr_misses::total 1387207 # number of overall MSHR misses 1355system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27515724784 # number of ReadReq MSHR miss cycles 1356system.cpu.dcache.ReadReq_mshr_miss_latency::total 27515724784 # number of ReadReq MSHR miss cycles 1357system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11792803134 # number of WriteReq MSHR miss cycles 1358system.cpu.dcache.WriteReq_mshr_miss_latency::total 11792803134 # number of WriteReq MSHR miss cycles 1359system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204517750 # number of LoadLockedReq MSHR miss cycles 1360system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204517750 # number of LoadLockedReq MSHR miss cycles 1361system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 349995 # number of StoreCondReq MSHR miss cycles 1362system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 349995 # number of StoreCondReq MSHR miss cycles 1363system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39308527918 # number of demand (read+write) MSHR miss cycles 1364system.cpu.dcache.demand_mshr_miss_latency::total 39308527918 # number of demand (read+write) MSHR miss cycles 1365system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39308527918 # number of overall MSHR miss cycles 1366system.cpu.dcache.overall_mshr_miss_latency::total 39308527918 # number of overall MSHR miss cycles 1367system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423597000 # number of ReadReq MSHR uncacheable cycles 1368system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423597000 # number of ReadReq MSHR uncacheable cycles 1369system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999614498 # number of WriteReq MSHR uncacheable cycles 1370system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999614498 # number of WriteReq MSHR uncacheable cycles 1371system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423211498 # number of overall MSHR uncacheable cycles 1372system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423211498 # number of overall MSHR uncacheable cycles 1373system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120930 # mshr miss rate for ReadReq accesses 1374system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120930 # mshr miss rate for ReadReq accesses 1375system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses 1376system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses 1377system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085843 # mshr miss rate for LoadLockedReq accesses 1378system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085843 # mshr miss rate for LoadLockedReq accesses 1379system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses 1380system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses 1381system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses 1382system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses 1383system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses 1384system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses 1385system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25103.503983 # average ReadReq mshr miss latency 1386system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25103.503983 # average ReadReq mshr miss latency 1387system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40508.948783 # average WriteReq mshr miss latency 1388system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40508.948783 # average WriteReq mshr miss latency 1389system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11367.781113 # average LoadLockedReq mshr miss latency 1390system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11367.781113 # average LoadLockedReq mshr miss latency 1391system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13461.346154 # average StoreCondReq mshr miss latency 1392system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13461.346154 # average StoreCondReq mshr miss latency 1393system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency 1394system.cpu.dcache.demand_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency 1395system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency 1396system.cpu.dcache.overall_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency 1397system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1398system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1399system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1400system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1401system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1402system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1403system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1227system.iocache.tags.replacements 41685 # number of replacements 1228system.iocache.tags.tagsinuse 1.260575 # Cycle average of tags in use 1229system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1230system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1231system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1232system.iocache.tags.warmup_cycle 1709355371000 # Cycle when the warmup percentage was hit. 1233system.iocache.tags.occ_blocks::tsunami.ide 1.260575 # Average occupied blocks per requestor 1234system.iocache.tags.occ_percent::tsunami.ide 0.078786 # Average percentage of cache occupancy 1235system.iocache.tags.occ_percent::total 0.078786 # Average percentage of cache occupancy 1236system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1237system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1238system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1239system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1240system.iocache.tags.data_accesses 375525 # Number of data accesses 1241system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1242system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1243system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 1244system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 1245system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1246system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1247system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1248system.iocache.overall_misses::total 173 # number of overall misses 1249system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 1250system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 1251system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13648838856 # number of WriteInvalidateReq miss cycles 1252system.iocache.WriteInvalidateReq_miss_latency::total 13648838856 # number of WriteInvalidateReq miss cycles 1253system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 1254system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 1255system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 1256system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 1257system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1258system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1259system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1260system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 1261system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1262system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1263system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1264system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1265system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1266system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1267system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1268system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1269system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1270system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1271system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1272system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1273system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 1274system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 1275system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328476.098768 # average WriteInvalidateReq miss latency 1276system.iocache.WriteInvalidateReq_avg_miss_latency::total 328476.098768 # average WriteInvalidateReq miss latency 1277system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 1278system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 1279system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 1280system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 1281system.iocache.blocked_cycles::no_mshrs 206574 # number of cycles access was blocked 1282system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1283system.iocache.blocked::no_mshrs 23538 # number of cycles access was blocked 1284system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1285system.iocache.avg_blocked_cycles::no_mshrs 8.776192 # average number of cycles each access was blocked 1286system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1287system.iocache.fast_writes 0 # number of fast writes performed 1288system.iocache.cache_copies 0 # number of cache copies performed 1289system.iocache.writebacks::writebacks 41512 # number of writebacks 1290system.iocache.writebacks::total 41512 # number of writebacks 1291system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1292system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1293system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1294system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1295system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1296system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1297system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1298system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1299system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 1300system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 1301system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11488062928 # number of WriteInvalidateReq MSHR miss cycles 1302system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11488062928 # number of WriteInvalidateReq MSHR miss cycles 1303system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 1304system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 1305system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 1306system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 1307system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1308system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1309system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1310system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1311system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1312system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1313system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1314system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1315system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 1316system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 1317system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276474.367732 # average WriteInvalidateReq mshr miss latency 1318system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276474.367732 # average WriteInvalidateReq mshr miss latency 1319system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1320system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 1321system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1322system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 1323system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1324system.membus.trans_dist::ReadReq 296033 # Transaction distribution 1325system.membus.trans_dist::ReadResp 295940 # Transaction distribution 1326system.membus.trans_dist::WriteReq 9597 # Transaction distribution 1327system.membus.trans_dist::WriteResp 9597 # Transaction distribution 1328system.membus.trans_dist::Writeback 117441 # Transaction distribution 1329system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1330system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 1331system.membus.trans_dist::UpgradeReq 186 # Transaction distribution 1332system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution 1333system.membus.trans_dist::UpgradeResp 192 # Transaction distribution 1334system.membus.trans_dist::ReadExReq 115233 # Transaction distribution 1335system.membus.trans_dist::ReadExResp 115233 # Transaction distribution 1336system.membus.trans_dist::BadAddressError 93 # Transaction distribution 1337system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) 1338system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884176 # Packet count per connected master and slave (bytes) 1339system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 186 # Packet count per connected master and slave (bytes) 1340system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917416 # Packet count per connected master and slave (bytes) 1341system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1342system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) 1343system.membus.pkt_count::total 1042220 # Packet count per connected master and slave (bytes) 1344system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) 1345system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702400 # Cumulative packet size per connected master and slave (bytes) 1346system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746540 # Cumulative packet size per connected master and slave (bytes) 1347system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1348system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1349system.membus.pkt_size::total 36063596 # Cumulative packet size per connected master and slave (bytes) 1350system.membus.snoops 435 # Total snoops (count) 1351system.membus.snoop_fanout::samples 563522 # Request fanout histogram 1352system.membus.snoop_fanout::mean 1 # Request fanout histogram 1353system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1354system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1355system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1356system.membus.snoop_fanout::1 563522 100.00% 100.00% # Request fanout histogram 1357system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1358system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1359system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1360system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1361system.membus.snoop_fanout::total 563522 # Request fanout histogram 1362system.membus.reqLayer0.occupancy 31470000 # Layer occupancy (ticks) 1363system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1364system.membus.reqLayer1.occupancy 1857946999 # Layer occupancy (ticks) 1365system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1366system.membus.reqLayer2.occupancy 115000 # Layer occupancy (ticks) 1367system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1368system.membus.respLayer1.occupancy 3754266813 # Layer occupancy (ticks) 1369system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1370system.membus.respLayer2.occupancy 43145464 # Layer occupancy (ticks) 1371system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1372system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1373system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1374system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1375system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1376system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1377system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1378system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1379system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1380system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1381system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1382system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1383system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1384system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1385system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1386system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1387system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1388system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1389system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1390system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1391system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1392system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1393system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1394system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1395system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1396system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1397system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1398system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1399system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1400system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1401system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1402system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1404system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1403system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1405system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed 1406system.cpu.kern.inst.hwrei 210986 # number of hwrei instructions executed 1407system.cpu.kern.ipl_count::0 74656 40.97% 40.97% # number of times we switched to this ipl | 1404system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed 1405system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed 1406system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl |
| 1408system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1409system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl | 1407system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1408system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl |
| 1410system.cpu.kern.ipl_count::31 105550 57.93% 100.00% # number of times we switched to this ipl 1411system.cpu.kern.ipl_count::total 182216 # number of times we switched to this ipl 1412system.cpu.kern.ipl_good::0 73289 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 1409system.cpu.kern.ipl_count::31 105561 57.93% 100.00% # number of times we switched to this ipl 1410system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl 1411system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 1413system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1414system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl | 1412system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1413system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl |
| 1415system.cpu.kern.ipl_good::31 73289 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1416system.cpu.kern.ipl_good::total 148588 # number of times we switched to this ipl from a different ipl 1417system.cpu.kern.ipl_ticks::0 1817327743500 97.76% 97.76% # number of cycles we spent at this ipl 1418system.cpu.kern.ipl_ticks::21 61881000 0.00% 97.76% # number of cycles we spent at this ipl 1419system.cpu.kern.ipl_ticks::22 521765000 0.03% 97.79% # number of cycles we spent at this ipl 1420system.cpu.kern.ipl_ticks::31 41126450000 2.21% 100.00% # number of cycles we spent at this ipl 1421system.cpu.kern.ipl_ticks::total 1859037839500 # number of cycles we spent at this ipl 1422system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl | 1414system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1415system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl 1416system.cpu.kern.ipl_ticks::0 1817339213500 97.76% 97.76% # number of cycles we spent at this ipl 1417system.cpu.kern.ipl_ticks::21 61863500 0.00% 97.76% # number of cycles we spent at this ipl 1418system.cpu.kern.ipl_ticks::22 521835500 0.03% 97.79% # number of cycles we spent at this ipl 1419system.cpu.kern.ipl_ticks::31 41125418500 2.21% 100.00% # number of cycles we spent at this ipl 1420system.cpu.kern.ipl_ticks::total 1859048331000 # number of cycles we spent at this ipl 1421system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl |
| 1423system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1424system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 1422system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1423system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 1425system.cpu.kern.ipl_used::31 0.694353 # fraction of swpipl calls that actually changed the ipl 1426system.cpu.kern.ipl_used::total 0.815450 # fraction of swpipl calls that actually changed the ipl | 1424system.cpu.kern.ipl_used::31 0.694338 # fraction of swpipl calls that actually changed the ipl 1425system.cpu.kern.ipl_used::total 0.815440 # fraction of swpipl calls that actually changed the ipl |
| 1427system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1428system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1429system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1430system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1431system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1432system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1433system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1434system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 1457system.cpu.kern.syscall::total 326 # number of syscalls executed 1458system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1459system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1460system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1461system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1462system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed 1463system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1464system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed | 1426system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1427system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1428system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1429system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1430system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1431system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1432system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1433system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 1456system.cpu.kern.syscall::total 326 # number of syscalls executed 1457system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1458system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1459system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1460system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1461system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed 1462system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1463system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed |
| 1465system.cpu.kern.callpal::swpipl 175101 91.22% 93.43% # number of callpals executed | 1464system.cpu.kern.callpal::swpipl 175118 91.22% 93.44% # number of callpals executed |
| 1466system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 1467system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1468system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1469system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1470system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1471system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 1472system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1473system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 1465system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed 1466system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1467system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1468system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1469system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1470system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 1471system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1472system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 1474system.cpu.kern.callpal::total 191946 # number of callpals executed 1475system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches 1476system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 1477system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 1478system.cpu.kern.mode_good::kernel 1910 1479system.cpu.kern.mode_good::user 1740 | 1473system.cpu.kern.callpal::total 191963 # number of callpals executed 1474system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches 1475system.cpu.kern.mode_switch::user 1741 # number of protection mode switches 1476system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches 1477system.cpu.kern.mode_good::kernel 1911 1478system.cpu.kern.mode_good::user 1741 |
| 1480system.cpu.kern.mode_good::idle 170 | 1479system.cpu.kern.mode_good::idle 170 |
| 1481system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches | 1480system.cpu.kern.mode_switch_good::kernel 0.326499 # fraction of useful protection mode switches |
| 1482system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1481system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1483system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 1484system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches 1485system.cpu.kern.mode_ticks::kernel 29097785000 1.57% 1.57% # number of ticks spent at the given mode 1486system.cpu.kern.mode_ticks::user 2655967500 0.14% 1.71% # number of ticks spent at the given mode 1487system.cpu.kern.mode_ticks::idle 1827284079000 98.29% 100.00% # number of ticks spent at the given mode | 1482system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 1483system.cpu.kern.mode_switch_good::total 0.394468 # fraction of useful protection mode switches 1484system.cpu.kern.mode_ticks::kernel 29096339500 1.57% 1.57% # number of ticks spent at the given mode 1485system.cpu.kern.mode_ticks::user 2660038000 0.14% 1.71% # number of ticks spent at the given mode 1486system.cpu.kern.mode_ticks::idle 1827291945500 98.29% 100.00% # number of ticks spent at the given mode |
| 1488system.cpu.kern.swap_context 4179 # number of times the context was actually changed 1489 1490---------- End Simulation Statistics ---------- | 1487system.cpu.kern.swap_context 4179 # number of times the context was actually changed 1488 1489---------- End Simulation Statistics ---------- |