| stats.txt (10433:821cbe4a183b) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.859039 # Number of seconds simulated 4sim_ticks 1859038679000 # Number of ticks simulated 5final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.859039 # Number of seconds simulated 4sim_ticks 1859038679000 # Number of ticks simulated 5final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 145866 # Simulator instruction rate (inst/s) 8host_op_rate 145866 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5123409698 # Simulator tick rate (ticks/s) 10host_mem_usage 320704 # Number of bytes of host memory used 11host_seconds 362.85 # Real time elapsed on the host | 7host_inst_rate 164458 # Simulator instruction rate (inst/s) 8host_op_rate 164458 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5776457310 # Simulator tick rate (ticks/s) 10host_mem_usage 314484 # Number of bytes of host memory used 11host_seconds 321.83 # Real time elapsed on the host |
| 12sim_insts 52927600 # Number of instructions simulated 13sim_ops 52927600 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25861824 # Number of bytes read from this memory --- 395 unchanged lines hidden (view full) --- 415system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.iocache.blocked::no_targets 0 # number of cycles access was blocked 417system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.iocache.fast_writes 41552 # number of fast writes performed 420system.iocache.cache_copies 0 # number of cache copies performed 421system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 422system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses | 12sim_insts 52927600 # Number of instructions simulated 13sim_ops 52927600 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25861824 # Number of bytes read from this memory --- 395 unchanged lines hidden (view full) --- 415system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.iocache.blocked::no_targets 0 # number of cycles access was blocked 417system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.iocache.fast_writes 41552 # number of fast writes performed 420system.iocache.cache_copies 0 # number of cache copies performed 421system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 422system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses |
| 423system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 424system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses | |
| 425system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 426system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 427system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 428system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 429system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 430system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 431system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles 432system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles 433system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 434system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 435system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 436system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 437system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 438system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 423system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 424system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 425system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 426system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 427system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 428system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 429system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles 430system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles 431system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 432system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 433system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 434system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 435system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 436system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 439system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses 440system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses | |
| 441system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 442system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 443system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 444system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 445system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 446system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency | 437system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 438system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 439system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 440system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 441system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 442system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency |
| 447system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency 448system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency | 443system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency 444system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 449system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 450system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 451system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 452system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 453system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 454system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 455system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 456system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 1038 unchanged lines hidden --- | 445system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 446system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 447system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 448system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 449system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 450system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 451system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 452system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 1038 unchanged lines hidden --- |