| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.860009 # Number of seconds simulated 4sim_ticks 1860008936000 # Number of ticks simulated 5final_tick 1860008936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.859039 # Number of seconds simulated 4sim_ticks 1859038679000 # Number of ticks simulated 5final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 106543 # Simulator instruction rate (inst/s) 8host_op_rate 106543 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3740252336 # Simulator tick rate (ticks/s) 10host_mem_usage 320492 # Number of bytes of host memory used 11host_seconds 497.30 # Real time elapsed on the host 12sim_insts 52983264 # Number of instructions simulated 13sim_ops 52983264 # Number of ops (including micro ops) simulated | 7host_inst_rate 164972 # Simulator instruction rate (inst/s) 8host_op_rate 164972 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5794497034 # Simulator tick rate (ticks/s) 10host_mem_usage 371088 # Number of bytes of host memory used 11host_seconds 320.83 # Real time elapsed on the host 12sim_insts 52927600 # Number of instructions simulated 13sim_ops 52927600 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 968512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24900352 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 25869824 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 968512 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 968512 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4866048 # Number of bytes written to this memory | 19system.physmem.bytes_read::total 25861824 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 968256 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4860032 # Number of bytes written to this memory |
| 23system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory | 23system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory |
| 24system.physmem.bytes_written::total 7525376 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 15133 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 389068 # Number of read requests responded to by this memory | 24system.physmem.bytes_written::total 7519360 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 15129 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388947 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::total 404216 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 76032 # Number of write requests responded to by this memory | 28system.physmem.num_reads::total 404091 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 75938 # Number of write requests responded to by this memory |
| 30system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory | 30system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory |
| 31system.physmem.num_writes::total 117584 # Number of write requests responded to by this memory 32system.physmem.bw_read::cpu.inst 520703 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.data 13387222 # Total read bandwidth from this memory (bytes/s) | 31system.physmem.num_writes::total 117490 # Number of write requests responded to by this memory 32system.physmem.bw_read::cpu.inst 520837 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.data 13390043 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::total 13908441 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::cpu.inst 520703 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_inst_read::total 520703 # Instruction read bandwidth from this memory (bytes/s) 38system.physmem.bw_write::writebacks 2616142 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_write::tsunami.ide 1429739 # Write bandwidth from this memory (bytes/s) 40system.physmem.bw_write::total 4045882 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_total::writebacks 2616142 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 520703 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 13387222 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::tsunami.ide 1430255 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::total 17954322 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.readReqs 404216 # Number of read requests accepted 47system.physmem.writeReqs 117584 # Number of write requests accepted 48system.physmem.readBursts 404216 # Number of DRAM read bursts, including those serviced by the write queue 49system.physmem.writeBursts 117584 # Number of DRAM write bursts, including those merged in the write queue 50system.physmem.bytesReadDRAM 25858752 # Total number of bytes read from DRAM 51system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue 52system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM 53system.physmem.bytesReadSys 25869824 # Total read bytes from the system interface side 54system.physmem.bytesWrittenSys 7525376 # Total written bytes from the system interface side 55system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue | 35system.physmem.bw_read::total 13911396 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::cpu.inst 520837 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_inst_read::total 520837 # Instruction read bandwidth from this memory (bytes/s) 38system.physmem.bw_write::writebacks 2614272 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_write::tsunami.ide 1430486 # Write bandwidth from this memory (bytes/s) 40system.physmem.bw_write::total 4044757 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_total::writebacks 2614272 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 520837 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 13390043 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::tsunami.ide 1431002 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::total 17956154 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.readReqs 404091 # Number of read requests accepted 47system.physmem.writeReqs 117490 # Number of write requests accepted 48system.physmem.readBursts 404091 # Number of DRAM read bursts, including those serviced by the write queue 49system.physmem.writeBursts 117490 # Number of DRAM write bursts, including those merged in the write queue 50system.physmem.bytesReadDRAM 25850368 # Total number of bytes read from DRAM 51system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue 52system.physmem.bytesWritten 7517888 # Total number of bytes written to DRAM 53system.physmem.bytesReadSys 25861824 # Total read bytes from the system interface side 54system.physmem.bytesWrittenSys 7519360 # Total written bytes from the system interface side 55system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue |
| 56system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 56system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 57system.physmem.neitherReadNorWriteReqs 213 # Number of requests that are neither read nor write 58system.physmem.perBankRdBursts::0 25622 # Per bank write bursts 59system.physmem.perBankRdBursts::1 25451 # Per bank write bursts 60system.physmem.perBankRdBursts::2 25608 # Per bank write bursts 61system.physmem.perBankRdBursts::3 25528 # Per bank write bursts 62system.physmem.perBankRdBursts::4 25399 # Per bank write bursts 63system.physmem.perBankRdBursts::5 24757 # Per bank write bursts 64system.physmem.perBankRdBursts::6 24940 # Per bank write bursts 65system.physmem.perBankRdBursts::7 25074 # Per bank write bursts 66system.physmem.perBankRdBursts::8 24966 # Per bank write bursts 67system.physmem.perBankRdBursts::9 25053 # Per bank write bursts 68system.physmem.perBankRdBursts::10 25586 # Per bank write bursts 69system.physmem.perBankRdBursts::11 24884 # Per bank write bursts 70system.physmem.perBankRdBursts::12 24485 # Per bank write bursts 71system.physmem.perBankRdBursts::13 25285 # Per bank write bursts 72system.physmem.perBankRdBursts::14 25789 # Per bank write bursts 73system.physmem.perBankRdBursts::15 25616 # Per bank write bursts 74system.physmem.perBankWrBursts::0 7925 # Per bank write bursts 75system.physmem.perBankWrBursts::1 7509 # Per bank write bursts 76system.physmem.perBankWrBursts::2 7974 # Per bank write bursts 77system.physmem.perBankWrBursts::3 7525 # Per bank write bursts 78system.physmem.perBankWrBursts::4 7335 # Per bank write bursts 79system.physmem.perBankWrBursts::5 6682 # Per bank write bursts 80system.physmem.perBankWrBursts::6 6769 # Per bank write bursts 81system.physmem.perBankWrBursts::7 6701 # Per bank write bursts 82system.physmem.perBankWrBursts::8 7135 # Per bank write bursts 83system.physmem.perBankWrBursts::9 6719 # Per bank write bursts 84system.physmem.perBankWrBursts::10 7431 # Per bank write bursts 85system.physmem.perBankWrBursts::11 6970 # Per bank write bursts 86system.physmem.perBankWrBursts::12 7113 # Per bank write bursts 87system.physmem.perBankWrBursts::13 7882 # Per bank write bursts 88system.physmem.perBankWrBursts::14 8065 # Per bank write bursts 89system.physmem.perBankWrBursts::15 7817 # Per bank write bursts | 57system.physmem.neitherReadNorWriteReqs 193 # Number of requests that are neither read nor write 58system.physmem.perBankRdBursts::0 25747 # Per bank write bursts 59system.physmem.perBankRdBursts::1 25572 # Per bank write bursts 60system.physmem.perBankRdBursts::2 25523 # Per bank write bursts 61system.physmem.perBankRdBursts::3 25355 # Per bank write bursts 62system.physmem.perBankRdBursts::4 25392 # Per bank write bursts 63system.physmem.perBankRdBursts::5 24811 # Per bank write bursts 64system.physmem.perBankRdBursts::6 25029 # Per bank write bursts 65system.physmem.perBankRdBursts::7 25134 # Per bank write bursts 66system.physmem.perBankRdBursts::8 24968 # Per bank write bursts 67system.physmem.perBankRdBursts::9 25052 # Per bank write bursts 68system.physmem.perBankRdBursts::10 25439 # Per bank write bursts 69system.physmem.perBankRdBursts::11 24779 # Per bank write bursts 70system.physmem.perBankRdBursts::12 24568 # Per bank write bursts 71system.physmem.perBankRdBursts::13 25250 # Per bank write bursts 72system.physmem.perBankRdBursts::14 25688 # Per bank write bursts 73system.physmem.perBankRdBursts::15 25605 # Per bank write bursts 74system.physmem.perBankWrBursts::0 8041 # Per bank write bursts 75system.physmem.perBankWrBursts::1 7603 # Per bank write bursts 76system.physmem.perBankWrBursts::2 7894 # Per bank write bursts 77system.physmem.perBankWrBursts::3 7385 # Per bank write bursts 78system.physmem.perBankWrBursts::4 7327 # Per bank write bursts 79system.physmem.perBankWrBursts::5 6730 # Per bank write bursts 80system.physmem.perBankWrBursts::6 6858 # Per bank write bursts 81system.physmem.perBankWrBursts::7 6765 # Per bank write bursts 82system.physmem.perBankWrBursts::8 7133 # Per bank write bursts 83system.physmem.perBankWrBursts::9 6722 # Per bank write bursts 84system.physmem.perBankWrBursts::10 7301 # Per bank write bursts 85system.physmem.perBankWrBursts::11 6871 # Per bank write bursts 86system.physmem.perBankWrBursts::12 7190 # Per bank write bursts 87system.physmem.perBankWrBursts::13 7853 # Per bank write bursts 88system.physmem.perBankWrBursts::14 7964 # Per bank write bursts 89system.physmem.perBankWrBursts::15 7830 # Per bank write bursts |
| 90system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 91system.physmem.numWrRetry 9 # Number of times write queue was full causing retry | 90system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 91system.physmem.numWrRetry 9 # Number of times write queue was full causing retry |
| 92system.physmem.totGap 1860003602000 # Total gap between requests | 92system.physmem.totGap 1859033424000 # Total gap between requests |
| 93system.physmem.readPktSize::0 0 # Read request sizes (log2) 94system.physmem.readPktSize::1 0 # Read request sizes (log2) 95system.physmem.readPktSize::2 0 # Read request sizes (log2) 96system.physmem.readPktSize::3 0 # Read request sizes (log2) 97system.physmem.readPktSize::4 0 # Read request sizes (log2) 98system.physmem.readPktSize::5 0 # Read request sizes (log2) | 93system.physmem.readPktSize::0 0 # Read request sizes (log2) 94system.physmem.readPktSize::1 0 # Read request sizes (log2) 95system.physmem.readPktSize::2 0 # Read request sizes (log2) 96system.physmem.readPktSize::3 0 # Read request sizes (log2) 97system.physmem.readPktSize::4 0 # Read request sizes (log2) 98system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 99system.physmem.readPktSize::6 404216 # Read request sizes (log2) | 99system.physmem.readPktSize::6 404091 # Read request sizes (log2) |
| 100system.physmem.writePktSize::0 0 # Write request sizes (log2) 101system.physmem.writePktSize::1 0 # Write request sizes (log2) 102system.physmem.writePktSize::2 0 # Write request sizes (log2) 103system.physmem.writePktSize::3 0 # Write request sizes (log2) 104system.physmem.writePktSize::4 0 # Write request sizes (log2) 105system.physmem.writePktSize::5 0 # Write request sizes (log2) | 100system.physmem.writePktSize::0 0 # Write request sizes (log2) 101system.physmem.writePktSize::1 0 # Write request sizes (log2) 102system.physmem.writePktSize::2 0 # Write request sizes (log2) 103system.physmem.writePktSize::3 0 # Write request sizes (log2) 104system.physmem.writePktSize::4 0 # Write request sizes (log2) 105system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 106system.physmem.writePktSize::6 117584 # Write request sizes (log2) | 106system.physmem.writePktSize::6 117490 # Write request sizes (log2) |
| 107system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see | 107system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see |
| 108system.physmem.rdQLenPdf::1 37801 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 42911 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 8183 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see | 108system.physmem.rdQLenPdf::1 37620 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 42963 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 8182 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see |
| 113system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 146system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 113system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 146system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::15 1589 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 2253 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 3103 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 4140 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 5361 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6916 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 7275 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 8550 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 9031 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 8802 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 9048 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 7865 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 7965 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 6074 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 5926 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::32 5563 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::33 182 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::34 134 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::39 119 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::58 51 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see 203system.physmem.bytesPerActivate::samples 61090 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::mean 546.434703 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::gmean 336.353089 # Bytes accessed per row activation 206system.physmem.bytesPerActivate::stdev 417.871718 # Bytes accessed per row activation 207system.physmem.bytesPerActivate::0-127 13232 21.66% 21.66% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::128-255 10443 17.09% 38.75% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::256-383 4742 7.76% 46.52% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::384-511 2710 4.44% 50.95% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::512-639 2446 4.00% 54.96% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::640-767 1597 2.61% 57.57% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::768-895 1401 2.29% 59.86% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::896-1023 1610 2.64% 62.50% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1024-1151 22909 37.50% 100.00% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::total 61090 # Bytes accessed per row activation 217system.physmem.rdPerTurnAround::samples 5256 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::mean 76.868151 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::stdev 2912.510758 # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::0-8191 5253 99.94% 99.94% # Reads before turning the bus around for writes | 154system.physmem.wrQLenPdf::15 1544 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 2141 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 3054 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 4174 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 5440 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6763 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 7142 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 8810 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 9005 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 8758 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 8976 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 7859 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 7939 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 6211 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 6103 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 6088 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::35 158 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::36 154 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::39 113 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::41 141 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::44 155 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see 203system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::mean 544.521149 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::gmean 334.160448 # Bytes accessed per row activation 206system.physmem.bytesPerActivate::stdev 418.029082 # Bytes accessed per row activation 207system.physmem.bytesPerActivate::0-127 13483 22.00% 22.00% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::128-255 10372 16.93% 38.93% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::256-383 4758 7.76% 46.69% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::384-511 2785 4.54% 51.24% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::512-639 2293 3.74% 54.98% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::640-767 1673 2.73% 57.71% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::768-895 1477 2.41% 60.12% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::896-1023 1592 2.60% 62.72% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1024-1151 22847 37.28% 100.00% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation 217system.physmem.rdPerTurnAround::samples 5232 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::mean 77.198394 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::stdev 2919.153555 # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::0-8191 5229 99.94% 99.94% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 221system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 224system.physmem.rdPerTurnAround::total 5256 # Reads before turning the bus around for writes 225system.physmem.wrPerTurnAround::samples 5256 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::mean 22.365297 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::gmean 19.103318 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::stdev 20.103778 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::16-19 4494 85.50% 85.50% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20-23 124 2.36% 87.86% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::24-27 9 0.17% 88.03% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::28-31 232 4.41% 92.45% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::32-35 40 0.76% 93.21% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::36-39 6 0.11% 93.32% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::40-43 12 0.23% 93.55% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::44-47 3 0.06% 93.61% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-51 27 0.51% 94.12% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::52-55 3 0.06% 94.18% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::56-59 1 0.02% 94.20% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::60-63 1 0.02% 94.22% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::64-67 15 0.29% 94.50% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::68-71 5 0.10% 94.60% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-75 3 0.06% 94.65% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-83 31 0.59% 95.24% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::84-87 8 0.15% 95.40% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::88-91 4 0.08% 95.47% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::92-95 5 0.10% 95.57% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::96-99 188 3.58% 99.14% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::108-111 2 0.04% 99.18% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::112-115 5 0.10% 99.28% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::124-127 3 0.06% 99.33% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::128-131 11 0.21% 99.54% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::132-135 3 0.06% 99.60% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::136-139 1 0.02% 99.62% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::140-143 7 0.13% 99.75% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::144-147 5 0.10% 99.85% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::160-163 2 0.04% 99.92% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::164-167 2 0.04% 99.96% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::total 5256 # Writes before turning the bus around for reads 263system.physmem.totQLat 3626109250 # Total ticks spent queuing 264system.physmem.totMemAccLat 11201915500 # Total ticks spent from burst creation until serviced by the DRAM 265system.physmem.totBusLat 2020215000 # Total ticks spent in databus transfers 266system.physmem.avgQLat 8974.56 # Average queueing delay per DRAM burst | 224system.physmem.rdPerTurnAround::total 5232 # Reads before turning the bus around for writes 225system.physmem.wrPerTurnAround::samples 5232 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::mean 22.451644 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::gmean 19.067800 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::stdev 21.155033 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::16-19 4469 85.42% 85.42% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20-23 138 2.64% 88.05% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::24-27 12 0.23% 88.28% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::28-31 232 4.43% 92.72% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::32-35 44 0.84% 93.56% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::36-39 2 0.04% 93.60% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::40-43 5 0.10% 93.69% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::44-47 10 0.19% 93.88% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-51 17 0.32% 94.21% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::52-55 2 0.04% 94.25% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::56-59 1 0.02% 94.27% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::60-63 2 0.04% 94.30% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::64-67 7 0.13% 94.44% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::68-71 3 0.06% 94.50% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-75 4 0.08% 94.57% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::76-79 1 0.02% 94.59% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::80-83 28 0.54% 95.13% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::84-87 15 0.29% 95.41% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::92-95 15 0.29% 95.70% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::96-99 171 3.27% 98.97% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::100-103 6 0.11% 99.08% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::116-119 2 0.04% 99.14% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::120-123 2 0.04% 99.18% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::124-127 1 0.02% 99.20% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::128-131 5 0.10% 99.29% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::132-135 1 0.02% 99.31% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::136-139 6 0.11% 99.43% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::140-143 4 0.08% 99.50% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::144-147 11 0.21% 99.71% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::148-151 1 0.02% 99.73% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::152-155 2 0.04% 99.77% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::176-179 1 0.02% 99.85% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::224-227 7 0.13% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 5232 # Writes before turning the bus around for reads 268system.physmem.totQLat 3681492750 # Total ticks spent queuing 269system.physmem.totMemAccLat 11254842750 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 2019560000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 9114.59 # Average queueing delay per DRAM burst |
| 267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 268system.physmem.avgMemAccLat 27724.56 # Average memory access latency per DRAM burst 269system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s | 273system.physmem.avgMemAccLat 27864.59 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 13.91 # Average DRAM read bandwidth in MiByte/s |
| 270system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 271system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s | 275system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s |
| 272system.physmem.avgWrBWSys 4.05 # Average system write bandwidth in MiByte/s | 277system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s |
| 273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 274system.physmem.busUtil 0.14 # Data bus utilization in percentage 275system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 276system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.14 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 277system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing 278system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing 279system.physmem.readRowHits 364992 # Number of row buffer hits during reads 280system.physmem.writeRowHits 95512 # Number of row buffer hits during writes 281system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads 282system.physmem.writeRowHitRate 81.23 # Row buffer hit rate for writes 283system.physmem.avgGap 3564591.03 # Average gap between requests 284system.physmem.pageHitRate 88.28 # Row buffer hit rate, read and write combined 285system.physmem.memoryStateTime::IDLE 1761923491250 # Time in different power states 286system.physmem.memoryStateTime::REF 62109580000 # Time in different power states | 282system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing 284system.physmem.readRowHits 364830 # Number of row buffer hits during reads 285system.physmem.writeRowHits 95269 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 90.32 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 81.09 # Row buffer hit rate for writes 288system.physmem.avgGap 3564227.65 # Average gap between requests 289system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined 290system.physmem.memoryStateTime::IDLE 1761056207000 # Time in different power states 291system.physmem.memoryStateTime::REF 62077340000 # Time in different power states |
| 287system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 292system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 288system.physmem.memoryStateTime::ACT 35970256750 # Time in different power states | 293system.physmem.memoryStateTime::ACT 35903990500 # Time in different power states |
| 289system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 294system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 290system.membus.throughput 17983494 # Throughput (bytes/s) 291system.membus.trans_dist::ReadReq 296097 # Transaction distribution 292system.membus.trans_dist::ReadResp 296008 # Transaction distribution 293system.membus.trans_dist::WriteReq 9598 # Transaction distribution 294system.membus.trans_dist::WriteResp 9598 # Transaction distribution 295system.membus.trans_dist::Writeback 76032 # Transaction distribution | 295system.membus.trans_dist::ReadReq 296046 # Transaction distribution 296system.membus.trans_dist::ReadResp 295957 # Transaction distribution 297system.membus.trans_dist::WriteReq 9597 # Transaction distribution 298system.membus.trans_dist::WriteResp 9597 # Transaction distribution 299system.membus.trans_dist::Writeback 75938 # Transaction distribution |
| 296system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 297system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution | 300system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 301system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 298system.membus.trans_dist::UpgradeReq 207 # Transaction distribution 299system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution 300system.membus.trans_dist::UpgradeResp 213 # Transaction distribution 301system.membus.trans_dist::ReadExReq 115296 # Transaction distribution 302system.membus.trans_dist::ReadExResp 115296 # Transaction distribution | 302system.membus.trans_dist::UpgradeReq 188 # Transaction distribution 303system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution 304system.membus.trans_dist::UpgradeResp 193 # Transaction distribution 305system.membus.trans_dist::ReadExReq 115222 # Transaction distribution 306system.membus.trans_dist::ReadExResp 115222 # Transaction distribution |
| 303system.membus.trans_dist::BadAddressError 89 # Transaction distribution | 307system.membus.trans_dist::BadAddressError 89 # Transaction distribution |
| 304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884860 # Packet count per connected master and slave (bytes) | 308system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884476 # Packet count per connected master and slave (bytes) |
| 306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) | 310system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) |
| 307system.membus.pkt_count_system.cpu.l2cache.mem_side::total 918094 # Packet count per connected master and slave (bytes) | 311system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917708 # Packet count per connected master and slave (bytes) |
| 308system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) | 312system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 313system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) |
| 310system.membus.pkt_count::total 1001386 # Packet count per connected master and slave (bytes) 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30734912 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30779060 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 316system.membus.tot_pkt_size::total 33439348 # Cumulative packet size per connected master and slave (bytes) 317system.membus.data_through_bus 33439348 # Total data (bytes) 318system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) 319system.membus.reqLayer0.occupancy 29284000 # Layer occupancy (ticks) | 314system.membus.pkt_count::total 1001000 # Packet count per connected master and slave (bytes) 315system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) 316system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30720896 # Cumulative packet size per connected master and slave (bytes) 317system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30765036 # Cumulative packet size per connected master and slave (bytes) 318system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 319system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 320system.membus.pkt_size::total 33425324 # Cumulative packet size per connected master and slave (bytes) 321system.membus.snoops 158 # Total snoops (count) 322system.membus.snoop_fanout::samples 522030 # Request fanout histogram 323system.membus.snoop_fanout::mean 1 # Request fanout histogram 324system.membus.snoop_fanout::stdev 0 # Request fanout histogram 325system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 326system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 327system.membus.snoop_fanout::1 522030 100.00% 100.00% # Request fanout histogram 328system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 329system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 330system.membus.snoop_fanout::min_value 1 # Request fanout histogram 331system.membus.snoop_fanout::max_value 1 # Request fanout histogram 332system.membus.snoop_fanout::total 522030 # Request fanout histogram 333system.membus.reqLayer0.occupancy 31457000 # Layer occupancy (ticks) |
| 320system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 334system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 321system.membus.reqLayer1.occupancy 1484965250 # Layer occupancy (ticks) | 335system.membus.reqLayer1.occupancy 1484421249 # Layer occupancy (ticks) |
| 322system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 336system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 323system.membus.reqLayer2.occupancy 112000 # Layer occupancy (ticks) | 337system.membus.reqLayer2.occupancy 110500 # Layer occupancy (ticks) |
| 324system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 338system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 325system.membus.respLayer1.occupancy 3755505039 # Layer occupancy (ticks) | 339system.membus.respLayer1.occupancy 3754388311 # Layer occupancy (ticks) |
| 326system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 327system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) 328system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 329system.iocache.tags.replacements 41685 # number of replacements | 340system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 341system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) 342system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 343system.iocache.tags.replacements 41685 # number of replacements |
| 330system.iocache.tags.tagsinuse 1.268186 # Cycle average of tags in use | 344system.iocache.tags.tagsinuse 1.260487 # Cycle average of tags in use |
| 331system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 332system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 333system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 345system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 346system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 347system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 334system.iocache.tags.warmup_cycle 1709354954000 # Cycle when the warmup percentage was hit. 335system.iocache.tags.occ_blocks::tsunami.ide 1.268186 # Average occupied blocks per requestor 336system.iocache.tags.occ_percent::tsunami.ide 0.079262 # Average percentage of cache occupancy 337system.iocache.tags.occ_percent::total 0.079262 # Average percentage of cache occupancy | 348system.iocache.tags.warmup_cycle 1709355301000 # Cycle when the warmup percentage was hit. 349system.iocache.tags.occ_blocks::tsunami.ide 1.260487 # Average occupied blocks per requestor 350system.iocache.tags.occ_percent::tsunami.ide 0.078780 # Average percentage of cache occupancy 351system.iocache.tags.occ_percent::total 0.078780 # Average percentage of cache occupancy |
| 338system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 339system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 340system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 352system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 353system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 354system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 341system.iocache.tags.tag_accesses 376037 # Number of tag accesses 342system.iocache.tags.data_accesses 376037 # Number of data accesses | 355system.iocache.tags.tag_accesses 376213 # Number of tag accesses 356system.iocache.tags.data_accesses 376213 # Number of data accesses |
| 343system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 344system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 345system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 346system.iocache.ReadReq_misses::total 173 # number of ReadReq misses | 357system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 358system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 359system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 360system.iocache.ReadReq_misses::total 173 # number of ReadReq misses |
| 347system.iocache.WriteInvalidateReq_misses::tsunami.ide 64 # number of WriteInvalidateReq misses 348system.iocache.WriteInvalidateReq_misses::total 64 # number of WriteInvalidateReq misses | 361system.iocache.WriteInvalidateReq_misses::tsunami.ide 86 # number of WriteInvalidateReq misses 362system.iocache.WriteInvalidateReq_misses::total 86 # number of WriteInvalidateReq misses |
| 349system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 350system.iocache.demand_misses::total 173 # number of demand (read+write) misses 351system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 352system.iocache.overall_misses::total 173 # number of overall misses 353system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 354system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 355system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 356system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 357system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 358system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 359system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 360system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) | 363system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 364system.iocache.demand_misses::total 173 # number of demand (read+write) misses 365system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 366system.iocache.overall_misses::total 173 # number of overall misses 367system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 368system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 369system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 370system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 371system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 372system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 373system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 374system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) |
| 361system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41616 # number of WriteInvalidateReq accesses(hits+misses) 362system.iocache.WriteInvalidateReq_accesses::total 41616 # number of WriteInvalidateReq accesses(hits+misses) | 375system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41638 # number of WriteInvalidateReq accesses(hits+misses) 376system.iocache.WriteInvalidateReq_accesses::total 41638 # number of WriteInvalidateReq accesses(hits+misses) |
| 363system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 364system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 365system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 366system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 367system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 368system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 377system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 378system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 379system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 380system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 381system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 382system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 369system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.001538 # miss rate for WriteInvalidateReq accesses 370system.iocache.WriteInvalidateReq_miss_rate::total 0.001538 # miss rate for WriteInvalidateReq accesses | 383system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.002065 # miss rate for WriteInvalidateReq accesses 384system.iocache.WriteInvalidateReq_miss_rate::total 0.002065 # miss rate for WriteInvalidateReq accesses |
| 371system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 372system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 373system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 374system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 375system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 376system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 377system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 378system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency --- 12 unchanged lines hidden (view full) --- 391system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 392system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 393system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 394system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 395system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 396system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 397system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 398system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles | 385system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 386system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 387system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 388system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 389system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 390system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 391system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 392system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency --- 12 unchanged lines hidden (view full) --- 405system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 406system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 407system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 408system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 409system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 410system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 411system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 412system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles |
| 399system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2528134047 # number of WriteInvalidateReq MSHR miss cycles 400system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2528134047 # number of WriteInvalidateReq MSHR miss cycles | 413system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles 414system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles |
| 401system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 402system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 403system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 404system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 405system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 406system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 415system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 416system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 417system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 418system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 419system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 420system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 407system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.998462 # mshr miss rate for WriteInvalidateReq accesses 408system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.998462 # mshr miss rate for WriteInvalidateReq accesses | 421system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses 422system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses |
| 409system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 410system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 411system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 412system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 413system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 414system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency | 423system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 424system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 425system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 426system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 427system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 428system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency |
| 415system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60842.656118 # average WriteInvalidateReq mshr miss latency 416system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60842.656118 # average WriteInvalidateReq mshr miss latency | 429system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency 430system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency |
| 417system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 418system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 419system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 420system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 421system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 422system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 423system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 424system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 425system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 426system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 427system.disk0.dma_write_txs 395 # Number of DMA write transactions. 428system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 429system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 430system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 431system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 432system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 433system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 431system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 432system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 433system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 434system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 435system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 436system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 437system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 438system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 439system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 440system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 441system.disk0.dma_write_txs 395 # Number of DMA write transactions. 442system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 444system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 445system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 446system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 447system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 434system.cpu.branchPred.lookups 17833670 # Number of BP lookups 435system.cpu.branchPred.condPredicted 15506350 # Number of conditional branches predicted 436system.cpu.branchPred.condIncorrect 381114 # Number of conditional branches incorrect 437system.cpu.branchPred.BTBLookups 12104225 # Number of BTB lookups 438system.cpu.branchPred.BTBHits 5926115 # Number of BTB hits | 448system.cpu.branchPred.lookups 17804968 # Number of BP lookups 449system.cpu.branchPred.condPredicted 15499600 # Number of conditional branches predicted 450system.cpu.branchPred.condIncorrect 379466 # Number of conditional branches incorrect 451system.cpu.branchPred.BTBLookups 11923628 # Number of BTB lookups 452system.cpu.branchPred.BTBHits 5932721 # Number of BTB hits |
| 439system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 453system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 440system.cpu.branchPred.BTBHitPct 48.959062 # BTB Hit Percentage 441system.cpu.branchPred.usedRAS 921355 # Number of times the RAS was used to get a target. 442system.cpu.branchPred.RASInCorrect 21398 # Number of incorrect RAS predictions. | 454system.cpu.branchPred.BTBHitPct 49.756005 # BTB Hit Percentage 455system.cpu.branchPred.usedRAS 914118 # Number of times the RAS was used to get a target. 456system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions. |
| 443system.cpu_clk_domain.clock 500 # Clock period in ticks 444system.cpu.dtb.fetch_hits 0 # ITB hits 445system.cpu.dtb.fetch_misses 0 # ITB misses 446system.cpu.dtb.fetch_acv 0 # ITB acv 447system.cpu.dtb.fetch_accesses 0 # ITB accesses | 457system.cpu_clk_domain.clock 500 # Clock period in ticks 458system.cpu.dtb.fetch_hits 0 # ITB hits 459system.cpu.dtb.fetch_misses 0 # ITB misses 460system.cpu.dtb.fetch_acv 0 # ITB acv 461system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 448system.cpu.dtb.read_hits 10317598 # DTB read hits 449system.cpu.dtb.read_misses 42841 # DTB read misses 450system.cpu.dtb.read_acv 498 # DTB read access violations 451system.cpu.dtb.read_accesses 968680 # DTB read accesses 452system.cpu.dtb.write_hits 6661505 # DTB write hits 453system.cpu.dtb.write_misses 9470 # DTB write misses 454system.cpu.dtb.write_acv 409 # DTB write access violations 455system.cpu.dtb.write_accesses 342844 # DTB write accesses 456system.cpu.dtb.data_hits 16979103 # DTB hits 457system.cpu.dtb.data_misses 52311 # DTB misses 458system.cpu.dtb.data_acv 907 # DTB access violations 459system.cpu.dtb.data_accesses 1311524 # DTB accesses 460system.cpu.itb.fetch_hits 1772041 # ITB hits 461system.cpu.itb.fetch_misses 34420 # ITB misses 462system.cpu.itb.fetch_acv 658 # ITB acv 463system.cpu.itb.fetch_accesses 1806461 # ITB accesses | 462system.cpu.dtb.read_hits 10302215 # DTB read hits 463system.cpu.dtb.read_misses 41309 # DTB read misses 464system.cpu.dtb.read_acv 513 # DTB read access violations 465system.cpu.dtb.read_accesses 965594 # DTB read accesses 466system.cpu.dtb.write_hits 6646492 # DTB write hits 467system.cpu.dtb.write_misses 9371 # DTB write misses 468system.cpu.dtb.write_acv 419 # DTB write access violations 469system.cpu.dtb.write_accesses 342338 # DTB write accesses 470system.cpu.dtb.data_hits 16948707 # DTB hits 471system.cpu.dtb.data_misses 50680 # DTB misses 472system.cpu.dtb.data_acv 932 # DTB access violations 473system.cpu.dtb.data_accesses 1307932 # DTB accesses 474system.cpu.itb.fetch_hits 1774610 # ITB hits 475system.cpu.itb.fetch_misses 34401 # ITB misses 476system.cpu.itb.fetch_acv 653 # ITB acv 477system.cpu.itb.fetch_accesses 1809011 # ITB accesses |
| 464system.cpu.itb.read_hits 0 # DTB read hits 465system.cpu.itb.read_misses 0 # DTB read misses 466system.cpu.itb.read_acv 0 # DTB read access violations 467system.cpu.itb.read_accesses 0 # DTB read accesses 468system.cpu.itb.write_hits 0 # DTB write hits 469system.cpu.itb.write_misses 0 # DTB write misses 470system.cpu.itb.write_acv 0 # DTB write access violations 471system.cpu.itb.write_accesses 0 # DTB write accesses 472system.cpu.itb.data_hits 0 # DTB hits 473system.cpu.itb.data_misses 0 # DTB misses 474system.cpu.itb.data_acv 0 # DTB access violations 475system.cpu.itb.data_accesses 0 # DTB accesses | 478system.cpu.itb.read_hits 0 # DTB read hits 479system.cpu.itb.read_misses 0 # DTB read misses 480system.cpu.itb.read_acv 0 # DTB read access violations 481system.cpu.itb.read_accesses 0 # DTB read accesses 482system.cpu.itb.write_hits 0 # DTB write hits 483system.cpu.itb.write_misses 0 # DTB write misses 484system.cpu.itb.write_acv 0 # DTB write access violations 485system.cpu.itb.write_accesses 0 # DTB write accesses 486system.cpu.itb.data_hits 0 # DTB hits 487system.cpu.itb.data_misses 0 # DTB misses 488system.cpu.itb.data_acv 0 # DTB access violations 489system.cpu.itb.data_accesses 0 # DTB accesses |
| 476system.cpu.numCycles 118354133 # number of cpu cycles simulated | 490system.cpu.numCycles 118301061 # number of cpu cycles simulated |
| 477system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 478system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 491system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 492system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 479system.cpu.fetch.icacheStallCycles 29610053 # Number of cycles fetch is stalled on an Icache miss 480system.cpu.fetch.Insts 78304025 # Number of instructions fetch has processed 481system.cpu.fetch.Branches 17833670 # Number of branches that fetch encountered 482system.cpu.fetch.predictedBranches 6847470 # Number of branches that fetch has predicted taken 483system.cpu.fetch.Cycles 80574615 # Number of cycles fetch has run and was not squashing or blocked 484system.cpu.fetch.SquashCycles 1256858 # Number of cycles fetch has spent squashing 485system.cpu.fetch.TlbCycles 1099 # Number of cycles fetch has spent waiting for tlb 486system.cpu.fetch.MiscStallCycles 26263 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 487system.cpu.fetch.PendingTrapStallCycles 1650622 # Number of stall cycles due to pending traps 488system.cpu.fetch.PendingQuiesceStallCycles 440507 # Number of stall cycles due to pending quiesce instructions 489system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR 490system.cpu.fetch.CacheLines 9057340 # Number of cache lines fetched 491system.cpu.fetch.IcacheSquashes 272482 # Number of outstanding Icache misses that were squashed 492system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 493system.cpu.fetch.rateDist::samples 112931823 # Number of instructions fetched each cycle (Total) 494system.cpu.fetch.rateDist::mean 0.693374 # Number of instructions fetched each cycle (Total) 495system.cpu.fetch.rateDist::stdev 2.013486 # Number of instructions fetched each cycle (Total) | 493system.cpu.fetch.icacheStallCycles 29562966 # Number of cycles fetch is stalled on an Icache miss 494system.cpu.fetch.Insts 78094807 # Number of instructions fetch has processed 495system.cpu.fetch.Branches 17804968 # Number of branches that fetch encountered 496system.cpu.fetch.predictedBranches 6846839 # Number of branches that fetch has predicted taken 497system.cpu.fetch.Cycles 80553195 # Number of cycles fetch has run and was not squashing or blocked 498system.cpu.fetch.SquashCycles 1252096 # Number of cycles fetch has spent squashing 499system.cpu.fetch.TlbCycles 1416 # Number of cycles fetch has spent waiting for tlb 500system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 501system.cpu.fetch.PendingTrapStallCycles 1649882 # Number of stall cycles due to pending traps 502system.cpu.fetch.PendingQuiesceStallCycles 450417 # Number of stall cycles due to pending quiesce instructions 503system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR 504system.cpu.fetch.CacheLines 9025532 # Number of cache lines fetched 505system.cpu.fetch.IcacheSquashes 274121 # Number of outstanding Icache misses that were squashed 506system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed 507system.cpu.fetch.rateDist::samples 112872082 # Number of instructions fetched each cycle (Total) 508system.cpu.fetch.rateDist::mean 0.691888 # Number of instructions fetched each cycle (Total) 509system.cpu.fetch.rateDist::stdev 2.011514 # Number of instructions fetched each cycle (Total) |
| 496system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 510system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 497system.cpu.fetch.rateDist::0 98319716 87.06% 87.06% # Number of instructions fetched each cycle (Total) 498system.cpu.fetch.rateDist::1 938849 0.83% 87.89% # Number of instructions fetched each cycle (Total) 499system.cpu.fetch.rateDist::2 1975725 1.75% 89.64% # Number of instructions fetched each cycle (Total) 500system.cpu.fetch.rateDist::3 910849 0.81% 90.45% # Number of instructions fetched each cycle (Total) 501system.cpu.fetch.rateDist::4 2798510 2.48% 92.93% # Number of instructions fetched each cycle (Total) 502system.cpu.fetch.rateDist::5 647409 0.57% 93.50% # Number of instructions fetched each cycle (Total) 503system.cpu.fetch.rateDist::6 732146 0.65% 94.15% # Number of instructions fetched each cycle (Total) 504system.cpu.fetch.rateDist::7 1011734 0.90% 95.04% # Number of instructions fetched each cycle (Total) 505system.cpu.fetch.rateDist::8 5596885 4.96% 100.00% # Number of instructions fetched each cycle (Total) | 511system.cpu.fetch.rateDist::0 98296528 87.09% 87.09% # Number of instructions fetched each cycle (Total) 512system.cpu.fetch.rateDist::1 933530 0.83% 87.91% # Number of instructions fetched each cycle (Total) 513system.cpu.fetch.rateDist::2 1975700 1.75% 89.66% # Number of instructions fetched each cycle (Total) 514system.cpu.fetch.rateDist::3 908755 0.81% 90.47% # Number of instructions fetched each cycle (Total) 515system.cpu.fetch.rateDist::4 2800334 2.48% 92.95% # Number of instructions fetched each cycle (Total) 516system.cpu.fetch.rateDist::5 638924 0.57% 93.52% # Number of instructions fetched each cycle (Total) 517system.cpu.fetch.rateDist::6 725896 0.64% 94.16% # Number of instructions fetched each cycle (Total) 518system.cpu.fetch.rateDist::7 1007040 0.89% 95.05% # Number of instructions fetched each cycle (Total) 519system.cpu.fetch.rateDist::8 5585375 4.95% 100.00% # Number of instructions fetched each cycle (Total) |
| 506system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 507system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 508system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 520system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 521system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 522system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 509system.cpu.fetch.rateDist::total 112931823 # Number of instructions fetched each cycle (Total) 510system.cpu.fetch.branchRate 0.150681 # Number of branch fetches per cycle 511system.cpu.fetch.rate 0.661608 # Number of inst fetches per cycle 512system.cpu.decode.IdleCycles 24101711 # Number of cycles decode is idle 513system.cpu.decode.BlockedCycles 76820135 # Number of cycles decode is blocked 514system.cpu.decode.RunCycles 9519710 # Number of cycles decode is running 515system.cpu.decode.UnblockCycles 1904377 # Number of cycles decode is unblocking 516system.cpu.decode.SquashCycles 585889 # Number of cycles decode is squashing 517system.cpu.decode.BranchResolved 591731 # Number of times decode resolved a branch 518system.cpu.decode.BranchMispred 42945 # Number of times decode detected a branch misprediction 519system.cpu.decode.DecodedInsts 68430953 # Number of instructions handled by decode 520system.cpu.decode.SquashedInsts 130896 # Number of squashed instructions handled by decode 521system.cpu.rename.SquashCycles 585889 # Number of cycles rename is squashing 522system.cpu.rename.IdleCycles 25024532 # Number of cycles rename is idle 523system.cpu.rename.BlockCycles 47243324 # Number of cycles rename is blocking 524system.cpu.rename.serializeStallCycles 20763433 # count of cycles rename stalled for serializing inst 525system.cpu.rename.RunCycles 10413926 # Number of cycles rename is running 526system.cpu.rename.UnblockCycles 8900717 # Number of cycles rename is unblocking 527system.cpu.rename.RenamedInsts 65988448 # Number of instructions processed by rename 528system.cpu.rename.ROBFullEvents 204336 # Number of times rename has blocked due to ROB full 529system.cpu.rename.IQFullEvents 2037147 # Number of times rename has blocked due to IQ full 530system.cpu.rename.LQFullEvents 141186 # Number of times rename has blocked due to LQ full 531system.cpu.rename.SQFullEvents 4759131 # Number of times rename has blocked due to SQ full 532system.cpu.rename.RenamedOperands 44017538 # Number of destination operands rename has renamed 533system.cpu.rename.RenameLookups 79991288 # Number of register rename lookups that rename has made 534system.cpu.rename.int_rename_lookups 79809724 # Number of integer rename lookups 535system.cpu.rename.fp_rename_lookups 169111 # Number of floating rename lookups 536system.cpu.rename.CommittedMaps 38182266 # Number of HB maps that are committed 537system.cpu.rename.UndoneMaps 5835264 # Number of HB maps that are undone due to squashing 538system.cpu.rename.serializingInsts 1692739 # count of serializing insts renamed 539system.cpu.rename.tempSerializingInsts 242112 # count of temporary serializing insts renamed 540system.cpu.rename.skidInsts 13540611 # count of insts added to the skid buffer 541system.cpu.memDep0.insertedLoads 10451547 # Number of loads inserted to the mem dependence unit. 542system.cpu.memDep0.insertedStores 6960595 # Number of stores inserted to the mem dependence unit. 543system.cpu.memDep0.conflictingLoads 1482211 # Number of conflicting loads. 544system.cpu.memDep0.conflictingStores 1061862 # Number of conflicting stores. 545system.cpu.iq.iqInstsAdded 58727790 # Number of instructions added to the IQ (excludes non-spec) 546system.cpu.iq.iqNonSpecInstsAdded 2141622 # Number of non-speculative instructions added to the IQ 547system.cpu.iq.iqInstsIssued 57666213 # Number of instructions issued 548system.cpu.iq.iqSquashedInstsIssued 56106 # Number of squashed instructions issued 549system.cpu.iq.iqSquashedInstsExamined 7541795 # Number of squashed instructions iterated over during squash; mainly for profiling 550system.cpu.iq.iqSquashedOperandsExamined 3548748 # Number of squashed operands that are examined and possibly removed from graph 551system.cpu.iq.iqSquashedNonSpecRemoved 1480432 # Number of squashed non-spec instructions that were removed 552system.cpu.iq.issued_per_cycle::samples 112931823 # Number of insts issued each cycle 553system.cpu.iq.issued_per_cycle::mean 0.510629 # Number of insts issued each cycle 554system.cpu.iq.issued_per_cycle::stdev 1.253101 # Number of insts issued each cycle | 523system.cpu.fetch.rateDist::total 112872082 # Number of instructions fetched each cycle (Total) 524system.cpu.fetch.branchRate 0.150506 # Number of branch fetches per cycle 525system.cpu.fetch.rate 0.660136 # Number of inst fetches per cycle 526system.cpu.decode.IdleCycles 24068860 # Number of cycles decode is idle 527system.cpu.decode.BlockedCycles 76820836 # Number of cycles decode is blocked 528system.cpu.decode.RunCycles 9500551 # Number of cycles decode is running 529system.cpu.decode.UnblockCycles 1898196 # Number of cycles decode is unblocking 530system.cpu.decode.SquashCycles 583638 # Number of cycles decode is squashing 531system.cpu.decode.BranchResolved 588301 # Number of times decode resolved a branch 532system.cpu.decode.BranchMispred 42850 # Number of times decode detected a branch misprediction 533system.cpu.decode.DecodedInsts 68299285 # Number of instructions handled by decode 534system.cpu.decode.SquashedInsts 133126 # Number of squashed instructions handled by decode 535system.cpu.rename.SquashCycles 583638 # Number of cycles rename is squashing 536system.cpu.rename.IdleCycles 24994916 # Number of cycles rename is idle 537system.cpu.rename.BlockCycles 47249741 # Number of cycles rename is blocking 538system.cpu.rename.serializeStallCycles 20742683 # count of cycles rename stalled for serializing inst 539system.cpu.rename.RunCycles 10385328 # Number of cycles rename is running 540system.cpu.rename.UnblockCycles 8915774 # Number of cycles rename is unblocking 541system.cpu.rename.RenamedInsts 65865702 # Number of instructions processed by rename 542system.cpu.rename.ROBFullEvents 202022 # Number of times rename has blocked due to ROB full 543system.cpu.rename.IQFullEvents 2036806 # Number of times rename has blocked due to IQ full 544system.cpu.rename.LQFullEvents 141544 # Number of times rename has blocked due to LQ full 545system.cpu.rename.SQFullEvents 4770005 # Number of times rename has blocked due to SQ full 546system.cpu.rename.RenamedOperands 43944287 # Number of destination operands rename has renamed 547system.cpu.rename.RenameLookups 79812474 # Number of register rename lookups that rename has made 548system.cpu.rename.int_rename_lookups 79631676 # Number of integer rename lookups 549system.cpu.rename.fp_rename_lookups 168345 # Number of floating rename lookups 550system.cpu.rename.CommittedMaps 38137411 # Number of HB maps that are committed 551system.cpu.rename.UndoneMaps 5806868 # Number of HB maps that are undone due to squashing 552system.cpu.rename.serializingInsts 1690855 # count of serializing insts renamed 553system.cpu.rename.tempSerializingInsts 241233 # count of temporary serializing insts renamed 554system.cpu.rename.skidInsts 13548292 # count of insts added to the skid buffer 555system.cpu.memDep0.insertedLoads 10425085 # Number of loads inserted to the mem dependence unit. 556system.cpu.memDep0.insertedStores 6927485 # Number of stores inserted to the mem dependence unit. 557system.cpu.memDep0.conflictingLoads 1490397 # Number of conflicting loads. 558system.cpu.memDep0.conflictingStores 1054253 # Number of conflicting stores. 559system.cpu.iq.iqInstsAdded 58626057 # Number of instructions added to the IQ (excludes non-spec) 560system.cpu.iq.iqNonSpecInstsAdded 2139161 # Number of non-speculative instructions added to the IQ 561system.cpu.iq.iqInstsIssued 57592696 # Number of instructions issued 562system.cpu.iq.iqSquashedInstsIssued 51229 # Number of squashed instructions issued 563system.cpu.iq.iqSquashedInstsExamined 7502337 # Number of squashed instructions iterated over during squash; mainly for profiling 564system.cpu.iq.iqSquashedOperandsExamined 3486338 # Number of squashed operands that are examined and possibly removed from graph 565system.cpu.iq.iqSquashedNonSpecRemoved 1478017 # Number of squashed non-spec instructions that were removed 566system.cpu.iq.issued_per_cycle::samples 112872082 # Number of insts issued each cycle 567system.cpu.iq.issued_per_cycle::mean 0.510247 # Number of insts issued each cycle 568system.cpu.iq.issued_per_cycle::stdev 1.252928 # Number of insts issued each cycle |
| 555system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 569system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 556system.cpu.iq.issued_per_cycle::0 89418441 79.18% 79.18% # Number of insts issued each cycle 557system.cpu.iq.issued_per_cycle::1 10028401 8.88% 88.06% # Number of insts issued each cycle 558system.cpu.iq.issued_per_cycle::2 4312192 3.82% 91.88% # Number of insts issued each cycle 559system.cpu.iq.issued_per_cycle::3 2973812 2.63% 94.51% # Number of insts issued each cycle 560system.cpu.iq.issued_per_cycle::4 3078524 2.73% 97.24% # Number of insts issued each cycle 561system.cpu.iq.issued_per_cycle::5 1589541 1.41% 98.64% # Number of insts issued each cycle 562system.cpu.iq.issued_per_cycle::6 1010242 0.89% 99.54% # Number of insts issued each cycle 563system.cpu.iq.issued_per_cycle::7 396621 0.35% 99.89% # Number of insts issued each cycle 564system.cpu.iq.issued_per_cycle::8 124049 0.11% 100.00% # Number of insts issued each cycle | 570system.cpu.iq.issued_per_cycle::0 89394835 79.20% 79.20% # Number of insts issued each cycle 571system.cpu.iq.issued_per_cycle::1 10016384 8.87% 88.07% # Number of insts issued each cycle 572system.cpu.iq.issued_per_cycle::2 4304507 3.81% 91.89% # Number of insts issued each cycle 573system.cpu.iq.issued_per_cycle::3 2950730 2.61% 94.50% # Number of insts issued each cycle 574system.cpu.iq.issued_per_cycle::4 3082787 2.73% 97.23% # Number of insts issued each cycle 575system.cpu.iq.issued_per_cycle::5 1592384 1.41% 98.64% # Number of insts issued each cycle 576system.cpu.iq.issued_per_cycle::6 1013037 0.90% 99.54% # Number of insts issued each cycle 577system.cpu.iq.issued_per_cycle::7 395526 0.35% 99.89% # Number of insts issued each cycle 578system.cpu.iq.issued_per_cycle::8 121892 0.11% 100.00% # Number of insts issued each cycle |
| 565system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 566system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 567system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 579system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 580system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 581system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 568system.cpu.iq.issued_per_cycle::total 112931823 # Number of insts issued each cycle | 582system.cpu.iq.issued_per_cycle::total 112872082 # Number of insts issued each cycle |
| 569system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 583system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 570system.cpu.iq.fu_full::IntAlu 207021 18.24% 18.24% # attempts to use FU when none available 571system.cpu.iq.fu_full::IntMult 0 0.00% 18.24% # attempts to use FU when none available 572system.cpu.iq.fu_full::IntDiv 0 0.00% 18.24% # attempts to use FU when none available 573system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.24% # attempts to use FU when none available 574system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.24% # attempts to use FU when none available 575system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.24% # attempts to use FU when none available 576system.cpu.iq.fu_full::FloatMult 0 0.00% 18.24% # attempts to use FU when none available 577system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.24% # attempts to use FU when none available 578system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.24% # attempts to use FU when none available 579system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.24% # attempts to use FU when none available 580system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.24% # attempts to use FU when none available 581system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.24% # attempts to use FU when none available 582system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.24% # attempts to use FU when none available 583system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.24% # attempts to use FU when none available 584system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.24% # attempts to use FU when none available 585system.cpu.iq.fu_full::SimdMult 0 0.00% 18.24% # attempts to use FU when none available 586system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.24% # attempts to use FU when none available 587system.cpu.iq.fu_full::SimdShift 0 0.00% 18.24% # attempts to use FU when none available 588system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.24% # attempts to use FU when none available 589system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.24% # attempts to use FU when none available 590system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.24% # attempts to use FU when none available 591system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.24% # attempts to use FU when none available 592system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.24% # attempts to use FU when none available 593system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.24% # attempts to use FU when none available 594system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.24% # attempts to use FU when none available 595system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.24% # attempts to use FU when none available 596system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.24% # attempts to use FU when none available 597system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.24% # attempts to use FU when none available 598system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.24% # attempts to use FU when none available 599system.cpu.iq.fu_full::MemRead 552834 48.70% 66.94% # attempts to use FU when none available 600system.cpu.iq.fu_full::MemWrite 375297 33.06% 100.00% # attempts to use FU when none available | 584system.cpu.iq.fu_full::IntAlu 212963 18.82% 18.82% # attempts to use FU when none available 585system.cpu.iq.fu_full::IntMult 0 0.00% 18.82% # attempts to use FU when none available 586system.cpu.iq.fu_full::IntDiv 0 0.00% 18.82% # attempts to use FU when none available 587system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.82% # attempts to use FU when none available 588system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.82% # attempts to use FU when none available 589system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.82% # attempts to use FU when none available 590system.cpu.iq.fu_full::FloatMult 0 0.00% 18.82% # attempts to use FU when none available 591system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.82% # attempts to use FU when none available 592system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.82% # attempts to use FU when none available 593system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.82% # attempts to use FU when none available 594system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.82% # attempts to use FU when none available 595system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.82% # attempts to use FU when none available 596system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.82% # attempts to use FU when none available 597system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.82% # attempts to use FU when none available 598system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.82% # attempts to use FU when none available 599system.cpu.iq.fu_full::SimdMult 0 0.00% 18.82% # attempts to use FU when none available 600system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.82% # attempts to use FU when none available 601system.cpu.iq.fu_full::SimdShift 0 0.00% 18.82% # attempts to use FU when none available 602system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.82% # attempts to use FU when none available 603system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.82% # attempts to use FU when none available 604system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.82% # attempts to use FU when none available 605system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.82% # attempts to use FU when none available 606system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.82% # attempts to use FU when none available 607system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.82% # attempts to use FU when none available 608system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.82% # attempts to use FU when none available 609system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.82% # attempts to use FU when none available 610system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.82% # attempts to use FU when none available 611system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.82% # attempts to use FU when none available 612system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.82% # attempts to use FU when none available 613system.cpu.iq.fu_full::MemRead 545078 48.16% 66.97% # attempts to use FU when none available 614system.cpu.iq.fu_full::MemWrite 373836 33.03% 100.00% # attempts to use FU when none available |
| 601system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 602system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 603system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued | 615system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 616system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 617system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued |
| 604system.cpu.iq.FU_type_0::IntAlu 39135351 67.87% 67.88% # Type of FU issued 605system.cpu.iq.FU_type_0::IntMult 61883 0.11% 67.99% # Type of FU issued 606system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued 607system.cpu.iq.FU_type_0::FloatAdd 38374 0.07% 68.05% # Type of FU issued 608system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued 609system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued 610system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued 611system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued 612system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued 613system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued 614system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued 615system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued 616system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued 617system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued 618system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued 619system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued 620system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued 621system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued 622system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued 623system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued 624system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued 625system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued 626system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued 627system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued 628system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued 629system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued 630system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued 631system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued 632system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued 633system.cpu.iq.FU_type_0::MemRead 10730394 18.61% 86.67% # Type of FU issued 634system.cpu.iq.FU_type_0::MemWrite 6740242 11.69% 98.35% # Type of FU issued 635system.cpu.iq.FU_type_0::IprAccess 949047 1.65% 100.00% # Type of FU issued | 618system.cpu.iq.FU_type_0::IntAlu 39097776 67.89% 67.90% # Type of FU issued 619system.cpu.iq.FU_type_0::IntMult 61804 0.11% 68.01% # Type of FU issued 620system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued 621system.cpu.iq.FU_type_0::FloatAdd 38376 0.07% 68.07% # Type of FU issued 622system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued 623system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued 624system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued 625system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.08% # Type of FU issued 626system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued 627system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued 628system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued 629system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued 630system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued 631system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued 632system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued 633system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued 634system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued 635system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued 636system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued 637system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued 638system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued 639system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued 640system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued 641system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued 642system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued 643system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued 644system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.08% # Type of FU issued 645system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued 646system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued 647system.cpu.iq.FU_type_0::MemRead 10712581 18.60% 86.68% # Type of FU issued 648system.cpu.iq.FU_type_0::MemWrite 6722276 11.67% 98.35% # Type of FU issued 649system.cpu.iq.FU_type_0::IprAccess 948961 1.65% 100.00% # Type of FU issued |
| 636system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 650system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 637system.cpu.iq.FU_type_0::total 57666213 # Type of FU issued 638system.cpu.iq.rate 0.487234 # Inst issue rate 639system.cpu.iq.fu_busy_cnt 1135152 # FU busy when requested 640system.cpu.iq.fu_busy_rate 0.019685 # FU busy rate (busy events/executed inst) 641system.cpu.iq.int_inst_queue_reads 228740415 # Number of integer instruction queue reads 642system.cpu.iq.int_inst_queue_writes 68094123 # Number of integer instruction queue writes 643system.cpu.iq.int_inst_queue_wakeup_accesses 55977641 # Number of integer instruction queue wakeup accesses 644system.cpu.iq.fp_inst_queue_reads 715091 # Number of floating instruction queue reads 645system.cpu.iq.fp_inst_queue_writes 336647 # Number of floating instruction queue writes 646system.cpu.iq.fp_inst_queue_wakeup_accesses 329707 # Number of floating instruction queue wakeup accesses 647system.cpu.iq.int_alu_accesses 58410087 # Number of integer alu accesses 648system.cpu.iq.fp_alu_accesses 383992 # Number of floating point alu accesses 649system.cpu.iew.lsq.thread0.forwLoads 639401 # Number of loads that had data forwarded from stores | 651system.cpu.iq.FU_type_0::total 57592696 # Type of FU issued 652system.cpu.iq.rate 0.486832 # Inst issue rate 653system.cpu.iq.fu_busy_cnt 1131877 # FU busy when requested 654system.cpu.iq.fu_busy_rate 0.019653 # FU busy rate (busy events/executed inst) 655system.cpu.iq.int_inst_queue_reads 228528169 # Number of integer instruction queue reads 656system.cpu.iq.int_inst_queue_writes 67952558 # Number of integer instruction queue writes 657system.cpu.iq.int_inst_queue_wakeup_accesses 55916727 # Number of integer instruction queue wakeup accesses 658system.cpu.iq.fp_inst_queue_reads 712410 # Number of floating instruction queue reads 659system.cpu.iq.fp_inst_queue_writes 334609 # Number of floating instruction queue writes 660system.cpu.iq.fp_inst_queue_wakeup_accesses 328997 # Number of floating instruction queue wakeup accesses 661system.cpu.iq.int_alu_accesses 58334880 # Number of integer alu accesses 662system.cpu.iq.fp_alu_accesses 382407 # Number of floating point alu accesses 663system.cpu.iew.lsq.thread0.forwLoads 639606 # Number of loads that had data forwarded from stores |
| 650system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 664system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 651system.cpu.iew.lsq.thread0.squashedLoads 1358213 # Number of loads squashed 652system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed 653system.cpu.iew.lsq.thread0.memOrderViolation 20004 # Number of memory ordering violations 654system.cpu.iew.lsq.thread0.squashedStores 581979 # Number of stores squashed | 665system.cpu.iew.lsq.thread0.squashedLoads 1340629 # Number of loads squashed 666system.cpu.iew.lsq.thread0.ignoredResponses 4088 # Number of memory responses ignored because the instruction is squashed 667system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations 668system.cpu.iew.lsq.thread0.squashedStores 553798 # Number of stores squashed |
| 655system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 656system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 669system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 670system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 657system.cpu.iew.lsq.thread0.rescheduledLoads 18257 # Number of loads that were rescheduled 658system.cpu.iew.lsq.thread0.cacheBlocked 542602 # Number of times an access to memory failed due to the cache being blocked | 671system.cpu.iew.lsq.thread0.rescheduledLoads 18287 # Number of loads that were rescheduled 672system.cpu.iew.lsq.thread0.cacheBlocked 539247 # Number of times an access to memory failed due to the cache being blocked |
| 659system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 673system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 660system.cpu.iew.iewSquashCycles 585889 # Number of cycles IEW is squashing 661system.cpu.iew.iewBlockCycles 44309531 # Number of cycles IEW is blocking 662system.cpu.iew.iewUnblockCycles 608680 # Number of cycles IEW is unblocking 663system.cpu.iew.iewDispatchedInsts 64580146 # Number of instructions dispatched to IQ 664system.cpu.iew.iewDispSquashedInsts 145680 # Number of squashed instructions skipped by dispatch 665system.cpu.iew.iewDispLoadInsts 10451547 # Number of dispatched load instructions 666system.cpu.iew.iewDispStoreInsts 6960595 # Number of dispatched store instructions 667system.cpu.iew.iewDispNonSpecInsts 1891521 # Number of dispatched non-speculative instructions 668system.cpu.iew.iewIQFullEvents 42330 # Number of times the IQ has become full, causing a stall 669system.cpu.iew.iewLSQFullEvents 362520 # Number of times the LSQ has become full, causing a stall 670system.cpu.iew.memOrderViolationEvents 20004 # Number of memory order violations 671system.cpu.iew.predictedTakenIncorrect 191994 # Number of branches that were predicted taken incorrectly 672system.cpu.iew.predictedNotTakenIncorrect 411566 # Number of branches that were predicted not taken incorrectly 673system.cpu.iew.branchMispredicts 603560 # Number of branch mispredicts detected at execute 674system.cpu.iew.iewExecutedInsts 57078103 # Number of executed instructions 675system.cpu.iew.iewExecLoadInsts 10388088 # Number of load instructions executed 676system.cpu.iew.iewExecSquashedInsts 588109 # Number of squashed instructions skipped in execute | 674system.cpu.iew.iewSquashCycles 583638 # Number of cycles IEW is squashing 675system.cpu.iew.iewBlockCycles 44307486 # Number of cycles IEW is blocking 676system.cpu.iew.iewUnblockCycles 616008 # Number of cycles IEW is unblocking 677system.cpu.iew.iewDispatchedInsts 64468948 # Number of instructions dispatched to IQ 678system.cpu.iew.iewDispSquashedInsts 145079 # Number of squashed instructions skipped by dispatch 679system.cpu.iew.iewDispLoadInsts 10425085 # Number of dispatched load instructions 680system.cpu.iew.iewDispStoreInsts 6927485 # Number of dispatched store instructions 681system.cpu.iew.iewDispNonSpecInsts 1890835 # Number of dispatched non-speculative instructions 682system.cpu.iew.iewIQFullEvents 42893 # Number of times the IQ has become full, causing a stall 683system.cpu.iew.iewLSQFullEvents 369751 # Number of times the LSQ has become full, causing a stall 684system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations 685system.cpu.iew.predictedTakenIncorrect 190429 # Number of branches that were predicted taken incorrectly 686system.cpu.iew.predictedNotTakenIncorrect 410127 # Number of branches that were predicted not taken incorrectly 687system.cpu.iew.branchMispredicts 600556 # Number of branch mispredicts detected at execute 688system.cpu.iew.iewExecutedInsts 57009373 # Number of executed instructions 689system.cpu.iew.iewExecLoadInsts 10371242 # Number of load instructions executed 690system.cpu.iew.iewExecSquashedInsts 583322 # Number of squashed instructions skipped in execute |
| 677system.cpu.iew.exec_swp 0 # number of swp insts executed | 691system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 678system.cpu.iew.exec_nop 3710734 # number of nop insts executed 679system.cpu.iew.exec_refs 17074164 # number of memory reference insts executed 680system.cpu.iew.exec_branches 8987700 # Number of branches executed 681system.cpu.iew.exec_stores 6686076 # Number of stores executed 682system.cpu.iew.exec_rate 0.482265 # Inst execution rate 683system.cpu.iew.wb_sent 56446206 # cumulative count of insts sent to commit 684system.cpu.iew.wb_count 56307348 # cumulative count of insts written-back 685system.cpu.iew.wb_producers 28961590 # num instructions producing a value 686system.cpu.iew.wb_consumers 40346871 # num instructions consuming a value | 692system.cpu.iew.exec_nop 3703730 # number of nop insts executed 693system.cpu.iew.exec_refs 17042240 # number of memory reference insts executed 694system.cpu.iew.exec_branches 8981920 # Number of branches executed 695system.cpu.iew.exec_stores 6670998 # Number of stores executed 696system.cpu.iew.exec_rate 0.481901 # Inst execution rate 697system.cpu.iew.wb_sent 56380366 # cumulative count of insts sent to commit 698system.cpu.iew.wb_count 56245724 # cumulative count of insts written-back 699system.cpu.iew.wb_producers 28936691 # num instructions producing a value 700system.cpu.iew.wb_consumers 40310167 # num instructions consuming a value |
| 687system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 701system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 688system.cpu.iew.wb_rate 0.475753 # insts written-back per cycle 689system.cpu.iew.wb_fanout 0.717815 # average fanout of values written-back | 702system.cpu.iew.wb_rate 0.475446 # insts written-back per cycle 703system.cpu.iew.wb_fanout 0.717851 # average fanout of values written-back |
| 690system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 704system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 691system.cpu.commit.commitSquashedInsts 8290413 # The number of squashed insts skipped by commit 692system.cpu.commit.commitNonSpecStalls 661190 # The number of times commit has been forced to stall to communicate backwards 693system.cpu.commit.branchMispredicts 549582 # The number of times a branch was mispredicted 694system.cpu.commit.committed_per_cycle::samples 111493844 # Number of insts commited each cycle 695system.cpu.commit.committed_per_cycle::mean 0.503831 # Number of insts commited each cycle 696system.cpu.commit.committed_per_cycle::stdev 1.456125 # Number of insts commited each cycle | 705system.cpu.commit.commitSquashedInsts 8239182 # The number of squashed insts skipped by commit 706system.cpu.commit.commitNonSpecStalls 661144 # The number of times commit has been forced to stall to communicate backwards 707system.cpu.commit.branchMispredicts 548042 # The number of times a branch was mispredicted 708system.cpu.commit.committed_per_cycle::samples 111437316 # Number of insts commited each cycle 709system.cpu.commit.committed_per_cycle::mean 0.503568 # Number of insts commited each cycle 710system.cpu.commit.committed_per_cycle::stdev 1.455315 # Number of insts commited each cycle |
| 697system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 711system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 698system.cpu.commit.committed_per_cycle::0 91848046 82.38% 82.38% # Number of insts commited each cycle 699system.cpu.commit.committed_per_cycle::1 7822356 7.02% 89.40% # Number of insts commited each cycle 700system.cpu.commit.committed_per_cycle::2 4123652 3.70% 93.09% # Number of insts commited each cycle 701system.cpu.commit.committed_per_cycle::3 2157766 1.94% 95.03% # Number of insts commited each cycle 702system.cpu.commit.committed_per_cycle::4 1851713 1.66% 96.69% # Number of insts commited each cycle 703system.cpu.commit.committed_per_cycle::5 614180 0.55% 97.24% # Number of insts commited each cycle 704system.cpu.commit.committed_per_cycle::6 473259 0.42% 97.67% # Number of insts commited each cycle 705system.cpu.commit.committed_per_cycle::7 509141 0.46% 98.12% # Number of insts commited each cycle 706system.cpu.commit.committed_per_cycle::8 2093731 1.88% 100.00% # Number of insts commited each cycle | 712system.cpu.commit.committed_per_cycle::0 91810154 82.39% 82.39% # Number of insts commited each cycle 713system.cpu.commit.committed_per_cycle::1 7802563 7.00% 89.39% # Number of insts commited each cycle 714system.cpu.commit.committed_per_cycle::2 4132031 3.71% 93.10% # Number of insts commited each cycle 715system.cpu.commit.committed_per_cycle::3 2155493 1.93% 95.03% # Number of insts commited each cycle 716system.cpu.commit.committed_per_cycle::4 1853584 1.66% 96.69% # Number of insts commited each cycle 717system.cpu.commit.committed_per_cycle::5 616181 0.55% 97.25% # Number of insts commited each cycle 718system.cpu.commit.committed_per_cycle::6 467348 0.42% 97.67% # Number of insts commited each cycle 719system.cpu.commit.committed_per_cycle::7 515869 0.46% 98.13% # Number of insts commited each cycle 720system.cpu.commit.committed_per_cycle::8 2084093 1.87% 100.00% # Number of insts commited each cycle |
| 707system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 708system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 709system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 721system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 722system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 723system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 710system.cpu.commit.committed_per_cycle::total 111493844 # Number of insts commited each cycle 711system.cpu.commit.committedInsts 56174099 # Number of instructions committed 712system.cpu.commit.committedOps 56174099 # Number of ops (including micro ops) committed | 724system.cpu.commit.committed_per_cycle::total 111437316 # Number of insts commited each cycle 725system.cpu.commit.committedInsts 56116260 # Number of instructions committed 726system.cpu.commit.committedOps 56116260 # Number of ops (including micro ops) committed |
| 713system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 727system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 714system.cpu.commit.refs 15471950 # Number of memory references committed 715system.cpu.commit.loads 9093334 # Number of loads committed 716system.cpu.commit.membars 226345 # Number of memory barriers committed 717system.cpu.commit.branches 8441019 # Number of branches committed 718system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. 719system.cpu.commit.int_insts 52023449 # Number of committed integer instructions. 720system.cpu.commit.function_calls 740634 # Number of function calls committed. 721system.cpu.commit.op_class_0::No_OpClass 3198108 5.69% 5.69% # Class of committed instruction 722system.cpu.commit.op_class_0::IntAlu 36220301 64.48% 70.17% # Class of committed instruction 723system.cpu.commit.op_class_0::IntMult 60671 0.11% 70.28% # Class of committed instruction 724system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 725system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction 726system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 727system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 728system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction | 728system.cpu.commit.refs 15458143 # Number of memory references committed 729system.cpu.commit.loads 9084456 # Number of loads committed 730system.cpu.commit.membars 226334 # Number of memory barriers committed 731system.cpu.commit.branches 8434463 # Number of branches committed 732system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. 733system.cpu.commit.int_insts 51967854 # Number of committed integer instructions. 734system.cpu.commit.function_calls 739911 # Number of function calls committed. 735system.cpu.commit.op_class_0::No_OpClass 3195933 5.70% 5.70% # Class of committed instruction 736system.cpu.commit.op_class_0::IntAlu 36178550 64.47% 70.17% # Class of committed instruction 737system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.27% # Class of committed instruction 738system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction 739system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction 740system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction 741system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction 742system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction |
| 729system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 730system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 731system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 732system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 733system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 734system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 735system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 736system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction --- 6 unchanged lines hidden (view full) --- 743system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 744system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 745system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 746system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 747system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 748system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 749system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 750system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction | 743system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 744system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 745system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 746system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 747system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 748system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 749system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 750system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction --- 6 unchanged lines hidden (view full) --- 757system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 758system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 759system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 760system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 761system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 762system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 763system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 764system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction |
| 751system.cpu.commit.op_class_0::MemRead 9319679 16.59% 86.94% # Class of committed instruction 752system.cpu.commit.op_class_0::MemWrite 6384570 11.37% 98.31% # Class of committed instruction 753system.cpu.commit.op_class_0::IprAccess 949047 1.69% 100.00% # Class of committed instruction | 765system.cpu.commit.op_class_0::MemRead 9310790 16.59% 86.94% # Class of committed instruction 766system.cpu.commit.op_class_0::MemWrite 6379639 11.37% 98.31% # Class of committed instruction 767system.cpu.commit.op_class_0::IprAccess 948960 1.69% 100.00% # Class of committed instruction |
| 754system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 768system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 755system.cpu.commit.op_class_0::total 56174099 # Class of committed instruction 756system.cpu.commit.bw_lim_events 2093731 # number cycles where commit BW limit reached | 769system.cpu.commit.op_class_0::total 56116260 # Class of committed instruction 770system.cpu.commit.bw_lim_events 2084093 # number cycles where commit BW limit reached |
| 757system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 771system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 758system.cpu.rob.rob_reads 173614429 # The number of ROB reads 759system.cpu.rob.rob_writes 130369620 # The number of ROB writes 760system.cpu.timesIdled 576556 # Number of times that the entire CPU went into an idle state and unscheduled itself 761system.cpu.idleCycles 5422310 # Total number of cycles that the CPU has spent unscheduled due to idling 762system.cpu.quiesceCycles 3601657297 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 763system.cpu.committedInsts 52983264 # Number of Instructions Simulated 764system.cpu.committedOps 52983264 # Number of Ops (including micro ops) Simulated 765system.cpu.cpi 2.233802 # CPI: Cycles Per Instruction 766system.cpu.cpi_total 2.233802 # CPI: Total CPI of All Threads 767system.cpu.ipc 0.447667 # IPC: Instructions Per Cycle 768system.cpu.ipc_total 0.447667 # IPC: Total IPC of All Threads 769system.cpu.int_regfile_reads 74755796 # number of integer regfile reads 770system.cpu.int_regfile_writes 40630218 # number of integer regfile writes 771system.cpu.fp_regfile_reads 167440 # number of floating regfile reads 772system.cpu.fp_regfile_writes 167913 # number of floating regfile writes 773system.cpu.misc_regfile_reads 2030226 # number of misc regfile reads 774system.cpu.misc_regfile_writes 939431 # number of misc regfile writes | 772system.cpu.rob.rob_reads 173459156 # The number of ROB reads 773system.cpu.rob.rob_writes 130141826 # The number of ROB writes 774system.cpu.timesIdled 576115 # Number of times that the entire CPU went into an idle state and unscheduled itself 775system.cpu.idleCycles 5428979 # Total number of cycles that the CPU has spent unscheduled due to idling 776system.cpu.quiesceCycles 3599776298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 777system.cpu.committedInsts 52927600 # Number of Instructions Simulated 778system.cpu.committedOps 52927600 # Number of Ops (including micro ops) Simulated 779system.cpu.cpi 2.235149 # CPI: Cycles Per Instruction 780system.cpu.cpi_total 2.235149 # CPI: Total CPI of All Threads 781system.cpu.ipc 0.447398 # IPC: Instructions Per Cycle 782system.cpu.ipc_total 0.447398 # IPC: Total IPC of All Threads 783system.cpu.int_regfile_reads 74648651 # number of integer regfile reads 784system.cpu.int_regfile_writes 40584029 # number of integer regfile writes 785system.cpu.fp_regfile_reads 166982 # number of floating regfile reads 786system.cpu.fp_regfile_writes 167600 # number of floating regfile writes 787system.cpu.misc_regfile_reads 2029015 # number of misc regfile reads 788system.cpu.misc_regfile_writes 939371 # number of misc regfile writes |
| 775system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 776system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 777system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 778system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 779system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 780system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 781system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 782system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 798system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 799system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 800system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 801system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 802system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 803system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 804system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 805system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 789system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 790system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 791system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 792system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 793system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 794system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 795system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 796system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 812system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 813system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 814system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 815system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 816system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 817system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 818system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 819system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 806system.iobus.throughput 1454701 # Throughput (bytes/s) | |
| 807system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 808system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 820system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 821system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 809system.iobus.trans_dist::WriteReq 51086 # Transaction distribution 810system.iobus.trans_dist::WriteResp 51150 # Transaction distribution 811system.iobus.trans_dist::WriteInvalidateReq 64 # Transaction distribution 812system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) | 822system.iobus.trans_dist::WriteReq 51063 # Transaction distribution 823system.iobus.trans_dist::WriteResp 51149 # Transaction distribution 824system.iobus.trans_dist::WriteInvalidateReq 86 # Transaction distribution 825system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) |
| 813system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 814system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 815system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 816system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 817system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 818system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 819system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 820system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 821system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 822system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 823system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 826system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 827system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 828system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 829system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 830system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 831system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 832system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 833system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 834system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 835system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 836system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 824system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) | 837system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) |
| 825system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 826system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 838system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 839system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 827system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 828system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 829system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 830system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 831system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 832system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 833system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 834system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 835system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 836system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 837system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 838system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 839system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 840system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 841system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 842system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 843system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 844system.iobus.data_through_bus 2705756 # Total data (bytes) 845system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) | 840system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) 841system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) 842system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 843system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 844system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 845system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 846system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 847system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 848system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 849system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 850system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 851system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 852system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 853system.iobus.pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) 854system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 855system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 856system.iobus.pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) 857system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) |
| 846system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 847system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 848system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 849system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 850system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 851system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 852system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 853system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 859system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 860system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 861system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 862system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 863system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 864system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 865system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 866system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 858system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 859system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 860system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 861system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 862system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 863system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 864system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 865system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 871system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 872system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 873system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 874system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 875system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 876system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 877system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 878system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 867system.iobus.reqLayer29.occupancy 374510641 # Layer occupancy (ticks) | 879system.iobus.reqLayer29.occupancy 374547621 # Layer occupancy (ticks) |
| 868system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 869system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 870system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 880system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 881system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 882system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 871system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) | 883system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) |
| 872system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 873system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) 874system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 884system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 885system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) 886system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 875system.cpu.toL2Bus.throughput 114654995 # Throughput (bytes/s) 876system.cpu.toL2Bus.trans_dist::ReadReq 2149538 # Transaction distribution 877system.cpu.toL2Bus.trans_dist::ReadResp 2149432 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 879system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 880system.cpu.toL2Bus.trans_dist::Writeback 845214 # Transaction distribution | 887system.cpu.toL2Bus.trans_dist::ReadReq 2147499 # Transaction distribution 888system.cpu.toL2Bus.trans_dist::ReadResp 2147393 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::Writeback 842679 # Transaction distribution |
| 881system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution | 892system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution |
| 882system.cpu.toL2Bus.trans_dist::UpgradeReq 94 # Transaction distribution 883system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution 884system.cpu.toL2Bus.trans_dist::UpgradeResp 122 # Transaction distribution 885system.cpu.toL2Bus.trans_dist::ReadExReq 302210 # Transaction distribution 886system.cpu.toL2Bus.trans_dist::ReadExResp 302210 # Transaction distribution | 893system.cpu.toL2Bus.trans_dist::UpgradeReq 81 # Transaction distribution 894system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution 895system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution 896system.cpu.toL2Bus.trans_dist::ReadExReq 301934 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::ReadExResp 301934 # Transaction distribution |
| 887system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution | 898system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution |
| 888system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074480 # Packet count per connected master and slave (bytes) 889system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3693292 # Packet count per connected master and slave (bytes) 890system.cpu.toL2Bus.pkt_count::total 5767772 # Packet count per connected master and slave (bytes) 891system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66377344 # Cumulative packet size per connected master and slave (bytes) 892system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144210036 # Cumulative packet size per connected master and slave (bytes) 893system.cpu.toL2Bus.tot_pkt_size::total 210587380 # Cumulative packet size per connected master and slave (bytes) 894system.cpu.toL2Bus.data_through_bus 210577396 # Total data (bytes) 895system.cpu.toL2Bus.snoop_data_through_bus 2681920 # Total snoop data (bytes) 896system.cpu.toL2Bus.reqLayer0.occupancy 2503268997 # Layer occupancy (ticks) | 899system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074254 # Packet count per connected master and slave (bytes) 900system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686339 # Packet count per connected master and slave (bytes) 901system.cpu.toL2Bus.pkt_count::total 5760593 # Packet count per connected master and slave (bytes) 902system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66370688 # Cumulative packet size per connected master and slave (bytes) 903system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143907436 # Cumulative packet size per connected master and slave (bytes) 904system.cpu.toL2Bus.pkt_size::total 210278124 # Cumulative packet size per connected master and slave (bytes) 905system.cpu.toL2Bus.snoops 42060 # Total snoops (count) 906system.cpu.toL2Bus.snoop_fanout::samples 3326850 # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::stdev 0.111298 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 911system.cpu.toL2Bus.snoop_fanout::1 3285116 98.75% 98.75% # Request fanout histogram 912system.cpu.toL2Bus.snoop_fanout::2 41734 1.25% 100.00% # Request fanout histogram 913system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 914system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 915system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 916system.cpu.toL2Bus.snoop_fanout::total 3326850 # Request fanout histogram 917system.cpu.toL2Bus.reqLayer0.occupancy 2498300996 # Layer occupancy (ticks) |
| 897system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 898system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 899system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 918system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 919system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 920system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 900system.cpu.toL2Bus.respLayer0.occupancy 1560084006 # Layer occupancy (ticks) | 921system.cpu.toL2Bus.respLayer0.occupancy 1559854344 # Layer occupancy (ticks) |
| 901system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 922system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 902system.cpu.toL2Bus.respLayer1.occupancy 2193039668 # Layer occupancy (ticks) | 923system.cpu.toL2Bus.respLayer1.occupancy 2189806641 # Layer occupancy (ticks) |
| 903system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 924system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 904system.cpu.icache.tags.replacements 1036559 # number of replacements 905system.cpu.icache.tags.tagsinuse 509.401978 # Cycle average of tags in use 906system.cpu.icache.tags.total_refs 7968978 # Total number of references to valid blocks. 907system.cpu.icache.tags.sampled_refs 1037067 # Sample count of references to valid blocks. 908system.cpu.icache.tags.avg_refs 7.684150 # Average number of references to valid blocks. 909system.cpu.icache.tags.warmup_cycle 26427286250 # Cycle when the warmup percentage was hit. 910system.cpu.icache.tags.occ_blocks::cpu.inst 509.401978 # Average occupied blocks per requestor | 925system.cpu.icache.tags.replacements 1036451 # number of replacements 926system.cpu.icache.tags.tagsinuse 509.402237 # Cycle average of tags in use 927system.cpu.icache.tags.total_refs 7937240 # Total number of references to valid blocks. 928system.cpu.icache.tags.sampled_refs 1036959 # Sample count of references to valid blocks. 929system.cpu.icache.tags.avg_refs 7.654343 # Average number of references to valid blocks. 930system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. 931system.cpu.icache.tags.occ_blocks::cpu.inst 509.402237 # Average occupied blocks per requestor |
| 911system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy 912system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy 913system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 914system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id | 932system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy 933system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy 934system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id 935system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id |
| 915system.cpu.icache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id 916system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id | 936system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id 937system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id |
| 917system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id | 938system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id |
| 918system.cpu.icache.tags.tag_accesses 10094673 # Number of tag accesses 919system.cpu.icache.tags.data_accesses 10094673 # Number of data accesses 920system.cpu.icache.ReadReq_hits::cpu.inst 7968979 # number of ReadReq hits 921system.cpu.icache.ReadReq_hits::total 7968979 # number of ReadReq hits 922system.cpu.icache.demand_hits::cpu.inst 7968979 # number of demand (read+write) hits 923system.cpu.icache.demand_hits::total 7968979 # number of demand (read+write) hits 924system.cpu.icache.overall_hits::cpu.inst 7968979 # number of overall hits 925system.cpu.icache.overall_hits::total 7968979 # number of overall hits 926system.cpu.icache.ReadReq_misses::cpu.inst 1088360 # number of ReadReq misses 927system.cpu.icache.ReadReq_misses::total 1088360 # number of ReadReq misses 928system.cpu.icache.demand_misses::cpu.inst 1088360 # number of demand (read+write) misses 929system.cpu.icache.demand_misses::total 1088360 # number of demand (read+write) misses 930system.cpu.icache.overall_misses::cpu.inst 1088360 # number of overall misses 931system.cpu.icache.overall_misses::total 1088360 # number of overall misses 932system.cpu.icache.ReadReq_miss_latency::cpu.inst 15140469933 # number of ReadReq miss cycles 933system.cpu.icache.ReadReq_miss_latency::total 15140469933 # number of ReadReq miss cycles 934system.cpu.icache.demand_miss_latency::cpu.inst 15140469933 # number of demand (read+write) miss cycles 935system.cpu.icache.demand_miss_latency::total 15140469933 # number of demand (read+write) miss cycles 936system.cpu.icache.overall_miss_latency::cpu.inst 15140469933 # number of overall miss cycles 937system.cpu.icache.overall_miss_latency::total 15140469933 # number of overall miss cycles 938system.cpu.icache.ReadReq_accesses::cpu.inst 9057339 # number of ReadReq accesses(hits+misses) 939system.cpu.icache.ReadReq_accesses::total 9057339 # number of ReadReq accesses(hits+misses) 940system.cpu.icache.demand_accesses::cpu.inst 9057339 # number of demand (read+write) accesses 941system.cpu.icache.demand_accesses::total 9057339 # number of demand (read+write) accesses 942system.cpu.icache.overall_accesses::cpu.inst 9057339 # number of overall (read+write) accesses 943system.cpu.icache.overall_accesses::total 9057339 # number of overall (read+write) accesses 944system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120163 # miss rate for ReadReq accesses 945system.cpu.icache.ReadReq_miss_rate::total 0.120163 # miss rate for ReadReq accesses 946system.cpu.icache.demand_miss_rate::cpu.inst 0.120163 # miss rate for demand accesses 947system.cpu.icache.demand_miss_rate::total 0.120163 # miss rate for demand accesses 948system.cpu.icache.overall_miss_rate::cpu.inst 0.120163 # miss rate for overall accesses 949system.cpu.icache.overall_miss_rate::total 0.120163 # miss rate for overall accesses 950system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13911.270106 # average ReadReq miss latency 951system.cpu.icache.ReadReq_avg_miss_latency::total 13911.270106 # average ReadReq miss latency 952system.cpu.icache.demand_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency 953system.cpu.icache.demand_avg_miss_latency::total 13911.270106 # average overall miss latency 954system.cpu.icache.overall_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency 955system.cpu.icache.overall_avg_miss_latency::total 13911.270106 # average overall miss latency 956system.cpu.icache.blocked_cycles::no_mshrs 4471 # number of cycles access was blocked | 939system.cpu.icache.tags.tag_accesses 10062742 # Number of tag accesses 940system.cpu.icache.tags.data_accesses 10062742 # Number of data accesses 941system.cpu.icache.ReadReq_hits::cpu.inst 7937241 # number of ReadReq hits 942system.cpu.icache.ReadReq_hits::total 7937241 # number of ReadReq hits 943system.cpu.icache.demand_hits::cpu.inst 7937241 # number of demand (read+write) hits 944system.cpu.icache.demand_hits::total 7937241 # number of demand (read+write) hits 945system.cpu.icache.overall_hits::cpu.inst 7937241 # number of overall hits 946system.cpu.icache.overall_hits::total 7937241 # number of overall hits 947system.cpu.icache.ReadReq_misses::cpu.inst 1088289 # number of ReadReq misses 948system.cpu.icache.ReadReq_misses::total 1088289 # number of ReadReq misses 949system.cpu.icache.demand_misses::cpu.inst 1088289 # number of demand (read+write) misses 950system.cpu.icache.demand_misses::total 1088289 # number of demand (read+write) misses 951system.cpu.icache.overall_misses::cpu.inst 1088289 # number of overall misses 952system.cpu.icache.overall_misses::total 1088289 # number of overall misses 953system.cpu.icache.ReadReq_miss_latency::cpu.inst 15130440508 # number of ReadReq miss cycles 954system.cpu.icache.ReadReq_miss_latency::total 15130440508 # number of ReadReq miss cycles 955system.cpu.icache.demand_miss_latency::cpu.inst 15130440508 # number of demand (read+write) miss cycles 956system.cpu.icache.demand_miss_latency::total 15130440508 # number of demand (read+write) miss cycles 957system.cpu.icache.overall_miss_latency::cpu.inst 15130440508 # number of overall miss cycles 958system.cpu.icache.overall_miss_latency::total 15130440508 # number of overall miss cycles 959system.cpu.icache.ReadReq_accesses::cpu.inst 9025530 # number of ReadReq accesses(hits+misses) 960system.cpu.icache.ReadReq_accesses::total 9025530 # number of ReadReq accesses(hits+misses) 961system.cpu.icache.demand_accesses::cpu.inst 9025530 # number of demand (read+write) accesses 962system.cpu.icache.demand_accesses::total 9025530 # number of demand (read+write) accesses 963system.cpu.icache.overall_accesses::cpu.inst 9025530 # number of overall (read+write) accesses 964system.cpu.icache.overall_accesses::total 9025530 # number of overall (read+write) accesses 965system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120579 # miss rate for ReadReq accesses 966system.cpu.icache.ReadReq_miss_rate::total 0.120579 # miss rate for ReadReq accesses 967system.cpu.icache.demand_miss_rate::cpu.inst 0.120579 # miss rate for demand accesses 968system.cpu.icache.demand_miss_rate::total 0.120579 # miss rate for demand accesses 969system.cpu.icache.overall_miss_rate::cpu.inst 0.120579 # miss rate for overall accesses 970system.cpu.icache.overall_miss_rate::total 0.120579 # miss rate for overall accesses 971system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13902.961904 # average ReadReq miss latency 972system.cpu.icache.ReadReq_avg_miss_latency::total 13902.961904 # average ReadReq miss latency 973system.cpu.icache.demand_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency 974system.cpu.icache.demand_avg_miss_latency::total 13902.961904 # average overall miss latency 975system.cpu.icache.overall_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency 976system.cpu.icache.overall_avg_miss_latency::total 13902.961904 # average overall miss latency 977system.cpu.icache.blocked_cycles::no_mshrs 4627 # number of cycles access was blocked |
| 957system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 978system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 958system.cpu.icache.blocked::no_mshrs 200 # number of cycles access was blocked | 979system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked |
| 959system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 980system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 960system.cpu.icache.avg_blocked_cycles::no_mshrs 22.355000 # average number of cycles each access was blocked | 981system.cpu.icache.avg_blocked_cycles::no_mshrs 22.793103 # average number of cycles each access was blocked |
| 961system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 962system.cpu.icache.fast_writes 0 # number of fast writes performed 963system.cpu.icache.cache_copies 0 # number of cache copies performed | 982system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 983system.cpu.icache.fast_writes 0 # number of fast writes performed 984system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 964system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51026 # number of ReadReq MSHR hits 965system.cpu.icache.ReadReq_mshr_hits::total 51026 # number of ReadReq MSHR hits 966system.cpu.icache.demand_mshr_hits::cpu.inst 51026 # number of demand (read+write) MSHR hits 967system.cpu.icache.demand_mshr_hits::total 51026 # number of demand (read+write) MSHR hits 968system.cpu.icache.overall_mshr_hits::cpu.inst 51026 # number of overall MSHR hits 969system.cpu.icache.overall_mshr_hits::total 51026 # number of overall MSHR hits 970system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037334 # number of ReadReq MSHR misses 971system.cpu.icache.ReadReq_mshr_misses::total 1037334 # number of ReadReq MSHR misses 972system.cpu.icache.demand_mshr_misses::cpu.inst 1037334 # number of demand (read+write) MSHR misses 973system.cpu.icache.demand_mshr_misses::total 1037334 # number of demand (read+write) MSHR misses 974system.cpu.icache.overall_mshr_misses::cpu.inst 1037334 # number of overall MSHR misses 975system.cpu.icache.overall_mshr_misses::total 1037334 # number of overall MSHR misses 976system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12446794989 # number of ReadReq MSHR miss cycles 977system.cpu.icache.ReadReq_mshr_miss_latency::total 12446794989 # number of ReadReq MSHR miss cycles 978system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12446794989 # number of demand (read+write) MSHR miss cycles 979system.cpu.icache.demand_mshr_miss_latency::total 12446794989 # number of demand (read+write) MSHR miss cycles 980system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12446794989 # number of overall MSHR miss cycles 981system.cpu.icache.overall_mshr_miss_latency::total 12446794989 # number of overall MSHR miss cycles 982system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for ReadReq accesses 983system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114530 # mshr miss rate for ReadReq accesses 984system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for demand accesses 985system.cpu.icache.demand_mshr_miss_rate::total 0.114530 # mshr miss rate for demand accesses 986system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for overall accesses 987system.cpu.icache.overall_mshr_miss_rate::total 0.114530 # mshr miss rate for overall accesses 988system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.830646 # average ReadReq mshr miss latency 989system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.830646 # average ReadReq mshr miss latency 990system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency 991system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency 992system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency 993system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency | 985system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51077 # number of ReadReq MSHR hits 986system.cpu.icache.ReadReq_mshr_hits::total 51077 # number of ReadReq MSHR hits 987system.cpu.icache.demand_mshr_hits::cpu.inst 51077 # number of demand (read+write) MSHR hits 988system.cpu.icache.demand_mshr_hits::total 51077 # number of demand (read+write) MSHR hits 989system.cpu.icache.overall_mshr_hits::cpu.inst 51077 # number of overall MSHR hits 990system.cpu.icache.overall_mshr_hits::total 51077 # number of overall MSHR hits 991system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037212 # number of ReadReq MSHR misses 992system.cpu.icache.ReadReq_mshr_misses::total 1037212 # number of ReadReq MSHR misses 993system.cpu.icache.demand_mshr_misses::cpu.inst 1037212 # number of demand (read+write) MSHR misses 994system.cpu.icache.demand_mshr_misses::total 1037212 # number of demand (read+write) MSHR misses 995system.cpu.icache.overall_mshr_misses::cpu.inst 1037212 # number of overall MSHR misses 996system.cpu.icache.overall_mshr_misses::total 1037212 # number of overall MSHR misses 997system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12445124401 # number of ReadReq MSHR miss cycles 998system.cpu.icache.ReadReq_mshr_miss_latency::total 12445124401 # number of ReadReq MSHR miss cycles 999system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12445124401 # number of demand (read+write) MSHR miss cycles 1000system.cpu.icache.demand_mshr_miss_latency::total 12445124401 # number of demand (read+write) MSHR miss cycles 1001system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12445124401 # number of overall MSHR miss cycles 1002system.cpu.icache.overall_mshr_miss_latency::total 12445124401 # number of overall MSHR miss cycles 1003system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for ReadReq accesses 1004system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114920 # mshr miss rate for ReadReq accesses 1005system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for demand accesses 1006system.cpu.icache.demand_mshr_miss_rate::total 0.114920 # mshr miss rate for demand accesses 1007system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for overall accesses 1008system.cpu.icache.overall_mshr_miss_rate::total 0.114920 # mshr miss rate for overall accesses 1009system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.631332 # average ReadReq mshr miss latency 1010system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.631332 # average ReadReq mshr miss latency 1011system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency 1012system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency 1013system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency 1014system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency |
| 994system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1015system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 995system.cpu.l2cache.tags.replacements 338424 # number of replacements 996system.cpu.l2cache.tags.tagsinuse 65337.415563 # Cycle average of tags in use 997system.cpu.l2cache.tags.total_refs 2581710 # Total number of references to valid blocks. 998system.cpu.l2cache.tags.sampled_refs 403590 # Sample count of references to valid blocks. 999system.cpu.l2cache.tags.avg_refs 6.396863 # Average number of references to valid blocks. 1000system.cpu.l2cache.tags.warmup_cycle 5538438750 # Cycle when the warmup percentage was hit. 1001system.cpu.l2cache.tags.occ_blocks::writebacks 53805.196085 # Average occupied blocks per requestor 1002system.cpu.l2cache.tags.occ_blocks::cpu.inst 5357.724352 # Average occupied blocks per requestor 1003system.cpu.l2cache.tags.occ_blocks::cpu.data 6174.495125 # Average occupied blocks per requestor 1004system.cpu.l2cache.tags.occ_percent::writebacks 0.821002 # Average percentage of cache occupancy 1005system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081752 # Average percentage of cache occupancy 1006system.cpu.l2cache.tags.occ_percent::cpu.data 0.094215 # Average percentage of cache occupancy 1007system.cpu.l2cache.tags.occ_percent::total 0.996970 # Average percentage of cache occupancy 1008system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id 1009system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 1010system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3497 # Occupied blocks per task id 1011system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3323 # Occupied blocks per task id 1012system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id 1013system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55433 # Occupied blocks per task id 1014system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id 1015system.cpu.l2cache.tags.tag_accesses 27024459 # Number of tag accesses 1016system.cpu.l2cache.tags.data_accesses 27024459 # Number of data accesses 1017system.cpu.l2cache.ReadReq_hits::cpu.inst 1022012 # number of ReadReq hits 1018system.cpu.l2cache.ReadReq_hits::cpu.data 831240 # number of ReadReq hits 1019system.cpu.l2cache.ReadReq_hits::total 1853252 # number of ReadReq hits 1020system.cpu.l2cache.Writeback_hits::writebacks 845214 # number of Writeback hits 1021system.cpu.l2cache.Writeback_hits::total 845214 # number of Writeback hits 1022system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 1023system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 1024system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits 1025system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits 1026system.cpu.l2cache.ReadExReq_hits::cpu.data 186775 # number of ReadExReq hits 1027system.cpu.l2cache.ReadExReq_hits::total 186775 # number of ReadExReq hits 1028system.cpu.l2cache.demand_hits::cpu.inst 1022012 # number of demand (read+write) hits 1029system.cpu.l2cache.demand_hits::cpu.data 1018015 # number of demand (read+write) hits 1030system.cpu.l2cache.demand_hits::total 2040027 # number of demand (read+write) hits 1031system.cpu.l2cache.overall_hits::cpu.inst 1022012 # number of overall hits 1032system.cpu.l2cache.overall_hits::cpu.data 1018015 # number of overall hits 1033system.cpu.l2cache.overall_hits::total 2040027 # number of overall hits 1034system.cpu.l2cache.ReadReq_misses::cpu.inst 15134 # number of ReadReq misses 1035system.cpu.l2cache.ReadReq_misses::cpu.data 273861 # number of ReadReq misses 1036system.cpu.l2cache.ReadReq_misses::total 288995 # number of ReadReq misses 1037system.cpu.l2cache.UpgradeReq_misses::cpu.data 68 # number of UpgradeReq misses 1038system.cpu.l2cache.UpgradeReq_misses::total 68 # number of UpgradeReq misses 1039system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses 1040system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses 1041system.cpu.l2cache.ReadExReq_misses::cpu.data 115435 # number of ReadExReq misses 1042system.cpu.l2cache.ReadExReq_misses::total 115435 # number of ReadExReq misses 1043system.cpu.l2cache.demand_misses::cpu.inst 15134 # number of demand (read+write) misses 1044system.cpu.l2cache.demand_misses::cpu.data 389296 # number of demand (read+write) misses 1045system.cpu.l2cache.demand_misses::total 404430 # number of demand (read+write) misses 1046system.cpu.l2cache.overall_misses::cpu.inst 15134 # number of overall misses 1047system.cpu.l2cache.overall_misses::cpu.data 389296 # number of overall misses 1048system.cpu.l2cache.overall_misses::total 404430 # number of overall misses 1049system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1158853750 # number of ReadReq miss cycles 1050system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17990415250 # number of ReadReq miss cycles 1051system.cpu.l2cache.ReadReq_miss_latency::total 19149269000 # number of ReadReq miss cycles 1052system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 271990 # number of UpgradeReq miss cycles 1053system.cpu.l2cache.UpgradeReq_miss_latency::total 271990 # number of UpgradeReq miss cycles 1054system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles 1055system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles 1056system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9647831862 # number of ReadExReq miss cycles 1057system.cpu.l2cache.ReadExReq_miss_latency::total 9647831862 # number of ReadExReq miss cycles 1058system.cpu.l2cache.demand_miss_latency::cpu.inst 1158853750 # number of demand (read+write) miss cycles 1059system.cpu.l2cache.demand_miss_latency::cpu.data 27638247112 # number of demand (read+write) miss cycles 1060system.cpu.l2cache.demand_miss_latency::total 28797100862 # number of demand (read+write) miss cycles 1061system.cpu.l2cache.overall_miss_latency::cpu.inst 1158853750 # number of overall miss cycles 1062system.cpu.l2cache.overall_miss_latency::cpu.data 27638247112 # number of overall miss cycles 1063system.cpu.l2cache.overall_miss_latency::total 28797100862 # number of overall miss cycles 1064system.cpu.l2cache.ReadReq_accesses::cpu.inst 1037146 # number of ReadReq accesses(hits+misses) 1065system.cpu.l2cache.ReadReq_accesses::cpu.data 1105101 # number of ReadReq accesses(hits+misses) 1066system.cpu.l2cache.ReadReq_accesses::total 2142247 # number of ReadReq accesses(hits+misses) 1067system.cpu.l2cache.Writeback_accesses::writebacks 845214 # number of Writeback accesses(hits+misses) 1068system.cpu.l2cache.Writeback_accesses::total 845214 # number of Writeback accesses(hits+misses) 1069system.cpu.l2cache.UpgradeReq_accesses::cpu.data 94 # number of UpgradeReq accesses(hits+misses) 1070system.cpu.l2cache.UpgradeReq_accesses::total 94 # number of UpgradeReq accesses(hits+misses) 1071system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) 1072system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) 1073system.cpu.l2cache.ReadExReq_accesses::cpu.data 302210 # number of ReadExReq accesses(hits+misses) 1074system.cpu.l2cache.ReadExReq_accesses::total 302210 # number of ReadExReq accesses(hits+misses) 1075system.cpu.l2cache.demand_accesses::cpu.inst 1037146 # number of demand (read+write) accesses 1076system.cpu.l2cache.demand_accesses::cpu.data 1407311 # number of demand (read+write) accesses 1077system.cpu.l2cache.demand_accesses::total 2444457 # number of demand (read+write) accesses 1078system.cpu.l2cache.overall_accesses::cpu.inst 1037146 # number of overall (read+write) accesses 1079system.cpu.l2cache.overall_accesses::cpu.data 1407311 # number of overall (read+write) accesses 1080system.cpu.l2cache.overall_accesses::total 2444457 # number of overall (read+write) accesses 1081system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014592 # miss rate for ReadReq accesses 1082system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.247815 # miss rate for ReadReq accesses 1083system.cpu.l2cache.ReadReq_miss_rate::total 0.134903 # miss rate for ReadReq accesses 1084system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.723404 # miss rate for UpgradeReq accesses 1085system.cpu.l2cache.UpgradeReq_miss_rate::total 0.723404 # miss rate for UpgradeReq accesses 1086system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses 1087system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses 1088system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.381969 # miss rate for ReadExReq accesses 1089system.cpu.l2cache.ReadExReq_miss_rate::total 0.381969 # miss rate for ReadExReq accesses 1090system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014592 # miss rate for demand accesses 1091system.cpu.l2cache.demand_miss_rate::cpu.data 0.276624 # miss rate for demand accesses 1092system.cpu.l2cache.demand_miss_rate::total 0.165448 # miss rate for demand accesses 1093system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014592 # miss rate for overall accesses 1094system.cpu.l2cache.overall_miss_rate::cpu.data 0.276624 # miss rate for overall accesses 1095system.cpu.l2cache.overall_miss_rate::total 0.165448 # miss rate for overall accesses 1096system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76572.865733 # average ReadReq miss latency 1097system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65691.775207 # average ReadReq miss latency 1098system.cpu.l2cache.ReadReq_avg_miss_latency::total 66261.592761 # average ReadReq miss latency 1099system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3999.852941 # average UpgradeReq miss latency 1100system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3999.852941 # average UpgradeReq miss latency 1101system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 7833 # average SCUpgradeReq miss latency 1102system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 7833 # average SCUpgradeReq miss latency 1103system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83578.047057 # average ReadExReq miss latency 1104system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83578.047057 # average ReadExReq miss latency 1105system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76572.865733 # average overall miss latency 1106system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70995.456188 # average overall miss latency 1107system.cpu.l2cache.demand_avg_miss_latency::total 71204.166016 # average overall miss latency 1108system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76572.865733 # average overall miss latency 1109system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70995.456188 # average overall miss latency 1110system.cpu.l2cache.overall_avg_miss_latency::total 71204.166016 # average overall miss latency | 1016system.cpu.l2cache.tags.replacements 338311 # number of replacements 1017system.cpu.l2cache.tags.tagsinuse 65336.723406 # Cycle average of tags in use 1018system.cpu.l2cache.tags.total_refs 2577279 # Total number of references to valid blocks. 1019system.cpu.l2cache.tags.sampled_refs 403479 # Sample count of references to valid blocks. 1020system.cpu.l2cache.tags.avg_refs 6.387641 # Average number of references to valid blocks. 1021system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. 1022system.cpu.l2cache.tags.occ_blocks::writebacks 53740.150485 # Average occupied blocks per requestor 1023system.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.296148 # Average occupied blocks per requestor 1024system.cpu.l2cache.tags.occ_blocks::cpu.data 6255.276773 # Average occupied blocks per requestor 1025system.cpu.l2cache.tags.occ_percent::writebacks 0.820010 # Average percentage of cache occupancy 1026system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081502 # Average percentage of cache occupancy 1027system.cpu.l2cache.tags.occ_percent::cpu.data 0.095448 # Average percentage of cache occupancy 1028system.cpu.l2cache.tags.occ_percent::total 0.996959 # Average percentage of cache occupancy 1029system.cpu.l2cache.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id 1030system.cpu.l2cache.tags.age_task_id_blocks_1024::0 497 # Occupied blocks per task id 1031system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id 1032system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id 1033system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2421 # Occupied blocks per task id 1034system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id 1035system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id 1036system.cpu.l2cache.tags.tag_accesses 26985288 # Number of tag accesses 1037system.cpu.l2cache.tags.data_accesses 26985288 # Number of data accesses 1038system.cpu.l2cache.ReadReq_hits::cpu.inst 1021912 # number of ReadReq hits 1039system.cpu.l2cache.ReadReq_hits::cpu.data 829370 # number of ReadReq hits 1040system.cpu.l2cache.ReadReq_hits::total 1851282 # number of ReadReq hits 1041system.cpu.l2cache.Writeback_hits::writebacks 842679 # number of Writeback hits 1042system.cpu.l2cache.Writeback_hits::total 842679 # number of Writeback hits 1043system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits 1044system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits 1045system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 21 # number of SCUpgradeReq hits 1046system.cpu.l2cache.SCUpgradeReq_hits::total 21 # number of SCUpgradeReq hits 1047system.cpu.l2cache.ReadExReq_hits::cpu.data 186572 # number of ReadExReq hits 1048system.cpu.l2cache.ReadExReq_hits::total 186572 # number of ReadExReq hits 1049system.cpu.l2cache.demand_hits::cpu.inst 1021912 # number of demand (read+write) hits 1050system.cpu.l2cache.demand_hits::cpu.data 1015942 # number of demand (read+write) hits 1051system.cpu.l2cache.demand_hits::total 2037854 # number of demand (read+write) hits 1052system.cpu.l2cache.overall_hits::cpu.inst 1021912 # number of overall hits 1053system.cpu.l2cache.overall_hits::cpu.data 1015942 # number of overall hits 1054system.cpu.l2cache.overall_hits::total 2037854 # number of overall hits 1055system.cpu.l2cache.ReadReq_misses::cpu.inst 15130 # number of ReadReq misses 1056system.cpu.l2cache.ReadReq_misses::cpu.data 273814 # number of ReadReq misses 1057system.cpu.l2cache.ReadReq_misses::total 288944 # number of ReadReq misses 1058system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses 1059system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses 1060system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses 1061system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses 1062system.cpu.l2cache.ReadExReq_misses::cpu.data 115362 # number of ReadExReq misses 1063system.cpu.l2cache.ReadExReq_misses::total 115362 # number of ReadExReq misses 1064system.cpu.l2cache.demand_misses::cpu.inst 15130 # number of demand (read+write) misses 1065system.cpu.l2cache.demand_misses::cpu.data 389176 # number of demand (read+write) misses 1066system.cpu.l2cache.demand_misses::total 404306 # number of demand (read+write) misses 1067system.cpu.l2cache.overall_misses::cpu.inst 15130 # number of overall misses 1068system.cpu.l2cache.overall_misses::cpu.data 389176 # number of overall misses 1069system.cpu.l2cache.overall_misses::total 404306 # number of overall misses 1070system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1158124750 # number of ReadReq miss cycles 1071system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17992143250 # number of ReadReq miss cycles 1072system.cpu.l2cache.ReadReq_miss_latency::total 19150268000 # number of ReadReq miss cycles 1073system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 194993 # number of UpgradeReq miss cycles 1074system.cpu.l2cache.UpgradeReq_miss_latency::total 194993 # number of UpgradeReq miss cycles 1075system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 69497 # number of SCUpgradeReq miss cycles 1076system.cpu.l2cache.SCUpgradeReq_miss_latency::total 69497 # number of SCUpgradeReq miss cycles 1077system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9692879611 # number of ReadExReq miss cycles 1078system.cpu.l2cache.ReadExReq_miss_latency::total 9692879611 # number of ReadExReq miss cycles 1079system.cpu.l2cache.demand_miss_latency::cpu.inst 1158124750 # number of demand (read+write) miss cycles 1080system.cpu.l2cache.demand_miss_latency::cpu.data 27685022861 # number of demand (read+write) miss cycles 1081system.cpu.l2cache.demand_miss_latency::total 28843147611 # number of demand (read+write) miss cycles 1082system.cpu.l2cache.overall_miss_latency::cpu.inst 1158124750 # number of overall miss cycles 1083system.cpu.l2cache.overall_miss_latency::cpu.data 27685022861 # number of overall miss cycles 1084system.cpu.l2cache.overall_miss_latency::total 28843147611 # number of overall miss cycles 1085system.cpu.l2cache.ReadReq_accesses::cpu.inst 1037042 # number of ReadReq accesses(hits+misses) 1086system.cpu.l2cache.ReadReq_accesses::cpu.data 1103184 # number of ReadReq accesses(hits+misses) 1087system.cpu.l2cache.ReadReq_accesses::total 2140226 # number of ReadReq accesses(hits+misses) 1088system.cpu.l2cache.Writeback_accesses::writebacks 842679 # number of Writeback accesses(hits+misses) 1089system.cpu.l2cache.Writeback_accesses::total 842679 # number of Writeback accesses(hits+misses) 1090system.cpu.l2cache.UpgradeReq_accesses::cpu.data 81 # number of UpgradeReq accesses(hits+misses) 1091system.cpu.l2cache.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) 1092system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 26 # number of SCUpgradeReq accesses(hits+misses) 1093system.cpu.l2cache.SCUpgradeReq_accesses::total 26 # number of SCUpgradeReq accesses(hits+misses) 1094system.cpu.l2cache.ReadExReq_accesses::cpu.data 301934 # number of ReadExReq accesses(hits+misses) 1095system.cpu.l2cache.ReadExReq_accesses::total 301934 # number of ReadExReq accesses(hits+misses) 1096system.cpu.l2cache.demand_accesses::cpu.inst 1037042 # number of demand (read+write) accesses 1097system.cpu.l2cache.demand_accesses::cpu.data 1405118 # number of demand (read+write) accesses 1098system.cpu.l2cache.demand_accesses::total 2442160 # number of demand (read+write) accesses 1099system.cpu.l2cache.overall_accesses::cpu.inst 1037042 # number of overall (read+write) accesses 1100system.cpu.l2cache.overall_accesses::cpu.data 1405118 # number of overall (read+write) accesses 1101system.cpu.l2cache.overall_accesses::total 2442160 # number of overall (read+write) accesses 1102system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014590 # miss rate for ReadReq accesses 1103system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248203 # miss rate for ReadReq accesses 1104system.cpu.l2cache.ReadReq_miss_rate::total 0.135006 # miss rate for ReadReq accesses 1105system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.592593 # miss rate for UpgradeReq accesses 1106system.cpu.l2cache.UpgradeReq_miss_rate::total 0.592593 # miss rate for UpgradeReq accesses 1107system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.192308 # miss rate for SCUpgradeReq accesses 1108system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.192308 # miss rate for SCUpgradeReq accesses 1109system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382077 # miss rate for ReadExReq accesses 1110system.cpu.l2cache.ReadExReq_miss_rate::total 0.382077 # miss rate for ReadExReq accesses 1111system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014590 # miss rate for demand accesses 1112system.cpu.l2cache.demand_miss_rate::cpu.data 0.276970 # miss rate for demand accesses 1113system.cpu.l2cache.demand_miss_rate::total 0.165553 # miss rate for demand accesses 1114system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014590 # miss rate for overall accesses 1115system.cpu.l2cache.overall_miss_rate::cpu.data 0.276970 # miss rate for overall accesses 1116system.cpu.l2cache.overall_miss_rate::total 0.165553 # miss rate for overall accesses 1117system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76544.927297 # average ReadReq miss latency 1118system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65709.362012 # average ReadReq miss latency 1119system.cpu.l2cache.ReadReq_avg_miss_latency::total 66276.745667 # average ReadReq miss latency 1120system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4062.354167 # average UpgradeReq miss latency 1121system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4062.354167 # average UpgradeReq miss latency 1122system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 13899.400000 # average SCUpgradeReq miss latency 1123system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 13899.400000 # average SCUpgradeReq miss latency 1124system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84021.424828 # average ReadExReq miss latency 1125system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84021.424828 # average ReadExReq miss latency 1126system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency 1127system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency 1128system.cpu.l2cache.demand_avg_miss_latency::total 71339.895057 # average overall miss latency 1129system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency 1130system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency 1131system.cpu.l2cache.overall_avg_miss_latency::total 71339.895057 # average overall miss latency |
| 1111system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1112system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1113system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1114system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1115system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1116system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1117system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1118system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1132system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1133system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1134system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1135system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1136system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1137system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1138system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1139system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1119system.cpu.l2cache.writebacks::writebacks 76032 # number of writebacks 1120system.cpu.l2cache.writebacks::total 76032 # number of writebacks | 1140system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks 1141system.cpu.l2cache.writebacks::total 75938 # number of writebacks |
| 1121system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1122system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1123system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1124system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1125system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1126system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 1142system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1143system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1144system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1145system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1146system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1147system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 1127system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15133 # number of ReadReq MSHR misses 1128system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273861 # number of ReadReq MSHR misses 1129system.cpu.l2cache.ReadReq_mshr_misses::total 288994 # number of ReadReq MSHR misses 1130system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 68 # number of UpgradeReq MSHR misses 1131system.cpu.l2cache.UpgradeReq_mshr_misses::total 68 # number of UpgradeReq MSHR misses 1132system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses 1133system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses 1134system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115435 # number of ReadExReq MSHR misses 1135system.cpu.l2cache.ReadExReq_mshr_misses::total 115435 # number of ReadExReq MSHR misses 1136system.cpu.l2cache.demand_mshr_misses::cpu.inst 15133 # number of demand (read+write) MSHR misses 1137system.cpu.l2cache.demand_mshr_misses::cpu.data 389296 # number of demand (read+write) MSHR misses 1138system.cpu.l2cache.demand_mshr_misses::total 404429 # number of demand (read+write) MSHR misses 1139system.cpu.l2cache.overall_mshr_misses::cpu.inst 15133 # number of overall MSHR misses 1140system.cpu.l2cache.overall_mshr_misses::cpu.data 389296 # number of overall MSHR misses 1141system.cpu.l2cache.overall_mshr_misses::total 404429 # number of overall MSHR misses 1142system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967955000 # number of ReadReq MSHR miss cycles 1143system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14578847250 # number of ReadReq MSHR miss cycles 1144system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15546802250 # number of ReadReq MSHR miss cycles 1145system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 698067 # number of UpgradeReq MSHR miss cycles 1146system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 698067 # number of UpgradeReq MSHR miss cycles 1147system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 60006 # number of SCUpgradeReq MSHR miss cycles 1148system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 60006 # number of SCUpgradeReq MSHR miss cycles 1149system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8240977138 # number of ReadExReq MSHR miss cycles 1150system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8240977138 # number of ReadExReq MSHR miss cycles 1151system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967955000 # number of demand (read+write) MSHR miss cycles 1152system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22819824388 # number of demand (read+write) MSHR miss cycles 1153system.cpu.l2cache.demand_mshr_miss_latency::total 23787779388 # number of demand (read+write) MSHR miss cycles 1154system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967955000 # number of overall MSHR miss cycles 1155system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22819824388 # number of overall MSHR miss cycles 1156system.cpu.l2cache.overall_mshr_miss_latency::total 23787779388 # number of overall MSHR miss cycles 1157system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333197000 # number of ReadReq MSHR uncacheable cycles 1158system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333197000 # number of ReadReq MSHR uncacheable cycles 1159system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882784000 # number of WriteReq MSHR uncacheable cycles 1160system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882784000 # number of WriteReq MSHR uncacheable cycles 1161system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3215981000 # number of overall MSHR uncacheable cycles 1162system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3215981000 # number of overall MSHR uncacheable cycles 1163system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for ReadReq accesses 1164system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.247815 # mshr miss rate for ReadReq accesses 1165system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.134902 # mshr miss rate for ReadReq accesses 1166system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.723404 # mshr miss rate for UpgradeReq accesses 1167system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.723404 # mshr miss rate for UpgradeReq accesses 1168system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses 1169system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses 1170system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.381969 # mshr miss rate for ReadExReq accesses 1171system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.381969 # mshr miss rate for ReadExReq accesses 1172system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for demand accesses 1173system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276624 # mshr miss rate for demand accesses 1174system.cpu.l2cache.demand_mshr_miss_rate::total 0.165447 # mshr miss rate for demand accesses 1175system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014591 # mshr miss rate for overall accesses 1176system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276624 # mshr miss rate for overall accesses 1177system.cpu.l2cache.overall_mshr_miss_rate::total 0.165447 # mshr miss rate for overall accesses 1178system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63963.193022 # average ReadReq mshr miss latency 1179system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53234.477527 # average ReadReq mshr miss latency 1180system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53796.280373 # average ReadReq mshr miss latency 1181system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10265.691176 # average UpgradeReq mshr miss latency 1182system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10265.691176 # average UpgradeReq mshr miss latency | 1148system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15129 # number of ReadReq MSHR misses 1149system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273814 # number of ReadReq MSHR misses 1150system.cpu.l2cache.ReadReq_mshr_misses::total 288943 # number of ReadReq MSHR misses 1151system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses 1152system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses 1153system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses 1154system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses 1155system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115362 # number of ReadExReq MSHR misses 1156system.cpu.l2cache.ReadExReq_mshr_misses::total 115362 # number of ReadExReq MSHR misses 1157system.cpu.l2cache.demand_mshr_misses::cpu.inst 15129 # number of demand (read+write) MSHR misses 1158system.cpu.l2cache.demand_mshr_misses::cpu.data 389176 # number of demand (read+write) MSHR misses 1159system.cpu.l2cache.demand_mshr_misses::total 404305 # number of demand (read+write) MSHR misses 1160system.cpu.l2cache.overall_mshr_misses::cpu.inst 15129 # number of overall MSHR misses 1161system.cpu.l2cache.overall_mshr_misses::cpu.data 389176 # number of overall MSHR misses 1162system.cpu.l2cache.overall_mshr_misses::total 404305 # number of overall MSHR misses 1163system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967311000 # number of ReadReq MSHR miss cycles 1164system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14580972250 # number of ReadReq MSHR miss cycles 1165system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15548283250 # number of ReadReq MSHR miss cycles 1166system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 493045 # number of UpgradeReq MSHR miss cycles 1167system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 493045 # number of UpgradeReq MSHR miss cycles 1168system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 50005 # number of SCUpgradeReq MSHR miss cycles 1169system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 50005 # number of SCUpgradeReq MSHR miss cycles 1170system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8286916389 # number of ReadExReq MSHR miss cycles 1171system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8286916389 # number of ReadExReq MSHR miss cycles 1172system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967311000 # number of demand (read+write) MSHR miss cycles 1173system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22867888639 # number of demand (read+write) MSHR miss cycles 1174system.cpu.l2cache.demand_mshr_miss_latency::total 23835199639 # number of demand (read+write) MSHR miss cycles 1175system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967311000 # number of overall MSHR miss cycles 1176system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22867888639 # number of overall MSHR miss cycles 1177system.cpu.l2cache.overall_mshr_miss_latency::total 23835199639 # number of overall MSHR miss cycles 1178system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333507000 # number of ReadReq MSHR uncacheable cycles 1179system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333507000 # number of ReadReq MSHR uncacheable cycles 1180system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884436000 # number of WriteReq MSHR uncacheable cycles 1181system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884436000 # number of WriteReq MSHR uncacheable cycles 1182system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217943000 # number of overall MSHR uncacheable cycles 1183system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217943000 # number of overall MSHR uncacheable cycles 1184system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for ReadReq accesses 1185system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248203 # mshr miss rate for ReadReq accesses 1186system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135006 # mshr miss rate for ReadReq accesses 1187system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.592593 # mshr miss rate for UpgradeReq accesses 1188system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.592593 # mshr miss rate for UpgradeReq accesses 1189system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.192308 # mshr miss rate for SCUpgradeReq accesses 1190system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.192308 # mshr miss rate for SCUpgradeReq accesses 1191system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382077 # mshr miss rate for ReadExReq accesses 1192system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382077 # mshr miss rate for ReadExReq accesses 1193system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for demand accesses 1194system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for demand accesses 1195system.cpu.l2cache.demand_mshr_miss_rate::total 0.165552 # mshr miss rate for demand accesses 1196system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for overall accesses 1197system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for overall accesses 1198system.cpu.l2cache.overall_mshr_miss_rate::total 0.165552 # mshr miss rate for overall accesses 1199system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63937.537180 # average ReadReq mshr miss latency 1200system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53251.375934 # average ReadReq mshr miss latency 1201system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53810.901285 # average ReadReq mshr miss latency 1202system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10271.770833 # average UpgradeReq mshr miss latency 1203system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10271.770833 # average UpgradeReq mshr miss latency |
| 1183system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1184system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 1204system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1205system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 1185system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71390.627955 # average ReadExReq mshr miss latency 1186system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71390.627955 # average ReadExReq mshr miss latency 1187system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63963.193022 # average overall mshr miss latency 1188system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58618.183562 # average overall mshr miss latency 1189system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58818.184126 # average overall mshr miss latency 1190system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63963.193022 # average overall mshr miss latency 1191system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58618.183562 # average overall mshr miss latency 1192system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58818.184126 # average overall mshr miss latency | 1206system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71834.021506 # average ReadExReq mshr miss latency 1207system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71834.021506 # average ReadExReq mshr miss latency 1208system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency 1209system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency 1210system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency 1211system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency 1212system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency 1213system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency |
| 1193system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1194system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1195system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1196system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1197system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1198system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1199system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1214system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1215system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1216system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1217system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1218system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1219system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1220system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1200system.cpu.dcache.tags.replacements 1406709 # number of replacements 1201system.cpu.dcache.tags.tagsinuse 511.994656 # Cycle average of tags in use 1202system.cpu.dcache.tags.total_refs 11889160 # Total number of references to valid blocks. 1203system.cpu.dcache.tags.sampled_refs 1407221 # Sample count of references to valid blocks. 1204system.cpu.dcache.tags.avg_refs 8.448680 # Average number of references to valid blocks. | 1221system.cpu.dcache.tags.replacements 1404516 # number of replacements 1222system.cpu.dcache.tags.tagsinuse 511.994651 # Cycle average of tags in use 1223system.cpu.dcache.tags.total_refs 11877087 # Total number of references to valid blocks. 1224system.cpu.dcache.tags.sampled_refs 1405028 # Sample count of references to valid blocks. 1225system.cpu.dcache.tags.avg_refs 8.453274 # Average number of references to valid blocks. |
| 1205system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. | 1226system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. |
| 1206system.cpu.dcache.tags.occ_blocks::cpu.data 511.994656 # Average occupied blocks per requestor | 1227system.cpu.dcache.tags.occ_blocks::cpu.data 511.994651 # Average occupied blocks per requestor |
| 1207system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 1208system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy 1209system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1210system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id | 1228system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy 1229system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy 1230system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1231system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id |
| 1211system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id 1212system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id | 1232system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id 1233system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id |
| 1213system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1234system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1214system.cpu.dcache.tags.tag_accesses 64006618 # Number of tag accesses 1215system.cpu.dcache.tags.data_accesses 64006618 # Number of data accesses 1216system.cpu.dcache.ReadReq_hits::cpu.data 7294645 # number of ReadReq hits 1217system.cpu.dcache.ReadReq_hits::total 7294645 # number of ReadReq hits 1218system.cpu.dcache.WriteReq_hits::cpu.data 4192085 # number of WriteReq hits 1219system.cpu.dcache.WriteReq_hits::total 4192085 # number of WriteReq hits 1220system.cpu.dcache.LoadLockedReq_hits::cpu.data 186406 # number of LoadLockedReq hits 1221system.cpu.dcache.LoadLockedReq_hits::total 186406 # number of LoadLockedReq hits 1222system.cpu.dcache.StoreCondReq_hits::cpu.data 215722 # number of StoreCondReq hits 1223system.cpu.dcache.StoreCondReq_hits::total 215722 # number of StoreCondReq hits 1224system.cpu.dcache.demand_hits::cpu.data 11486730 # number of demand (read+write) hits 1225system.cpu.dcache.demand_hits::total 11486730 # number of demand (read+write) hits 1226system.cpu.dcache.overall_hits::cpu.data 11486730 # number of overall hits 1227system.cpu.dcache.overall_hits::total 11486730 # number of overall hits 1228system.cpu.dcache.ReadReq_misses::cpu.data 1781450 # number of ReadReq misses 1229system.cpu.dcache.ReadReq_misses::total 1781450 # number of ReadReq misses 1230system.cpu.dcache.WriteReq_misses::cpu.data 1956078 # number of WriteReq misses 1231system.cpu.dcache.WriteReq_misses::total 1956078 # number of WriteReq misses 1232system.cpu.dcache.LoadLockedReq_misses::cpu.data 23435 # number of LoadLockedReq misses 1233system.cpu.dcache.LoadLockedReq_misses::total 23435 # number of LoadLockedReq misses 1234system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses 1235system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses 1236system.cpu.dcache.demand_misses::cpu.data 3737528 # number of demand (read+write) misses 1237system.cpu.dcache.demand_misses::total 3737528 # number of demand (read+write) misses 1238system.cpu.dcache.overall_misses::cpu.data 3737528 # number of overall misses 1239system.cpu.dcache.overall_misses::total 3737528 # number of overall misses 1240system.cpu.dcache.ReadReq_miss_latency::cpu.data 39460898751 # number of ReadReq miss cycles 1241system.cpu.dcache.ReadReq_miss_latency::total 39460898751 # number of ReadReq miss cycles 1242system.cpu.dcache.WriteReq_miss_latency::cpu.data 77926098572 # number of WriteReq miss cycles 1243system.cpu.dcache.WriteReq_miss_latency::total 77926098572 # number of WriteReq miss cycles 1244system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 366682499 # number of LoadLockedReq miss cycles 1245system.cpu.dcache.LoadLockedReq_miss_latency::total 366682499 # number of LoadLockedReq miss cycles 1246system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 440006 # number of StoreCondReq miss cycles 1247system.cpu.dcache.StoreCondReq_miss_latency::total 440006 # number of StoreCondReq miss cycles 1248system.cpu.dcache.demand_miss_latency::cpu.data 117386997323 # number of demand (read+write) miss cycles 1249system.cpu.dcache.demand_miss_latency::total 117386997323 # number of demand (read+write) miss cycles 1250system.cpu.dcache.overall_miss_latency::cpu.data 117386997323 # number of overall miss cycles 1251system.cpu.dcache.overall_miss_latency::total 117386997323 # number of overall miss cycles 1252system.cpu.dcache.ReadReq_accesses::cpu.data 9076095 # number of ReadReq accesses(hits+misses) 1253system.cpu.dcache.ReadReq_accesses::total 9076095 # number of ReadReq accesses(hits+misses) 1254system.cpu.dcache.WriteReq_accesses::cpu.data 6148163 # number of WriteReq accesses(hits+misses) 1255system.cpu.dcache.WriteReq_accesses::total 6148163 # number of WriteReq accesses(hits+misses) 1256system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209841 # number of LoadLockedReq accesses(hits+misses) 1257system.cpu.dcache.LoadLockedReq_accesses::total 209841 # number of LoadLockedReq accesses(hits+misses) 1258system.cpu.dcache.StoreCondReq_accesses::cpu.data 215750 # number of StoreCondReq accesses(hits+misses) 1259system.cpu.dcache.StoreCondReq_accesses::total 215750 # number of StoreCondReq accesses(hits+misses) 1260system.cpu.dcache.demand_accesses::cpu.data 15224258 # number of demand (read+write) accesses 1261system.cpu.dcache.demand_accesses::total 15224258 # number of demand (read+write) accesses 1262system.cpu.dcache.overall_accesses::cpu.data 15224258 # number of overall (read+write) accesses 1263system.cpu.dcache.overall_accesses::total 15224258 # number of overall (read+write) accesses 1264system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196279 # miss rate for ReadReq accesses 1265system.cpu.dcache.ReadReq_miss_rate::total 0.196279 # miss rate for ReadReq accesses 1266system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318156 # miss rate for WriteReq accesses 1267system.cpu.dcache.WriteReq_miss_rate::total 0.318156 # miss rate for WriteReq accesses 1268system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111680 # miss rate for LoadLockedReq accesses 1269system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111680 # miss rate for LoadLockedReq accesses 1270system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses 1271system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses 1272system.cpu.dcache.demand_miss_rate::cpu.data 0.245498 # miss rate for demand accesses 1273system.cpu.dcache.demand_miss_rate::total 0.245498 # miss rate for demand accesses 1274system.cpu.dcache.overall_miss_rate::cpu.data 0.245498 # miss rate for overall accesses 1275system.cpu.dcache.overall_miss_rate::total 0.245498 # miss rate for overall accesses 1276system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22150.999888 # average ReadReq miss latency 1277system.cpu.dcache.ReadReq_avg_miss_latency::total 22150.999888 # average ReadReq miss latency 1278system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39837.930068 # average WriteReq miss latency 1279system.cpu.dcache.WriteReq_avg_miss_latency::total 39837.930068 # average WriteReq miss latency 1280system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15646.788948 # average LoadLockedReq miss latency 1281system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15646.788948 # average LoadLockedReq miss latency 1282system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15714.500000 # average StoreCondReq miss latency 1283system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15714.500000 # average StoreCondReq miss latency 1284system.cpu.dcache.demand_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency 1285system.cpu.dcache.demand_avg_miss_latency::total 31407.656966 # average overall miss latency 1286system.cpu.dcache.overall_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency 1287system.cpu.dcache.overall_avg_miss_latency::total 31407.656966 # average overall miss latency 1288system.cpu.dcache.blocked_cycles::no_mshrs 3974317 # number of cycles access was blocked 1289system.cpu.dcache.blocked_cycles::no_targets 2076 # number of cycles access was blocked 1290system.cpu.dcache.blocked::no_mshrs 180350 # number of cycles access was blocked 1291system.cpu.dcache.blocked::no_targets 21 # number of cycles access was blocked 1292system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.036690 # average number of cycles each access was blocked 1293system.cpu.dcache.avg_blocked_cycles::no_targets 98.857143 # average number of cycles each access was blocked | 1235system.cpu.dcache.tags.tag_accesses 63934725 # Number of tag accesses 1236system.cpu.dcache.tags.data_accesses 63934725 # Number of data accesses 1237system.cpu.dcache.ReadReq_hits::cpu.data 7287009 # number of ReadReq hits 1238system.cpu.dcache.ReadReq_hits::total 7287009 # number of ReadReq hits 1239system.cpu.dcache.WriteReq_hits::cpu.data 4187789 # number of WriteReq hits 1240system.cpu.dcache.WriteReq_hits::total 4187789 # number of WriteReq hits 1241system.cpu.dcache.LoadLockedReq_hits::cpu.data 186297 # number of LoadLockedReq hits 1242system.cpu.dcache.LoadLockedReq_hits::total 186297 # number of LoadLockedReq hits 1243system.cpu.dcache.StoreCondReq_hits::cpu.data 215715 # number of StoreCondReq hits 1244system.cpu.dcache.StoreCondReq_hits::total 215715 # number of StoreCondReq hits 1245system.cpu.dcache.demand_hits::cpu.data 11474798 # number of demand (read+write) hits 1246system.cpu.dcache.demand_hits::total 11474798 # number of demand (read+write) hits 1247system.cpu.dcache.overall_hits::cpu.data 11474798 # number of overall hits 1248system.cpu.dcache.overall_hits::total 11474798 # number of overall hits 1249system.cpu.dcache.ReadReq_misses::cpu.data 1776849 # number of ReadReq misses 1250system.cpu.dcache.ReadReq_misses::total 1776849 # number of ReadReq misses 1251system.cpu.dcache.WriteReq_misses::cpu.data 1955456 # number of WriteReq misses 1252system.cpu.dcache.WriteReq_misses::total 1955456 # number of WriteReq misses 1253system.cpu.dcache.LoadLockedReq_misses::cpu.data 23283 # number of LoadLockedReq misses 1254system.cpu.dcache.LoadLockedReq_misses::total 23283 # number of LoadLockedReq misses 1255system.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses 1256system.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses 1257system.cpu.dcache.demand_misses::cpu.data 3732305 # number of demand (read+write) misses 1258system.cpu.dcache.demand_misses::total 3732305 # number of demand (read+write) misses 1259system.cpu.dcache.overall_misses::cpu.data 3732305 # number of overall misses 1260system.cpu.dcache.overall_misses::total 3732305 # number of overall misses 1261system.cpu.dcache.ReadReq_miss_latency::cpu.data 39503001495 # number of ReadReq miss cycles 1262system.cpu.dcache.ReadReq_miss_latency::total 39503001495 # number of ReadReq miss cycles 1263system.cpu.dcache.WriteReq_miss_latency::cpu.data 78159072008 # number of WriteReq miss cycles 1264system.cpu.dcache.WriteReq_miss_latency::total 78159072008 # number of WriteReq miss cycles 1265system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364867750 # number of LoadLockedReq miss cycles 1266system.cpu.dcache.LoadLockedReq_miss_latency::total 364867750 # number of LoadLockedReq miss cycles 1267system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 402005 # number of StoreCondReq miss cycles 1268system.cpu.dcache.StoreCondReq_miss_latency::total 402005 # number of StoreCondReq miss cycles 1269system.cpu.dcache.demand_miss_latency::cpu.data 117662073503 # number of demand (read+write) miss cycles 1270system.cpu.dcache.demand_miss_latency::total 117662073503 # number of demand (read+write) miss cycles 1271system.cpu.dcache.overall_miss_latency::cpu.data 117662073503 # number of overall miss cycles 1272system.cpu.dcache.overall_miss_latency::total 117662073503 # number of overall miss cycles 1273system.cpu.dcache.ReadReq_accesses::cpu.data 9063858 # number of ReadReq accesses(hits+misses) 1274system.cpu.dcache.ReadReq_accesses::total 9063858 # number of ReadReq accesses(hits+misses) 1275system.cpu.dcache.WriteReq_accesses::cpu.data 6143245 # number of WriteReq accesses(hits+misses) 1276system.cpu.dcache.WriteReq_accesses::total 6143245 # number of WriteReq accesses(hits+misses) 1277system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209580 # number of LoadLockedReq accesses(hits+misses) 1278system.cpu.dcache.LoadLockedReq_accesses::total 209580 # number of LoadLockedReq accesses(hits+misses) 1279system.cpu.dcache.StoreCondReq_accesses::cpu.data 215741 # number of StoreCondReq accesses(hits+misses) 1280system.cpu.dcache.StoreCondReq_accesses::total 215741 # number of StoreCondReq accesses(hits+misses) 1281system.cpu.dcache.demand_accesses::cpu.data 15207103 # number of demand (read+write) accesses 1282system.cpu.dcache.demand_accesses::total 15207103 # number of demand (read+write) accesses 1283system.cpu.dcache.overall_accesses::cpu.data 15207103 # number of overall (read+write) accesses 1284system.cpu.dcache.overall_accesses::total 15207103 # number of overall (read+write) accesses 1285system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196037 # miss rate for ReadReq accesses 1286system.cpu.dcache.ReadReq_miss_rate::total 0.196037 # miss rate for ReadReq accesses 1287system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318310 # miss rate for WriteReq accesses 1288system.cpu.dcache.WriteReq_miss_rate::total 0.318310 # miss rate for WriteReq accesses 1289system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111094 # miss rate for LoadLockedReq accesses 1290system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111094 # miss rate for LoadLockedReq accesses 1291system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses 1292system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses 1293system.cpu.dcache.demand_miss_rate::cpu.data 0.245432 # miss rate for demand accesses 1294system.cpu.dcache.demand_miss_rate::total 0.245432 # miss rate for demand accesses 1295system.cpu.dcache.overall_miss_rate::cpu.data 0.245432 # miss rate for overall accesses 1296system.cpu.dcache.overall_miss_rate::total 0.245432 # miss rate for overall accesses 1297system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22232.053199 # average ReadReq miss latency 1298system.cpu.dcache.ReadReq_avg_miss_latency::total 22232.053199 # average ReadReq miss latency 1299system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39969.742100 # average WriteReq miss latency 1300system.cpu.dcache.WriteReq_avg_miss_latency::total 39969.742100 # average WriteReq miss latency 1301system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15670.993858 # average LoadLockedReq miss latency 1302system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15670.993858 # average LoadLockedReq miss latency 1303system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15461.730769 # average StoreCondReq miss latency 1304system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15461.730769 # average StoreCondReq miss latency 1305system.cpu.dcache.demand_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency 1306system.cpu.dcache.demand_avg_miss_latency::total 31525.310365 # average overall miss latency 1307system.cpu.dcache.overall_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency 1308system.cpu.dcache.overall_avg_miss_latency::total 31525.310365 # average overall miss latency 1309system.cpu.dcache.blocked_cycles::no_mshrs 3999248 # number of cycles access was blocked 1310system.cpu.dcache.blocked_cycles::no_targets 1376 # number of cycles access was blocked 1311system.cpu.dcache.blocked::no_mshrs 180044 # number of cycles access was blocked 1312system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked 1313system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.212615 # average number of cycles each access was blocked 1314system.cpu.dcache.avg_blocked_cycles::no_targets 62.545455 # average number of cycles each access was blocked |
| 1294system.cpu.dcache.fast_writes 0 # number of fast writes performed 1295system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1315system.cpu.dcache.fast_writes 0 # number of fast writes performed 1316system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1296system.cpu.dcache.writebacks::writebacks 845214 # number of writebacks 1297system.cpu.dcache.writebacks::total 845214 # number of writebacks 1298system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683673 # number of ReadReq MSHR hits 1299system.cpu.dcache.ReadReq_mshr_hits::total 683673 # number of ReadReq MSHR hits 1300system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664672 # number of WriteReq MSHR hits 1301system.cpu.dcache.WriteReq_mshr_hits::total 1664672 # number of WriteReq MSHR hits 1302system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5215 # number of LoadLockedReq MSHR hits 1303system.cpu.dcache.LoadLockedReq_mshr_hits::total 5215 # number of LoadLockedReq MSHR hits 1304system.cpu.dcache.demand_mshr_hits::cpu.data 2348345 # number of demand (read+write) MSHR hits 1305system.cpu.dcache.demand_mshr_hits::total 2348345 # number of demand (read+write) MSHR hits 1306system.cpu.dcache.overall_mshr_hits::cpu.data 2348345 # number of overall MSHR hits 1307system.cpu.dcache.overall_mshr_hits::total 2348345 # number of overall MSHR hits 1308system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1097777 # number of ReadReq MSHR misses 1309system.cpu.dcache.ReadReq_mshr_misses::total 1097777 # number of ReadReq MSHR misses 1310system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291406 # number of WriteReq MSHR misses 1311system.cpu.dcache.WriteReq_mshr_misses::total 291406 # number of WriteReq MSHR misses 1312system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18220 # number of LoadLockedReq MSHR misses 1313system.cpu.dcache.LoadLockedReq_mshr_misses::total 18220 # number of LoadLockedReq MSHR misses 1314system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses 1315system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses 1316system.cpu.dcache.demand_mshr_misses::cpu.data 1389183 # number of demand (read+write) MSHR misses 1317system.cpu.dcache.demand_mshr_misses::total 1389183 # number of demand (read+write) MSHR misses 1318system.cpu.dcache.overall_mshr_misses::cpu.data 1389183 # number of overall MSHR misses 1319system.cpu.dcache.overall_mshr_misses::total 1389183 # number of overall MSHR misses 1320system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27531600277 # number of ReadReq MSHR miss cycles 1321system.cpu.dcache.ReadReq_mshr_miss_latency::total 27531600277 # number of ReadReq MSHR miss cycles 1322system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11750999106 # number of WriteReq MSHR miss cycles 1323system.cpu.dcache.WriteReq_mshr_miss_latency::total 11750999106 # number of WriteReq MSHR miss cycles 1324system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 207629251 # number of LoadLockedReq MSHR miss cycles 1325system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 207629251 # number of LoadLockedReq MSHR miss cycles 1326system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 383994 # number of StoreCondReq MSHR miss cycles 1327system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 383994 # number of StoreCondReq MSHR miss cycles 1328system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39282599383 # number of demand (read+write) MSHR miss cycles 1329system.cpu.dcache.demand_mshr_miss_latency::total 39282599383 # number of demand (read+write) MSHR miss cycles 1330system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39282599383 # number of overall MSHR miss cycles 1331system.cpu.dcache.overall_mshr_miss_latency::total 39282599383 # number of overall MSHR miss cycles 1332system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423287000 # number of ReadReq MSHR uncacheable cycles 1333system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423287000 # number of ReadReq MSHR uncacheable cycles 1334system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997974498 # number of WriteReq MSHR uncacheable cycles 1335system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997974498 # number of WriteReq MSHR uncacheable cycles 1336system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421261498 # number of overall MSHR uncacheable cycles 1337system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421261498 # number of overall MSHR uncacheable cycles 1338system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120953 # mshr miss rate for ReadReq accesses 1339system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120953 # mshr miss rate for ReadReq accesses 1340system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047397 # mshr miss rate for WriteReq accesses 1341system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047397 # mshr miss rate for WriteReq accesses 1342system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086828 # mshr miss rate for LoadLockedReq accesses 1343system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086828 # mshr miss rate for LoadLockedReq accesses 1344system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses 1345system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses 1346system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for demand accesses 1347system.cpu.dcache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses 1348system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for overall accesses 1349system.cpu.dcache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses 1350system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25079.410734 # average ReadReq mshr miss latency 1351system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25079.410734 # average ReadReq mshr miss latency 1352system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40325.178981 # average WriteReq mshr miss latency 1353system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40325.178981 # average WriteReq mshr miss latency 1354system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11395.677881 # average LoadLockedReq mshr miss latency 1355system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.677881 # average LoadLockedReq mshr miss latency 1356system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13714.071429 # average StoreCondReq mshr miss latency 1357system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13714.071429 # average StoreCondReq mshr miss latency 1358system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency 1359system.cpu.dcache.demand_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency 1360system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency 1361system.cpu.dcache.overall_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency | 1317system.cpu.dcache.writebacks::writebacks 842679 # number of writebacks 1318system.cpu.dcache.writebacks::total 842679 # number of writebacks 1319system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680758 # number of ReadReq MSHR hits 1320system.cpu.dcache.ReadReq_mshr_hits::total 680758 # number of ReadReq MSHR hits 1321system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664340 # number of WriteReq MSHR hits 1322system.cpu.dcache.WriteReq_mshr_hits::total 1664340 # number of WriteReq MSHR hits 1323system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5292 # number of LoadLockedReq MSHR hits 1324system.cpu.dcache.LoadLockedReq_mshr_hits::total 5292 # number of LoadLockedReq MSHR hits 1325system.cpu.dcache.demand_mshr_hits::cpu.data 2345098 # number of demand (read+write) MSHR hits 1326system.cpu.dcache.demand_mshr_hits::total 2345098 # number of demand (read+write) MSHR hits 1327system.cpu.dcache.overall_mshr_hits::cpu.data 2345098 # number of overall MSHR hits 1328system.cpu.dcache.overall_mshr_hits::total 2345098 # number of overall MSHR hits 1329system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096091 # number of ReadReq MSHR misses 1330system.cpu.dcache.ReadReq_mshr_misses::total 1096091 # number of ReadReq MSHR misses 1331system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291116 # number of WriteReq MSHR misses 1332system.cpu.dcache.WriteReq_mshr_misses::total 291116 # number of WriteReq MSHR misses 1333system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17991 # number of LoadLockedReq MSHR misses 1334system.cpu.dcache.LoadLockedReq_mshr_misses::total 17991 # number of LoadLockedReq MSHR misses 1335system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses 1336system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses 1337system.cpu.dcache.demand_mshr_misses::cpu.data 1387207 # number of demand (read+write) MSHR misses 1338system.cpu.dcache.demand_mshr_misses::total 1387207 # number of demand (read+write) MSHR misses 1339system.cpu.dcache.overall_mshr_misses::cpu.data 1387207 # number of overall MSHR misses 1340system.cpu.dcache.overall_mshr_misses::total 1387207 # number of overall MSHR misses 1341system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27515724784 # number of ReadReq MSHR miss cycles 1342system.cpu.dcache.ReadReq_mshr_miss_latency::total 27515724784 # number of ReadReq MSHR miss cycles 1343system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11792803134 # number of WriteReq MSHR miss cycles 1344system.cpu.dcache.WriteReq_mshr_miss_latency::total 11792803134 # number of WriteReq MSHR miss cycles 1345system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204517750 # number of LoadLockedReq MSHR miss cycles 1346system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204517750 # number of LoadLockedReq MSHR miss cycles 1347system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 349995 # number of StoreCondReq MSHR miss cycles 1348system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 349995 # number of StoreCondReq MSHR miss cycles 1349system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39308527918 # number of demand (read+write) MSHR miss cycles 1350system.cpu.dcache.demand_mshr_miss_latency::total 39308527918 # number of demand (read+write) MSHR miss cycles 1351system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39308527918 # number of overall MSHR miss cycles 1352system.cpu.dcache.overall_mshr_miss_latency::total 39308527918 # number of overall MSHR miss cycles 1353system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423597000 # number of ReadReq MSHR uncacheable cycles 1354system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423597000 # number of ReadReq MSHR uncacheable cycles 1355system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999614498 # number of WriteReq MSHR uncacheable cycles 1356system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999614498 # number of WriteReq MSHR uncacheable cycles 1357system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423211498 # number of overall MSHR uncacheable cycles 1358system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423211498 # number of overall MSHR uncacheable cycles 1359system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120930 # mshr miss rate for ReadReq accesses 1360system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120930 # mshr miss rate for ReadReq accesses 1361system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses 1362system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses 1363system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085843 # mshr miss rate for LoadLockedReq accesses 1364system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085843 # mshr miss rate for LoadLockedReq accesses 1365system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses 1366system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses 1367system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses 1368system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses 1369system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses 1370system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses 1371system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25103.503983 # average ReadReq mshr miss latency 1372system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25103.503983 # average ReadReq mshr miss latency 1373system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40508.948783 # average WriteReq mshr miss latency 1374system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40508.948783 # average WriteReq mshr miss latency 1375system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11367.781113 # average LoadLockedReq mshr miss latency 1376system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11367.781113 # average LoadLockedReq mshr miss latency 1377system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13461.346154 # average StoreCondReq mshr miss latency 1378system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13461.346154 # average StoreCondReq mshr miss latency 1379system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency 1380system.cpu.dcache.demand_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency 1381system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency 1382system.cpu.dcache.overall_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency |
| 1362system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1363system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1364system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1365system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1366system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1367system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1368system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1369system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1383system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1384system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1385system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1386system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1387system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1388system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1389system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1390system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1370system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed 1371system.cpu.kern.inst.hwrei 211008 # number of hwrei instructions executed 1372system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl | 1391system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed 1392system.cpu.kern.inst.hwrei 210986 # number of hwrei instructions executed 1393system.cpu.kern.ipl_count::0 74656 40.97% 40.97% # number of times we switched to this ipl |
| 1373system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl | 1394system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl |
| 1374system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1375system.cpu.kern.ipl_count::31 105564 57.93% 100.00% # number of times we switched to this ipl 1376system.cpu.kern.ipl_count::total 182238 # number of times we switched to this ipl 1377system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 1395system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl 1396system.cpu.kern.ipl_count::31 105550 57.93% 100.00% # number of times we switched to this ipl 1397system.cpu.kern.ipl_count::total 182216 # number of times we switched to this ipl 1398system.cpu.kern.ipl_good::0 73289 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 1378system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl | 1399system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl |
| 1379system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1380system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1381system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl 1382system.cpu.kern.ipl_ticks::0 1818262027500 97.76% 97.76% # number of cycles we spent at this ipl 1383system.cpu.kern.ipl_ticks::21 61927000 0.00% 97.76% # number of cycles we spent at this ipl 1384system.cpu.kern.ipl_ticks::22 526143500 0.03% 97.79% # number of cycles we spent at this ipl 1385system.cpu.kern.ipl_ticks::31 41157993000 2.21% 100.00% # number of cycles we spent at this ipl 1386system.cpu.kern.ipl_ticks::total 1860008091000 # number of cycles we spent at this ipl 1387system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl | 1400system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl 1401system.cpu.kern.ipl_good::31 73289 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1402system.cpu.kern.ipl_good::total 148588 # number of times we switched to this ipl from a different ipl 1403system.cpu.kern.ipl_ticks::0 1817327743500 97.76% 97.76% # number of cycles we spent at this ipl 1404system.cpu.kern.ipl_ticks::21 61881000 0.00% 97.76% # number of cycles we spent at this ipl 1405system.cpu.kern.ipl_ticks::22 521765000 0.03% 97.79% # number of cycles we spent at this ipl 1406system.cpu.kern.ipl_ticks::31 41126450000 2.21% 100.00% # number of cycles we spent at this ipl 1407system.cpu.kern.ipl_ticks::total 1859037839500 # number of cycles we spent at this ipl 1408system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl |
| 1388system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1389system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 1409system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1410system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 1390system.cpu.kern.ipl_used::31 0.694328 # fraction of swpipl calls that actually changed the ipl 1391system.cpu.kern.ipl_used::total 0.815434 # fraction of swpipl calls that actually changed the ipl | 1411system.cpu.kern.ipl_used::31 0.694353 # fraction of swpipl calls that actually changed the ipl 1412system.cpu.kern.ipl_used::total 0.815450 # fraction of swpipl calls that actually changed the ipl |
| 1392system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1393system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1394system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1395system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1396system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1397system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1398system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1399system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 1419system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 1420system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 1421system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 1422system.cpu.kern.syscall::total 326 # number of syscalls executed 1423system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1424system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1425system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1426system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 1413system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1414system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1415system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1416system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1417system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1418system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1419system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1420system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 1440system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 1441system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 1442system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 1443system.cpu.kern.syscall::total 326 # number of syscalls executed 1444system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1445system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1446system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1447system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 1427system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed | 1448system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed |
| 1428system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1429system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed | 1449system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1450system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed |
| 1430system.cpu.kern.callpal::swpipl 175121 91.22% 93.43% # number of callpals executed 1431system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed | 1451system.cpu.kern.callpal::swpipl 175101 91.22% 93.43% # number of callpals executed 1452system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed |
| 1432system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1433system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1434system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1435system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed | 1453system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1454system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1455system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1456system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed |
| 1436system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed | 1457system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed |
| 1437system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1438system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 1458system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1459system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 1439system.cpu.kern.callpal::total 191967 # number of callpals executed 1440system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches | 1460system.cpu.kern.callpal::total 191946 # number of callpals executed 1461system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches |
| 1441system.cpu.kern.mode_switch::user 1740 # number of protection mode switches | 1462system.cpu.kern.mode_switch::user 1740 # number of protection mode switches |
| 1442system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches | 1463system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches |
| 1443system.cpu.kern.mode_good::kernel 1910 1444system.cpu.kern.mode_good::user 1740 1445system.cpu.kern.mode_good::idle 170 | 1464system.cpu.kern.mode_good::kernel 1910 1465system.cpu.kern.mode_good::user 1740 1466system.cpu.kern.mode_good::idle 170 |
| 1446system.cpu.kern.mode_switch_good::kernel 0.326496 # fraction of useful protection mode switches | 1467system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches |
| 1447system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1468system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1448system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches | 1469system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches |
| 1449system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches | 1470system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches |
| 1450system.cpu.kern.mode_ticks::kernel 29080060000 1.56% 1.56% # number of ticks spent at the given mode 1451system.cpu.kern.mode_ticks::user 2655672500 0.14% 1.71% # number of ticks spent at the given mode 1452system.cpu.kern.mode_ticks::idle 1828272350500 98.29% 100.00% # number of ticks spent at the given mode 1453system.cpu.kern.swap_context 4178 # number of times the context was actually changed | 1471system.cpu.kern.mode_ticks::kernel 29097785000 1.57% 1.57% # number of ticks spent at the given mode 1472system.cpu.kern.mode_ticks::user 2655967500 0.14% 1.71% # number of ticks spent at the given mode 1473system.cpu.kern.mode_ticks::idle 1827284079000 98.29% 100.00% # number of ticks spent at the given mode 1474system.cpu.kern.swap_context 4179 # number of times the context was actually changed |
| 1454 1455---------- End Simulation Statistics ---------- | 1475 1476---------- End Simulation Statistics ---------- |