| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.860192 # Number of seconds simulated 4sim_ticks 1860191785500 # Number of ticks simulated 5final_tick 1860191785500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.860188 # Number of seconds simulated 4sim_ticks 1860187818000 # Number of ticks simulated 5final_tick 1860187818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 128947 # Simulator instruction rate (inst/s) 8host_op_rate 128947 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4527634915 # Simulator tick rate (ticks/s) 10host_mem_usage 347764 # Number of bytes of host memory used 11host_seconds 410.85 # Real time elapsed on the host 12sim_insts 52978349 # Number of instructions simulated 13sim_ops 52978349 # Number of ops (including micro ops) simulated | 7host_inst_rate 129673 # Simulator instruction rate (inst/s) 8host_op_rate 129673 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4553007725 # Simulator tick rate (ticks/s) 10host_mem_usage 348812 # Number of bytes of host memory used 11host_seconds 408.56 # Real time elapsed on the host 12sim_insts 52979638 # Number of instructions simulated 13sim_ops 52979638 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 963264 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 963200 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24881344 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 28492800 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 963264 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 963264 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 15051 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 28496832 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 963200 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 963200 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7516608 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7516608 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 15050 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388771 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::total 445200 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 517830 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13373486 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 1425814 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 15317130 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 517830 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 517830 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4040117 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4040117 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4040117 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 517830 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13373486 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 1425814 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 19357247 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 445200 # Number of read requests accepted 44system.physmem.writeReqs 117428 # Number of write requests accepted 45system.physmem.readBursts 445200 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 117428 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 28485504 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7513728 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 28492800 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7515392 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue | 27system.physmem.num_reads::total 445263 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 117447 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 117447 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 517797 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 13375716 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 1425817 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 15319331 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 517797 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 517797 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4040779 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4040779 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4040779 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 517797 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 13375716 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 1425817 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 19360110 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 445263 # Number of read requests accepted 44system.physmem.writeReqs 117447 # Number of write requests accepted 45system.physmem.readBursts 445263 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 117447 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 28490624 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7515520 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 28496832 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7516608 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue |
| 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 54system.physmem.neitherReadNorWriteReqs 178 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 28210 # Per bank write bursts 56system.physmem.perBankRdBursts::1 27995 # Per bank write bursts 57system.physmem.perBankRdBursts::2 28357 # Per bank write bursts 58system.physmem.perBankRdBursts::3 27829 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27761 # Per bank write bursts 60system.physmem.perBankRdBursts::5 27267 # Per bank write bursts 61system.physmem.perBankRdBursts::6 27371 # Per bank write bursts 62system.physmem.perBankRdBursts::7 27375 # Per bank write bursts 63system.physmem.perBankRdBursts::8 27696 # Per bank write bursts 64system.physmem.perBankRdBursts::9 27269 # Per bank write bursts 65system.physmem.perBankRdBursts::10 28017 # Per bank write bursts | 54system.physmem.neitherReadNorWriteReqs 171 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 28211 # Per bank write bursts 56system.physmem.perBankRdBursts::1 27992 # Per bank write bursts 57system.physmem.perBankRdBursts::2 28433 # Per bank write bursts 58system.physmem.perBankRdBursts::3 27987 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27796 # Per bank write bursts 60system.physmem.perBankRdBursts::5 27217 # Per bank write bursts 61system.physmem.perBankRdBursts::6 27269 # Per bank write bursts 62system.physmem.perBankRdBursts::7 27319 # Per bank write bursts 63system.physmem.perBankRdBursts::8 27690 # Per bank write bursts 64system.physmem.perBankRdBursts::9 27272 # Per bank write bursts 65system.physmem.perBankRdBursts::10 28021 # Per bank write bursts |
| 66system.physmem.perBankRdBursts::11 27509 # Per bank write bursts | 66system.physmem.perBankRdBursts::11 27509 # Per bank write bursts |
| 67system.physmem.perBankRdBursts::12 27546 # Per bank write bursts 68system.physmem.perBankRdBursts::13 28232 # Per bank write bursts 69system.physmem.perBankRdBursts::14 28342 # Per bank write bursts 70system.physmem.perBankRdBursts::15 28310 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7920 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7516 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7873 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7373 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7309 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6720 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6881 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6774 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7136 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6679 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7411 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6967 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7107 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7877 # Per bank write bursts 85system.physmem.perBankWrBursts::14 8064 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7795 # Per bank write bursts | 67system.physmem.perBankRdBursts::12 27548 # Per bank write bursts 68system.physmem.perBankRdBursts::13 28237 # Per bank write bursts 69system.physmem.perBankRdBursts::14 28335 # Per bank write bursts 70system.physmem.perBankRdBursts::15 28330 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7921 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7511 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7946 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7492 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7346 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6678 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6778 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6711 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7130 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6681 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7414 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6966 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7109 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7879 # Per bank write bursts 85system.physmem.perBankWrBursts::14 8056 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7812 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 88system.physmem.numWrRetry 10 # Number of times write queue was full causing retry 89system.physmem.totGap 1860186344000 # Total gap between requests | 88system.physmem.numWrRetry 11 # Number of times write queue was full causing retry 89system.physmem.totGap 1860182401000 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 445200 # Read request sizes (log2) | 96system.physmem.readPktSize::6 445263 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 117428 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 322906 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 56729 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 22897 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 5869 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1157 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 4278 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 3757 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 3842 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3993 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 2551 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 2136 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2038 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1891 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1835 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1567 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 1541 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 1538 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 1552 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 1725 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 1258 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 117447 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 316668 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 59729 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 27667 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 5430 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 2043 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 4389 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 3993 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 3992 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 2540 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 2192 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2086 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1617 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1588 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1906 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 1882 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 2139 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 1226 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 986 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 905 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see |
| 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 765 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 934 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 2202 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 3347 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4688 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4756 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4816 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4872 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5562 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5401 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5474 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6284 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 6230 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6245 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5759 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 3432 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 2435 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 1613 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 1063 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 1141 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 1099 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1072 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 1163 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1289 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1446 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1531 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1699 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1801 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 1872 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 1823 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 1946 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1928 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1837 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1841 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 1726 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 1489 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 1270 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 915 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 647 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 300 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 48603 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 651.388927 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 428.580055 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 419.495686 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 8350 17.18% 17.18% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 6347 13.06% 30.24% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 2940 6.05% 36.29% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1813 3.73% 40.02% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1501 3.09% 43.11% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 899 1.85% 44.96% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 723 1.49% 46.44% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 886 1.82% 48.27% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 25144 51.73% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 48603 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 6893 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 64.568403 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2543.170744 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 6890 99.96% 99.96% # Reads before turning the bus around for writes | 151system.physmem.wrQLenPdf::15 1100 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1131 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 2272 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 3501 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 4229 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4755 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4765 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4891 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5082 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 5274 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5526 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5836 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 6245 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6873 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 6071 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6268 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6172 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5967 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 924 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 916 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 938 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 867 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 935 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 954 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 998 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1187 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1236 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1182 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1234 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1359 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 1592 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 1859 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 2023 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1831 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1802 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1695 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 1731 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 1643 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 821 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 354 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 206 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 137 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 30 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 63749 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 564.805095 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 351.189585 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 419.649920 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 13350 20.94% 20.94% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 10335 16.21% 37.15% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4789 7.51% 44.67% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 2797 4.39% 49.05% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2437 3.82% 52.88% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1576 2.47% 55.35% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1469 2.30% 57.65% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1613 2.53% 60.18% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 25383 39.82% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 63749 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 6887 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 64.637723 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 16.523346 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2544.314640 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 6884 99.96% 99.96% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes | 219system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::total 6893 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 6893 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 17.032062 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 16.789521 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 3.768510 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16 5850 84.87% 84.87% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::17 28 0.41% 85.27% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::18 70 1.02% 86.29% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::19 418 6.06% 92.35% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20 134 1.94% 94.30% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::21 49 0.71% 95.01% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::22 24 0.35% 95.36% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::23 22 0.32% 95.68% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24 53 0.77% 96.45% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::25 38 0.55% 97.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::26 20 0.29% 97.29% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::27 34 0.49% 97.78% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28 19 0.28% 98.06% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::29 34 0.49% 98.55% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::30 7 0.10% 98.65% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::31 10 0.15% 98.80% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32 2 0.03% 98.82% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::34 2 0.03% 98.85% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::35 3 0.04% 98.90% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::36 6 0.09% 98.98% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::37 5 0.07% 99.06% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::38 5 0.07% 99.13% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::39 8 0.12% 99.25% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::40 4 0.06% 99.30% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::41 2 0.03% 99.33% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::43 1 0.01% 99.35% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::44 2 0.03% 99.38% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::45 5 0.07% 99.45% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::46 2 0.03% 99.48% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::47 6 0.09% 99.56% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::48 6 0.09% 99.65% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::49 4 0.06% 99.71% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::50 2 0.03% 99.74% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::51 1 0.01% 99.75% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::52 2 0.03% 99.78% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::53 2 0.03% 99.81% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::54 3 0.04% 99.85% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::55 1 0.01% 99.87% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::56 6 0.09% 99.96% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::57 1 0.01% 99.97% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::58 2 0.03% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 6893 # Writes before turning the bus around for reads 268system.physmem.totQLat 10196532000 # Total ticks spent queuing 269system.physmem.totMemAccLat 17805650750 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 2225430000 # Total ticks spent in databus transfers 271system.physmem.totBankLat 5383688750 # Total ticks spent accessing banks 272system.physmem.avgQLat 22909.13 # Average queueing delay per DRAM burst 273system.physmem.avgBankLat 12095.84 # Average bank access latency per DRAM burst | 222system.physmem.rdPerTurnAround::total 6887 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 6887 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 17.050966 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 16.814496 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 3.834643 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16 5493 79.76% 79.76% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::17 28 0.41% 80.17% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::18 690 10.02% 90.18% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::19 216 3.14% 93.32% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::20 116 1.68% 95.01% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::21 20 0.29% 95.30% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::22 25 0.36% 95.66% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::23 93 1.35% 97.01% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::24 19 0.28% 97.28% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::25 44 0.64% 97.92% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::26 11 0.16% 98.08% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::27 7 0.10% 98.18% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28 8 0.12% 98.30% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::29 16 0.23% 98.53% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::30 2 0.03% 98.56% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::31 14 0.20% 98.77% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::32 9 0.13% 98.90% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::33 1 0.01% 98.91% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::34 1 0.01% 98.93% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::35 3 0.04% 98.97% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::36 2 0.03% 99.00% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::37 1 0.01% 99.01% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::38 1 0.01% 99.03% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::39 2 0.03% 99.06% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::40 7 0.10% 99.16% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::41 4 0.06% 99.22% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::42 2 0.03% 99.24% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::43 3 0.04% 99.29% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::44 1 0.01% 99.30% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::45 4 0.06% 99.36% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::46 3 0.04% 99.40% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::47 3 0.04% 99.45% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::48 7 0.10% 99.55% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::50 4 0.06% 99.61% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::51 1 0.01% 99.62% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::53 1 0.01% 99.64% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::54 1 0.01% 99.65% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::56 7 0.10% 99.75% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::57 17 0.25% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::total 6887 # Writes before turning the bus around for reads 267system.physmem.totQLat 8647566500 # Total ticks spent queuing 268system.physmem.totMemAccLat 16994429000 # Total ticks spent from burst creation until serviced by the DRAM 269system.physmem.totBusLat 2225830000 # Total ticks spent in databus transfers 270system.physmem.avgQLat 19425.49 # Average queueing delay per DRAM burst |
| 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 275system.physmem.avgMemAccLat 40004.97 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 15.31 # Average DRAM read bandwidth in MiByte/s | 272system.physmem.avgMemAccLat 38175.49 # Average memory access latency per DRAM burst 273system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s |
| 277system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 281system.physmem.busUtil 0.15 # Data bus utilization in percentage 282system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 283system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 274system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s 275system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s 276system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s 277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 278system.physmem.busUtil 0.15 # Data bus utilization in percentage 279system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 280system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 284system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing 285system.physmem.avgWrQLen 26.57 # Average write queue length when enqueuing 286system.physmem.readRowHits 402462 # Number of row buffer hits during reads 287system.physmem.writeRowHits 96189 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 81.91 # Row buffer hit rate for writes 290system.physmem.avgGap 3306245.59 # Average gap between requests 291system.physmem.pageHitRate 88.65 # Row buffer hit rate, read and write combined 292system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state 293system.membus.throughput 19400105 # Throughput (bytes/s) 294system.membus.trans_dist::ReadReq 295926 # Transaction distribution 295system.membus.trans_dist::ReadResp 295846 # Transaction distribution | 281system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing 282system.physmem.avgWrQLen 26.02 # Average write queue length when enqueuing 283system.physmem.readRowHits 403062 # Number of row buffer hits during reads 284system.physmem.writeRowHits 95784 # Number of row buffer hits during writes 285system.physmem.readRowHitRate 90.54 # Row buffer hit rate for reads 286system.physmem.writeRowHitRate 81.56 # Row buffer hit rate for writes 287system.physmem.avgGap 3305756.79 # Average gap between requests 288system.physmem.pageHitRate 88.67 # Row buffer hit rate, read and write combined 289system.physmem.memoryStateTime::IDLE 1761433244000 # Time in different power states 290system.physmem.memoryStateTime::REF 62115560000 # Time in different power states 291system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 292system.physmem.memoryStateTime::ACT 36633312250 # Time in different power states 293system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 294system.membus.throughput 19402968 # Throughput (bytes/s) 295system.membus.trans_dist::ReadReq 295944 # Transaction distribution 296system.membus.trans_dist::ReadResp 295866 # Transaction distribution |
| 296system.membus.trans_dist::WriteReq 9597 # Transaction distribution 297system.membus.trans_dist::WriteResp 9597 # Transaction distribution | 297system.membus.trans_dist::WriteReq 9597 # Transaction distribution 298system.membus.trans_dist::WriteResp 9597 # Transaction distribution |
| 298system.membus.trans_dist::Writeback 117428 # Transaction distribution 299system.membus.trans_dist::UpgradeReq 181 # Transaction distribution 300system.membus.trans_dist::UpgradeResp 181 # Transaction distribution 301system.membus.trans_dist::ReadExReq 156840 # Transaction distribution 302system.membus.trans_dist::ReadExResp 156840 # Transaction distribution 303system.membus.trans_dist::BadAddressError 80 # Transaction distribution | 299system.membus.trans_dist::Writeback 117447 # Transaction distribution 300system.membus.trans_dist::UpgradeReq 174 # Transaction distribution 301system.membus.trans_dist::UpgradeResp 174 # Transaction distribution 302system.membus.trans_dist::ReadExReq 156883 # Transaction distribution 303system.membus.trans_dist::ReadExResp 156883 # Transaction distribution 304system.membus.trans_dist::BadAddressError 78 # Transaction distribution |
| 304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) | 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) |
| 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884064 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917278 # Packet count per connected master and slave (bytes) | 306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884195 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes) |
| 308system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) | 309system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) 310system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) |
| 310system.membus.pkt_count::total 1041957 # Packet count per connected master and slave (bytes) | 311system.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes) |
| 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) | 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) |
| 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699136 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30743276 # Cumulative packet size per connected master and slave (bytes) | 313system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704384 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748524 # Cumulative packet size per connected master and slave (bytes) |
| 314system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) | 315system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) 316system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) |
| 316system.membus.tot_pkt_size::total 36052332 # Cumulative packet size per connected master and slave (bytes) 317system.membus.data_through_bus 36052332 # Total data (bytes) | 317system.membus.tot_pkt_size::total 36057580 # Cumulative packet size per connected master and slave (bytes) 318system.membus.data_through_bus 36057580 # Total data (bytes) |
| 318system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) | 319system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) |
| 319system.membus.reqLayer0.occupancy 29929000 # Layer occupancy (ticks) | 320system.membus.reqLayer0.occupancy 29864500 # Layer occupancy (ticks) |
| 320system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 321system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 321system.membus.reqLayer1.occupancy 1552530249 # Layer occupancy (ticks) | 322system.membus.reqLayer1.occupancy 1548275500 # Layer occupancy (ticks) |
| 322system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 323system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 323system.membus.reqLayer2.occupancy 100500 # Layer occupancy (ticks) | 324system.membus.reqLayer2.occupancy 98000 # Layer occupancy (ticks) |
| 324system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 325system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 325system.membus.respLayer1.occupancy 3767548549 # Layer occupancy (ticks) | 326system.membus.respLayer1.occupancy 3770327047 # Layer occupancy (ticks) |
| 326system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 327system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 327system.membus.respLayer2.occupancy 376726994 # Layer occupancy (ticks) | 328system.membus.respLayer2.occupancy 376611244 # Layer occupancy (ticks) |
| 328system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 329system.iocache.tags.replacements 41685 # number of replacements | 329system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 330system.iocache.tags.replacements 41685 # number of replacements |
| 330system.iocache.tags.tagsinuse 1.261130 # Cycle average of tags in use | 331system.iocache.tags.tagsinuse 1.261115 # Cycle average of tags in use |
| 331system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 332system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 333system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 332system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 333system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 334system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 334system.iocache.tags.warmup_cycle 1710337661000 # Cycle when the warmup percentage was hit. 335system.iocache.tags.occ_blocks::tsunami.ide 1.261130 # Average occupied blocks per requestor 336system.iocache.tags.occ_percent::tsunami.ide 0.078821 # Average percentage of cache occupancy 337system.iocache.tags.occ_percent::total 0.078821 # Average percentage of cache occupancy | 335system.iocache.tags.warmup_cycle 1710335896000 # Cycle when the warmup percentage was hit. 336system.iocache.tags.occ_blocks::tsunami.ide 1.261115 # Average occupied blocks per requestor 337system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy 338system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy |
| 338system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 339system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 340system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 341system.iocache.tags.tag_accesses 375525 # Number of tag accesses 342system.iocache.tags.data_accesses 375525 # Number of data accesses 343system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 344system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 345system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 346system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 347system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 348system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 349system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 350system.iocache.overall_misses::total 41725 # number of overall misses | 339system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 340system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 341system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 342system.iocache.tags.tag_accesses 375525 # Number of tag accesses 343system.iocache.tags.data_accesses 375525 # Number of data accesses 344system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 345system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 346system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 347system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 348system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 349system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 350system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 351system.iocache.overall_misses::total 41725 # number of overall misses |
| 351system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles 352system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles 353system.iocache.WriteReq_miss_latency::tsunami.ide 13194182648 # number of WriteReq miss cycles 354system.iocache.WriteReq_miss_latency::total 13194182648 # number of WriteReq miss cycles 355system.iocache.demand_miss_latency::tsunami.ide 13215316531 # number of demand (read+write) miss cycles 356system.iocache.demand_miss_latency::total 13215316531 # number of demand (read+write) miss cycles 357system.iocache.overall_miss_latency::tsunami.ide 13215316531 # number of overall miss cycles 358system.iocache.overall_miss_latency::total 13215316531 # number of overall miss cycles | 352system.iocache.ReadReq_miss_latency::tsunami.ide 21272883 # number of ReadReq miss cycles 353system.iocache.ReadReq_miss_latency::total 21272883 # number of ReadReq miss cycles 354system.iocache.WriteReq_miss_latency::tsunami.ide 12456693929 # number of WriteReq miss cycles 355system.iocache.WriteReq_miss_latency::total 12456693929 # number of WriteReq miss cycles 356system.iocache.demand_miss_latency::tsunami.ide 12477966812 # number of demand (read+write) miss cycles 357system.iocache.demand_miss_latency::total 12477966812 # number of demand (read+write) miss cycles 358system.iocache.overall_miss_latency::tsunami.ide 12477966812 # number of overall miss cycles 359system.iocache.overall_miss_latency::total 12477966812 # number of overall miss cycles |
| 359system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 360system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 361system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 362system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 363system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 364system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 365system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 366system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 367system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 368system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 369system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 370system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 371system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 372system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 373system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 374system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 360system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 361system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 362system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 363system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 364system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 365system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 366system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 367system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 368system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 369system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 370system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 371system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 372system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 373system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 374system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 375system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 375system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency 376system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency 377system.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774 # average WriteReq miss latency 378system.iocache.WriteReq_avg_miss_latency::total 317534.237774 # average WriteReq miss latency 379system.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency 380system.iocache.demand_avg_miss_latency::total 316724.182888 # average overall miss latency 381system.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency 382system.iocache.overall_avg_miss_latency::total 316724.182888 # average overall miss latency 383system.iocache.blocked_cycles::no_mshrs 393531 # number of cycles access was blocked | 376system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618 # average ReadReq miss latency 377system.iocache.ReadReq_avg_miss_latency::total 122964.641618 # average ReadReq miss latency 378system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445 # average WriteReq miss latency 379system.iocache.WriteReq_avg_miss_latency::total 299785.664445 # average WriteReq miss latency 380system.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency 381system.iocache.demand_avg_miss_latency::total 299052.529946 # average overall miss latency 382system.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency 383system.iocache.overall_avg_miss_latency::total 299052.529946 # average overall miss latency 384system.iocache.blocked_cycles::no_mshrs 365915 # number of cycles access was blocked |
| 384system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 385system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 385system.iocache.blocked::no_mshrs 28535 # number of cycles access was blocked | 386system.iocache.blocked::no_mshrs 28370 # number of cycles access was blocked |
| 386system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 387system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 387system.iocache.avg_blocked_cycles::no_mshrs 13.791169 # average number of cycles each access was blocked | 388system.iocache.avg_blocked_cycles::no_mshrs 12.897956 # average number of cycles each access was blocked |
| 388system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 389system.iocache.fast_writes 0 # number of fast writes performed 390system.iocache.cache_copies 0 # number of cache copies performed 391system.iocache.writebacks::writebacks 41512 # number of writebacks 392system.iocache.writebacks::total 41512 # number of writebacks 393system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 394system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 395system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 396system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 397system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 398system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 399system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 400system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 389system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 390system.iocache.fast_writes 0 # number of fast writes performed 391system.iocache.cache_copies 0 # number of cache copies performed 392system.iocache.writebacks::writebacks 41512 # number of writebacks 393system.iocache.writebacks::total 41512 # number of writebacks 394system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 395system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 396system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 397system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 398system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 399system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 400system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 401system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 401system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles 402system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles 403system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11031075660 # number of WriteReq MSHR miss cycles 404system.iocache.WriteReq_mshr_miss_latency::total 11031075660 # number of WriteReq MSHR miss cycles 405system.iocache.demand_mshr_miss_latency::tsunami.ide 11043212543 # number of demand (read+write) MSHR miss cycles 406system.iocache.demand_mshr_miss_latency::total 11043212543 # number of demand (read+write) MSHR miss cycles 407system.iocache.overall_mshr_miss_latency::tsunami.ide 11043212543 # number of overall MSHR miss cycles 408system.iocache.overall_mshr_miss_latency::total 11043212543 # number of overall MSHR miss cycles | 402system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12274883 # number of ReadReq MSHR miss cycles 403system.iocache.ReadReq_mshr_miss_latency::total 12274883 # number of ReadReq MSHR miss cycles 404system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10293819441 # number of WriteReq MSHR miss cycles 405system.iocache.WriteReq_mshr_miss_latency::total 10293819441 # number of WriteReq MSHR miss cycles 406system.iocache.demand_mshr_miss_latency::tsunami.ide 10306094324 # number of demand (read+write) MSHR miss cycles 407system.iocache.demand_mshr_miss_latency::total 10306094324 # number of demand (read+write) MSHR miss cycles 408system.iocache.overall_mshr_miss_latency::tsunami.ide 10306094324 # number of overall MSHR miss cycles 409system.iocache.overall_mshr_miss_latency::total 10306094324 # number of overall MSHR miss cycles |
| 409system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 410system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 411system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 412system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 413system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 414system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 415system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 416system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 410system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 411system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 412system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 413system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 414system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 415system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 416system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 417system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 417system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency 418system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency 419system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912 # average WriteReq mshr miss latency 420system.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912 # average WriteReq mshr miss latency 421system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency 422system.iocache.demand_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency 423system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency 424system.iocache.overall_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency | 418system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925 # average ReadReq mshr miss latency 419system.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925 # average ReadReq mshr miss latency 420system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981 # average WriteReq mshr miss latency 421system.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981 # average WriteReq mshr miss latency 422system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency 423system.iocache.demand_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency 424system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency 425system.iocache.overall_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency |
| 425system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 426system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 427system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 428system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 429system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 430system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 431system.disk0.dma_write_txs 395 # Number of DMA write transactions. 432system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 433system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 434system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 435system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 436system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 437system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 426system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 427system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 428system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 429system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 430system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 431system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 432system.disk0.dma_write_txs 395 # Number of DMA write transactions. 433system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 434system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 435system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 436system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 437system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 438system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 438system.cpu.branchPred.lookups 13847711 # Number of BP lookups 439system.cpu.branchPred.condPredicted 11622265 # Number of conditional branches predicted 440system.cpu.branchPred.condIncorrect 397151 # Number of conditional branches incorrect 441system.cpu.branchPred.BTBLookups 9355929 # Number of BTB lookups 442system.cpu.branchPred.BTBHits 5809145 # Number of BTB hits | 439system.cpu.branchPred.lookups 13846630 # Number of BP lookups 440system.cpu.branchPred.condPredicted 11622667 # Number of conditional branches predicted 441system.cpu.branchPred.condIncorrect 398238 # Number of conditional branches incorrect 442system.cpu.branchPred.BTBLookups 9513264 # Number of BTB lookups 443system.cpu.branchPred.BTBHits 5817388 # Number of BTB hits |
| 443system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 444system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 444system.cpu.branchPred.BTBHitPct 62.090520 # BTB Hit Percentage 445system.cpu.branchPred.usedRAS 903416 # Number of times the RAS was used to get a target. 446system.cpu.branchPred.RASInCorrect 38861 # Number of incorrect RAS predictions. | 445system.cpu.branchPred.BTBHitPct 61.150284 # BTB Hit Percentage 446system.cpu.branchPred.usedRAS 900921 # Number of times the RAS was used to get a target. 447system.cpu.branchPred.RASInCorrect 39034 # Number of incorrect RAS predictions. |
| 447system.cpu_clk_domain.clock 500 # Clock period in ticks 448system.cpu.dtb.fetch_hits 0 # ITB hits 449system.cpu.dtb.fetch_misses 0 # ITB misses 450system.cpu.dtb.fetch_acv 0 # ITB acv 451system.cpu.dtb.fetch_accesses 0 # ITB accesses | 448system.cpu_clk_domain.clock 500 # Clock period in ticks 449system.cpu.dtb.fetch_hits 0 # ITB hits 450system.cpu.dtb.fetch_misses 0 # ITB misses 451system.cpu.dtb.fetch_acv 0 # ITB acv 452system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 452system.cpu.dtb.read_hits 9926060 # DTB read hits 453system.cpu.dtb.read_misses 41229 # DTB read misses 454system.cpu.dtb.read_acv 545 # DTB read access violations 455system.cpu.dtb.read_accesses 943227 # DTB read accesses 456system.cpu.dtb.write_hits 6592681 # DTB write hits 457system.cpu.dtb.write_misses 10567 # DTB write misses 458system.cpu.dtb.write_acv 408 # DTB write access violations 459system.cpu.dtb.write_accesses 338977 # DTB write accesses 460system.cpu.dtb.data_hits 16518741 # DTB hits 461system.cpu.dtb.data_misses 51796 # DTB misses 462system.cpu.dtb.data_acv 953 # DTB access violations 463system.cpu.dtb.data_accesses 1282204 # DTB accesses 464system.cpu.itb.fetch_hits 1307907 # ITB hits 465system.cpu.itb.fetch_misses 36763 # ITB misses 466system.cpu.itb.fetch_acv 1058 # ITB acv 467system.cpu.itb.fetch_accesses 1344670 # ITB accesses | 453system.cpu.dtb.read_hits 9912884 # DTB read hits 454system.cpu.dtb.read_misses 41215 # DTB read misses 455system.cpu.dtb.read_acv 553 # DTB read access violations 456system.cpu.dtb.read_accesses 941108 # DTB read accesses 457system.cpu.dtb.write_hits 6599017 # DTB write hits 458system.cpu.dtb.write_misses 10339 # DTB write misses 459system.cpu.dtb.write_acv 401 # DTB write access violations 460system.cpu.dtb.write_accesses 338138 # DTB write accesses 461system.cpu.dtb.data_hits 16511901 # DTB hits 462system.cpu.dtb.data_misses 51554 # DTB misses 463system.cpu.dtb.data_acv 954 # DTB access violations 464system.cpu.dtb.data_accesses 1279246 # DTB accesses 465system.cpu.itb.fetch_hits 1308304 # ITB hits 466system.cpu.itb.fetch_misses 36786 # ITB misses 467system.cpu.itb.fetch_acv 1079 # ITB acv 468system.cpu.itb.fetch_accesses 1345090 # ITB accesses |
| 468system.cpu.itb.read_hits 0 # DTB read hits 469system.cpu.itb.read_misses 0 # DTB read misses 470system.cpu.itb.read_acv 0 # DTB read access violations 471system.cpu.itb.read_accesses 0 # DTB read accesses 472system.cpu.itb.write_hits 0 # DTB write hits 473system.cpu.itb.write_misses 0 # DTB write misses 474system.cpu.itb.write_acv 0 # DTB write access violations 475system.cpu.itb.write_accesses 0 # DTB write accesses 476system.cpu.itb.data_hits 0 # DTB hits 477system.cpu.itb.data_misses 0 # DTB misses 478system.cpu.itb.data_acv 0 # DTB access violations 479system.cpu.itb.data_accesses 0 # DTB accesses | 469system.cpu.itb.read_hits 0 # DTB read hits 470system.cpu.itb.read_misses 0 # DTB read misses 471system.cpu.itb.read_acv 0 # DTB read access violations 472system.cpu.itb.read_accesses 0 # DTB read accesses 473system.cpu.itb.write_hits 0 # DTB write hits 474system.cpu.itb.write_misses 0 # DTB write misses 475system.cpu.itb.write_acv 0 # DTB write access violations 476system.cpu.itb.write_accesses 0 # DTB write accesses 477system.cpu.itb.data_hits 0 # DTB hits 478system.cpu.itb.data_misses 0 # DTB misses 479system.cpu.itb.data_acv 0 # DTB access violations 480system.cpu.itb.data_accesses 0 # DTB accesses |
| 480system.cpu.numCycles 122133073 # number of cpu cycles simulated | 481system.cpu.numCycles 121969353 # number of cpu cycles simulated |
| 481system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 482system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 482system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 483system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 483system.cpu.fetch.icacheStallCycles 28029052 # Number of cycles fetch is stalled on an Icache miss 484system.cpu.fetch.Insts 70711644 # Number of instructions fetch has processed 485system.cpu.fetch.Branches 13847711 # Number of branches that fetch encountered 486system.cpu.fetch.predictedBranches 6712561 # Number of branches that fetch has predicted taken 487system.cpu.fetch.Cycles 13244944 # Number of cycles fetch has run and was not squashing or blocked 488system.cpu.fetch.SquashCycles 1986135 # Number of cycles fetch has spent squashing 489system.cpu.fetch.BlockedCycles 38034896 # Number of cycles fetch has spent blocked 490system.cpu.fetch.MiscStallCycles 32174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 491system.cpu.fetch.PendingTrapStallCycles 253831 # Number of stall cycles due to pending traps 492system.cpu.fetch.PendingQuiesceStallCycles 364385 # Number of stall cycles due to pending quiesce instructions 493system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR 494system.cpu.fetch.CacheLines 8541461 # Number of cache lines fetched 495system.cpu.fetch.IcacheSquashes 263003 # Number of outstanding Icache misses that were squashed 496system.cpu.fetch.rateDist::samples 81242947 # Number of instructions fetched each cycle (Total) 497system.cpu.fetch.rateDist::mean 0.870373 # Number of instructions fetched each cycle (Total) 498system.cpu.fetch.rateDist::stdev 2.213979 # Number of instructions fetched each cycle (Total) | 484system.cpu.fetch.icacheStallCycles 28022459 # Number of cycles fetch is stalled on an Icache miss 485system.cpu.fetch.Insts 70674133 # Number of instructions fetch has processed 486system.cpu.fetch.Branches 13846630 # Number of branches that fetch encountered 487system.cpu.fetch.predictedBranches 6718309 # Number of branches that fetch has predicted taken 488system.cpu.fetch.Cycles 13243332 # Number of cycles fetch has run and was not squashing or blocked 489system.cpu.fetch.SquashCycles 1983249 # Number of cycles fetch has spent squashing 490system.cpu.fetch.BlockedCycles 37995640 # Number of cycles fetch has spent blocked 491system.cpu.fetch.MiscStallCycles 32164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 492system.cpu.fetch.PendingTrapStallCycles 254581 # Number of stall cycles due to pending traps 493system.cpu.fetch.PendingQuiesceStallCycles 364654 # Number of stall cycles due to pending quiesce instructions 494system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR 495system.cpu.fetch.CacheLines 8542175 # Number of cache lines fetched 496system.cpu.fetch.IcacheSquashes 264688 # Number of outstanding Icache misses that were squashed 497system.cpu.fetch.rateDist::samples 81194854 # Number of instructions fetched each cycle (Total) 498system.cpu.fetch.rateDist::mean 0.870426 # Number of instructions fetched each cycle (Total) 499system.cpu.fetch.rateDist::stdev 2.213908 # Number of instructions fetched each cycle (Total) |
| 499system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 500system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 500system.cpu.fetch.rateDist::0 67998003 83.70% 83.70% # Number of instructions fetched each cycle (Total) 501system.cpu.fetch.rateDist::1 851901 1.05% 84.75% # Number of instructions fetched each cycle (Total) 502system.cpu.fetch.rateDist::2 1695578 2.09% 86.83% # Number of instructions fetched each cycle (Total) 503system.cpu.fetch.rateDist::3 822984 1.01% 87.85% # Number of instructions fetched each cycle (Total) 504system.cpu.fetch.rateDist::4 2755109 3.39% 91.24% # Number of instructions fetched each cycle (Total) 505system.cpu.fetch.rateDist::5 560259 0.69% 91.93% # Number of instructions fetched each cycle (Total) 506system.cpu.fetch.rateDist::6 643349 0.79% 92.72% # Number of instructions fetched each cycle (Total) 507system.cpu.fetch.rateDist::7 1008302 1.24% 93.96% # Number of instructions fetched each cycle (Total) 508system.cpu.fetch.rateDist::8 4907462 6.04% 100.00% # Number of instructions fetched each cycle (Total) | 501system.cpu.fetch.rateDist::0 67951522 83.69% 83.69% # Number of instructions fetched each cycle (Total) 502system.cpu.fetch.rateDist::1 854853 1.05% 84.74% # Number of instructions fetched each cycle (Total) 503system.cpu.fetch.rateDist::2 1698258 2.09% 86.83% # Number of instructions fetched each cycle (Total) 504system.cpu.fetch.rateDist::3 823227 1.01% 87.85% # Number of instructions fetched each cycle (Total) 505system.cpu.fetch.rateDist::4 2753963 3.39% 91.24% # Number of instructions fetched each cycle (Total) 506system.cpu.fetch.rateDist::5 558188 0.69% 91.93% # Number of instructions fetched each cycle (Total) 507system.cpu.fetch.rateDist::6 642929 0.79% 92.72% # Number of instructions fetched each cycle (Total) 508system.cpu.fetch.rateDist::7 1006595 1.24% 93.96% # Number of instructions fetched each cycle (Total) 509system.cpu.fetch.rateDist::8 4905319 6.04% 100.00% # Number of instructions fetched each cycle (Total) |
| 509system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 510system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 511system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 510system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 511system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 512system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 512system.cpu.fetch.rateDist::total 81242947 # Number of instructions fetched each cycle (Total) 513system.cpu.fetch.branchRate 0.113382 # Number of branch fetches per cycle 514system.cpu.fetch.rate 0.578972 # Number of inst fetches per cycle 515system.cpu.decode.IdleCycles 29204589 # Number of cycles decode is idle 516system.cpu.decode.BlockedCycles 37726390 # Number of cycles decode is blocked 517system.cpu.decode.RunCycles 12112827 # Number of cycles decode is running 518system.cpu.decode.UnblockCycles 958015 # Number of cycles decode is unblocking 519system.cpu.decode.SquashCycles 1241125 # Number of cycles decode is squashing 520system.cpu.decode.BranchResolved 582779 # Number of times decode resolved a branch 521system.cpu.decode.BranchMispred 42656 # Number of times decode detected a branch misprediction 522system.cpu.decode.DecodedInsts 69393384 # Number of instructions handled by decode 523system.cpu.decode.SquashedInsts 129440 # Number of squashed instructions handled by decode 524system.cpu.rename.SquashCycles 1241125 # Number of cycles rename is squashing 525system.cpu.rename.IdleCycles 30348079 # Number of cycles rename is idle 526system.cpu.rename.BlockCycles 14012797 # Number of cycles rename is blocking 527system.cpu.rename.serializeStallCycles 20034433 # count of cycles rename stalled for serializing inst 528system.cpu.rename.RunCycles 11321379 # Number of cycles rename is running 529system.cpu.rename.UnblockCycles 4285132 # Number of cycles rename is unblocking 530system.cpu.rename.RenamedInsts 65602946 # Number of instructions processed by rename 531system.cpu.rename.ROBFullEvents 7156 # Number of times rename has blocked due to ROB full 532system.cpu.rename.IQFullEvents 505213 # Number of times rename has blocked due to IQ full 533system.cpu.rename.LSQFullEvents 1511728 # Number of times rename has blocked due to LSQ full 534system.cpu.rename.RenamedOperands 43797820 # Number of destination operands rename has renamed 535system.cpu.rename.RenameLookups 79654521 # Number of register rename lookups that rename has made 536system.cpu.rename.int_rename_lookups 79475437 # Number of integer rename lookups 537system.cpu.rename.fp_rename_lookups 166633 # Number of floating rename lookups 538system.cpu.rename.CommittedMaps 38179156 # Number of HB maps that are committed 539system.cpu.rename.UndoneMaps 5618656 # Number of HB maps that are undone due to squashing 540system.cpu.rename.serializingInsts 1682920 # count of serializing insts renamed 541system.cpu.rename.tempSerializingInsts 240154 # count of temporary serializing insts renamed 542system.cpu.rename.skidInsts 12205182 # count of insts added to the skid buffer 543system.cpu.memDep0.insertedLoads 10434201 # Number of loads inserted to the mem dependence unit. 544system.cpu.memDep0.insertedStores 6904424 # Number of stores inserted to the mem dependence unit. 545system.cpu.memDep0.conflictingLoads 1321264 # Number of conflicting loads. 546system.cpu.memDep0.conflictingStores 860087 # Number of conflicting stores. 547system.cpu.iq.iqInstsAdded 58162225 # Number of instructions added to the IQ (excludes non-spec) 548system.cpu.iq.iqNonSpecInstsAdded 2049609 # Number of non-speculative instructions added to the IQ 549system.cpu.iq.iqInstsIssued 56784496 # Number of instructions issued 550system.cpu.iq.iqSquashedInstsIssued 110090 # Number of squashed instructions issued 551system.cpu.iq.iqSquashedInstsExamined 6876207 # Number of squashed instructions iterated over during squash; mainly for profiling 552system.cpu.iq.iqSquashedOperandsExamined 3554384 # Number of squashed operands that are examined and possibly removed from graph 553system.cpu.iq.iqSquashedNonSpecRemoved 1388666 # Number of squashed non-spec instructions that were removed 554system.cpu.iq.issued_per_cycle::samples 81242947 # Number of insts issued each cycle 555system.cpu.iq.issued_per_cycle::mean 0.698947 # Number of insts issued each cycle 556system.cpu.iq.issued_per_cycle::stdev 1.361354 # Number of insts issued each cycle | 513system.cpu.fetch.rateDist::total 81194854 # Number of instructions fetched each cycle (Total) 514system.cpu.fetch.branchRate 0.113525 # Number of branch fetches per cycle 515system.cpu.fetch.rate 0.579442 # Number of inst fetches per cycle 516system.cpu.decode.IdleCycles 29206421 # Number of cycles decode is idle 517system.cpu.decode.BlockedCycles 37679452 # Number of cycles decode is blocked 518system.cpu.decode.RunCycles 12104138 # Number of cycles decode is running 519system.cpu.decode.UnblockCycles 965352 # Number of cycles decode is unblocking 520system.cpu.decode.SquashCycles 1239490 # Number of cycles decode is squashing 521system.cpu.decode.BranchResolved 585042 # Number of times decode resolved a branch 522system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction 523system.cpu.decode.DecodedInsts 69357398 # Number of instructions handled by decode 524system.cpu.decode.SquashedInsts 129450 # Number of squashed instructions handled by decode 525system.cpu.rename.SquashCycles 1239490 # Number of cycles rename is squashing 526system.cpu.rename.IdleCycles 30354385 # Number of cycles rename is idle 527system.cpu.rename.BlockCycles 13996332 # Number of cycles rename is blocking 528system.cpu.rename.serializeStallCycles 19984766 # count of cycles rename stalled for serializing inst 529system.cpu.rename.RunCycles 11324382 # Number of cycles rename is running 530system.cpu.rename.UnblockCycles 4295497 # Number of cycles rename is unblocking 531system.cpu.rename.RenamedInsts 65588313 # Number of instructions processed by rename 532system.cpu.rename.ROBFullEvents 7118 # Number of times rename has blocked due to ROB full 533system.cpu.rename.IQFullEvents 505148 # Number of times rename has blocked due to IQ full 534system.cpu.rename.LSQFullEvents 1530678 # Number of times rename has blocked due to LSQ full 535system.cpu.rename.RenamedOperands 43795306 # Number of destination operands rename has renamed 536system.cpu.rename.RenameLookups 79617271 # Number of register rename lookups that rename has made 537system.cpu.rename.int_rename_lookups 79438234 # Number of integer rename lookups 538system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups 539system.cpu.rename.CommittedMaps 38180209 # Number of HB maps that are committed 540system.cpu.rename.UndoneMaps 5615089 # Number of HB maps that are undone due to squashing 541system.cpu.rename.serializingInsts 1682372 # count of serializing insts renamed 542system.cpu.rename.tempSerializingInsts 239607 # count of temporary serializing insts renamed 543system.cpu.rename.skidInsts 12205686 # count of insts added to the skid buffer 544system.cpu.memDep0.insertedLoads 10422971 # Number of loads inserted to the mem dependence unit. 545system.cpu.memDep0.insertedStores 6895231 # Number of stores inserted to the mem dependence unit. 546system.cpu.memDep0.conflictingLoads 1319326 # Number of conflicting loads. 547system.cpu.memDep0.conflictingStores 854507 # Number of conflicting stores. 548system.cpu.iq.iqInstsAdded 58152614 # Number of instructions added to the IQ (excludes non-spec) 549system.cpu.iq.iqNonSpecInstsAdded 2049745 # Number of non-speculative instructions added to the IQ 550system.cpu.iq.iqInstsIssued 56795087 # Number of instructions issued 551system.cpu.iq.iqSquashedInstsIssued 97937 # Number of squashed instructions issued 552system.cpu.iq.iqSquashedInstsExamined 6861282 # Number of squashed instructions iterated over during squash; mainly for profiling 553system.cpu.iq.iqSquashedOperandsExamined 3503589 # Number of squashed operands that are examined and possibly removed from graph 554system.cpu.iq.iqSquashedNonSpecRemoved 1388801 # Number of squashed non-spec instructions that were removed 555system.cpu.iq.issued_per_cycle::samples 81194854 # Number of insts issued each cycle 556system.cpu.iq.issued_per_cycle::mean 0.699491 # Number of insts issued each cycle 557system.cpu.iq.issued_per_cycle::stdev 1.361721 # Number of insts issued each cycle |
| 557system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 558system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 558system.cpu.iq.issued_per_cycle::0 56591956 69.66% 69.66% # Number of insts issued each cycle 559system.cpu.iq.issued_per_cycle::1 10816248 13.31% 82.97% # Number of insts issued each cycle 560system.cpu.iq.issued_per_cycle::2 5164366 6.36% 89.33% # Number of insts issued each cycle 561system.cpu.iq.issued_per_cycle::3 3390360 4.17% 93.50% # Number of insts issued each cycle 562system.cpu.iq.issued_per_cycle::4 2636798 3.25% 96.75% # Number of insts issued each cycle 563system.cpu.iq.issued_per_cycle::5 1463129 1.80% 98.55% # Number of insts issued each cycle 564system.cpu.iq.issued_per_cycle::6 751413 0.92% 99.47% # Number of insts issued each cycle 565system.cpu.iq.issued_per_cycle::7 332295 0.41% 99.88% # Number of insts issued each cycle 566system.cpu.iq.issued_per_cycle::8 96382 0.12% 100.00% # Number of insts issued each cycle | 559system.cpu.iq.issued_per_cycle::0 56519522 69.61% 69.61% # Number of insts issued each cycle 560system.cpu.iq.issued_per_cycle::1 10856431 13.37% 82.98% # Number of insts issued each cycle 561system.cpu.iq.issued_per_cycle::2 5145956 6.34% 89.32% # Number of insts issued each cycle 562system.cpu.iq.issued_per_cycle::3 3402319 4.19% 93.51% # Number of insts issued each cycle 563system.cpu.iq.issued_per_cycle::4 2626681 3.24% 96.74% # Number of insts issued each cycle 564system.cpu.iq.issued_per_cycle::5 1459376 1.80% 98.54% # Number of insts issued each cycle 565system.cpu.iq.issued_per_cycle::6 753323 0.93% 99.47% # Number of insts issued each cycle 566system.cpu.iq.issued_per_cycle::7 333723 0.41% 99.88% # Number of insts issued each cycle 567system.cpu.iq.issued_per_cycle::8 97523 0.12% 100.00% # Number of insts issued each cycle |
| 567system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 568system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 569system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 568system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 569system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 570system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 570system.cpu.iq.issued_per_cycle::total 81242947 # Number of insts issued each cycle | 571system.cpu.iq.issued_per_cycle::total 81194854 # Number of insts issued each cycle |
| 571system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 572system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 572system.cpu.iq.fu_full::IntAlu 91428 11.57% 11.57% # attempts to use FU when none available 573system.cpu.iq.fu_full::IntMult 0 0.00% 11.57% # attempts to use FU when none available 574system.cpu.iq.fu_full::IntDiv 0 0.00% 11.57% # attempts to use FU when none available 575system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.57% # attempts to use FU when none available 576system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.57% # attempts to use FU when none available 577system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.57% # attempts to use FU when none available 578system.cpu.iq.fu_full::FloatMult 0 0.00% 11.57% # attempts to use FU when none available 579system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.57% # attempts to use FU when none available 580system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.57% # attempts to use FU when none available 581system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.57% # attempts to use FU when none available 582system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.57% # attempts to use FU when none available 583system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.57% # attempts to use FU when none available 584system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.57% # attempts to use FU when none available 585system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.57% # attempts to use FU when none available 586system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.57% # attempts to use FU when none available 587system.cpu.iq.fu_full::SimdMult 0 0.00% 11.57% # attempts to use FU when none available 588system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.57% # attempts to use FU when none available 589system.cpu.iq.fu_full::SimdShift 0 0.00% 11.57% # attempts to use FU when none available 590system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.57% # attempts to use FU when none available 591system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.57% # attempts to use FU when none available 592system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.57% # attempts to use FU when none available 593system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.57% # attempts to use FU when none available 594system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.57% # attempts to use FU when none available 595system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.57% # attempts to use FU when none available 596system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.57% # attempts to use FU when none available 597system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.57% # attempts to use FU when none available 598system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.57% # attempts to use FU when none available 599system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.57% # attempts to use FU when none available 600system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.57% # attempts to use FU when none available 601system.cpu.iq.fu_full::MemRead 372699 47.16% 58.73% # attempts to use FU when none available 602system.cpu.iq.fu_full::MemWrite 326088 41.27% 100.00% # attempts to use FU when none available | 573system.cpu.iq.fu_full::IntAlu 92642 11.69% 11.69% # attempts to use FU when none available 574system.cpu.iq.fu_full::IntMult 0 0.00% 11.69% # attempts to use FU when none available 575system.cpu.iq.fu_full::IntDiv 0 0.00% 11.69% # attempts to use FU when none available 576system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.69% # attempts to use FU when none available 577system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.69% # attempts to use FU when none available 578system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.69% # attempts to use FU when none available 579system.cpu.iq.fu_full::FloatMult 0 0.00% 11.69% # attempts to use FU when none available 580system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.69% # attempts to use FU when none available 581system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.69% # attempts to use FU when none available 582system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.69% # attempts to use FU when none available 583system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.69% # attempts to use FU when none available 584system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.69% # attempts to use FU when none available 585system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.69% # attempts to use FU when none available 586system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.69% # attempts to use FU when none available 587system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.69% # attempts to use FU when none available 588system.cpu.iq.fu_full::SimdMult 0 0.00% 11.69% # attempts to use FU when none available 589system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.69% # attempts to use FU when none available 590system.cpu.iq.fu_full::SimdShift 0 0.00% 11.69% # attempts to use FU when none available 591system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.69% # attempts to use FU when none available 592system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.69% # attempts to use FU when none available 593system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.69% # attempts to use FU when none available 594system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.69% # attempts to use FU when none available 595system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.69% # attempts to use FU when none available 596system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.69% # attempts to use FU when none available 597system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.69% # attempts to use FU when none available 598system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.69% # attempts to use FU when none available 599system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.69% # attempts to use FU when none available 600system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.69% # attempts to use FU when none available 601system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.69% # attempts to use FU when none available 602system.cpu.iq.fu_full::MemRead 372744 47.05% 58.74% # attempts to use FU when none available 603system.cpu.iq.fu_full::MemWrite 326922 41.26% 100.00% # attempts to use FU when none available |
| 603system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 604system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 605system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued | 604system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 605system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 606system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued |
| 606system.cpu.iq.FU_type_0::IntAlu 38710597 68.17% 68.18% # Type of FU issued 607system.cpu.iq.FU_type_0::IntMult 61705 0.11% 68.29% # Type of FU issued 608system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued 609system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued 610system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued 611system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued 612system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued 613system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued 614system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued 615system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued 616system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued 617system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued 618system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued 619system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued 620system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued 621system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued 622system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued 623system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued 624system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued 625system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued 626system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued 627system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued 628system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued 629system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued 630system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued 631system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued 632system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued 633system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued 634system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued 635system.cpu.iq.FU_type_0::MemRead 10355398 18.24% 86.58% # Type of FU issued 636system.cpu.iq.FU_type_0::MemWrite 6671255 11.75% 98.33% # Type of FU issued | 607system.cpu.iq.FU_type_0::IntAlu 38726894 68.19% 68.20% # Type of FU issued 608system.cpu.iq.FU_type_0::IntMult 61723 0.11% 68.31% # Type of FU issued 609system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued 610system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued 611system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued 612system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued 613system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued 614system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued 615system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued 616system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued 617system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued 618system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued 619system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued 620system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued 621system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued 622system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued 623system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued 624system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued 625system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued 626system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued 627system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued 628system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued 629system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued 630system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued 631system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued 632system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued 633system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued 634system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued 635system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued 636system.cpu.iq.FU_type_0::MemRead 10344006 18.21% 86.57% # Type of FU issued 637system.cpu.iq.FU_type_0::MemWrite 6676923 11.76% 98.33% # Type of FU issued |
| 637system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued 638system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 638system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued 639system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 639system.cpu.iq.FU_type_0::total 56784496 # Type of FU issued 640system.cpu.iq.rate 0.464940 # Inst issue rate 641system.cpu.iq.fu_busy_cnt 790215 # FU busy when requested 642system.cpu.iq.fu_busy_rate 0.013916 # FU busy rate (busy events/executed inst) 643system.cpu.iq.int_inst_queue_reads 195020122 # Number of integer instruction queue reads 644system.cpu.iq.int_inst_queue_writes 66766340 # Number of integer instruction queue writes 645system.cpu.iq.int_inst_queue_wakeup_accesses 55549754 # Number of integer instruction queue wakeup accesses 646system.cpu.iq.fp_inst_queue_reads 692121 # Number of floating instruction queue reads 647system.cpu.iq.fp_inst_queue_writes 335594 # Number of floating instruction queue writes 648system.cpu.iq.fp_inst_queue_wakeup_accesses 327937 # Number of floating instruction queue wakeup accesses 649system.cpu.iq.int_alu_accesses 57205980 # Number of integer alu accesses 650system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses 651system.cpu.iew.lsq.thread0.forwLoads 599867 # Number of loads that had data forwarded from stores | 640system.cpu.iq.FU_type_0::total 56795087 # Type of FU issued 641system.cpu.iq.rate 0.465650 # Inst issue rate 642system.cpu.iq.fu_busy_cnt 792308 # FU busy when requested 643system.cpu.iq.fu_busy_rate 0.013950 # FU busy rate (busy events/executed inst) 644system.cpu.iq.int_inst_queue_reads 194982001 # Number of integer instruction queue reads 645system.cpu.iq.int_inst_queue_writes 66741051 # Number of integer instruction queue writes 646system.cpu.iq.int_inst_queue_wakeup_accesses 55566428 # Number of integer instruction queue wakeup accesses 647system.cpu.iq.fp_inst_queue_reads 693271 # Number of floating instruction queue reads 648system.cpu.iq.fp_inst_queue_writes 336387 # Number of floating instruction queue writes 649system.cpu.iq.fp_inst_queue_wakeup_accesses 327889 # Number of floating instruction queue wakeup accesses 650system.cpu.iq.int_alu_accesses 57217918 # Number of integer alu accesses 651system.cpu.iq.fp_alu_accesses 362191 # Number of floating point alu accesses 652system.cpu.iew.lsq.thread0.forwLoads 598643 # Number of loads that had data forwarded from stores |
| 652system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 653system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 653system.cpu.iew.lsq.thread0.squashedLoads 1342082 # Number of loads squashed 654system.cpu.iew.lsq.thread0.ignoredResponses 3325 # Number of memory responses ignored because the instruction is squashed 655system.cpu.iew.lsq.thread0.memOrderViolation 14250 # Number of memory ordering violations 656system.cpu.iew.lsq.thread0.squashedStores 526611 # Number of stores squashed | 654system.cpu.iew.lsq.thread0.squashedLoads 1330641 # Number of loads squashed 655system.cpu.iew.lsq.thread0.ignoredResponses 3245 # Number of memory responses ignored because the instruction is squashed 656system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations 657system.cpu.iew.lsq.thread0.squashedStores 517313 # Number of stores squashed |
| 657system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 658system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 658system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 659system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 659system.cpu.iew.lsq.thread0.rescheduledLoads 17915 # Number of loads that were rescheduled 660system.cpu.iew.lsq.thread0.cacheBlocked 172386 # Number of times an access to memory failed due to the cache being blocked | 660system.cpu.iew.lsq.thread0.rescheduledLoads 17932 # Number of loads that were rescheduled 661system.cpu.iew.lsq.thread0.cacheBlocked 166827 # Number of times an access to memory failed due to the cache being blocked |
| 661system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 662system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 662system.cpu.iew.iewSquashCycles 1241125 # Number of cycles IEW is squashing 663system.cpu.iew.iewBlockCycles 10205447 # Number of cycles IEW is blocking 664system.cpu.iew.iewUnblockCycles 698563 # Number of cycles IEW is unblocking 665system.cpu.iew.iewDispatchedInsts 63733516 # Number of instructions dispatched to IQ 666system.cpu.iew.iewDispSquashedInsts 684669 # Number of squashed instructions skipped by dispatch 667system.cpu.iew.iewDispLoadInsts 10434201 # Number of dispatched load instructions 668system.cpu.iew.iewDispStoreInsts 6904424 # Number of dispatched store instructions 669system.cpu.iew.iewDispNonSpecInsts 1805473 # Number of dispatched non-speculative instructions 670system.cpu.iew.iewIQFullEvents 512478 # Number of times the IQ has become full, causing a stall 671system.cpu.iew.iewLSQFullEvents 17546 # Number of times the LSQ has become full, causing a stall 672system.cpu.iew.memOrderViolationEvents 14250 # Number of memory order violations 673system.cpu.iew.predictedTakenIncorrect 200257 # Number of branches that were predicted taken incorrectly 674system.cpu.iew.predictedNotTakenIncorrect 411476 # Number of branches that were predicted not taken incorrectly 675system.cpu.iew.branchMispredicts 611733 # Number of branch mispredicts detected at execute 676system.cpu.iew.iewExecutedInsts 56321962 # Number of executed instructions 677system.cpu.iew.iewExecLoadInsts 9995488 # Number of load instructions executed 678system.cpu.iew.iewExecSquashedInsts 462533 # Number of squashed instructions skipped in execute | 663system.cpu.iew.iewSquashCycles 1239490 # Number of cycles IEW is squashing 664system.cpu.iew.iewBlockCycles 10213175 # Number of cycles IEW is blocking 665system.cpu.iew.iewUnblockCycles 697716 # Number of cycles IEW is unblocking 666system.cpu.iew.iewDispatchedInsts 63724678 # Number of instructions dispatched to IQ 667system.cpu.iew.iewDispSquashedInsts 681593 # Number of squashed instructions skipped by dispatch 668system.cpu.iew.iewDispLoadInsts 10422971 # Number of dispatched load instructions 669system.cpu.iew.iewDispStoreInsts 6895231 # Number of dispatched store instructions 670system.cpu.iew.iewDispNonSpecInsts 1805950 # Number of dispatched non-speculative instructions 671system.cpu.iew.iewIQFullEvents 512370 # Number of times the IQ has become full, causing a stall 672system.cpu.iew.iewLSQFullEvents 16905 # Number of times the LSQ has become full, causing a stall 673system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations 674system.cpu.iew.predictedTakenIncorrect 202448 # Number of branches that were predicted taken incorrectly 675system.cpu.iew.predictedNotTakenIncorrect 409860 # Number of branches that were predicted not taken incorrectly 676system.cpu.iew.branchMispredicts 612308 # Number of branch mispredicts detected at execute 677system.cpu.iew.iewExecutedInsts 56329043 # Number of executed instructions 678system.cpu.iew.iewExecLoadInsts 9982328 # Number of load instructions executed 679system.cpu.iew.iewExecSquashedInsts 466043 # Number of squashed instructions skipped in execute |
| 679system.cpu.iew.exec_swp 0 # number of swp insts executed | 680system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 680system.cpu.iew.exec_nop 3521682 # number of nop insts executed 681system.cpu.iew.exec_refs 16613940 # number of memory reference insts executed 682system.cpu.iew.exec_branches 8922207 # Number of branches executed 683system.cpu.iew.exec_stores 6618452 # Number of stores executed 684system.cpu.iew.exec_rate 0.461152 # Inst execution rate 685system.cpu.iew.wb_sent 55993079 # cumulative count of insts sent to commit 686system.cpu.iew.wb_count 55877691 # cumulative count of insts written-back 687system.cpu.iew.wb_producers 27722224 # num instructions producing a value 688system.cpu.iew.wb_consumers 37565081 # num instructions consuming a value | 681system.cpu.iew.exec_nop 3522319 # number of nop insts executed 682system.cpu.iew.exec_refs 16606918 # number of memory reference insts executed 683system.cpu.iew.exec_branches 8922931 # Number of branches executed 684system.cpu.iew.exec_stores 6624590 # Number of stores executed 685system.cpu.iew.exec_rate 0.461829 # Inst execution rate 686system.cpu.iew.wb_sent 56008659 # cumulative count of insts sent to commit 687system.cpu.iew.wb_count 55894317 # cumulative count of insts written-back 688system.cpu.iew.wb_producers 27713107 # num instructions producing a value 689system.cpu.iew.wb_consumers 37520284 # num instructions consuming a value |
| 689system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 690system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 690system.cpu.iew.wb_rate 0.457515 # insts written-back per cycle 691system.cpu.iew.wb_fanout 0.737979 # average fanout of values written-back | 691system.cpu.iew.wb_rate 0.458265 # insts written-back per cycle 692system.cpu.iew.wb_fanout 0.738617 # average fanout of values written-back |
| 692system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 693system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 693system.cpu.commit.commitSquashedInsts 7447390 # The number of squashed insts skipped by commit 694system.cpu.commit.commitNonSpecStalls 660943 # The number of times commit has been forced to stall to communicate backwards 695system.cpu.commit.branchMispredicts 565908 # The number of times a branch was mispredicted 696system.cpu.commit.committed_per_cycle::samples 80001822 # Number of insts commited each cycle 697system.cpu.commit.committed_per_cycle::mean 0.702098 # Number of insts commited each cycle 698system.cpu.commit.committed_per_cycle::stdev 1.631989 # Number of insts commited each cycle | 694system.cpu.commit.commitSquashedInsts 7436889 # The number of squashed insts skipped by commit 695system.cpu.commit.commitNonSpecStalls 660944 # The number of times commit has been forced to stall to communicate backwards 696system.cpu.commit.branchMispredicts 566942 # The number of times a branch was mispredicted 697system.cpu.commit.committed_per_cycle::samples 79955364 # Number of insts commited each cycle 698system.cpu.commit.committed_per_cycle::mean 0.702522 # Number of insts commited each cycle 699system.cpu.commit.committed_per_cycle::stdev 1.631936 # Number of insts commited each cycle |
| 699system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 700system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 700system.cpu.commit.committed_per_cycle::0 59240837 74.05% 74.05% # Number of insts commited each cycle 701system.cpu.commit.committed_per_cycle::1 8588333 10.74% 84.78% # Number of insts commited each cycle 702system.cpu.commit.committed_per_cycle::2 4609463 5.76% 90.55% # Number of insts commited each cycle 703system.cpu.commit.committed_per_cycle::3 2533581 3.17% 93.71% # Number of insts commited each cycle 704system.cpu.commit.committed_per_cycle::4 1517845 1.90% 95.61% # Number of insts commited each cycle 705system.cpu.commit.committed_per_cycle::5 611107 0.76% 96.37% # Number of insts commited each cycle 706system.cpu.commit.committed_per_cycle::6 522353 0.65% 97.03% # Number of insts commited each cycle 707system.cpu.commit.committed_per_cycle::7 526375 0.66% 97.69% # Number of insts commited each cycle 708system.cpu.commit.committed_per_cycle::8 1851928 2.31% 100.00% # Number of insts commited each cycle | 701system.cpu.commit.committed_per_cycle::0 59166975 74.00% 74.00% # Number of insts commited each cycle 702system.cpu.commit.committed_per_cycle::1 8627079 10.79% 84.79% # Number of insts commited each cycle 703system.cpu.commit.committed_per_cycle::2 4603678 5.76% 90.55% # Number of insts commited each cycle 704system.cpu.commit.committed_per_cycle::3 2536989 3.17% 93.72% # Number of insts commited each cycle 705system.cpu.commit.committed_per_cycle::4 1507337 1.89% 95.61% # Number of insts commited each cycle 706system.cpu.commit.committed_per_cycle::5 611638 0.76% 96.37% # Number of insts commited each cycle 707system.cpu.commit.committed_per_cycle::6 523619 0.65% 97.03% # Number of insts commited each cycle 708system.cpu.commit.committed_per_cycle::7 528614 0.66% 97.69% # Number of insts commited each cycle 709system.cpu.commit.committed_per_cycle::8 1849435 2.31% 100.00% # Number of insts commited each cycle |
| 709system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 710system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 711system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 710system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 711system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 712system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 712system.cpu.commit.committed_per_cycle::total 80001822 # Number of insts commited each cycle 713system.cpu.commit.committedInsts 56169084 # Number of instructions committed 714system.cpu.commit.committedOps 56169084 # Number of ops (including micro ops) committed | 713system.cpu.commit.committed_per_cycle::total 79955364 # Number of insts commited each cycle 714system.cpu.commit.committedInsts 56170432 # Number of instructions committed 715system.cpu.commit.committedOps 56170432 # Number of ops (including micro ops) committed |
| 715system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 716system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 716system.cpu.commit.refs 15469932 # Number of memory references committed 717system.cpu.commit.loads 9092119 # Number of loads committed 718system.cpu.commit.membars 226344 # Number of memory barriers committed 719system.cpu.commit.branches 8439731 # Number of branches committed | 717system.cpu.commit.refs 15470248 # Number of memory references committed 718system.cpu.commit.loads 9092330 # Number of loads committed 719system.cpu.commit.membars 226348 # Number of memory barriers committed 720system.cpu.commit.branches 8439871 # Number of branches committed |
| 720system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. | 721system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. |
| 721system.cpu.commit.int_insts 52018783 # Number of committed integer instructions. 722system.cpu.commit.function_calls 740550 # Number of function calls committed. 723system.cpu.commit.bw_lim_events 1851928 # number cycles where commit BW limit reached | 722system.cpu.commit.int_insts 52020070 # Number of committed integer instructions. 723system.cpu.commit.function_calls 740568 # Number of function calls committed. 724system.cpu.commit.op_class_0::No_OpClass 3198067 5.69% 5.69% # Class of committed instruction 725system.cpu.commit.op_class_0::IntAlu 36230888 64.50% 70.20% # Class of committed instruction 726system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.30% # Class of committed instruction 727system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction 728system.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction 729system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 730system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 731system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 732system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction 733system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction 734system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction 735system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction 736system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction 737system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction 738system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction 739system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction 740system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction 741system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction 742system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction 743system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction 744system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction 745system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction 746system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction 747system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction 748system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction 749system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction 750system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction 751system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction 752system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction 753system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction 754system.cpu.commit.op_class_0::MemRead 9318678 16.59% 86.95% # Class of committed instruction 755system.cpu.commit.op_class_0::MemWrite 6383871 11.37% 98.31% # Class of committed instruction 756system.cpu.commit.op_class_0::IprAccess 949012 1.69% 100.00% # Class of committed instruction 757system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 758system.cpu.commit.op_class_0::total 56170432 # Class of committed instruction 759system.cpu.commit.bw_lim_events 1849435 # number cycles where commit BW limit reached |
| 724system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 760system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 725system.cpu.rob.rob_reads 141516799 # The number of ROB reads 726system.cpu.rob.rob_writes 128475885 # The number of ROB writes 727system.cpu.timesIdled 1198400 # Number of times that the entire CPU went into an idle state and unscheduled itself 728system.cpu.idleCycles 40890126 # Total number of cycles that the CPU has spent unscheduled due to idling 729system.cpu.quiesceCycles 3598244060 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 730system.cpu.committedInsts 52978349 # Number of Instructions Simulated 731system.cpu.committedOps 52978349 # Number of Ops (including micro ops) Simulated 732system.cpu.committedInsts_total 52978349 # Number of Instructions Simulated 733system.cpu.cpi 2.305339 # CPI: Cycles Per Instruction 734system.cpu.cpi_total 2.305339 # CPI: Total CPI of All Threads 735system.cpu.ipc 0.433776 # IPC: Instructions Per Cycle 736system.cpu.ipc_total 0.433776 # IPC: Total IPC of All Threads 737system.cpu.int_regfile_reads 73853807 # number of integer regfile reads 738system.cpu.int_regfile_writes 40298046 # number of integer regfile writes 739system.cpu.fp_regfile_reads 166062 # number of floating regfile reads 740system.cpu.fp_regfile_writes 167446 # number of floating regfile writes 741system.cpu.misc_regfile_reads 2027357 # number of misc regfile reads 742system.cpu.misc_regfile_writes 938942 # number of misc regfile writes | 761system.cpu.rob.rob_reads 141463709 # The number of ROB reads 762system.cpu.rob.rob_writes 128455843 # The number of ROB writes 763system.cpu.timesIdled 1197783 # Number of times that the entire CPU went into an idle state and unscheduled itself 764system.cpu.idleCycles 40774499 # Total number of cycles that the CPU has spent unscheduled due to idling 765system.cpu.quiesceCycles 3598399845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 766system.cpu.committedInsts 52979638 # Number of Instructions Simulated 767system.cpu.committedOps 52979638 # Number of Ops (including micro ops) Simulated 768system.cpu.committedInsts_total 52979638 # Number of Instructions Simulated 769system.cpu.cpi 2.302193 # CPI: Cycles Per Instruction 770system.cpu.cpi_total 2.302193 # CPI: Total CPI of All Threads 771system.cpu.ipc 0.434368 # IPC: Instructions Per Cycle 772system.cpu.ipc_total 0.434368 # IPC: Total IPC of All Threads 773system.cpu.int_regfile_reads 73867254 # number of integer regfile reads 774system.cpu.int_regfile_writes 40307997 # number of integer regfile writes 775system.cpu.fp_regfile_reads 166020 # number of floating regfile reads 776system.cpu.fp_regfile_writes 167441 # number of floating regfile writes 777system.cpu.misc_regfile_reads 2027897 # number of misc regfile reads 778system.cpu.misc_regfile_writes 938938 # number of misc regfile writes |
| 743system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 744system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 745system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 746system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 747system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 748system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 749system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 750system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 766system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 767system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 768system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 769system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 770system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 771system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 772system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 773system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 779system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 780system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 781system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 782system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 783system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 784system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 785system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 786system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 802system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 803system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 804system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 805system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 806system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 807system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 808system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 809system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 774system.iobus.throughput 1454553 # Throughput (bytes/s) | 810system.iobus.throughput 1454556 # Throughput (bytes/s) |
| 775system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 776system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 777system.iobus.trans_dist::WriteReq 51149 # Transaction distribution 778system.iobus.trans_dist::WriteResp 51149 # Transaction distribution 779system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) 780system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 781system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 782system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 43 unchanged lines hidden (view full) --- 826system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 827system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 828system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 829system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 830system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 831system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 832system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 833system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 811system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 812system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 813system.iobus.trans_dist::WriteReq 51149 # Transaction distribution 814system.iobus.trans_dist::WriteResp 51149 # Transaction distribution 815system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) 816system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 817system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 818system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 43 unchanged lines hidden (view full) --- 862system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 863system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 864system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 865system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 866system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 867system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 868system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 869system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 834system.iobus.reqLayer29.occupancy 380111537 # Layer occupancy (ticks) | 870system.iobus.reqLayer29.occupancy 380172568 # Layer occupancy (ticks) |
| 835system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 836system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 837system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 838system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) 839system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 871system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 872system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 873system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 874system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) 875system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 840system.iobus.respLayer1.occupancy 43192006 # Layer occupancy (ticks) | 876system.iobus.respLayer1.occupancy 43172756 # Layer occupancy (ticks) |
| 841system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 877system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 842system.cpu.toL2Bus.throughput 111856774 # Throughput (bytes/s) 843system.cpu.toL2Bus.trans_dist::ReadReq 2116112 # Transaction distribution 844system.cpu.toL2Bus.trans_dist::ReadResp 2116015 # Transaction distribution | 878system.cpu.toL2Bus.throughput 111944057 # Throughput (bytes/s) 879system.cpu.toL2Bus.trans_dist::ReadReq 2118154 # Transaction distribution 880system.cpu.toL2Bus.trans_dist::ReadResp 2118059 # Transaction distribution |
| 845system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 846system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution | 881system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution 882system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution |
| 847system.cpu.toL2Bus.trans_dist::Writeback 840541 # Transaction distribution | 883system.cpu.toL2Bus.trans_dist::Writeback 840946 # Transaction distribution |
| 848system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution | 884system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution |
| 849system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 850system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution 851system.cpu.toL2Bus.trans_dist::ReadExReq 342408 # Transaction distribution 852system.cpu.toL2Bus.trans_dist::ReadExResp 300857 # Transaction distribution 853system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution 854system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2017437 # Packet count per connected master and slave (bytes) 855system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3676056 # Packet count per connected master and slave (bytes) 856system.cpu.toL2Bus.pkt_count::total 5693493 # Packet count per connected master and slave (bytes) 857system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64554304 # Cumulative packet size per connected master and slave (bytes) 858system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143513388 # Cumulative packet size per connected master and slave (bytes) 859system.cpu.toL2Bus.tot_pkt_size::total 208067692 # Cumulative packet size per connected master and slave (bytes) 860system.cpu.toL2Bus.data_through_bus 208057644 # Total data (bytes) 861system.cpu.toL2Bus.snoop_data_through_bus 17408 # Total snoop data (bytes) 862system.cpu.toL2Bus.reqLayer0.occupancy 2478840496 # Layer occupancy (ticks) | 885system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 886system.cpu.toL2Bus.trans_dist::UpgradeResp 64 # Transaction distribution 887system.cpu.toL2Bus.trans_dist::ReadExReq 342489 # Transaction distribution 888system.cpu.toL2Bus.trans_dist::ReadExResp 300938 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution 890system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020220 # Packet count per connected master and slave (bytes) 891system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677927 # Packet count per connected master and slave (bytes) 892system.cpu.toL2Bus.pkt_count::total 5698147 # Packet count per connected master and slave (bytes) 893system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64643392 # Cumulative packet size per connected master and slave (bytes) 894system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586284 # Cumulative packet size per connected master and slave (bytes) 895system.cpu.toL2Bus.tot_pkt_size::total 208229676 # Cumulative packet size per connected master and slave (bytes) 896system.cpu.toL2Bus.data_through_bus 208219628 # Total data (bytes) 897system.cpu.toL2Bus.snoop_data_through_bus 17344 # Total snoop data (bytes) 898system.cpu.toL2Bus.reqLayer0.occupancy 2480508998 # Layer occupancy (ticks) |
| 863system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 864system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 865system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 899system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 900system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 901system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 866system.cpu.toL2Bus.respLayer0.occupancy 1516414125 # Layer occupancy (ticks) | 902system.cpu.toL2Bus.respLayer0.occupancy 1518532368 # Layer occupancy (ticks) |
| 867system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 903system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 868system.cpu.toL2Bus.respLayer1.occupancy 2186111163 # Layer occupancy (ticks) | 904system.cpu.toL2Bus.respLayer1.occupancy 2189805164 # Layer occupancy (ticks) |
| 869system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 905system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 870system.cpu.icache.tags.replacements 1008048 # number of replacements 871system.cpu.icache.tags.tagsinuse 509.665585 # Cycle average of tags in use 872system.cpu.icache.tags.total_refs 7476650 # Total number of references to valid blocks. 873system.cpu.icache.tags.sampled_refs 1008556 # Sample count of references to valid blocks. 874system.cpu.icache.tags.avg_refs 7.413222 # Average number of references to valid blocks. 875system.cpu.icache.tags.warmup_cycle 26682759250 # Cycle when the warmup percentage was hit. 876system.cpu.icache.tags.occ_blocks::cpu.inst 509.665585 # Average occupied blocks per requestor 877system.cpu.icache.tags.occ_percent::cpu.inst 0.995441 # Average percentage of cache occupancy 878system.cpu.icache.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy | 906system.cpu.icache.tags.replacements 1009436 # number of replacements 907system.cpu.icache.tags.tagsinuse 509.668112 # Cycle average of tags in use 908system.cpu.icache.tags.total_refs 7476172 # Total number of references to valid blocks. 909system.cpu.icache.tags.sampled_refs 1009944 # Sample count of references to valid blocks. 910system.cpu.icache.tags.avg_refs 7.402561 # Average number of references to valid blocks. 911system.cpu.icache.tags.warmup_cycle 26651967250 # Cycle when the warmup percentage was hit. 912system.cpu.icache.tags.occ_blocks::cpu.inst 509.668112 # Average occupied blocks per requestor 913system.cpu.icache.tags.occ_percent::cpu.inst 0.995446 # Average percentage of cache occupancy 914system.cpu.icache.tags.occ_percent::total 0.995446 # Average percentage of cache occupancy |
| 879system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id | 915system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id |
| 880system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 881system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 882system.cpu.icache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id | 916system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 917system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id 918system.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id |
| 883system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id | 919system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id |
| 884system.cpu.icache.tags.tag_accesses 9550236 # Number of tag accesses 885system.cpu.icache.tags.data_accesses 9550236 # Number of data accesses 886system.cpu.icache.ReadReq_hits::cpu.inst 7476651 # number of ReadReq hits 887system.cpu.icache.ReadReq_hits::total 7476651 # number of ReadReq hits 888system.cpu.icache.demand_hits::cpu.inst 7476651 # number of demand (read+write) hits 889system.cpu.icache.demand_hits::total 7476651 # number of demand (read+write) hits 890system.cpu.icache.overall_hits::cpu.inst 7476651 # number of overall hits 891system.cpu.icache.overall_hits::total 7476651 # number of overall hits 892system.cpu.icache.ReadReq_misses::cpu.inst 1064809 # number of ReadReq misses 893system.cpu.icache.ReadReq_misses::total 1064809 # number of ReadReq misses 894system.cpu.icache.demand_misses::cpu.inst 1064809 # number of demand (read+write) misses 895system.cpu.icache.demand_misses::total 1064809 # number of demand (read+write) misses 896system.cpu.icache.overall_misses::cpu.inst 1064809 # number of overall misses 897system.cpu.icache.overall_misses::total 1064809 # number of overall misses 898system.cpu.icache.ReadReq_miss_latency::cpu.inst 14791038698 # number of ReadReq miss cycles 899system.cpu.icache.ReadReq_miss_latency::total 14791038698 # number of ReadReq miss cycles 900system.cpu.icache.demand_miss_latency::cpu.inst 14791038698 # number of demand (read+write) miss cycles 901system.cpu.icache.demand_miss_latency::total 14791038698 # number of demand (read+write) miss cycles 902system.cpu.icache.overall_miss_latency::cpu.inst 14791038698 # number of overall miss cycles 903system.cpu.icache.overall_miss_latency::total 14791038698 # number of overall miss cycles 904system.cpu.icache.ReadReq_accesses::cpu.inst 8541460 # number of ReadReq accesses(hits+misses) 905system.cpu.icache.ReadReq_accesses::total 8541460 # number of ReadReq accesses(hits+misses) 906system.cpu.icache.demand_accesses::cpu.inst 8541460 # number of demand (read+write) accesses 907system.cpu.icache.demand_accesses::total 8541460 # number of demand (read+write) accesses 908system.cpu.icache.overall_accesses::cpu.inst 8541460 # number of overall (read+write) accesses 909system.cpu.icache.overall_accesses::total 8541460 # number of overall (read+write) accesses 910system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124664 # miss rate for ReadReq accesses 911system.cpu.icache.ReadReq_miss_rate::total 0.124664 # miss rate for ReadReq accesses 912system.cpu.icache.demand_miss_rate::cpu.inst 0.124664 # miss rate for demand accesses 913system.cpu.icache.demand_miss_rate::total 0.124664 # miss rate for demand accesses 914system.cpu.icache.overall_miss_rate::cpu.inst 0.124664 # miss rate for overall accesses 915system.cpu.icache.overall_miss_rate::total 0.124664 # miss rate for overall accesses 916system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13890.790459 # average ReadReq miss latency 917system.cpu.icache.ReadReq_avg_miss_latency::total 13890.790459 # average ReadReq miss latency 918system.cpu.icache.demand_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency 919system.cpu.icache.demand_avg_miss_latency::total 13890.790459 # average overall miss latency 920system.cpu.icache.overall_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency 921system.cpu.icache.overall_avg_miss_latency::total 13890.790459 # average overall miss latency 922system.cpu.icache.blocked_cycles::no_mshrs 5929 # number of cycles access was blocked 923system.cpu.icache.blocked_cycles::no_targets 286 # number of cycles access was blocked | 920system.cpu.icache.tags.tag_accesses 9552342 # Number of tag accesses 921system.cpu.icache.tags.data_accesses 9552342 # Number of data accesses 922system.cpu.icache.ReadReq_hits::cpu.inst 7476173 # number of ReadReq hits 923system.cpu.icache.ReadReq_hits::total 7476173 # number of ReadReq hits 924system.cpu.icache.demand_hits::cpu.inst 7476173 # number of demand (read+write) hits 925system.cpu.icache.demand_hits::total 7476173 # number of demand (read+write) hits 926system.cpu.icache.overall_hits::cpu.inst 7476173 # number of overall hits 927system.cpu.icache.overall_hits::total 7476173 # number of overall hits 928system.cpu.icache.ReadReq_misses::cpu.inst 1066002 # number of ReadReq misses 929system.cpu.icache.ReadReq_misses::total 1066002 # number of ReadReq misses 930system.cpu.icache.demand_misses::cpu.inst 1066002 # number of demand (read+write) misses 931system.cpu.icache.demand_misses::total 1066002 # number of demand (read+write) misses 932system.cpu.icache.overall_misses::cpu.inst 1066002 # number of overall misses 933system.cpu.icache.overall_misses::total 1066002 # number of overall misses 934system.cpu.icache.ReadReq_miss_latency::cpu.inst 14786308436 # number of ReadReq miss cycles 935system.cpu.icache.ReadReq_miss_latency::total 14786308436 # number of ReadReq miss cycles 936system.cpu.icache.demand_miss_latency::cpu.inst 14786308436 # number of demand (read+write) miss cycles 937system.cpu.icache.demand_miss_latency::total 14786308436 # number of demand (read+write) miss cycles 938system.cpu.icache.overall_miss_latency::cpu.inst 14786308436 # number of overall miss cycles 939system.cpu.icache.overall_miss_latency::total 14786308436 # number of overall miss cycles 940system.cpu.icache.ReadReq_accesses::cpu.inst 8542175 # number of ReadReq accesses(hits+misses) 941system.cpu.icache.ReadReq_accesses::total 8542175 # number of ReadReq accesses(hits+misses) 942system.cpu.icache.demand_accesses::cpu.inst 8542175 # number of demand (read+write) accesses 943system.cpu.icache.demand_accesses::total 8542175 # number of demand (read+write) accesses 944system.cpu.icache.overall_accesses::cpu.inst 8542175 # number of overall (read+write) accesses 945system.cpu.icache.overall_accesses::total 8542175 # number of overall (read+write) accesses 946system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124793 # miss rate for ReadReq accesses 947system.cpu.icache.ReadReq_miss_rate::total 0.124793 # miss rate for ReadReq accesses 948system.cpu.icache.demand_miss_rate::cpu.inst 0.124793 # miss rate for demand accesses 949system.cpu.icache.demand_miss_rate::total 0.124793 # miss rate for demand accesses 950system.cpu.icache.overall_miss_rate::cpu.inst 0.124793 # miss rate for overall accesses 951system.cpu.icache.overall_miss_rate::total 0.124793 # miss rate for overall accesses 952system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13870.807406 # average ReadReq miss latency 953system.cpu.icache.ReadReq_avg_miss_latency::total 13870.807406 # average ReadReq miss latency 954system.cpu.icache.demand_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency 955system.cpu.icache.demand_avg_miss_latency::total 13870.807406 # average overall miss latency 956system.cpu.icache.overall_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency 957system.cpu.icache.overall_avg_miss_latency::total 13870.807406 # average overall miss latency 958system.cpu.icache.blocked_cycles::no_mshrs 4221 # number of cycles access was blocked 959system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 924system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked | 960system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked |
| 925system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 926system.cpu.icache.avg_blocked_cycles::no_mshrs 32.398907 # average number of cycles each access was blocked 927system.cpu.icache.avg_blocked_cycles::no_targets 286 # average number of cycles each access was blocked | 961system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 962system.cpu.icache.avg_blocked_cycles::no_mshrs 23.065574 # average number of cycles each access was blocked 963system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 928system.cpu.icache.fast_writes 0 # number of fast writes performed 929system.cpu.icache.cache_copies 0 # number of cache copies performed | 964system.cpu.icache.fast_writes 0 # number of fast writes performed 965system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 930system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56033 # number of ReadReq MSHR hits 931system.cpu.icache.ReadReq_mshr_hits::total 56033 # number of ReadReq MSHR hits 932system.cpu.icache.demand_mshr_hits::cpu.inst 56033 # number of demand (read+write) MSHR hits 933system.cpu.icache.demand_mshr_hits::total 56033 # number of demand (read+write) MSHR hits 934system.cpu.icache.overall_mshr_hits::cpu.inst 56033 # number of overall MSHR hits 935system.cpu.icache.overall_mshr_hits::total 56033 # number of overall MSHR hits 936system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008776 # number of ReadReq MSHR misses 937system.cpu.icache.ReadReq_mshr_misses::total 1008776 # number of ReadReq MSHR misses 938system.cpu.icache.demand_mshr_misses::cpu.inst 1008776 # number of demand (read+write) MSHR misses 939system.cpu.icache.demand_mshr_misses::total 1008776 # number of demand (read+write) MSHR misses 940system.cpu.icache.overall_mshr_misses::cpu.inst 1008776 # number of overall MSHR misses 941system.cpu.icache.overall_mshr_misses::total 1008776 # number of overall MSHR misses 942system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12131918870 # number of ReadReq MSHR miss cycles 943system.cpu.icache.ReadReq_mshr_miss_latency::total 12131918870 # number of ReadReq MSHR miss cycles 944system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12131918870 # number of demand (read+write) MSHR miss cycles 945system.cpu.icache.demand_mshr_miss_latency::total 12131918870 # number of demand (read+write) MSHR miss cycles 946system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12131918870 # number of overall MSHR miss cycles 947system.cpu.icache.overall_mshr_miss_latency::total 12131918870 # number of overall MSHR miss cycles 948system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118103 # mshr miss rate for ReadReq accesses 949system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118103 # mshr miss rate for ReadReq accesses 950system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118103 # mshr miss rate for demand accesses 951system.cpu.icache.demand_mshr_miss_rate::total 0.118103 # mshr miss rate for demand accesses 952system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118103 # mshr miss rate for overall accesses 953system.cpu.icache.overall_mshr_miss_rate::total 0.118103 # mshr miss rate for overall accesses 954system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.375399 # average ReadReq mshr miss latency 955system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.375399 # average ReadReq mshr miss latency 956system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.375399 # average overall mshr miss latency 957system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.375399 # average overall mshr miss latency 958system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.375399 # average overall mshr miss latency 959system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.375399 # average overall mshr miss latency | 966system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55835 # number of ReadReq MSHR hits 967system.cpu.icache.ReadReq_mshr_hits::total 55835 # number of ReadReq MSHR hits 968system.cpu.icache.demand_mshr_hits::cpu.inst 55835 # number of demand (read+write) MSHR hits 969system.cpu.icache.demand_mshr_hits::total 55835 # number of demand (read+write) MSHR hits 970system.cpu.icache.overall_mshr_hits::cpu.inst 55835 # number of overall MSHR hits 971system.cpu.icache.overall_mshr_hits::total 55835 # number of overall MSHR hits 972system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010167 # number of ReadReq MSHR misses 973system.cpu.icache.ReadReq_mshr_misses::total 1010167 # number of ReadReq MSHR misses 974system.cpu.icache.demand_mshr_misses::cpu.inst 1010167 # number of demand (read+write) MSHR misses 975system.cpu.icache.demand_mshr_misses::total 1010167 # number of demand (read+write) MSHR misses 976system.cpu.icache.overall_mshr_misses::cpu.inst 1010167 # number of overall MSHR misses 977system.cpu.icache.overall_mshr_misses::total 1010167 # number of overall MSHR misses 978system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12133097628 # number of ReadReq MSHR miss cycles 979system.cpu.icache.ReadReq_mshr_miss_latency::total 12133097628 # number of ReadReq MSHR miss cycles 980system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12133097628 # number of demand (read+write) MSHR miss cycles 981system.cpu.icache.demand_mshr_miss_latency::total 12133097628 # number of demand (read+write) MSHR miss cycles 982system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12133097628 # number of overall MSHR miss cycles 983system.cpu.icache.overall_mshr_miss_latency::total 12133097628 # number of overall MSHR miss cycles 984system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for ReadReq accesses 985system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118256 # mshr miss rate for ReadReq accesses 986system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for demand accesses 987system.cpu.icache.demand_mshr_miss_rate::total 0.118256 # mshr miss rate for demand accesses 988system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for overall accesses 989system.cpu.icache.overall_mshr_miss_rate::total 0.118256 # mshr miss rate for overall accesses 990system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12010.981974 # average ReadReq mshr miss latency 991system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12010.981974 # average ReadReq mshr miss latency 992system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency 993system.cpu.icache.demand_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency 994system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency 995system.cpu.icache.overall_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency |
| 960system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 996system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 961system.cpu.l2cache.tags.replacements 338266 # number of replacements 962system.cpu.l2cache.tags.tagsinuse 65338.058683 # Cycle average of tags in use 963system.cpu.l2cache.tags.total_refs 2543929 # Total number of references to valid blocks. 964system.cpu.l2cache.tags.sampled_refs 403433 # Sample count of references to valid blocks. 965system.cpu.l2cache.tags.avg_refs 6.305704 # Average number of references to valid blocks. 966system.cpu.l2cache.tags.warmup_cycle 5551710750 # Cycle when the warmup percentage was hit. 967system.cpu.l2cache.tags.occ_blocks::writebacks 53796.698722 # Average occupied blocks per requestor 968system.cpu.l2cache.tags.occ_blocks::cpu.inst 5304.345669 # Average occupied blocks per requestor 969system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.014293 # Average occupied blocks per requestor 970system.cpu.l2cache.tags.occ_percent::writebacks 0.820872 # Average percentage of cache occupancy 971system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080938 # Average percentage of cache occupancy 972system.cpu.l2cache.tags.occ_percent::cpu.data 0.095169 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_percent::total 0.996980 # Average percentage of cache occupancy 974system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3493 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3306 # Occupied blocks per task id | 997system.cpu.l2cache.tags.replacements 338321 # number of replacements 998system.cpu.l2cache.tags.tagsinuse 65341.789916 # Cycle average of tags in use 999system.cpu.l2cache.tags.total_refs 2546336 # Total number of references to valid blocks. 1000system.cpu.l2cache.tags.sampled_refs 403490 # Sample count of references to valid blocks. 1001system.cpu.l2cache.tags.avg_refs 6.310778 # Average number of references to valid blocks. 1002system.cpu.l2cache.tags.warmup_cycle 5544203750 # Cycle when the warmup percentage was hit. 1003system.cpu.l2cache.tags.occ_blocks::writebacks 53907.448463 # Average occupied blocks per requestor 1004system.cpu.l2cache.tags.occ_blocks::cpu.inst 5292.784095 # Average occupied blocks per requestor 1005system.cpu.l2cache.tags.occ_blocks::cpu.data 6141.557358 # Average occupied blocks per requestor 1006system.cpu.l2cache.tags.occ_percent::writebacks 0.822562 # Average percentage of cache occupancy 1007system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080761 # Average percentage of cache occupancy 1008system.cpu.l2cache.tags.occ_percent::cpu.data 0.093713 # Average percentage of cache occupancy 1009system.cpu.l2cache.tags.occ_percent::total 0.997037 # Average percentage of cache occupancy 1010system.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id 1011system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id 1012system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3494 # Occupied blocks per task id 1013system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3325 # Occupied blocks per task id |
| 978system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id | 1014system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id |
| 979system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55462 # Occupied blocks per task id 980system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id 981system.cpu.l2cache.tags.tag_accesses 26707389 # Number of tag accesses 982system.cpu.l2cache.tags.data_accesses 26707389 # Number of data accesses 983system.cpu.l2cache.ReadReq_hits::cpu.inst 993608 # number of ReadReq hits 984system.cpu.l2cache.ReadReq_hits::cpu.data 826462 # number of ReadReq hits 985system.cpu.l2cache.ReadReq_hits::total 1820070 # number of ReadReq hits 986system.cpu.l2cache.Writeback_hits::writebacks 840541 # number of Writeback hits 987system.cpu.l2cache.Writeback_hits::total 840541 # number of Writeback hits 988system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 989system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 990system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits 991system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 992system.cpu.l2cache.ReadExReq_hits::cpu.data 185429 # number of ReadExReq hits 993system.cpu.l2cache.ReadExReq_hits::total 185429 # number of ReadExReq hits 994system.cpu.l2cache.demand_hits::cpu.inst 993608 # number of demand (read+write) hits 995system.cpu.l2cache.demand_hits::cpu.data 1011891 # number of demand (read+write) hits 996system.cpu.l2cache.demand_hits::total 2005499 # number of demand (read+write) hits 997system.cpu.l2cache.overall_hits::cpu.inst 993608 # number of overall hits 998system.cpu.l2cache.overall_hits::cpu.data 1011891 # number of overall hits 999system.cpu.l2cache.overall_hits::total 2005499 # number of overall hits 1000system.cpu.l2cache.ReadReq_misses::cpu.inst 15053 # number of ReadReq misses 1001system.cpu.l2cache.ReadReq_misses::cpu.data 273771 # number of ReadReq misses 1002system.cpu.l2cache.ReadReq_misses::total 288824 # number of ReadReq misses 1003system.cpu.l2cache.UpgradeReq_misses::cpu.data 42 # number of UpgradeReq misses 1004system.cpu.l2cache.UpgradeReq_misses::total 42 # number of UpgradeReq misses 1005system.cpu.l2cache.ReadExReq_misses::cpu.data 115427 # number of ReadExReq misses 1006system.cpu.l2cache.ReadExReq_misses::total 115427 # number of ReadExReq misses 1007system.cpu.l2cache.demand_misses::cpu.inst 15053 # number of demand (read+write) misses 1008system.cpu.l2cache.demand_misses::cpu.data 389198 # number of demand (read+write) misses 1009system.cpu.l2cache.demand_misses::total 404251 # number of demand (read+write) misses 1010system.cpu.l2cache.overall_misses::cpu.inst 15053 # number of overall misses 1011system.cpu.l2cache.overall_misses::cpu.data 389198 # number of overall misses 1012system.cpu.l2cache.overall_misses::total 404251 # number of overall misses 1013system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1161439993 # number of ReadReq miss cycles 1014system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17964720233 # number of ReadReq miss cycles 1015system.cpu.l2cache.ReadReq_miss_latency::total 19126160226 # number of ReadReq miss cycles 1016system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262498 # number of UpgradeReq miss cycles 1017system.cpu.l2cache.UpgradeReq_miss_latency::total 262498 # number of UpgradeReq miss cycles 1018system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9625411610 # number of ReadExReq miss cycles 1019system.cpu.l2cache.ReadExReq_miss_latency::total 9625411610 # number of ReadExReq miss cycles 1020system.cpu.l2cache.demand_miss_latency::cpu.inst 1161439993 # number of demand (read+write) miss cycles 1021system.cpu.l2cache.demand_miss_latency::cpu.data 27590131843 # number of demand (read+write) miss cycles 1022system.cpu.l2cache.demand_miss_latency::total 28751571836 # number of demand (read+write) miss cycles 1023system.cpu.l2cache.overall_miss_latency::cpu.inst 1161439993 # number of overall miss cycles 1024system.cpu.l2cache.overall_miss_latency::cpu.data 27590131843 # number of overall miss cycles 1025system.cpu.l2cache.overall_miss_latency::total 28751571836 # number of overall miss cycles 1026system.cpu.l2cache.ReadReq_accesses::cpu.inst 1008661 # number of ReadReq accesses(hits+misses) 1027system.cpu.l2cache.ReadReq_accesses::cpu.data 1100233 # number of ReadReq accesses(hits+misses) 1028system.cpu.l2cache.ReadReq_accesses::total 2108894 # number of ReadReq accesses(hits+misses) 1029system.cpu.l2cache.Writeback_accesses::writebacks 840541 # number of Writeback accesses(hits+misses) 1030system.cpu.l2cache.Writeback_accesses::total 840541 # number of Writeback accesses(hits+misses) | 1015system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55443 # Occupied blocks per task id 1016system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id 1017system.cpu.l2cache.tags.tag_accesses 26727783 # Number of tag accesses 1018system.cpu.l2cache.tags.data_accesses 26727783 # Number of data accesses 1019system.cpu.l2cache.ReadReq_hits::cpu.inst 995001 # number of ReadReq hits 1020system.cpu.l2cache.ReadReq_hits::cpu.data 827094 # number of ReadReq hits 1021system.cpu.l2cache.ReadReq_hits::total 1822095 # number of ReadReq hits 1022system.cpu.l2cache.Writeback_hits::writebacks 840946 # number of Writeback hits 1023system.cpu.l2cache.Writeback_hits::total 840946 # number of Writeback hits 1024system.cpu.l2cache.UpgradeReq_hits::cpu.data 27 # number of UpgradeReq hits 1025system.cpu.l2cache.UpgradeReq_hits::total 27 # number of UpgradeReq hits 1026system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1027system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1028system.cpu.l2cache.ReadExReq_hits::cpu.data 185467 # number of ReadExReq hits 1029system.cpu.l2cache.ReadExReq_hits::total 185467 # number of ReadExReq hits 1030system.cpu.l2cache.demand_hits::cpu.inst 995001 # number of demand (read+write) hits 1031system.cpu.l2cache.demand_hits::cpu.data 1012561 # number of demand (read+write) hits 1032system.cpu.l2cache.demand_hits::total 2007562 # number of demand (read+write) hits 1033system.cpu.l2cache.overall_hits::cpu.inst 995001 # number of overall hits 1034system.cpu.l2cache.overall_hits::cpu.data 1012561 # number of overall hits 1035system.cpu.l2cache.overall_hits::total 2007562 # number of overall hits 1036system.cpu.l2cache.ReadReq_misses::cpu.inst 15052 # number of ReadReq misses 1037system.cpu.l2cache.ReadReq_misses::cpu.data 273790 # number of ReadReq misses 1038system.cpu.l2cache.ReadReq_misses::total 288842 # number of ReadReq misses 1039system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses 1040system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses 1041system.cpu.l2cache.ReadExReq_misses::cpu.data 115470 # number of ReadExReq misses 1042system.cpu.l2cache.ReadExReq_misses::total 115470 # number of ReadExReq misses 1043system.cpu.l2cache.demand_misses::cpu.inst 15052 # number of demand (read+write) misses 1044system.cpu.l2cache.demand_misses::cpu.data 389260 # number of demand (read+write) misses 1045system.cpu.l2cache.demand_misses::total 404312 # number of demand (read+write) misses 1046system.cpu.l2cache.overall_misses::cpu.inst 15052 # number of overall misses 1047system.cpu.l2cache.overall_misses::cpu.data 389260 # number of overall misses 1048system.cpu.l2cache.overall_misses::total 404312 # number of overall misses 1049system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1147195743 # number of ReadReq miss cycles 1050system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17910681229 # number of ReadReq miss cycles 1051system.cpu.l2cache.ReadReq_miss_latency::total 19057876972 # number of ReadReq miss cycles 1052system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262998 # number of UpgradeReq miss cycles 1053system.cpu.l2cache.UpgradeReq_miss_latency::total 262998 # number of UpgradeReq miss cycles 1054system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9445420357 # number of ReadExReq miss cycles 1055system.cpu.l2cache.ReadExReq_miss_latency::total 9445420357 # number of ReadExReq miss cycles 1056system.cpu.l2cache.demand_miss_latency::cpu.inst 1147195743 # number of demand (read+write) miss cycles 1057system.cpu.l2cache.demand_miss_latency::cpu.data 27356101586 # number of demand (read+write) miss cycles 1058system.cpu.l2cache.demand_miss_latency::total 28503297329 # number of demand (read+write) miss cycles 1059system.cpu.l2cache.overall_miss_latency::cpu.inst 1147195743 # number of overall miss cycles 1060system.cpu.l2cache.overall_miss_latency::cpu.data 27356101586 # number of overall miss cycles 1061system.cpu.l2cache.overall_miss_latency::total 28503297329 # number of overall miss cycles 1062system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010053 # number of ReadReq accesses(hits+misses) 1063system.cpu.l2cache.ReadReq_accesses::cpu.data 1100884 # number of ReadReq accesses(hits+misses) 1064system.cpu.l2cache.ReadReq_accesses::total 2110937 # number of ReadReq accesses(hits+misses) 1065system.cpu.l2cache.Writeback_accesses::writebacks 840946 # number of Writeback accesses(hits+misses) 1066system.cpu.l2cache.Writeback_accesses::total 840946 # number of Writeback accesses(hits+misses) |
| 1031system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses) 1032system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses) | 1067system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses) 1068system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses) |
| 1033system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 1034system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 1035system.cpu.l2cache.ReadExReq_accesses::cpu.data 300856 # number of ReadExReq accesses(hits+misses) 1036system.cpu.l2cache.ReadExReq_accesses::total 300856 # number of ReadExReq accesses(hits+misses) 1037system.cpu.l2cache.demand_accesses::cpu.inst 1008661 # number of demand (read+write) accesses 1038system.cpu.l2cache.demand_accesses::cpu.data 1401089 # number of demand (read+write) accesses 1039system.cpu.l2cache.demand_accesses::total 2409750 # number of demand (read+write) accesses 1040system.cpu.l2cache.overall_accesses::cpu.inst 1008661 # number of overall (read+write) accesses 1041system.cpu.l2cache.overall_accesses::cpu.data 1401089 # number of overall (read+write) accesses 1042system.cpu.l2cache.overall_accesses::total 2409750 # number of overall (read+write) accesses 1043system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014924 # miss rate for ReadReq accesses 1044system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248830 # miss rate for ReadReq accesses 1045system.cpu.l2cache.ReadReq_miss_rate::total 0.136955 # miss rate for ReadReq accesses 1046system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.677419 # miss rate for UpgradeReq accesses 1047system.cpu.l2cache.UpgradeReq_miss_rate::total 0.677419 # miss rate for UpgradeReq accesses 1048system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383662 # miss rate for ReadExReq accesses 1049system.cpu.l2cache.ReadExReq_miss_rate::total 0.383662 # miss rate for ReadExReq accesses 1050system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014924 # miss rate for demand accesses 1051system.cpu.l2cache.demand_miss_rate::cpu.data 0.277782 # miss rate for demand accesses 1052system.cpu.l2cache.demand_miss_rate::total 0.167756 # miss rate for demand accesses 1053system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014924 # miss rate for overall accesses 1054system.cpu.l2cache.overall_miss_rate::cpu.data 0.277782 # miss rate for overall accesses 1055system.cpu.l2cache.overall_miss_rate::total 0.167756 # miss rate for overall accesses 1056system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77156.712483 # average ReadReq miss latency 1057system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65619.514971 # average ReadReq miss latency 1058system.cpu.l2cache.ReadReq_avg_miss_latency::total 66220.813457 # average ReadReq miss latency 1059system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6249.952381 # average UpgradeReq miss latency 1060system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6249.952381 # average UpgradeReq miss latency 1061system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83389.602173 # average ReadExReq miss latency 1062system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83389.602173 # average ReadExReq miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77156.712483 # average overall miss latency 1064system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70889.706121 # average overall miss latency 1065system.cpu.l2cache.demand_avg_miss_latency::total 71123.069172 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77156.712483 # average overall miss latency 1067system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70889.706121 # average overall miss latency 1068system.cpu.l2cache.overall_avg_miss_latency::total 71123.069172 # average overall miss latency | 1069system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1070system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 1071system.cpu.l2cache.ReadExReq_accesses::cpu.data 300937 # number of ReadExReq accesses(hits+misses) 1072system.cpu.l2cache.ReadExReq_accesses::total 300937 # number of ReadExReq accesses(hits+misses) 1073system.cpu.l2cache.demand_accesses::cpu.inst 1010053 # number of demand (read+write) accesses 1074system.cpu.l2cache.demand_accesses::cpu.data 1401821 # number of demand (read+write) accesses 1075system.cpu.l2cache.demand_accesses::total 2411874 # number of demand (read+write) accesses 1076system.cpu.l2cache.overall_accesses::cpu.inst 1010053 # number of overall (read+write) accesses 1077system.cpu.l2cache.overall_accesses::cpu.data 1401821 # number of overall (read+write) accesses 1078system.cpu.l2cache.overall_accesses::total 2411874 # number of overall (read+write) accesses 1079system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014902 # miss rate for ReadReq accesses 1080system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248700 # miss rate for ReadReq accesses 1081system.cpu.l2cache.ReadReq_miss_rate::total 0.136831 # miss rate for ReadReq accesses 1082system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.564516 # miss rate for UpgradeReq accesses 1083system.cpu.l2cache.UpgradeReq_miss_rate::total 0.564516 # miss rate for UpgradeReq accesses 1084system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383702 # miss rate for ReadExReq accesses 1085system.cpu.l2cache.ReadExReq_miss_rate::total 0.383702 # miss rate for ReadExReq accesses 1086system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014902 # miss rate for demand accesses 1087system.cpu.l2cache.demand_miss_rate::cpu.data 0.277682 # miss rate for demand accesses 1088system.cpu.l2cache.demand_miss_rate::total 0.167634 # miss rate for demand accesses 1089system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014902 # miss rate for overall accesses 1090system.cpu.l2cache.overall_miss_rate::cpu.data 0.277682 # miss rate for overall accesses 1091system.cpu.l2cache.overall_miss_rate::total 0.167634 # miss rate for overall accesses 1092system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76215.502458 # average ReadReq miss latency 1093system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65417.587308 # average ReadReq miss latency 1094system.cpu.l2cache.ReadReq_avg_miss_latency::total 65980.283241 # average ReadReq miss latency 1095system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7514.228571 # average UpgradeReq miss latency 1096system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7514.228571 # average UpgradeReq miss latency 1097system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81799.777925 # average ReadExReq miss latency 1098system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81799.777925 # average ReadExReq miss latency 1099system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76215.502458 # average overall miss latency 1100system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70277.196696 # average overall miss latency 1101system.cpu.l2cache.demand_avg_miss_latency::total 70498.271951 # average overall miss latency 1102system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76215.502458 # average overall miss latency 1103system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70277.196696 # average overall miss latency 1104system.cpu.l2cache.overall_avg_miss_latency::total 70498.271951 # average overall miss latency |
| 1069system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1070system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1071system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1072system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1073system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1074system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1075system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1076system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1105system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1106system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1107system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1108system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1109system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1110system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1111system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1112system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1077system.cpu.l2cache.writebacks::writebacks 75916 # number of writebacks 1078system.cpu.l2cache.writebacks::total 75916 # number of writebacks | 1113system.cpu.l2cache.writebacks::writebacks 75935 # number of writebacks 1114system.cpu.l2cache.writebacks::total 75935 # number of writebacks |
| 1079system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1080system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1081system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1082system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1083system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1084system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits | 1115system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1116system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1117system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1118system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1119system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1120system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 1085system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15052 # number of ReadReq MSHR misses 1086system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273771 # number of ReadReq MSHR misses 1087system.cpu.l2cache.ReadReq_mshr_misses::total 288823 # number of ReadReq MSHR misses 1088system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 42 # number of UpgradeReq MSHR misses 1089system.cpu.l2cache.UpgradeReq_mshr_misses::total 42 # number of UpgradeReq MSHR misses 1090system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115427 # number of ReadExReq MSHR misses 1091system.cpu.l2cache.ReadExReq_mshr_misses::total 115427 # number of ReadExReq MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 15052 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.demand_mshr_misses::cpu.data 389198 # number of demand (read+write) MSHR misses 1094system.cpu.l2cache.demand_mshr_misses::total 404250 # number of demand (read+write) MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 15052 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.data 389198 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::total 404250 # number of overall MSHR misses 1098system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 971628757 # number of ReadReq MSHR miss cycles 1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14552447267 # number of ReadReq MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15524076024 # number of ReadReq MSHR miss cycles 1101system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 573037 # number of UpgradeReq MSHR miss cycles 1102system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 573037 # number of UpgradeReq MSHR miss cycles 1103system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8203174390 # number of ReadExReq MSHR miss cycles 1104system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8203174390 # number of ReadExReq MSHR miss cycles 1105system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 971628757 # number of demand (read+write) MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22755621657 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::total 23727250414 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 971628757 # number of overall MSHR miss cycles 1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22755621657 # number of overall MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::total 23727250414 # number of overall MSHR miss cycles 1111system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334007000 # number of ReadReq MSHR uncacheable cycles 1112system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334007000 # number of ReadReq MSHR uncacheable cycles 1113system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882413000 # number of WriteReq MSHR uncacheable cycles 1114system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882413000 # 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number of overall MSHR misses 1134system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 957328507 # number of ReadReq MSHR miss cycles 1135system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14497719271 # number of ReadReq MSHR miss cycles 1136system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15455047778 # number of ReadReq MSHR miss cycles 1137system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 500032 # number of UpgradeReq MSHR miss cycles 1138system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 500032 # number of UpgradeReq MSHR miss cycles 1139system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8018115143 # number of ReadExReq MSHR miss cycles 1140system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8018115143 # number of ReadExReq MSHR miss cycles 1141system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 957328507 # number of demand (read+write) MSHR miss cycles 1142system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22515834414 # number of demand (read+write) MSHR miss cycles 1143system.cpu.l2cache.demand_mshr_miss_latency::total 23473162921 # number of demand (read+write) MSHR miss cycles 1144system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 957328507 # number of overall MSHR miss cycles 1145system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22515834414 # number of overall MSHR miss cycles 1146system.cpu.l2cache.overall_mshr_miss_latency::total 23473162921 # number of overall MSHR miss cycles 1147system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333977500 # number of ReadReq MSHR uncacheable cycles 1148system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333977500 # number of ReadReq MSHR uncacheable cycles 1149system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882390000 # number of WriteReq MSHR uncacheable cycles 1150system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882390000 # number of WriteReq MSHR uncacheable cycles 1151system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216367500 # number of overall MSHR uncacheable cycles 1152system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216367500 # number of overall MSHR uncacheable cycles 1153system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for ReadReq accesses 1154system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248700 # mshr miss rate for ReadReq accesses 1155system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136831 # mshr miss rate for ReadReq accesses 1156system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.564516 # mshr miss rate for UpgradeReq accesses 1157system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.564516 # mshr miss rate for UpgradeReq accesses 1158system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383702 # mshr miss rate for ReadExReq accesses 1159system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383702 # mshr miss rate for ReadExReq accesses 1160system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for demand accesses 1161system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277682 # mshr miss rate for demand accesses 1162system.cpu.l2cache.demand_mshr_miss_rate::total 0.167634 # mshr miss rate for demand accesses 1163system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for overall accesses 1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277682 # mshr miss rate for overall accesses 1165system.cpu.l2cache.overall_mshr_miss_rate::total 0.167634 # mshr miss rate for overall accesses 1166system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63605.641286 # average ReadReq mshr miss latency 1167system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52951.967826 # average ReadReq mshr miss latency 1168system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53507.112141 # average ReadReq mshr miss latency 1169system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14286.628571 # average UpgradeReq mshr miss latency 1170system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14286.628571 # average UpgradeReq mshr miss latency 1171system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69438.946419 # average ReadExReq mshr miss latency 1172system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69438.946419 # average ReadExReq mshr miss latency 1173system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63605.641286 # average overall mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57842.661496 # average overall mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58057.195874 # average overall mshr miss latency 1176system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63605.641286 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57842.661496 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58057.195874 # average overall mshr miss latency |
| 1143system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1144system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1145system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1146system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1147system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1148system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1149system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1179system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1180system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1181system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1182system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1183system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1184system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1185system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1150system.cpu.dcache.tags.replacements 1400496 # number of replacements 1151system.cpu.dcache.tags.tagsinuse 511.994513 # Cycle average of tags in use 1152system.cpu.dcache.tags.total_refs 11811358 # Total number of references to valid blocks. 1153system.cpu.dcache.tags.sampled_refs 1401008 # Sample count of references to valid blocks. 1154system.cpu.dcache.tags.avg_refs 8.430614 # Average number of references to valid blocks. 1155system.cpu.dcache.tags.warmup_cycle 25856000 # Cycle when the warmup percentage was hit. 1156system.cpu.dcache.tags.occ_blocks::cpu.data 511.994513 # Average occupied blocks per requestor | 1186system.cpu.dcache.tags.replacements 1401230 # number of replacements 1187system.cpu.dcache.tags.tagsinuse 511.994514 # Cycle average of tags in use 1188system.cpu.dcache.tags.total_refs 11803041 # Total number of references to valid blocks. 1189system.cpu.dcache.tags.sampled_refs 1401742 # Sample count of references to valid blocks. 1190system.cpu.dcache.tags.avg_refs 8.420266 # Average number of references to valid blocks. 1191system.cpu.dcache.tags.warmup_cycle 25812000 # Cycle when the warmup percentage was hit. 1192system.cpu.dcache.tags.occ_blocks::cpu.data 511.994514 # Average occupied blocks per requestor |
| 1157system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 1158system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy 1159system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1193system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 1194system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy 1195system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1160system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 1161system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id 1162system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id | 1196system.cpu.dcache.tags.age_task_id_blocks_1024::0 417 # Occupied blocks per task id 1197system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id 1198system.cpu.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id |
| 1163system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1199system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1164system.cpu.dcache.tags.tag_accesses 63734677 # Number of tag accesses 1165system.cpu.dcache.tags.data_accesses 63734677 # Number of data accesses 1166system.cpu.dcache.ReadReq_hits::cpu.data 7206132 # number of ReadReq hits 1167system.cpu.dcache.ReadReq_hits::total 7206132 # number of ReadReq hits 1168system.cpu.dcache.WriteReq_hits::cpu.data 4203012 # number of WriteReq hits 1169system.cpu.dcache.WriteReq_hits::total 4203012 # number of WriteReq hits 1170system.cpu.dcache.LoadLockedReq_hits::cpu.data 186466 # number of LoadLockedReq hits 1171system.cpu.dcache.LoadLockedReq_hits::total 186466 # number of LoadLockedReq hits 1172system.cpu.dcache.StoreCondReq_hits::cpu.data 215515 # number of StoreCondReq hits 1173system.cpu.dcache.StoreCondReq_hits::total 215515 # number of StoreCondReq hits 1174system.cpu.dcache.demand_hits::cpu.data 11409144 # number of demand (read+write) hits 1175system.cpu.dcache.demand_hits::total 11409144 # number of demand (read+write) hits 1176system.cpu.dcache.overall_hits::cpu.data 11409144 # number of overall hits 1177system.cpu.dcache.overall_hits::total 11409144 # number of overall hits 1178system.cpu.dcache.ReadReq_misses::cpu.data 1805019 # number of ReadReq misses 1179system.cpu.dcache.ReadReq_misses::total 1805019 # number of ReadReq misses 1180system.cpu.dcache.WriteReq_misses::cpu.data 1944584 # number of WriteReq misses 1181system.cpu.dcache.WriteReq_misses::total 1944584 # number of WriteReq misses 1182system.cpu.dcache.LoadLockedReq_misses::cpu.data 22688 # number of LoadLockedReq misses 1183system.cpu.dcache.LoadLockedReq_misses::total 22688 # number of LoadLockedReq misses 1184system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 1185system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 1186system.cpu.dcache.demand_misses::cpu.data 3749603 # number of demand (read+write) misses 1187system.cpu.dcache.demand_misses::total 3749603 # number of demand (read+write) misses 1188system.cpu.dcache.overall_misses::cpu.data 3749603 # number of overall misses 1189system.cpu.dcache.overall_misses::total 3749603 # number of overall misses 1190system.cpu.dcache.ReadReq_miss_latency::cpu.data 40356893890 # number of ReadReq miss cycles 1191system.cpu.dcache.ReadReq_miss_latency::total 40356893890 # number of ReadReq miss cycles 1192system.cpu.dcache.WriteReq_miss_latency::cpu.data 77719104532 # number of WriteReq miss cycles 1193system.cpu.dcache.WriteReq_miss_latency::total 77719104532 # number of WriteReq miss cycles 1194system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321753501 # number of LoadLockedReq miss cycles 1195system.cpu.dcache.LoadLockedReq_miss_latency::total 321753501 # number of LoadLockedReq miss cycles 1196system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles 1197system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles 1198system.cpu.dcache.demand_miss_latency::cpu.data 118075998422 # number of demand (read+write) miss cycles 1199system.cpu.dcache.demand_miss_latency::total 118075998422 # number of demand (read+write) miss cycles 1200system.cpu.dcache.overall_miss_latency::cpu.data 118075998422 # number of overall miss cycles 1201system.cpu.dcache.overall_miss_latency::total 118075998422 # number of overall miss cycles 1202system.cpu.dcache.ReadReq_accesses::cpu.data 9011151 # number of ReadReq accesses(hits+misses) 1203system.cpu.dcache.ReadReq_accesses::total 9011151 # number of ReadReq accesses(hits+misses) 1204system.cpu.dcache.WriteReq_accesses::cpu.data 6147596 # number of WriteReq accesses(hits+misses) 1205system.cpu.dcache.WriteReq_accesses::total 6147596 # number of WriteReq accesses(hits+misses) 1206system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209154 # number of LoadLockedReq accesses(hits+misses) 1207system.cpu.dcache.LoadLockedReq_accesses::total 209154 # number of LoadLockedReq accesses(hits+misses) 1208system.cpu.dcache.StoreCondReq_accesses::cpu.data 215516 # number of StoreCondReq accesses(hits+misses) 1209system.cpu.dcache.StoreCondReq_accesses::total 215516 # number of StoreCondReq accesses(hits+misses) 1210system.cpu.dcache.demand_accesses::cpu.data 15158747 # number of demand (read+write) accesses 1211system.cpu.dcache.demand_accesses::total 15158747 # number of demand (read+write) accesses 1212system.cpu.dcache.overall_accesses::cpu.data 15158747 # number of overall (read+write) accesses 1213system.cpu.dcache.overall_accesses::total 15158747 # number of overall (read+write) accesses 1214system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200309 # miss rate for ReadReq accesses 1215system.cpu.dcache.ReadReq_miss_rate::total 0.200309 # miss rate for ReadReq accesses 1216system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316316 # miss rate for WriteReq accesses 1217system.cpu.dcache.WriteReq_miss_rate::total 0.316316 # miss rate for WriteReq accesses 1218system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108475 # miss rate for LoadLockedReq accesses 1219system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108475 # miss rate for LoadLockedReq accesses 1220system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses 1221system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses 1222system.cpu.dcache.demand_miss_rate::cpu.data 0.247356 # miss rate for demand accesses 1223system.cpu.dcache.demand_miss_rate::total 0.247356 # miss rate for demand accesses 1224system.cpu.dcache.overall_miss_rate::cpu.data 0.247356 # miss rate for overall accesses 1225system.cpu.dcache.overall_miss_rate::total 0.247356 # miss rate for overall accesses 1226system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22358.154618 # average ReadReq miss latency 1227system.cpu.dcache.ReadReq_avg_miss_latency::total 22358.154618 # average ReadReq miss latency 1228system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39966.956702 # average WriteReq miss latency 1229system.cpu.dcache.WriteReq_avg_miss_latency::total 39966.956702 # average WriteReq miss latency 1230system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14181.659952 # average LoadLockedReq miss latency 1231system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14181.659952 # average LoadLockedReq miss latency | 1200system.cpu.dcache.tags.tag_accesses 63715251 # Number of tag accesses 1201system.cpu.dcache.tags.data_accesses 63715251 # Number of data accesses 1202system.cpu.dcache.ReadReq_hits::cpu.data 7198260 # number of ReadReq hits 1203system.cpu.dcache.ReadReq_hits::total 7198260 # number of ReadReq hits 1204system.cpu.dcache.WriteReq_hits::cpu.data 4203038 # number of WriteReq hits 1205system.cpu.dcache.WriteReq_hits::total 4203038 # number of WriteReq hits 1206system.cpu.dcache.LoadLockedReq_hits::cpu.data 186010 # number of LoadLockedReq hits 1207system.cpu.dcache.LoadLockedReq_hits::total 186010 # number of LoadLockedReq hits 1208system.cpu.dcache.StoreCondReq_hits::cpu.data 215511 # number of StoreCondReq hits 1209system.cpu.dcache.StoreCondReq_hits::total 215511 # number of StoreCondReq hits 1210system.cpu.dcache.demand_hits::cpu.data 11401298 # number of demand (read+write) hits 1211system.cpu.dcache.demand_hits::total 11401298 # number of demand (read+write) hits 1212system.cpu.dcache.overall_hits::cpu.data 11401298 # number of overall hits 1213system.cpu.dcache.overall_hits::total 11401298 # number of overall hits 1214system.cpu.dcache.ReadReq_misses::cpu.data 1808147 # number of ReadReq misses 1215system.cpu.dcache.ReadReq_misses::total 1808147 # number of ReadReq misses 1216system.cpu.dcache.WriteReq_misses::cpu.data 1944666 # number of WriteReq misses 1217system.cpu.dcache.WriteReq_misses::total 1944666 # number of WriteReq misses 1218system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses 1219system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses 1220system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1221system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 1222system.cpu.dcache.demand_misses::cpu.data 3752813 # number of demand (read+write) misses 1223system.cpu.dcache.demand_misses::total 3752813 # number of demand (read+write) misses 1224system.cpu.dcache.overall_misses::cpu.data 3752813 # number of overall misses 1225system.cpu.dcache.overall_misses::total 3752813 # number of overall misses 1226system.cpu.dcache.ReadReq_miss_latency::cpu.data 40323855155 # number of ReadReq miss cycles 1227system.cpu.dcache.ReadReq_miss_latency::total 40323855155 # number of ReadReq miss cycles 1228system.cpu.dcache.WriteReq_miss_latency::cpu.data 76523868035 # number of WriteReq miss cycles 1229system.cpu.dcache.WriteReq_miss_latency::total 76523868035 # number of WriteReq miss cycles 1230system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322545000 # number of LoadLockedReq miss cycles 1231system.cpu.dcache.LoadLockedReq_miss_latency::total 322545000 # number of LoadLockedReq miss cycles 1232system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles 1233system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles 1234system.cpu.dcache.demand_miss_latency::cpu.data 116847723190 # number of demand (read+write) miss cycles 1235system.cpu.dcache.demand_miss_latency::total 116847723190 # number of demand (read+write) miss cycles 1236system.cpu.dcache.overall_miss_latency::cpu.data 116847723190 # number of overall miss cycles 1237system.cpu.dcache.overall_miss_latency::total 116847723190 # number of overall miss cycles 1238system.cpu.dcache.ReadReq_accesses::cpu.data 9006407 # number of ReadReq accesses(hits+misses) 1239system.cpu.dcache.ReadReq_accesses::total 9006407 # number of ReadReq accesses(hits+misses) 1240system.cpu.dcache.WriteReq_accesses::cpu.data 6147704 # number of WriteReq accesses(hits+misses) 1241system.cpu.dcache.WriteReq_accesses::total 6147704 # number of WriteReq accesses(hits+misses) 1242system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208753 # number of LoadLockedReq accesses(hits+misses) 1243system.cpu.dcache.LoadLockedReq_accesses::total 208753 # number of LoadLockedReq accesses(hits+misses) 1244system.cpu.dcache.StoreCondReq_accesses::cpu.data 215513 # number of StoreCondReq accesses(hits+misses) 1245system.cpu.dcache.StoreCondReq_accesses::total 215513 # number of StoreCondReq accesses(hits+misses) 1246system.cpu.dcache.demand_accesses::cpu.data 15154111 # number of demand (read+write) accesses 1247system.cpu.dcache.demand_accesses::total 15154111 # number of demand (read+write) accesses 1248system.cpu.dcache.overall_accesses::cpu.data 15154111 # number of overall (read+write) accesses 1249system.cpu.dcache.overall_accesses::total 15154111 # number of overall (read+write) accesses 1250system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200762 # miss rate for ReadReq accesses 1251system.cpu.dcache.ReadReq_miss_rate::total 0.200762 # miss rate for ReadReq accesses 1252system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316324 # miss rate for WriteReq accesses 1253system.cpu.dcache.WriteReq_miss_rate::total 0.316324 # miss rate for WriteReq accesses 1254system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108947 # miss rate for LoadLockedReq accesses 1255system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108947 # miss rate for LoadLockedReq accesses 1256system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 1257system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 1258system.cpu.dcache.demand_miss_rate::cpu.data 0.247643 # miss rate for demand accesses 1259system.cpu.dcache.demand_miss_rate::total 0.247643 # miss rate for demand accesses 1260system.cpu.dcache.overall_miss_rate::cpu.data 0.247643 # miss rate for overall accesses 1261system.cpu.dcache.overall_miss_rate::total 0.247643 # miss rate for overall accesses 1262system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025 # average ReadReq miss latency 1263system.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025 # average ReadReq miss latency 1264system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407 # average WriteReq miss latency 1265system.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407 # average WriteReq miss latency 1266system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941 # average LoadLockedReq miss latency 1267system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941 # average LoadLockedReq miss latency |
| 1232system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 1233system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency | 1268system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 1269system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency |
| 1234system.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency 1235system.cpu.dcache.demand_avg_miss_latency::total 31490.266682 # average overall miss latency 1236system.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency 1237system.cpu.dcache.overall_avg_miss_latency::total 31490.266682 # average overall miss latency 1238system.cpu.dcache.blocked_cycles::no_mshrs 3050951 # number of cycles access was blocked 1239system.cpu.dcache.blocked_cycles::no_targets 663 # number of cycles access was blocked 1240system.cpu.dcache.blocked::no_mshrs 86776 # number of cycles access was blocked | 1270system.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency 1271system.cpu.dcache.demand_avg_miss_latency::total 31136.036672 # average overall miss latency 1272system.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency 1273system.cpu.dcache.overall_avg_miss_latency::total 31136.036672 # average overall miss latency 1274system.cpu.dcache.blocked_cycles::no_mshrs 3013190 # number of cycles access was blocked 1275system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked 1276system.cpu.dcache.blocked::no_mshrs 80012 # number of cycles access was blocked |
| 1241system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked | 1277system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 1242system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.158926 # average number of cycles each access was blocked 1243system.cpu.dcache.avg_blocked_cycles::no_targets 94.714286 # average number of cycles each access was blocked | 1278system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.659226 # average number of cycles each access was blocked 1279system.cpu.dcache.avg_blocked_cycles::no_targets 118.428571 # average number of cycles each access was blocked |
| 1244system.cpu.dcache.fast_writes 0 # number of fast writes performed 1245system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1280system.cpu.dcache.fast_writes 0 # number of fast writes performed 1281system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1246system.cpu.dcache.writebacks::writebacks 840541 # number of writebacks 1247system.cpu.dcache.writebacks::total 840541 # number of writebacks 1248system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721694 # number of ReadReq MSHR hits 1249system.cpu.dcache.ReadReq_mshr_hits::total 721694 # number of ReadReq MSHR hits | 1282system.cpu.dcache.writebacks::writebacks 840946 # number of writebacks 1283system.cpu.dcache.writebacks::total 840946 # number of writebacks 1284system.cpu.dcache.ReadReq_mshr_hits::cpu.data 724204 # number of ReadReq MSHR hits 1285system.cpu.dcache.ReadReq_mshr_hits::total 724204 # number of ReadReq MSHR hits |
| 1250system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits 1251system.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits | 1286system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits 1287system.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits |
| 1252system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits 1253system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits 1254system.cpu.dcache.demand_mshr_hits::cpu.data 2366018 # number of demand (read+write) MSHR hits 1255system.cpu.dcache.demand_mshr_hits::total 2366018 # number of demand (read+write) MSHR hits 1256system.cpu.dcache.overall_mshr_hits::cpu.data 2366018 # number of overall MSHR hits 1257system.cpu.dcache.overall_mshr_hits::total 2366018 # number of overall MSHR hits 1258system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083325 # number of ReadReq MSHR misses 1259system.cpu.dcache.ReadReq_mshr_misses::total 1083325 # number of ReadReq MSHR misses 1260system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300260 # number of WriteReq MSHR misses 1261system.cpu.dcache.WriteReq_mshr_misses::total 300260 # number of WriteReq MSHR misses 1262system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17565 # number of LoadLockedReq MSHR misses 1263system.cpu.dcache.LoadLockedReq_mshr_misses::total 17565 # number of LoadLockedReq MSHR misses 1264system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 1265system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 1266system.cpu.dcache.demand_mshr_misses::cpu.data 1383585 # number of demand (read+write) MSHR misses 1267system.cpu.dcache.demand_mshr_misses::total 1383585 # number of demand (read+write) MSHR misses 1268system.cpu.dcache.overall_mshr_misses::cpu.data 1383585 # number of overall MSHR misses 1269system.cpu.dcache.overall_mshr_misses::total 1383585 # number of overall MSHR misses 1270system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27323478009 # number of ReadReq MSHR miss cycles 1271system.cpu.dcache.ReadReq_mshr_miss_latency::total 27323478009 # number of ReadReq MSHR miss cycles 1272system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11844407335 # number of WriteReq MSHR miss cycles 1273system.cpu.dcache.WriteReq_mshr_miss_latency::total 11844407335 # number of WriteReq MSHR miss cycles 1274system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200869499 # number of LoadLockedReq MSHR miss cycles 1275system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200869499 # number of LoadLockedReq MSHR miss cycles 1276system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles 1277system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles 1278system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39167885344 # number of demand (read+write) MSHR miss cycles 1279system.cpu.dcache.demand_mshr_miss_latency::total 39167885344 # number of demand (read+write) MSHR miss cycles 1280system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39167885344 # number of overall MSHR miss cycles 1281system.cpu.dcache.overall_mshr_miss_latency::total 39167885344 # number of overall MSHR miss cycles 1282system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424097000 # number of ReadReq MSHR uncacheable cycles 1283system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424097000 # number of ReadReq MSHR uncacheable cycles 1284system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997590998 # number of WriteReq MSHR uncacheable cycles 1285system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997590998 # number of WriteReq MSHR uncacheable cycles 1286system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421687998 # number of overall MSHR uncacheable cycles 1287system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421687998 # number of overall MSHR uncacheable cycles 1288system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120220 # mshr miss rate for ReadReq accesses 1289system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120220 # mshr miss rate for ReadReq accesses 1290system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048842 # mshr miss rate for WriteReq accesses 1291system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048842 # mshr miss rate for WriteReq accesses 1292system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083981 # mshr miss rate for LoadLockedReq accesses 1293system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083981 # mshr miss rate for LoadLockedReq accesses 1294system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses 1295system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses 1296system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses 1297system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses 1298system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses 1299system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses 1300system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023 # average ReadReq mshr miss latency 1301system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023 # average ReadReq mshr miss latency 1302system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236 # average WriteReq mshr miss latency 1303system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236 # average WriteReq mshr miss latency 1304system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327 # average LoadLockedReq mshr miss latency 1305system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327 # average LoadLockedReq mshr miss latency | 1288system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5146 # number of LoadLockedReq MSHR hits 1289system.cpu.dcache.LoadLockedReq_mshr_hits::total 5146 # number of LoadLockedReq MSHR hits 1290system.cpu.dcache.demand_mshr_hits::cpu.data 2368528 # number of demand (read+write) MSHR hits 1291system.cpu.dcache.demand_mshr_hits::total 2368528 # number of demand (read+write) MSHR hits 1292system.cpu.dcache.overall_mshr_hits::cpu.data 2368528 # number of overall MSHR hits 1293system.cpu.dcache.overall_mshr_hits::total 2368528 # number of overall MSHR hits 1294system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083943 # number of ReadReq MSHR misses 1295system.cpu.dcache.ReadReq_mshr_misses::total 1083943 # number of ReadReq MSHR misses 1296system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300342 # number of WriteReq MSHR misses 1297system.cpu.dcache.WriteReq_mshr_misses::total 300342 # number of WriteReq MSHR misses 1298system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17597 # number of LoadLockedReq MSHR misses 1299system.cpu.dcache.LoadLockedReq_mshr_misses::total 17597 # number of LoadLockedReq MSHR misses 1300system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1301system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 1302system.cpu.dcache.demand_mshr_misses::cpu.data 1384285 # number of demand (read+write) MSHR misses 1303system.cpu.dcache.demand_mshr_misses::total 1384285 # number of demand (read+write) MSHR misses 1304system.cpu.dcache.overall_mshr_misses::cpu.data 1384285 # number of overall MSHR misses 1305system.cpu.dcache.overall_mshr_misses::total 1384285 # number of overall MSHR misses 1306system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275514507 # number of ReadReq MSHR miss cycles 1307system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275514507 # number of ReadReq MSHR miss cycles 1308system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11674414609 # number of WriteReq MSHR miss cycles 1309system.cpu.dcache.WriteReq_mshr_miss_latency::total 11674414609 # number of WriteReq MSHR miss cycles 1310system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201282500 # number of LoadLockedReq MSHR miss cycles 1311system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201282500 # number of LoadLockedReq MSHR miss cycles 1312system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles 1313system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles 1314system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38949929116 # number of demand (read+write) MSHR miss cycles 1315system.cpu.dcache.demand_mshr_miss_latency::total 38949929116 # number of demand (read+write) MSHR miss cycles 1316system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38949929116 # number of overall MSHR miss cycles 1317system.cpu.dcache.overall_mshr_miss_latency::total 38949929116 # number of overall MSHR miss cycles 1318system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424067500 # number of ReadReq MSHR uncacheable cycles 1319system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424067500 # number of ReadReq MSHR uncacheable cycles 1320system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997567998 # number of WriteReq MSHR uncacheable cycles 1321system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997567998 # number of WriteReq MSHR uncacheable cycles 1322system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421635498 # number of overall MSHR uncacheable cycles 1323system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421635498 # number of overall MSHR uncacheable cycles 1324system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120352 # mshr miss rate for ReadReq accesses 1325system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120352 # mshr miss rate for ReadReq accesses 1326system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses 1327system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses 1328system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084296 # mshr miss rate for LoadLockedReq accesses 1329system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084296 # mshr miss rate for LoadLockedReq accesses 1330system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 1331system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 1332system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for demand accesses 1333system.cpu.dcache.demand_mshr_miss_rate::total 0.091347 # mshr miss rate for demand accesses 1334system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for overall accesses 1335system.cpu.dcache.overall_mshr_miss_rate::total 0.091347 # mshr miss rate for overall accesses 1336system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911 # average ReadReq mshr miss latency 1337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911 # average ReadReq mshr miss latency 1338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104 # average WriteReq mshr miss latency 1339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104 # average WriteReq mshr miss latency 1340system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419 # average LoadLockedReq mshr miss latency 1341system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419 # average LoadLockedReq mshr miss latency |
| 1306system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 1307system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency | 1342system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 1343system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency |
| 1308system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency 1309system.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency 1310system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency 1311system.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency | 1344system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency 1345system.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency 1346system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency 1347system.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency |
| 1312system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1313system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1314system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1315system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1316system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1317system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1318system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1319system.cpu.kern.inst.arm 0 # number of arm instructions executed --- 4 unchanged lines hidden (view full) --- 1324system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl 1325system.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl 1326system.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl 1327system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1328system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1329system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl 1330system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1331system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl | 1348system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1349system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1350system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1351system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1352system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1353system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1354system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1355system.cpu.kern.inst.arm 0 # number of arm instructions executed --- 4 unchanged lines hidden (view full) --- 1360system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl 1361system.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl 1362system.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl 1363system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1364system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1365system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl 1366system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1367system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl |
| 1332system.cpu.kern.ipl_ticks::0 1817851866500 97.72% 97.72% # number of cycles we spent at this ipl 1333system.cpu.kern.ipl_ticks::21 64172000 0.00% 97.73% # number of cycles we spent at this ipl 1334system.cpu.kern.ipl_ticks::22 559556500 0.03% 97.76% # number of cycles we spent at this ipl 1335system.cpu.kern.ipl_ticks::31 41715361500 2.24% 100.00% # number of cycles we spent at this ipl 1336system.cpu.kern.ipl_ticks::total 1860190956500 # number of cycles we spent at this ipl | 1368system.cpu.kern.ipl_ticks::0 1817873983000 97.73% 97.73% # number of cycles we spent at this ipl 1369system.cpu.kern.ipl_ticks::21 64184500 0.00% 97.73% # number of cycles we spent at this ipl 1370system.cpu.kern.ipl_ticks::22 553817500 0.03% 97.76% # number of cycles we spent at this ipl 1371system.cpu.kern.ipl_ticks::31 41694992500 2.24% 100.00% # number of cycles we spent at this ipl 1372system.cpu.kern.ipl_ticks::total 1860186977500 # number of cycles we spent at this ipl |
| 1337system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 1338system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1339system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1340system.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl 1341system.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl 1342system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1343system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1344system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed --- 37 unchanged lines hidden (view full) --- 1382system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1383system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1384system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1385system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1386system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 1387system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1388system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 1389system.cpu.kern.callpal::total 191963 # number of callpals executed | 1373system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 1374system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1375system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1376system.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl 1377system.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl 1378system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1379system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1380system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed --- 37 unchanged lines hidden (view full) --- 1418system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1419system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1420system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1421system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1422system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed 1423system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1424system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 1425system.cpu.kern.callpal::total 191963 # number of callpals executed |
| 1390system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches | 1426system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches |
| 1391system.cpu.kern.mode_switch::user 1740 # number of protection mode switches | 1427system.cpu.kern.mode_switch::user 1740 # number of protection mode switches |
| 1392system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches | 1428system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches |
| 1393system.cpu.kern.mode_good::kernel 1910 1394system.cpu.kern.mode_good::user 1740 1395system.cpu.kern.mode_good::idle 170 | 1429system.cpu.kern.mode_good::kernel 1910 1430system.cpu.kern.mode_good::user 1740 1431system.cpu.kern.mode_good::idle 170 |
| 1396system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches | 1432system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches |
| 1397system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1433system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1398system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches | 1434system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches |
| 1399system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches | 1435system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches |
| 1400system.cpu.kern.mode_ticks::kernel 29573655500 1.59% 1.59% # number of ticks spent at the given mode 1401system.cpu.kern.mode_ticks::user 2713841000 0.15% 1.74% # number of ticks spent at the given mode 1402system.cpu.kern.mode_ticks::idle 1827903452000 98.26% 100.00% # number of ticks spent at the given mode | 1436system.cpu.kern.mode_ticks::kernel 29561208000 1.59% 1.59% # number of ticks spent at the given mode 1437system.cpu.kern.mode_ticks::user 2704677000 0.15% 1.73% # number of ticks spent at the given mode 1438system.cpu.kern.mode_ticks::idle 1827921084500 98.27% 100.00% # number of ticks spent at the given mode |
| 1403system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1404 1405---------- End Simulation Statistics ---------- | 1439system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1440 1441---------- End Simulation Statistics ---------- |