3,5c3,5
< sim_seconds 1.854310 # Number of seconds simulated
< sim_ticks 1854310111000 # Number of ticks simulated
< final_tick 1854310111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.854307 # Number of seconds simulated
> sim_ticks 1854307399500 # Number of ticks simulated
> final_tick 1854307399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,81c7,81
< host_inst_rate 145253 # Simulator instruction rate (inst/s)
< host_op_rate 145253 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5083862253 # Simulator tick rate (ticks/s)
< host_mem_usage 332668 # Number of bytes of host memory used
< host_seconds 364.74 # Real time elapsed on the host
< sim_insts 52980262 # Number of instructions simulated
< sim_ops 52980262 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu.inst 964224 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24877184 # Number of bytes read from this memory
< system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28493696 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 964224 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 964224 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7514944 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7514944 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 15066 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388706 # Number of read requests responded to by this memory
< system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 445214 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 117421 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 117421 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 519991 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13415870 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15366198 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 519991 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 519991 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4052690 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4052690 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4052690 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 519991 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13415870 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 19418888 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 445214 # Total number of read requests seen
< system.physmem.writeReqs 117421 # Total number of write requests seen
< system.physmem.cpureqs 564314 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 28493696 # Total number of bytes read from memory
< system.physmem.bytesWritten 7514944 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 28493696 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7514944 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 28116 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 27714 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 27520 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 27750 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 27793 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 27726 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 27564 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 28224 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 27918 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 27999 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 27794 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 27705 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 27923 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 27829 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 27717 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 7633 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 7399 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 7274 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 7170 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 7277 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 7235 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 7211 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 7144 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 7765 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 7469 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 7552 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 7291 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 7210 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 7264 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 7200 # Track writes on a per bank basis
---
> host_inst_rate 106006 # Simulator instruction rate (inst/s)
> host_op_rate 106006 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3711029376 # Simulator tick rate (ticks/s)
> host_mem_usage 333480 # Number of bytes of host memory used
> host_seconds 499.67 # Real time elapsed on the host
> sim_insts 52968721 # Number of instructions simulated
> sim_ops 52968721 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu.inst 963456 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24875584 # Number of bytes read from this memory
> system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28491392 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 963456 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 963456 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7501184 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7501184 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 15054 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388681 # Number of read requests responded to by this memory
> system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 445178 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 117206 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 117206 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 519577 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 13415027 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 1430373 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15364978 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 519577 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 519577 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4045275 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4045275 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4045275 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 519577 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 13415027 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1430373 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 19410253 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 445178 # Total number of read requests seen
> system.physmem.writeReqs 117206 # Total number of write requests seen
> system.physmem.cpureqs 565467 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 28491392 # Total number of bytes read from memory
> system.physmem.bytesWritten 7501184 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 28491392 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7501184 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q
> system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 27748 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 27561 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 27866 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 27961 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 27981 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 27784 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 28083 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 27812 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 27967 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 27770 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 27982 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 27794 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 7541 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 7285 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 7132 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 7366 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 7434 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 7324 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 7647 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 7361 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 7507 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 7242 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 7283 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 7386 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 7202 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis
83,84c83,84
< system.physmem.numWrRetry 946 # Number of times wr buffer was full causing retry
< system.physmem.totGap 1854304705000 # Total gap between requests
---
> system.physmem.numWrRetry 2907 # Number of times wr buffer was full causing retry
> system.physmem.totGap 1854301986000 # Total gap between requests
91,134c91,121
< system.physmem.readPktSize::6 445214 # Categorize read packet sizes
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 118367 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 174 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
< system.physmem.rdQLenPdf::0 323357 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 64296 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 7564 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2710 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2705 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 2662 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1551 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1463 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1409 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1357 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 1378 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1393 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1481 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
---
> system.physmem.readPktSize::6 445178 # Categorize read packet sizes
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 117206 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 323486 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 64269 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 19585 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 7544 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3203 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2972 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2705 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2704 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1475 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1419 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1396 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1621 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1492 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 769 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
144,169c131,155
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
< system.physmem.wrQLenPdf::0 2975 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 4221 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 4750 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5085 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5091 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5093 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 2131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1394 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 2959 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 3694 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 4215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 4727 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5063 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5074 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5079 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5080 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5095 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5095 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 2137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see
171,183c157,168
< system.physmem.wrQLenPdf::26 885 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 7913395266 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 15649662766 # Sum of mem lat for all requests
< system.physmem.totBusLat 2225790000 # Total cycles spent in databus access
< system.physmem.totBankLat 5510477500 # Total cycles spent in bank access
< system.physmem.avgQLat 17776.60 # Average queueing delay per request
< system.physmem.avgBankLat 12378.70 # Average bank access latency per request
---
> system.physmem.wrQLenPdf::26 881 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 369 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see
> system.physmem.totQLat 7499469250 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 15210035500 # Sum of mem lat for all requests
> system.physmem.totBusLat 2225595000 # Total cycles spent in databus access
> system.physmem.totBankLat 5484971250 # Total cycles spent in bank access
> system.physmem.avgQLat 16848.23 # Average queueing delay per request
> system.physmem.avgBankLat 12322.48 # Average bank access latency per request
185,186c170,171
< system.physmem.avgMemAccLat 35155.30 # Average memory access latency
< system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
---
> system.physmem.avgMemAccLat 34170.72 # Average memory access latency
> system.physmem.avgRdBW 15.36 # Average achieved read bandwidth in MB/s
188c173
< system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
---
> system.physmem.avgConsumedRdBW 15.36 # Average consumed read bandwidth in MB/s
193,198c178,183
< system.physmem.avgWrQLen 11.52 # Average write queue length over time
< system.physmem.readRowHits 417628 # Number of row buffer hits during reads
< system.physmem.writeRowHits 91533 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 93.82 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 77.95 # Row buffer hit rate for writes
< system.physmem.avgGap 3295750.72 # Average gap between requests
---
> system.physmem.avgWrQLen 14.44 # Average write queue length over time
> system.physmem.readRowHits 417746 # Number of row buffer hits during reads
> system.physmem.writeRowHits 91351 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 93.85 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes
> system.physmem.avgGap 3297216.82 # Average gap between requests
200c185
< system.iocache.tagsinuse 1.265053 # Cycle average of tags in use
---
> system.iocache.tagsinuse 1.265036 # Cycle average of tags in use
204,207c189,192
< system.iocache.warmup_cycle 1704474436000 # Cycle when the warmup percentage was hit.
< system.iocache.occ_blocks::tsunami.ide 1.265053 # Average occupied blocks per requestor
< system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy
---
> system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit.
> system.iocache.occ_blocks::tsunami.ide 1.265036 # Average occupied blocks per requestor
> system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy
218,223c203,208
< system.iocache.WriteReq_miss_latency::tsunami.ide 10610366806 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10610366806 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 10631294804 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10631294804 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 10631294804 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10631294804 # number of overall miss cycles
---
> system.iocache.WriteReq_miss_latency::tsunami.ide 10707310806 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 10707310806 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 10728238804 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 10728238804 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 10728238804 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 10728238804 # number of overall miss cycles
242,248c227,233
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 255351.530757 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 254794.363188 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 254794.363188 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 282772 # number of cycles access was blocked
---
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 257684.607384 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 257684.607384 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 257117.766423 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 257117.766423 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 287181 # number of cycles access was blocked
250c235
< system.iocache.blocked::no_mshrs 27194 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 27254 # number of cycles access was blocked
252c237
< system.iocache.avg_blocked_cycles::no_mshrs 10.398323 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.537206 # average number of cycles each access was blocked
266,273c251,258
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8448369274 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 8448369274 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 8460300524 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8460300524 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 8460300524 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8460300524 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8545305081 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 8545305081 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 8557236330 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 8557236330 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 8557236330 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 8557236330 # number of overall MSHR miss cycles
282,289c267,274
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205653.279770 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 205653.279770 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency
303,307c288,292
< system.cpu.branchPred.lookups 13838840 # Number of BP lookups
< system.cpu.branchPred.condPredicted 11607895 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 399412 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9524270 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 5814876 # Number of BTB hits
---
> system.cpu.branchPred.lookups 13852347 # Number of BP lookups
> system.cpu.branchPred.condPredicted 11625691 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 399405 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9419832 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 5813293 # Number of BTB hits
309,311c294,296
< system.cpu.branchPred.BTBHitPct 61.053246 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 905729 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 39052 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 61.713341 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 901451 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 38715 # Number of incorrect RAS predictions.
316,331c301,316
< system.cpu.dtb.read_hits 9926019 # DTB read hits
< system.cpu.dtb.read_misses 41533 # DTB read misses
< system.cpu.dtb.read_acv 530 # DTB read access violations
< system.cpu.dtb.read_accesses 942239 # DTB read accesses
< system.cpu.dtb.write_hits 6593693 # DTB write hits
< system.cpu.dtb.write_misses 10528 # DTB write misses
< system.cpu.dtb.write_acv 400 # DTB write access violations
< system.cpu.dtb.write_accesses 337995 # DTB write accesses
< system.cpu.dtb.data_hits 16519712 # DTB hits
< system.cpu.dtb.data_misses 52061 # DTB misses
< system.cpu.dtb.data_acv 930 # DTB access violations
< system.cpu.dtb.data_accesses 1280234 # DTB accesses
< system.cpu.itb.fetch_hits 1304342 # ITB hits
< system.cpu.itb.fetch_misses 39856 # ITB misses
< system.cpu.itb.fetch_acv 1022 # ITB acv
< system.cpu.itb.fetch_accesses 1344198 # ITB accesses
---
> system.cpu.dtb.read_hits 9912757 # DTB read hits
> system.cpu.dtb.read_misses 41466 # DTB read misses
> system.cpu.dtb.read_acv 543 # DTB read access violations
> system.cpu.dtb.read_accesses 941271 # DTB read accesses
> system.cpu.dtb.write_hits 6601987 # DTB write hits
> system.cpu.dtb.write_misses 10361 # DTB write misses
> system.cpu.dtb.write_acv 401 # DTB write access violations
> system.cpu.dtb.write_accesses 337783 # DTB write accesses
> system.cpu.dtb.data_hits 16514744 # DTB hits
> system.cpu.dtb.data_misses 51827 # DTB misses
> system.cpu.dtb.data_acv 944 # DTB access violations
> system.cpu.dtb.data_accesses 1279054 # DTB accesses
> system.cpu.itb.fetch_hits 1307981 # ITB hits
> system.cpu.itb.fetch_misses 36519 # ITB misses
> system.cpu.itb.fetch_acv 1105 # ITB acv
> system.cpu.itb.fetch_accesses 1344500 # ITB accesses
344c329
< system.cpu.numCycles 109629781 # number of cpu cycles simulated
---
> system.cpu.numCycles 108624305 # number of cpu cycles simulated
347,362c332,347
< system.cpu.fetch.icacheStallCycles 28054548 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 70673295 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 13838840 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 6720605 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 13244077 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1985157 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 37404215 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 32636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 256282 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 293547 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 8545648 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 265175 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 80570729 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.877158 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.220803 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 28031603 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 70677368 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 13852347 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 6714744 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 13246931 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1983028 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 37386086 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 31591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 253691 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 294769 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 735 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 8549977 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 266732 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 80529349 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.877660 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.221433 # Number of instructions fetched each cycle (Total)
364,372c349,357
< system.cpu.fetch.rateDist::0 67326652 83.56% 83.56% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 851821 1.06% 84.62% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 1698513 2.11% 86.73% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 825554 1.02% 87.75% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2751975 3.42% 91.17% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 562639 0.70% 91.87% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 645154 0.80% 92.67% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1011601 1.26% 93.92% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 4896820 6.08% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 67282418 83.55% 83.55% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 855134 1.06% 84.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 1701405 2.11% 86.72% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 823363 1.02% 87.75% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2750758 3.42% 91.16% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 561116 0.70% 91.86% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 645464 0.80% 92.66% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1009589 1.25% 93.92% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 4900102 6.08% 100.00% # Number of instructions fetched each cycle (Total)
376,420c361,405
< system.cpu.fetch.rateDist::total 80570729 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.126232 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.644654 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 29191187 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 37065229 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 12109046 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 962419 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1242847 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 584292 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 42668 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 69380603 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 129620 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 1242847 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 30314558 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 13623750 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 19784463 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 11341758 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 4263351 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 65627824 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 6945 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 510530 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 1483365 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 43820100 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 79668795 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 79189543 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 479252 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 38180356 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 5639736 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1682796 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 239926 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 12145356 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 10440685 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 6902590 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1325482 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 872752 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 58180873 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2047058 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 56813064 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 111741 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 6883646 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3532849 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1386082 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 80570729 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.705133 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.366225 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 80529349 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.127525 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.650659 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 29153342 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 37060255 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 12110722 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 963448 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1241581 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 585928 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 42780 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 69380340 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 129844 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 1241581 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 30275533 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 13620847 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 19786861 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 11346001 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 4258524 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 65625141 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 6921 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 508210 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 1478954 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 43830191 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 79653139 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 79174156 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 478983 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 38170900 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 5659283 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1683041 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 240056 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 12113189 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 10427468 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 6890622 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1312006 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 847421 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 58167835 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2052016 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 56809344 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 88346 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 6890448 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3503635 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1391090 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 80529349 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.705449 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.366907 # Number of insts issued each cycle
422,430c407,415
< system.cpu.iq.issued_per_cycle::0 55925631 69.41% 69.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 10804122 13.41% 82.82% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 5164072 6.41% 89.23% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 3379310 4.19% 93.42% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 2651147 3.29% 96.72% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 1461283 1.81% 98.53% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 759145 0.94% 99.47% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 331157 0.41% 99.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 94862 0.12% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 55889300 69.40% 69.40% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 10803861 13.42% 82.82% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 5162711 6.41% 89.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 3375118 4.19% 93.42% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 2651639 3.29% 96.71% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 1461034 1.81% 98.53% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 755339 0.94% 99.47% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 331829 0.41% 99.88% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 98518 0.12% 100.00% # Number of insts issued each cycle
434c419
< system.cpu.iq.issued_per_cycle::total 80570729 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 80529349 # Number of insts issued each cycle
436,466c421,451
< system.cpu.iq.fu_full::IntAlu 89963 11.41% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.41% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 373446 47.37% 58.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 325006 41.22% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 91375 11.51% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 373733 47.09% 58.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 328605 41.40% 100.00% # attempts to use FU when none available
470,472c455,457
< system.cpu.iq.FU_type_0::IntAlu 38735893 68.18% 68.19% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 61716 0.11% 68.30% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 38736276 68.19% 68.20% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued
477,501c462,486
< system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 10357569 18.23% 86.59% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 6672257 11.74% 98.33% # Type of FU issued
< system.cpu.iq.FU_type_0::IprAccess 949100 1.67% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 10345170 18.21% 86.57% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 6680665 11.76% 98.33% # Type of FU issued
> system.cpu.iq.FU_type_0::IprAccess 948997 1.67% 100.00% # Type of FU issued
503,515c488,500
< system.cpu.iq.FU_type_0::total 56813064 # Type of FU issued
< system.cpu.iq.rate 0.518227 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 788415 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.013877 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 194404430 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 66788743 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 55573367 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 692582 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 336629 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 57232794 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 361399 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 600057 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 56809344 # Type of FU issued
> system.cpu.iq.rate 0.522989 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 793713 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.013972 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 194336981 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 66788043 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 55575971 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 693114 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 336007 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 327916 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 57233562 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 362209 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 600992 # Number of loads that had data forwarded from stores
517,520c502,505
< system.cpu.iew.lsq.thread0.squashedLoads 1348422 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 4157 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 14125 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 524715 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1337423 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 4170 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 513944 # Number of stores squashed
523,524c508,509
< system.cpu.iew.lsq.thread0.rescheduledLoads 17951 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 174954 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 17964 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 173464 # Number of times an access to memory failed due to the cache being blocked
526,542c511,527
< system.cpu.iew.iewSquashCycles 1242847 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 9951157 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 684131 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 63754506 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 676985 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 10440685 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 6902590 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1803123 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 512112 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 18418 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 14125 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 202045 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 411832 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 613877 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 56345945 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 9995759 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 467118 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 1241581 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 9950428 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 684284 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 63748308 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 674797 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 10427468 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 6890622 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1807435 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 512768 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 18119 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 203235 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 412070 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 615305 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 56339118 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 9982368 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 470225 # Number of squashed instructions skipped in execute
544,552c529,537
< system.cpu.iew.exec_nop 3526575 # number of nop insts executed
< system.cpu.iew.exec_refs 16615200 # number of memory reference insts executed
< system.cpu.iew.exec_branches 8926807 # Number of branches executed
< system.cpu.iew.exec_stores 6619441 # Number of stores executed
< system.cpu.iew.exec_rate 0.513966 # Inst execution rate
< system.cpu.iew.wb_sent 56016691 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 55901254 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 27769565 # num instructions producing a value
< system.cpu.iew.wb_consumers 37614191 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 3528457 # number of nop insts executed
> system.cpu.iew.exec_refs 16609952 # number of memory reference insts executed
> system.cpu.iew.exec_branches 8925181 # Number of branches executed
> system.cpu.iew.exec_stores 6627584 # Number of stores executed
> system.cpu.iew.exec_rate 0.518660 # Inst execution rate
> system.cpu.iew.wb_sent 56017641 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 55903887 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 27773544 # num instructions producing a value
> system.cpu.iew.wb_consumers 37603829 # num instructions consuming a value
554,555c539,540
< system.cpu.iew.wb_rate 0.509909 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.738274 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.514654 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.738583 # average fanout of values written-back
557,562c542,547
< system.cpu.commit.commitSquashedInsts 7465102 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 568169 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 79327882 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.708087 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.637784 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 7472187 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 660926 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 568042 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 79287768 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.708292 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.638038 # Number of insts commited each cycle
564,572c549,557
< system.cpu.commit.committed_per_cycle::0 58561818 73.82% 73.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 8602415 10.84% 84.67% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 4601651 5.80% 90.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2532853 3.19% 93.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1516154 1.91% 95.57% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 607730 0.77% 96.34% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 522045 0.66% 97.00% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 534524 0.67% 97.67% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 1848692 2.33% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 58526272 73.82% 73.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 8600403 10.85% 84.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 4599837 5.80% 90.46% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2533746 3.20% 93.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1516837 1.91% 95.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 606860 0.77% 96.34% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 524643 0.66% 97.00% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 525259 0.66% 97.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 1853911 2.34% 100.00% # Number of insts commited each cycle
576,578c561,563
< system.cpu.commit.committed_per_cycle::total 79327882 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 56171016 # Number of instructions committed
< system.cpu.commit.committedOps 56171016 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 79287768 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 56158922 # Number of instructions committed
> system.cpu.commit.committedOps 56158922 # Number of ops (including micro ops) committed
580,583c565,568
< system.cpu.commit.refs 15470138 # Number of memory references committed
< system.cpu.commit.loads 9092263 # Number of loads committed
< system.cpu.commit.membars 226349 # Number of memory barriers committed
< system.cpu.commit.branches 8440338 # Number of branches committed
---
> system.cpu.commit.refs 15466723 # Number of memory references committed
> system.cpu.commit.loads 9090045 # Number of loads committed
> system.cpu.commit.membars 226335 # Number of memory barriers committed
> system.cpu.commit.branches 8439344 # Number of branches committed
585,587c570,572
< system.cpu.commit.int_insts 52020652 # Number of committed integer instructions.
< system.cpu.commit.function_calls 740552 # Number of function calls committed.
< system.cpu.commit.bw_lim_events 1848692 # number cycles where commit BW limit reached
---
> system.cpu.commit.int_insts 52009184 # Number of committed integer instructions.
> system.cpu.commit.function_calls 740395 # Number of function calls committed.
> system.cpu.commit.bw_lim_events 1853911 # number cycles where commit BW limit reached
589,606c574,591
< system.cpu.rob.rob_reads 140865752 # The number of ROB reads
< system.cpu.rob.rob_writes 128516921 # The number of ROB writes
< system.cpu.timesIdled 1179002 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 29059052 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 3598984001 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 52980262 # Number of Instructions Simulated
< system.cpu.committedOps 52980262 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 52980262 # Number of Instructions Simulated
< system.cpu.cpi 2.069257 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.069257 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.483265 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.483265 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 73880365 # number of integer regfile reads
< system.cpu.int_regfile_writes 40316413 # number of integer regfile writes
< system.cpu.fp_regfile_reads 166011 # number of floating regfile reads
< system.cpu.fp_regfile_writes 167446 # number of floating regfile writes
< system.cpu.misc_regfile_reads 1987331 # number of misc regfile reads
< system.cpu.misc_regfile_writes 938994 # number of misc regfile writes
---
> system.cpu.rob.rob_reads 140815408 # The number of ROB reads
> system.cpu.rob.rob_writes 128505533 # The number of ROB writes
> system.cpu.timesIdled 1178112 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 28094956 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 3599984053 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 52968721 # Number of Instructions Simulated
> system.cpu.committedOps 52968721 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 52968721 # Number of Instructions Simulated
> system.cpu.cpi 2.050725 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.050725 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.487632 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.487632 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 73881531 # number of integer regfile reads
> system.cpu.int_regfile_writes 40312822 # number of integer regfile writes
> system.cpu.fp_regfile_reads 166061 # number of floating regfile reads
> system.cpu.fp_regfile_writes 167429 # number of floating regfile writes
> system.cpu.misc_regfile_reads 1987886 # number of misc regfile reads
> system.cpu.misc_regfile_writes 938918 # number of misc regfile writes
638,688c623,673
< system.cpu.icache.replacements 1008798 # number of replacements
< system.cpu.icache.tagsinuse 510.238342 # Cycle average of tags in use
< system.cpu.icache.total_refs 7480626 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 1009306 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 7.411653 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 510.238342 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.996559 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 7480627 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 7480627 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 7480627 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 7480627 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 7480627 # number of overall hits
< system.cpu.icache.overall_hits::total 7480627 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1065018 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1065018 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1065018 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1065018 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1065018 # number of overall misses
< system.cpu.icache.overall_misses::total 1065018 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14700112992 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14700112992 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14700112992 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14700112992 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14700112992 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14700112992 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 8545645 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 8545645 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 8545645 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 8545645 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 8545645 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 8545645 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124627 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.124627 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.124627 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.124627 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.124627 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13802.689712 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13802.689712 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13802.689712 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13802.689712 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 5838 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 237 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 28.758621 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 237 # average number of cycles each access was blocked
---
> system.cpu.icache.replacements 1008795 # number of replacements
> system.cpu.icache.tagsinuse 510.288576 # Cycle average of tags in use
> system.cpu.icache.total_refs 7484836 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 1009303 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 7.415846 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 510.288576 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 7484837 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 7484837 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 7484837 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 7484837 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 7484837 # number of overall hits
> system.cpu.icache.overall_hits::total 7484837 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1065140 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1065140 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1065140 # number of overall misses
> system.cpu.icache.overall_misses::total 1065140 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14678664495 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14678664495 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14678664495 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14678664495 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14678664495 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14678664495 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 8549977 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 8549977 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 8549977 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 8549977 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 8549977 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 8549977 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124578 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13780.971980 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13780.971980 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13780.971980 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13780.971980 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 7122 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 1606 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 164 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 43.426829 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 803 # average number of cycles each access was blocked
691,720c676,705
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55491 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 55491 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 55491 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 55491 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 55491 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 55491 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009527 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1009527 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1009527 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1009527 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1009527 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1009527 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12048771993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12048771993 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12048771993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12048771993 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12048771993 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12048771993 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118134 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.118134 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.118134 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11935.066613 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11935.066613 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55619 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 55619 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 55619 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 55619 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 55619 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 55619 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009521 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1009521 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1009521 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1009521 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1009521 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1009521 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12035617996 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12035617996 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12035617996 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12035617996 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12035617996 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12035617996 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118073 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.118073 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.118073 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.107609 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.107609 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency
722,820c707,813
< system.cpu.l2cache.replacements 338275 # number of replacements
< system.cpu.l2cache.tagsinuse 65364.674694 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 2545615 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 403441 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 6.309758 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 4180772752 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 54011.059986 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 5325.208257 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 6028.406451 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.824143 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.inst 0.081256 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.091986 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.997386 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 994342 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 827132 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1821474 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 840875 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 840875 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 185593 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 185593 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 994342 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1012725 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2007067 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 994342 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1012725 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2007067 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 15068 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 273766 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 288834 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 115432 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 115432 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 15068 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 389198 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 404266 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 15068 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 389198 # number of overall misses
< system.cpu.l2cache.overall_misses::total 404266 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1052241000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12408474500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 13460715500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 274500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 274500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7669350500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7669350500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1052241000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 20077825000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 21130066000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1052241000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 20077825000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 21130066000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009410 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1100898 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2110308 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 840875 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 840875 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 61 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 61 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 301025 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 301025 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1009410 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1401923 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2411333 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1009410 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1401923 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2411333 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014928 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248675 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.136868 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.573770 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.573770 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014928 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.277617 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014928 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.277617 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69832.824529 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45325.111592 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 46603.639115 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7842.857143 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7842.857143 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66440.419468 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66440.419468 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52267.729663 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52267.729663 # average overall miss latency
---
> system.cpu.l2cache.replacements 338260 # number of replacements
> system.cpu.l2cache.tagsinuse 65365.866515 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 2544525 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 403426 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 6.307291 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 4078120751 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 53972.516540 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 5322.981591 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 6070.368385 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.823555 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.081222 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.092626 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.997404 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 994349 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 826677 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1821026 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 840320 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 840320 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 185342 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 185342 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 994349 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1012019 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2006368 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 994349 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1012019 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2006368 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 15056 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 273775 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 288831 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 115395 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 115395 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 15056 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 389170 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 404226 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 15056 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 389170 # number of overall misses
> system.cpu.l2cache.overall_misses::total 404226 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1039366500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11945940500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 12985307000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 290000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 290000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 23000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 23000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7619154000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7619154000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1039366500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 19565094500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 20604461000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1039366500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 19565094500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 20604461000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009405 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1100452 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2109857 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 840320 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 840320 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 300737 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 300737 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1009405 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1401189 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2410594 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1009405 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1401189 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2410594 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014916 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248784 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.136896 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.619048 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.619048 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383707 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383707 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014916 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.277743 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.167687 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014916 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.277743 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.167687 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69033.375399 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43634.153959 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 44958.148537 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7435.897436 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7435.897436 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 11500 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 11500 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66026.725595 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66026.725595 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69033.375399 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50273.902151 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 50972.626699 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69033.375399 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50273.902151 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 50972.626699 # average overall miss latency
829,830c822,823
< system.cpu.l2cache.writebacks::writebacks 75909 # number of writebacks
< system.cpu.l2cache.writebacks::total 75909 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 75694 # number of writebacks
> system.cpu.l2cache.writebacks::total 75694 # number of writebacks
837,894c830,895
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15067 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273766 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 288833 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115432 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 115432 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 15067 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 389198 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 404265 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 15067 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 389198 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 404265 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 864374583 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9058859411 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9923233994 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 514531 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 514531 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6259293268 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6259293268 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 864374583 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15318152679 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 16182527262 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 864374583 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15318152679 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 16182527262 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333805500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333805500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882511000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882511000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216316500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216316500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248675 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136868 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.573770 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.573770 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.167652 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.167652 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57368.725227 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.789861 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34356.302756 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700.885714 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700.885714 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54224.939947 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54224.939947 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15055 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273775 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 288830 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115395 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 115395 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 15055 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 389170 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 404225 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 15055 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 389170 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 404225 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 851622750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8594985001 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9446607751 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 547534 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 547534 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6209572959 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6209572959 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851622750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14804557960 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 15656180710 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851622750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14804557960 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 15656180710 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333813500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333813500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882743500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882743500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216557000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216557000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248784 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136896 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383707 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383707 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.167687 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.167687 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56567.436068 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31394.338420 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32706.463148 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14039.333333 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14039.333333 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53811.455947 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53811.455947 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency
902,906c903,907
< system.cpu.dcache.replacements 1401332 # number of replacements
< system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use
< system.cpu.dcache.total_refs 11818848 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1401844 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 8.430930 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 1400597 # number of replacements
> system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use
> system.cpu.dcache.total_refs 11804639 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1401109 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 8.425211 # Average number of references to valid blocks.
908c909
< system.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor
---
> system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor
911,988c912,989
< system.cpu.dcache.ReadReq_hits::cpu.data 7212145 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7212145 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4204906 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4204906 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 186063 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 186063 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 11417051 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 11417051 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 11417051 # number of overall hits
< system.cpu.dcache.overall_hits::total 11417051 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1802577 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1802577 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1942748 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1942748 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22749 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22749 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 3745325 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3745325 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3745325 # number of overall misses
< system.cpu.dcache.overall_misses::total 3745325 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 34332308500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 34332308500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 65131487898 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 65131487898 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306015000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 306015000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 99463796398 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 99463796398 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 99463796398 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 99463796398 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9014722 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9014722 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6147654 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6147654 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208812 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 208812 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15162376 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15162376 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15162376 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15162376 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199959 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.199959 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316015 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.316015 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108945 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108945 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.247014 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.247014 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.247014 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.247014 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19046.236860 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 19046.236860 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33525.443289 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 33525.443289 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13451.800079 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13451.800079 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26556.786500 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 26556.786500 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 2193487 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 506 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 95928 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.865972 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 72.285714 # average number of cycles each access was blocked
---
> system.cpu.dcache.ReadReq_hits::cpu.data 7199170 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7199170 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4203355 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4203355 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 186385 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 186385 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 215505 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 11402525 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 11402525 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 11402525 # number of overall hits
> system.cpu.dcache.overall_hits::total 11402525 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1802469 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1802469 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1943114 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1943114 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22653 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22653 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 3745583 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3745583 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3745583 # number of overall misses
> system.cpu.dcache.overall_misses::total 3745583 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 33840497500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 33840497500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 64776324525 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 64776324525 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306197000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 306197000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 76500 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 76500 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 98616822025 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 98616822025 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 98616822025 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 98616822025 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9001639 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9001639 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6146469 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6146469 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209038 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 209038 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15148108 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15148108 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15148108 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15148108 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200238 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.200238 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316135 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.316135 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108368 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108368 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.247264 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.247264 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.247264 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.247264 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18774.524000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 18774.524000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33336.348009 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33336.348009 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13516.841037 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13516.841037 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19125 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19125 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26328.831059 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 26328.831059 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 2181836 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 95774 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.781089 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked
991,1056c992,1057
< system.cpu.dcache.writebacks::writebacks 840875 # number of writebacks
< system.cpu.dcache.writebacks::total 840875 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718560 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 718560 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642321 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1642321 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5210 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 5210 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2360881 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2360881 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2360881 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2360881 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084017 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1084017 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300427 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 300427 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17539 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17539 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1384444 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1384444 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1384444 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1384444 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21793042000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 21793042000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9888893772 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 9888893772 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199306000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199306000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31681935772 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 31681935772 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31681935772 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 31681935772 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423882500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423882500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997678998 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997678998 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421561498 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421561498 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120250 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120250 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048869 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048869 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083994 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083994 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091308 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091308 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 840320 # number of writebacks
> system.cpu.dcache.writebacks::total 840320 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718906 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 718906 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642971 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1642971 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5109 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 5109 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2361877 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2361877 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2361877 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2361877 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083563 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1083563 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300143 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 300143 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17544 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17544 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1383706 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1383706 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1383706 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1383706 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21325000500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 21325000500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9835893766 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 9835893766 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200292500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200292500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 68500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 68500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31160894266 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 31160894266 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31160894266 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 31160894266 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423890500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423890500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997911498 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997911498 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421801998 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421801998 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120374 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120374 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048832 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048832 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083927 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083927 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091345 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091345 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19680.443592 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19680.443592 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32770.691857 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32770.691857 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11416.581167 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11416.581167 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17125 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17125 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency
1065,1067c1066,1068
< system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211025 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl
1070,1072c1071,1073
< system.cpu.kern.ipl_count::31 105575 57.93% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182256 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl
1075,1082c1076,1083
< system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1817868211500 98.03% 98.03% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 63824000 0.00% 98.04% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 559692500 0.03% 98.07% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 35817544000 1.93% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1854309272000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1818335798500 98.06% 98.06% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 63864000 0.00% 98.06% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 549180000 0.03% 98.09% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 35357724000 1.91% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1854306566500 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
1085,1086c1086,1087
< system.cpu.kern.ipl_used::31 0.694331 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl
1125c1126
< system.cpu.kern.callpal::swpipl 175141 91.23% 93.44% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed
1134c1135
< system.cpu.kern.callpal::total 191985 # number of callpals executed
---
> system.cpu.kern.callpal::total 191959 # number of callpals executed
1145,1147c1146,1148
< system.cpu.kern.mode_ticks::kernel 29467227000 1.59% 1.59% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 2708568500 0.15% 1.74% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1822133468500 98.26% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_ticks::kernel 29457551500 1.59% 1.59% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 2704315000 0.15% 1.73% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1822144692000 98.27% 100.00% # number of ticks spent at the given mode