4,5c4,5
< sim_ticks 1854309852000 # Number of ticks simulated
< final_tick 1854309852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 1854310111000 # Number of ticks simulated
> final_tick 1854310111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,15c7,15
< host_inst_rate 117975 # Simulator instruction rate (inst/s)
< host_op_rate 117975 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4129044881 # Simulator tick rate (ticks/s)
< host_mem_usage 335500 # Number of bytes of host memory used
< host_seconds 449.09 # Real time elapsed on the host
< sim_insts 52981417 # Number of instructions simulated
< sim_ops 52981417 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu.inst 964672 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24877888 # Number of bytes read from this memory
---
> host_inst_rate 145253 # Simulator instruction rate (inst/s)
> host_op_rate 145253 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5083862253 # Simulator tick rate (ticks/s)
> host_mem_usage 332668 # Number of bytes of host memory used
> host_seconds 364.74 # Real time elapsed on the host
> sim_insts 52980262 # Number of instructions simulated
> sim_ops 52980262 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu.inst 964224 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24877184 # Number of bytes read from this memory
17,23c17,23
< system.physmem.bytes_read::total 28494848 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 964672 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 964672 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7516416 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7516416 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 15073 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388717 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 28493696 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 964224 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 964224 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7514944 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7514944 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 15066 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388706 # Number of read requests responded to by this memory
25,29c25,29
< system.physmem.num_reads::total 445232 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 117444 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 117444 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 520232 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13416252 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::total 445214 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 117421 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 117421 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 519991 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 13415870 # Total read bandwidth from this memory (bytes/s)
31,38c31,38
< system.physmem.bw_read::total 15366821 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 520232 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 520232 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4053484 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4053484 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4053484 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 520232 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13416252 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 15366198 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 519991 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 519991 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4052690 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4052690 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4052690 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 519991 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 13415870 # Total bandwidth to/from this memory (bytes/s)
40,50c40,50
< system.physmem.bw_total::total 19420306 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 445232 # Total number of read requests seen
< system.physmem.writeReqs 117444 # Total number of write requests seen
< system.physmem.cpureqs 565193 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 28494848 # Total number of bytes read from memory
< system.physmem.bytesWritten 7516416 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 28494848 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7516416 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 28112 # Track reads on a per bank basis
---
> system.physmem.bw_total::total 19418888 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 445214 # Total number of read requests seen
> system.physmem.writeReqs 117421 # Total number of write requests seen
> system.physmem.cpureqs 564314 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 28493696 # Total number of bytes read from memory
> system.physmem.bytesWritten 7514944 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 28493696 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7514944 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q
> system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 28116 # Track reads on a per bank basis
52,78c52,78
< system.physmem.perBankRdReqs::2 27716 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 27523 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 27754 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 27723 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 27566 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 28230 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 27914 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 28000 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 27799 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 27706 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 27921 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 27830 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 27718 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 7398 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 7277 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 7173 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 7281 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 7238 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 7147 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 7771 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 7465 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 7554 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 7296 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 7212 # Track writes on a per bank basis
---
> system.physmem.perBankRdReqs::2 27714 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 27520 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 27750 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 27793 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 27726 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 27564 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 28224 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 27918 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 27999 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 27794 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 27705 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 27923 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 27829 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 27717 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 7633 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 7399 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 7274 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 7170 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 7277 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 7235 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 7211 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 7144 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 7765 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 7469 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 7552 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 7291 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 7210 # Track writes on a per bank basis
80,81c80,81
< system.physmem.perBankWrReqs::14 7265 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 7201 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::14 7264 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 7200 # Track writes on a per bank basis
83,84c83,84
< system.physmem.numWrRetry 1787 # Number of times wr buffer was full causing retry
< system.physmem.totGap 1854304427000 # Total gap between requests
---
> system.physmem.numWrRetry 946 # Number of times wr buffer was full causing retry
> system.physmem.totGap 1854304705000 # Total gap between requests
91c91
< system.physmem.readPktSize::6 445232 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 445214 # Categorize read packet sizes
100c100
< system.physmem.writePktSize::6 119231 # categorize write packet sizes
---
> system.physmem.writePktSize::6 118367 # categorize write packet sizes
109c109
< system.physmem.neitherpktsize::6 171 # categorize neither packet sizes
---
> system.physmem.neitherpktsize::6 174 # categorize neither packet sizes
112,133c112,133
< system.physmem.rdQLenPdf::0 323360 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 64418 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 19847 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 7546 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3166 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2952 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2668 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 2640 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2594 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1545 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1469 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1418 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1345 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1374 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1596 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1493 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 910 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 761 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 323357 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 64296 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 7564 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2710 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2705 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 2662 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1551 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1463 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1409 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1357 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 1378 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1393 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1481 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see
145,152c145,152
< system.physmem.wrQLenPdf::0 2999 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3738 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 4232 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 4753 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5084 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5089 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5092 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 2975 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 4221 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 4750 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5085 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5091 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5093 # What write queue length does an incoming req see
154,176c154,176
< system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 2108 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1369 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 935 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 875 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 354 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::9 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 2131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 1394 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 885 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
178,183c178,183
< system.physmem.totQLat 7898633503 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 15636428503 # Sum of mem lat for all requests
< system.physmem.totBusLat 2225860000 # Total cycles spent in databus access
< system.physmem.totBankLat 5511935000 # Total cycles spent in bank access
< system.physmem.avgQLat 17742.88 # Average queueing delay per request
< system.physmem.avgBankLat 12381.59 # Average bank access latency per request
---
> system.physmem.totQLat 7913395266 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 15649662766 # Sum of mem lat for all requests
> system.physmem.totBusLat 2225790000 # Total cycles spent in databus access
> system.physmem.totBankLat 5510477500 # Total cycles spent in bank access
> system.physmem.avgQLat 17776.60 # Average queueing delay per request
> system.physmem.avgBankLat 12378.70 # Average bank access latency per request
185c185
< system.physmem.avgMemAccLat 35124.47 # Average memory access latency
---
> system.physmem.avgMemAccLat 35155.30 # Average memory access latency
193,198c193,198
< system.physmem.avgWrQLen 10.74 # Average write queue length over time
< system.physmem.readRowHits 417598 # Number of row buffer hits during reads
< system.physmem.writeRowHits 91555 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes
< system.physmem.avgGap 3295510.08 # Average gap between requests
---
> system.physmem.avgWrQLen 11.52 # Average write queue length over time
> system.physmem.readRowHits 417628 # Number of row buffer hits during reads
> system.physmem.writeRowHits 91533 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 93.82 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 77.95 # Row buffer hit rate for writes
> system.physmem.avgGap 3295750.72 # Average gap between requests
200c200
< system.iocache.tagsinuse 1.265033 # Cycle average of tags in use
---
> system.iocache.tagsinuse 1.265053 # Cycle average of tags in use
204,207c204,207
< system.iocache.warmup_cycle 1704476002000 # Cycle when the warmup percentage was hit.
< system.iocache.occ_blocks::tsunami.ide 1.265033 # Average occupied blocks per requestor
< system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy
---
> system.iocache.warmup_cycle 1704474436000 # Cycle when the warmup percentage was hit.
> system.iocache.occ_blocks::tsunami.ide 1.265053 # Average occupied blocks per requestor
> system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy
218,223c218,223
< system.iocache.WriteReq_miss_latency::tsunami.ide 10574791806 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10574791806 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 10595719804 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10595719804 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 10595719804 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10595719804 # number of overall miss cycles
---
> system.iocache.WriteReq_miss_latency::tsunami.ide 10610366806 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 10610366806 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 10631294804 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 10631294804 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 10631294804 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 10631294804 # number of overall miss cycles
242,248c242,248
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254495.374615 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 254495.374615 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 253941.756836 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 253941.756836 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 280489 # number of cycles access was blocked
---
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 255351.530757 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 254794.363188 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 254794.363188 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 282772 # number of cycles access was blocked
250c250
< system.iocache.blocked::no_mshrs 27002 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 27194 # number of cycles access was blocked
252c252
< system.iocache.avg_blocked_cycles::no_mshrs 10.387712 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.398323 # average number of cycles each access was blocked
268,273c268,273
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8412803020 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 8412803020 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 8424734270 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8424734270 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 8424734270 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8424734270 # number of overall MSHR miss cycles
---
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8448369274 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 8448369274 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 8460300524 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 8460300524 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 8460300524 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 8460300524 # number of overall MSHR miss cycles
284,289c284,289
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202464.454659 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 202464.454659 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency
---
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency
303,307c303,307
< system.cpu.branchPred.lookups 13854519 # Number of BP lookups
< system.cpu.branchPred.condPredicted 11622006 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 399782 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9584331 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 5815567 # Number of BTB hits
---
> system.cpu.branchPred.lookups 13838840 # Number of BP lookups
> system.cpu.branchPred.condPredicted 11607895 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 399412 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9524270 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 5814876 # Number of BTB hits
309,311c309,311
< system.cpu.branchPred.BTBHitPct 60.677861 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 905443 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 39042 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 61.053246 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 905729 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 39052 # Number of incorrect RAS predictions.
316,331c316,331
< system.cpu.dtb.read_hits 9921013 # DTB read hits
< system.cpu.dtb.read_misses 41705 # DTB read misses
< system.cpu.dtb.read_acv 547 # DTB read access violations
< system.cpu.dtb.read_accesses 941529 # DTB read accesses
< system.cpu.dtb.write_hits 6598119 # DTB write hits
< system.cpu.dtb.write_misses 10489 # DTB write misses
< system.cpu.dtb.write_acv 411 # DTB write access violations
< system.cpu.dtb.write_accesses 338424 # DTB write accesses
< system.cpu.dtb.data_hits 16519132 # DTB hits
< system.cpu.dtb.data_misses 52194 # DTB misses
< system.cpu.dtb.data_acv 958 # DTB access violations
< system.cpu.dtb.data_accesses 1279953 # DTB accesses
< system.cpu.itb.fetch_hits 1307587 # ITB hits
< system.cpu.itb.fetch_misses 36909 # ITB misses
< system.cpu.itb.fetch_acv 1032 # ITB acv
< system.cpu.itb.fetch_accesses 1344496 # ITB accesses
---
> system.cpu.dtb.read_hits 9926019 # DTB read hits
> system.cpu.dtb.read_misses 41533 # DTB read misses
> system.cpu.dtb.read_acv 530 # DTB read access violations
> system.cpu.dtb.read_accesses 942239 # DTB read accesses
> system.cpu.dtb.write_hits 6593693 # DTB write hits
> system.cpu.dtb.write_misses 10528 # DTB write misses
> system.cpu.dtb.write_acv 400 # DTB write access violations
> system.cpu.dtb.write_accesses 337995 # DTB write accesses
> system.cpu.dtb.data_hits 16519712 # DTB hits
> system.cpu.dtb.data_misses 52061 # DTB misses
> system.cpu.dtb.data_acv 930 # DTB access violations
> system.cpu.dtb.data_accesses 1280234 # DTB accesses
> system.cpu.itb.fetch_hits 1304342 # ITB hits
> system.cpu.itb.fetch_misses 39856 # ITB misses
> system.cpu.itb.fetch_acv 1022 # ITB acv
> system.cpu.itb.fetch_accesses 1344198 # ITB accesses
344c344
< system.cpu.numCycles 109625107 # number of cpu cycles simulated
---
> system.cpu.numCycles 109629781 # number of cpu cycles simulated
347,362c347,362
< system.cpu.fetch.icacheStallCycles 28053642 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 70690468 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 13854519 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 6721010 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 13247907 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1985368 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 37409434 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 32200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 254032 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 293409 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 622 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 8552479 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 266219 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 80576938 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.877304 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.221000 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 28054548 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 70673295 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 13838840 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 6720605 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 13244077 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1985157 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 37404215 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 32636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 256282 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 293547 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 8545648 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 265175 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 80570729 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.877158 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.220803 # Number of instructions fetched each cycle (Total)
364,372c364,372
< system.cpu.fetch.rateDist::0 67329031 83.56% 83.56% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 853166 1.06% 84.62% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 1699610 2.11% 86.73% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 825917 1.03% 87.75% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2751267 3.41% 91.17% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 561372 0.70% 91.86% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 646563 0.80% 92.67% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1011071 1.25% 93.92% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 4898941 6.08% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 67326652 83.56% 83.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 851821 1.06% 84.62% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 1698513 2.11% 86.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 825554 1.02% 87.75% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2751975 3.42% 91.17% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 562639 0.70% 91.87% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 645154 0.80% 92.67% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1011601 1.26% 93.92% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 4896820 6.08% 100.00% # Number of instructions fetched each cycle (Total)
376,420c376,420
< system.cpu.fetch.rateDist::total 80576938 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.126381 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.644838 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 29188607 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 37070199 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 12111886 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 962831 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1243414 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 585279 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 42689 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 69390201 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 129780 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 1243414 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 30310150 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 13624817 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 19789639 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 11346848 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 4262068 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 65638780 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 6929 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 510249 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 1482252 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 43832025 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 79671797 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 79192798 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 478999 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 38181176 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 5650841 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1682596 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 239958 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 12134086 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 10437264 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 6898844 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1303944 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 867300 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 58187512 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2050080 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 56823763 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 104138 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 6892850 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3517048 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1389102 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 80576938 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.705211 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.366405 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 80570729 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.126232 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.644654 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 29191187 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 37065229 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 12109046 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 962419 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1242847 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 584292 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 42668 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 69380603 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 129620 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 1242847 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 30314558 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 13623750 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 19784463 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 11341758 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 4263351 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 65627824 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 6945 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 510530 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 1483365 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 43820100 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 79668795 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 79189543 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 479252 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 38180356 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 5639736 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1682796 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 239926 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 12145356 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 10440685 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 6902590 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1325482 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 872752 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 58180873 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2047058 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 56813064 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 111741 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 6883646 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3532849 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1386082 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 80570729 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.705133 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.366225 # Number of insts issued each cycle
422,430c422,430
< system.cpu.iq.issued_per_cycle::0 55928630 69.41% 69.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 10806018 13.41% 82.82% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 5163609 6.41% 89.23% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 3379495 4.19% 93.42% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 2652407 3.29% 96.72% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 1461056 1.81% 98.53% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 758797 0.94% 99.47% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 331056 0.41% 99.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 95870 0.12% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 55925631 69.41% 69.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 10804122 13.41% 82.82% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 5164072 6.41% 89.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 3379310 4.19% 93.42% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 2651147 3.29% 96.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 1461283 1.81% 98.53% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 759145 0.94% 99.47% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 331157 0.41% 99.88% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 94862 0.12% 100.00% # Number of insts issued each cycle
434c434
< system.cpu.iq.issued_per_cycle::total 80576938 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 80570729 # Number of insts issued each cycle
436,466c436,466
< system.cpu.iq.fu_full::IntAlu 90990 11.53% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 373752 47.37% 58.90% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 324325 41.10% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 89963 11.41% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.41% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 373446 47.37% 58.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 325006 41.22% 100.00% # attempts to use FU when none available
470,472c470,472
< system.cpu.iq.FU_type_0::IntAlu 38746520 68.19% 68.20% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 61714 0.11% 68.31% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 38735893 68.18% 68.19% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 61716 0.11% 68.30% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued
477,501c477,501
< system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 10353275 18.22% 86.58% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 6676641 11.75% 98.33% # Type of FU issued
< system.cpu.iq.FU_type_0::IprAccess 949084 1.67% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 10357569 18.23% 86.59% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 6672257 11.74% 98.33% # Type of FU issued
> system.cpu.iq.FU_type_0::IprAccess 949100 1.67% 100.00% # Type of FU issued
503,511c503,511
< system.cpu.iq.FU_type_0::total 56823763 # Type of FU issued
< system.cpu.iq.rate 0.518346 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 789067 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.013886 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 194424766 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 66808135 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 55585961 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 692902 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 336093 # Number of floating instruction queue writes
---
> system.cpu.iq.FU_type_0::total 56813064 # Type of FU issued
> system.cpu.iq.rate 0.518227 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 788415 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.013877 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 194404430 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 66788743 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 55573367 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 692582 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 336629 # Number of floating instruction queue writes
513,515c513,515
< system.cpu.iq.int_alu_accesses 57243591 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 361953 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 600271 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.int_alu_accesses 57232794 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 361399 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 600057 # Number of loads that had data forwarded from stores
517,520c517,520
< system.cpu.iew.lsq.thread0.squashedLoads 1344993 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 3536 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 14132 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 520971 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1348422 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 4157 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 14125 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 524715 # Number of stores squashed
523,524c523,524
< system.cpu.iew.lsq.thread0.rescheduledLoads 17952 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 173575 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 17951 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 174954 # Number of times an access to memory failed due to the cache being blocked
526,542c526,542
< system.cpu.iew.iewSquashCycles 1243414 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 9953615 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 683685 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 63765437 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 675848 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 10437264 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 6898844 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1805870 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 511832 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 18204 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 14132 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 202521 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 411600 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 614121 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 56355375 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 9990908 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 468387 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 1242847 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 9951157 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 684131 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 63754506 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 676985 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 10440685 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 6902590 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1803123 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 512112 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 18418 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 14125 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 202045 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 411832 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 613877 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 56345945 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 9995759 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 467118 # Number of squashed instructions skipped in execute
544,552c544,552
< system.cpu.iew.exec_nop 3527845 # number of nop insts executed
< system.cpu.iew.exec_refs 16614745 # number of memory reference insts executed
< system.cpu.iew.exec_branches 8928138 # Number of branches executed
< system.cpu.iew.exec_stores 6623837 # Number of stores executed
< system.cpu.iew.exec_rate 0.514074 # Inst execution rate
< system.cpu.iew.wb_sent 56029038 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 55913848 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 27775021 # num instructions producing a value
< system.cpu.iew.wb_consumers 37616621 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 3526575 # number of nop insts executed
> system.cpu.iew.exec_refs 16615200 # number of memory reference insts executed
> system.cpu.iew.exec_branches 8926807 # Number of branches executed
> system.cpu.iew.exec_stores 6619441 # Number of stores executed
> system.cpu.iew.exec_rate 0.513966 # Inst execution rate
> system.cpu.iew.wb_sent 56016691 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 55901254 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 27769565 # num instructions producing a value
> system.cpu.iew.wb_consumers 37614191 # num instructions consuming a value
554,555c554,555
< system.cpu.iew.wb_rate 0.510046 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.738371 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.509909 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.738274 # average fanout of values written-back
557,562c557,562
< system.cpu.commit.commitSquashedInsts 7476360 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 660978 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 568527 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 79333524 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.708051 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.637595 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 7465102 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 568169 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 79327882 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.708087 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.637784 # Number of insts commited each cycle
564,572c564,572
< system.cpu.commit.committed_per_cycle::0 58563645 73.82% 73.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 8604221 10.85% 84.67% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 4603933 5.80% 90.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2533514 3.19% 93.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1516762 1.91% 95.57% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 607132 0.77% 96.34% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 522001 0.66% 97.00% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 533698 0.67% 97.67% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 1848618 2.33% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 58561818 73.82% 73.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 8602415 10.84% 84.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 4601651 5.80% 90.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2532853 3.19% 93.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1516154 1.91% 95.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 607730 0.77% 96.34% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 522045 0.66% 97.00% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 534524 0.67% 97.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 1848692 2.33% 100.00% # Number of insts commited each cycle
576,578c576,578
< system.cpu.commit.committed_per_cycle::total 79333524 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 56172173 # Number of instructions committed
< system.cpu.commit.committedOps 56172173 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 79327882 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 56171016 # Number of instructions committed
> system.cpu.commit.committedOps 56171016 # Number of ops (including micro ops) committed
580,581c580,581
< system.cpu.commit.refs 15470144 # Number of memory references committed
< system.cpu.commit.loads 9092271 # Number of loads committed
---
> system.cpu.commit.refs 15470138 # Number of memory references committed
> system.cpu.commit.loads 9092263 # Number of loads committed
583c583
< system.cpu.commit.branches 8440686 # Number of branches committed
---
> system.cpu.commit.branches 8440338 # Number of branches committed
585,587c585,587
< system.cpu.commit.int_insts 52021801 # Number of committed integer instructions.
< system.cpu.commit.function_calls 740555 # Number of function calls committed.
< system.cpu.commit.bw_lim_events 1848618 # number cycles where commit BW limit reached
---
> system.cpu.commit.int_insts 52020652 # Number of committed integer instructions.
> system.cpu.commit.function_calls 740552 # Number of function calls committed.
> system.cpu.commit.bw_lim_events 1848692 # number cycles where commit BW limit reached
589,606c589,606
< system.cpu.rob.rob_reads 140883934 # The number of ROB reads
< system.cpu.rob.rob_writes 128542305 # The number of ROB writes
< system.cpu.timesIdled 1179238 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 29048169 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 3598988155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 52981417 # Number of Instructions Simulated
< system.cpu.committedOps 52981417 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 52981417 # Number of Instructions Simulated
< system.cpu.cpi 2.069124 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.069124 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.483296 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.483296 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 73895852 # number of integer regfile reads
< system.cpu.int_regfile_writes 40324169 # number of integer regfile writes
< system.cpu.fp_regfile_reads 166027 # number of floating regfile reads
< system.cpu.fp_regfile_writes 167433 # number of floating regfile writes
< system.cpu.misc_regfile_reads 1987804 # number of misc regfile reads
< system.cpu.misc_regfile_writes 938984 # number of misc regfile writes
---
> system.cpu.rob.rob_reads 140865752 # The number of ROB reads
> system.cpu.rob.rob_writes 128516921 # The number of ROB writes
> system.cpu.timesIdled 1179002 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 29059052 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 3598984001 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 52980262 # Number of Instructions Simulated
> system.cpu.committedOps 52980262 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 52980262 # Number of Instructions Simulated
> system.cpu.cpi 2.069257 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.069257 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.483265 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.483265 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 73880365 # number of integer regfile reads
> system.cpu.int_regfile_writes 40316413 # number of integer regfile writes
> system.cpu.fp_regfile_reads 166011 # number of floating regfile reads
> system.cpu.fp_regfile_writes 167446 # number of floating regfile writes
> system.cpu.misc_regfile_reads 1987331 # number of misc regfile reads
> system.cpu.misc_regfile_writes 938994 # number of misc regfile writes
638,642c638,642
< system.cpu.icache.replacements 1009308 # number of replacements
< system.cpu.icache.tagsinuse 510.238404 # Cycle average of tags in use
< system.cpu.icache.total_refs 7486940 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 1009816 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 7.414163 # Average number of references to valid blocks.
---
> system.cpu.icache.replacements 1008798 # number of replacements
> system.cpu.icache.tagsinuse 510.238342 # Cycle average of tags in use
> system.cpu.icache.total_refs 7480626 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 1009306 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 7.411653 # Average number of references to valid blocks.
644c644
< system.cpu.icache.occ_blocks::cpu.inst 510.238404 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 510.238342 # Average occupied blocks per requestor
647,688c647,688
< system.cpu.icache.ReadReq_hits::cpu.inst 7486941 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 7486941 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 7486941 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 7486941 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 7486941 # number of overall hits
< system.cpu.icache.overall_hits::total 7486941 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1065537 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1065537 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1065537 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1065537 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1065537 # number of overall misses
< system.cpu.icache.overall_misses::total 1065537 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14679368493 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14679368493 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14679368493 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14679368493 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14679368493 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14679368493 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 8552478 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 8552478 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 8552478 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 8552478 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 8552478 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 8552478 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124588 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.124588 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.124588 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.124588 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.124588 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.124588 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.498135 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13776.498135 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13776.498135 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13776.498135 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 6928 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 616 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 184 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 37.652174 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 308 # average number of cycles each access was blocked
---
> system.cpu.icache.ReadReq_hits::cpu.inst 7480627 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 7480627 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 7480627 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 7480627 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 7480627 # number of overall hits
> system.cpu.icache.overall_hits::total 7480627 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1065018 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1065018 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1065018 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1065018 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1065018 # number of overall misses
> system.cpu.icache.overall_misses::total 1065018 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14700112992 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14700112992 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14700112992 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14700112992 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14700112992 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14700112992 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 8545645 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 8545645 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 8545645 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 8545645 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 8545645 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 8545645 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124627 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.124627 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.124627 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.124627 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.124627 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13802.689712 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13802.689712 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13802.689712 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13802.689712 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 5838 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 237 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 28.758621 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 237 # average number of cycles each access was blocked
691,720c691,720
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55502 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 55502 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 55502 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 55502 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 55502 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 55502 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010035 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1010035 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1010035 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1010035 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1010035 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1010035 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042197495 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12042197495 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042197495 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12042197495 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042197495 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12042197495 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118099 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.118099 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.118099 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.554659 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.554659 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.554659 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11922.554659 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.554659 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11922.554659 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55491 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 55491 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 55491 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 55491 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 55491 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 55491 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009527 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1009527 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1009527 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1009527 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1009527 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1009527 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12048771993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12048771993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12048771993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12048771993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12048771993 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12048771993 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118134 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.118134 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.118134 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11935.066613 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11935.066613 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency
722,726c722,726
< system.cpu.l2cache.replacements 338291 # number of replacements
< system.cpu.l2cache.tagsinuse 65364.646667 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 2546198 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 403460 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 6.310906 # Average number of references to valid blocks.
---
> system.cpu.l2cache.replacements 338275 # number of replacements
> system.cpu.l2cache.tagsinuse 65364.674694 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 2545615 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 403441 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 6.309758 # Average number of references to valid blocks.
728,739c728,739
< system.cpu.l2cache.occ_blocks::writebacks 54014.481347 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 5327.723075 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 6022.442245 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.824196 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.inst 0.081295 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.091895 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.997385 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 994848 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 827113 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1821961 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 840942 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 840942 # number of Writeback hits
---
> system.cpu.l2cache.occ_blocks::writebacks 54011.059986 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 5325.208257 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 6028.406451 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.824143 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.081256 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.091986 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.997386 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 994342 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 827132 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1821474 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 840875 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 840875 # number of Writeback hits
744,754c744,754
< system.cpu.l2cache.ReadExReq_hits::cpu.data 185617 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 185617 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 994848 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1012730 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2007578 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 994848 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1012730 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2007578 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 15075 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 273765 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 288840 # number of ReadReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 185593 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 185593 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 994342 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1012725 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2007067 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 994342 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1012725 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2007067 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 15068 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 273766 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 288834 # number of ReadReq misses
757,782c757,782
< system.cpu.l2cache.ReadExReq_misses::cpu.data 115444 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 115444 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 15075 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 389209 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 404284 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 15075 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 389209 # number of overall misses
< system.cpu.l2cache.overall_misses::total 404284 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1040084000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12407885000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 13447969000 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 291000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 291000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7693925000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7693925000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1040084000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 20101810000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 21141894000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1040084000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 20101810000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 21141894000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009923 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1100878 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2110801 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 840942 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 840942 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 115432 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 115432 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 15068 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 389198 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 404266 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 15068 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 389198 # number of overall misses
> system.cpu.l2cache.overall_misses::total 404266 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1052241000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12408474500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 13460715500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 274500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 274500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7669350500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7669350500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1052241000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 20077825000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21130066000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1052241000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 20077825000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21130066000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009410 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1100898 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2110308 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 840875 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 840875 # number of Writeback accesses(hits+misses)
787,797c787,797
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 301061 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 301061 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1009923 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1401939 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2411862 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1009923 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1401939 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2411862 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014927 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248679 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.136839 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 301025 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 301025 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1009410 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1401923 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2411333 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1009410 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1401923 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2411333 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014928 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248675 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.136868 # miss rate for ReadReq accesses
800,820c800,820
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383457 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383457 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014927 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.277622 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.167623 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014927 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.277622 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.167623 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68993.963516 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45323.123847 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 46558.541061 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8314.285714 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8314.285714 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66646.382662 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66646.382662 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68993.963516 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51647.855008 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52294.659200 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68993.963516 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51647.855008 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52294.659200 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014928 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.277617 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014928 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.277617 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69832.824529 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45325.111592 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 46603.639115 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7842.857143 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7842.857143 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66440.419468 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66440.419468 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52267.729663 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52267.729663 # average overall miss latency
829,830c829,830
< system.cpu.l2cache.writebacks::writebacks 75932 # number of writebacks
< system.cpu.l2cache.writebacks::total 75932 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 75909 # number of writebacks
> system.cpu.l2cache.writebacks::total 75909 # number of writebacks
837,839c837,839
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15074 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273765 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 288839 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15067 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273766 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 288833 # number of ReadReq MSHR misses
842,871c842,871
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115444 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 115444 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 15074 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 389209 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 404283 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 15074 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 389209 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 404283 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 852119347 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9058627177 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9910746524 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 507531 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 507531 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6283747927 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6283747927 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 852119347 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15342375104 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 16194494451 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 852119347 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15342375104 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 16194494451 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333816000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333816000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882705000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882705000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216521000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216521000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248679 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136839 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115432 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 115432 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 15067 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 389198 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 404265 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 15067 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 389198 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 404265 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 864374583 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9058859411 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9923233994 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 514531 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 514531 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6259293268 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6259293268 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 864374583 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15318152679 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 16182527262 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 864374583 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15318152679 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 16182527262 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333805500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333805500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882511000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882511000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216316500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216316500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248675 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136868 # mshr miss rate for ReadReq accesses
874,894c874,894
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383457 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383457 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.167623 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.167623 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56529.079674 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.062433 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34312.355755 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14500.885714 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14500.885714 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54431.134810 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54431.134810 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.167652 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.167652 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57368.725227 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.789861 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34356.302756 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700.885714 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700.885714 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54224.939947 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54224.939947 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency
902c902
< system.cpu.dcache.replacements 1401345 # number of replacements
---
> system.cpu.dcache.replacements 1401332 # number of replacements
904,906c904,906
< system.cpu.dcache.total_refs 11814052 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1401857 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 8.427430 # Average number of references to valid blocks.
---
> system.cpu.dcache.total_refs 11818848 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1401844 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 8.430930 # Average number of references to valid blocks.
911,916c911,916
< system.cpu.dcache.ReadReq_hits::cpu.data 7207582 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7207582 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4204734 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4204734 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 185999 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 185999 # number of LoadLockedReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 7212145 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7212145 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4204906 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4204906 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 186063 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 186063 # number of LoadLockedReq hits
919,926c919,926
< system.cpu.dcache.demand_hits::cpu.data 11412316 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 11412316 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 11412316 # number of overall hits
< system.cpu.dcache.overall_hits::total 11412316 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1803400 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1803400 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1942918 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1942918 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 11417051 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 11417051 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 11417051 # number of overall hits
> system.cpu.dcache.overall_hits::total 11417051 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1802577 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1802577 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1942748 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1942748 # number of WriteReq misses
931,940c931,940
< system.cpu.dcache.demand_misses::cpu.data 3746318 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3746318 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3746318 # number of overall misses
< system.cpu.dcache.overall_misses::total 3746318 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 34352879000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 34352879000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 65301849857 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 65301849857 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 305868500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 305868500 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 3745325 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3745325 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3745325 # number of overall misses
> system.cpu.dcache.overall_misses::total 3745325 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 34332308500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 34332308500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 65131487898 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 65131487898 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306015000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 306015000 # number of LoadLockedReq miss cycles
943,952c943,952
< system.cpu.dcache.demand_miss_latency::cpu.data 99654728857 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 99654728857 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 99654728857 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 99654728857 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9010982 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9010982 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6147652 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6147652 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208748 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 208748 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 99463796398 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 99463796398 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 99463796398 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 99463796398 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9014722 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9014722 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6147654 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6147654 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208812 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 208812 # number of LoadLockedReq accesses(hits+misses)
955,964c955,964
< system.cpu.dcache.demand_accesses::cpu.data 15158634 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15158634 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15158634 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15158634 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200134 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.200134 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316042 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.316042 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108978 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108978 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 15162376 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15162376 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15162376 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15162376 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199959 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.199959 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316015 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.316015 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108945 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108945 # miss rate for LoadLockedReq accesses
967,976c967,976
< system.cpu.dcache.demand_miss_rate::cpu.data 0.247141 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.247141 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.247141 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.247141 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19048.951425 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 19048.951425 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33610.193460 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 33610.193460 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13445.360236 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13445.360236 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.247014 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.247014 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.247014 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.247014 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19046.236860 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 19046.236860 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33525.443289 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33525.443289 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13451.800079 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13451.800079 # average LoadLockedReq miss latency
979,985c979,985
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26600.712715 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 26600.712715 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 2209173 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 1658 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 95967 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26556.786500 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 26556.786500 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 2193487 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 506 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 95928 # number of cycles access was blocked
987,988c987,988
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.020132 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 236.857143 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.865972 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 72.285714 # average number of cycles each access was blocked
991,1008c991,1008
< system.cpu.dcache.writebacks::writebacks 840942 # number of writebacks
< system.cpu.dcache.writebacks::total 840942 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719404 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 719404 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642459 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1642459 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2361863 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2361863 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2361863 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2361863 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083996 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1083996 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300459 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 300459 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17543 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17543 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 840875 # number of writebacks
> system.cpu.dcache.writebacks::total 840875 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718560 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 718560 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642321 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1642321 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5210 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 5210 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2360881 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2360881 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2360881 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2360881 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084017 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1084017 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300427 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 300427 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17539 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17539 # number of LoadLockedReq MSHR misses
1011,1020c1011,1020
< system.cpu.dcache.demand_mshr_misses::cpu.data 1384455 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1384455 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1384455 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1384455 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21792492000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 21792492000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9914016773 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 9914016773 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199792500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199792500 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 1384444 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1384444 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1384444 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1384444 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21793042000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 21793042000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9888893772 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 9888893772 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199306000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199306000 # number of LoadLockedReq MSHR miss cycles
1023,1038c1023,1038
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31706508773 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 31706508773 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31706508773 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 31706508773 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423893000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423893000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997872998 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997872998 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421765998 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421765998 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120297 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120297 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048874 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048874 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084039 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084039 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31681935772 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 31681935772 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31681935772 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 31681935772 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423882500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423882500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997678998 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997678998 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421561498 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421561498 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120250 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120250 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048869 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048869 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083994 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083994 # mshr miss rate for LoadLockedReq accesses
1041,1050c1041,1050
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091331 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091331 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.849092 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.849092 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32996.238332 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32996.238332 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11388.730548 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.730548 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091308 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091308 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714 # average LoadLockedReq mshr miss latency
1053,1056c1053,1056
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency
1065,1066c1065,1066
< system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211023 # number of hwrei instructions executed
---
> system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211025 # number of hwrei instructions executed
1070,1071c1070,1071
< system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182254 # number of times we switched to this ipl
---
> system.cpu.kern.ipl_count::31 105575 57.93% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182256 # number of times we switched to this ipl
1077,1081c1077,1081
< system.cpu.kern.ipl_ticks::0 1817865196000 98.03% 98.03% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 63825500 0.00% 98.04% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 556558000 0.03% 98.07% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 35823437500 1.93% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1854309017000 # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::0 1817868211500 98.03% 98.03% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 63824000 0.00% 98.04% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 559692500 0.03% 98.07% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 35817544000 1.93% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1854309272000 # number of cycles we spent at this ipl
1085,1086c1085,1086
< system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.694331 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl
1125c1125
< system.cpu.kern.callpal::swpipl 175139 91.23% 93.44% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175141 91.23% 93.44% # number of callpals executed
1134c1134
< system.cpu.kern.callpal::total 191983 # number of callpals executed
---
> system.cpu.kern.callpal::total 191985 # number of callpals executed
1136c1136
< system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
---
> system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
1138,1139c1138,1139
< system.cpu.kern.mode_good::kernel 1908
< system.cpu.kern.mode_good::user 1738
---
> system.cpu.kern.mode_good::kernel 1910
> system.cpu.kern.mode_good::user 1740
1141c1141
< system.cpu.kern.mode_switch_good::kernel 0.326210 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches
1144,1147c1144,1147
< system.cpu.kern.mode_switch_good::total 0.394052 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 29463172000 1.59% 1.59% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 2708574500 0.15% 1.73% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1822137262500 98.27% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 29467227000 1.59% 1.59% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 2708568500 0.15% 1.74% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1822133468500 98.26% 100.00% # number of ticks spent at the given mode