3,5c3,5
< sim_seconds 1.859851 # Number of seconds simulated
< sim_ticks 1859850554500 # Number of ticks simulated
< final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.858684 # Number of seconds simulated
> sim_ticks 1858684403000 # Number of ticks simulated
> final_tick 1858684403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,18c7,18
< host_inst_rate 188989 # Simulator instruction rate (inst/s)
< host_op_rate 188989 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6621174751 # Simulator tick rate (ticks/s)
< host_mem_usage 292896 # Number of bytes of host memory used
< host_seconds 280.89 # Real time elapsed on the host
< sim_insts 53085804 # Number of instructions simulated
< sim_ops 53085804 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read 29820864 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 10193536 # Number of bytes written to this memory
< system.physmem.num_reads 465951 # Number of read requests responded to by this memory
< system.physmem.num_writes 159274 # Number of write requests responded to by this memory
---
> host_inst_rate 192280 # Simulator instruction rate (inst/s)
> host_op_rate 192280 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 6731751609 # Simulator tick rate (ticks/s)
> host_mem_usage 292636 # Number of bytes of host memory used
> host_seconds 276.11 # Real time elapsed on the host
> sim_insts 53089851 # Number of instructions simulated
> sim_ops 53089851 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read 29847552 # Number of bytes read from this memory
> system.physmem.bytes_inst_read 1082432 # Number of instructions bytes read from this memory
> system.physmem.bytes_written 10195968 # Number of bytes written to this memory
> system.physmem.num_reads 466368 # Number of read requests responded to by this memory
> system.physmem.num_writes 159312 # Number of write requests responded to by this memory
20,43c20,43
< system.physmem.bw_read 16034011 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 572089 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 5480836 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 21514847 # Total bandwidth to/from this memory (bytes/s)
< system.l2c.replacements 391353 # number of replacements
< system.l2c.tagsinuse 34925.820021 # Cycle average of tags in use
< system.l2c.total_refs 2406767 # Total number of references to valid blocks.
< system.l2c.sampled_refs 424249 # Sample count of references to valid blocks.
< system.l2c.avg_refs 5.673006 # Average number of references to valid blocks.
< system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit.
< system.l2c.occ_blocks::writebacks 22620.354669 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.inst 4081.669847 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 8223.795506 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.345159 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.inst 0.062281 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.data 0.125485 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.532926 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu.inst 988583 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.data 812181 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1800764 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 835189 # number of Writeback hits
< system.l2c.Writeback_hits::total 835189 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits
---
> system.physmem.bw_read 16058429 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read 582365 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write 5485583 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total 21544012 # Total bandwidth to/from this memory (bytes/s)
> system.l2c.replacements 391653 # number of replacements
> system.l2c.tagsinuse 34933.081455 # Cycle average of tags in use
> system.l2c.total_refs 2427420 # Total number of references to valid blocks.
> system.l2c.sampled_refs 424662 # Sample count of references to valid blocks.
> system.l2c.avg_refs 5.716122 # Average number of references to valid blocks.
> system.l2c.warmup_cycle 5620155000 # Cycle when the warmup percentage was hit.
> system.l2c.occ_blocks::writebacks 22664.143946 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.inst 4133.885317 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.data 8135.052193 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.345827 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu.inst 0.063078 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu.data 0.124131 # Average percentage of cache occupancy
> system.l2c.occ_percent::total 0.533037 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu.inst 1009333 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.data 810762 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1820095 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 834721 # number of Writeback hits
> system.l2c.Writeback_hits::total 834721 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits
46,112c46,115
< system.l2c.ReadExReq_hits::cpu.data 183241 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 183241 # number of ReadExReq hits
< system.l2c.demand_hits::cpu.inst 988583 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.data 995422 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1984005 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu.inst 988583 # number of overall hits
< system.l2c.overall_hits::cpu.data 995422 # number of overall hits
< system.l2c.overall_hits::total 1984005 # number of overall hits
< system.l2c.ReadReq_misses::cpu.inst 16626 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.data 291511 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 308137 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 35 # number of UpgradeReq misses
< system.l2c.ReadExReq_misses::cpu.data 116889 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 116889 # number of ReadExReq misses
< system.l2c.demand_misses::cpu.inst 16626 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.data 408400 # number of demand (read+write) misses
< system.l2c.demand_misses::total 425026 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu.inst 16626 # number of overall misses
< system.l2c.overall_misses::cpu.data 408400 # number of overall misses
< system.l2c.overall_misses::total 425026 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu.inst 869674000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.data 15168138500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 16037812500 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu.data 424500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 424500 # number of UpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu.data 6132457500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 6132457500 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu.inst 869674000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.data 21300596000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 22170270000 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu.inst 869674000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.data 21300596000 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 22170270000 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu.inst 1005209 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.data 1103692 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2108901 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 835189 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 835189 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu.data 51 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 51 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu.data 300130 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 300130 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu.inst 1005209 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.data 1403822 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2409031 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu.inst 1005209 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.data 1403822 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2409031 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.data 0.264124 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu.data 0.686275 # miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu.data 0.389461 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.data 0.290920 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.data 0.290920 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu.inst 52308.071695 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu.data 52032.816943 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu.data 12128.571429 # average UpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu.data 52463.940148 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.inst 52308.071695 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.data 52156.209598 # average overall miss latency
---
> system.l2c.ReadExReq_hits::cpu.data 183748 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 183748 # number of ReadExReq hits
> system.l2c.demand_hits::cpu.inst 1009333 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.data 994510 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2003843 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu.inst 1009333 # number of overall hits
> system.l2c.overall_hits::cpu.data 994510 # number of overall hits
> system.l2c.overall_hits::total 2003843 # number of overall hits
> system.l2c.ReadReq_misses::cpu.inst 16915 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.data 291468 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 308383 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu.data 32 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 32 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu.data 117029 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 117029 # number of ReadExReq misses
> system.l2c.demand_misses::cpu.inst 16915 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.data 408497 # number of demand (read+write) misses
> system.l2c.demand_misses::total 425412 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu.inst 16915 # number of overall misses
> system.l2c.overall_misses::cpu.data 408497 # number of overall misses
> system.l2c.overall_misses::total 425412 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu.inst 884741000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu.data 15168191000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 16052932000 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu.data 425500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 425500 # number of UpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu.data 6138440500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 6138440500 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu.inst 884741000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu.data 21306631500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 22191372500 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu.inst 884741000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu.data 21306631500 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 22191372500 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu.inst 1026248 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.data 1102230 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2128478 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 834721 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 834721 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu.data 47 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 47 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu.data 300777 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 300777 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu.inst 1026248 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.data 1403007 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2429255 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu.inst 1026248 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.data 1403007 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2429255 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu.inst 0.016482 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.data 0.264435 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu.data 0.680851 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu.data 0.389089 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu.inst 0.016482 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.data 0.291158 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu.inst 0.016482 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.data 0.291158 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu.inst 52305.113804 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu.data 52040.673419 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13296.875000 # average UpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu.data 52452.302421 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu.inst 52305.113804 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu.data 52158.599696 # average overall miss latency
121,170c124,185
< system.l2c.writebacks::writebacks 117762 # number of writebacks
< system.l2c.writebacks::total 117762 # number of writebacks
< system.l2c.ReadReq_mshr_misses::cpu.inst 16626 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.data 291511 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 308137 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu.data 116889 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 116889 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu.inst 16626 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.data 408400 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 425026 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu.inst 16626 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.data 408400 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 425026 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu.inst 666148500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.data 11667923000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 12334071500 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1460000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 1460000 # number of UpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4711233500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 4711233500 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.inst 666148500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.data 16379156500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 17045305000 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.inst 666148500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.data 16379156500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 17045305000 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809589500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 809589500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114928998 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 1114928998 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924518498 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 1924518498 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264124 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.686275 # mshr miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389461 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.data 0.290920 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.672681 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40025.669700 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41714.285714 # average UpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40305.191250 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40066.672681 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.data 40105.672135 # average overall mshr miss latency
---
> system.l2c.writebacks::writebacks 117800 # number of writebacks
> system.l2c.writebacks::total 117800 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu.inst 16914 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu.data 291468 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 308382 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu.data 32 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 32 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu.data 117029 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 117029 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu.inst 16914 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu.data 408497 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 425411 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu.inst 16914 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu.data 408497 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 425411 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu.inst 677644000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu.data 11668187500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 12345831500 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 1343000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 1343000 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 40000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 40000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4714582500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 4714582500 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu.inst 677644000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu.data 16382770000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 17060414000 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu.inst 677644000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu.data 16382770000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 17060414000 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 809666500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 809666500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1114488498 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 1114488498 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu.data 1924154998 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 1924154998 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.264435 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.680851 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.389089 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu.inst 0.016481 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu.data 0.291158 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40064.088920 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40032.482125 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41968.750000 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40285.591605 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40064.088920 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu.data 40104.994651 # average overall mshr miss latency
176c191
< system.iocache.tagsinuse 1.276011 # Cycle average of tags in use
---
> system.iocache.tagsinuse 1.266745 # Cycle average of tags in use
180,183c195,198
< system.iocache.warmup_cycle 1708338781000 # Cycle when the warmup percentage was hit.
< system.iocache.occ_blocks::tsunami.ide 1.276011 # Average occupied blocks per requestor
< system.iocache.occ_percent::tsunami.ide 0.079751 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.079751 # Average percentage of cache occupancy
---
> system.iocache.warmup_cycle 1708341003000 # Cycle when the warmup percentage was hit.
> system.iocache.occ_blocks::tsunami.ide 1.266745 # Average occupied blocks per requestor
> system.iocache.occ_percent::tsunami.ide 0.079172 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.079172 # Average percentage of cache occupancy
194,199c209,214
< system.iocache.WriteReq_miss_latency::tsunami.ide 5721891806 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 5721891806 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 5741829804 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 5741829804 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 5741829804 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 5741829804 # number of overall miss cycles
---
> system.iocache.WriteReq_miss_latency::tsunami.ide 5721838806 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 5721838806 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 5741776804 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5741776804 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5741776804 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5741776804 # number of overall miss cycles
213,216c228,231
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.365759 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 137611.259533 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked
---
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137703.090248 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 137609.989311 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 64629068 # number of cycles access was blocked
218c233
< system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
220c235
< system.iocache.avg_blocked_cycles::no_mshrs 6168.215752 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6169.250477 # average number of cycles each access was blocked
236,241c251,256
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561041984 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 3561041984 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 3571983982 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 3571983982 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 3571983982 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 3571983982 # number of overall MSHR miss cycles
---
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560986994 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 3560986994 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3571928992 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3571928992 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3571928992 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3571928992 # number of overall MSHR miss cycles
247,249c262,264
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85700.856373 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.764697 # average overall mshr miss latency
---
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85699.532971 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85606.446783 # average overall mshr miss latency
267,282c282,297
< system.cpu.dtb.read_hits 10136178 # DTB read hits
< system.cpu.dtb.read_misses 46729 # DTB read misses
< system.cpu.dtb.read_acv 584 # DTB read access violations
< system.cpu.dtb.read_accesses 970980 # DTB read accesses
< system.cpu.dtb.write_hits 6626287 # DTB write hits
< system.cpu.dtb.write_misses 12218 # DTB write misses
< system.cpu.dtb.write_acv 419 # DTB write access violations
< system.cpu.dtb.write_accesses 347267 # DTB write accesses
< system.cpu.dtb.data_hits 16762465 # DTB hits
< system.cpu.dtb.data_misses 58947 # DTB misses
< system.cpu.dtb.data_acv 1003 # DTB access violations
< system.cpu.dtb.data_accesses 1318247 # DTB accesses
< system.cpu.itb.fetch_hits 1326719 # ITB hits
< system.cpu.itb.fetch_misses 39613 # ITB misses
< system.cpu.itb.fetch_acv 1063 # ITB acv
< system.cpu.itb.fetch_accesses 1366332 # ITB accesses
---
> system.cpu.dtb.read_hits 10017178 # DTB read hits
> system.cpu.dtb.read_misses 45828 # DTB read misses
> system.cpu.dtb.read_acv 561 # DTB read access violations
> system.cpu.dtb.read_accesses 954843 # DTB read accesses
> system.cpu.dtb.write_hits 6639084 # DTB write hits
> system.cpu.dtb.write_misses 10800 # DTB write misses
> system.cpu.dtb.write_acv 415 # DTB write access violations
> system.cpu.dtb.write_accesses 340295 # DTB write accesses
> system.cpu.dtb.data_hits 16656262 # DTB hits
> system.cpu.dtb.data_misses 56628 # DTB misses
> system.cpu.dtb.data_acv 976 # DTB access violations
> system.cpu.dtb.data_accesses 1295138 # DTB accesses
> system.cpu.itb.fetch_hits 1345400 # ITB hits
> system.cpu.itb.fetch_misses 36691 # ITB misses
> system.cpu.itb.fetch_acv 1385 # ITB acv
> system.cpu.itb.fetch_accesses 1382091 # ITB accesses
295c310
< system.cpu.numCycles 116271514 # number of cpu cycles simulated
---
> system.cpu.numCycles 115937106 # number of cpu cycles simulated
298,302c313,317
< system.cpu.BPredUnit.lookups 14404381 # Number of BP lookups
< system.cpu.BPredUnit.condPredicted 12049368 # Number of conditional branches predicted
< system.cpu.BPredUnit.condIncorrect 531407 # Number of conditional branches incorrect
< system.cpu.BPredUnit.BTBLookups 13004312 # Number of BTB lookups
< system.cpu.BPredUnit.BTBHits 6709840 # Number of BTB hits
---
> system.cpu.BPredUnit.lookups 14171679 # Number of BP lookups
> system.cpu.BPredUnit.condPredicted 11793956 # Number of conditional branches predicted
> system.cpu.BPredUnit.condIncorrect 477051 # Number of conditional branches incorrect
> system.cpu.BPredUnit.BTBLookups 10388735 # Number of BTB lookups
> system.cpu.BPredUnit.BTBHits 5970315 # Number of BTB hits
304,321c319,336
< system.cpu.BPredUnit.usedRAS 971693 # Number of times the RAS was used to get a target.
< system.cpu.BPredUnit.RASInCorrect 45037 # Number of incorrect RAS predictions.
< system.cpu.fetch.icacheStallCycles 29087793 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 73522129 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 14404381 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 7681533 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 14275065 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 2363223 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 36625670 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 33401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 258943 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 335385 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 155 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 9051216 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 322280 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 82158877 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.894877 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.211744 # Number of instructions fetched each cycle (Total)
---
> system.cpu.BPredUnit.usedRAS 956584 # Number of times the RAS was used to get a target.
> system.cpu.BPredUnit.RASInCorrect 68437 # Number of incorrect RAS predictions.
> system.cpu.fetch.icacheStallCycles 29509897 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 72276663 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 14171679 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 6926899 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 13625760 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 2211095 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 36451359 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 33988 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 254368 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 318126 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 9001683 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 320234 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 81638301 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.885328 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.224856 # Number of instructions fetched each cycle (Total)
323,331c338,346
< system.cpu.fetch.rateDist::0 67883812 82.63% 82.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1025449 1.25% 83.87% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 2024221 2.46% 86.34% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 965546 1.18% 87.51% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2955118 3.60% 91.11% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 688428 0.84% 91.95% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 786197 0.96% 92.90% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1069042 1.30% 94.21% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 4761064 5.79% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 68012541 83.31% 83.31% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 890285 1.09% 84.40% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 1788287 2.19% 86.59% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 860446 1.05% 87.64% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2806697 3.44% 91.08% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 613121 0.75% 91.83% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 690439 0.85% 92.68% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1018441 1.25% 93.93% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 4958044 6.07% 100.00% # Number of instructions fetched each cycle (Total)
335,379c350,394
< system.cpu.fetch.rateDist::total 82158877 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.123886 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.632331 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 30342810 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 36285765 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 13055396 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 974232 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1500673 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 609120 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 42110 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 71910719 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 128198 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 1500673 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 31545269 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 12820046 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 19759905 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 12205401 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 4327581 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 67985937 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 6903 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 504868 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 1537776 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 45488593 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 82604485 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 82125154 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 479331 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 38256265 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 7232320 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1700161 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 251408 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 12102195 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 10719689 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 6992362 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1255856 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 835149 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 59697251 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2115237 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 57966423 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 118182 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 8327603 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 4293139 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1447692 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 82158877 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.705541 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.352283 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 81638301 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.122236 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.623413 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 30605398 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 36211579 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 12459009 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 962410 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1399904 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 626907 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 46406 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 70869283 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 128122 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 1399904 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 31751021 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 12870145 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 19629693 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 11657858 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 4329678 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 67084686 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 6936 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 509202 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 1545669 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 44883895 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 81279618 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 80782275 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 497343 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 38259023 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 6624872 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1702108 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 250876 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 12154886 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 10647937 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 6996260 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1317222 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 890257 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 59186479 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2094113 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 57496699 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 116770 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 7805626 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 4020701 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1426389 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 81638301 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.704286 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.361652 # Number of insts issued each cycle
381,389c396,404
< system.cpu.iq.issued_per_cycle::0 56706238 69.02% 69.02% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 11186331 13.62% 82.64% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 5491014 6.68% 89.32% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 3497852 4.26% 93.58% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 2643618 3.22% 96.79% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 1562284 1.90% 98.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 690020 0.84% 99.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 273664 0.33% 99.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 107856 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 56549177 69.27% 69.27% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 11085908 13.58% 82.85% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 5246792 6.43% 89.27% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 3470006 4.25% 93.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 2637448 3.23% 96.76% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 1477237 1.81% 98.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 737523 0.90% 99.47% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 327606 0.40% 99.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 106604 0.13% 100.00% # Number of insts issued each cycle
393c408
< system.cpu.iq.issued_per_cycle::total 82158877 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 81638301 # Number of insts issued each cycle
395,425c410,440
< system.cpu.iq.fu_full::IntAlu 66675 8.67% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 379311 49.30% 57.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 323479 42.04% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 90136 11.38% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.38% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 378271 47.76% 59.14% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 323650 40.86% 100.00% # attempts to use FU when none available
429,460c444,475
< system.cpu.iq.FU_type_0::IntAlu 39589342 68.30% 68.31% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 62143 0.11% 68.42% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.42% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.47% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 10612322 18.31% 86.77% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 6714161 11.58% 98.36% # Type of FU issued
< system.cpu.iq.FU_type_0::IprAccess 951931 1.64% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 39231645 68.23% 68.25% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 61830 0.11% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.35% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 10492080 18.25% 86.65% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 6722416 11.69% 98.34% # Type of FU issued
> system.cpu.iq.FU_type_0::IprAccess 952204 1.66% 100.00% # Type of FU issued
462,474c477,489
< system.cpu.iq.FU_type_0::total 57966423 # Type of FU issued
< system.cpu.iq.rate 0.498544 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 769465 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.013274 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 198287117 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 69820873 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 56409682 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 692252 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 333301 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 328338 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 58365379 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 363228 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 574200 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 57496699 # Type of FU issued
> system.cpu.iq.rate 0.495930 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 792057 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.013776 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 196846794 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 68765054 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 56061076 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 693732 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 333965 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 328206 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 57917538 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 363937 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 590984 # Number of loads that had data forwarded from stores
476,479c491,494
< system.cpu.iew.lsq.thread0.squashedLoads 1607370 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 13516 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 14481 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 600235 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1535089 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 3470 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 13124 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 604028 # Number of stores squashed
482,483c497,498
< system.cpu.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 173076 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 18323 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 170629 # Number of times an access to memory failed due to the cache being blocked
485,501c500,516
< system.cpu.iew.iewSquashCycles 1500673 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 8975371 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 617328 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 65437961 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 865160 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 10719689 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 6992362 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1868933 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 485175 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 15743 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 14481 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 386643 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 382870 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 769513 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 57271021 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 10213321 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 695401 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 1399904 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 9017933 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 616152 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 64867759 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 849536 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 10647937 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 6996260 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1840231 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 482623 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 15971 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 13124 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 267386 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 425155 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 692541 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 56871146 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 10095387 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 625553 # Number of squashed instructions skipped in execute
503,511c518,526
< system.cpu.iew.exec_nop 3625473 # number of nop insts executed
< system.cpu.iew.exec_refs 16867223 # number of memory reference insts executed
< system.cpu.iew.exec_branches 9097936 # Number of branches executed
< system.cpu.iew.exec_stores 6653902 # Number of stores executed
< system.cpu.iew.exec_rate 0.492563 # Inst execution rate
< system.cpu.iew.wb_sent 56871872 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 56738020 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 28030988 # num instructions producing a value
< system.cpu.iew.wb_consumers 37770905 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 3587167 # number of nop insts executed
> system.cpu.iew.exec_refs 16760622 # number of memory reference insts executed
> system.cpu.iew.exec_branches 9006504 # Number of branches executed
> system.cpu.iew.exec_stores 6665235 # Number of stores executed
> system.cpu.iew.exec_rate 0.490534 # Inst execution rate
> system.cpu.iew.wb_sent 56517124 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 56389282 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 27888094 # num instructions producing a value
> system.cpu.iew.wb_consumers 37753450 # num instructions consuming a value
513,514c528,529
< system.cpu.iew.wb_rate 0.487979 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.486378 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.738690 # average fanout of values written-back
516,523c531,538
< system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions
< system.cpu.commit.commitCommittedOps 56280196 # The number of committed instructions
< system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 80658204 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.697762 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.611283 # Number of insts commited each cycle
---
> system.cpu.commit.commitCommittedInsts 56284358 # The number of committed instructions
> system.cpu.commit.commitCommittedOps 56284358 # The number of committed instructions
> system.cpu.commit.commitSquashedInsts 8468547 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 667724 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 643899 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 80238397 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.701464 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.625122 # Number of insts commited each cycle
525,533c540,548
< system.cpu.commit.committed_per_cycle::0 59481462 73.75% 73.75% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 8887876 11.02% 84.76% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 4721135 5.85% 90.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2612091 3.24% 93.86% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1531941 1.90% 95.76% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 645193 0.80% 96.56% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 475603 0.59% 97.14% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 516794 0.64% 97.79% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 1786109 2.21% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 59258262 73.85% 73.85% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 8767408 10.93% 84.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 4647312 5.79% 90.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2573487 3.21% 93.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1500960 1.87% 95.65% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 651575 0.81% 96.46% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 486922 0.61% 97.07% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 501150 0.62% 97.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 1851321 2.31% 100.00% # Number of insts commited each cycle
537,539c552,554
< system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 56280196 # Number of instructions committed
< system.cpu.commit.committedOps 56280196 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 80238397 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 56284358 # Number of instructions committed
> system.cpu.commit.committedOps 56284358 # Number of ops (including micro ops) committed
541,544c556,559
< system.cpu.commit.refs 15504446 # Number of memory references committed
< system.cpu.commit.loads 9112319 # Number of loads committed
< system.cpu.commit.membars 227818 # Number of memory barriers committed
< system.cpu.commit.branches 8461284 # Number of branches committed
---
> system.cpu.commit.refs 15505080 # Number of memory references committed
> system.cpu.commit.loads 9112848 # Number of loads committed
> system.cpu.commit.membars 227858 # Number of memory barriers committed
> system.cpu.commit.branches 8462387 # Number of branches committed
546,548c561,563
< system.cpu.commit.int_insts 52119152 # Number of committed integer instructions.
< system.cpu.commit.function_calls 744404 # Number of function calls committed.
< system.cpu.commit.bw_lim_events 1786109 # number cycles where commit BW limit reached
---
> system.cpu.commit.int_insts 52122951 # Number of committed integer instructions.
> system.cpu.commit.function_calls 744427 # Number of function calls committed.
> system.cpu.commit.bw_lim_events 1851321 # number cycles where commit BW limit reached
550,567c565,582
< system.cpu.rob.rob_reads 143937484 # The number of ROB reads
< system.cpu.rob.rob_writes 132136289 # The number of ROB writes
< system.cpu.timesIdled 1255783 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 53085804 # Number of Instructions Simulated
< system.cpu.committedOps 53085804 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated
< system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.456568 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.456568 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 75080091 # number of integer regfile reads
< system.cpu.int_regfile_writes 40965330 # number of integer regfile writes
< system.cpu.fp_regfile_reads 166532 # number of floating regfile reads
< system.cpu.fp_regfile_writes 167403 # number of floating regfile writes
< system.cpu.misc_regfile_reads 1996306 # number of misc regfile reads
< system.cpu.misc_regfile_writes 949674 # number of misc regfile writes
---
> system.cpu.rob.rob_reads 142888950 # The number of ROB reads
> system.cpu.rob.rob_writes 130907900 # The number of ROB writes
> system.cpu.timesIdled 1275123 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 34298805 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 3601425271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 53089851 # Number of Instructions Simulated
> system.cpu.committedOps 53089851 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 53089851 # Number of Instructions Simulated
> system.cpu.cpi 2.183790 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.183790 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.457919 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.457919 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 74514493 # number of integer regfile reads
> system.cpu.int_regfile_writes 40703979 # number of integer regfile writes
> system.cpu.fp_regfile_reads 166152 # number of floating regfile reads
> system.cpu.fp_regfile_writes 167434 # number of floating regfile writes
> system.cpu.misc_regfile_reads 1998995 # number of misc regfile reads
> system.cpu.misc_regfile_writes 949957 # number of misc regfile writes
599,638c614,653
< system.cpu.icache.replacements 1004588 # number of replacements
< system.cpu.icache.tagsinuse 509.963959 # Cycle average of tags in use
< system.cpu.icache.total_refs 7985769 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 509.963959 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.996023 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.996023 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 7985770 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 7985770 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 7985770 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 7985770 # number of overall hits
< system.cpu.icache.overall_hits::total 7985770 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1065446 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1065446 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1065446 # number of overall misses
< system.cpu.icache.overall_misses::total 1065446 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15927822494 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15927822494 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15927822494 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15927822494 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15927822494 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15927822494 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 9051216 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 9051216 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 9051216 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 9051216 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117713 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.117713 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.117713 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14949.441355 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14949.441355 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked
---
> system.cpu.icache.replacements 1025621 # number of replacements
> system.cpu.icache.tagsinuse 509.964536 # Cycle average of tags in use
> system.cpu.icache.total_refs 7915589 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 1026130 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 7.714022 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 23323095000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 509.964536 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.996024 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.996024 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 7915590 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 7915590 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 7915590 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 7915590 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 7915590 # number of overall hits
> system.cpu.icache.overall_hits::total 7915590 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1086093 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1086093 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1086093 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1086093 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1086093 # number of overall misses
> system.cpu.icache.overall_misses::total 1086093 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 16268467995 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 16268467995 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 16268467995 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 16268467995 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 16268467995 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 16268467995 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 9001683 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 9001683 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 9001683 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 9001683 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 9001683 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 9001683 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120654 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.120654 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.120654 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.890385 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.890385 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 1679497 # number of cycles access was blocked
640c655
< system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 150 # number of cycles access was blocked
642c657
< system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 11196.646667 # average number of cycles each access was blocked
646,671c661,686
< system.cpu.icache.writebacks::writebacks 234 # number of writebacks
< system.cpu.icache.writebacks::total 234 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60134 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 60134 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 60134 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 60134 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 60134 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 60134 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1005312 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1005312 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1005312 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1005312 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1005312 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1005312 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12047333996 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12047333996 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12047333996 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12047333996 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12047333996 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12047333996 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.676705 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency
---
> system.cpu.icache.writebacks::writebacks 238 # number of writebacks
> system.cpu.icache.writebacks::total 238 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59750 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 59750 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 59750 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 59750 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 59750 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 59750 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026343 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1026343 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1026343 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1026343 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1026343 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1026343 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12299507497 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12299507497 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12299507497 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12299507497 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12299507497 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12299507497 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114017 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.817785 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.817785 # average overall mshr miss latency
673,679c688,694
< system.cpu.dcache.replacements 1403406 # number of replacements
< system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use
< system.cpu.dcache.total_refs 12086534 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 511.996008 # Average occupied blocks per requestor
---
> system.cpu.dcache.replacements 1402627 # number of replacements
> system.cpu.dcache.tagsinuse 511.995944 # Cycle average of tags in use
> system.cpu.dcache.total_refs 11951343 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1403139 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 8.517576 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 19459000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 511.995944 # Average occupied blocks per requestor
682,747c697,762
< system.cpu.dcache.ReadReq_hits::cpu.data 7453772 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4220462 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 192050 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 220033 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 11674234 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 11674234 # number of overall hits
< system.cpu.dcache.overall_hits::total 11674234 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1809182 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1936475 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22599 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 3745657 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3745657 # number of overall misses
< system.cpu.dcache.overall_misses::total 3745657 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 38930236000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 38930236000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 57815325976 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 57815325976 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338636000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 338636000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 28500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 28500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 96745561976 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 96745561976 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 96745561976 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 96745561976 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9262954 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6156937 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214649 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 220035 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15419891 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15419891 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195314 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314519 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.105284 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.242911 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.242911 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21518.142453 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29855.963013 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14984.556839 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14250 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 9036.683421 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked
---
> system.cpu.dcache.ReadReq_hits::cpu.data 7323424 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7323424 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4214108 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4214108 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 193501 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 193501 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 220102 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 220102 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 11537532 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 11537532 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 11537532 # number of overall hits
> system.cpu.dcache.overall_hits::total 11537532 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1804216 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1804216 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1942860 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1942860 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 23377 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 23377 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 3747076 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3747076 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3747076 # number of overall misses
> system.cpu.dcache.overall_misses::total 3747076 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 38906858000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 38906858000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 58108807026 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 58108807026 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 346630500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 346630500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83500 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 83500 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 97015665026 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 97015665026 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 97015665026 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 97015665026 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9127640 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9127640 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6156968 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6156968 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 216878 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 216878 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 220105 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 220105 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15284608 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15284608 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15284608 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15284608 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.197665 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315555 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107789 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000014 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.245154 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.245154 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21564.412465 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29908.900809 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14827.843607 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27833.333333 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 25891.032108 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 927127320 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 101622 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 9123.293381 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked
750,803c765,818
< system.cpu.dcache.writebacks::writebacks 834955 # number of writebacks
< system.cpu.dcache.writebacks::total 834955 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721461 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 721461 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1637588 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1637588 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5103 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 5103 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2359049 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2359049 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2359049 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2359049 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1087721 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1087721 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298887 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298887 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17496 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17496 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1386608 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1386608 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1386608 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1386608 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24804888500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 24804888500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509686826 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509686826 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206420500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206420500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33314575326 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 33314575326 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33314575326 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 33314575326 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904009500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904009500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234178998 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234178998 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138188498 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138188498 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.117427 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048545 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.081510 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 834483 # number of writebacks
> system.cpu.dcache.writebacks::total 834483 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718769 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 718769 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643008 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1643008 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5385 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 5385 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2361777 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2361777 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2361777 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2361777 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1085447 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1085447 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299852 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 299852 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17992 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17992 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1385299 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1385299 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1385299 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1385299 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24777383500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 24777383500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8529644820 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8529644820 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212567500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212567500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 74000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 74000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307028320 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 33307028320 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33307028320 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 33307028320 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904080500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904080500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1233731998 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1233731998 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2137812498 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 2137812498 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118919 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048701 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082959 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000014 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090634 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22826.893897 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28446.182850 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11814.556470 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24666.666667 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24043.205344 # average overall mshr miss latency
809,811c824,826
< system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211491 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74854 40.97% 40.97% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6430 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211556 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74875 40.96% 40.96% # number of times we switched to this ipl
813,816c828,831
< system.cpu.kern.ipl_count::22 1878 1.03% 42.13% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 105750 57.87% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182723 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73487 49.29% 49.29% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::22 1880 1.03% 42.12% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 105790 57.88% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182786 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73508 49.29% 49.29% # number of times we switched to this ipl from a different ipl
818,826c833,841
< system.cpu.kern.ipl_good::22 1878 1.26% 50.71% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73489 49.29% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 149095 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1821211214000 97.92% 97.92% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 93652500 0.01% 97.93% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 383616500 0.02% 97.95% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 38161211000 2.05% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1859849694000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981738 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1880 1.26% 50.71% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73510 49.29% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 149139 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1820018970500 97.92% 97.92% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 94294500 0.01% 97.92% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 380287500 0.02% 97.95% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 38189985000 2.05% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1858683537500 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl
829c844
< system.cpu.kern.ipl_used::31 0.694931 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.694867 # fraction of swpipl calls that actually changed the ipl
868,869c883,884
< system.cpu.kern.callpal::swpipl 175394 91.19% 93.39% # number of callpals executed
< system.cpu.kern.callpal::rdps 6783 3.53% 96.92% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175453 91.19% 93.39% # number of callpals executed
> system.cpu.kern.callpal::rdps 6785 3.53% 96.92% # number of callpals executed
874c889
< system.cpu.kern.callpal::rti 5211 2.71% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5213 2.71% 99.64% # number of callpals executed
877,882c892,897
< system.cpu.kern.callpal::total 192344 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches
< system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
< system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1909
< system.cpu.kern.mode_good::user 1739
---
> system.cpu.kern.callpal::total 192407 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5952 # number of protection mode switches
> system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
> system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1910
> system.cpu.kern.mode_good::user 1740
884c899
< system.cpu.kern.mode_switch_good::kernel 0.320948 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.320901 # fraction of useful protection mode switches
886,890c901,905
< system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 1.401708 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 29148036500 1.57% 1.57% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 2681917500 0.14% 1.71% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1828019732000 98.29% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 1.401737 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 29137471500 1.57% 1.57% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 2698722000 0.15% 1.71% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1826847336000 98.29% 100.00% # number of ticks spent at the given mode