3,5c3,5
< sim_seconds 1.876794 # Number of seconds simulated
< sim_ticks 1876794488000 # Number of ticks simulated
< final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.862042 # Number of seconds simulated
> sim_ticks 1862042063000 # Number of ticks simulated
> final_tick 1862042063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 152079 # Simulator instruction rate (inst/s)
< host_op_rate 152079 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5387044029 # Simulator tick rate (ticks/s)
< host_mem_usage 330796 # Number of bytes of host memory used
< host_seconds 348.39 # Real time elapsed on the host
< sim_insts 52982943 # Number of instructions simulated
< sim_ops 52982943 # Number of ops (including micro ops) simulated
---
> host_inst_rate 137297 # Simulator instruction rate (inst/s)
> host_op_rate 137297 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4825772422 # Simulator tick rate (ticks/s)
> host_mem_usage 338492 # Number of bytes of host memory used
> host_seconds 385.85 # Real time elapsed on the host
> sim_insts 52976505 # Number of instructions simulated
> sim_ops 52976505 # Number of ops (including micro ops) simulated
16,18c16,18
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 963392 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24881792 # Number of bytes read from this memory
20,26c20,26
< system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7527680 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 15027 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25846144 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 963392 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 963392 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7528832 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7528832 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 15053 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388778 # Number of read requests responded to by this memory
28,53c28,53
< system.physmem.num_reads::total 403799 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 117620 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 117620 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 512431 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13256885 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 13769827 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 512431 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 512431 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4010924 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4010924 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4010924 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 512431 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13256885 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17780751 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 403799 # Number of read requests accepted
< system.physmem.writeReqs 117620 # Number of write requests accepted
< system.physmem.readBursts 403799 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 117620 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25835776 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7525824 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25843136 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7527680 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::total 403846 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 117638 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 117638 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 517385 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 13362637 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 13880537 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 517385 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 517385 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4043320 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4043320 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4043320 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 517385 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 13362637 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17923857 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 403846 # Number of read requests accepted
> system.physmem.writeReqs 117638 # Number of write requests accepted
> system.physmem.readBursts 403846 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 117638 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25839232 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7527104 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25846144 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7528832 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue
56,87c56,87
< system.physmem.perBankRdBursts::0 25625 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25421 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25559 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25464 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25431 # Per bank write bursts
< system.physmem.perBankRdBursts::5 24732 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24935 # Per bank write bursts
< system.physmem.perBankRdBursts::7 25090 # Per bank write bursts
< system.physmem.perBankRdBursts::8 24946 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25020 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25560 # Per bank write bursts
< system.physmem.perBankRdBursts::11 24886 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24460 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25266 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25703 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25586 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7949 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7513 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7969 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7485 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7367 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6667 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6767 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6715 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7150 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6697 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7421 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6978 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7150 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7899 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8060 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7804 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 25618 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25426 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25537 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25512 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25419 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24740 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24937 # Per bank write bursts
> system.physmem.perBankRdBursts::7 25096 # Per bank write bursts
> system.physmem.perBankRdBursts::8 24930 # Per bank write bursts
> system.physmem.perBankRdBursts::9 25035 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25569 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24892 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24450 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25273 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25713 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25591 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7930 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7514 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7945 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7523 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7351 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6673 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6769 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6726 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7138 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6708 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7428 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6991 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7147 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7895 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8063 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7810 # Per bank write bursts
89,90c89,90
< system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
< system.physmem.totGap 1876789160500 # Total gap between requests
---
> system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
> system.physmem.totGap 1862036687500 # Total gap between requests
97c97
< system.physmem.readPktSize::6 403799 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 403846 # Read request sizes (log2)
104,110c104,110
< system.physmem.writePktSize::6 117620 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 315619 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 35764 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 28247 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 23961 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 117638 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 315267 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 36112 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 28338 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 23939 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see
152,181c152,181
< system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2968 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4960 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4449 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6001 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5883 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6949 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6473 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8556 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8916 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7560 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7602 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6731 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5823 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 100 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1560 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2800 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 3376 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4390 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5897 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6646 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7683 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 9037 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7269 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7983 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8709 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7918 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7106 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7375 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7621 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5960 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5674 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see
183,218c183,218
< system.physmem.wrQLenPdf::46 200 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 43 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 62139 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 536.886657 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 331.247155 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 411.697741 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 13677 22.01% 22.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 10478 16.86% 38.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4968 7.99% 46.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2775 4.47% 51.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2441 3.93% 55.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1588 2.56% 57.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3776 6.08% 63.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1174 1.89% 65.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 21262 34.22% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 62139 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5217 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 77.374545 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2903.927058 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5214 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 205 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 154 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 110 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 63 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 61611 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 541.558358 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 333.246769 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 417.180517 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 13396 21.74% 21.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 10505 17.05% 38.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5359 8.70% 47.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2621 4.25% 51.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2461 3.99% 55.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1425 2.31% 58.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1507 2.45% 60.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1351 2.19% 62.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 22986 37.31% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 61611 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5236 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 77.104660 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2917.579007 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5233 99.94% 99.94% # Reads before turning the bus around for writes
222,239c222,241
< system.physmem.rdPerTurnAround::total 5217 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5217 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.539965 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.244136 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 20.635763 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4619 88.54% 88.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 29 0.56% 89.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 25 0.48% 89.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 38 0.73% 90.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 214 4.10% 94.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 9 0.17% 94.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 11 0.21% 94.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 34 0.65% 95.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 184 3.53% 98.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 5 0.10% 99.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 5 0.10% 99.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 4 0.08% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 6 0.12% 99.35% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5236 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5236 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.461994 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 19.033018 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 22.013556 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4631 88.45% 88.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 42 0.80% 89.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 243 4.64% 93.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-47 21 0.40% 94.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-55 6 0.11% 94.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-63 10 0.19% 94.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-71 6 0.11% 94.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 2 0.04% 94.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 20 0.38% 95.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-95 23 0.44% 95.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-103 185 3.53% 99.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 2 0.04% 99.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-119 3 0.06% 99.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-127 1 0.02% 99.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-135 7 0.13% 99.35% # Writes before turning the bus around for reads
242,255c244,258
< system.physmem.wrPerTurnAround::160-167 4 0.08% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 8 0.15% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 4 0.08% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 3 0.06% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-215 6 0.12% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-263 2 0.04% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5217 # Writes before turning the bus around for reads
< system.physmem.totQLat 4201005000 # Total ticks spent queuing
< system.physmem.totMemAccLat 11770080000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2018420000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10406.67 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::152-159 3 0.06% 99.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-167 2 0.04% 99.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-175 11 0.21% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-215 3 0.06% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5236 # Writes before turning the bus around for reads
> system.physmem.totQLat 3726058000 # Total ticks spent queuing
> system.physmem.totMemAccLat 11296145500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2018690000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9228.90 # Average queueing delay per DRAM burst
257,261c260,264
< system.physmem.avgMemAccLat 29156.67 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27978.90 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.88 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s
267,284c270,287
< system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing
< system.physmem.readRowHits 363845 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95291 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 90.13 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes
< system.physmem.avgGap 3599387.75 # Average gap between requests
< system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 233399880 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 127351125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1577604600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 378639360 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 61740410985 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1071915840750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1258556040540 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.589641 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1783024934000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 62670140000 # Time in different power states
---
> system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing
> system.physmem.readRowHits 364089 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95648 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 90.18 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 81.31 # Row buffer hit rate for writes
> system.physmem.avgGap 3570649.70 # Average gap between requests
> system.physmem.pageHitRate 88.18 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 230882400 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 125977500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1577823000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 378632880 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 56327619735 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1067810937000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1248070945155 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.272471 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1776230272500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 62177440000 # Time in different power states
286c289
< system.physmem_0.memoryStateTime::ACT 31095099750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 23627517500 # Time in different power states
288,298c291,301
< system.physmem_1.actEnergy 236370960 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 128972250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1571130600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 383350320 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 61477234290 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.573928 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states
---
> system.physmem_1.actEnergy 234896760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 128167875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1571286600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 383486400 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 56258103960 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1067871924000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1248066938235 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.270314 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1776335363750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 62177440000 # Time in different power states
300c303
< system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 23523591750 # Time in different power states
302,308c305,311
< system.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 19569408 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 5420664 # Number of BTB hits
---
> system.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 19539848 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16614646 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 591620 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 12579114 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 5416634 # Number of BTB hits
310,316c313,319
< system.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 42865 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 6372302 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 563108 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 5809194 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 264983 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 43.060537 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1121926 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 41569 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 6087322 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 563395 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 5523927 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 264320 # Number of mispredicted indirect branches.
322,337c325,340
< system.cpu.dtb.read_hits 11131372 # DTB read hits
< system.cpu.dtb.read_misses 49301 # DTB read misses
< system.cpu.dtb.read_acv 623 # DTB read access violations
< system.cpu.dtb.read_accesses 996761 # DTB read accesses
< system.cpu.dtb.write_hits 6776847 # DTB write hits
< system.cpu.dtb.write_misses 12217 # DTB write misses
< system.cpu.dtb.write_acv 418 # DTB write access violations
< system.cpu.dtb.write_accesses 345142 # DTB write accesses
< system.cpu.dtb.data_hits 17908219 # DTB hits
< system.cpu.dtb.data_misses 61518 # DTB misses
< system.cpu.dtb.data_acv 1041 # DTB access violations
< system.cpu.dtb.data_accesses 1341903 # DTB accesses
< system.cpu.itb.fetch_hits 1817383 # ITB hits
< system.cpu.itb.fetch_misses 10321 # ITB misses
< system.cpu.itb.fetch_acv 767 # ITB acv
< system.cpu.itb.fetch_accesses 1827704 # ITB accesses
---
> system.cpu.dtb.read_hits 11126873 # DTB read hits
> system.cpu.dtb.read_misses 49288 # DTB read misses
> system.cpu.dtb.read_acv 612 # DTB read access violations
> system.cpu.dtb.read_accesses 995471 # DTB read accesses
> system.cpu.dtb.write_hits 6773971 # DTB write hits
> system.cpu.dtb.write_misses 12183 # DTB write misses
> system.cpu.dtb.write_acv 423 # DTB write access violations
> system.cpu.dtb.write_accesses 345274 # DTB write accesses
> system.cpu.dtb.data_hits 17900844 # DTB hits
> system.cpu.dtb.data_misses 61471 # DTB misses
> system.cpu.dtb.data_acv 1035 # DTB access violations
> system.cpu.dtb.data_accesses 1340745 # DTB accesses
> system.cpu.itb.fetch_hits 1815480 # ITB hits
> system.cpu.itb.fetch_misses 10441 # ITB misses
> system.cpu.itb.fetch_acv 750 # ITB acv
> system.cpu.itb.fetch_accesses 1825921 # ITB accesses
350,355c353,358
< system.cpu.numPwrStateTransitions 12876 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 6438 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 279467835.818577 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 439243252.658256 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 6438 100.00% 100.00% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::min_value 81000 # Distribution of time spent in the clock gated state
---
> system.cpu.numPwrStateTransitions 12878 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 279534848.967231 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 439378966.267034 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::min_value 96000 # Distribution of time spent in the clock gated state
357,360c360,363
< system.cpu.pwrStateClkGateDist::total 6438 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 77580561000 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 155167561 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 62117170500 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 1799924892500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 124240781 # number of cpu cycles simulated
363,375c366,378
< system.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1681668 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 87 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 29150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 207083 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 421165 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 751 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 9930605 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 406777 # Number of outstanding Icache misses that were squashed
---
> system.cpu.fetch.icacheStallCycles 30188704 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 85612379 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 19539848 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 7101955 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 86725868 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1678156 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 31498 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 207275 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 432547 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 9909625 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 405389 # Number of outstanding Icache misses that were squashed
377,379c380,382
< system.cpu.fetch.rateDist::samples 148422395 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.577690 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.864310 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 118425370 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.722923 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.060283 # Number of instructions fetched each cycle (Total)
381,389c384,392
< system.cpu.fetch.rateDist::0 132578342 89.33% 89.33% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1033201 0.70% 90.02% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 2106811 1.42% 91.44% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 971505 0.65% 92.10% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2908700 1.96% 94.05% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 663530 0.45% 94.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 808471 0.54% 95.05% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1037122 0.70% 95.75% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 6314713 4.25% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 102607090 86.64% 86.64% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1029926 0.87% 87.51% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 2106958 1.78% 89.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 967243 0.82% 90.11% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2899427 2.45% 92.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 665654 0.56% 93.12% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 809857 0.68% 93.80% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1032032 0.87% 94.67% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 6307183 5.33% 100.00% # Number of instructions fetched each cycle (Total)
393,438c396,441
< system.cpu.fetch.rateDist::total 148422395 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.126118 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.552578 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 24118440 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 111208587 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 10245196 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 2044112 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 806059 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 738327 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 35573 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 74062953 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 114064 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 806059 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 25129468 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 79314805 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 20217508 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 11209636 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 11744917 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 71031430 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 202187 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2134257 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 304114 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 7385918 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 47856784 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 85577316 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 85396639 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 168224 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 38182032 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 9674744 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1729903 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 277398 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13945265 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 11667584 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 7222268 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1740236 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1128330 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 62719117 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2208284 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 60532785 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 94680 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 11944453 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 5319004 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1547012 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 148422395 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.407841 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.141989 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 118425370 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.157274 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.689084 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 24239485 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 81100635 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 10246732 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 2034421 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 804096 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 734883 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 35786 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 73972445 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 113808 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 804096 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 25248689 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 52456334 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 19565246 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 11202200 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 9148803 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 70966243 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 196842 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 2117370 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 228092 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 4881037 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 47806174 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 85505184 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 85324382 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 168350 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 38176913 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 9629253 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1728484 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 276268 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13926032 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 11656323 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 7221031 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1724354 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1093863 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 62666856 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2206869 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 60507866 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 96262 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 11897215 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 5284366 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1545682 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 118425370 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.510937 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.257755 # Number of insts issued each cycle
440,448c443,451
< system.cpu.iq.issued_per_cycle::0 123871811 83.46% 83.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 10428219 7.03% 90.49% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 4419616 2.98% 93.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 3188761 2.15% 95.61% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 3243069 2.19% 97.80% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 1605515 1.08% 98.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1096686 0.74% 99.62% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 430660 0.29% 99.91% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 138058 0.09% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 93896241 79.29% 79.29% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 10410761 8.79% 88.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 4424184 3.74% 91.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 3178503 2.68% 94.50% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 3240709 2.74% 97.23% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 1606797 1.36% 98.59% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1097474 0.93% 99.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 434045 0.37% 99.88% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 136656 0.12% 100.00% # Number of insts issued each cycle
452c455
< system.cpu.iq.issued_per_cycle::total 148422395 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 118425370 # Number of insts issued each cycle
454,484c457,487
< system.cpu.iq.fu_full::IntAlu 206261 16.62% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.62% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 637065 51.34% 67.96% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 397617 32.04% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 206587 16.63% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 638209 51.38% 68.02% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 397270 31.98% 100.00% # attempts to use FU when none available
487,489c490,492
< system.cpu.iq.FU_type_0::No_OpClass 7280 0.01% 0.01% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 40910867 67.58% 67.60% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 62087 0.10% 67.70% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 7277 0.01% 0.01% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 40893641 67.58% 67.60% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 62155 0.10% 67.70% # Type of FU issued
491c494
< system.cpu.iq.FU_type_0::FloatAdd 38559 0.06% 67.76% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatAdd 38558 0.06% 67.76% # Type of FU issued
517,519c520,522
< system.cpu.iq.FU_type_0::MemRead 11677582 19.29% 87.06% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 6883616 11.37% 98.43% # Type of FU issued
< system.cpu.iq.FU_type_0::IprAccess 949158 1.57% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 11671611 19.29% 87.06% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 6881999 11.37% 98.43% # Type of FU issued
> system.cpu.iq.FU_type_0::IprAccess 948989 1.57% 100.00% # Type of FU issued
521,533c524,536
< system.cpu.iq.FU_type_0::total 60532785 # Type of FU issued
< system.cpu.iq.rate 0.390112 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1240943 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.020500 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 270086631 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 76534291 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 58304379 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 736956 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 359180 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 336827 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 61370896 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 395552 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 686477 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 60507866 # Type of FU issued
> system.cpu.iq.rate 0.487021 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1242066 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.020527 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 240042364 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 76433076 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 58286910 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 737065 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 359346 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 336745 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 61347086 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 395569 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 690461 # Number of loads that had data forwarded from stores
535,538c538,541
< system.cpu.iew.lsq.thread0.squashedLoads 2574541 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 4210 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 22293 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 843973 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 2564224 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 22069 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 843181 # Number of stores squashed
541,542c544,545
< system.cpu.iew.lsq.thread0.rescheduledLoads 18024 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 466103 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 17987 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 463704 # Number of times an access to memory failed due to the cache being blocked
544,560c547,563
< system.cpu.iew.iewSquashCycles 806059 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 75493298 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1202730 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 68906340 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 204916 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 11667584 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 7222268 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1958885 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 46577 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 953145 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 22293 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 228745 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 630471 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 859216 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 59676170 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 11213777 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 856614 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 804096 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 49123510 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 920451 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 68850753 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 204809 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 11656323 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 7221031 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1958834 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 45972 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 671584 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 22069 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 229357 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 628132 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 857489 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 59656852 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 11208773 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 851013 # Number of squashed instructions skipped in execute
562,578c565,581
< system.cpu.iew.exec_nop 3978939 # number of nop insts executed
< system.cpu.iew.exec_refs 18023142 # number of memory reference insts executed
< system.cpu.iew.exec_branches 9384066 # Number of branches executed
< system.cpu.iew.exec_stores 6809365 # Number of stores executed
< system.cpu.iew.exec_rate 0.384592 # Inst execution rate
< system.cpu.iew.wb_sent 58885265 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 58641206 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 29760600 # num instructions producing a value
< system.cpu.iew.wb_consumers 41260135 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.377922 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.721292 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 12542077 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 661272 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 769434 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 146251910 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.384089 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.283290 # Number of insts commited each cycle
---
> system.cpu.iew.exec_nop 3977028 # number of nop insts executed
> system.cpu.iew.exec_refs 18015122 # number of memory reference insts executed
> system.cpu.iew.exec_branches 9379233 # Number of branches executed
> system.cpu.iew.exec_stores 6806349 # Number of stores executed
> system.cpu.iew.exec_rate 0.480171 # Inst execution rate
> system.cpu.iew.wb_sent 58867691 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 58623655 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 29756177 # num instructions producing a value
> system.cpu.iew.wb_consumers 41250197 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.471855 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.721358 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 12492004 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 661187 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 767634 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 116265516 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.483093 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.421972 # Number of insts commited each cycle
580,588c583,591
< system.cpu.commit.committed_per_cycle::0 126403677 86.43% 86.43% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 7969213 5.45% 91.88% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 4187918 2.86% 94.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2256490 1.54% 96.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1756984 1.20% 97.49% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 633259 0.43% 97.92% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 482491 0.33% 98.25% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 524954 0.36% 98.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 2036924 1.39% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 96403146 82.92% 82.92% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 7978599 6.86% 89.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 4192375 3.61% 93.38% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2264506 1.95% 95.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1757271 1.51% 96.84% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 632678 0.54% 97.39% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 482043 0.41% 97.80% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 513720 0.44% 98.24% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 2041178 1.76% 100.00% # Number of insts commited each cycle
592,594c595,597
< system.cpu.commit.committed_per_cycle::total 146251910 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 56173766 # Number of instructions committed
< system.cpu.commit.committedOps 56173766 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 116265516 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 56167063 # Number of instructions committed
> system.cpu.commit.committedOps 56167063 # Number of ops (including micro ops) committed
596,599c599,602
< system.cpu.commit.refs 15471338 # Number of memory references committed
< system.cpu.commit.loads 9093043 # Number of loads committed
< system.cpu.commit.membars 226379 # Number of memory barriers committed
< system.cpu.commit.branches 8441154 # Number of branches committed
---
> system.cpu.commit.refs 15469949 # Number of memory references committed
> system.cpu.commit.loads 9092099 # Number of loads committed
> system.cpu.commit.membars 226348 # Number of memory barriers committed
> system.cpu.commit.branches 8440307 # Number of branches committed
601,605c604,608
< system.cpu.commit.int_insts 52023017 # Number of committed integer instructions.
< system.cpu.commit.function_calls 740601 # Number of function calls committed.
< system.cpu.commit.op_class_0::No_OpClass 3198096 5.69% 5.69% # Class of committed instruction
< system.cpu.commit.op_class_0::IntAlu 36220454 64.48% 70.17% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.28% # Class of committed instruction
---
> system.cpu.commit.int_insts 52016709 # Number of committed integer instructions.
> system.cpu.commit.function_calls 740521 # Number of function calls committed.
> system.cpu.commit.op_class_0::No_OpClass 3197831 5.69% 5.69% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 36215597 64.48% 70.17% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 60674 0.11% 70.28% # Class of committed instruction
633,635c636,638
< system.cpu.commit.op_class_0::MemRead 9319422 16.59% 86.95% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 6384252 11.37% 98.31% # Class of committed instruction
< system.cpu.commit.op_class_0::IprAccess 949158 1.69% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 9318447 16.59% 86.94% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 6383804 11.37% 98.31% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 948989 1.69% 100.00% # Class of committed instruction
637,665c640,668
< system.cpu.commit.op_class_0::total 56173766 # Class of committed instruction
< system.cpu.commit.bw_lim_events 2036924 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 212681294 # The number of ROB reads
< system.cpu.rob.rob_writes 139606986 # The number of ROB writes
< system.cpu.timesIdled 557347 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 6745166 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 3598421416 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 52982943 # Number of Instructions Simulated
< system.cpu.committedOps 52982943 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 2.928632 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.928632 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.341456 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 77864960 # number of integer regfile reads
< system.cpu.int_regfile_writes 42584488 # number of integer regfile writes
< system.cpu.fp_regfile_reads 166613 # number of floating regfile reads
< system.cpu.fp_regfile_writes 175794 # number of floating regfile writes
< system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads
< system.cpu.misc_regfile_writes 939529 # number of misc regfile writes
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 1405900 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy
---
> system.cpu.commit.op_class_0::total 56167063 # Class of committed instruction
> system.cpu.commit.bw_lim_events 2041178 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 182633884 # The number of ROB reads
> system.cpu.rob.rob_writes 139481914 # The number of ROB writes
> system.cpu.timesIdled 555871 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 5815411 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 3599843346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 52976505 # Number of Instructions Simulated
> system.cpu.committedOps 52976505 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 2.345205 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.345205 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.426402 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.426402 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 77842014 # number of integer regfile reads
> system.cpu.int_regfile_writes 42572961 # number of integer regfile writes
> system.cpu.fp_regfile_reads 166584 # number of floating regfile reads
> system.cpu.fp_regfile_writes 175742 # number of floating regfile writes
> system.cpu.misc_regfile_reads 2001057 # number of misc regfile reads
> system.cpu.misc_regfile_writes 939419 # number of misc regfile writes
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 1405448 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.994324 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 12624146 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1405960 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 8.979022 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 26885500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.994324 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
667,669c670,672
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
671,775c674,778
< system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4181578 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 212474 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 212474 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 215675 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 215675 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 12199345 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 12199345 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 12199345 # number of overall hits
< system.cpu.dcache.overall_hits::total 12199345 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1817411 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1817411 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1966241 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1966241 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 23192 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 23192 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 96 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 96 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 3783652 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3783652 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3783652 # number of overall misses
< system.cpu.dcache.overall_misses::total 3783652 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 57696836500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 57696836500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 116764719993 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 116764719993 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 411714000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 411714000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1875000 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 1875000 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 174461556493 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 174461556493 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 174461556493 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 174461556493 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9835178 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9835178 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6147819 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6147819 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235666 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 235666 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 215771 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 215771 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15982997 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15982997 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15982997 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15982997 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184787 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.184787 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319827 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.319827 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098410 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098410 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000445 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000445 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.236730 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.236730 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.236730 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.236730 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31746.719097 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 31746.719097 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59384.744796 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 59384.744796 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17752.414626 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17752.414626 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19531.250000 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19531.250000 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 46109.302994 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 46109.302994 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 7149027 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 5119 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 133846 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 843569 # number of writebacks
< system.cpu.dcache.writebacks::total 843569 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 717041 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676919 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1676919 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6351 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 6351 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2393960 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2393960 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2393960 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2393960 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100370 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1100370 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289322 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 289322 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16841 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 16841 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 96 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 96 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1389692 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1389692 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1389692 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1389692 # number of overall MSHR misses
---
> system.cpu.dcache.tags.tag_accesses 67117469 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 67117469 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 8015814 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 8015814 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4179783 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4179783 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 212605 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 212605 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 215671 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 215671 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 12195597 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 12195597 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 12195597 # number of overall hits
> system.cpu.dcache.overall_hits::total 12195597 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1813103 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1813103 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1967603 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1967603 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 23208 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 23208 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 90 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 90 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 3780706 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3780706 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3780706 # number of overall misses
> system.cpu.dcache.overall_misses::total 3780706 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 42125006500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 42125006500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 80961387023 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 80961387023 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 351774000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 351774000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1258000 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 1258000 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 123086393523 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 123086393523 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 123086393523 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 123086393523 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9828917 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9828917 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6147386 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6147386 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235813 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 235813 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 215761 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 215761 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15976303 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15976303 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15976303 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15976303 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184466 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.184466 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320071 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.320071 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098417 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098417 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000417 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000417 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.236645 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.236645 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.236645 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.236645 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23233.653300 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 23233.653300 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41147.216701 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41147.216701 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15157.445708 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15157.445708 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13977.777778 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13977.777778 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 32556.457319 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 32556.457319 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 4549830 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 3359 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 133574 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.062243 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 93.305556 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 843871 # number of writebacks
> system.cpu.dcache.writebacks::total 843871 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 713283 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 713283 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1678038 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1678038 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6508 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 6508 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2391321 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2391321 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2391321 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2391321 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1099820 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1099820 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289565 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 289565 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16700 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 16700 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 90 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 90 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1389385 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1389385 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1389385 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1389385 # number of overall MSHR misses
778,835c781,838
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44732838000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 44732838000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18336828964 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 18336828964 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214607500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214607500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1779000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1779000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63069666964 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 63069666964 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63069666964 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 63069666964 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528639000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528639000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528639000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528639000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111881 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111881 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047061 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047061 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071461 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071461 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000445 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000445 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.086948 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.086948 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.542327 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.542327 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63378.619545 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63378.619545 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12743.156582 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12743.156582 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1074186 # number of replacements
< system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy
---
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30901101000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 30901101000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12647974805 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12647974805 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 208768500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 208768500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1168000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1168000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43549075805 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 43549075805 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43549075805 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 43549075805 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535163500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535163500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535163500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535163500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111896 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111896 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047104 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047104 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.070819 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.070819 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000417 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000417 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.086965 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.086965 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28096.507610 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28096.507610 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43679.225062 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43679.225062 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12501.107784 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12501.107784 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12977.777778 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12977.777778 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31344.138453 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31344.138453 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31344.138453 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31344.138453 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221524.314574 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221524.314574 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92882.593175 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92882.593175 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1075014 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.176961 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 8765751 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1075522 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 8.150229 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 28399256500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.176961 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.994486 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.994486 # Average percentage of cache occupancy
838,839c841,842
< system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id
841,880c844,883
< system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits
< system.cpu.icache.overall_hits::total 8786985 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1143615 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1143615 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1143615 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1143615 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1143615 # number of overall misses
< system.cpu.icache.overall_misses::total 1143615 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 17001547978 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 17001547978 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 17001547978 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 17001547978 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 17001547978 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 17001547978 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 9930600 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 9930600 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 9930600 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 9930600 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 9930600 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 9930600 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115161 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.115161 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.115161 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.115161 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.115161 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.115161 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14866.496136 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14866.496136 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14866.496136 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14866.496136 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 12933 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 10985459 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 10985459 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 8765751 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 8765751 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 8765751 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 8765751 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 8765751 # number of overall hits
> system.cpu.icache.overall_hits::total 8765751 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1143868 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1143868 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1143868 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1143868 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1143868 # number of overall misses
> system.cpu.icache.overall_misses::total 1143868 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15979138992 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15979138992 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15979138992 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15979138992 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15979138992 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15979138992 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 9909619 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 9909619 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 9909619 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 9909619 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 9909619 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 9909619 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115430 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.115430 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.115430 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.115430 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.115430 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.115430 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13969.390692 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13969.390692 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13969.390692 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13969.390692 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13969.390692 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13969.390692 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 7656 # number of cycles access was blocked
882c885
< system.cpu.icache.blocked::no_mshrs 342 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 228 # number of cycles access was blocked
884c887
< system.cpu.icache.avg_blocked_cycles::no_mshrs 37.815789 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 33.578947 # average number of cycles each access was blocked
886,1045c889,1040
< system.cpu.icache.writebacks::writebacks 1074186 # number of writebacks
< system.cpu.icache.writebacks::total 1074186 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68615 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 68615 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 68615 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 68615 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 68615 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 68615 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075000 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1075000 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1075000 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1075000 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1075000 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1075000 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14900351984 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 14900351984 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14900351984 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 14900351984 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14900351984 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 14900351984 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108251 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.108251 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108251 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.108251 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 338591 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 403759 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 10.534943 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 9186566000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5255.268427 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7006.243291 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.809083 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080189 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.106907 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996179 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3471 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3347 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2431 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55427 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1073682 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 88 # number of SCUpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::total 88 # number of SCUpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 185036 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 185036 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1059597 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1059597 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 832111 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 832111 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 1059597 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1017147 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2076744 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 1059597 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1017147 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2076744 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 45 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 45 # number of UpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 8 # number of SCUpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 114791 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 114791 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15028 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 15028 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274518 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 274518 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 15028 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 389309 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 404337 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 15028 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 389309 # number of overall misses
< system.cpu.l2cache.overall_misses::total 404337 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 866000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 866000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 547500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 547500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16017370500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 16017370500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2025075000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2025075000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34108164000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 34108164000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2025075000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 50125534500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 52150609500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2025075000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 50125534500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 52150609500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 843569 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 843569 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1073682 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1073682 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 80 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 96 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 96 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 299827 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 299827 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1074625 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1074625 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106629 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1106629 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1074625 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1406456 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2481081 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1074625 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1406456 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2481081 # number of overall (read+write) accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.562500 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.562500 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.083333 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.083333 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382857 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.382857 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013984 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013984 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248067 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248067 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013984 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.276801 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.162968 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013984 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.276801 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.162968 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19244.444444 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19244.444444 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 68437.500000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 68437.500000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139535.072436 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139535.072436 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134753.460208 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134753.460208 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124247.459183 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124247.459183 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134753.460208 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128755.139234 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 128978.078929 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134753.460208 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128755.139234 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 128978.078929 # average overall miss latency
---
> system.cpu.icache.writebacks::writebacks 1075014 # number of writebacks
> system.cpu.icache.writebacks::total 1075014 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68028 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 68028 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 68028 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 68028 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 68028 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 68028 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075840 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1075840 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1075840 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1075840 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1075840 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1075840 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14160831996 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14160831996 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14160831996 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14160831996 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14160831996 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14160831996 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108565 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108565 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108565 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.108565 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108565 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.108565 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13162.581793 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13162.581793 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13162.581793 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13162.581793 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13162.581793 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13162.581793 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 338638 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65427.252545 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4555596 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 404160 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 11.271764 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 5985561000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 253.752588 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5311.170770 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 59862.329187 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.003872 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081042 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.913427 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.998341 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 449 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5579 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58592 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 40086542 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 40086542 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 843871 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 843871 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1074552 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1074552 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 90 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 90 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 185367 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 185367 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1060413 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1060413 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 831413 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 831413 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 1060413 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1016780 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2077193 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 1060413 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1016780 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2077193 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 114699 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 114699 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15055 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 15055 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274527 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 274527 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 15055 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 389226 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 404281 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 15055 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 389226 # number of overall misses
> system.cpu.l2cache.overall_misses::total 404281 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 387500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 387500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10326275500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10326275500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1274090500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 1274090500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 20279625500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 20279625500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1274090500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 30605901000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31879991500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1274090500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 30605901000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31879991500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 843871 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 843871 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1074552 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1074552 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 82 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 90 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 90 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 300066 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 300066 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1075468 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1075468 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1105940 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1105940 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1075468 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1406006 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2481474 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1075468 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1406006 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2481474 # number of overall (read+write) accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.097561 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.097561 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382246 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.382246 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013999 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013999 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248230 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248230 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013999 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.276831 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.162920 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013999 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.276831 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.162920 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48437.500000 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48437.500000 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90029.342017 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90029.342017 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84629.060113 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84629.060113 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73871.151107 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73871.151107 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84629.060113 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78632.724946 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78856.022173 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84629.060113 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78632.724946 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78856.022173 # average overall miss latency
1052,1069c1047,1068
< system.cpu.l2cache.writebacks::writebacks 76108 # number of writebacks
< system.cpu.l2cache.writebacks::total 76108 # number of writebacks
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 45 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 45 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114791 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 114791 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15028 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15028 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274518 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274518 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 15028 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 389309 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 404337 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 15028 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 389309 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 404337 # number of overall MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 76126 # number of writebacks
> system.cpu.l2cache.writebacks::total 76126 # number of writebacks
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114699 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 114699 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15054 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15054 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274527 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274527 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 15054 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 389226 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 404280 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 15054 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 389226 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 404280 # number of overall MSHR misses
1072,1136c1071,1129
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3100000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3100000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 546000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 546000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14869460001 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14869460001 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1874795000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1874795000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31368563001 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31368563001 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1874795000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46238023002 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 48112818002 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1874795000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46238023002 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 48112818002 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442000500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442000500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1442000500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1442000500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.562500 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.562500 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.083333 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382857 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382857 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013984 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248067 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248067 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276801 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.162968 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013984 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276801 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.162968 # mshr miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68888.888889 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68888.888889 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129535.068089 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129535.068089 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124753.460208 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124753.460208 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114267.782080 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114267.782080 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124753.460208 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 307500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 307500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9179285500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9179285500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1123478500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1123478500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17540240000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17540240000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1123478500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26719525500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 27843004000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1123478500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26719525500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 27843004000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448524000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448524000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448524000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448524000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097561 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097561 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382246 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382246 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013998 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248230 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248230 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.162919 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.162919 # mshr miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 38437.500000 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 38437.500000 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80029.342017 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80029.342017 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74629.899030 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74629.899030 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63892.586157 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63892.586157 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209022.222222 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209022.222222 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87640.609874 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87640.609874 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 4962480 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480820 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 950 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1138c1131
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
1140,1165c1133,1158
< system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 96 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 299827 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 299827 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075000 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106802 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::BadAddressError 43 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3223811 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252378 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7476189 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137523904 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144052988 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 281576892 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 422541 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 7562240 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 2920171 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.001264 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.035530 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2188821 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 919997 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1075014 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 824089 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 90 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 172 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 300066 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 300066 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075840 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106100 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 254 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3226322 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4251016 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7477338 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137630848 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144043380 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 281674228 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 339580 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 4905856 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 2837598 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.001208 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.034736 # Request fanout histogram
1167,1168c1160,1161
< system.cpu.toL2Bus.snoop_fanout::0 2916480 99.87% 99.87% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 3691 0.13% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2834170 99.88% 99.88% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3428 0.12% 100.00% # Request fanout histogram
1173,1174c1166,1167
< system.cpu.toL2Bus.snoop_fanout::total 2920171 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4411678000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2837598 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4413188000 # Layer occupancy (ticks)
1178c1171
< system.cpu.toL2Bus.respLayer0.occupancy 1613546403 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1614811393 # Layer occupancy (ticks)
1180c1173
< system.cpu.toL2Bus.respLayer1.occupancy 2121618679 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2121037981 # Layer occupancy (ticks)
1194c1187
< system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
1197,1199c1190,1192
< system.iobus.trans_dist::WriteReq 51151 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51151 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 51150 # Transaction distribution
> system.iobus.trans_dist::WriteResp 51150 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
1208c1201
< system.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
1211,1212c1204,1205
< system.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
1221c1214
< system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
1224,1225c1217,1218
< system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 5364000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 5361000 # Layer occupancy (ticks)
1227c1220
< system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks)
1233c1226
< system.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks)
1235c1228
< system.iobus.reqLayer23.occupancy 14181000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 14040000 # Layer occupancy (ticks)
1237c1230
< system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 2177500 # Layer occupancy (ticks)
1239c1232
< system.iobus.reqLayer25.occupancy 6052000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 6050500 # Layer occupancy (ticks)
1243c1236
< system.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 216173801 # Layer occupancy (ticks)
1245c1238
< system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks)
1249c1242
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
1251c1244
< system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.258860 # Cycle average of tags in use
1255,1258c1248,1251
< system.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1712294555000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.258860 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.078679 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.078679 # Average percentage of cache occupancy
1264c1257
< system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
1273,1280c1266,1273
< system.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 5268272163 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 5268272163 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 5268272163 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 5268272163 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21845883 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21845883 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858784918 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4858784918 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 4880630801 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4880630801 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 4880630801 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4880630801 # number of overall miss cycles
1297,1305c1290,1298
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 126261.765440 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 126261.765440 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126276.780347 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 126276.780347 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116932.636648 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 116932.636648 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 116971.379293 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 116971.379293 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 8 # number of cycles access was blocked
1309c1302
< system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked
1321,1328c1314,1321
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 3180227354 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 3180227354 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 3180227354 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 3180227354 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13195883 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 13195883 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778792164 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2778792164 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 2791988047 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2791988047 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 2791988047 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2791988047 # number of overall MSHR miss cycles
1337,1345c1330,1344
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
< system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76276.780347 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 76276.780347 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66875.052079 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66875.052079 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 825555 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 380464 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
1347,1353c1346,1351
< system.membus.trans_dist::ReadResp 296606 # Transaction distribution
< system.membus.trans_dist::WriteReq 9599 # Transaction distribution
< system.membus.trans_dist::WriteResp 9599 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution
< system.membus.trans_dist::CleanEvict 261864 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 278 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 296639 # Transaction distribution
> system.membus.trans_dist::WriteReq 9598 # Transaction distribution
> system.membus.trans_dist::WriteResp 9598 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 117638 # Transaction distribution
> system.membus.trans_dist::CleanEvict 261892 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 135 # Transaction distribution
1355,1358c1353,1356
< system.membus.trans_dist::ReadExReq 114558 # Transaction distribution
< system.membus.trans_dist::ReadExResp 114558 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 289719 # Transaction distribution
< system.membus.trans_dist::BadAddressError 43 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 114572 # Transaction distribution
> system.membus.trans_dist::ReadExResp 114572 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 289754 # Transaction distribution
> system.membus.trans_dist::BadAddressError 45 # Transaction distribution
1360,1363c1358,1361
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145930 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 86 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179074 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145919 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179065 # Packet count per connected master and slave (bytes)
1366,1369c1364,1367
< system.membus.pkt_count::total 1262499 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30713088 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757244 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1262490 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30717248 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30761396 # Cumulative packet size per connected master and slave (bytes)
1372c1370
< system.membus.pkt_size::total 33414972 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 33419124 # Cumulative packet size per connected master and slave (bytes)
1375,1377c1373,1375
< system.membus.snoop_fanout::samples 842137 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 462541 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.001500 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.038706 # Request fanout histogram
1379,1380c1377,1378
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 842137 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 461847 99.85% 99.85% # Request fanout histogram
> system.membus.snoop_fanout::1 694 0.15% 100.00% # Request fanout histogram
1383c1381
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1385,1386c1383,1384
< system.membus.snoop_fanout::total 842137 # Request fanout histogram
< system.membus.reqLayer0.occupancy 28883000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 462541 # Request fanout histogram
> system.membus.reqLayer0.occupancy 28740000 # Layer occupancy (ticks)
1388c1386
< system.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1314155780 # Layer occupancy (ticks)
1390c1388
< system.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 57000 # Layer occupancy (ticks)
1392c1390
< system.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2139053000 # Layer occupancy (ticks)
1396,1400c1394,1398
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
1432,1454c1430,1452
< system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
< system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states
---
> system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
> system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states
1456,1458c1454,1456
< system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 210996 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74658 40.97% 40.97% # number of times we switched to this ipl
1460,1463c1458,1461
< system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 105584 57.93% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182266 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 105558 57.93% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182227 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73291 49.32% 49.32% # number of times we switched to this ipl from a different ipl
1465,1473c1463,1471
< system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1818987792000 96.92% 96.92% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 67503500 0.00% 96.92% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 563118000 0.03% 96.95% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 57175249500 3.05% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1876793663000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73291 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148593 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1818067214500 97.64% 97.64% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 67498000 0.00% 97.64% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 564111500 0.03% 97.67% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 43342412500 2.33% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1862041236500 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981690 # fraction of swpipl calls that actually changed the ipl
1476,1477c1474,1475
< system.cpu.kern.ipl_used::31 0.694262 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.815391 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.694320 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.815428 # fraction of swpipl calls that actually changed the ipl
1516,1517c1514,1515
< system.cpu.kern.callpal::swpipl 175147 91.23% 93.43% # number of callpals executed
< system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175110 91.22% 93.43% # number of callpals executed
> system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
1522c1520
< system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
1525,1530c1523,1528
< system.cpu.kern.callpal::total 191994 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5854 # number of protection mode switches
< system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
< system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1910
< system.cpu.kern.mode_good::user 1740
---
> system.cpu.kern.callpal::total 191955 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches
> system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
> system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1909
> system.cpu.kern.mode_good::user 1739
1532c1530
< system.cpu.kern.mode_switch_good::kernel 0.326273 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches
1534,1538c1532,1536
< system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 30164955000 1.61% 1.61% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 2918722500 0.16% 1.76% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1843709977500 98.24% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 29461996000 1.58% 1.58% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 2701361000 0.15% 1.73% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1829877871500 98.27% 100.00% # number of ticks spent at the given mode