7,9c7,9
< host_inst_rate 164316 # Simulator instruction rate (inst/s)
< host_op_rate 164316 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5820514836 # Simulator tick rate (ticks/s)
---
> host_inst_rate 142986 # Simulator instruction rate (inst/s)
> host_op_rate 142986 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5064945596 # Simulator tick rate (ticks/s)
11c11
< host_seconds 322.44 # Real time elapsed on the host
---
> host_seconds 370.55 # Real time elapsed on the host
737,738d736
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
783,786c781,782
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154562000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154562000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683201000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683201000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528639000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528639000 # number of overall MSHR uncacheable cycles
813,817c809,810
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency
876,877d868
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
910d900
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1043,1044d1032
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1087,1090c1075,1076
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2044145000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2044145000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486145500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486145500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1442000500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1442000500 # number of overall MSHR uncacheable cycles
1125,1129c1111,1112
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency
1262,1265c1245,1248
< system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
< system.iocache.demand_misses::total 173 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
< system.iocache.overall_misses::total 173 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
> system.iocache.overall_misses::total 41725 # number of overall misses
1270,1273c1253,1256
< system.iocache.demand_miss_latency::tsunami.ide 21828883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21828883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21828883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21828883 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5268272163 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5268272163 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5268272163 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5268272163 # number of overall miss cycles
1278,1281c1261,1264
< system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
1294,1297c1277,1280
< system.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 126178.514451 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 126178.514451 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126261.765440 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126261.765440 # average overall miss latency
1304,1305d1286
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1312,1315c1293,1296
< system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
1320,1323c1301,1304
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13178883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13178883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13178883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13178883 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3180227354 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3180227354 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3180227354 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3180227354 # number of overall MSHR miss cycles
1336,1340c1317,1320
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
< host_inst_rate 164316 # Simulator instruction rate (inst/s)
< host_op_rate 164316 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5820514836 # Simulator tick rate (ticks/s)
---
> host_inst_rate 142986 # Simulator instruction rate (inst/s)
> host_op_rate 142986 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5064945596 # Simulator tick rate (ticks/s)
11c11
< host_seconds 322.44 # Real time elapsed on the host
---
> host_seconds 370.55 # Real time elapsed on the host
737,738d736
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
783,786c781,782
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154562000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154562000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683201000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683201000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528639000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528639000 # number of overall MSHR uncacheable cycles
813,817c809,810
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency
876,877d868
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
910d900
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1043,1044d1032
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1087,1090c1075,1076
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2044145000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2044145000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486145500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486145500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1442000500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1442000500 # number of overall MSHR uncacheable cycles
1125,1129c1111,1112
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency
1262,1265c1245,1248
< system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
< system.iocache.demand_misses::total 173 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
< system.iocache.overall_misses::total 173 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
> system.iocache.overall_misses::total 41725 # number of overall misses
1270,1273c1253,1256
< system.iocache.demand_miss_latency::tsunami.ide 21828883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21828883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21828883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21828883 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5268272163 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5268272163 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5268272163 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5268272163 # number of overall miss cycles
1278,1281c1261,1264
< system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
1294,1297c1277,1280
< system.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 126178.514451 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 126178.514451 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126261.765440 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126261.765440 # average overall miss latency
1304,1305d1286
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1312,1315c1293,1296
< system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
1320,1323c1301,1304
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13178883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13178883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13178883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13178883 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3180227354 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3180227354 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3180227354 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3180227354 # number of overall MSHR miss cycles
1336,1340c1317,1320
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency