3,5c3,5
< sim_seconds 1.860990 # Number of seconds simulated
< sim_ticks 1860990273000 # Number of ticks simulated
< final_tick 1860990273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.875745 # Number of seconds simulated
> sim_ticks 1875745192000 # Number of ticks simulated
> final_tick 1875745192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 102674 # Simulator instruction rate (inst/s)
< host_op_rate 102674 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 3606509618 # Simulator tick rate (ticks/s)
< host_mem_usage 370916 # Number of bytes of host memory used
< host_seconds 516.01 # Real time elapsed on the host
< sim_insts 52980740 # Number of instructions simulated
< sim_ops 52980740 # Number of ops (including micro ops) simulated
---
> host_inst_rate 131976 # Simulator instruction rate (inst/s)
> host_op_rate 131976 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4672432142 # Simulator tick rate (ticks/s)
> host_mem_usage 378172 # Number of bytes of host memory used
> host_seconds 401.45 # Real time elapsed on the host
> sim_insts 52981683 # Number of instructions simulated
> sim_ops 52981683 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.bytes_read::cpu.inst 964096 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 962112 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24881536 # Number of bytes read from this memory
19,25c19,25
< system.physmem.bytes_read::total 25845056 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 964096 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 964096 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7523456 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7523456 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 15064 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25844608 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 962112 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 962112 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7523648 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7523648 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 15033 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388774 # Number of read requests responded to by this memory
27,52c27,52
< system.physmem.num_reads::total 403829 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 117554 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 117554 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 518055 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13369226 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 13887797 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 518055 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 518055 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4042716 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4042716 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4042716 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 518055 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13369226 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17930514 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 403829 # Number of read requests accepted
< system.physmem.writeReqs 117554 # Number of write requests accepted
< system.physmem.readBursts 403829 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 117554 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25837696 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7522048 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25845056 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7523456 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::total 403822 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 117557 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 117557 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 512923 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 13264881 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 13778315 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 512923 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 512923 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4011018 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4011018 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4011018 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 512923 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 13264881 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17789333 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 403822 # Number of read requests accepted
> system.physmem.writeReqs 117557 # Number of write requests accepted
> system.physmem.readBursts 403822 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 117557 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25836864 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7522176 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25844608 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7523648 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue
55,71c55,71
< system.physmem.perBankRdBursts::0 25640 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25420 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25567 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25490 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25392 # Per bank write bursts
< system.physmem.perBankRdBursts::5 24736 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24946 # Per bank write bursts
< system.physmem.perBankRdBursts::7 25069 # Per bank write bursts
< system.physmem.perBankRdBursts::8 24934 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25024 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25571 # Per bank write bursts
< system.physmem.perBankRdBursts::11 24874 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24488 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25240 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25741 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25582 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7942 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 25633 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25421 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25565 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25492 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25387 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24737 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24937 # Per bank write bursts
> system.physmem.perBankRdBursts::7 25080 # Per bank write bursts
> system.physmem.perBankRdBursts::8 24933 # Per bank write bursts
> system.physmem.perBankRdBursts::9 25019 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25561 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24878 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24487 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25242 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25745 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25584 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7946 # Per bank write bursts
73,82c73,82
< system.physmem.perBankWrBursts::2 7958 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7515 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7335 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6671 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6772 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6705 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7147 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6708 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7414 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6974 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 7960 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7517 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7330 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6676 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6762 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6719 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7146 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6702 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7407 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6970 # Per bank write bursts
84,85c84,85
< system.physmem.perBankWrBursts::13 7857 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8057 # Per bank write bursts
---
> system.physmem.perBankWrBursts::13 7861 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8061 # Per bank write bursts
88,89c88,89
< system.physmem.numWrRetry 22 # Number of times write queue was full causing retry
< system.physmem.totGap 1860985018500 # Total gap between requests
---
> system.physmem.numWrRetry 19 # Number of times write queue was full causing retry
> system.physmem.totGap 1875739913500 # Total gap between requests
96c96
< system.physmem.readPktSize::6 403829 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 403822 # Read request sizes (log2)
103,109c103,109
< system.physmem.writePktSize::6 117554 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 314954 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 36116 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 28406 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 117557 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 315399 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 36013 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 28212 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 23984 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 76 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see
151,217c151,217
< system.physmem.wrQLenPdf::15 1546 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1892 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 3644 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4720 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5263 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7047 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9676 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8910 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 7716 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8590 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6996 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7044 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8436 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5726 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 321 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 182 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 150 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 61694 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 540.722923 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 331.893410 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 417.338201 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 13637 22.10% 22.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 10472 16.97% 39.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4852 7.86% 46.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3164 5.13% 52.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2278 3.69% 55.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1550 2.51% 58.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1469 2.38% 60.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1300 2.11% 62.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22972 37.24% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 61694 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5210 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 77.486564 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2926.418549 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5207 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1634 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1915 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 3287 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4150 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5413 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6026 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6352 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9376 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8640 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8795 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7819 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6510 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6491 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5735 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 222 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 259 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 115 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 110 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 62141 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 536.822002 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 331.292900 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 411.615573 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 13686 22.02% 22.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 10474 16.86% 38.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4974 8.00% 46.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2759 4.44% 51.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2428 3.91% 55.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1656 2.66% 57.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3743 6.02% 63.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1149 1.85% 65.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 21272 34.23% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 62141 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5219 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 77.350259 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2906.647984 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5216 99.94% 99.94% # Reads before turning the bus around for writes
221,270c221,265
< system.physmem.rdPerTurnAround::total 5210 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5210 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.558925 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.942347 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 23.343325 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4470 85.80% 85.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 144 2.76% 88.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 197 3.78% 92.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 15 0.29% 92.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 22 0.42% 93.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 47 0.90% 93.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 16 0.31% 94.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 1 0.02% 94.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 3 0.06% 94.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 6 0.12% 94.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 5 0.10% 94.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 2 0.04% 94.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 4 0.08% 94.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 2 0.04% 94.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 3 0.06% 94.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 10 0.19% 94.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 6 0.12% 95.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 10 0.19% 95.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 18 0.35% 95.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 17 0.33% 95.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 156 2.99% 98.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 8 0.15% 99.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.04% 99.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.02% 99.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 7 0.13% 99.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.02% 99.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.02% 99.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 3 0.06% 99.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 1 0.02% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 3 0.06% 99.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 3 0.06% 99.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 1 0.02% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 3 0.06% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 1 0.02% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::196-199 2 0.04% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-203 2 0.04% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-219 1 0.02% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::220-223 4 0.08% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 1 0.02% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::228-231 11 0.21% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5210 # Writes before turning the bus around for reads
< system.physmem.totQLat 3803541750 # Total ticks spent queuing
< system.physmem.totMemAccLat 11373179250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2018570000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9421.38 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5219 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5219 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.520406 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 19.103659 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 21.296995 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 4441 85.09% 85.09% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 172 3.30% 88.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 18 0.34% 88.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 180 3.45% 92.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 4 0.08% 92.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 21 0.40% 92.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 36 0.69% 93.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 2 0.04% 93.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 12 0.23% 93.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 25 0.48% 94.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 3 0.06% 94.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 4 0.08% 94.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 11 0.21% 94.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 4 0.08% 94.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 20 0.38% 94.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 29 0.56% 95.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 1 0.02% 95.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 29 0.56% 96.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 164 3.14% 99.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.02% 99.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.02% 99.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.02% 99.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 5 0.10% 99.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 3 0.06% 99.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 6 0.11% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 4 0.08% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 1 0.02% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-171 4 0.08% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 1 0.02% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 11 0.21% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::196-199 1 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5219 # Writes before turning the bus around for reads
> system.physmem.totQLat 4201414500 # Total ticks spent queuing
> system.physmem.totMemAccLat 11770808250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2018505000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10407.24 # Average queueing delay per DRAM burst
272,276c267,271
< system.physmem.avgMemAccLat 28171.38 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 29157.24 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s
281,299c276,294
< system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing
< system.physmem.readRowHits 364213 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95338 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 90.22 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes
< system.physmem.avgGap 3569324.31 # Average gap between requests
< system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 231343560 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 126229125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1577628000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 378516240 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 56189479095 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1067301426750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1247355039810 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.266370 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1775383293000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 62142340000 # Time in different power states
---
> system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing
> system.physmem.readRowHits 363834 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95259 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 81.03 # Row buffer hit rate for writes
> system.physmem.avgGap 3597651.45 # Average gap between requests
> system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 233286480 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 127289250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1577565600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 378594000 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 61659983700 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1071355704750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1257846562020 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.587193 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1782093997750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 62635040000 # Time in different power states
301c296
< system.physmem_0.memoryStateTime::ACT 23458453250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 31009992250 # Time in different power states
303,313c298,308
< system.physmem_1.actEnergy 235063080 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 128258625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1571294400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 383091120 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 55921872645 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1067536177500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1247326174410 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.250855 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1775778508500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 62142340000 # Time in different power states
---
> system.physmem_1.actEnergy 236499480 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 129042375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1571255400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 383026320 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 61488464715 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1071506168250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1257828594780 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.577609 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1782344410500 # Time in different power states
> system.physmem_1.memoryStateTime::REF 62635040000 # Time in different power states
315c310
< system.physmem_1.memoryStateTime::ACT 23063881500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30760024500 # Time in different power states
317,321c312,316
< system.cpu.branchPred.lookups 17952495 # Number of BP lookups
< system.cpu.branchPred.condPredicted 15650737 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 369298 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 11540660 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 5852648 # Number of BTB hits
---
> system.cpu.branchPred.lookups 17977610 # Number of BP lookups
> system.cpu.branchPred.condPredicted 15676073 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 370677 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 11479744 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 5859077 # Number of BTB hits
323,325c318,320
< system.cpu.branchPred.BTBHitPct 50.713287 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 911814 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 21176 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 51.038394 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 912903 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 21206 # Number of incorrect RAS predictions.
331,344c326,339
< system.cpu.dtb.read_hits 10266725 # DTB read hits
< system.cpu.dtb.read_misses 41420 # DTB read misses
< system.cpu.dtb.read_acv 529 # DTB read access violations
< system.cpu.dtb.read_accesses 965767 # DTB read accesses
< system.cpu.dtb.write_hits 6642195 # DTB write hits
< system.cpu.dtb.write_misses 9809 # DTB write misses
< system.cpu.dtb.write_acv 405 # DTB write access violations
< system.cpu.dtb.write_accesses 342270 # DTB write accesses
< system.cpu.dtb.data_hits 16908920 # DTB hits
< system.cpu.dtb.data_misses 51229 # DTB misses
< system.cpu.dtb.data_acv 934 # DTB access violations
< system.cpu.dtb.data_accesses 1308037 # DTB accesses
< system.cpu.itb.fetch_hits 1768997 # ITB hits
< system.cpu.itb.fetch_misses 27603 # ITB misses
---
> system.cpu.dtb.read_hits 10250294 # DTB read hits
> system.cpu.dtb.read_misses 41452 # DTB read misses
> system.cpu.dtb.read_acv 531 # DTB read access violations
> system.cpu.dtb.read_accesses 965916 # DTB read accesses
> system.cpu.dtb.write_hits 6642949 # DTB write hits
> system.cpu.dtb.write_misses 9723 # DTB write misses
> system.cpu.dtb.write_acv 398 # DTB write access violations
> system.cpu.dtb.write_accesses 342082 # DTB write accesses
> system.cpu.dtb.data_hits 16893243 # DTB hits
> system.cpu.dtb.data_misses 51175 # DTB misses
> system.cpu.dtb.data_acv 929 # DTB access violations
> system.cpu.dtb.data_accesses 1307998 # DTB accesses
> system.cpu.itb.fetch_hits 1771116 # ITB hits
> system.cpu.itb.fetch_misses 27251 # ITB misses
346c341
< system.cpu.itb.fetch_accesses 1796600 # ITB accesses
---
> system.cpu.itb.fetch_accesses 1798367 # ITB accesses
359c354
< system.cpu.numCycles 122250725 # number of cpu cycles simulated
---
> system.cpu.numCycles 153807945 # number of cpu cycles simulated
362,378c357,373
< system.cpu.fetch.icacheStallCycles 29590872 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 78035312 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 17952495 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 6764462 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 84736015 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1230846 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 3604 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 27977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 1246103 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 463506 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 270 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 8988072 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 271207 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 116683770 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.668776 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.983888 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 29589963 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 78082078 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 17977610 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 6771980 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 115315004 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1233982 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 2306 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 29550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 1247451 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 470617 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 460 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 8997640 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 271780 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 147272342 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.530188 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.786973 # Number of instructions fetched each cycle (Total)
380,388c375,383
< system.cpu.fetch.rateDist::0 102162821 87.56% 87.56% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 926771 0.79% 88.35% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 1955000 1.68% 90.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 905545 0.78% 90.80% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2771139 2.37% 93.18% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 614884 0.53% 93.70% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 724459 0.62% 94.32% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1009032 0.86% 95.19% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 5614119 4.81% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 132738967 90.13% 90.13% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 930397 0.63% 90.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 1956016 1.33% 92.09% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 907001 0.62% 92.71% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2772714 1.88% 94.59% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 615474 0.42% 95.01% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 727209 0.49% 95.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1009346 0.69% 96.19% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 5615218 3.81% 100.00% # Number of instructions fetched each cycle (Total)
392,430c387,425
< system.cpu.fetch.rateDist::total 116683770 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.146850 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.638322 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 24065548 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 80700938 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 9436968 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 1906955 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 573360 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 582340 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 42404 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 68029803 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 132508 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 573360 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 24987085 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 50897393 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 20868454 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 10337136 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 9020340 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 65614260 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 203152 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2087104 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 150571 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 4833262 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 43733220 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 79561709 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 79380946 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 168313 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 38180223 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 5552989 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1689330 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 239361 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13544094 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 10376074 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 6949198 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1492318 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1087072 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 58452380 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2137932 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 57496742 # Number of instructions issued
---
> system.cpu.fetch.rateDist::total 147272342 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.116883 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.507660 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 24002291 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 111345789 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 9440793 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 1908530 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 574938 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 581140 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 42414 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 68062016 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 132549 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 574938 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 24926396 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 78168566 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 21593766 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 10339140 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 11669534 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 65637228 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 204564 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 2092706 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 229144 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 7400964 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 43743792 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 79597549 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 79416724 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 168373 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 38181235 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 5562549 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1689699 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 239435 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13568621 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 10378795 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 6951631 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1513940 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1098335 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 58473138 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2139162 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 57493462 # Number of instructions issued
432,437c427,432
< system.cpu.iq.iqSquashedInstsExamined 7609567 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3401604 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1476871 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 116683770 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.492757 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.231576 # Number of insts issued each cycle
---
> system.cpu.iq.iqSquashedInstsExamined 7630612 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3411321 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1477941 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 147272342 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.390389 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.114131 # Number of insts issued each cycle
439,447c434,442
< system.cpu.iq.issued_per_cycle::0 93080109 79.77% 79.77% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 10182698 8.73% 88.50% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 4288903 3.68% 92.17% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 3018996 2.59% 94.76% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 3082938 2.64% 97.40% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 1488362 1.28% 98.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1011835 0.87% 99.55% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 404754 0.35% 99.89% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 125175 0.11% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 123663895 83.97% 83.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 10186331 6.92% 90.89% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 4292878 2.91% 93.80% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 3019293 2.05% 95.85% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 3081041 2.09% 97.94% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 1488323 1.01% 98.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1011420 0.69% 99.64% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 404091 0.27% 99.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 125070 0.08% 100.00% # Number of insts issued each cycle
451c446
< system.cpu.iq.issued_per_cycle::total 116683770 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 147272342 # Number of insts issued each cycle
453,483c448,478
< system.cpu.iq.fu_full::IntAlu 209669 18.63% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 542046 48.17% 66.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 373622 33.20% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 210189 18.68% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 539111 47.92% 66.61% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 375615 33.39% 100.00% # attempts to use FU when none available
487,518c482,513
< system.cpu.iq.FU_type_0::IntAlu 39037181 67.89% 67.91% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 61834 0.11% 68.01% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 38554 0.07% 68.08% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 10676723 18.57% 86.66% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 6722717 11.69% 98.35% # Type of FU issued
< system.cpu.iq.FU_type_0::IprAccess 948811 1.65% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 39049173 67.92% 67.93% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 61879 0.11% 68.04% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 10660314 18.54% 86.65% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 6723536 11.69% 98.35% # Type of FU issued
> system.cpu.iq.FU_type_0::IprAccess 949085 1.65% 100.00% # Type of FU issued
520,532c515,527
< system.cpu.iq.FU_type_0::total 57496742 # Type of FU issued
< system.cpu.iq.rate 0.470318 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1125337 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 232146820 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 67882277 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 55834928 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 712827 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 336508 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 328971 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 58232105 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 382688 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 634703 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 57493462 # Type of FU issued
> system.cpu.iq.rate 0.373800 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1124915 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.019566 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 262728196 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 67925320 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 55850502 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 713041 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 336604 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 329051 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 58228243 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 382848 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 635438 # Number of loads that had data forwarded from stores
534,537c529,532
< system.cpu.iew.lsq.thread0.squashedLoads 1283936 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 3373 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 19308 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 571381 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1285740 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 3115 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 19427 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 573353 # Number of stores squashed
540,541c535,536
< system.cpu.iew.lsq.thread0.rescheduledLoads 18194 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 477327 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 18203 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 457581 # Number of times an access to memory failed due to the cache being blocked
543,559c538,554
< system.cpu.iew.iewSquashCycles 573360 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 47668673 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 853294 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 64278853 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 140556 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 10376074 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 6949198 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1890343 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 43583 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 606693 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 19308 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 178271 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 409117 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 587388 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 56911436 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 10335818 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 585305 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 574938 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 74485816 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1122121 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 64302959 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 140159 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 10378795 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 6951631 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1891041 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 44126 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 874685 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 19427 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 179710 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 409314 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 589024 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 56907888 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 10319427 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 585573 # Number of squashed instructions skipped in execute
561,569c556,564
< system.cpu.iew.exec_nop 3688541 # number of nop insts executed
< system.cpu.iew.exec_refs 17002933 # number of memory reference insts executed
< system.cpu.iew.exec_branches 8971597 # Number of branches executed
< system.cpu.iew.exec_stores 6667115 # Number of stores executed
< system.cpu.iew.exec_rate 0.465530 # Inst execution rate
< system.cpu.iew.wb_sent 56299831 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 56163899 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 28741573 # num instructions producing a value
< system.cpu.iew.wb_consumers 39917507 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 3690659 # number of nop insts executed
> system.cpu.iew.exec_refs 16987198 # number of memory reference insts executed
> system.cpu.iew.exec_branches 8973802 # Number of branches executed
> system.cpu.iew.exec_stores 6667771 # Number of stores executed
> system.cpu.iew.exec_rate 0.369993 # Inst execution rate
> system.cpu.iew.wb_sent 56315493 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 56179553 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 28757989 # num instructions producing a value
> system.cpu.iew.wb_consumers 39945326 # num instructions consuming a value
571,572c566,567
< system.cpu.iew.wb_rate 0.459416 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.720024 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.365258 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.719934 # average fanout of values written-back
574,579c569,574
< system.cpu.commit.commitSquashedInsts 7990103 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 661061 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 538190 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 115283305 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.487246 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.430050 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 8014233 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 661221 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 539644 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 145865842 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.385097 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.287358 # Number of insts commited each cycle
581,589c576,584
< system.cpu.commit.committed_per_cycle::0 95489644 82.83% 82.83% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 7861367 6.82% 89.65% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 4279666 3.71% 93.36% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2238986 1.94% 95.30% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1753667 1.52% 96.83% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 610357 0.53% 97.35% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 475106 0.41% 97.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 479497 0.42% 98.18% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 2095015 1.82% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 126089885 86.44% 86.44% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 7851403 5.38% 91.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 4272179 2.93% 94.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2235192 1.53% 96.29% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1747101 1.20% 97.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 615790 0.42% 97.91% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 475839 0.33% 98.23% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 478833 0.33% 98.56% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 2099620 1.44% 100.00% # Number of insts commited each cycle
593,595c588,590
< system.cpu.commit.committed_per_cycle::total 115283305 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 56171345 # Number of instructions committed
< system.cpu.commit.committedOps 56171345 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 145865842 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 56172516 # Number of instructions committed
> system.cpu.commit.committedOps 56172516 # Number of ops (including micro ops) committed
597,600c592,595
< system.cpu.commit.refs 15469955 # Number of memory references committed
< system.cpu.commit.loads 9092138 # Number of loads committed
< system.cpu.commit.membars 226307 # Number of memory barriers committed
< system.cpu.commit.branches 8441356 # Number of branches committed
---
> system.cpu.commit.refs 15471333 # Number of memory references committed
> system.cpu.commit.loads 9093055 # Number of loads committed
> system.cpu.commit.membars 226352 # Number of memory barriers committed
> system.cpu.commit.branches 8440752 # Number of branches committed
602,606c597,601
< system.cpu.commit.int_insts 52021098 # Number of committed integer instructions.
< system.cpu.commit.function_calls 740502 # Number of function calls committed.
< system.cpu.commit.op_class_0::No_OpClass 3197878 5.69% 5.69% # Class of committed instruction
< system.cpu.commit.op_class_0::IntAlu 36220066 64.48% 70.17% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 60657 0.11% 70.28% # Class of committed instruction
---
> system.cpu.commit.int_insts 52021823 # Number of committed integer instructions.
> system.cpu.commit.function_calls 740586 # Number of function calls committed.
> system.cpu.commit.op_class_0::No_OpClass 3198106 5.69% 5.69% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 36219281 64.48% 70.17% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 60683 0.11% 70.28% # Class of committed instruction
612,636c607,631
< system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction
< system.cpu.commit.op_class_0::MemRead 9318445 16.59% 86.95% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 6383767 11.36% 98.31% # Class of committed instruction
< system.cpu.commit.op_class_0::IprAccess 948811 1.69% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 9319407 16.59% 86.95% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 6384233 11.37% 98.31% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 949085 1.69% 100.00% # Class of committed instruction
638,665c633,660
< system.cpu.commit.op_class_0::total 56171345 # Class of committed instruction
< system.cpu.commit.bw_lim_events 2095015 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 177100105 # The number of ROB reads
< system.cpu.rob.rob_writes 129718981 # The number of ROB writes
< system.cpu.timesIdled 575678 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 5566955 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 3599729822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 52980740 # Number of Instructions Simulated
< system.cpu.committedOps 52980740 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 2.307456 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.307456 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.433378 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.433378 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 74560962 # number of integer regfile reads
< system.cpu.int_regfile_writes 40515010 # number of integer regfile writes
< system.cpu.fp_regfile_reads 167029 # number of floating regfile reads
< system.cpu.fp_regfile_writes 167528 # number of floating regfile writes
< system.cpu.misc_regfile_reads 2030483 # number of misc regfile reads
< system.cpu.misc_regfile_writes 939256 # number of misc regfile writes
< system.cpu.dcache.tags.replacements 1402429 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.994497 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 11825966 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1402941 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 8.429411 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 26175500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.994497 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
---
> system.cpu.commit.op_class_0::total 56172516 # Class of committed instruction
> system.cpu.commit.bw_lim_events 2099620 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 207703277 # The number of ROB reads
> system.cpu.rob.rob_writes 129775597 # The number of ROB writes
> system.cpu.timesIdled 576321 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 6535603 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 3597682440 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 52981683 # Number of Instructions Simulated
> system.cpu.committedOps 52981683 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 2.903040 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.903040 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.344466 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.344466 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 74566924 # number of integer regfile reads
> system.cpu.int_regfile_writes 40527176 # number of integer regfile writes
> system.cpu.fp_regfile_reads 167101 # number of floating regfile reads
> system.cpu.fp_regfile_writes 167535 # number of floating regfile writes
> system.cpu.misc_regfile_reads 1985778 # number of misc regfile reads
> system.cpu.misc_regfile_writes 939467 # number of misc regfile writes
> system.cpu.dcache.tags.replacements 1402095 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.992786 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 11832212 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1402607 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 8.435871 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.992786 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy
667,669c662,664
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
671,750c666,745
< system.cpu.dcache.tags.tag_accesses 63836458 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63836458 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 7233922 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7233922 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4189857 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4189857 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 186093 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 186093 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 215697 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 215697 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 11423779 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 11423779 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 11423779 # number of overall hits
< system.cpu.dcache.overall_hits::total 11423779 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1801919 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1801919 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1957536 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1957536 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 23327 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 23327 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 3759455 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3759455 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3759455 # number of overall misses
< system.cpu.dcache.overall_misses::total 3759455 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 41733061500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 41733061500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 80455809465 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 80455809465 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376093000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 376093000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 485000 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 485000 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 122188870965 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 122188870965 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 122188870965 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 122188870965 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9035841 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9035841 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6147393 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6147393 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209420 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 209420 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 215725 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 215725 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15183234 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15183234 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15183234 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15183234 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199419 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.199419 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318434 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.318434 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111389 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111389 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.247606 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.247606 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.247606 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.247606 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23160.342668 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 23160.342668 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41100.551645 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 41100.551645 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16122.647576 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16122.647576 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17321.428571 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 17321.428571 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 32501.751175 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 32501.751175 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 32501.751175 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 32501.751175 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 4515997 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 2303 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 134454 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 26 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.587673 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 88.576923 # average number of cycles each access was blocked
---
> system.cpu.dcache.tags.tag_accesses 63847952 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63847952 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 7239475 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7239475 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4190405 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4190405 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 186164 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 186164 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 215734 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 215734 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 11429880 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 11429880 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 11429880 # number of overall hits
> system.cpu.dcache.overall_hits::total 11429880 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1798792 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1798792 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1957410 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1957410 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 23330 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 23330 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 3756202 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3756202 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3756202 # number of overall misses
> system.cpu.dcache.overall_misses::total 3756202 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 57198715500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 57198715500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 116967363039 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 116967363039 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 446591500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 446591500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 850000 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 850000 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 174166078539 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 174166078539 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 174166078539 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 174166078539 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9038267 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9038267 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6147815 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6147815 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209494 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 209494 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 215760 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 215760 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15186082 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15186082 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15186082 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15186082 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199020 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.199020 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318391 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.318391 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111364 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111364 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.247345 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.247345 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.247345 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.247345 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31798.404429 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 31798.404429 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59756.189577 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 59756.189577 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19142.370339 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19142.370339 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 32692.307692 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 32692.307692 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 46367.601779 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 46367.601779 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 7156530 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 5457 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 133923 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437647 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 188.172414 # average number of cycles each access was blocked
753,776c748,771
< system.cpu.dcache.writebacks::writebacks 841625 # number of writebacks
< system.cpu.dcache.writebacks::total 841625 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 707636 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 707636 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666818 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1666818 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5179 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 5179 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2374454 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2374454 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2374454 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2374454 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1094283 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1094283 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290718 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 290718 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18148 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 18148 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1385001 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1385001 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1385001 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1385001 # number of overall MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 841276 # number of writebacks
> system.cpu.dcache.writebacks::total 841276 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 704782 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 704782 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666649 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1666649 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5284 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 5284 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2371431 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2371431 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2371431 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2371431 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1094010 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1094010 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290761 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 290761 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18046 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 18046 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1384771 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1384771 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1384771 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1384771 # number of overall MSHR misses
779,830c774,825
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30550296500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 30550296500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12634151241 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12634151241 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226327000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226327000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 457000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 457000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43184447741 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 43184447741 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43184447741 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 43184447741 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450758000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450758000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035709998 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035709998 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486467998 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486467998 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121105 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121105 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047291 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047291 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086658 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086658 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091219 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091219 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27918.094771 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27918.094771 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43458.441655 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43458.441655 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12471.181397 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12471.181397 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16321.428571 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16321.428571 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31180.084160 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 31180.084160 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209344.588745 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209344.588745 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212141.517090 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212141.517090 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210968.655331 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210968.655331 # average overall mshr uncacheable latency
---
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44554526500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 44554526500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18468782348 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 18468782348 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 228783500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 228783500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 824000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 824000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63023308848 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 63023308848 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63023308848 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 63023308848 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450570000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450570000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2036143500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2036143500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486713500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486713500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121042 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121042 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047295 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047295 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086141 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086141 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091187 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091187 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40725.885961 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40725.885961 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63518.774347 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63518.774347 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12677.795633 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12677.795633 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 31692.307692 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 31692.307692 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209317.460317 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209317.460317 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.477599 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.477599 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210957.980397 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210957.980397 # average overall mshr uncacheable latency
832,840c827,835
< system.cpu.icache.tags.replacements 1038549 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.170339 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 7895321 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1039057 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 7.598545 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 28146856500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.170339 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 1038950 # number of replacements
> system.cpu.icache.tags.tagsinuse 507.834309 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 7904301 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1039458 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 7.604252 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 42289841500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 507.834309 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.991864 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.991864 # Average percentage of cache occupancy
842,844c837,839
< system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id
846,884c841,879
< system.cpu.icache.tags.tag_accesses 10027494 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 10027494 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 7895322 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 7895322 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 7895322 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 7895322 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 7895322 # number of overall hits
< system.cpu.icache.overall_hits::total 7895322 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1092746 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1092746 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1092746 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1092746 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1092746 # number of overall misses
< system.cpu.icache.overall_misses::total 1092746 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15273300993 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15273300993 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15273300993 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15273300993 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15273300993 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15273300993 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 8988068 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 8988068 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 8988068 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 8988068 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 8988068 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 8988068 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121577 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.121577 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.121577 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.121577 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.121577 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.121577 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.990987 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13976.990987 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13976.990987 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13976.990987 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 6859 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 10037466 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 10037466 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 7904302 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 7904302 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 7904302 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 7904302 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 7904302 # number of overall hits
> system.cpu.icache.overall_hits::total 7904302 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1093336 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1093336 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1093336 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1093336 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1093336 # number of overall misses
> system.cpu.icache.overall_misses::total 1093336 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 16294267486 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 16294267486 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 16294267486 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 16294267486 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 16294267486 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 16294267486 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 8997638 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 8997638 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 8997638 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 8997638 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 8997638 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 8997638 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.121514 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.121514 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.121514 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.121514 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.257083 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14903.257083 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.257083 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14903.257083 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.257083 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14903.257083 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 10533 # number of cycles access was blocked
886c881
< system.cpu.icache.blocked::no_mshrs 220 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 301 # number of cycles access was blocked
888c883
< system.cpu.icache.avg_blocked_cycles::no_mshrs 31.177273 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 34.993355 # average number of cycles each access was blocked
892,921c887,916
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53320 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 53320 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 53320 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 53320 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 53320 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 53320 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039426 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1039426 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1039426 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1039426 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1039426 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1039426 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13594657497 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 13594657497 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13594657497 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 13594657497 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13594657497 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 13594657497 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115645 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.115645 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115645 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.115645 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13079.004659 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13079.004659 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13079.004659 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13079.004659 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13079.004659 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13079.004659 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53508 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 53508 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 53508 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 53508 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 53508 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 53508 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039828 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1039828 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1039828 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1039828 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1039828 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1039828 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14359854493 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14359854493 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14359854493 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14359854493 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14359854493 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14359854493 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115567 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.115567 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.115567 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13809.836332 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13809.836332 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency
923,962c918,957
< system.cpu.l2cache.tags.replacements 338316 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65333.743960 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4173914 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 403482 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 10.344734 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 5938026000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 53662.904675 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5355.130521 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 6315.708764 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.818831 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081713 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.096370 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996914 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 494 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3498 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2393 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55462 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 39757135 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 39757135 # Number of data accesses
< system.cpu.l2cache.Writeback_hits::writebacks 841625 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 841625 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 29 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 29 # number of UpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 185982 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 185982 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1024048 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1024048 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827700 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 827700 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 1024048 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1013682 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2037730 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 1024048 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1013682 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2037730 # number of overall hits
---
> system.cpu.l2cache.tags.replacements 338309 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65280.236813 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4173910 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 403476 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 10.344878 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 9183094000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 53277.296150 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.937838 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 6694.002825 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.812947 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081008 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.102142 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996097 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3483 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3330 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2415 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55446 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 39757210 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 39757210 # Number of data accesses
> system.cpu.l2cache.Writeback_hits::writebacks 841276 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 841276 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 30 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 30 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 19 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 186016 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 186016 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1024478 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1024478 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 827309 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 827309 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 1024478 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1013325 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2037803 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 1024478 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1013325 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2037803 # number of overall hits
965,1044c960,1039
< system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 115503 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 115503 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15066 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 15066 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273839 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 273839 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 15066 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 389342 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 404408 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 15066 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 389342 # number of overall misses
< system.cpu.l2cache.overall_misses::total 404408 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 454500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 454500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 61000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 61000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10302938500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 10302938500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1259119000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1259119000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19992285500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 19992285500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1259119000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 30295224000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31554343000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1259119000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 30295224000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31554343000 # number of overall miss cycles
< system.cpu.l2cache.Writeback_accesses::writebacks 841625 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 841625 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 127 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 127 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 301485 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 301485 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1039114 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1039114 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1101539 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1101539 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1039114 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1403024 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2442138 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1039114 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1403024 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2442138 # number of overall (read+write) accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.771654 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.771654 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383114 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383114 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014499 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014499 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248597 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248597 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014499 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.277502 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.165596 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014499 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.277502 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.165596 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4637.755102 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4637.755102 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 10166.666667 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 10166.666667 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89200.613837 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89200.613837 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83573.543077 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83573.543077 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73007.444155 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73007.444155 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83573.543077 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77811.343241 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78026.010860 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83573.543077 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77811.343241 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78026.010860 # average overall miss latency
---
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 7 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 115511 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 115511 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15035 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 15035 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273855 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 273855 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 15035 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 389366 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 404401 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 15035 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 389366 # number of overall misses
> system.cpu.l2cache.overall_misses::total 404401 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 804000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 804000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 243500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 243500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16132911000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 16132911000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2019085000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2019085000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34002540500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 34002540500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2019085000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 50135451500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 52154536500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2019085000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 50135451500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 52154536500 # number of overall miss cycles
> system.cpu.l2cache.Writeback_accesses::writebacks 841276 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 841276 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 128 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 128 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 26 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 26 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 301527 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 301527 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1039513 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1039513 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1101164 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1101164 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1039513 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1402691 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2442204 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1039513 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1402691 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2442204 # number of overall (read+write) accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.765625 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.765625 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.269231 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.269231 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383087 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383087 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014464 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014464 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248696 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248696 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014464 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.277585 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.165589 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014464 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.277585 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.165589 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8204.081633 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8204.081633 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 34785.714286 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 34785.714286 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139665.581633 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139665.581633 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134292.317925 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134292.317925 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124162.569608 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124162.569608 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134292.317925 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128761.760143 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 128967.377677 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134292.317925 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128761.760143 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 128967.377677 # average overall miss latency
1053,1054c1048,1049
< system.cpu.l2cache.writebacks::writebacks 76042 # number of writebacks
< system.cpu.l2cache.writebacks::total 76042 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 76045 # number of writebacks
> system.cpu.l2cache.writebacks::total 76045 # number of writebacks
1061,1062c1056,1057
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 305 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 305 # number of CleanEvict MSHR misses
---
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 304 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 304 # number of CleanEvict MSHR misses
1065,1078c1060,1073
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115503 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 115503 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15065 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15065 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273839 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273839 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 15065 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 389342 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 404407 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 15065 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 389342 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 404407 # number of overall MSHR misses
---
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 7 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115511 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 115511 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15034 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15034 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273855 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273855 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 15034 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 389366 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 404400 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 15034 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 389366 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 404400 # number of overall MSHR misses
1081,1106c1076,1101
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2195000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2195000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 124000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 124000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9147908500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9147908500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1108373500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1108373500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17263967500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17263967500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1108373500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26411876000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 27520249500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1108373500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26411876000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 27520249500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364133000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364133000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925339500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925339500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289472500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289472500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 7022000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 7022000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 499500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 499500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14977801000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14977801000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1868614000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1868614000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31274184500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31274184500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1868614000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46251985500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 48120599500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1868614000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46251985500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 48120599500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363945000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363945000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925742500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925742500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289687500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289687500 # number of overall MSHR uncacheable cycles
1109,1146c1104,1141
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.771654 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.771654 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383114 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383114 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014498 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248597 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248597 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.165595 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.165595 # mshr miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22397.959184 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22397.959184 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20666.666667 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20666.666667 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79200.613837 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79200.613837 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73572.751411 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73572.751411 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63044.224891 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63044.224891 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196844.588745 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196844.588745 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.797832 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.797832 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199048.317802 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199048.317802 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.765625 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.765625 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.269231 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.269231 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383087 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383087 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014463 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248696 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248696 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.165588 # mshr miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71653.061224 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71653.061224 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71357.142857 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71357.142857 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129665.581633 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129665.581633 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124292.536916 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124292.536916 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114199.793686 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114199.793686 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196817.460317 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196817.460317 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.977079 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.977079 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199037.239835 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199037.239835 # average overall mshr uncacheable latency
1147a1143,1148
> system.cpu.toL2Bus.snoop_filter.tot_requests 4883718 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2441508 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1149,1161c1150,1162
< system.cpu.toL2Bus.trans_dist::ReadResp 2147969 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9596 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9596 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 959201 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 1860011 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 127 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 155 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 301485 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 301485 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039426 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101712 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::BadAddressError 82 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2147995 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 958852 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 1860290 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 128 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 154 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 301527 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 301527 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039828 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101337 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution
1163,1172c1164,1173
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3116681 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240614 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7357295 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66503296 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143706404 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 210209700 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 422216 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 5321857 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.079248 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.270126 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3117755 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4239617 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7357372 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66528832 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143662708 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 210191540 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 422209 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 5321984 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.032932 # Request fanout histogram
1174,1176c1175,1177
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 4900109 92.08% 92.08% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 421748 7.92% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 5316206 99.89% 99.89% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 5778 0.11% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1178,1181c1179,1182
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 5321857 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3296477500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 5321984 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3296198000 # Layer occupancy (ticks)
1183c1184
< system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks)
1185c1186
< system.cpu.toL2Bus.respLayer0.occupancy 1560615042 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1561216545 # Layer occupancy (ticks)
1187c1188
< system.cpu.toL2Bus.respLayer1.occupancy 2116394230 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2115809899 # Layer occupancy (ticks)
1203,1205c1204,1206
< system.iobus.trans_dist::WriteReq 51148 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51148 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5048 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 51150 # Transaction distribution
> system.iobus.trans_dist::WriteResp 51150 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
1217c1218
< system.iobus.pkt_count_system.bridge.master::total 33052 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
1220,1221c1221,1222
< system.iobus.pkt_count::total 116502 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20192 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
1233c1234
< system.iobus.pkt_size_system.bridge.master::total 44132 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
1236,1237c1237,1238
< system.iobus.pkt_size::total 2705740 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 4659000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
1259c1260
< system.iobus.reqLayer29.occupancy 216075504 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 215079498 # Layer occupancy (ticks)
1263c1264
< system.iobus.respLayer0.occupancy 23456000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks)
1268c1269
< system.iocache.tags.tagsinuse 1.259061 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.249403 # Cycle average of tags in use
1272,1275c1273,1276
< system.iocache.tags.warmup_cycle 1711310965000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.259061 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.078691 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.078691 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1725991887000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.249403 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.078088 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.078088 # Average percentage of cache occupancy
1289,1296c1290,1297
< system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908771621 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4908771621 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21903883 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21903883 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427983615 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 5427983615 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 21903883 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 21903883 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 21903883 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 21903883 # number of overall miss cycles
1313,1321c1314,1322
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118135.628153 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118135.628153 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126612.040462 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 126612.040462 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.103557 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 130631.103557 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126612.040462 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126612.040462 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1323c1324
< system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1325c1326
< system.iocache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1339,1346c1340,1347
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831171621 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2831171621 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13253883 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 13253883 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350383615 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 3350383615 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 13253883 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 13253883 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 13253883 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 13253883 # number of overall MSHR miss cycles
1355,1362c1356,1363
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68135.628153 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68135.628153 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 76612.040462 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.103557 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.103557 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency
1365,1371c1366,1372
< system.membus.trans_dist::ReadResp 295925 # Transaction distribution
< system.membus.trans_dist::WriteReq 9596 # Transaction distribution
< system.membus.trans_dist::WriteResp 9596 # Transaction distribution
< system.membus.trans_dist::Writeback 117554 # Transaction distribution
< system.membus.trans_dist::CleanEvict 261799 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 335 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 295909 # Transaction distribution
> system.membus.trans_dist::WriteReq 9598 # Transaction distribution
> system.membus.trans_dist::WriteResp 9598 # Transaction distribution
> system.membus.trans_dist::Writeback 117557 # Transaction distribution
> system.membus.trans_dist::CleanEvict 261789 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 334 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution
1373,1376c1374,1377
< system.membus.trans_dist::ReadExReq 115266 # Transaction distribution
< system.membus.trans_dist::ReadExResp 115266 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 289077 # Transaction distribution
< system.membus.trans_dist::BadAddressError 82 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 115275 # Transaction distribution
> system.membus.trans_dist::ReadExResp 115275 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 289062 # Transaction distribution
> system.membus.trans_dist::BadAddressError 83 # Transaction distribution
1379,1382c1380,1383
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33052 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146409 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 164 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179625 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146388 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179610 # Packet count per connected master and slave (bytes)
1385,1388c1386,1389
< system.membus.pkt_count::total 1304442 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44132 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710784 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754916 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1304427 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710528 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754676 # Cumulative packet size per connected master and slave (bytes)
1391c1392
< system.membus.pkt_size::total 33412644 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 33412404 # Cumulative packet size per connected master and slave (bytes)
1393c1394
< system.membus.snoop_fanout::samples 842297 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 842283 # Request fanout histogram
1398c1399
< system.membus.snoop_fanout::1 842297 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 842283 100.00% 100.00% # Request fanout histogram
1403,1404c1404,1405
< system.membus.snoop_fanout::total 842297 # Request fanout histogram
< system.membus.reqLayer0.occupancy 28891000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 842283 # Request fanout histogram
> system.membus.reqLayer0.occupancy 28662500 # Layer occupancy (ticks)
1406c1407
< system.membus.reqLayer1.occupancy 1313747676 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1313672631 # Layer occupancy (ticks)
1408c1409
< system.membus.reqLayer2.occupancy 109000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 106500 # Layer occupancy (ticks)
1410c1411
< system.membus.respLayer1.occupancy 2139659662 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2139416664 # Layer occupancy (ticks)
1412c1413
< system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 69895667 # Layer occupancy (ticks)
1446,1448c1447,1449
< system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 210955 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74645 40.97% 40.97% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74668 40.97% 40.97% # number of times we switched to this ipl
1450,1453c1451,1454
< system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 105533 57.93% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182187 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73278 49.32% 49.32% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182251 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73301 49.32% 49.32% # number of times we switched to this ipl from a different ipl
1455,1463c1456,1464
< system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73278 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148565 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1817526707500 97.66% 97.66% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 62603000 0.00% 97.67% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 536431500 0.03% 97.70% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 42863705000 2.30% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1860989447000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981687 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73301 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148613 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1818203066500 96.93% 96.93% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 62700500 0.00% 96.94% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 538036000 0.03% 96.96% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 56940563000 3.04% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1875744366000 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl
1466,1467c1467,1468
< system.cpu.kern.ipl_used::31 0.694361 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.815453 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.815430 # fraction of swpipl calls that actually changed the ipl
1506,1507c1507,1508
< system.cpu.kern.callpal::swpipl 175074 91.22% 93.43% # number of callpals executed
< system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175134 91.23% 93.43% # number of callpals executed
> system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
1512c1513
< system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
1515,1516c1516,1517
< system.cpu.kern.callpal::total 191916 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches
---
> system.cpu.kern.callpal::total 191979 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches
1522c1523
< system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.326325 # fraction of useful protection mode switches
1525,1528c1526,1529
< system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 29189899500 1.57% 1.57% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 2667621500 0.14% 1.71% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1829131918000 98.29% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 29901576500 1.59% 1.59% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 2896080000 0.15% 1.75% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1842946701500 98.25% 100.00% # number of ticks spent at the given mode